1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/CodeGen/SSARegMap.h"
21 #include "llvm/Constants.h"
22 #include "llvm/Function.h"
25 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
26 : TargetLowering(TM) {
28 // Fold away setcc operations if possible.
29 setSetCCIsExpensive();
32 // Use _setjmp/_longjmp instead of setjmp/longjmp.
33 setUseUnderscoreSetJmpLongJmp(true);
35 // Set up the register classes.
36 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
37 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
38 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
40 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
41 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
43 // PowerPC has no intrinsics for these particular operations
44 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
45 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
46 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
48 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
49 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
50 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
52 // PowerPC has no SREM/UREM instructions
53 setOperationAction(ISD::SREM, MVT::i32, Expand);
54 setOperationAction(ISD::UREM, MVT::i32, Expand);
56 // We don't support sin/cos/sqrt/fmod
57 setOperationAction(ISD::FSIN , MVT::f64, Expand);
58 setOperationAction(ISD::FCOS , MVT::f64, Expand);
59 setOperationAction(ISD::FREM , MVT::f64, Expand);
60 setOperationAction(ISD::FSIN , MVT::f32, Expand);
61 setOperationAction(ISD::FCOS , MVT::f32, Expand);
62 setOperationAction(ISD::FREM , MVT::f32, Expand);
64 // If we're enabling GP optimizations, use hardware square root
65 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
66 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
67 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
70 // PowerPC does not have BSWAP, CTPOP or CTTZ
71 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
72 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
73 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
75 // PowerPC does not have ROTR
76 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
78 // PowerPC does not have Select
79 setOperationAction(ISD::SELECT, MVT::i32, Expand);
80 setOperationAction(ISD::SELECT, MVT::f32, Expand);
81 setOperationAction(ISD::SELECT, MVT::f64, Expand);
83 // PowerPC wants to turn select_cc of FP into fsel when possible.
84 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
85 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
87 // PowerPC does not have BRCOND* which requires SetCC
88 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
89 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
91 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
92 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
94 // PowerPC does not have [U|S]INT_TO_FP
95 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
96 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
98 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
99 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
101 // PowerPC does not have truncstore for i1.
102 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
104 // Support label based line numbers.
105 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
106 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
107 // FIXME - use subtarget debug flags
108 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
109 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
111 // We want to legalize GlobalAddress and ConstantPool nodes into the
112 // appropriate instructions to materialize the address.
113 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
114 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
116 // RET must be custom lowered, to meet ABI requirements
117 setOperationAction(ISD::RET , MVT::Other, Custom);
119 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
120 setOperationAction(ISD::VASTART , MVT::Other, Custom);
122 // Use the default implementation.
123 setOperationAction(ISD::VAARG , MVT::Other, Expand);
124 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
125 setOperationAction(ISD::VAEND , MVT::Other, Expand);
126 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
127 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
128 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
130 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
131 // They also have instructions for converting between i64 and fp.
132 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
133 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
134 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
135 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
137 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
138 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
141 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
142 // 64 bit PowerPC implementations can support i64 types directly
143 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
144 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
145 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
147 // 32 bit PowerPC wants to expand i64 shifts itself.
148 setOperationAction(ISD::SHL, MVT::i64, Custom);
149 setOperationAction(ISD::SRL, MVT::i64, Custom);
150 setOperationAction(ISD::SRA, MVT::i64, Custom);
153 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
154 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
155 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
157 // FIXME: We don't support any ConstantVec's yet. We should custom expand
159 //setOperationAction(ISD::ConstantVec, MVT::v4f32, Expand);
160 //setOperationAction(ISD::ConstantVec, MVT::v4i32, Expand);
163 setSetCCResultContents(ZeroOrOneSetCCResult);
164 setStackPointerRegisterToSaveRestore(PPC::R1);
166 computeRegisterProperties();
169 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
172 case PPCISD::FSEL: return "PPCISD::FSEL";
173 case PPCISD::FCFID: return "PPCISD::FCFID";
174 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
175 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
176 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
177 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
178 case PPCISD::Hi: return "PPCISD::Hi";
179 case PPCISD::Lo: return "PPCISD::Lo";
180 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
181 case PPCISD::SRL: return "PPCISD::SRL";
182 case PPCISD::SRA: return "PPCISD::SRA";
183 case PPCISD::SHL: return "PPCISD::SHL";
184 case PPCISD::CALL: return "PPCISD::CALL";
185 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
189 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
190 static bool isFloatingPointZero(SDOperand Op) {
191 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
192 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
193 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
194 // Maybe this has already been legalized into the constant pool?
195 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
196 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
197 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
202 /// LowerOperation - Provide custom lowering hooks for some operations.
204 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
205 switch (Op.getOpcode()) {
206 default: assert(0 && "Wasn't expecting to be able to lower this!");
207 case ISD::FP_TO_SINT: {
208 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
209 SDOperand Src = Op.getOperand(0);
210 if (Src.getValueType() == MVT::f32)
211 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
214 switch (Op.getValueType()) {
215 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
217 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
220 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
224 // Convert the FP value to an int value through memory.
225 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
226 if (Op.getValueType() == MVT::i32)
227 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
230 case ISD::SINT_TO_FP: {
231 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
232 "Unhandled SINT_TO_FP type in custom expander!");
233 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
234 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
235 if (MVT::f32 == Op.getValueType())
236 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
239 case ISD::SELECT_CC: {
240 // Turn FP only select_cc's into fsel instructions.
241 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
242 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
245 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
247 // Cannot handle SETEQ/SETNE.
248 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
250 MVT::ValueType ResVT = Op.getValueType();
251 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
252 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
253 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
255 // If the RHS of the comparison is a 0.0, we don't need to do the
256 // subtraction at all.
257 if (isFloatingPointZero(RHS))
259 default: break; // SETUO etc aren't handled by fsel.
262 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
265 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
266 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
267 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
270 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
273 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
274 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
275 return DAG.getNode(PPCISD::FSEL, ResVT,
276 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
281 default: break; // SETUO etc aren't handled by fsel.
284 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
285 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
286 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
287 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
290 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
291 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
292 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
293 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
296 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
297 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
298 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
299 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
302 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
303 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
304 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
305 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
310 assert(Op.getValueType() == MVT::i64 &&
311 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
312 // The generic code does a fine job expanding shift by a constant.
313 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
315 // Otherwise, expand into a bunch of logical ops. Note that these ops
316 // depend on the PPC behavior for oversized shift amounts.
317 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
318 DAG.getConstant(0, MVT::i32));
319 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
320 DAG.getConstant(1, MVT::i32));
321 SDOperand Amt = Op.getOperand(1);
323 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
324 DAG.getConstant(32, MVT::i32), Amt);
325 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
326 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
327 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
328 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
329 DAG.getConstant(-32U, MVT::i32));
330 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
331 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
332 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
333 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
336 assert(Op.getValueType() == MVT::i64 &&
337 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
338 // The generic code does a fine job expanding shift by a constant.
339 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
341 // Otherwise, expand into a bunch of logical ops. Note that these ops
342 // depend on the PPC behavior for oversized shift amounts.
343 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
344 DAG.getConstant(0, MVT::i32));
345 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
346 DAG.getConstant(1, MVT::i32));
347 SDOperand Amt = Op.getOperand(1);
349 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
350 DAG.getConstant(32, MVT::i32), Amt);
351 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
352 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
353 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
354 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
355 DAG.getConstant(-32U, MVT::i32));
356 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
357 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
358 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
359 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
362 assert(Op.getValueType() == MVT::i64 &&
363 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
364 // The generic code does a fine job expanding shift by a constant.
365 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
367 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
368 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
369 DAG.getConstant(0, MVT::i32));
370 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
371 DAG.getConstant(1, MVT::i32));
372 SDOperand Amt = Op.getOperand(1);
374 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
375 DAG.getConstant(32, MVT::i32), Amt);
376 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
377 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
378 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
379 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
380 DAG.getConstant(-32U, MVT::i32));
381 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
382 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
383 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
384 Tmp4, Tmp6, ISD::SETLE);
385 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
387 case ISD::ConstantPool: {
388 Constant *C = cast<ConstantPoolSDNode>(Op)->get();
389 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32);
390 SDOperand Zero = DAG.getConstant(0, MVT::i32);
392 if (PPCGenerateStaticCode) {
393 // Generate non-pic code that has direct accesses to the constant pool.
394 // The address of the global is just (hi(&g)+lo(&g)).
395 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
396 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
397 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
400 // Only lower ConstantPool on Darwin.
401 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
402 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
404 // With PIC, the first instruction is actually "GR+hi(&G)".
405 Hi = DAG.getNode(ISD::ADD, MVT::i32,
406 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
409 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
410 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
413 case ISD::GlobalAddress: {
414 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
415 GlobalValue *GV = GSDN->getGlobal();
416 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
417 SDOperand Zero = DAG.getConstant(0, MVT::i32);
419 if (PPCGenerateStaticCode) {
420 // Generate non-pic code that has direct accesses to globals.
421 // The address of the global is just (hi(&g)+lo(&g)).
422 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
423 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
424 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
427 // Only lower GlobalAddress on Darwin.
428 if (!getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin()) break;
430 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
432 // With PIC, the first instruction is actually "GR+hi(&G)".
433 Hi = DAG.getNode(ISD::ADD, MVT::i32,
434 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
437 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
438 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
440 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() && !GV->isExternal())
443 // If the global is weak or external, we have to go through the lazy
445 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
448 // vastart just stores the address of the VarArgsFrameIndex slot into the
449 // memory location argument.
450 // FIXME: Replace MVT::i32 with PointerTy
451 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
452 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
453 Op.getOperand(1), Op.getOperand(2));
458 switch(Op.getNumOperands()) {
460 assert(0 && "Do not know how to return this many arguments!");
463 return SDOperand(); // ret void is legal
465 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
466 unsigned ArgReg = MVT::isInteger(ArgVT) ? PPC::R3 : PPC::F1;
467 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
472 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
474 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
477 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
483 std::vector<SDOperand>
484 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
486 // add beautiful description of PPC stack frame format, or at least some docs
488 MachineFunction &MF = DAG.getMachineFunction();
489 MachineFrameInfo *MFI = MF.getFrameInfo();
490 MachineBasicBlock& BB = MF.front();
491 SSARegMap *RegMap = MF.getSSARegMap();
492 std::vector<SDOperand> ArgValues;
494 unsigned ArgOffset = 24;
495 unsigned GPR_remaining = 8;
496 unsigned FPR_remaining = 13;
497 unsigned GPR_idx = 0, FPR_idx = 0;
498 static const unsigned GPR[] = {
499 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
500 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
502 static const unsigned FPR[] = {
503 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
504 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
507 // Add DAG nodes to load the arguments... On entry to a function on PPC,
508 // the arguments start at offset 24, although they are likely to be passed
510 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
511 SDOperand newroot, argt;
513 bool needsLoad = false;
514 bool ArgLive = !I->use_empty();
515 MVT::ValueType ObjectVT = getValueType(I->getType());
518 default: assert(0 && "Unhandled argument type!");
525 if (GPR_remaining > 0) {
526 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
527 MF.addLiveIn(GPR[GPR_idx], VReg);
528 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
529 if (ObjectVT != MVT::i32) {
530 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
532 argt = DAG.getNode(AssertOp, MVT::i32, argt,
533 DAG.getValueType(ObjectVT));
534 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
543 if (GPR_remaining > 0) {
544 SDOperand argHi, argLo;
545 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
546 MF.addLiveIn(GPR[GPR_idx], VReg);
547 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
548 // If we have two or more remaining argument registers, then both halves
549 // of the i64 can be sourced from there. Otherwise, the lower half will
550 // have to come off the stack. This can happen when an i64 is preceded
551 // by 28 bytes of arguments.
552 if (GPR_remaining > 1) {
553 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
554 MF.addLiveIn(GPR[GPR_idx+1], VReg);
555 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
557 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
558 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
559 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
560 DAG.getSrcValue(NULL));
562 // Build the outgoing arg thingy
563 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
571 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
573 if (FPR_remaining > 0) {
579 if (FPR_remaining > 0) {
581 if (ObjectVT == MVT::f32)
582 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
584 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
585 MF.addLiveIn(FPR[FPR_idx], VReg);
586 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
595 // We need to load the argument to a virtual register if we determined above
596 // that we ran out of physical registers of the appropriate type
598 unsigned SubregOffset = 0;
599 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
600 if (ObjectVT == MVT::i16) SubregOffset = 2;
601 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
602 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
603 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
604 DAG.getConstant(SubregOffset, MVT::i32));
605 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
606 DAG.getSrcValue(NULL));
609 // Every 4 bytes of argument space consumes one of the GPRs available for
611 if (GPR_remaining > 0) {
612 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
613 GPR_remaining -= delta;
616 ArgOffset += ObjSize;
618 DAG.setRoot(newroot.getValue(1));
620 ArgValues.push_back(argt);
623 // If the function takes variable number of arguments, make a frame index for
624 // the start of the first vararg value... for expansion of llvm.va_start.
626 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
627 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
628 // If this function is vararg, store any remaining integer argument regs
629 // to their spots on the stack so that they may be loaded by deferencing the
630 // result of va_next.
631 std::vector<SDOperand> MemOps;
632 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
633 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
634 MF.addLiveIn(GPR[GPR_idx], VReg);
635 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
636 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
637 Val, FIN, DAG.getSrcValue(NULL));
638 MemOps.push_back(Store);
639 // Increment the address by four for the next argument to store
640 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
641 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
643 if (!MemOps.empty()) {
644 MemOps.push_back(DAG.getRoot());
645 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
649 // Finally, inform the code generator which regs we return values in.
650 switch (getValueType(F.getReturnType())) {
651 default: assert(0 && "Unknown type!");
652 case MVT::isVoid: break;
657 MF.addLiveOut(PPC::R3);
660 MF.addLiveOut(PPC::R3);
661 MF.addLiveOut(PPC::R4);
665 MF.addLiveOut(PPC::F1);
672 std::pair<SDOperand, SDOperand>
673 PPCTargetLowering::LowerCallTo(SDOperand Chain,
674 const Type *RetTy, bool isVarArg,
675 unsigned CallingConv, bool isTailCall,
676 SDOperand Callee, ArgListTy &Args,
678 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
679 // SelectExpr to use to put the arguments in the appropriate registers.
680 std::vector<SDOperand> args_to_use;
682 // Count how many bytes are to be pushed on the stack, including the linkage
683 // area, and parameter passing area.
684 unsigned NumBytes = 24;
687 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
688 DAG.getConstant(NumBytes, getPointerTy()));
690 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
691 switch (getValueType(Args[i].second)) {
692 default: assert(0 && "Unknown value type!");
707 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
708 // plus 32 bytes of argument space in case any called code gets funky on us.
709 // (Required by ABI to support var arg)
710 if (NumBytes < 56) NumBytes = 56;
712 // Adjust the stack pointer for the new arguments...
713 // These operations are automatically eliminated by the prolog/epilog pass
714 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
715 DAG.getConstant(NumBytes, getPointerTy()));
717 // Set up a copy of the stack pointer for use loading and storing any
718 // arguments that may not fit in the registers available for argument
720 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
722 // Figure out which arguments are going to go in registers, and which in
723 // memory. Also, if this is a vararg function, floating point operations
724 // must be stored to our stack, and loaded into integer regs as well, if
725 // any integer regs are available for argument passing.
726 unsigned ArgOffset = 24;
727 unsigned GPR_remaining = 8;
728 unsigned FPR_remaining = 13;
730 std::vector<SDOperand> MemOps;
731 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
732 // PtrOff will be used to store the current argument to the stack if a
733 // register cannot be found for it.
734 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
735 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
736 MVT::ValueType ArgVT = getValueType(Args[i].second);
739 default: assert(0 && "Unexpected ValueType for argument!");
743 // Promote the integer to 32 bits. If the input type is signed use a
744 // sign extend, otherwise use a zero extend.
745 if (Args[i].second->isSigned())
746 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
748 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
751 if (GPR_remaining > 0) {
752 args_to_use.push_back(Args[i].first);
755 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
756 Args[i].first, PtrOff,
757 DAG.getSrcValue(NULL)));
762 // If we have one free GPR left, we can place the upper half of the i64
763 // in it, and store the other half to the stack. If we have two or more
764 // free GPRs, then we can pass both halves of the i64 in registers.
765 if (GPR_remaining > 0) {
766 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
767 Args[i].first, DAG.getConstant(1, MVT::i32));
768 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
769 Args[i].first, DAG.getConstant(0, MVT::i32));
770 args_to_use.push_back(Hi);
772 if (GPR_remaining > 0) {
773 args_to_use.push_back(Lo);
776 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
777 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
778 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
779 Lo, PtrOff, DAG.getSrcValue(NULL)));
782 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
783 Args[i].first, PtrOff,
784 DAG.getSrcValue(NULL)));
790 if (FPR_remaining > 0) {
791 args_to_use.push_back(Args[i].first);
794 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
795 Args[i].first, PtrOff,
796 DAG.getSrcValue(NULL));
797 MemOps.push_back(Store);
798 // Float varargs are always shadowed in available integer registers
799 if (GPR_remaining > 0) {
800 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
801 DAG.getSrcValue(NULL));
802 MemOps.push_back(Load.getValue(1));
803 args_to_use.push_back(Load);
806 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
807 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
808 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
809 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
810 DAG.getSrcValue(NULL));
811 MemOps.push_back(Load.getValue(1));
812 args_to_use.push_back(Load);
816 // If we have any FPRs remaining, we may also have GPRs remaining.
817 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
819 if (GPR_remaining > 0) {
820 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
823 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
824 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
829 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
830 Args[i].first, PtrOff,
831 DAG.getSrcValue(NULL)));
833 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
838 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
841 std::vector<MVT::ValueType> RetVals;
842 MVT::ValueType RetTyVT = getValueType(RetTy);
843 MVT::ValueType ActualRetTyVT = RetTyVT;
844 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
845 ActualRetTyVT = MVT::i32; // Promote result to i32.
847 if (RetTyVT == MVT::i64) {
848 RetVals.push_back(MVT::i32);
849 RetVals.push_back(MVT::i32);
850 } else if (RetTyVT != MVT::isVoid) {
851 RetVals.push_back(ActualRetTyVT);
853 RetVals.push_back(MVT::Other);
855 // If the callee is a GlobalAddress node (quite common, every direct call is)
856 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
857 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
858 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
860 std::vector<SDOperand> Ops;
861 Ops.push_back(Chain);
862 Ops.push_back(Callee);
863 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
864 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops);
865 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1);
866 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
867 DAG.getConstant(NumBytes, getPointerTy()));
868 SDOperand RetVal = TheCall;
870 // If the result is a small value, add a note so that we keep track of the
871 // information about whether it is sign or zero extended.
872 if (RetTyVT != ActualRetTyVT) {
873 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
874 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
875 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
876 } else if (RetTyVT == MVT::i64) {
877 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1));
880 return std::make_pair(RetVal, Chain);
884 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
885 MachineBasicBlock *BB) {
886 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
887 MI->getOpcode() == PPC::SELECT_CC_F4 ||
888 MI->getOpcode() == PPC::SELECT_CC_F8) &&
889 "Unexpected instr type to insert");
891 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
892 // control-flow pattern. The incoming instruction knows the destination vreg
893 // to set, the condition code register to branch on, the true/false values to
894 // select between, and a branch opcode to use.
895 const BasicBlock *LLVM_BB = BB->getBasicBlock();
896 ilist<MachineBasicBlock>::iterator It = BB;
904 // fallthrough --> copy0MBB
905 MachineBasicBlock *thisMBB = BB;
906 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
907 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
908 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
909 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
910 MachineFunction *F = BB->getParent();
911 F->getBasicBlockList().insert(It, copy0MBB);
912 F->getBasicBlockList().insert(It, sinkMBB);
913 // Update machine-CFG edges
914 BB->addSuccessor(copy0MBB);
915 BB->addSuccessor(sinkMBB);
919 // # fallthrough to sinkMBB
922 // Update machine-CFG edges
923 BB->addSuccessor(sinkMBB);
926 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
929 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
930 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
931 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
933 delete MI; // The pseudo instruction is gone now.