1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "PPCPerfectShuffle.h"
17 #include "llvm/ADT/VectorExtras.h"
18 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/SSARegMap.h"
24 #include "llvm/Constants.h"
25 #include "llvm/Function.h"
26 #include "llvm/Intrinsics.h"
27 #include "llvm/Support/MathExtras.h"
28 #include "llvm/Target/TargetOptions.h"
31 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
32 : TargetLowering(TM) {
34 // Fold away setcc operations if possible.
35 setSetCCIsExpensive();
38 // Use _setjmp/_longjmp instead of setjmp/longjmp.
39 setUseUnderscoreSetJmpLongJmp(true);
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
43 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
44 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
46 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
47 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
49 // PowerPC has no intrinsics for these particular operations
50 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
51 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
52 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC has no SREM/UREM instructions
59 setOperationAction(ISD::SREM, MVT::i32, Expand);
60 setOperationAction(ISD::UREM, MVT::i32, Expand);
62 // We don't support sin/cos/sqrt/fmod
63 setOperationAction(ISD::FSIN , MVT::f64, Expand);
64 setOperationAction(ISD::FCOS , MVT::f64, Expand);
65 setOperationAction(ISD::FREM , MVT::f64, Expand);
66 setOperationAction(ISD::FSIN , MVT::f32, Expand);
67 setOperationAction(ISD::FCOS , MVT::f32, Expand);
68 setOperationAction(ISD::FREM , MVT::f32, Expand);
70 // If we're enabling GP optimizations, use hardware square root
71 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
72 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
73 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
76 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
77 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
79 // PowerPC does not have BSWAP, CTPOP or CTTZ
80 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
81 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
82 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
84 // PowerPC does not have ROTR
85 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
87 // PowerPC does not have Select
88 setOperationAction(ISD::SELECT, MVT::i32, Expand);
89 setOperationAction(ISD::SELECT, MVT::f32, Expand);
90 setOperationAction(ISD::SELECT, MVT::f64, Expand);
92 // PowerPC wants to turn select_cc of FP into fsel when possible.
93 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
94 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
96 // PowerPC wants to optimize integer setcc a bit
97 setOperationAction(ISD::SETCC, MVT::i32, Custom);
99 // PowerPC does not have BRCOND which requires SetCC
100 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
102 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
103 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
105 // PowerPC does not have [U|S]INT_TO_FP
106 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
109 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
110 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
112 // PowerPC does not have truncstore for i1.
113 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
115 // Support label based line numbers.
116 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
117 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
118 // FIXME - use subtarget debug flags
119 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
120 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
122 // We want to legalize GlobalAddress and ConstantPool nodes into the
123 // appropriate instructions to materialize the address.
124 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
125 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
127 // RET must be custom lowered, to meet ABI requirements
128 setOperationAction(ISD::RET , MVT::Other, Custom);
130 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
131 setOperationAction(ISD::VASTART , MVT::Other, Custom);
133 // Use the default implementation.
134 setOperationAction(ISD::VAARG , MVT::Other, Expand);
135 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
136 setOperationAction(ISD::VAEND , MVT::Other, Expand);
137 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
138 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
139 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
141 // We want to custom lower some of our intrinsics.
142 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
144 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
145 // They also have instructions for converting between i64 and fp.
146 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
147 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
149 // FIXME: disable this lowered code. This generates 64-bit register values,
150 // and we don't model the fact that the top part is clobbered by calls. We
151 // need to flag these together so that the value isn't live across a call.
152 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
154 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
155 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
157 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
158 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
161 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
162 // 64 bit PowerPC implementations can support i64 types directly
163 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
164 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
165 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
167 // 32 bit PowerPC wants to expand i64 shifts itself.
168 setOperationAction(ISD::SHL, MVT::i64, Custom);
169 setOperationAction(ISD::SRL, MVT::i64, Custom);
170 setOperationAction(ISD::SRA, MVT::i64, Custom);
173 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
174 // First set operation action for all vector types to expand. Then we
175 // will selectively turn on ones that can be effectively codegen'd.
176 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
177 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
178 // add/sub are legal for all supported vector VT's.
179 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
180 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
182 // We promote all shuffles to v16i8.
183 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
184 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
186 // We promote all non-typed operations to v4i32.
187 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
188 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
189 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
190 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
191 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
192 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
193 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
194 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
195 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
196 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
197 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
198 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
200 // No other operations are legal.
201 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
202 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
203 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
204 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
205 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
206 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
207 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
208 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
210 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
213 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
214 // with merges, splats, etc.
215 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
217 setOperationAction(ISD::AND , MVT::v4i32, Legal);
218 setOperationAction(ISD::OR , MVT::v4i32, Legal);
219 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
220 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
221 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
222 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
224 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
225 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
226 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
227 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
229 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
231 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
232 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
234 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
235 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
236 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
237 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
240 setSetCCResultContents(ZeroOrOneSetCCResult);
241 setStackPointerRegisterToSaveRestore(PPC::R1);
243 // We have target-specific dag combine patterns for the following nodes:
244 setTargetDAGCombine(ISD::SINT_TO_FP);
245 setTargetDAGCombine(ISD::STORE);
247 computeRegisterProperties();
250 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
253 case PPCISD::FSEL: return "PPCISD::FSEL";
254 case PPCISD::FCFID: return "PPCISD::FCFID";
255 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
256 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
257 case PPCISD::STFIWX: return "PPCISD::STFIWX";
258 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
259 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
260 case PPCISD::VPERM: return "PPCISD::VPERM";
261 case PPCISD::Hi: return "PPCISD::Hi";
262 case PPCISD::Lo: return "PPCISD::Lo";
263 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
264 case PPCISD::SRL: return "PPCISD::SRL";
265 case PPCISD::SRA: return "PPCISD::SRA";
266 case PPCISD::SHL: return "PPCISD::SHL";
267 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
268 case PPCISD::STD_32: return "PPCISD::STD_32";
269 case PPCISD::CALL: return "PPCISD::CALL";
270 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
271 case PPCISD::MFCR: return "PPCISD::MFCR";
272 case PPCISD::VCMP: return "PPCISD::VCMP";
273 case PPCISD::VCMPo: return "PPCISD::VCMPo";
277 //===----------------------------------------------------------------------===//
278 // Node matching predicates, for use by the tblgen matching code.
279 //===----------------------------------------------------------------------===//
281 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
282 static bool isFloatingPointZero(SDOperand Op) {
283 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
284 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
285 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
286 // Maybe this has already been legalized into the constant pool?
287 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
288 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
289 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
294 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
295 /// true if Op is undef or if it matches the specified value.
296 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
297 return Op.getOpcode() == ISD::UNDEF ||
298 cast<ConstantSDNode>(Op)->getValue() == Val;
301 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
302 /// VPKUHUM instruction.
303 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
305 for (unsigned i = 0; i != 16; ++i)
306 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
309 for (unsigned i = 0; i != 8; ++i)
310 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
311 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
317 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
318 /// VPKUWUM instruction.
319 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
321 for (unsigned i = 0; i != 16; i += 2)
322 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
323 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
326 for (unsigned i = 0; i != 8; i += 2)
327 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
328 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
329 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
330 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
336 /// isVMerge - Common function, used to match vmrg* shuffles.
338 static bool isVMerge(SDNode *N, unsigned UnitSize,
339 unsigned LHSStart, unsigned RHSStart) {
340 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
341 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
342 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
343 "Unsupported merge size!");
345 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
346 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
347 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
348 LHSStart+j+i*UnitSize) ||
349 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
350 RHSStart+j+i*UnitSize))
356 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
357 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
358 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
360 return isVMerge(N, UnitSize, 8, 24);
361 return isVMerge(N, UnitSize, 8, 8);
364 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
365 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
366 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
368 return isVMerge(N, UnitSize, 0, 16);
369 return isVMerge(N, UnitSize, 0, 0);
373 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
374 /// amount, otherwise return -1.
375 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
376 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
377 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
378 // Find the first non-undef value in the shuffle mask.
380 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
383 if (i == 16) return -1; // all undef.
385 // Otherwise, check to see if the rest of the elements are consequtively
386 // numbered from this value.
387 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
388 if (ShiftAmt < i) return -1;
392 // Check the rest of the elements to see if they are consequtive.
393 for (++i; i != 16; ++i)
394 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
397 // Check the rest of the elements to see if they are consequtive.
398 for (++i; i != 16; ++i)
399 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
406 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
407 /// specifies a splat of a single element that is suitable for input to
408 /// VSPLTB/VSPLTH/VSPLTW.
409 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
410 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
411 N->getNumOperands() == 16 &&
412 (EltSize == 1 || EltSize == 2 || EltSize == 4));
414 // This is a splat operation if each element of the permute is the same, and
415 // if the value doesn't reference the second vector.
416 unsigned ElementBase = 0;
417 SDOperand Elt = N->getOperand(0);
418 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
419 ElementBase = EltV->getValue();
421 return false; // FIXME: Handle UNDEF elements too!
423 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
426 // Check that they are consequtive.
427 for (unsigned i = 1; i != EltSize; ++i) {
428 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
429 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
433 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
434 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
435 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
436 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
437 "Invalid VECTOR_SHUFFLE mask!");
438 for (unsigned j = 0; j != EltSize; ++j)
439 if (N->getOperand(i+j) != N->getOperand(j))
446 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
447 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
448 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
449 assert(isSplatShuffleMask(N, EltSize));
450 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
453 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
454 /// by using a vspltis[bhw] instruction of the specified element size, return
455 /// the constant being splatted. The ByteSize field indicates the number of
456 /// bytes of each element [124] -> [bhw].
457 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
458 SDOperand OpVal(0, 0);
460 // If ByteSize of the splat is bigger than the element size of the
461 // build_vector, then we have a case where we are checking for a splat where
462 // multiple elements of the buildvector are folded together into a single
463 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
464 unsigned EltSize = 16/N->getNumOperands();
465 if (EltSize < ByteSize) {
466 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
467 SDOperand UniquedVals[4];
468 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
470 // See if all of the elements in the buildvector agree across.
471 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
472 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
473 // If the element isn't a constant, bail fully out.
474 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
477 if (UniquedVals[i&(Multiple-1)].Val == 0)
478 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
479 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
480 return SDOperand(); // no match.
483 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
484 // either constant or undef values that are identical for each chunk. See
485 // if these chunks can form into a larger vspltis*.
487 // Check to see if all of the leading entries are either 0 or -1. If
488 // neither, then this won't fit into the immediate field.
489 bool LeadingZero = true;
490 bool LeadingOnes = true;
491 for (unsigned i = 0; i != Multiple-1; ++i) {
492 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
494 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
495 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
497 // Finally, check the least significant entry.
499 if (UniquedVals[Multiple-1].Val == 0)
500 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
501 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
503 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
506 if (UniquedVals[Multiple-1].Val == 0)
507 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
508 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
509 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
510 return DAG.getTargetConstant(Val, MVT::i32);
516 // Check to see if this buildvec has a single non-undef value in its elements.
517 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
518 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
520 OpVal = N->getOperand(i);
521 else if (OpVal != N->getOperand(i))
525 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
527 unsigned ValSizeInBytes = 0;
529 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
530 Value = CN->getValue();
531 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
532 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
533 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
534 Value = FloatToBits(CN->getValue());
538 // If the splat value is larger than the element value, then we can never do
539 // this splat. The only case that we could fit the replicated bits into our
540 // immediate field for would be zero, and we prefer to use vxor for it.
541 if (ValSizeInBytes < ByteSize) return SDOperand();
543 // If the element value is larger than the splat value, cut it in half and
544 // check to see if the two halves are equal. Continue doing this until we
545 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
546 while (ValSizeInBytes > ByteSize) {
547 ValSizeInBytes >>= 1;
549 // If the top half equals the bottom half, we're still ok.
550 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
551 (Value & ((1 << (8*ValSizeInBytes))-1)))
555 // Properly sign extend the value.
556 int ShAmt = (4-ByteSize)*8;
557 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
559 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
560 if (MaskVal == 0) return SDOperand();
562 // Finally, if this value fits in a 5 bit sext field, return it
563 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
564 return DAG.getTargetConstant(MaskVal, MVT::i32);
568 //===----------------------------------------------------------------------===//
569 // LowerOperation implementation
570 //===----------------------------------------------------------------------===//
572 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
573 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
574 Constant *C = CP->get();
575 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
576 SDOperand Zero = DAG.getConstant(0, MVT::i32);
578 const TargetMachine &TM = DAG.getTarget();
580 // If this is a non-darwin platform, we don't support non-static relo models
582 if (TM.getRelocationModel() == Reloc::Static ||
583 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
584 // Generate non-pic code that has direct accesses to the constant pool.
585 // The address of the global is just (hi(&g)+lo(&g)).
586 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
587 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
588 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
591 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
592 if (TM.getRelocationModel() == Reloc::PIC) {
593 // With PIC, the first instruction is actually "GR+hi(&G)".
594 Hi = DAG.getNode(ISD::ADD, MVT::i32,
595 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
598 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
599 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
603 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
604 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
605 GlobalValue *GV = GSDN->getGlobal();
606 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
607 SDOperand Zero = DAG.getConstant(0, MVT::i32);
609 const TargetMachine &TM = DAG.getTarget();
611 // If this is a non-darwin platform, we don't support non-static relo models
613 if (TM.getRelocationModel() == Reloc::Static ||
614 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
615 // Generate non-pic code that has direct accesses to globals.
616 // The address of the global is just (hi(&g)+lo(&g)).
617 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
618 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
619 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
622 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
623 if (TM.getRelocationModel() == Reloc::PIC) {
624 // With PIC, the first instruction is actually "GR+hi(&G)".
625 Hi = DAG.getNode(ISD::ADD, MVT::i32,
626 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
629 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
630 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
632 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
633 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
636 // If the global is weak or external, we have to go through the lazy
638 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
641 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
642 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
644 // If we're comparing for equality to zero, expose the fact that this is
645 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
646 // fold the new nodes.
647 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
648 if (C->isNullValue() && CC == ISD::SETEQ) {
649 MVT::ValueType VT = Op.getOperand(0).getValueType();
650 SDOperand Zext = Op.getOperand(0);
653 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
655 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
656 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
657 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
658 DAG.getConstant(Log2b, MVT::i32));
659 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
661 // Leave comparisons against 0 and -1 alone for now, since they're usually
662 // optimized. FIXME: revisit this when we can custom lower all setcc
664 if (C->isAllOnesValue() || C->isNullValue())
668 // If we have an integer seteq/setne, turn it into a compare against zero
669 // by subtracting the rhs from the lhs, which is faster than setting a
670 // condition register, reading it back out, and masking the correct bit.
671 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
672 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
673 MVT::ValueType VT = Op.getValueType();
674 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
676 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
681 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
682 unsigned VarArgsFrameIndex) {
683 // vastart just stores the address of the VarArgsFrameIndex slot into the
684 // memory location argument.
685 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
686 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
687 Op.getOperand(1), Op.getOperand(2));
690 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
692 switch(Op.getNumOperands()) {
694 assert(0 && "Do not know how to return this many arguments!");
697 return SDOperand(); // ret void is legal
699 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
701 if (MVT::isVector(ArgVT))
703 else if (MVT::isInteger(ArgVT))
706 assert(MVT::isFloatingPoint(ArgVT));
710 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
713 // If we haven't noted the R3/F1 are live out, do so now.
714 if (DAG.getMachineFunction().liveout_empty())
715 DAG.getMachineFunction().addLiveOut(ArgReg);
719 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
721 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
722 // If we haven't noted the R3+R4 are live out, do so now.
723 if (DAG.getMachineFunction().liveout_empty()) {
724 DAG.getMachineFunction().addLiveOut(PPC::R3);
725 DAG.getMachineFunction().addLiveOut(PPC::R4);
729 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
732 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
734 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
735 // Not FP? Not a fsel.
736 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
737 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
740 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
742 // Cannot handle SETEQ/SETNE.
743 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
745 MVT::ValueType ResVT = Op.getValueType();
746 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
747 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
748 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
750 // If the RHS of the comparison is a 0.0, we don't need to do the
751 // subtraction at all.
752 if (isFloatingPointZero(RHS))
754 default: break; // SETUO etc aren't handled by fsel.
757 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
760 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
761 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
762 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
765 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
768 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
769 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
770 return DAG.getNode(PPCISD::FSEL, ResVT,
771 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
776 default: break; // SETUO etc aren't handled by fsel.
779 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
780 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
781 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
782 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
785 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
786 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
787 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
788 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
791 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
792 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
793 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
794 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
797 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
798 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
799 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
800 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
805 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
806 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
807 SDOperand Src = Op.getOperand(0);
808 if (Src.getValueType() == MVT::f32)
809 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
812 switch (Op.getValueType()) {
813 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
815 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
818 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
822 // Convert the FP value to an int value through memory.
823 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
824 if (Op.getValueType() == MVT::i32)
825 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
829 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
830 if (Op.getOperand(0).getValueType() == MVT::i64) {
831 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
832 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
833 if (Op.getValueType() == MVT::f32)
834 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
838 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
839 "Unhandled SINT_TO_FP type in custom expander!");
840 // Since we only generate this in 64-bit mode, we can take advantage of
841 // 64-bit registers. In particular, sign extend the input value into the
842 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
843 // then lfd it and fcfid it.
844 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
845 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
846 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
848 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
851 // STD the extended value into the stack slot.
852 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
853 DAG.getEntryNode(), Ext64, FIdx,
854 DAG.getSrcValue(NULL));
855 // Load the value as a double.
856 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
858 // FCFID it and return it.
859 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
860 if (Op.getValueType() == MVT::f32)
861 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
865 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) {
866 assert(Op.getValueType() == MVT::i64 &&
867 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
868 // The generic code does a fine job expanding shift by a constant.
869 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
871 // Otherwise, expand into a bunch of logical ops. Note that these ops
872 // depend on the PPC behavior for oversized shift amounts.
873 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
874 DAG.getConstant(0, MVT::i32));
875 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
876 DAG.getConstant(1, MVT::i32));
877 SDOperand Amt = Op.getOperand(1);
879 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
880 DAG.getConstant(32, MVT::i32), Amt);
881 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
882 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
883 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
884 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
885 DAG.getConstant(-32U, MVT::i32));
886 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
887 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
888 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
889 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
892 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) {
893 assert(Op.getValueType() == MVT::i64 &&
894 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
895 // The generic code does a fine job expanding shift by a constant.
896 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
898 // Otherwise, expand into a bunch of logical ops. Note that these ops
899 // depend on the PPC behavior for oversized shift amounts.
900 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
901 DAG.getConstant(0, MVT::i32));
902 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
903 DAG.getConstant(1, MVT::i32));
904 SDOperand Amt = Op.getOperand(1);
906 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
907 DAG.getConstant(32, MVT::i32), Amt);
908 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
909 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
910 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
911 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
912 DAG.getConstant(-32U, MVT::i32));
913 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
914 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
915 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
916 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
919 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) {
920 assert(Op.getValueType() == MVT::i64 &&
921 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
922 // The generic code does a fine job expanding shift by a constant.
923 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
925 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
926 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
927 DAG.getConstant(0, MVT::i32));
928 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
929 DAG.getConstant(1, MVT::i32));
930 SDOperand Amt = Op.getOperand(1);
932 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
933 DAG.getConstant(32, MVT::i32), Amt);
934 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
935 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
936 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
937 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
938 DAG.getConstant(-32U, MVT::i32));
939 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
940 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
941 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
942 Tmp4, Tmp6, ISD::SETLE);
943 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
946 //===----------------------------------------------------------------------===//
947 // Vector related lowering.
950 // If this is a vector of constants or undefs, get the bits. A bit in
951 // UndefBits is set if the corresponding element of the vector is an
952 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
953 // zero. Return true if this is not an array of constants, false if it is.
955 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
956 uint64_t UndefBits[2]) {
957 // Start with zero'd results.
958 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
960 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
961 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
962 SDOperand OpVal = BV->getOperand(i);
964 unsigned PartNo = i >= e/2; // In the upper 128 bits?
965 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
967 uint64_t EltBits = 0;
968 if (OpVal.getOpcode() == ISD::UNDEF) {
969 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
970 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
972 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
973 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
974 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
975 assert(CN->getValueType(0) == MVT::f32 &&
976 "Only one legal FP vector type!");
977 EltBits = FloatToBits(CN->getValue());
979 // Nonconstant element.
983 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
986 //printf("%llx %llx %llx %llx\n",
987 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
991 // If this is a splat (repetition) of a value across the whole vector, return
992 // the smallest size that splats it. For example, "0x01010101010101..." is a
993 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
994 // SplatSize = 1 byte.
995 static bool isConstantSplat(const uint64_t Bits128[2],
996 const uint64_t Undef128[2],
997 unsigned &SplatBits, unsigned &SplatUndef,
998 unsigned &SplatSize) {
1000 // Don't let undefs prevent splats from matching. See if the top 64-bits are
1001 // the same as the lower 64-bits, ignoring undefs.
1002 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
1003 return false; // Can't be a splat if two pieces don't match.
1005 uint64_t Bits64 = Bits128[0] | Bits128[1];
1006 uint64_t Undef64 = Undef128[0] & Undef128[1];
1008 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
1010 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
1011 return false; // Can't be a splat if two pieces don't match.
1013 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
1014 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
1016 // If the top 16-bits are different than the lower 16-bits, ignoring
1017 // undefs, we have an i32 splat.
1018 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
1020 SplatUndef = Undef32;
1025 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
1026 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
1028 // If the top 8-bits are different than the lower 8-bits, ignoring
1029 // undefs, we have an i16 splat.
1030 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
1032 SplatUndef = Undef16;
1037 // Otherwise, we have an 8-bit splat.
1038 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
1039 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
1044 // If this is a case we can't handle, return null and let the default
1045 // expansion code take care of it. If we CAN select this case, and if it
1046 // selects to a single instruction, return Op. Otherwise, if we can codegen
1047 // this case more efficiently than a constant pool load, lower it to the
1048 // sequence of ops that should be used.
1049 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1050 // If this is a vector of constants or undefs, get the bits. A bit in
1051 // UndefBits is set if the corresponding element of the vector is an
1052 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
1054 uint64_t VectorBits[2];
1055 uint64_t UndefBits[2];
1056 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
1057 return SDOperand(); // Not a constant vector.
1059 // If this is a splat (repetition) of a value across the whole vector, return
1060 // the smallest size that splats it. For example, "0x01010101010101..." is a
1061 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
1062 // SplatSize = 1 byte.
1063 unsigned SplatBits, SplatUndef, SplatSize;
1064 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
1065 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
1067 // First, handle single instruction cases.
1070 if (SplatBits == 0) {
1071 // Canonicalize all zero vectors to be v4i32.
1072 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
1073 SDOperand Z = DAG.getConstant(0, MVT::i32);
1074 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
1075 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1080 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
1081 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
1082 if (SextVal >= -16 && SextVal <= 15) {
1083 const MVT::ValueType VTys[] = { // canonical VT to use for each size.
1084 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
1086 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
1088 // If this is a non-canonical splat for this value,
1089 if (Op.getValueType() != CanonicalVT || HasAnyUndefs) {
1090 SDOperand Elt = DAG.getConstant(SplatBits,
1091 MVT::getVectorBaseType(CanonicalVT));
1092 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1093 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1094 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1100 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1101 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important
1103 if (SplatSize == 4 &&
1104 SplatBits == 0x80000000 || SplatBits == (0x7FFFFFFF&~SplatUndef)) {
1105 // Make -1 and vspltisw -1:
1106 SDOperand OnesI = DAG.getConstant(~0U, MVT::i32);
1107 SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
1108 OnesI, OnesI, OnesI, OnesI);
1110 // Make the VSLW intrinsic, computing 0x8000_0000.
1112 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32,
1113 DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32),
1116 // If this is 0x7FFF_FFFF, xor by OnesV to invert it.
1117 if (SplatBits == 0x80000000)
1118 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1120 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1127 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
1128 /// the specified operations to build the shuffle.
1129 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
1130 SDOperand RHS, SelectionDAG &DAG) {
1131 unsigned OpNum = (PFEntry >> 26) & 0x0F;
1132 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
1133 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
1136 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
1148 if (OpNum == OP_COPY) {
1149 if (LHSID == (1*9+2)*9+3) return LHS;
1150 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
1154 unsigned ShufIdxs[16];
1156 default: assert(0 && "Unknown i32 permute!");
1158 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
1159 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
1160 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
1161 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
1164 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
1165 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
1166 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
1167 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
1170 for (unsigned i = 0; i != 16; ++i)
1171 ShufIdxs[i] = (i&3)+0;
1174 for (unsigned i = 0; i != 16; ++i)
1175 ShufIdxs[i] = (i&3)+4;
1178 for (unsigned i = 0; i != 16; ++i)
1179 ShufIdxs[i] = (i&3)+8;
1182 for (unsigned i = 0; i != 16; ++i)
1183 ShufIdxs[i] = (i&3)+12;
1186 for (unsigned i = 0; i != 16; ++i)
1190 for (unsigned i = 0; i != 16; ++i)
1194 for (unsigned i = 0; i != 16; ++i)
1198 std::vector<SDOperand> Ops;
1199 for (unsigned i = 0; i != 16; ++i)
1200 Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
1201 SDOperand OpLHS, OpRHS;
1202 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
1203 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
1205 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
1206 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
1209 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1210 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1211 /// return the code it can be lowered into. Worst case, it can always be
1212 /// lowered into a vperm.
1213 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1214 SDOperand V1 = Op.getOperand(0);
1215 SDOperand V2 = Op.getOperand(1);
1216 SDOperand PermMask = Op.getOperand(2);
1218 // Cases that are handled by instructions that take permute immediates
1219 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1220 // selected by the instruction selector.
1221 if (V2.getOpcode() == ISD::UNDEF) {
1222 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1223 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1224 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1225 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1226 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1227 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1228 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1229 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1230 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1231 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1232 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1233 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1238 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1239 // and produce a fixed permutation. If any of these match, do not lower to
1241 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1242 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1243 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1244 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1245 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1246 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1247 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1248 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1249 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1252 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
1253 // perfect shuffle table to emit an optimal matching sequence.
1254 unsigned PFIndexes[4];
1255 bool isFourElementShuffle = true;
1256 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
1257 unsigned EltNo = 8; // Start out undef.
1258 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
1259 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
1260 continue; // Undef, ignore it.
1262 unsigned ByteSource =
1263 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
1264 if ((ByteSource & 3) != j) {
1265 isFourElementShuffle = false;
1270 EltNo = ByteSource/4;
1271 } else if (EltNo != ByteSource/4) {
1272 isFourElementShuffle = false;
1276 PFIndexes[i] = EltNo;
1279 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
1280 // perfect shuffle vector to determine if it is cost effective to do this as
1281 // discrete instructions, or whether we should use a vperm.
1282 if (isFourElementShuffle) {
1283 // Compute the index in the perfect shuffle table.
1284 unsigned PFTableIndex =
1285 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
1287 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
1288 unsigned Cost = (PFEntry >> 30);
1290 // Determining when to avoid vperm is tricky. Many things affect the cost
1291 // of vperm, particularly how many times the perm mask needs to be computed.
1292 // For example, if the perm mask can be hoisted out of a loop or is already
1293 // used (perhaps because there are multiple permutes with the same shuffle
1294 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
1295 // the loop requires an extra register.
1297 // As a compromise, we only emit discrete instructions if the shuffle can be
1298 // generated in 3 or fewer operations. When we have loop information
1299 // available, if this block is within a loop, we should avoid using vperm
1300 // for 3-operation perms and use a constant pool load instead.
1302 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
1305 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1306 // vector that will get spilled to the constant pool.
1307 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1309 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1310 // that it is in input element units, not in bytes. Convert now.
1311 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1312 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1314 std::vector<SDOperand> ResultMask;
1315 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1317 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
1320 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1322 for (unsigned j = 0; j != BytesPerElement; ++j)
1323 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1327 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
1328 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
1331 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
1332 /// lower, do it, otherwise return null.
1333 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
1334 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
1336 // If this is a lowered altivec predicate compare, CompareOpc is set to the
1337 // opcode number of the comparison.
1338 int CompareOpc = -1;
1341 default: return SDOperand(); // Don't custom lower most intrinsics.
1342 // Comparison predicates.
1343 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
1344 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
1345 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
1346 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
1347 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
1348 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
1349 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
1350 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
1351 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
1352 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
1353 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
1354 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
1355 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
1357 // Normal Comparisons.
1358 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
1359 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
1360 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
1361 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
1362 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
1363 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
1364 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
1365 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
1366 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
1367 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
1368 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
1369 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
1370 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
1373 assert(CompareOpc>0 && "We only lower altivec predicate compares so far!");
1375 // If this is a non-dot comparison, make the VCMP node.
1377 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
1378 Op.getOperand(1), Op.getOperand(2),
1379 DAG.getConstant(CompareOpc, MVT::i32));
1380 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
1383 // Create the PPCISD altivec 'dot' comparison node.
1384 std::vector<SDOperand> Ops;
1385 std::vector<MVT::ValueType> VTs;
1386 Ops.push_back(Op.getOperand(2)); // LHS
1387 Ops.push_back(Op.getOperand(3)); // RHS
1388 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
1389 VTs.push_back(Op.getOperand(2).getValueType());
1390 VTs.push_back(MVT::Flag);
1391 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
1393 // Now that we have the comparison, emit a copy from the CR to a GPR.
1394 // This is flagged to the above dot comparison.
1395 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
1396 DAG.getRegister(PPC::CR6, MVT::i32),
1397 CompNode.getValue(1));
1399 // Unpack the result based on how the target uses it.
1400 unsigned BitNo; // Bit # of CR6.
1401 bool InvertBit; // Invert result?
1402 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1403 default: // Can't happen, don't crash on invalid number though.
1404 case 0: // Return the value of the EQ bit of CR6.
1405 BitNo = 0; InvertBit = false;
1407 case 1: // Return the inverted value of the EQ bit of CR6.
1408 BitNo = 0; InvertBit = true;
1410 case 2: // Return the value of the LT bit of CR6.
1411 BitNo = 2; InvertBit = false;
1413 case 3: // Return the inverted value of the LT bit of CR6.
1414 BitNo = 2; InvertBit = true;
1418 // Shift the bit into the low position.
1419 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
1420 DAG.getConstant(8-(3-BitNo), MVT::i32));
1422 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
1423 DAG.getConstant(1, MVT::i32));
1425 // If we are supposed to, toggle the bit.
1427 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
1428 DAG.getConstant(1, MVT::i32));
1432 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1433 // Create a stack slot that is 16-byte aligned.
1434 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1435 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
1436 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1438 // Store the input value into Value#0 of the stack slot.
1439 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1440 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
1442 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
1445 /// LowerOperation - Provide custom lowering hooks for some operations.
1447 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1448 switch (Op.getOpcode()) {
1449 default: assert(0 && "Wasn't expecting to be able to lower this!");
1450 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1451 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1452 case ISD::SETCC: return LowerSETCC(Op, DAG);
1453 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1454 case ISD::RET: return LowerRET(Op, DAG);
1456 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1457 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1458 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1460 // Lower 64-bit shifts.
1461 case ISD::SHL: return LowerSHL(Op, DAG);
1462 case ISD::SRL: return LowerSRL(Op, DAG);
1463 case ISD::SRA: return LowerSRA(Op, DAG);
1465 // Vector-related lowering.
1466 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
1467 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
1468 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1469 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
1474 //===----------------------------------------------------------------------===//
1475 // Other Lowering Code
1476 //===----------------------------------------------------------------------===//
1478 std::vector<SDOperand>
1479 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
1481 // add beautiful description of PPC stack frame format, or at least some docs
1483 MachineFunction &MF = DAG.getMachineFunction();
1484 MachineFrameInfo *MFI = MF.getFrameInfo();
1485 MachineBasicBlock& BB = MF.front();
1486 SSARegMap *RegMap = MF.getSSARegMap();
1487 std::vector<SDOperand> ArgValues;
1489 unsigned ArgOffset = 24;
1490 unsigned GPR_remaining = 8;
1491 unsigned FPR_remaining = 13;
1492 unsigned GPR_idx = 0, FPR_idx = 0;
1493 static const unsigned GPR[] = {
1494 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1495 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1497 static const unsigned FPR[] = {
1498 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1499 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1502 // Add DAG nodes to load the arguments... On entry to a function on PPC,
1503 // the arguments start at offset 24, although they are likely to be passed
1505 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
1506 SDOperand newroot, argt;
1508 bool needsLoad = false;
1509 bool ArgLive = !I->use_empty();
1510 MVT::ValueType ObjectVT = getValueType(I->getType());
1513 default: assert(0 && "Unhandled argument type!");
1519 if (!ArgLive) break;
1520 if (GPR_remaining > 0) {
1521 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1522 MF.addLiveIn(GPR[GPR_idx], VReg);
1523 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1524 if (ObjectVT != MVT::i32) {
1525 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
1527 argt = DAG.getNode(AssertOp, MVT::i32, argt,
1528 DAG.getValueType(ObjectVT));
1529 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
1537 if (!ArgLive) break;
1538 if (GPR_remaining > 0) {
1539 SDOperand argHi, argLo;
1540 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1541 MF.addLiveIn(GPR[GPR_idx], VReg);
1542 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1543 // If we have two or more remaining argument registers, then both halves
1544 // of the i64 can be sourced from there. Otherwise, the lower half will
1545 // have to come off the stack. This can happen when an i64 is preceded
1546 // by 28 bytes of arguments.
1547 if (GPR_remaining > 1) {
1548 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1549 MF.addLiveIn(GPR[GPR_idx+1], VReg);
1550 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
1552 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
1553 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
1554 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
1555 DAG.getSrcValue(NULL));
1557 // Build the outgoing arg thingy
1558 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
1566 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
1568 if (FPR_remaining > 0) {
1574 if (FPR_remaining > 0) {
1576 if (ObjectVT == MVT::f32)
1577 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1579 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1580 MF.addLiveIn(FPR[FPR_idx], VReg);
1581 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
1590 // We need to load the argument to a virtual register if we determined above
1591 // that we ran out of physical registers of the appropriate type
1593 unsigned SubregOffset = 0;
1594 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
1595 if (ObjectVT == MVT::i16) SubregOffset = 2;
1596 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1597 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
1598 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
1599 DAG.getConstant(SubregOffset, MVT::i32));
1600 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
1601 DAG.getSrcValue(NULL));
1604 // Every 4 bytes of argument space consumes one of the GPRs available for
1605 // argument passing.
1606 if (GPR_remaining > 0) {
1607 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
1608 GPR_remaining -= delta;
1611 ArgOffset += ObjSize;
1613 DAG.setRoot(newroot.getValue(1));
1615 ArgValues.push_back(argt);
1618 // If the function takes variable number of arguments, make a frame index for
1619 // the start of the first vararg value... for expansion of llvm.va_start.
1621 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1622 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
1623 // If this function is vararg, store any remaining integer argument regs
1624 // to their spots on the stack so that they may be loaded by deferencing the
1625 // result of va_next.
1626 std::vector<SDOperand> MemOps;
1627 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
1628 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1629 MF.addLiveIn(GPR[GPR_idx], VReg);
1630 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1631 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
1632 Val, FIN, DAG.getSrcValue(NULL));
1633 MemOps.push_back(Store);
1634 // Increment the address by four for the next argument to store
1635 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
1636 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
1638 if (!MemOps.empty()) {
1639 MemOps.push_back(DAG.getRoot());
1640 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
1647 std::pair<SDOperand, SDOperand>
1648 PPCTargetLowering::LowerCallTo(SDOperand Chain,
1649 const Type *RetTy, bool isVarArg,
1650 unsigned CallingConv, bool isTailCall,
1651 SDOperand Callee, ArgListTy &Args,
1652 SelectionDAG &DAG) {
1653 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1654 // SelectExpr to use to put the arguments in the appropriate registers.
1655 std::vector<SDOperand> args_to_use;
1657 // Count how many bytes are to be pushed on the stack, including the linkage
1658 // area, and parameter passing area.
1659 unsigned NumBytes = 24;
1662 Chain = DAG.getCALLSEQ_START(Chain,
1663 DAG.getConstant(NumBytes, getPointerTy()));
1665 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1666 switch (getValueType(Args[i].second)) {
1667 default: assert(0 && "Unknown value type!");
1682 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
1683 // plus 32 bytes of argument space in case any called code gets funky on us.
1684 // (Required by ABI to support var arg)
1685 if (NumBytes < 56) NumBytes = 56;
1687 // Adjust the stack pointer for the new arguments...
1688 // These operations are automatically eliminated by the prolog/epilog pass
1689 Chain = DAG.getCALLSEQ_START(Chain,
1690 DAG.getConstant(NumBytes, getPointerTy()));
1692 // Set up a copy of the stack pointer for use loading and storing any
1693 // arguments that may not fit in the registers available for argument
1695 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1697 // Figure out which arguments are going to go in registers, and which in
1698 // memory. Also, if this is a vararg function, floating point operations
1699 // must be stored to our stack, and loaded into integer regs as well, if
1700 // any integer regs are available for argument passing.
1701 unsigned ArgOffset = 24;
1702 unsigned GPR_remaining = 8;
1703 unsigned FPR_remaining = 13;
1705 std::vector<SDOperand> MemOps;
1706 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1707 // PtrOff will be used to store the current argument to the stack if a
1708 // register cannot be found for it.
1709 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1710 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
1711 MVT::ValueType ArgVT = getValueType(Args[i].second);
1714 default: assert(0 && "Unexpected ValueType for argument!");
1718 // Promote the integer to 32 bits. If the input type is signed use a
1719 // sign extend, otherwise use a zero extend.
1720 if (Args[i].second->isSigned())
1721 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
1723 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
1726 if (GPR_remaining > 0) {
1727 args_to_use.push_back(Args[i].first);
1730 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1731 Args[i].first, PtrOff,
1732 DAG.getSrcValue(NULL)));
1737 // If we have one free GPR left, we can place the upper half of the i64
1738 // in it, and store the other half to the stack. If we have two or more
1739 // free GPRs, then we can pass both halves of the i64 in registers.
1740 if (GPR_remaining > 0) {
1741 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1742 Args[i].first, DAG.getConstant(1, MVT::i32));
1743 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1744 Args[i].first, DAG.getConstant(0, MVT::i32));
1745 args_to_use.push_back(Hi);
1747 if (GPR_remaining > 0) {
1748 args_to_use.push_back(Lo);
1751 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
1752 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
1753 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1754 Lo, PtrOff, DAG.getSrcValue(NULL)));
1757 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1758 Args[i].first, PtrOff,
1759 DAG.getSrcValue(NULL)));
1765 if (FPR_remaining > 0) {
1766 args_to_use.push_back(Args[i].first);
1769 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
1770 Args[i].first, PtrOff,
1771 DAG.getSrcValue(NULL));
1772 MemOps.push_back(Store);
1773 // Float varargs are always shadowed in available integer registers
1774 if (GPR_remaining > 0) {
1775 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
1776 DAG.getSrcValue(NULL));
1777 MemOps.push_back(Load.getValue(1));
1778 args_to_use.push_back(Load);
1781 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
1782 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
1783 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
1784 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
1785 DAG.getSrcValue(NULL));
1786 MemOps.push_back(Load.getValue(1));
1787 args_to_use.push_back(Load);
1791 // If we have any FPRs remaining, we may also have GPRs remaining.
1792 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1794 if (GPR_remaining > 0) {
1795 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
1798 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
1799 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
1804 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1805 Args[i].first, PtrOff,
1806 DAG.getSrcValue(NULL)));
1808 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
1812 if (!MemOps.empty())
1813 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
1816 std::vector<MVT::ValueType> RetVals;
1817 MVT::ValueType RetTyVT = getValueType(RetTy);
1818 MVT::ValueType ActualRetTyVT = RetTyVT;
1819 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
1820 ActualRetTyVT = MVT::i32; // Promote result to i32.
1822 if (RetTyVT == MVT::i64) {
1823 RetVals.push_back(MVT::i32);
1824 RetVals.push_back(MVT::i32);
1825 } else if (RetTyVT != MVT::isVoid) {
1826 RetVals.push_back(ActualRetTyVT);
1828 RetVals.push_back(MVT::Other);
1830 // If the callee is a GlobalAddress node (quite common, every direct call is)
1831 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1832 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1833 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
1835 std::vector<SDOperand> Ops;
1836 Ops.push_back(Chain);
1837 Ops.push_back(Callee);
1838 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
1839 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops);
1840 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1);
1841 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1842 DAG.getConstant(NumBytes, getPointerTy()));
1843 SDOperand RetVal = TheCall;
1845 // If the result is a small value, add a note so that we keep track of the
1846 // information about whether it is sign or zero extended.
1847 if (RetTyVT != ActualRetTyVT) {
1848 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
1849 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
1850 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
1851 } else if (RetTyVT == MVT::i64) {
1852 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1));
1855 return std::make_pair(RetVal, Chain);
1859 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1860 MachineBasicBlock *BB) {
1861 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
1862 MI->getOpcode() == PPC::SELECT_CC_F4 ||
1863 MI->getOpcode() == PPC::SELECT_CC_F8 ||
1864 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
1865 "Unexpected instr type to insert");
1867 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1868 // control-flow pattern. The incoming instruction knows the destination vreg
1869 // to set, the condition code register to branch on, the true/false values to
1870 // select between, and a branch opcode to use.
1871 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1872 ilist<MachineBasicBlock>::iterator It = BB;
1878 // cmpTY ccX, r1, r2
1880 // fallthrough --> copy0MBB
1881 MachineBasicBlock *thisMBB = BB;
1882 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1883 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1884 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
1885 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1886 MachineFunction *F = BB->getParent();
1887 F->getBasicBlockList().insert(It, copy0MBB);
1888 F->getBasicBlockList().insert(It, sinkMBB);
1889 // Update machine-CFG edges by first adding all successors of the current
1890 // block to the new block which will contain the Phi node for the select.
1891 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1892 e = BB->succ_end(); i != e; ++i)
1893 sinkMBB->addSuccessor(*i);
1894 // Next, remove all successors of the current block, and add the true
1895 // and fallthrough blocks as its successors.
1896 while(!BB->succ_empty())
1897 BB->removeSuccessor(BB->succ_begin());
1898 BB->addSuccessor(copy0MBB);
1899 BB->addSuccessor(sinkMBB);
1902 // %FalseValue = ...
1903 // # fallthrough to sinkMBB
1906 // Update machine-CFG edges
1907 BB->addSuccessor(sinkMBB);
1910 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1913 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
1914 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1915 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1917 delete MI; // The pseudo instruction is gone now.
1921 //===----------------------------------------------------------------------===//
1922 // Target Optimization Hooks
1923 //===----------------------------------------------------------------------===//
1925 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
1926 DAGCombinerInfo &DCI) const {
1927 TargetMachine &TM = getTargetMachine();
1928 SelectionDAG &DAG = DCI.DAG;
1929 switch (N->getOpcode()) {
1931 case ISD::SINT_TO_FP:
1932 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
1933 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
1934 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
1935 // We allow the src/dst to be either f32/f64, but the intermediate
1936 // type must be i64.
1937 if (N->getOperand(0).getValueType() == MVT::i64) {
1938 SDOperand Val = N->getOperand(0).getOperand(0);
1939 if (Val.getValueType() == MVT::f32) {
1940 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
1941 DCI.AddToWorklist(Val.Val);
1944 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
1945 DCI.AddToWorklist(Val.Val);
1946 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
1947 DCI.AddToWorklist(Val.Val);
1948 if (N->getValueType(0) == MVT::f32) {
1949 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
1950 DCI.AddToWorklist(Val.Val);
1953 } else if (N->getOperand(0).getValueType() == MVT::i32) {
1954 // If the intermediate type is i32, we can avoid the load/store here
1961 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
1962 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
1963 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
1964 N->getOperand(1).getValueType() == MVT::i32) {
1965 SDOperand Val = N->getOperand(1).getOperand(0);
1966 if (Val.getValueType() == MVT::f32) {
1967 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
1968 DCI.AddToWorklist(Val.Val);
1970 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
1971 DCI.AddToWorklist(Val.Val);
1973 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
1974 N->getOperand(2), N->getOperand(3));
1975 DCI.AddToWorklist(Val.Val);
1979 case PPCISD::VCMP: {
1980 // If a VCMPo node already exists with exactly the same operands as this
1981 // node, use its result instead of this node (VCMPo computes both a CR6 and
1982 // a normal output).
1984 if (!N->getOperand(0).hasOneUse() &&
1985 !N->getOperand(1).hasOneUse() &&
1986 !N->getOperand(2).hasOneUse()) {
1988 // Scan all of the users of the LHS, looking for VCMPo's that match.
1989 SDNode *VCMPoNode = 0;
1991 SDNode *LHSN = N->getOperand(0).Val;
1992 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
1994 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
1995 (*UI)->getOperand(1) == N->getOperand(1) &&
1996 (*UI)->getOperand(2) == N->getOperand(2) &&
1997 (*UI)->getOperand(0) == N->getOperand(0)) {
2002 // If there are non-zero uses of the flag value, use the VCMPo node!
2003 if (VCMPoNode && !VCMPoNode->hasNUsesOfValue(0, 1))
2004 return SDOperand(VCMPoNode, 0);
2013 //===----------------------------------------------------------------------===//
2014 // Inline Assembly Support
2015 //===----------------------------------------------------------------------===//
2017 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
2019 uint64_t &KnownZero,
2021 unsigned Depth) const {
2024 switch (Op.getOpcode()) {
2026 case ISD::INTRINSIC_WO_CHAIN: {
2027 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
2029 case Intrinsic::ppc_altivec_vcmpbfp_p:
2030 case Intrinsic::ppc_altivec_vcmpeqfp_p:
2031 case Intrinsic::ppc_altivec_vcmpequb_p:
2032 case Intrinsic::ppc_altivec_vcmpequh_p:
2033 case Intrinsic::ppc_altivec_vcmpequw_p:
2034 case Intrinsic::ppc_altivec_vcmpgefp_p:
2035 case Intrinsic::ppc_altivec_vcmpgtfp_p:
2036 case Intrinsic::ppc_altivec_vcmpgtsb_p:
2037 case Intrinsic::ppc_altivec_vcmpgtsh_p:
2038 case Intrinsic::ppc_altivec_vcmpgtsw_p:
2039 case Intrinsic::ppc_altivec_vcmpgtub_p:
2040 case Intrinsic::ppc_altivec_vcmpgtuh_p:
2041 case Intrinsic::ppc_altivec_vcmpgtuw_p:
2042 KnownZero = ~1U; // All bits but the low one are known to be zero.
2050 /// getConstraintType - Given a constraint letter, return the type of
2051 /// constraint it is for this target.
2052 PPCTargetLowering::ConstraintType
2053 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
2054 switch (ConstraintLetter) {
2061 return C_RegisterClass;
2063 return TargetLowering::getConstraintType(ConstraintLetter);
2067 std::vector<unsigned> PPCTargetLowering::
2068 getRegClassForInlineAsmConstraint(const std::string &Constraint,
2069 MVT::ValueType VT) const {
2070 if (Constraint.size() == 1) {
2071 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
2072 default: break; // Unknown constriant letter
2074 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
2075 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2076 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2077 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2078 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2079 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2080 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2081 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2084 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
2085 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
2086 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
2087 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
2088 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
2089 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
2090 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
2091 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
2094 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
2095 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
2096 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
2097 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
2098 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
2099 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
2100 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
2101 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
2104 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
2105 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
2106 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
2107 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
2108 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
2109 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
2110 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
2111 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
2114 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
2115 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
2120 return std::vector<unsigned>();
2123 // isOperandValidForConstraint
2124 bool PPCTargetLowering::
2125 isOperandValidForConstraint(SDOperand Op, char Letter) {
2136 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
2137 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
2139 default: assert(0 && "Unknown constraint letter!");
2140 case 'I': // "I" is a signed 16-bit constant.
2141 return (short)Value == (int)Value;
2142 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
2143 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
2144 return (short)Value == 0;
2145 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
2146 return (Value >> 16) == 0;
2147 case 'M': // "M" is a constant that is greater than 31.
2149 case 'N': // "N" is a positive constant that is an exact power of two.
2150 return (int)Value > 0 && isPowerOf2_32(Value);
2151 case 'O': // "O" is the constant zero.
2153 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
2154 return (short)-Value == (int)-Value;
2160 // Handle standard constraint letters.
2161 return TargetLowering::isOperandValidForConstraint(Op, Letter);
2164 /// isLegalAddressImmediate - Return true if the integer value can be used
2165 /// as the offset of the target addressing mode.
2166 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
2167 // PPC allows a sign-extended 16-bit immediate field.
2168 return (V > -(1 << 16) && V < (1 << 16)-1);