1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::MULHU, VT, Expand);
457 setOperationAction(ISD::MULHS, VT, Expand);
458 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
459 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
460 setOperationAction(ISD::UDIVREM, VT, Expand);
461 setOperationAction(ISD::SDIVREM, VT, Expand);
462 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
463 setOperationAction(ISD::FPOW, VT, Expand);
464 setOperationAction(ISD::BSWAP, VT, Expand);
465 setOperationAction(ISD::CTPOP, VT, Expand);
466 setOperationAction(ISD::CTLZ, VT, Expand);
467 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::CTTZ, VT, Expand);
469 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
470 setOperationAction(ISD::VSELECT, VT, Expand);
471 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
473 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
474 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
475 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
476 setTruncStoreAction(VT, InnerVT, Expand);
478 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
479 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
480 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
483 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
484 // with merges, splats, etc.
485 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
487 setOperationAction(ISD::AND , MVT::v4i32, Legal);
488 setOperationAction(ISD::OR , MVT::v4i32, Legal);
489 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
490 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
491 setOperationAction(ISD::SELECT, MVT::v4i32,
492 Subtarget.useCRBits() ? Legal : Expand);
493 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
494 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
495 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
496 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
497 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
498 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
499 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
500 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
501 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
503 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
505 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
506 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
508 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
509 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
511 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
512 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
513 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
516 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
517 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
518 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
520 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
521 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
525 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
526 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
528 // Altivec does not contain unordered floating-point compare instructions
529 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
534 if (Subtarget.hasVSX()) {
535 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
536 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
538 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
540 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
541 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
542 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
544 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
546 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
547 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
549 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
550 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
552 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
553 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
554 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
558 // Share the Altivec comparison restrictions.
559 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
560 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
561 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
562 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
564 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
565 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
567 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
569 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
571 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
572 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
574 // VSX v2i64 only supports non-arithmetic operations.
575 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
576 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
578 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
579 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
580 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
582 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
584 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
585 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
586 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
587 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
589 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
591 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
592 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
593 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
594 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
596 // Vector operation legalization checks the result type of
597 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
598 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
599 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
600 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
601 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
603 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
607 if (Subtarget.has64BitSupport()) {
608 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
609 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
612 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
613 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
614 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
615 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
617 setBooleanContents(ZeroOrOneBooleanContent);
618 // Altivec instructions set fields to all zeros or all ones.
619 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
622 // These libcalls are not available in 32-bit.
623 setLibcallName(RTLIB::SHL_I128, nullptr);
624 setLibcallName(RTLIB::SRL_I128, nullptr);
625 setLibcallName(RTLIB::SRA_I128, nullptr);
629 setStackPointerRegisterToSaveRestore(PPC::X1);
630 setExceptionPointerRegister(PPC::X3);
631 setExceptionSelectorRegister(PPC::X4);
633 setStackPointerRegisterToSaveRestore(PPC::R1);
634 setExceptionPointerRegister(PPC::R3);
635 setExceptionSelectorRegister(PPC::R4);
638 // We have target-specific dag combine patterns for the following nodes:
639 setTargetDAGCombine(ISD::SINT_TO_FP);
640 setTargetDAGCombine(ISD::LOAD);
641 setTargetDAGCombine(ISD::STORE);
642 setTargetDAGCombine(ISD::BR_CC);
643 if (Subtarget.useCRBits())
644 setTargetDAGCombine(ISD::BRCOND);
645 setTargetDAGCombine(ISD::BSWAP);
646 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
648 setTargetDAGCombine(ISD::SIGN_EXTEND);
649 setTargetDAGCombine(ISD::ZERO_EXTEND);
650 setTargetDAGCombine(ISD::ANY_EXTEND);
652 if (Subtarget.useCRBits()) {
653 setTargetDAGCombine(ISD::TRUNCATE);
654 setTargetDAGCombine(ISD::SETCC);
655 setTargetDAGCombine(ISD::SELECT_CC);
658 // Use reciprocal estimates.
659 if (TM.Options.UnsafeFPMath) {
660 setTargetDAGCombine(ISD::FDIV);
661 setTargetDAGCombine(ISD::FSQRT);
664 // Darwin long double math library functions have $LDBL128 appended.
665 if (Subtarget.isDarwin()) {
666 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
667 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
668 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
669 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
670 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
671 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
672 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
673 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
674 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
675 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
678 // With 32 condition bits, we don't need to sink (and duplicate) compares
679 // aggressively in CodeGenPrep.
680 if (Subtarget.useCRBits())
681 setHasMultipleConditionRegisters();
683 setMinFunctionAlignment(2);
684 if (Subtarget.isDarwin())
685 setPrefFunctionAlignment(4);
687 if (isPPC64 && Subtarget.isJITCodeModel())
688 // Temporary workaround for the inability of PPC64 JIT to handle jump
690 setSupportJumpTables(false);
692 setInsertFencesForAtomic(true);
694 if (Subtarget.enableMachineScheduler())
695 setSchedulingPreference(Sched::Source);
697 setSchedulingPreference(Sched::Hybrid);
699 computeRegisterProperties();
701 // The Freescale cores does better with aggressive inlining of memcpy and
702 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
703 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
704 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
705 MaxStoresPerMemset = 32;
706 MaxStoresPerMemsetOptSize = 16;
707 MaxStoresPerMemcpy = 32;
708 MaxStoresPerMemcpyOptSize = 8;
709 MaxStoresPerMemmove = 32;
710 MaxStoresPerMemmoveOptSize = 8;
712 setPrefFunctionAlignment(4);
716 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
717 /// the desired ByVal argument alignment.
718 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
719 unsigned MaxMaxAlign) {
720 if (MaxAlign == MaxMaxAlign)
722 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
723 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
725 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
727 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
728 unsigned EltAlign = 0;
729 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
730 if (EltAlign > MaxAlign)
732 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
733 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
734 unsigned EltAlign = 0;
735 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
736 if (EltAlign > MaxAlign)
738 if (MaxAlign == MaxMaxAlign)
744 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
745 /// function arguments in the caller parameter area.
746 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
747 // Darwin passes everything on 4 byte boundary.
748 if (Subtarget.isDarwin())
751 // 16byte and wider vectors are passed on 16byte boundary.
752 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
753 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
754 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
755 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
759 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
761 default: return nullptr;
762 case PPCISD::FSEL: return "PPCISD::FSEL";
763 case PPCISD::FCFID: return "PPCISD::FCFID";
764 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
765 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
766 case PPCISD::FRE: return "PPCISD::FRE";
767 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
768 case PPCISD::STFIWX: return "PPCISD::STFIWX";
769 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
770 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
771 case PPCISD::VPERM: return "PPCISD::VPERM";
772 case PPCISD::Hi: return "PPCISD::Hi";
773 case PPCISD::Lo: return "PPCISD::Lo";
774 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
775 case PPCISD::LOAD: return "PPCISD::LOAD";
776 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
777 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
778 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
779 case PPCISD::SRL: return "PPCISD::SRL";
780 case PPCISD::SRA: return "PPCISD::SRA";
781 case PPCISD::SHL: return "PPCISD::SHL";
782 case PPCISD::CALL: return "PPCISD::CALL";
783 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
784 case PPCISD::MTCTR: return "PPCISD::MTCTR";
785 case PPCISD::BCTRL: return "PPCISD::BCTRL";
786 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
787 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
788 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
789 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
790 case PPCISD::VCMP: return "PPCISD::VCMP";
791 case PPCISD::VCMPo: return "PPCISD::VCMPo";
792 case PPCISD::LBRX: return "PPCISD::LBRX";
793 case PPCISD::STBRX: return "PPCISD::STBRX";
794 case PPCISD::LARX: return "PPCISD::LARX";
795 case PPCISD::STCX: return "PPCISD::STCX";
796 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
797 case PPCISD::BDNZ: return "PPCISD::BDNZ";
798 case PPCISD::BDZ: return "PPCISD::BDZ";
799 case PPCISD::MFFS: return "PPCISD::MFFS";
800 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
801 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
802 case PPCISD::CR6SET: return "PPCISD::CR6SET";
803 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
804 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
805 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
806 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
807 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
808 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
809 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
810 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
811 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
812 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
813 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
814 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
815 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
816 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
817 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
818 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
819 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
820 case PPCISD::SC: return "PPCISD::SC";
824 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
826 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
827 return VT.changeVectorElementTypeToInteger();
830 //===----------------------------------------------------------------------===//
831 // Node matching predicates, for use by the tblgen matching code.
832 //===----------------------------------------------------------------------===//
834 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
835 static bool isFloatingPointZero(SDValue Op) {
836 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
837 return CFP->getValueAPF().isZero();
838 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
839 // Maybe this has already been legalized into the constant pool?
840 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
841 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
842 return CFP->getValueAPF().isZero();
847 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
848 /// true if Op is undef or if it matches the specified value.
849 static bool isConstantOrUndef(int Op, int Val) {
850 return Op < 0 || Op == Val;
853 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
854 /// VPKUHUM instruction.
855 /// The ShuffleKind distinguishes between big-endian operations with
856 /// two different inputs (0), either-endian operations with two identical
857 /// inputs (1), and little-endian operantion with two different inputs (2).
858 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
859 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
861 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
862 if (ShuffleKind == 0) {
865 for (unsigned i = 0; i != 16; ++i)
866 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
868 } else if (ShuffleKind == 2) {
871 for (unsigned i = 0; i != 16; ++i)
872 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
874 } else if (ShuffleKind == 1) {
875 unsigned j = IsLE ? 0 : 1;
876 for (unsigned i = 0; i != 8; ++i)
877 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
878 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
884 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
885 /// VPKUWUM instruction.
886 /// The ShuffleKind distinguishes between big-endian operations with
887 /// two different inputs (0), either-endian operations with two identical
888 /// inputs (1), and little-endian operantion with two different inputs (2).
889 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
890 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
892 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
893 if (ShuffleKind == 0) {
896 for (unsigned i = 0; i != 16; i += 2)
897 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
898 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
900 } else if (ShuffleKind == 2) {
903 for (unsigned i = 0; i != 16; i += 2)
904 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
905 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
907 } else if (ShuffleKind == 1) {
908 unsigned j = IsLE ? 0 : 2;
909 for (unsigned i = 0; i != 8; i += 2)
910 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
911 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
912 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
913 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
919 /// isVMerge - Common function, used to match vmrg* shuffles.
921 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
922 unsigned LHSStart, unsigned RHSStart) {
923 if (N->getValueType(0) != MVT::v16i8)
925 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
926 "Unsupported merge size!");
928 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
929 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
930 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
931 LHSStart+j+i*UnitSize) ||
932 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
933 RHSStart+j+i*UnitSize))
939 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
940 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
941 /// The ShuffleKind distinguishes between big-endian merges with two
942 /// different inputs (0), either-endian merges with two identical inputs (1),
943 /// and little-endian merges with two different inputs (2). For the latter,
944 /// the input operands are swapped (see PPCInstrAltivec.td).
945 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
946 unsigned ShuffleKind, SelectionDAG &DAG) {
947 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
948 if (ShuffleKind == 1) // unary
949 return isVMerge(N, UnitSize, 0, 0);
950 else if (ShuffleKind == 2) // swapped
951 return isVMerge(N, UnitSize, 0, 16);
955 if (ShuffleKind == 1) // unary
956 return isVMerge(N, UnitSize, 8, 8);
957 else if (ShuffleKind == 0) // normal
958 return isVMerge(N, UnitSize, 8, 24);
964 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
965 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
966 /// The ShuffleKind distinguishes between big-endian merges with two
967 /// different inputs (0), either-endian merges with two identical inputs (1),
968 /// and little-endian merges with two different inputs (2). For the latter,
969 /// the input operands are swapped (see PPCInstrAltivec.td).
970 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
971 unsigned ShuffleKind, SelectionDAG &DAG) {
972 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
973 if (ShuffleKind == 1) // unary
974 return isVMerge(N, UnitSize, 8, 8);
975 else if (ShuffleKind == 2) // swapped
976 return isVMerge(N, UnitSize, 8, 24);
980 if (ShuffleKind == 1) // unary
981 return isVMerge(N, UnitSize, 0, 0);
982 else if (ShuffleKind == 0) // normal
983 return isVMerge(N, UnitSize, 0, 16);
990 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
991 /// amount, otherwise return -1.
992 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
993 if (N->getValueType(0) != MVT::v16i8)
996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
998 // Find the first non-undef value in the shuffle mask.
1000 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1003 if (i == 16) return -1; // all undef.
1005 // Otherwise, check to see if the rest of the elements are consecutively
1006 // numbered from this value.
1007 unsigned ShiftAmt = SVOp->getMaskElt(i);
1008 if (ShiftAmt < i) return -1;
1013 // Check the rest of the elements to see if they are consecutive.
1014 for (++i; i != 16; ++i)
1015 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1018 // Check the rest of the elements to see if they are consecutive.
1019 for (++i; i != 16; ++i)
1020 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1027 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1028 /// specifies a splat of a single element that is suitable for input to
1029 /// VSPLTB/VSPLTH/VSPLTW.
1030 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1031 assert(N->getValueType(0) == MVT::v16i8 &&
1032 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1034 // This is a splat operation if each element of the permute is the same, and
1035 // if the value doesn't reference the second vector.
1036 unsigned ElementBase = N->getMaskElt(0);
1038 // FIXME: Handle UNDEF elements too!
1039 if (ElementBase >= 16)
1042 // Check that the indices are consecutive, in the case of a multi-byte element
1043 // splatted with a v16i8 mask.
1044 for (unsigned i = 1; i != EltSize; ++i)
1045 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1048 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1049 if (N->getMaskElt(i) < 0) continue;
1050 for (unsigned j = 0; j != EltSize; ++j)
1051 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1057 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1059 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1060 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1062 APInt APVal, APUndef;
1066 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1067 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1068 return CFP->getValueAPF().isNegZero();
1073 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1074 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1075 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1076 SelectionDAG &DAG) {
1077 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1078 assert(isSplatShuffleMask(SVOp, EltSize));
1079 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1080 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1082 return SVOp->getMaskElt(0) / EltSize;
1085 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1086 /// by using a vspltis[bhw] instruction of the specified element size, return
1087 /// the constant being splatted. The ByteSize field indicates the number of
1088 /// bytes of each element [124] -> [bhw].
1089 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1090 SDValue OpVal(nullptr, 0);
1092 // If ByteSize of the splat is bigger than the element size of the
1093 // build_vector, then we have a case where we are checking for a splat where
1094 // multiple elements of the buildvector are folded together into a single
1095 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1096 unsigned EltSize = 16/N->getNumOperands();
1097 if (EltSize < ByteSize) {
1098 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1099 SDValue UniquedVals[4];
1100 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1102 // See if all of the elements in the buildvector agree across.
1103 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1104 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1105 // If the element isn't a constant, bail fully out.
1106 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1109 if (!UniquedVals[i&(Multiple-1)].getNode())
1110 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1111 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1112 return SDValue(); // no match.
1115 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1116 // either constant or undef values that are identical for each chunk. See
1117 // if these chunks can form into a larger vspltis*.
1119 // Check to see if all of the leading entries are either 0 or -1. If
1120 // neither, then this won't fit into the immediate field.
1121 bool LeadingZero = true;
1122 bool LeadingOnes = true;
1123 for (unsigned i = 0; i != Multiple-1; ++i) {
1124 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1126 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1127 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1129 // Finally, check the least significant entry.
1131 if (!UniquedVals[Multiple-1].getNode())
1132 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1133 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1135 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1138 if (!UniquedVals[Multiple-1].getNode())
1139 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1140 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1141 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1142 return DAG.getTargetConstant(Val, MVT::i32);
1148 // Check to see if this buildvec has a single non-undef value in its elements.
1149 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1150 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1151 if (!OpVal.getNode())
1152 OpVal = N->getOperand(i);
1153 else if (OpVal != N->getOperand(i))
1157 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1159 unsigned ValSizeInBytes = EltSize;
1161 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1162 Value = CN->getZExtValue();
1163 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1164 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1165 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1168 // If the splat value is larger than the element value, then we can never do
1169 // this splat. The only case that we could fit the replicated bits into our
1170 // immediate field for would be zero, and we prefer to use vxor for it.
1171 if (ValSizeInBytes < ByteSize) return SDValue();
1173 // If the element value is larger than the splat value, cut it in half and
1174 // check to see if the two halves are equal. Continue doing this until we
1175 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1176 while (ValSizeInBytes > ByteSize) {
1177 ValSizeInBytes >>= 1;
1179 // If the top half equals the bottom half, we're still ok.
1180 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1181 (Value & ((1 << (8*ValSizeInBytes))-1)))
1185 // Properly sign extend the value.
1186 int MaskVal = SignExtend32(Value, ByteSize * 8);
1188 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1189 if (MaskVal == 0) return SDValue();
1191 // Finally, if this value fits in a 5 bit sext field, return it
1192 if (SignExtend32<5>(MaskVal) == MaskVal)
1193 return DAG.getTargetConstant(MaskVal, MVT::i32);
1197 //===----------------------------------------------------------------------===//
1198 // Addressing Mode Selection
1199 //===----------------------------------------------------------------------===//
1201 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1202 /// or 64-bit immediate, and if the value can be accurately represented as a
1203 /// sign extension from a 16-bit value. If so, this returns true and the
1205 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1206 if (!isa<ConstantSDNode>(N))
1209 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1210 if (N->getValueType(0) == MVT::i32)
1211 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1213 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1215 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1216 return isIntS16Immediate(Op.getNode(), Imm);
1220 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1221 /// can be represented as an indexed [r+r] operation. Returns false if it
1222 /// can be more efficiently represented with [r+imm].
1223 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1225 SelectionDAG &DAG) const {
1227 if (N.getOpcode() == ISD::ADD) {
1228 if (isIntS16Immediate(N.getOperand(1), imm))
1229 return false; // r+i
1230 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1231 return false; // r+i
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1236 } else if (N.getOpcode() == ISD::OR) {
1237 if (isIntS16Immediate(N.getOperand(1), imm))
1238 return false; // r+i can fold it if we can.
1240 // If this is an or of disjoint bitfields, we can codegen this as an add
1241 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1243 APInt LHSKnownZero, LHSKnownOne;
1244 APInt RHSKnownZero, RHSKnownOne;
1245 DAG.computeKnownBits(N.getOperand(0),
1246 LHSKnownZero, LHSKnownOne);
1248 if (LHSKnownZero.getBoolValue()) {
1249 DAG.computeKnownBits(N.getOperand(1),
1250 RHSKnownZero, RHSKnownOne);
1251 // If all of the bits are known zero on the LHS or RHS, the add won't
1253 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1254 Base = N.getOperand(0);
1255 Index = N.getOperand(1);
1264 // If we happen to be doing an i64 load or store into a stack slot that has
1265 // less than a 4-byte alignment, then the frame-index elimination may need to
1266 // use an indexed load or store instruction (because the offset may not be a
1267 // multiple of 4). The extra register needed to hold the offset comes from the
1268 // register scavenger, and it is possible that the scavenger will need to use
1269 // an emergency spill slot. As a result, we need to make sure that a spill slot
1270 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1272 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1273 // FIXME: This does not handle the LWA case.
1277 // NOTE: We'll exclude negative FIs here, which come from argument
1278 // lowering, because there are no known test cases triggering this problem
1279 // using packed structures (or similar). We can remove this exclusion if
1280 // we find such a test case. The reason why this is so test-case driven is
1281 // because this entire 'fixup' is only to prevent crashes (from the
1282 // register scavenger) on not-really-valid inputs. For example, if we have:
1284 // %b = bitcast i1* %a to i64*
1285 // store i64* a, i64 b
1286 // then the store should really be marked as 'align 1', but is not. If it
1287 // were marked as 'align 1' then the indexed form would have been
1288 // instruction-selected initially, and the problem this 'fixup' is preventing
1289 // won't happen regardless.
1293 MachineFunction &MF = DAG.getMachineFunction();
1294 MachineFrameInfo *MFI = MF.getFrameInfo();
1296 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1300 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1301 FuncInfo->setHasNonRISpills();
1304 /// Returns true if the address N can be represented by a base register plus
1305 /// a signed 16-bit displacement [r+imm], and if it is not better
1306 /// represented as reg+reg. If Aligned is true, only accept displacements
1307 /// suitable for STD and friends, i.e. multiples of 4.
1308 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1311 bool Aligned) const {
1312 // FIXME dl should come from parent load or store, not from address
1314 // If this can be more profitably realized as r+r, fail.
1315 if (SelectAddressRegReg(N, Disp, Base, DAG))
1318 if (N.getOpcode() == ISD::ADD) {
1320 if (isIntS16Immediate(N.getOperand(1), imm) &&
1321 (!Aligned || (imm & 3) == 0)) {
1322 Disp = DAG.getTargetConstant(imm, N.getValueType());
1323 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1324 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1325 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1327 Base = N.getOperand(0);
1329 return true; // [r+i]
1330 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1331 // Match LOAD (ADD (X, Lo(G))).
1332 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1333 && "Cannot handle constant offsets yet!");
1334 Disp = N.getOperand(1).getOperand(0); // The global address.
1335 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1336 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1337 Disp.getOpcode() == ISD::TargetConstantPool ||
1338 Disp.getOpcode() == ISD::TargetJumpTable);
1339 Base = N.getOperand(0);
1340 return true; // [&g+r]
1342 } else if (N.getOpcode() == ISD::OR) {
1344 if (isIntS16Immediate(N.getOperand(1), imm) &&
1345 (!Aligned || (imm & 3) == 0)) {
1346 // If this is an or of disjoint bitfields, we can codegen this as an add
1347 // (for better address arithmetic) if the LHS and RHS of the OR are
1348 // provably disjoint.
1349 APInt LHSKnownZero, LHSKnownOne;
1350 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1352 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1353 // If all of the bits are known zero on the LHS or RHS, the add won't
1355 if (FrameIndexSDNode *FI =
1356 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1357 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1358 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1360 Base = N.getOperand(0);
1362 Disp = DAG.getTargetConstant(imm, N.getValueType());
1366 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1367 // Loading from a constant address.
1369 // If this address fits entirely in a 16-bit sext immediate field, codegen
1372 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1373 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1374 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1375 CN->getValueType(0));
1379 // Handle 32-bit sext immediates with LIS + addr mode.
1380 if ((CN->getValueType(0) == MVT::i32 ||
1381 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1382 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1383 int Addr = (int)CN->getZExtValue();
1385 // Otherwise, break this down into an LIS + disp.
1386 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1388 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1389 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1390 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1395 Disp = DAG.getTargetConstant(0, getPointerTy());
1396 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1397 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1398 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1401 return true; // [r+0]
1404 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1405 /// represented as an indexed [r+r] operation.
1406 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1408 SelectionDAG &DAG) const {
1409 // Check to see if we can easily represent this as an [r+r] address. This
1410 // will fail if it thinks that the address is more profitably represented as
1411 // reg+imm, e.g. where imm = 0.
1412 if (SelectAddressRegReg(N, Base, Index, DAG))
1415 // If the operand is an addition, always emit this as [r+r], since this is
1416 // better (for code size, and execution, as the memop does the add for free)
1417 // than emitting an explicit add.
1418 if (N.getOpcode() == ISD::ADD) {
1419 Base = N.getOperand(0);
1420 Index = N.getOperand(1);
1424 // Otherwise, do it the hard way, using R0 as the base register.
1425 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1431 /// getPreIndexedAddressParts - returns true by value, base pointer and
1432 /// offset pointer and addressing mode by reference if the node's address
1433 /// can be legally represented as pre-indexed load / store address.
1434 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1436 ISD::MemIndexedMode &AM,
1437 SelectionDAG &DAG) const {
1438 if (DisablePPCPreinc) return false;
1444 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1445 Ptr = LD->getBasePtr();
1446 VT = LD->getMemoryVT();
1447 Alignment = LD->getAlignment();
1448 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1449 Ptr = ST->getBasePtr();
1450 VT = ST->getMemoryVT();
1451 Alignment = ST->getAlignment();
1456 // PowerPC doesn't have preinc load/store instructions for vectors.
1460 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1462 // Common code will reject creating a pre-inc form if the base pointer
1463 // is a frame index, or if N is a store and the base pointer is either
1464 // the same as or a predecessor of the value being stored. Check for
1465 // those situations here, and try with swapped Base/Offset instead.
1468 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1471 SDValue Val = cast<StoreSDNode>(N)->getValue();
1472 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1477 std::swap(Base, Offset);
1483 // LDU/STU can only handle immediates that are a multiple of 4.
1484 if (VT != MVT::i64) {
1485 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1488 // LDU/STU need an address with at least 4-byte alignment.
1492 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1496 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1497 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1498 // sext i32 to i64 when addr mode is r+i.
1499 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1500 LD->getExtensionType() == ISD::SEXTLOAD &&
1501 isa<ConstantSDNode>(Offset))
1509 //===----------------------------------------------------------------------===//
1510 // LowerOperation implementation
1511 //===----------------------------------------------------------------------===//
1513 /// GetLabelAccessInfo - Return true if we should reference labels using a
1514 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1515 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1516 unsigned &LoOpFlags,
1517 const GlobalValue *GV = nullptr) {
1518 HiOpFlags = PPCII::MO_HA;
1519 LoOpFlags = PPCII::MO_LO;
1521 // Don't use the pic base if not in PIC relocation model.
1522 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1525 HiOpFlags |= PPCII::MO_PIC_FLAG;
1526 LoOpFlags |= PPCII::MO_PIC_FLAG;
1529 // If this is a reference to a global value that requires a non-lazy-ptr, make
1530 // sure that instruction lowering adds it.
1531 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1532 HiOpFlags |= PPCII::MO_NLP_FLAG;
1533 LoOpFlags |= PPCII::MO_NLP_FLAG;
1535 if (GV->hasHiddenVisibility()) {
1536 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1537 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1544 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1545 SelectionDAG &DAG) {
1546 EVT PtrVT = HiPart.getValueType();
1547 SDValue Zero = DAG.getConstant(0, PtrVT);
1550 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1551 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1553 // With PIC, the first instruction is actually "GR+hi(&G)".
1555 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1556 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1558 // Generate non-pic code that has direct accesses to the constant pool.
1559 // The address of the global is just (hi(&g)+lo(&g)).
1560 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1563 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1564 SelectionDAG &DAG) const {
1565 EVT PtrVT = Op.getValueType();
1566 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1567 const Constant *C = CP->getConstVal();
1569 // 64-bit SVR4 ABI code is always position-independent.
1570 // The actual address of the GlobalValue is stored in the TOC.
1571 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1572 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1573 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1574 DAG.getRegister(PPC::X2, MVT::i64));
1577 unsigned MOHiFlag, MOLoFlag;
1578 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1580 if (isPIC && Subtarget.isSVR4ABI()) {
1581 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1582 PPCII::MO_PIC_FLAG);
1584 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1585 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1589 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1591 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1592 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1595 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1596 EVT PtrVT = Op.getValueType();
1597 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1599 // 64-bit SVR4 ABI code is always position-independent.
1600 // The actual address of the GlobalValue is stored in the TOC.
1601 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1602 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1603 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1604 DAG.getRegister(PPC::X2, MVT::i64));
1607 unsigned MOHiFlag, MOLoFlag;
1608 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1610 if (isPIC && Subtarget.isSVR4ABI()) {
1611 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1612 PPCII::MO_PIC_FLAG);
1614 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1615 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1618 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1619 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1620 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1623 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1624 SelectionDAG &DAG) const {
1625 EVT PtrVT = Op.getValueType();
1627 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1629 unsigned MOHiFlag, MOLoFlag;
1630 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1631 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1632 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1633 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1636 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1637 SelectionDAG &DAG) const {
1639 // FIXME: TLS addresses currently use medium model code sequences,
1640 // which is the most useful form. Eventually support for small and
1641 // large models could be added if users need it, at the cost of
1642 // additional complexity.
1643 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1645 const GlobalValue *GV = GA->getGlobal();
1646 EVT PtrVT = getPointerTy();
1647 bool is64bit = Subtarget.isPPC64();
1649 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1651 if (Model == TLSModel::LocalExec) {
1652 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1653 PPCII::MO_TPREL_HA);
1654 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1655 PPCII::MO_TPREL_LO);
1656 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1657 is64bit ? MVT::i64 : MVT::i32);
1658 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1659 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1662 if (Model == TLSModel::InitialExec) {
1663 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1664 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1668 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1669 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1670 PtrVT, GOTReg, TGA);
1672 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1673 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1674 PtrVT, TGA, GOTPtr);
1675 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1678 if (Model == TLSModel::GeneralDynamic) {
1679 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1682 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1683 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1686 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1688 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1691 // We need a chain node, and don't have one handy. The underlying
1692 // call has no side effects, so using the function entry node
1694 SDValue Chain = DAG.getEntryNode();
1695 Chain = DAG.getCopyToReg(Chain, dl,
1696 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1697 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1698 is64bit ? MVT::i64 : MVT::i32);
1699 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1700 PtrVT, ParmReg, TGA);
1701 // The return value from GET_TLS_ADDR really is in X3 already, but
1702 // some hacks are needed here to tie everything together. The extra
1703 // copies dissolve during subsequent transforms.
1704 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1705 return DAG.getCopyFromReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, PtrVT);
1708 if (Model == TLSModel::LocalDynamic) {
1709 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1712 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1713 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1716 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1718 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1721 // We need a chain node, and don't have one handy. The underlying
1722 // call has no side effects, so using the function entry node
1724 SDValue Chain = DAG.getEntryNode();
1725 Chain = DAG.getCopyToReg(Chain, dl,
1726 is64bit ? PPC::X3 : PPC::R3, GOTEntry);
1727 SDValue ParmReg = DAG.getRegister(is64bit ? PPC::X3 : PPC::R3,
1728 is64bit ? MVT::i64 : MVT::i32);
1729 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1730 PtrVT, ParmReg, TGA);
1731 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1732 // some hacks are needed here to tie everything together. The extra
1733 // copies dissolve during subsequent transforms.
1734 Chain = DAG.getCopyToReg(Chain, dl, is64bit ? PPC::X3 : PPC::R3, TLSAddr);
1735 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1736 Chain, ParmReg, TGA);
1737 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1740 llvm_unreachable("Unknown TLS model!");
1743 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1744 SelectionDAG &DAG) const {
1745 EVT PtrVT = Op.getValueType();
1746 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1748 const GlobalValue *GV = GSDN->getGlobal();
1750 // 64-bit SVR4 ABI code is always position-independent.
1751 // The actual address of the GlobalValue is stored in the TOC.
1752 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1753 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1754 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1755 DAG.getRegister(PPC::X2, MVT::i64));
1758 unsigned MOHiFlag, MOLoFlag;
1759 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1761 if (isPIC && Subtarget.isSVR4ABI()) {
1762 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1764 PPCII::MO_PIC_FLAG);
1765 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1766 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1770 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1772 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1774 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1776 // If the global reference is actually to a non-lazy-pointer, we have to do an
1777 // extra load to get the address of the global.
1778 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1779 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1780 false, false, false, 0);
1784 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1785 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1788 if (Op.getValueType() == MVT::v2i64) {
1789 // When the operands themselves are v2i64 values, we need to do something
1790 // special because VSX has no underlying comparison operations for these.
1791 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1792 // Equality can be handled by casting to the legal type for Altivec
1793 // comparisons, everything else needs to be expanded.
1794 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1795 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1796 DAG.getSetCC(dl, MVT::v4i32,
1797 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1798 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1805 // We handle most of these in the usual way.
1809 // If we're comparing for equality to zero, expose the fact that this is
1810 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1811 // fold the new nodes.
1812 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1813 if (C->isNullValue() && CC == ISD::SETEQ) {
1814 EVT VT = Op.getOperand(0).getValueType();
1815 SDValue Zext = Op.getOperand(0);
1816 if (VT.bitsLT(MVT::i32)) {
1818 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1820 unsigned Log2b = Log2_32(VT.getSizeInBits());
1821 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1822 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1823 DAG.getConstant(Log2b, MVT::i32));
1824 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1826 // Leave comparisons against 0 and -1 alone for now, since they're usually
1827 // optimized. FIXME: revisit this when we can custom lower all setcc
1829 if (C->isAllOnesValue() || C->isNullValue())
1833 // If we have an integer seteq/setne, turn it into a compare against zero
1834 // by xor'ing the rhs with the lhs, which is faster than setting a
1835 // condition register, reading it back out, and masking the correct bit. The
1836 // normal approach here uses sub to do this instead of xor. Using xor exposes
1837 // the result to other bit-twiddling opportunities.
1838 EVT LHSVT = Op.getOperand(0).getValueType();
1839 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1840 EVT VT = Op.getValueType();
1841 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1843 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1848 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1849 const PPCSubtarget &Subtarget) const {
1850 SDNode *Node = Op.getNode();
1851 EVT VT = Node->getValueType(0);
1852 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1853 SDValue InChain = Node->getOperand(0);
1854 SDValue VAListPtr = Node->getOperand(1);
1855 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1858 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1861 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1862 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1863 false, false, false, 0);
1864 InChain = GprIndex.getValue(1);
1866 if (VT == MVT::i64) {
1867 // Check if GprIndex is even
1868 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1869 DAG.getConstant(1, MVT::i32));
1870 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1871 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1872 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1873 DAG.getConstant(1, MVT::i32));
1874 // Align GprIndex to be even if it isn't
1875 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1879 // fpr index is 1 byte after gpr
1880 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1881 DAG.getConstant(1, MVT::i32));
1884 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1885 FprPtr, MachinePointerInfo(SV), MVT::i8,
1886 false, false, false, 0);
1887 InChain = FprIndex.getValue(1);
1889 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1890 DAG.getConstant(8, MVT::i32));
1892 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1893 DAG.getConstant(4, MVT::i32));
1896 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1897 MachinePointerInfo(), false, false,
1899 InChain = OverflowArea.getValue(1);
1901 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1902 MachinePointerInfo(), false, false,
1904 InChain = RegSaveArea.getValue(1);
1906 // select overflow_area if index > 8
1907 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1908 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1910 // adjustment constant gpr_index * 4/8
1911 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1912 VT.isInteger() ? GprIndex : FprIndex,
1913 DAG.getConstant(VT.isInteger() ? 4 : 8,
1916 // OurReg = RegSaveArea + RegConstant
1917 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1920 // Floating types are 32 bytes into RegSaveArea
1921 if (VT.isFloatingPoint())
1922 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1923 DAG.getConstant(32, MVT::i32));
1925 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1926 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1927 VT.isInteger() ? GprIndex : FprIndex,
1928 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1931 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1932 VT.isInteger() ? VAListPtr : FprPtr,
1933 MachinePointerInfo(SV),
1934 MVT::i8, false, false, 0);
1936 // determine if we should load from reg_save_area or overflow_area
1937 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1939 // increase overflow_area by 4/8 if gpr/fpr > 8
1940 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1941 DAG.getConstant(VT.isInteger() ? 4 : 8,
1944 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1947 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1949 MachinePointerInfo(),
1950 MVT::i32, false, false, 0);
1952 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1953 false, false, false, 0);
1956 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1957 const PPCSubtarget &Subtarget) const {
1958 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1960 // We have to copy the entire va_list struct:
1961 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1962 return DAG.getMemcpy(Op.getOperand(0), Op,
1963 Op.getOperand(1), Op.getOperand(2),
1964 DAG.getConstant(12, MVT::i32), 8, false, true,
1965 MachinePointerInfo(), MachinePointerInfo());
1968 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1969 SelectionDAG &DAG) const {
1970 return Op.getOperand(0);
1973 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1974 SelectionDAG &DAG) const {
1975 SDValue Chain = Op.getOperand(0);
1976 SDValue Trmp = Op.getOperand(1); // trampoline
1977 SDValue FPtr = Op.getOperand(2); // nested function
1978 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1981 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1982 bool isPPC64 = (PtrVT == MVT::i64);
1984 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1987 TargetLowering::ArgListTy Args;
1988 TargetLowering::ArgListEntry Entry;
1990 Entry.Ty = IntPtrTy;
1991 Entry.Node = Trmp; Args.push_back(Entry);
1993 // TrampSize == (isPPC64 ? 48 : 40);
1994 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1995 isPPC64 ? MVT::i64 : MVT::i32);
1996 Args.push_back(Entry);
1998 Entry.Node = FPtr; Args.push_back(Entry);
1999 Entry.Node = Nest; Args.push_back(Entry);
2001 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2002 TargetLowering::CallLoweringInfo CLI(DAG);
2003 CLI.setDebugLoc(dl).setChain(Chain)
2004 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2005 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2006 std::move(Args), 0);
2008 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2009 return CallResult.second;
2012 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2013 const PPCSubtarget &Subtarget) const {
2014 MachineFunction &MF = DAG.getMachineFunction();
2015 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2019 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2020 // vastart just stores the address of the VarArgsFrameIndex slot into the
2021 // memory location argument.
2022 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2023 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2024 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2025 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2026 MachinePointerInfo(SV),
2030 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2031 // We suppose the given va_list is already allocated.
2034 // char gpr; /* index into the array of 8 GPRs
2035 // * stored in the register save area
2036 // * gpr=0 corresponds to r3,
2037 // * gpr=1 to r4, etc.
2039 // char fpr; /* index into the array of 8 FPRs
2040 // * stored in the register save area
2041 // * fpr=0 corresponds to f1,
2042 // * fpr=1 to f2, etc.
2044 // char *overflow_arg_area;
2045 // /* location on stack that holds
2046 // * the next overflow argument
2048 // char *reg_save_area;
2049 // /* where r3:r10 and f1:f8 (if saved)
2055 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2056 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2059 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2061 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2063 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2066 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2067 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2069 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2070 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2072 uint64_t FPROffset = 1;
2073 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2075 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2077 // Store first byte : number of int regs
2078 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2080 MachinePointerInfo(SV),
2081 MVT::i8, false, false, 0);
2082 uint64_t nextOffset = FPROffset;
2083 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2086 // Store second byte : number of float regs
2087 SDValue secondStore =
2088 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2089 MachinePointerInfo(SV, nextOffset), MVT::i8,
2091 nextOffset += StackOffset;
2092 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2094 // Store second word : arguments given on stack
2095 SDValue thirdStore =
2096 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2097 MachinePointerInfo(SV, nextOffset),
2099 nextOffset += FrameOffset;
2100 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2102 // Store third word : arguments given in registers
2103 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2104 MachinePointerInfo(SV, nextOffset),
2109 #include "PPCGenCallingConv.inc"
2111 // Function whose sole purpose is to kill compiler warnings
2112 // stemming from unused functions included from PPCGenCallingConv.inc.
2113 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2114 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2117 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2118 CCValAssign::LocInfo &LocInfo,
2119 ISD::ArgFlagsTy &ArgFlags,
2124 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2126 CCValAssign::LocInfo &LocInfo,
2127 ISD::ArgFlagsTy &ArgFlags,
2129 static const MCPhysReg ArgRegs[] = {
2130 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2131 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2133 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2135 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2137 // Skip one register if the first unallocated register has an even register
2138 // number and there are still argument registers available which have not been
2139 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2140 // need to skip a register if RegNum is odd.
2141 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2142 State.AllocateReg(ArgRegs[RegNum]);
2145 // Always return false here, as this function only makes sure that the first
2146 // unallocated register has an odd register number and does not actually
2147 // allocate a register for the current argument.
2151 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2153 CCValAssign::LocInfo &LocInfo,
2154 ISD::ArgFlagsTy &ArgFlags,
2156 static const MCPhysReg ArgRegs[] = {
2157 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2161 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2163 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2165 // If there is only one Floating-point register left we need to put both f64
2166 // values of a split ppc_fp128 value on the stack.
2167 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2168 State.AllocateReg(ArgRegs[RegNum]);
2171 // Always return false here, as this function only makes sure that the two f64
2172 // values a ppc_fp128 value is split into are both passed in registers or both
2173 // passed on the stack and does not actually allocate a register for the
2174 // current argument.
2178 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2180 static const MCPhysReg *GetFPR() {
2181 static const MCPhysReg FPR[] = {
2182 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2183 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2189 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2191 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2192 unsigned PtrByteSize) {
2193 unsigned ArgSize = ArgVT.getStoreSize();
2194 if (Flags.isByVal())
2195 ArgSize = Flags.getByValSize();
2197 // Round up to multiples of the pointer size, except for array members,
2198 // which are always packed.
2199 if (!Flags.isInConsecutiveRegs())
2200 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2205 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2207 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2208 ISD::ArgFlagsTy Flags,
2209 unsigned PtrByteSize) {
2210 unsigned Align = PtrByteSize;
2212 // Altivec parameters are padded to a 16 byte boundary.
2213 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2214 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2215 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2218 // ByVal parameters are aligned as requested.
2219 if (Flags.isByVal()) {
2220 unsigned BVAlign = Flags.getByValAlign();
2221 if (BVAlign > PtrByteSize) {
2222 if (BVAlign % PtrByteSize != 0)
2224 "ByVal alignment is not a multiple of the pointer size");
2230 // Array members are always packed to their original alignment.
2231 if (Flags.isInConsecutiveRegs()) {
2232 // If the array member was split into multiple registers, the first
2233 // needs to be aligned to the size of the full type. (Except for
2234 // ppcf128, which is only aligned as its f64 components.)
2235 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2236 Align = OrigVT.getStoreSize();
2238 Align = ArgVT.getStoreSize();
2244 /// CalculateStackSlotUsed - Return whether this argument will use its
2245 /// stack slot (instead of being passed in registers). ArgOffset,
2246 /// AvailableFPRs, and AvailableVRs must hold the current argument
2247 /// position, and will be updated to account for this argument.
2248 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2249 ISD::ArgFlagsTy Flags,
2250 unsigned PtrByteSize,
2251 unsigned LinkageSize,
2252 unsigned ParamAreaSize,
2253 unsigned &ArgOffset,
2254 unsigned &AvailableFPRs,
2255 unsigned &AvailableVRs) {
2256 bool UseMemory = false;
2258 // Respect alignment of argument on the stack.
2260 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2261 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2262 // If there's no space left in the argument save area, we must
2263 // use memory (this check also catches zero-sized arguments).
2264 if (ArgOffset >= LinkageSize + ParamAreaSize)
2267 // Allocate argument on the stack.
2268 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2269 if (Flags.isInConsecutiveRegsLast())
2270 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2271 // If we overran the argument save area, we must use memory
2272 // (this check catches arguments passed partially in memory)
2273 if (ArgOffset > LinkageSize + ParamAreaSize)
2276 // However, if the argument is actually passed in an FPR or a VR,
2277 // we don't use memory after all.
2278 if (!Flags.isByVal()) {
2279 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2280 if (AvailableFPRs > 0) {
2284 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2285 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2286 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2287 if (AvailableVRs > 0) {
2296 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2297 /// ensure minimum alignment required for target.
2298 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2299 unsigned NumBytes) {
2300 unsigned TargetAlign =
2301 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2302 unsigned AlignMask = TargetAlign - 1;
2303 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2308 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2309 CallingConv::ID CallConv, bool isVarArg,
2310 const SmallVectorImpl<ISD::InputArg>
2312 SDLoc dl, SelectionDAG &DAG,
2313 SmallVectorImpl<SDValue> &InVals)
2315 if (Subtarget.isSVR4ABI()) {
2316 if (Subtarget.isPPC64())
2317 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2320 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2323 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2329 PPCTargetLowering::LowerFormalArguments_32SVR4(
2331 CallingConv::ID CallConv, bool isVarArg,
2332 const SmallVectorImpl<ISD::InputArg>
2334 SDLoc dl, SelectionDAG &DAG,
2335 SmallVectorImpl<SDValue> &InVals) const {
2337 // 32-bit SVR4 ABI Stack Frame Layout:
2338 // +-----------------------------------+
2339 // +--> | Back chain |
2340 // | +-----------------------------------+
2341 // | | Floating-point register save area |
2342 // | +-----------------------------------+
2343 // | | General register save area |
2344 // | +-----------------------------------+
2345 // | | CR save word |
2346 // | +-----------------------------------+
2347 // | | VRSAVE save word |
2348 // | +-----------------------------------+
2349 // | | Alignment padding |
2350 // | +-----------------------------------+
2351 // | | Vector register save area |
2352 // | +-----------------------------------+
2353 // | | Local variable space |
2354 // | +-----------------------------------+
2355 // | | Parameter list area |
2356 // | +-----------------------------------+
2357 // | | LR save word |
2358 // | +-----------------------------------+
2359 // SP--> +--- | Back chain |
2360 // +-----------------------------------+
2363 // System V Application Binary Interface PowerPC Processor Supplement
2364 // AltiVec Technology Programming Interface Manual
2366 MachineFunction &MF = DAG.getMachineFunction();
2367 MachineFrameInfo *MFI = MF.getFrameInfo();
2368 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2370 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2371 // Potential tail calls could cause overwriting of argument stack slots.
2372 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2373 (CallConv == CallingConv::Fast));
2374 unsigned PtrByteSize = 4;
2376 // Assign locations to all of the incoming arguments.
2377 SmallVector<CCValAssign, 16> ArgLocs;
2378 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2379 getTargetMachine(), ArgLocs, *DAG.getContext());
2381 // Reserve space for the linkage area on the stack.
2382 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2383 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2385 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2387 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2388 CCValAssign &VA = ArgLocs[i];
2390 // Arguments stored in registers.
2391 if (VA.isRegLoc()) {
2392 const TargetRegisterClass *RC;
2393 EVT ValVT = VA.getValVT();
2395 switch (ValVT.getSimpleVT().SimpleTy) {
2397 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2400 RC = &PPC::GPRCRegClass;
2403 RC = &PPC::F4RCRegClass;
2406 if (Subtarget.hasVSX())
2407 RC = &PPC::VSFRCRegClass;
2409 RC = &PPC::F8RCRegClass;
2415 RC = &PPC::VRRCRegClass;
2419 RC = &PPC::VSHRCRegClass;
2423 // Transform the arguments stored in physical registers into virtual ones.
2424 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2425 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2426 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2428 if (ValVT == MVT::i1)
2429 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2431 InVals.push_back(ArgValue);
2433 // Argument stored in memory.
2434 assert(VA.isMemLoc());
2436 unsigned ArgSize = VA.getLocVT().getStoreSize();
2437 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2440 // Create load nodes to retrieve arguments from the stack.
2441 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2442 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2443 MachinePointerInfo(),
2444 false, false, false, 0));
2448 // Assign locations to all of the incoming aggregate by value arguments.
2449 // Aggregates passed by value are stored in the local variable space of the
2450 // caller's stack frame, right above the parameter list area.
2451 SmallVector<CCValAssign, 16> ByValArgLocs;
2452 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2453 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2455 // Reserve stack space for the allocations in CCInfo.
2456 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2458 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2460 // Area that is at least reserved in the caller of this function.
2461 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2462 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2464 // Set the size that is at least reserved in caller of this function. Tail
2465 // call optimized function's reserved stack space needs to be aligned so that
2466 // taking the difference between two stack areas will result in an aligned
2468 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2469 FuncInfo->setMinReservedArea(MinReservedArea);
2471 SmallVector<SDValue, 8> MemOps;
2473 // If the function takes variable number of arguments, make a frame index for
2474 // the start of the first vararg value... for expansion of llvm.va_start.
2476 static const MCPhysReg GPArgRegs[] = {
2477 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2478 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2480 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2482 static const MCPhysReg FPArgRegs[] = {
2483 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2486 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2488 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2490 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2493 // Make room for NumGPArgRegs and NumFPArgRegs.
2494 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2495 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2497 FuncInfo->setVarArgsStackOffset(
2498 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2499 CCInfo.getNextStackOffset(), true));
2501 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2502 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2504 // The fixed integer arguments of a variadic function are stored to the
2505 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2506 // the result of va_next.
2507 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2508 // Get an existing live-in vreg, or add a new one.
2509 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2511 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2513 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2514 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2515 MachinePointerInfo(), false, false, 0);
2516 MemOps.push_back(Store);
2517 // Increment the address by four for the next argument to store
2518 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2519 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2522 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2524 // The double arguments are stored to the VarArgsFrameIndex
2526 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2527 // Get an existing live-in vreg, or add a new one.
2528 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2530 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2532 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2533 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2534 MachinePointerInfo(), false, false, 0);
2535 MemOps.push_back(Store);
2536 // Increment the address by eight for the next argument to store
2537 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2539 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2543 if (!MemOps.empty())
2544 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2549 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2550 // value to MVT::i64 and then truncate to the correct register size.
2552 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2553 SelectionDAG &DAG, SDValue ArgVal,
2556 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2557 DAG.getValueType(ObjectVT));
2558 else if (Flags.isZExt())
2559 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2560 DAG.getValueType(ObjectVT));
2562 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2566 PPCTargetLowering::LowerFormalArguments_64SVR4(
2568 CallingConv::ID CallConv, bool isVarArg,
2569 const SmallVectorImpl<ISD::InputArg>
2571 SDLoc dl, SelectionDAG &DAG,
2572 SmallVectorImpl<SDValue> &InVals) const {
2573 // TODO: add description of PPC stack frame format, or at least some docs.
2575 bool isELFv2ABI = Subtarget.isELFv2ABI();
2576 bool isLittleEndian = Subtarget.isLittleEndian();
2577 MachineFunction &MF = DAG.getMachineFunction();
2578 MachineFrameInfo *MFI = MF.getFrameInfo();
2579 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2581 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2582 // Potential tail calls could cause overwriting of argument stack slots.
2583 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2584 (CallConv == CallingConv::Fast));
2585 unsigned PtrByteSize = 8;
2587 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2590 static const MCPhysReg GPR[] = {
2591 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2592 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2595 static const MCPhysReg *FPR = GetFPR();
2597 static const MCPhysReg VR[] = {
2598 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2599 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2601 static const MCPhysReg VSRH[] = {
2602 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2603 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2606 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2607 const unsigned Num_FPR_Regs = 13;
2608 const unsigned Num_VR_Regs = array_lengthof(VR);
2610 // Do a first pass over the arguments to determine whether the ABI
2611 // guarantees that our caller has allocated the parameter save area
2612 // on its stack frame. In the ELFv1 ABI, this is always the case;
2613 // in the ELFv2 ABI, it is true if this is a vararg function or if
2614 // any parameter is located in a stack slot.
2616 bool HasParameterArea = !isELFv2ABI || isVarArg;
2617 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2618 unsigned NumBytes = LinkageSize;
2619 unsigned AvailableFPRs = Num_FPR_Regs;
2620 unsigned AvailableVRs = Num_VR_Regs;
2621 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2622 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2623 PtrByteSize, LinkageSize, ParamAreaSize,
2624 NumBytes, AvailableFPRs, AvailableVRs))
2625 HasParameterArea = true;
2627 // Add DAG nodes to load the arguments or copy them out of registers. On
2628 // entry to a function on PPC, the arguments start after the linkage area,
2629 // although the first ones are often in registers.
2631 unsigned ArgOffset = LinkageSize;
2632 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2633 SmallVector<SDValue, 8> MemOps;
2634 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2635 unsigned CurArgIdx = 0;
2636 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2638 bool needsLoad = false;
2639 EVT ObjectVT = Ins[ArgNo].VT;
2640 EVT OrigVT = Ins[ArgNo].ArgVT;
2641 unsigned ObjSize = ObjectVT.getStoreSize();
2642 unsigned ArgSize = ObjSize;
2643 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2644 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2645 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2647 /* Respect alignment of argument on the stack. */
2649 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2650 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2651 unsigned CurArgOffset = ArgOffset;
2653 /* Compute GPR index associated with argument offset. */
2654 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2655 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2657 // FIXME the codegen can be much improved in some cases.
2658 // We do not have to keep everything in memory.
2659 if (Flags.isByVal()) {
2660 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2661 ObjSize = Flags.getByValSize();
2662 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2663 // Empty aggregate parameters do not take up registers. Examples:
2667 // etc. However, we have to provide a place-holder in InVals, so
2668 // pretend we have an 8-byte item at the current address for that
2671 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2672 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2673 InVals.push_back(FIN);
2677 // Create a stack object covering all stack doublewords occupied
2678 // by the argument. If the argument is (fully or partially) on
2679 // the stack, or if the argument is fully in registers but the
2680 // caller has allocated the parameter save anyway, we can refer
2681 // directly to the caller's stack frame. Otherwise, create a
2682 // local copy in our own frame.
2684 if (HasParameterArea ||
2685 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2686 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false);
2688 FI = MFI->CreateStackObject(ArgSize, Align, false);
2689 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2691 // Handle aggregates smaller than 8 bytes.
2692 if (ObjSize < PtrByteSize) {
2693 // The value of the object is its address, which differs from the
2694 // address of the enclosing doubleword on big-endian systems.
2696 if (!isLittleEndian) {
2697 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2698 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2700 InVals.push_back(Arg);
2702 if (GPR_idx != Num_GPR_Regs) {
2703 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2704 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2707 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2708 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2709 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2710 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2711 MachinePointerInfo(FuncArg),
2712 ObjType, false, false, 0);
2714 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2715 // store the whole register as-is to the parameter save area
2717 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2718 MachinePointerInfo(FuncArg),
2722 MemOps.push_back(Store);
2724 // Whether we copied from a register or not, advance the offset
2725 // into the parameter save area by a full doubleword.
2726 ArgOffset += PtrByteSize;
2730 // The value of the object is its address, which is the address of
2731 // its first stack doubleword.
2732 InVals.push_back(FIN);
2734 // Store whatever pieces of the object are in registers to memory.
2735 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2736 if (GPR_idx == Num_GPR_Regs)
2739 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2740 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2743 SDValue Off = DAG.getConstant(j, PtrVT);
2744 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2746 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2747 MachinePointerInfo(FuncArg, j),
2749 MemOps.push_back(Store);
2752 ArgOffset += ArgSize;
2756 switch (ObjectVT.getSimpleVT().SimpleTy) {
2757 default: llvm_unreachable("Unhandled argument type!");
2761 // These can be scalar arguments or elements of an integer array type
2762 // passed directly. Clang may use those instead of "byval" aggregate
2763 // types to avoid forcing arguments to memory unnecessarily.
2764 if (GPR_idx != Num_GPR_Regs) {
2765 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2766 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2768 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2769 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2770 // value to MVT::i64 and then truncate to the correct register size.
2771 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2774 ArgSize = PtrByteSize;
2781 // These can be scalar arguments or elements of a float array type
2782 // passed directly. The latter are used to implement ELFv2 homogenous
2783 // float aggregates.
2784 if (FPR_idx != Num_FPR_Regs) {
2787 if (ObjectVT == MVT::f32)
2788 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2790 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2791 &PPC::VSFRCRegClass :
2792 &PPC::F8RCRegClass);
2794 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2796 } else if (GPR_idx != Num_GPR_Regs) {
2797 // This can only ever happen in the presence of f32 array types,
2798 // since otherwise we never run out of FPRs before running out
2800 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2801 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2803 if (ObjectVT == MVT::f32) {
2804 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2805 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2806 DAG.getConstant(32, MVT::i32));
2807 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2810 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2815 // When passing an array of floats, the array occupies consecutive
2816 // space in the argument area; only round up to the next doubleword
2817 // at the end of the array. Otherwise, each float takes 8 bytes.
2818 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2819 ArgOffset += ArgSize;
2820 if (Flags.isInConsecutiveRegsLast())
2821 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2829 // These can be scalar arguments or elements of a vector array type
2830 // passed directly. The latter are used to implement ELFv2 homogenous
2831 // vector aggregates.
2832 if (VR_idx != Num_VR_Regs) {
2833 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2834 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2835 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2836 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2845 // We need to load the argument to a virtual register if we determined
2846 // above that we ran out of physical registers of the appropriate type.
2848 if (ObjSize < ArgSize && !isLittleEndian)
2849 CurArgOffset += ArgSize - ObjSize;
2850 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2851 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2852 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2853 false, false, false, 0);
2856 InVals.push_back(ArgVal);
2859 // Area that is at least reserved in the caller of this function.
2860 unsigned MinReservedArea;
2861 if (HasParameterArea)
2862 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2864 MinReservedArea = LinkageSize;
2866 // Set the size that is at least reserved in caller of this function. Tail
2867 // call optimized functions' reserved stack space needs to be aligned so that
2868 // taking the difference between two stack areas will result in an aligned
2870 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2871 FuncInfo->setMinReservedArea(MinReservedArea);
2873 // If the function takes variable number of arguments, make a frame index for
2874 // the start of the first vararg value... for expansion of llvm.va_start.
2876 int Depth = ArgOffset;
2878 FuncInfo->setVarArgsFrameIndex(
2879 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2880 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2882 // If this function is vararg, store any remaining integer argument regs
2883 // to their spots on the stack so that they may be loaded by deferencing the
2884 // result of va_next.
2885 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2886 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2887 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2888 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2889 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2890 MachinePointerInfo(), false, false, 0);
2891 MemOps.push_back(Store);
2892 // Increment the address by four for the next argument to store
2893 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2894 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2898 if (!MemOps.empty())
2899 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2905 PPCTargetLowering::LowerFormalArguments_Darwin(
2907 CallingConv::ID CallConv, bool isVarArg,
2908 const SmallVectorImpl<ISD::InputArg>
2910 SDLoc dl, SelectionDAG &DAG,
2911 SmallVectorImpl<SDValue> &InVals) const {
2912 // TODO: add description of PPC stack frame format, or at least some docs.
2914 MachineFunction &MF = DAG.getMachineFunction();
2915 MachineFrameInfo *MFI = MF.getFrameInfo();
2916 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2918 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2919 bool isPPC64 = PtrVT == MVT::i64;
2920 // Potential tail calls could cause overwriting of argument stack slots.
2921 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2922 (CallConv == CallingConv::Fast));
2923 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2925 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2927 unsigned ArgOffset = LinkageSize;
2928 // Area that is at least reserved in caller of this function.
2929 unsigned MinReservedArea = ArgOffset;
2931 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2932 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2933 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2935 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2936 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2937 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2940 static const MCPhysReg *FPR = GetFPR();
2942 static const MCPhysReg VR[] = {
2943 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2944 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2947 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2948 const unsigned Num_FPR_Regs = 13;
2949 const unsigned Num_VR_Regs = array_lengthof( VR);
2951 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2953 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2955 // In 32-bit non-varargs functions, the stack space for vectors is after the
2956 // stack space for non-vectors. We do not use this space unless we have
2957 // too many vectors to fit in registers, something that only occurs in
2958 // constructed examples:), but we have to walk the arglist to figure
2959 // that out...for the pathological case, compute VecArgOffset as the
2960 // start of the vector parameter area. Computing VecArgOffset is the
2961 // entire point of the following loop.
2962 unsigned VecArgOffset = ArgOffset;
2963 if (!isVarArg && !isPPC64) {
2964 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2966 EVT ObjectVT = Ins[ArgNo].VT;
2967 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2969 if (Flags.isByVal()) {
2970 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2971 unsigned ObjSize = Flags.getByValSize();
2973 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2974 VecArgOffset += ArgSize;
2978 switch(ObjectVT.getSimpleVT().SimpleTy) {
2979 default: llvm_unreachable("Unhandled argument type!");
2985 case MVT::i64: // PPC64
2987 // FIXME: We are guaranteed to be !isPPC64 at this point.
2988 // Does MVT::i64 apply?
2995 // Nothing to do, we're only looking at Nonvector args here.
3000 // We've found where the vector parameter area in memory is. Skip the
3001 // first 12 parameters; these don't use that memory.
3002 VecArgOffset = ((VecArgOffset+15)/16)*16;
3003 VecArgOffset += 12*16;
3005 // Add DAG nodes to load the arguments or copy them out of registers. On
3006 // entry to a function on PPC, the arguments start after the linkage area,
3007 // although the first ones are often in registers.
3009 SmallVector<SDValue, 8> MemOps;
3010 unsigned nAltivecParamsAtEnd = 0;
3011 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3012 unsigned CurArgIdx = 0;
3013 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3015 bool needsLoad = false;
3016 EVT ObjectVT = Ins[ArgNo].VT;
3017 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3018 unsigned ArgSize = ObjSize;
3019 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3020 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3021 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3023 unsigned CurArgOffset = ArgOffset;
3025 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3026 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3027 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3028 if (isVarArg || isPPC64) {
3029 MinReservedArea = ((MinReservedArea+15)/16)*16;
3030 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3033 } else nAltivecParamsAtEnd++;
3035 // Calculate min reserved area.
3036 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3040 // FIXME the codegen can be much improved in some cases.
3041 // We do not have to keep everything in memory.
3042 if (Flags.isByVal()) {
3043 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3044 ObjSize = Flags.getByValSize();
3045 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3046 // Objects of size 1 and 2 are right justified, everything else is
3047 // left justified. This means the memory address is adjusted forwards.
3048 if (ObjSize==1 || ObjSize==2) {
3049 CurArgOffset = CurArgOffset + (4 - ObjSize);
3051 // The value of the object is its address.
3052 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
3053 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3054 InVals.push_back(FIN);
3055 if (ObjSize==1 || ObjSize==2) {
3056 if (GPR_idx != Num_GPR_Regs) {
3059 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3061 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3062 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3063 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3064 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3065 MachinePointerInfo(FuncArg),
3066 ObjType, false, false, 0);
3067 MemOps.push_back(Store);
3071 ArgOffset += PtrByteSize;
3075 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3076 // Store whatever pieces of the object are in registers
3077 // to memory. ArgOffset will be the address of the beginning
3079 if (GPR_idx != Num_GPR_Regs) {
3082 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3084 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3085 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3086 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3087 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3088 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3089 MachinePointerInfo(FuncArg, j),
3091 MemOps.push_back(Store);
3093 ArgOffset += PtrByteSize;
3095 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3102 switch (ObjectVT.getSimpleVT().SimpleTy) {
3103 default: llvm_unreachable("Unhandled argument type!");
3107 if (GPR_idx != Num_GPR_Regs) {
3108 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3109 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3111 if (ObjectVT == MVT::i1)
3112 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3117 ArgSize = PtrByteSize;
3119 // All int arguments reserve stack space in the Darwin ABI.
3120 ArgOffset += PtrByteSize;
3124 case MVT::i64: // PPC64
3125 if (GPR_idx != Num_GPR_Regs) {
3126 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3127 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3129 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3130 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3131 // value to MVT::i64 and then truncate to the correct register size.
3132 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3137 ArgSize = PtrByteSize;
3139 // All int arguments reserve stack space in the Darwin ABI.
3145 // Every 4 bytes of argument space consumes one of the GPRs available for
3146 // argument passing.
3147 if (GPR_idx != Num_GPR_Regs) {
3149 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3152 if (FPR_idx != Num_FPR_Regs) {
3155 if (ObjectVT == MVT::f32)
3156 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3158 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3160 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3166 // All FP arguments reserve stack space in the Darwin ABI.
3167 ArgOffset += isPPC64 ? 8 : ObjSize;
3173 // Note that vector arguments in registers don't reserve stack space,
3174 // except in varargs functions.
3175 if (VR_idx != Num_VR_Regs) {
3176 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3177 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3179 while ((ArgOffset % 16) != 0) {
3180 ArgOffset += PtrByteSize;
3181 if (GPR_idx != Num_GPR_Regs)
3185 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3189 if (!isVarArg && !isPPC64) {
3190 // Vectors go after all the nonvectors.
3191 CurArgOffset = VecArgOffset;
3194 // Vectors are aligned.
3195 ArgOffset = ((ArgOffset+15)/16)*16;
3196 CurArgOffset = ArgOffset;
3204 // We need to load the argument to a virtual register if we determined above
3205 // that we ran out of physical registers of the appropriate type.
3207 int FI = MFI->CreateFixedObject(ObjSize,
3208 CurArgOffset + (ArgSize - ObjSize),
3210 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3211 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3212 false, false, false, 0);
3215 InVals.push_back(ArgVal);
3218 // Allow for Altivec parameters at the end, if needed.
3219 if (nAltivecParamsAtEnd) {
3220 MinReservedArea = ((MinReservedArea+15)/16)*16;
3221 MinReservedArea += 16*nAltivecParamsAtEnd;
3224 // Area that is at least reserved in the caller of this function.
3225 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3227 // Set the size that is at least reserved in caller of this function. Tail
3228 // call optimized functions' reserved stack space needs to be aligned so that
3229 // taking the difference between two stack areas will result in an aligned
3231 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3232 FuncInfo->setMinReservedArea(MinReservedArea);
3234 // If the function takes variable number of arguments, make a frame index for
3235 // the start of the first vararg value... for expansion of llvm.va_start.
3237 int Depth = ArgOffset;
3239 FuncInfo->setVarArgsFrameIndex(
3240 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3242 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3244 // If this function is vararg, store any remaining integer argument regs
3245 // to their spots on the stack so that they may be loaded by deferencing the
3246 // result of va_next.
3247 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3251 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3253 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3255 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3256 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3257 MachinePointerInfo(), false, false, 0);
3258 MemOps.push_back(Store);
3259 // Increment the address by four for the next argument to store
3260 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3261 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3265 if (!MemOps.empty())
3266 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3271 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3272 /// adjusted to accommodate the arguments for the tailcall.
3273 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3274 unsigned ParamSize) {
3276 if (!isTailCall) return 0;
3278 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3279 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3280 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3281 // Remember only if the new adjustement is bigger.
3282 if (SPDiff < FI->getTailCallSPDelta())
3283 FI->setTailCallSPDelta(SPDiff);
3288 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3289 /// for tail call optimization. Targets which want to do tail call
3290 /// optimization should implement this function.
3292 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3293 CallingConv::ID CalleeCC,
3295 const SmallVectorImpl<ISD::InputArg> &Ins,
3296 SelectionDAG& DAG) const {
3297 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3300 // Variable argument functions are not supported.
3304 MachineFunction &MF = DAG.getMachineFunction();
3305 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3306 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3307 // Functions containing by val parameters are not supported.
3308 for (unsigned i = 0; i != Ins.size(); i++) {
3309 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3310 if (Flags.isByVal()) return false;
3313 // Non-PIC/GOT tail calls are supported.
3314 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3317 // At the moment we can only do local tail calls (in same module, hidden
3318 // or protected) if we are generating PIC.
3319 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3320 return G->getGlobal()->hasHiddenVisibility()
3321 || G->getGlobal()->hasProtectedVisibility();
3327 /// isCallCompatibleAddress - Return the immediate to use if the specified
3328 /// 32-bit value is representable in the immediate field of a BxA instruction.
3329 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3330 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3331 if (!C) return nullptr;
3333 int Addr = C->getZExtValue();
3334 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3335 SignExtend32<26>(Addr) != Addr)
3336 return nullptr; // Top 6 bits have to be sext of immediate.
3338 return DAG.getConstant((int)C->getZExtValue() >> 2,
3339 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3344 struct TailCallArgumentInfo {
3349 TailCallArgumentInfo() : FrameIdx(0) {}
3354 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3356 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3358 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3359 SmallVectorImpl<SDValue> &MemOpChains,
3361 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3362 SDValue Arg = TailCallArgs[i].Arg;
3363 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3364 int FI = TailCallArgs[i].FrameIdx;
3365 // Store relative to framepointer.
3366 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3367 MachinePointerInfo::getFixedStack(FI),
3372 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3373 /// the appropriate stack slot for the tail call optimized function call.
3374 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3375 MachineFunction &MF,
3384 // Calculate the new stack slot for the return address.
3385 int SlotSize = isPPC64 ? 8 : 4;
3386 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3388 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3389 NewRetAddrLoc, true);
3390 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3391 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3392 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3393 MachinePointerInfo::getFixedStack(NewRetAddr),
3396 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3397 // slot as the FP is never overwritten.
3400 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3401 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3403 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3404 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3405 MachinePointerInfo::getFixedStack(NewFPIdx),
3412 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3413 /// the position of the argument.
3415 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3416 SDValue Arg, int SPDiff, unsigned ArgOffset,
3417 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3418 int Offset = ArgOffset + SPDiff;
3419 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3420 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3421 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3422 SDValue FIN = DAG.getFrameIndex(FI, VT);
3423 TailCallArgumentInfo Info;
3425 Info.FrameIdxOp = FIN;
3427 TailCallArguments.push_back(Info);
3430 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3431 /// stack slot. Returns the chain as result and the loaded frame pointers in
3432 /// LROpOut/FPOpout. Used when tail calling.
3433 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3441 // Load the LR and FP stack slot for later adjusting.
3442 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3443 LROpOut = getReturnAddrFrameIndex(DAG);
3444 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3445 false, false, false, 0);
3446 Chain = SDValue(LROpOut.getNode(), 1);
3448 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3449 // slot as the FP is never overwritten.
3451 FPOpOut = getFramePointerFrameIndex(DAG);
3452 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3453 false, false, false, 0);
3454 Chain = SDValue(FPOpOut.getNode(), 1);
3460 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3461 /// by "Src" to address "Dst" of size "Size". Alignment information is
3462 /// specified by the specific parameter attribute. The copy will be passed as
3463 /// a byval function parameter.
3464 /// Sometimes what we are copying is the end of a larger object, the part that
3465 /// does not fit in registers.
3467 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3468 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3470 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3471 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3472 false, false, MachinePointerInfo(),
3473 MachinePointerInfo());
3476 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3479 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3480 SDValue Arg, SDValue PtrOff, int SPDiff,
3481 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3482 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3483 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3485 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3490 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3492 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3493 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3494 DAG.getConstant(ArgOffset, PtrVT));
3496 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3497 MachinePointerInfo(), false, false, 0));
3498 // Calculate and remember argument location.
3499 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3504 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3505 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3506 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3507 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3508 MachineFunction &MF = DAG.getMachineFunction();
3510 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3511 // might overwrite each other in case of tail call optimization.
3512 SmallVector<SDValue, 8> MemOpChains2;
3513 // Do not flag preceding copytoreg stuff together with the following stuff.
3515 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3517 if (!MemOpChains2.empty())
3518 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3520 // Store the return address to the appropriate stack slot.
3521 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3522 isPPC64, isDarwinABI, dl);
3524 // Emit callseq_end just before tailcall node.
3525 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3526 DAG.getIntPtrConstant(0, true), InFlag, dl);
3527 InFlag = Chain.getValue(1);
3531 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3532 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3533 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3534 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3535 const PPCSubtarget &Subtarget) {
3537 bool isPPC64 = Subtarget.isPPC64();
3538 bool isSVR4ABI = Subtarget.isSVR4ABI();
3539 bool isELFv2ABI = Subtarget.isELFv2ABI();
3541 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3542 NodeTys.push_back(MVT::Other); // Returns a chain
3543 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3545 unsigned CallOpc = PPCISD::CALL;
3547 bool needIndirectCall = true;
3548 if (!isSVR4ABI || !isPPC64)
3549 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3550 // If this is an absolute destination address, use the munged value.
3551 Callee = SDValue(Dest, 0);
3552 needIndirectCall = false;
3555 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3556 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3557 // Use indirect calls for ALL functions calls in JIT mode, since the
3558 // far-call stubs may be outside relocation limits for a BL instruction.
3559 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3560 unsigned OpFlags = 0;
3561 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3562 (Subtarget.getTargetTriple().isMacOSX() &&
3563 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3564 (G->getGlobal()->isDeclaration() ||
3565 G->getGlobal()->isWeakForLinker())) ||
3566 (Subtarget.isTargetELF() && !isPPC64 &&
3567 !G->getGlobal()->hasLocalLinkage() &&
3568 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3569 // PC-relative references to external symbols should go through $stub,
3570 // unless we're building with the leopard linker or later, which
3571 // automatically synthesizes these stubs.
3572 OpFlags = PPCII::MO_PLT_OR_STUB;
3575 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3576 // every direct call is) turn it into a TargetGlobalAddress /
3577 // TargetExternalSymbol node so that legalize doesn't hack it.
3578 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3579 Callee.getValueType(),
3581 needIndirectCall = false;
3585 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3586 unsigned char OpFlags = 0;
3588 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3589 (Subtarget.getTargetTriple().isMacOSX() &&
3590 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3591 (Subtarget.isTargetELF() && !isPPC64 &&
3592 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3593 // PC-relative references to external symbols should go through $stub,
3594 // unless we're building with the leopard linker or later, which
3595 // automatically synthesizes these stubs.
3596 OpFlags = PPCII::MO_PLT_OR_STUB;
3599 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3601 needIndirectCall = false;
3604 if (needIndirectCall) {
3605 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3606 // to do the call, we can't use PPCISD::CALL.
3607 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3609 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3610 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3611 // entry point, but to the function descriptor (the function entry point
3612 // address is part of the function descriptor though).
3613 // The function descriptor is a three doubleword structure with the
3614 // following fields: function entry point, TOC base address and
3615 // environment pointer.
3616 // Thus for a call through a function pointer, the following actions need
3618 // 1. Save the TOC of the caller in the TOC save area of its stack
3619 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3620 // 2. Load the address of the function entry point from the function
3622 // 3. Load the TOC of the callee from the function descriptor into r2.
3623 // 4. Load the environment pointer from the function descriptor into
3625 // 5. Branch to the function entry point address.
3626 // 6. On return of the callee, the TOC of the caller needs to be
3627 // restored (this is done in FinishCall()).
3629 // All those operations are flagged together to ensure that no other
3630 // operations can be scheduled in between. E.g. without flagging the
3631 // operations together, a TOC access in the caller could be scheduled
3632 // between the load of the callee TOC and the branch to the callee, which
3633 // results in the TOC access going through the TOC of the callee instead
3634 // of going through the TOC of the caller, which leads to incorrect code.
3636 // Load the address of the function entry point from the function
3638 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3639 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3640 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3641 Chain = LoadFuncPtr.getValue(1);
3642 InFlag = LoadFuncPtr.getValue(2);
3644 // Load environment pointer into r11.
3645 // Offset of the environment pointer within the function descriptor.
3646 SDValue PtrOff = DAG.getIntPtrConstant(16);
3648 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3649 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3651 Chain = LoadEnvPtr.getValue(1);
3652 InFlag = LoadEnvPtr.getValue(2);
3654 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3656 Chain = EnvVal.getValue(0);
3657 InFlag = EnvVal.getValue(1);
3659 // Load TOC of the callee into r2. We are using a target-specific load
3660 // with r2 hard coded, because the result of a target-independent load
3661 // would never go directly into r2, since r2 is a reserved register (which
3662 // prevents the register allocator from allocating it), resulting in an
3663 // additional register being allocated and an unnecessary move instruction
3665 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3666 SDValue TOCOff = DAG.getIntPtrConstant(8);
3667 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3668 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3670 Chain = LoadTOCPtr.getValue(0);
3671 InFlag = LoadTOCPtr.getValue(1);
3673 MTCTROps[0] = Chain;
3674 MTCTROps[1] = LoadFuncPtr;
3675 MTCTROps[2] = InFlag;
3678 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3679 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3680 InFlag = Chain.getValue(1);
3683 NodeTys.push_back(MVT::Other);
3684 NodeTys.push_back(MVT::Glue);
3685 Ops.push_back(Chain);
3686 CallOpc = PPCISD::BCTRL;
3687 Callee.setNode(nullptr);
3688 // Add use of X11 (holding environment pointer)
3689 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3690 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3691 // Add CTR register as callee so a bctr can be emitted later.
3693 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3696 // If this is a direct call, pass the chain and the callee.
3697 if (Callee.getNode()) {
3698 Ops.push_back(Chain);
3699 Ops.push_back(Callee);
3701 // If this is a tail call add stack pointer delta.
3703 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3705 // Add argument registers to the end of the list so that they are known live
3707 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3708 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3709 RegsToPass[i].second.getValueType()));
3711 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3712 if (Callee.getNode() && isELFv2ABI)
3713 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3719 bool isLocalCall(const SDValue &Callee)
3721 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3722 return !G->getGlobal()->isDeclaration() &&
3723 !G->getGlobal()->isWeakForLinker();
3728 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3729 CallingConv::ID CallConv, bool isVarArg,
3730 const SmallVectorImpl<ISD::InputArg> &Ins,
3731 SDLoc dl, SelectionDAG &DAG,
3732 SmallVectorImpl<SDValue> &InVals) const {
3734 SmallVector<CCValAssign, 16> RVLocs;
3735 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3736 getTargetMachine(), RVLocs, *DAG.getContext());
3737 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3739 // Copy all of the result registers out of their specified physreg.
3740 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3741 CCValAssign &VA = RVLocs[i];
3742 assert(VA.isRegLoc() && "Can only return in registers!");
3744 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3745 VA.getLocReg(), VA.getLocVT(), InFlag);
3746 Chain = Val.getValue(1);
3747 InFlag = Val.getValue(2);
3749 switch (VA.getLocInfo()) {
3750 default: llvm_unreachable("Unknown loc info!");
3751 case CCValAssign::Full: break;
3752 case CCValAssign::AExt:
3753 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3755 case CCValAssign::ZExt:
3756 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3757 DAG.getValueType(VA.getValVT()));
3758 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3760 case CCValAssign::SExt:
3761 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3762 DAG.getValueType(VA.getValVT()));
3763 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3767 InVals.push_back(Val);
3774 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3775 bool isTailCall, bool isVarArg,
3777 SmallVector<std::pair<unsigned, SDValue>, 8>
3779 SDValue InFlag, SDValue Chain,
3781 int SPDiff, unsigned NumBytes,
3782 const SmallVectorImpl<ISD::InputArg> &Ins,
3783 SmallVectorImpl<SDValue> &InVals) const {
3785 bool isELFv2ABI = Subtarget.isELFv2ABI();
3786 std::vector<EVT> NodeTys;
3787 SmallVector<SDValue, 8> Ops;
3788 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3789 isTailCall, RegsToPass, Ops, NodeTys,
3792 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3793 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3794 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3796 // When performing tail call optimization the callee pops its arguments off
3797 // the stack. Account for this here so these bytes can be pushed back on in
3798 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3799 int BytesCalleePops =
3800 (CallConv == CallingConv::Fast &&
3801 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3803 // Add a register mask operand representing the call-preserved registers.
3804 const TargetRegisterInfo *TRI =
3805 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3806 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3807 assert(Mask && "Missing call preserved mask for calling convention");
3808 Ops.push_back(DAG.getRegisterMask(Mask));
3810 if (InFlag.getNode())
3811 Ops.push_back(InFlag);
3815 assert(((Callee.getOpcode() == ISD::Register &&
3816 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3817 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3818 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3819 isa<ConstantSDNode>(Callee)) &&
3820 "Expecting an global address, external symbol, absolute value or register");
3822 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3825 // Add a NOP immediately after the branch instruction when using the 64-bit
3826 // SVR4 ABI. At link time, if caller and callee are in a different module and
3827 // thus have a different TOC, the call will be replaced with a call to a stub
3828 // function which saves the current TOC, loads the TOC of the callee and
3829 // branches to the callee. The NOP will be replaced with a load instruction
3830 // which restores the TOC of the caller from the TOC save slot of the current
3831 // stack frame. If caller and callee belong to the same module (and have the
3832 // same TOC), the NOP will remain unchanged.
3834 bool needsTOCRestore = false;
3835 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3836 if (CallOpc == PPCISD::BCTRL) {
3837 // This is a call through a function pointer.
3838 // Restore the caller TOC from the save area into R2.
3839 // See PrepareCall() for more information about calls through function
3840 // pointers in the 64-bit SVR4 ABI.
3841 // We are using a target-specific load with r2 hard coded, because the
3842 // result of a target-independent load would never go directly into r2,
3843 // since r2 is a reserved register (which prevents the register allocator
3844 // from allocating it), resulting in an additional register being
3845 // allocated and an unnecessary move instruction being generated.
3846 needsTOCRestore = true;
3847 } else if ((CallOpc == PPCISD::CALL) &&
3848 (!isLocalCall(Callee) ||
3849 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3850 // Otherwise insert NOP for non-local calls.
3851 CallOpc = PPCISD::CALL_NOP;
3855 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3856 InFlag = Chain.getValue(1);
3858 if (needsTOCRestore) {
3859 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3860 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3861 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3862 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3863 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3864 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3865 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3866 InFlag = Chain.getValue(1);
3869 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3870 DAG.getIntPtrConstant(BytesCalleePops, true),
3873 InFlag = Chain.getValue(1);
3875 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3876 Ins, dl, DAG, InVals);
3880 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3881 SmallVectorImpl<SDValue> &InVals) const {
3882 SelectionDAG &DAG = CLI.DAG;
3884 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3885 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3886 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3887 SDValue Chain = CLI.Chain;
3888 SDValue Callee = CLI.Callee;
3889 bool &isTailCall = CLI.IsTailCall;
3890 CallingConv::ID CallConv = CLI.CallConv;
3891 bool isVarArg = CLI.IsVarArg;
3894 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3897 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3898 report_fatal_error("failed to perform tail call elimination on a call "
3899 "site marked musttail");
3901 if (Subtarget.isSVR4ABI()) {
3902 if (Subtarget.isPPC64())
3903 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3904 isTailCall, Outs, OutVals, Ins,
3907 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3908 isTailCall, Outs, OutVals, Ins,
3912 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3913 isTailCall, Outs, OutVals, Ins,
3918 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3919 CallingConv::ID CallConv, bool isVarArg,
3921 const SmallVectorImpl<ISD::OutputArg> &Outs,
3922 const SmallVectorImpl<SDValue> &OutVals,
3923 const SmallVectorImpl<ISD::InputArg> &Ins,
3924 SDLoc dl, SelectionDAG &DAG,
3925 SmallVectorImpl<SDValue> &InVals) const {
3926 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3927 // of the 32-bit SVR4 ABI stack frame layout.
3929 assert((CallConv == CallingConv::C ||
3930 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3932 unsigned PtrByteSize = 4;
3934 MachineFunction &MF = DAG.getMachineFunction();
3936 // Mark this function as potentially containing a function that contains a
3937 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3938 // and restoring the callers stack pointer in this functions epilog. This is
3939 // done because by tail calling the called function might overwrite the value
3940 // in this function's (MF) stack pointer stack slot 0(SP).
3941 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3942 CallConv == CallingConv::Fast)
3943 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3945 // Count how many bytes are to be pushed on the stack, including the linkage
3946 // area, parameter list area and the part of the local variable space which
3947 // contains copies of aggregates which are passed by value.
3949 // Assign locations to all of the outgoing arguments.
3950 SmallVector<CCValAssign, 16> ArgLocs;
3951 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3952 getTargetMachine(), ArgLocs, *DAG.getContext());
3954 // Reserve space for the linkage area on the stack.
3955 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3959 // Handle fixed and variable vector arguments differently.
3960 // Fixed vector arguments go into registers as long as registers are
3961 // available. Variable vector arguments always go into memory.
3962 unsigned NumArgs = Outs.size();
3964 for (unsigned i = 0; i != NumArgs; ++i) {
3965 MVT ArgVT = Outs[i].VT;
3966 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3969 if (Outs[i].IsFixed) {
3970 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3973 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3979 errs() << "Call operand #" << i << " has unhandled type "
3980 << EVT(ArgVT).getEVTString() << "\n";
3982 llvm_unreachable(nullptr);
3986 // All arguments are treated the same.
3987 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3990 // Assign locations to all of the outgoing aggregate by value arguments.
3991 SmallVector<CCValAssign, 16> ByValArgLocs;
3992 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3993 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3995 // Reserve stack space for the allocations in CCInfo.
3996 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3998 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4000 // Size of the linkage area, parameter list area and the part of the local
4001 // space variable where copies of aggregates which are passed by value are
4003 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4005 // Calculate by how many bytes the stack has to be adjusted in case of tail
4006 // call optimization.
4007 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4009 // Adjust the stack pointer for the new arguments...
4010 // These operations are automatically eliminated by the prolog/epilog pass
4011 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4013 SDValue CallSeqStart = Chain;
4015 // Load the return address and frame pointer so it can be moved somewhere else
4018 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4021 // Set up a copy of the stack pointer for use loading and storing any
4022 // arguments that may not fit in the registers available for argument
4024 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4026 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4027 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4028 SmallVector<SDValue, 8> MemOpChains;
4030 bool seenFloatArg = false;
4031 // Walk the register/memloc assignments, inserting copies/loads.
4032 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4035 CCValAssign &VA = ArgLocs[i];
4036 SDValue Arg = OutVals[i];
4037 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4039 if (Flags.isByVal()) {
4040 // Argument is an aggregate which is passed by value, thus we need to
4041 // create a copy of it in the local variable space of the current stack
4042 // frame (which is the stack frame of the caller) and pass the address of
4043 // this copy to the callee.
4044 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4045 CCValAssign &ByValVA = ByValArgLocs[j++];
4046 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4048 // Memory reserved in the local variable space of the callers stack frame.
4049 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4051 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4052 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4054 // Create a copy of the argument in the local area of the current
4056 SDValue MemcpyCall =
4057 CreateCopyOfByValArgument(Arg, PtrOff,
4058 CallSeqStart.getNode()->getOperand(0),
4061 // This must go outside the CALLSEQ_START..END.
4062 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4063 CallSeqStart.getNode()->getOperand(1),
4065 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4066 NewCallSeqStart.getNode());
4067 Chain = CallSeqStart = NewCallSeqStart;
4069 // Pass the address of the aggregate copy on the stack either in a
4070 // physical register or in the parameter list area of the current stack
4071 // frame to the callee.
4075 if (VA.isRegLoc()) {
4076 if (Arg.getValueType() == MVT::i1)
4077 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4079 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4080 // Put argument in a physical register.
4081 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4083 // Put argument in the parameter list area of the current stack frame.
4084 assert(VA.isMemLoc());
4085 unsigned LocMemOffset = VA.getLocMemOffset();
4088 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4089 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4091 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4092 MachinePointerInfo(),
4095 // Calculate and remember argument location.
4096 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4102 if (!MemOpChains.empty())
4103 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4105 // Build a sequence of copy-to-reg nodes chained together with token chain
4106 // and flag operands which copy the outgoing args into the appropriate regs.
4108 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4109 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4110 RegsToPass[i].second, InFlag);
4111 InFlag = Chain.getValue(1);
4114 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4117 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4118 SDValue Ops[] = { Chain, InFlag };
4120 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4121 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4123 InFlag = Chain.getValue(1);
4127 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4128 false, TailCallArguments);
4130 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4131 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4135 // Copy an argument into memory, being careful to do this outside the
4136 // call sequence for the call to which the argument belongs.
4138 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4139 SDValue CallSeqStart,
4140 ISD::ArgFlagsTy Flags,
4143 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4144 CallSeqStart.getNode()->getOperand(0),
4146 // The MEMCPY must go outside the CALLSEQ_START..END.
4147 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4148 CallSeqStart.getNode()->getOperand(1),
4150 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4151 NewCallSeqStart.getNode());
4152 return NewCallSeqStart;
4156 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4157 CallingConv::ID CallConv, bool isVarArg,
4159 const SmallVectorImpl<ISD::OutputArg> &Outs,
4160 const SmallVectorImpl<SDValue> &OutVals,
4161 const SmallVectorImpl<ISD::InputArg> &Ins,
4162 SDLoc dl, SelectionDAG &DAG,
4163 SmallVectorImpl<SDValue> &InVals) const {
4165 bool isELFv2ABI = Subtarget.isELFv2ABI();
4166 bool isLittleEndian = Subtarget.isLittleEndian();
4167 unsigned NumOps = Outs.size();
4169 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4170 unsigned PtrByteSize = 8;
4172 MachineFunction &MF = DAG.getMachineFunction();
4174 // Mark this function as potentially containing a function that contains a
4175 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4176 // and restoring the callers stack pointer in this functions epilog. This is
4177 // done because by tail calling the called function might overwrite the value
4178 // in this function's (MF) stack pointer stack slot 0(SP).
4179 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4180 CallConv == CallingConv::Fast)
4181 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4183 // Count how many bytes are to be pushed on the stack, including the linkage
4184 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4185 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4186 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4187 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4189 unsigned NumBytes = LinkageSize;
4191 // Add up all the space actually used.
4192 for (unsigned i = 0; i != NumOps; ++i) {
4193 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4194 EVT ArgVT = Outs[i].VT;
4195 EVT OrigVT = Outs[i].ArgVT;
4197 /* Respect alignment of argument on the stack. */
4199 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4200 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4202 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4203 if (Flags.isInConsecutiveRegsLast())
4204 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4207 unsigned NumBytesActuallyUsed = NumBytes;
4209 // The prolog code of the callee may store up to 8 GPR argument registers to
4210 // the stack, allowing va_start to index over them in memory if its varargs.
4211 // Because we cannot tell if this is needed on the caller side, we have to
4212 // conservatively assume that it is needed. As such, make sure we have at
4213 // least enough stack space for the caller to store the 8 GPRs.
4214 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4215 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4217 // Tail call needs the stack to be aligned.
4218 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4219 CallConv == CallingConv::Fast)
4220 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4222 // Calculate by how many bytes the stack has to be adjusted in case of tail
4223 // call optimization.
4224 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4226 // To protect arguments on the stack from being clobbered in a tail call,
4227 // force all the loads to happen before doing any other lowering.
4229 Chain = DAG.getStackArgumentTokenFactor(Chain);
4231 // Adjust the stack pointer for the new arguments...
4232 // These operations are automatically eliminated by the prolog/epilog pass
4233 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4235 SDValue CallSeqStart = Chain;
4237 // Load the return address and frame pointer so it can be move somewhere else
4240 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4243 // Set up a copy of the stack pointer for use loading and storing any
4244 // arguments that may not fit in the registers available for argument
4246 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4248 // Figure out which arguments are going to go in registers, and which in
4249 // memory. Also, if this is a vararg function, floating point operations
4250 // must be stored to our stack, and loaded into integer regs as well, if
4251 // any integer regs are available for argument passing.
4252 unsigned ArgOffset = LinkageSize;
4253 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4255 static const MCPhysReg GPR[] = {
4256 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4257 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4259 static const MCPhysReg *FPR = GetFPR();
4261 static const MCPhysReg VR[] = {
4262 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4263 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4265 static const MCPhysReg VSRH[] = {
4266 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4267 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4270 const unsigned NumGPRs = array_lengthof(GPR);
4271 const unsigned NumFPRs = 13;
4272 const unsigned NumVRs = array_lengthof(VR);
4274 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4275 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4277 SmallVector<SDValue, 8> MemOpChains;
4278 for (unsigned i = 0; i != NumOps; ++i) {
4279 SDValue Arg = OutVals[i];
4280 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4281 EVT ArgVT = Outs[i].VT;
4282 EVT OrigVT = Outs[i].ArgVT;
4284 /* Respect alignment of argument on the stack. */
4286 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4287 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4289 /* Compute GPR index associated with argument offset. */
4290 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4291 GPR_idx = std::min(GPR_idx, NumGPRs);
4293 // PtrOff will be used to store the current argument to the stack if a
4294 // register cannot be found for it.
4297 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4299 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4301 // Promote integers to 64-bit values.
4302 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4303 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4304 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4305 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4308 // FIXME memcpy is used way more than necessary. Correctness first.
4309 // Note: "by value" is code for passing a structure by value, not
4311 if (Flags.isByVal()) {
4312 // Note: Size includes alignment padding, so
4313 // struct x { short a; char b; }
4314 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4315 // These are the proper values we need for right-justifying the
4316 // aggregate in a parameter register.
4317 unsigned Size = Flags.getByValSize();
4319 // An empty aggregate parameter takes up no storage and no
4324 // All aggregates smaller than 8 bytes must be passed right-justified.
4325 if (Size==1 || Size==2 || Size==4) {
4326 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4327 if (GPR_idx != NumGPRs) {
4328 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4329 MachinePointerInfo(), VT,
4330 false, false, false, 0);
4331 MemOpChains.push_back(Load.getValue(1));
4332 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4334 ArgOffset += PtrByteSize;
4339 if (GPR_idx == NumGPRs && Size < 8) {
4340 SDValue AddPtr = PtrOff;
4341 if (!isLittleEndian) {
4342 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4343 PtrOff.getValueType());
4344 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4346 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4349 ArgOffset += PtrByteSize;
4352 // Copy entire object into memory. There are cases where gcc-generated
4353 // code assumes it is there, even if it could be put entirely into
4354 // registers. (This is not what the doc says.)
4356 // FIXME: The above statement is likely due to a misunderstanding of the
4357 // documents. All arguments must be copied into the parameter area BY
4358 // THE CALLEE in the event that the callee takes the address of any
4359 // formal argument. That has not yet been implemented. However, it is
4360 // reasonable to use the stack area as a staging area for the register
4363 // Skip this for small aggregates, as we will use the same slot for a
4364 // right-justified copy, below.
4366 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4370 // When a register is available, pass a small aggregate right-justified.
4371 if (Size < 8 && GPR_idx != NumGPRs) {
4372 // The easiest way to get this right-justified in a register
4373 // is to copy the structure into the rightmost portion of a
4374 // local variable slot, then load the whole slot into the
4376 // FIXME: The memcpy seems to produce pretty awful code for
4377 // small aggregates, particularly for packed ones.
4378 // FIXME: It would be preferable to use the slot in the
4379 // parameter save area instead of a new local variable.
4380 SDValue AddPtr = PtrOff;
4381 if (!isLittleEndian) {
4382 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4383 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4385 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4389 // Load the slot into the register.
4390 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4391 MachinePointerInfo(),
4392 false, false, false, 0);
4393 MemOpChains.push_back(Load.getValue(1));
4394 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4396 // Done with this argument.
4397 ArgOffset += PtrByteSize;
4401 // For aggregates larger than PtrByteSize, copy the pieces of the
4402 // object that fit into registers from the parameter save area.
4403 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4404 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4405 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4406 if (GPR_idx != NumGPRs) {
4407 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4408 MachinePointerInfo(),
4409 false, false, false, 0);
4410 MemOpChains.push_back(Load.getValue(1));
4411 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4412 ArgOffset += PtrByteSize;
4414 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4421 switch (Arg.getSimpleValueType().SimpleTy) {
4422 default: llvm_unreachable("Unexpected ValueType for argument!");
4426 // These can be scalar arguments or elements of an integer array type
4427 // passed directly. Clang may use those instead of "byval" aggregate
4428 // types to avoid forcing arguments to memory unnecessarily.
4429 if (GPR_idx != NumGPRs) {
4430 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4432 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4433 true, isTailCall, false, MemOpChains,
4434 TailCallArguments, dl);
4436 ArgOffset += PtrByteSize;
4440 // These can be scalar arguments or elements of a float array type
4441 // passed directly. The latter are used to implement ELFv2 homogenous
4442 // float aggregates.
4444 // Named arguments go into FPRs first, and once they overflow, the
4445 // remaining arguments go into GPRs and then the parameter save area.
4446 // Unnamed arguments for vararg functions always go to GPRs and
4447 // then the parameter save area. For now, put all arguments to vararg
4448 // routines always in both locations (FPR *and* GPR or stack slot).
4449 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4451 // First load the argument into the next available FPR.
4452 if (FPR_idx != NumFPRs)
4453 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4455 // Next, load the argument into GPR or stack slot if needed.
4456 if (!NeedGPROrStack)
4458 else if (GPR_idx != NumGPRs) {
4459 // In the non-vararg case, this can only ever happen in the
4460 // presence of f32 array types, since otherwise we never run
4461 // out of FPRs before running out of GPRs.
4464 // Double values are always passed in a single GPR.
4465 if (Arg.getValueType() != MVT::f32) {
4466 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4468 // Non-array float values are extended and passed in a GPR.
4469 } else if (!Flags.isInConsecutiveRegs()) {
4470 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4471 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4473 // If we have an array of floats, we collect every odd element
4474 // together with its predecessor into one GPR.
4475 } else if (ArgOffset % PtrByteSize != 0) {
4477 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4478 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4479 if (!isLittleEndian)
4481 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4483 // The final element, if even, goes into the first half of a GPR.
4484 } else if (Flags.isInConsecutiveRegsLast()) {
4485 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4486 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4487 if (!isLittleEndian)
4488 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4489 DAG.getConstant(32, MVT::i32));
4491 // Non-final even elements are skipped; they will be handled
4492 // together the with subsequent argument on the next go-around.
4496 if (ArgVal.getNode())
4497 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4499 // Single-precision floating-point values are mapped to the
4500 // second (rightmost) word of the stack doubleword.
4501 if (Arg.getValueType() == MVT::f32 &&
4502 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4503 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4504 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4507 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4508 true, isTailCall, false, MemOpChains,
4509 TailCallArguments, dl);
4511 // When passing an array of floats, the array occupies consecutive
4512 // space in the argument area; only round up to the next doubleword
4513 // at the end of the array. Otherwise, each float takes 8 bytes.
4514 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4515 Flags.isInConsecutiveRegs()) ? 4 : 8;
4516 if (Flags.isInConsecutiveRegsLast())
4517 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4526 // These can be scalar arguments or elements of a vector array type
4527 // passed directly. The latter are used to implement ELFv2 homogenous
4528 // vector aggregates.
4530 // For a varargs call, named arguments go into VRs or on the stack as
4531 // usual; unnamed arguments always go to the stack or the corresponding
4532 // GPRs when within range. For now, we always put the value in both
4533 // locations (or even all three).
4535 // We could elide this store in the case where the object fits
4536 // entirely in R registers. Maybe later.
4537 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4538 MachinePointerInfo(), false, false, 0);
4539 MemOpChains.push_back(Store);
4540 if (VR_idx != NumVRs) {
4541 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4542 MachinePointerInfo(),
4543 false, false, false, 0);
4544 MemOpChains.push_back(Load.getValue(1));
4546 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4547 Arg.getSimpleValueType() == MVT::v2i64) ?
4548 VSRH[VR_idx] : VR[VR_idx];
4551 RegsToPass.push_back(std::make_pair(VReg, Load));
4554 for (unsigned i=0; i<16; i+=PtrByteSize) {
4555 if (GPR_idx == NumGPRs)
4557 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4558 DAG.getConstant(i, PtrVT));
4559 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4560 false, false, false, 0);
4561 MemOpChains.push_back(Load.getValue(1));
4562 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4567 // Non-varargs Altivec params go into VRs or on the stack.
4568 if (VR_idx != NumVRs) {
4569 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4570 Arg.getSimpleValueType() == MVT::v2i64) ?
4571 VSRH[VR_idx] : VR[VR_idx];
4574 RegsToPass.push_back(std::make_pair(VReg, Arg));
4576 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4577 true, isTailCall, true, MemOpChains,
4578 TailCallArguments, dl);
4585 assert(NumBytesActuallyUsed == ArgOffset);
4586 (void)NumBytesActuallyUsed;
4588 if (!MemOpChains.empty())
4589 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4591 // Check if this is an indirect call (MTCTR/BCTRL).
4592 // See PrepareCall() for more information about calls through function
4593 // pointers in the 64-bit SVR4 ABI.
4595 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4596 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4597 // Load r2 into a virtual register and store it to the TOC save area.
4598 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4599 // TOC save area offset.
4600 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4601 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4602 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4603 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4605 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4606 // This does not mean the MTCTR instruction must use R12; it's easier
4607 // to model this as an extra parameter, so do that.
4609 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4612 // Build a sequence of copy-to-reg nodes chained together with token chain
4613 // and flag operands which copy the outgoing args into the appropriate regs.
4615 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4616 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4617 RegsToPass[i].second, InFlag);
4618 InFlag = Chain.getValue(1);
4622 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4623 FPOp, true, TailCallArguments);
4625 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4626 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4631 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4632 CallingConv::ID CallConv, bool isVarArg,
4634 const SmallVectorImpl<ISD::OutputArg> &Outs,
4635 const SmallVectorImpl<SDValue> &OutVals,
4636 const SmallVectorImpl<ISD::InputArg> &Ins,
4637 SDLoc dl, SelectionDAG &DAG,
4638 SmallVectorImpl<SDValue> &InVals) const {
4640 unsigned NumOps = Outs.size();
4642 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4643 bool isPPC64 = PtrVT == MVT::i64;
4644 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4646 MachineFunction &MF = DAG.getMachineFunction();
4648 // Mark this function as potentially containing a function that contains a
4649 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4650 // and restoring the callers stack pointer in this functions epilog. This is
4651 // done because by tail calling the called function might overwrite the value
4652 // in this function's (MF) stack pointer stack slot 0(SP).
4653 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4654 CallConv == CallingConv::Fast)
4655 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4657 // Count how many bytes are to be pushed on the stack, including the linkage
4658 // area, and parameter passing area. We start with 24/48 bytes, which is
4659 // prereserved space for [SP][CR][LR][3 x unused].
4660 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4662 unsigned NumBytes = LinkageSize;
4664 // Add up all the space actually used.
4665 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4666 // they all go in registers, but we must reserve stack space for them for
4667 // possible use by the caller. In varargs or 64-bit calls, parameters are
4668 // assigned stack space in order, with padding so Altivec parameters are
4670 unsigned nAltivecParamsAtEnd = 0;
4671 for (unsigned i = 0; i != NumOps; ++i) {
4672 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4673 EVT ArgVT = Outs[i].VT;
4674 // Varargs Altivec parameters are padded to a 16 byte boundary.
4675 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4676 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4677 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4678 if (!isVarArg && !isPPC64) {
4679 // Non-varargs Altivec parameters go after all the non-Altivec
4680 // parameters; handle those later so we know how much padding we need.
4681 nAltivecParamsAtEnd++;
4684 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4685 NumBytes = ((NumBytes+15)/16)*16;
4687 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4690 // Allow for Altivec parameters at the end, if needed.
4691 if (nAltivecParamsAtEnd) {
4692 NumBytes = ((NumBytes+15)/16)*16;
4693 NumBytes += 16*nAltivecParamsAtEnd;
4696 // The prolog code of the callee may store up to 8 GPR argument registers to
4697 // the stack, allowing va_start to index over them in memory if its varargs.
4698 // Because we cannot tell if this is needed on the caller side, we have to
4699 // conservatively assume that it is needed. As such, make sure we have at
4700 // least enough stack space for the caller to store the 8 GPRs.
4701 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4703 // Tail call needs the stack to be aligned.
4704 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4705 CallConv == CallingConv::Fast)
4706 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4708 // Calculate by how many bytes the stack has to be adjusted in case of tail
4709 // call optimization.
4710 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4712 // To protect arguments on the stack from being clobbered in a tail call,
4713 // force all the loads to happen before doing any other lowering.
4715 Chain = DAG.getStackArgumentTokenFactor(Chain);
4717 // Adjust the stack pointer for the new arguments...
4718 // These operations are automatically eliminated by the prolog/epilog pass
4719 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4721 SDValue CallSeqStart = Chain;
4723 // Load the return address and frame pointer so it can be move somewhere else
4726 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4729 // Set up a copy of the stack pointer for use loading and storing any
4730 // arguments that may not fit in the registers available for argument
4734 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4736 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4738 // Figure out which arguments are going to go in registers, and which in
4739 // memory. Also, if this is a vararg function, floating point operations
4740 // must be stored to our stack, and loaded into integer regs as well, if
4741 // any integer regs are available for argument passing.
4742 unsigned ArgOffset = LinkageSize;
4743 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4745 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4746 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4747 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4749 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4750 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4751 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4753 static const MCPhysReg *FPR = GetFPR();
4755 static const MCPhysReg VR[] = {
4756 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4757 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4759 const unsigned NumGPRs = array_lengthof(GPR_32);
4760 const unsigned NumFPRs = 13;
4761 const unsigned NumVRs = array_lengthof(VR);
4763 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4765 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4766 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4768 SmallVector<SDValue, 8> MemOpChains;
4769 for (unsigned i = 0; i != NumOps; ++i) {
4770 SDValue Arg = OutVals[i];
4771 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4773 // PtrOff will be used to store the current argument to the stack if a
4774 // register cannot be found for it.
4777 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4779 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4781 // On PPC64, promote integers to 64-bit values.
4782 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4783 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4784 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4785 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4788 // FIXME memcpy is used way more than necessary. Correctness first.
4789 // Note: "by value" is code for passing a structure by value, not
4791 if (Flags.isByVal()) {
4792 unsigned Size = Flags.getByValSize();
4793 // Very small objects are passed right-justified. Everything else is
4794 // passed left-justified.
4795 if (Size==1 || Size==2) {
4796 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4797 if (GPR_idx != NumGPRs) {
4798 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4799 MachinePointerInfo(), VT,
4800 false, false, false, 0);
4801 MemOpChains.push_back(Load.getValue(1));
4802 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4804 ArgOffset += PtrByteSize;
4806 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4807 PtrOff.getValueType());
4808 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4809 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4812 ArgOffset += PtrByteSize;
4816 // Copy entire object into memory. There are cases where gcc-generated
4817 // code assumes it is there, even if it could be put entirely into
4818 // registers. (This is not what the doc says.)
4819 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4823 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4824 // copy the pieces of the object that fit into registers from the
4825 // parameter save area.
4826 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4827 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4828 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4829 if (GPR_idx != NumGPRs) {
4830 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4831 MachinePointerInfo(),
4832 false, false, false, 0);
4833 MemOpChains.push_back(Load.getValue(1));
4834 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4835 ArgOffset += PtrByteSize;
4837 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4844 switch (Arg.getSimpleValueType().SimpleTy) {
4845 default: llvm_unreachable("Unexpected ValueType for argument!");
4849 if (GPR_idx != NumGPRs) {
4850 if (Arg.getValueType() == MVT::i1)
4851 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4853 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4855 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4856 isPPC64, isTailCall, false, MemOpChains,
4857 TailCallArguments, dl);
4859 ArgOffset += PtrByteSize;
4863 if (FPR_idx != NumFPRs) {
4864 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4867 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4868 MachinePointerInfo(), false, false, 0);
4869 MemOpChains.push_back(Store);
4871 // Float varargs are always shadowed in available integer registers
4872 if (GPR_idx != NumGPRs) {
4873 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4874 MachinePointerInfo(), false, false,
4876 MemOpChains.push_back(Load.getValue(1));
4877 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4879 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4880 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4881 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4882 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4883 MachinePointerInfo(),
4884 false, false, false, 0);
4885 MemOpChains.push_back(Load.getValue(1));
4886 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4889 // If we have any FPRs remaining, we may also have GPRs remaining.
4890 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4892 if (GPR_idx != NumGPRs)
4894 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4895 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4899 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4900 isPPC64, isTailCall, false, MemOpChains,
4901 TailCallArguments, dl);
4905 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4912 // These go aligned on the stack, or in the corresponding R registers
4913 // when within range. The Darwin PPC ABI doc claims they also go in
4914 // V registers; in fact gcc does this only for arguments that are
4915 // prototyped, not for those that match the ... We do it for all
4916 // arguments, seems to work.
4917 while (ArgOffset % 16 !=0) {
4918 ArgOffset += PtrByteSize;
4919 if (GPR_idx != NumGPRs)
4922 // We could elide this store in the case where the object fits
4923 // entirely in R registers. Maybe later.
4924 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4925 DAG.getConstant(ArgOffset, PtrVT));
4926 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4927 MachinePointerInfo(), false, false, 0);
4928 MemOpChains.push_back(Store);
4929 if (VR_idx != NumVRs) {
4930 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4931 MachinePointerInfo(),
4932 false, false, false, 0);
4933 MemOpChains.push_back(Load.getValue(1));
4934 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4937 for (unsigned i=0; i<16; i+=PtrByteSize) {
4938 if (GPR_idx == NumGPRs)
4940 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4941 DAG.getConstant(i, PtrVT));
4942 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4943 false, false, false, 0);
4944 MemOpChains.push_back(Load.getValue(1));
4945 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4950 // Non-varargs Altivec params generally go in registers, but have
4951 // stack space allocated at the end.
4952 if (VR_idx != NumVRs) {
4953 // Doesn't have GPR space allocated.
4954 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4955 } else if (nAltivecParamsAtEnd==0) {
4956 // We are emitting Altivec params in order.
4957 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4958 isPPC64, isTailCall, true, MemOpChains,
4959 TailCallArguments, dl);
4965 // If all Altivec parameters fit in registers, as they usually do,
4966 // they get stack space following the non-Altivec parameters. We
4967 // don't track this here because nobody below needs it.
4968 // If there are more Altivec parameters than fit in registers emit
4970 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4972 // Offset is aligned; skip 1st 12 params which go in V registers.
4973 ArgOffset = ((ArgOffset+15)/16)*16;
4975 for (unsigned i = 0; i != NumOps; ++i) {
4976 SDValue Arg = OutVals[i];
4977 EVT ArgType = Outs[i].VT;
4978 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4979 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4982 // We are emitting Altivec params in order.
4983 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4984 isPPC64, isTailCall, true, MemOpChains,
4985 TailCallArguments, dl);
4992 if (!MemOpChains.empty())
4993 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4995 // On Darwin, R12 must contain the address of an indirect callee. This does
4996 // not mean the MTCTR instruction must use R12; it's easier to model this as
4997 // an extra parameter, so do that.
4999 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5000 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5001 !isBLACompatibleAddress(Callee, DAG))
5002 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5003 PPC::R12), Callee));
5005 // Build a sequence of copy-to-reg nodes chained together with token chain
5006 // and flag operands which copy the outgoing args into the appropriate regs.
5008 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5009 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5010 RegsToPass[i].second, InFlag);
5011 InFlag = Chain.getValue(1);
5015 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5016 FPOp, true, TailCallArguments);
5018 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5019 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5024 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5025 MachineFunction &MF, bool isVarArg,
5026 const SmallVectorImpl<ISD::OutputArg> &Outs,
5027 LLVMContext &Context) const {
5028 SmallVector<CCValAssign, 16> RVLocs;
5029 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
5031 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5035 PPCTargetLowering::LowerReturn(SDValue Chain,
5036 CallingConv::ID CallConv, bool isVarArg,
5037 const SmallVectorImpl<ISD::OutputArg> &Outs,
5038 const SmallVectorImpl<SDValue> &OutVals,
5039 SDLoc dl, SelectionDAG &DAG) const {
5041 SmallVector<CCValAssign, 16> RVLocs;
5042 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
5043 getTargetMachine(), RVLocs, *DAG.getContext());
5044 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5047 SmallVector<SDValue, 4> RetOps(1, Chain);
5049 // Copy the result values into the output registers.
5050 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5051 CCValAssign &VA = RVLocs[i];
5052 assert(VA.isRegLoc() && "Can only return in registers!");
5054 SDValue Arg = OutVals[i];
5056 switch (VA.getLocInfo()) {
5057 default: llvm_unreachable("Unknown loc info!");
5058 case CCValAssign::Full: break;
5059 case CCValAssign::AExt:
5060 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5062 case CCValAssign::ZExt:
5063 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5065 case CCValAssign::SExt:
5066 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5070 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5071 Flag = Chain.getValue(1);
5072 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5075 RetOps[0] = Chain; // Update chain.
5077 // Add the flag if we have it.
5079 RetOps.push_back(Flag);
5081 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5084 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5085 const PPCSubtarget &Subtarget) const {
5086 // When we pop the dynamic allocation we need to restore the SP link.
5089 // Get the corect type for pointers.
5090 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5092 // Construct the stack pointer operand.
5093 bool isPPC64 = Subtarget.isPPC64();
5094 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5095 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5097 // Get the operands for the STACKRESTORE.
5098 SDValue Chain = Op.getOperand(0);
5099 SDValue SaveSP = Op.getOperand(1);
5101 // Load the old link SP.
5102 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5103 MachinePointerInfo(),
5104 false, false, false, 0);
5106 // Restore the stack pointer.
5107 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5109 // Store the old link SP.
5110 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5117 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5118 MachineFunction &MF = DAG.getMachineFunction();
5119 bool isPPC64 = Subtarget.isPPC64();
5120 bool isDarwinABI = Subtarget.isDarwinABI();
5121 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5123 // Get current frame pointer save index. The users of this index will be
5124 // primarily DYNALLOC instructions.
5125 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5126 int RASI = FI->getReturnAddrSaveIndex();
5128 // If the frame pointer save index hasn't been defined yet.
5130 // Find out what the fix offset of the frame pointer save area.
5131 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5132 // Allocate the frame index for frame pointer save area.
5133 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5135 FI->setReturnAddrSaveIndex(RASI);
5137 return DAG.getFrameIndex(RASI, PtrVT);
5141 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5142 MachineFunction &MF = DAG.getMachineFunction();
5143 bool isPPC64 = Subtarget.isPPC64();
5144 bool isDarwinABI = Subtarget.isDarwinABI();
5145 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5147 // Get current frame pointer save index. The users of this index will be
5148 // primarily DYNALLOC instructions.
5149 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5150 int FPSI = FI->getFramePointerSaveIndex();
5152 // If the frame pointer save index hasn't been defined yet.
5154 // Find out what the fix offset of the frame pointer save area.
5155 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5158 // Allocate the frame index for frame pointer save area.
5159 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5161 FI->setFramePointerSaveIndex(FPSI);
5163 return DAG.getFrameIndex(FPSI, PtrVT);
5166 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5168 const PPCSubtarget &Subtarget) const {
5170 SDValue Chain = Op.getOperand(0);
5171 SDValue Size = Op.getOperand(1);
5174 // Get the corect type for pointers.
5175 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5177 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5178 DAG.getConstant(0, PtrVT), Size);
5179 // Construct a node for the frame pointer save index.
5180 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5181 // Build a DYNALLOC node.
5182 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5183 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5184 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5187 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5188 SelectionDAG &DAG) const {
5190 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5191 DAG.getVTList(MVT::i32, MVT::Other),
5192 Op.getOperand(0), Op.getOperand(1));
5195 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5196 SelectionDAG &DAG) const {
5198 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5199 Op.getOperand(0), Op.getOperand(1));
5202 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5203 assert(Op.getValueType() == MVT::i1 &&
5204 "Custom lowering only for i1 loads");
5206 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5209 LoadSDNode *LD = cast<LoadSDNode>(Op);
5211 SDValue Chain = LD->getChain();
5212 SDValue BasePtr = LD->getBasePtr();
5213 MachineMemOperand *MMO = LD->getMemOperand();
5215 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5216 BasePtr, MVT::i8, MMO);
5217 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5219 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5220 return DAG.getMergeValues(Ops, dl);
5223 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5224 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5225 "Custom lowering only for i1 stores");
5227 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5230 StoreSDNode *ST = cast<StoreSDNode>(Op);
5232 SDValue Chain = ST->getChain();
5233 SDValue BasePtr = ST->getBasePtr();
5234 SDValue Value = ST->getValue();
5235 MachineMemOperand *MMO = ST->getMemOperand();
5237 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5238 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5241 // FIXME: Remove this once the ANDI glue bug is fixed:
5242 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5243 assert(Op.getValueType() == MVT::i1 &&
5244 "Custom lowering only for i1 results");
5247 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5251 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5253 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5254 // Not FP? Not a fsel.
5255 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5256 !Op.getOperand(2).getValueType().isFloatingPoint())
5259 // We might be able to do better than this under some circumstances, but in
5260 // general, fsel-based lowering of select is a finite-math-only optimization.
5261 // For more information, see section F.3 of the 2.06 ISA specification.
5262 if (!DAG.getTarget().Options.NoInfsFPMath ||
5263 !DAG.getTarget().Options.NoNaNsFPMath)
5266 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5268 EVT ResVT = Op.getValueType();
5269 EVT CmpVT = Op.getOperand(0).getValueType();
5270 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5271 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5274 // If the RHS of the comparison is a 0.0, we don't need to do the
5275 // subtraction at all.
5277 if (isFloatingPointZero(RHS))
5279 default: break; // SETUO etc aren't handled by fsel.
5283 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5284 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5285 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5286 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5287 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5288 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5289 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5292 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5295 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5296 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5297 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5300 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5303 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5304 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5305 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5306 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5311 default: break; // SETUO etc aren't handled by fsel.
5315 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5316 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5317 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5318 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5319 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5320 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5321 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5322 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5325 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5326 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5327 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5328 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5331 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5332 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5333 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5334 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5337 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5338 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5339 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5340 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5343 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5344 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5345 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5346 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5351 // FIXME: Split this code up when LegalizeDAGTypes lands.
5352 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5354 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5355 SDValue Src = Op.getOperand(0);
5356 if (Src.getValueType() == MVT::f32)
5357 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5360 switch (Op.getSimpleValueType().SimpleTy) {
5361 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5363 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5364 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5369 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5370 "i64 FP_TO_UINT is supported only with FPCVT");
5371 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5377 // Convert the FP value to an int value through memory.
5378 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5379 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5380 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5381 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5382 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5384 // Emit a store to the stack slot.
5387 MachineFunction &MF = DAG.getMachineFunction();
5388 MachineMemOperand *MMO =
5389 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5390 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5391 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5392 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5394 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5395 MPI, false, false, 0);
5397 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5399 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5400 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5401 DAG.getConstant(4, FIPtr.getValueType()));
5402 MPI = MachinePointerInfo();
5405 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5406 false, false, false, 0);
5409 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5410 SelectionDAG &DAG) const {
5412 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5413 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5416 if (Op.getOperand(0).getValueType() == MVT::i1)
5417 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5418 DAG.getConstantFP(1.0, Op.getValueType()),
5419 DAG.getConstantFP(0.0, Op.getValueType()));
5421 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5422 "UINT_TO_FP is supported only with FPCVT");
5424 // If we have FCFIDS, then use it when converting to single-precision.
5425 // Otherwise, convert to double-precision and then round.
5426 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5427 (Op.getOpcode() == ISD::UINT_TO_FP ?
5428 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5429 (Op.getOpcode() == ISD::UINT_TO_FP ?
5430 PPCISD::FCFIDU : PPCISD::FCFID);
5431 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5432 MVT::f32 : MVT::f64;
5434 if (Op.getOperand(0).getValueType() == MVT::i64) {
5435 SDValue SINT = Op.getOperand(0);
5436 // When converting to single-precision, we actually need to convert
5437 // to double-precision first and then round to single-precision.
5438 // To avoid double-rounding effects during that operation, we have
5439 // to prepare the input operand. Bits that might be truncated when
5440 // converting to double-precision are replaced by a bit that won't
5441 // be lost at this stage, but is below the single-precision rounding
5444 // However, if -enable-unsafe-fp-math is in effect, accept double
5445 // rounding to avoid the extra overhead.
5446 if (Op.getValueType() == MVT::f32 &&
5447 !Subtarget.hasFPCVT() &&
5448 !DAG.getTarget().Options.UnsafeFPMath) {
5450 // Twiddle input to make sure the low 11 bits are zero. (If this
5451 // is the case, we are guaranteed the value will fit into the 53 bit
5452 // mantissa of an IEEE double-precision value without rounding.)
5453 // If any of those low 11 bits were not zero originally, make sure
5454 // bit 12 (value 2048) is set instead, so that the final rounding
5455 // to single-precision gets the correct result.
5456 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5457 SINT, DAG.getConstant(2047, MVT::i64));
5458 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5459 Round, DAG.getConstant(2047, MVT::i64));
5460 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5461 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5462 Round, DAG.getConstant(-2048, MVT::i64));
5464 // However, we cannot use that value unconditionally: if the magnitude
5465 // of the input value is small, the bit-twiddling we did above might
5466 // end up visibly changing the output. Fortunately, in that case, we
5467 // don't need to twiddle bits since the original input will convert
5468 // exactly to double-precision floating-point already. Therefore,
5469 // construct a conditional to use the original value if the top 11
5470 // bits are all sign-bit copies, and use the rounded value computed
5472 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5473 SINT, DAG.getConstant(53, MVT::i32));
5474 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5475 Cond, DAG.getConstant(1, MVT::i64));
5476 Cond = DAG.getSetCC(dl, MVT::i32,
5477 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5479 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5482 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5483 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5485 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5486 FP = DAG.getNode(ISD::FP_ROUND, dl,
5487 MVT::f32, FP, DAG.getIntPtrConstant(0));
5491 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5492 "Unhandled INT_TO_FP type in custom expander!");
5493 // Since we only generate this in 64-bit mode, we can take advantage of
5494 // 64-bit registers. In particular, sign extend the input value into the
5495 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5496 // then lfd it and fcfid it.
5497 MachineFunction &MF = DAG.getMachineFunction();
5498 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5499 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5502 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5503 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5504 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5506 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5507 MachinePointerInfo::getFixedStack(FrameIdx),
5510 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5511 "Expected an i32 store");
5512 MachineMemOperand *MMO =
5513 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5514 MachineMemOperand::MOLoad, 4, 4);
5515 SDValue Ops[] = { Store, FIdx };
5516 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5517 PPCISD::LFIWZX : PPCISD::LFIWAX,
5518 dl, DAG.getVTList(MVT::f64, MVT::Other),
5519 Ops, MVT::i32, MMO);
5521 assert(Subtarget.isPPC64() &&
5522 "i32->FP without LFIWAX supported only on PPC64");
5524 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5525 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5527 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5530 // STD the extended value into the stack slot.
5531 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5532 MachinePointerInfo::getFixedStack(FrameIdx),
5535 // Load the value as a double.
5536 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5537 MachinePointerInfo::getFixedStack(FrameIdx),
5538 false, false, false, 0);
5541 // FCFID it and return it.
5542 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5543 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5544 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5548 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5549 SelectionDAG &DAG) const {
5552 The rounding mode is in bits 30:31 of FPSR, and has the following
5559 FLT_ROUNDS, on the other hand, expects the following:
5566 To perform the conversion, we do:
5567 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5570 MachineFunction &MF = DAG.getMachineFunction();
5571 EVT VT = Op.getValueType();
5572 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5574 // Save FP Control Word to register
5576 MVT::f64, // return register
5577 MVT::Glue // unused in this context
5579 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5581 // Save FP register to stack slot
5582 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5583 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5584 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5585 StackSlot, MachinePointerInfo(), false, false,0);
5587 // Load FP Control Word from low 32 bits of stack slot.
5588 SDValue Four = DAG.getConstant(4, PtrVT);
5589 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5590 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5591 false, false, false, 0);
5593 // Transform as necessary
5595 DAG.getNode(ISD::AND, dl, MVT::i32,
5596 CWD, DAG.getConstant(3, MVT::i32));
5598 DAG.getNode(ISD::SRL, dl, MVT::i32,
5599 DAG.getNode(ISD::AND, dl, MVT::i32,
5600 DAG.getNode(ISD::XOR, dl, MVT::i32,
5601 CWD, DAG.getConstant(3, MVT::i32)),
5602 DAG.getConstant(3, MVT::i32)),
5603 DAG.getConstant(1, MVT::i32));
5606 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5608 return DAG.getNode((VT.getSizeInBits() < 16 ?
5609 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5612 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5613 EVT VT = Op.getValueType();
5614 unsigned BitWidth = VT.getSizeInBits();
5616 assert(Op.getNumOperands() == 3 &&
5617 VT == Op.getOperand(1).getValueType() &&
5620 // Expand into a bunch of logical ops. Note that these ops
5621 // depend on the PPC behavior for oversized shift amounts.
5622 SDValue Lo = Op.getOperand(0);
5623 SDValue Hi = Op.getOperand(1);
5624 SDValue Amt = Op.getOperand(2);
5625 EVT AmtVT = Amt.getValueType();
5627 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5628 DAG.getConstant(BitWidth, AmtVT), Amt);
5629 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5630 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5631 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5632 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5633 DAG.getConstant(-BitWidth, AmtVT));
5634 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5635 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5636 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5637 SDValue OutOps[] = { OutLo, OutHi };
5638 return DAG.getMergeValues(OutOps, dl);
5641 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5642 EVT VT = Op.getValueType();
5644 unsigned BitWidth = VT.getSizeInBits();
5645 assert(Op.getNumOperands() == 3 &&
5646 VT == Op.getOperand(1).getValueType() &&
5649 // Expand into a bunch of logical ops. Note that these ops
5650 // depend on the PPC behavior for oversized shift amounts.
5651 SDValue Lo = Op.getOperand(0);
5652 SDValue Hi = Op.getOperand(1);
5653 SDValue Amt = Op.getOperand(2);
5654 EVT AmtVT = Amt.getValueType();
5656 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5657 DAG.getConstant(BitWidth, AmtVT), Amt);
5658 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5659 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5660 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5661 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5662 DAG.getConstant(-BitWidth, AmtVT));
5663 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5664 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5665 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5666 SDValue OutOps[] = { OutLo, OutHi };
5667 return DAG.getMergeValues(OutOps, dl);
5670 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5672 EVT VT = Op.getValueType();
5673 unsigned BitWidth = VT.getSizeInBits();
5674 assert(Op.getNumOperands() == 3 &&
5675 VT == Op.getOperand(1).getValueType() &&
5678 // Expand into a bunch of logical ops, followed by a select_cc.
5679 SDValue Lo = Op.getOperand(0);
5680 SDValue Hi = Op.getOperand(1);
5681 SDValue Amt = Op.getOperand(2);
5682 EVT AmtVT = Amt.getValueType();
5684 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5685 DAG.getConstant(BitWidth, AmtVT), Amt);
5686 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5687 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5688 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5689 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5690 DAG.getConstant(-BitWidth, AmtVT));
5691 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5692 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5693 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5694 Tmp4, Tmp6, ISD::SETLE);
5695 SDValue OutOps[] = { OutLo, OutHi };
5696 return DAG.getMergeValues(OutOps, dl);
5699 //===----------------------------------------------------------------------===//
5700 // Vector related lowering.
5703 /// BuildSplatI - Build a canonical splati of Val with an element size of
5704 /// SplatSize. Cast the result to VT.
5705 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5706 SelectionDAG &DAG, SDLoc dl) {
5707 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5709 static const EVT VTys[] = { // canonical VT to use for each size.
5710 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5713 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5715 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5719 EVT CanonicalVT = VTys[SplatSize-1];
5721 // Build a canonical splat for this value.
5722 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5723 SmallVector<SDValue, 8> Ops;
5724 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5725 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5726 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5729 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5730 /// specified intrinsic ID.
5731 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5732 SelectionDAG &DAG, SDLoc dl,
5733 EVT DestVT = MVT::Other) {
5734 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5735 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5736 DAG.getConstant(IID, MVT::i32), Op);
5739 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5740 /// specified intrinsic ID.
5741 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5742 SelectionDAG &DAG, SDLoc dl,
5743 EVT DestVT = MVT::Other) {
5744 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5745 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5746 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5749 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5750 /// specified intrinsic ID.
5751 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5752 SDValue Op2, SelectionDAG &DAG,
5753 SDLoc dl, EVT DestVT = MVT::Other) {
5754 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5755 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5756 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5760 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5761 /// amount. The result has the specified value type.
5762 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5763 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5764 // Force LHS/RHS to be the right type.
5765 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5766 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5769 for (unsigned i = 0; i != 16; ++i)
5771 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5772 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5775 // If this is a case we can't handle, return null and let the default
5776 // expansion code take care of it. If we CAN select this case, and if it
5777 // selects to a single instruction, return Op. Otherwise, if we can codegen
5778 // this case more efficiently than a constant pool load, lower it to the
5779 // sequence of ops that should be used.
5780 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5781 SelectionDAG &DAG) const {
5783 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5784 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5786 // Check if this is a splat of a constant value.
5787 APInt APSplatBits, APSplatUndef;
5788 unsigned SplatBitSize;
5790 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5791 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5794 unsigned SplatBits = APSplatBits.getZExtValue();
5795 unsigned SplatUndef = APSplatUndef.getZExtValue();
5796 unsigned SplatSize = SplatBitSize / 8;
5798 // First, handle single instruction cases.
5801 if (SplatBits == 0) {
5802 // Canonicalize all zero vectors to be v4i32.
5803 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5804 SDValue Z = DAG.getConstant(0, MVT::i32);
5805 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5806 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5811 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5812 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5814 if (SextVal >= -16 && SextVal <= 15)
5815 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5818 // Two instruction sequences.
5820 // If this value is in the range [-32,30] and is even, use:
5821 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5822 // If this value is in the range [17,31] and is odd, use:
5823 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5824 // If this value is in the range [-31,-17] and is odd, use:
5825 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5826 // Note the last two are three-instruction sequences.
5827 if (SextVal >= -32 && SextVal <= 31) {
5828 // To avoid having these optimizations undone by constant folding,
5829 // we convert to a pseudo that will be expanded later into one of
5831 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5832 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5833 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5834 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5835 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5836 if (VT == Op.getValueType())
5839 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5842 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5843 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5845 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5846 // Make -1 and vspltisw -1:
5847 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5849 // Make the VSLW intrinsic, computing 0x8000_0000.
5850 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5853 // xor by OnesV to invert it.
5854 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5855 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5858 // The remaining cases assume either big endian element order or
5859 // a splat-size that equates to the element size of the vector
5860 // to be built. An example that doesn't work for little endian is
5861 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5862 // and a vector element size of 16 bits. The code below will
5863 // produce the vector in big endian element order, which for little
5864 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5866 // For now, just avoid these optimizations in that case.
5867 // FIXME: Develop correct optimizations for LE with mismatched
5868 // splat and element sizes.
5870 if (Subtarget.isLittleEndian() &&
5871 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5874 // Check to see if this is a wide variety of vsplti*, binop self cases.
5875 static const signed char SplatCsts[] = {
5876 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5877 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5880 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5881 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5882 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5883 int i = SplatCsts[idx];
5885 // Figure out what shift amount will be used by altivec if shifted by i in
5887 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5889 // vsplti + shl self.
5890 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5891 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5892 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5893 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5894 Intrinsic::ppc_altivec_vslw
5896 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5897 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5900 // vsplti + srl self.
5901 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5902 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5903 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5904 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5905 Intrinsic::ppc_altivec_vsrw
5907 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5908 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5911 // vsplti + sra self.
5912 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5913 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5914 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5915 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5916 Intrinsic::ppc_altivec_vsraw
5918 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5919 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5922 // vsplti + rol self.
5923 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5924 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5925 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5926 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5927 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5928 Intrinsic::ppc_altivec_vrlw
5930 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5931 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5934 // t = vsplti c, result = vsldoi t, t, 1
5935 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5936 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5937 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5939 // t = vsplti c, result = vsldoi t, t, 2
5940 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5941 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5942 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5944 // t = vsplti c, result = vsldoi t, t, 3
5945 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5946 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5947 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5954 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5955 /// the specified operations to build the shuffle.
5956 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5957 SDValue RHS, SelectionDAG &DAG,
5959 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5960 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5961 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5964 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5976 if (OpNum == OP_COPY) {
5977 if (LHSID == (1*9+2)*9+3) return LHS;
5978 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5982 SDValue OpLHS, OpRHS;
5983 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5984 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5988 default: llvm_unreachable("Unknown i32 permute!");
5990 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5991 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5992 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5993 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5996 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5997 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5998 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5999 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6002 for (unsigned i = 0; i != 16; ++i)
6003 ShufIdxs[i] = (i&3)+0;
6006 for (unsigned i = 0; i != 16; ++i)
6007 ShufIdxs[i] = (i&3)+4;
6010 for (unsigned i = 0; i != 16; ++i)
6011 ShufIdxs[i] = (i&3)+8;
6014 for (unsigned i = 0; i != 16; ++i)
6015 ShufIdxs[i] = (i&3)+12;
6018 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6020 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6022 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6024 EVT VT = OpLHS.getValueType();
6025 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6026 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6027 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6028 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6031 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6032 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6033 /// return the code it can be lowered into. Worst case, it can always be
6034 /// lowered into a vperm.
6035 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6036 SelectionDAG &DAG) const {
6038 SDValue V1 = Op.getOperand(0);
6039 SDValue V2 = Op.getOperand(1);
6040 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6041 EVT VT = Op.getValueType();
6042 bool isLittleEndian = Subtarget.isLittleEndian();
6044 // Cases that are handled by instructions that take permute immediates
6045 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6046 // selected by the instruction selector.
6047 if (V2.getOpcode() == ISD::UNDEF) {
6048 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6049 PPC::isSplatShuffleMask(SVOp, 2) ||
6050 PPC::isSplatShuffleMask(SVOp, 4) ||
6051 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6052 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6053 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
6054 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6055 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6056 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6057 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6058 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6059 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6064 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6065 // and produce a fixed permutation. If any of these match, do not lower to
6067 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6068 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6069 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6070 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
6071 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6072 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6073 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6074 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6075 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6076 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6079 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6080 // perfect shuffle table to emit an optimal matching sequence.
6081 ArrayRef<int> PermMask = SVOp->getMask();
6083 unsigned PFIndexes[4];
6084 bool isFourElementShuffle = true;
6085 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6086 unsigned EltNo = 8; // Start out undef.
6087 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6088 if (PermMask[i*4+j] < 0)
6089 continue; // Undef, ignore it.
6091 unsigned ByteSource = PermMask[i*4+j];
6092 if ((ByteSource & 3) != j) {
6093 isFourElementShuffle = false;
6098 EltNo = ByteSource/4;
6099 } else if (EltNo != ByteSource/4) {
6100 isFourElementShuffle = false;
6104 PFIndexes[i] = EltNo;
6107 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6108 // perfect shuffle vector to determine if it is cost effective to do this as
6109 // discrete instructions, or whether we should use a vperm.
6110 // For now, we skip this for little endian until such time as we have a
6111 // little-endian perfect shuffle table.
6112 if (isFourElementShuffle && !isLittleEndian) {
6113 // Compute the index in the perfect shuffle table.
6114 unsigned PFTableIndex =
6115 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6117 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6118 unsigned Cost = (PFEntry >> 30);
6120 // Determining when to avoid vperm is tricky. Many things affect the cost
6121 // of vperm, particularly how many times the perm mask needs to be computed.
6122 // For example, if the perm mask can be hoisted out of a loop or is already
6123 // used (perhaps because there are multiple permutes with the same shuffle
6124 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6125 // the loop requires an extra register.
6127 // As a compromise, we only emit discrete instructions if the shuffle can be
6128 // generated in 3 or fewer operations. When we have loop information
6129 // available, if this block is within a loop, we should avoid using vperm
6130 // for 3-operation perms and use a constant pool load instead.
6132 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6135 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6136 // vector that will get spilled to the constant pool.
6137 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6139 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6140 // that it is in input element units, not in bytes. Convert now.
6142 // For little endian, the order of the input vectors is reversed, and
6143 // the permutation mask is complemented with respect to 31. This is
6144 // necessary to produce proper semantics with the big-endian-biased vperm
6146 EVT EltVT = V1.getValueType().getVectorElementType();
6147 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6149 SmallVector<SDValue, 16> ResultMask;
6150 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6151 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6153 for (unsigned j = 0; j != BytesPerElement; ++j)
6155 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6158 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6162 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6165 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6168 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6172 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6173 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6174 /// information about the intrinsic.
6175 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6177 unsigned IntrinsicID =
6178 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6181 switch (IntrinsicID) {
6182 default: return false;
6183 // Comparison predicates.
6184 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6185 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6186 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6187 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6188 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6189 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6190 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6191 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6192 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6193 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6194 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6195 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6196 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6198 // Normal Comparisons.
6199 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6200 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6201 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6202 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6203 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6204 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6205 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6206 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6207 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6208 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6209 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6210 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6211 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6216 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6217 /// lower, do it, otherwise return null.
6218 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6219 SelectionDAG &DAG) const {
6220 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6221 // opcode number of the comparison.
6225 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6226 return SDValue(); // Don't custom lower most intrinsics.
6228 // If this is a non-dot comparison, make the VCMP node and we are done.
6230 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6231 Op.getOperand(1), Op.getOperand(2),
6232 DAG.getConstant(CompareOpc, MVT::i32));
6233 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6236 // Create the PPCISD altivec 'dot' comparison node.
6238 Op.getOperand(2), // LHS
6239 Op.getOperand(3), // RHS
6240 DAG.getConstant(CompareOpc, MVT::i32)
6242 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6243 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6245 // Now that we have the comparison, emit a copy from the CR to a GPR.
6246 // This is flagged to the above dot comparison.
6247 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6248 DAG.getRegister(PPC::CR6, MVT::i32),
6249 CompNode.getValue(1));
6251 // Unpack the result based on how the target uses it.
6252 unsigned BitNo; // Bit # of CR6.
6253 bool InvertBit; // Invert result?
6254 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6255 default: // Can't happen, don't crash on invalid number though.
6256 case 0: // Return the value of the EQ bit of CR6.
6257 BitNo = 0; InvertBit = false;
6259 case 1: // Return the inverted value of the EQ bit of CR6.
6260 BitNo = 0; InvertBit = true;
6262 case 2: // Return the value of the LT bit of CR6.
6263 BitNo = 2; InvertBit = false;
6265 case 3: // Return the inverted value of the LT bit of CR6.
6266 BitNo = 2; InvertBit = true;
6270 // Shift the bit into the low position.
6271 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6272 DAG.getConstant(8-(3-BitNo), MVT::i32));
6274 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6275 DAG.getConstant(1, MVT::i32));
6277 // If we are supposed to, toggle the bit.
6279 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6280 DAG.getConstant(1, MVT::i32));
6284 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6285 SelectionDAG &DAG) const {
6287 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6288 // instructions), but for smaller types, we need to first extend up to v2i32
6289 // before doing going farther.
6290 if (Op.getValueType() == MVT::v2i64) {
6291 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6292 if (ExtVT != MVT::v2i32) {
6293 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6294 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6295 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6296 ExtVT.getVectorElementType(), 4)));
6297 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6298 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6299 DAG.getValueType(MVT::v2i32));
6308 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6309 SelectionDAG &DAG) const {
6311 // Create a stack slot that is 16-byte aligned.
6312 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6313 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6314 EVT PtrVT = getPointerTy();
6315 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6317 // Store the input value into Value#0 of the stack slot.
6318 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6319 Op.getOperand(0), FIdx, MachinePointerInfo(),
6322 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6323 false, false, false, 0);
6326 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6328 if (Op.getValueType() == MVT::v4i32) {
6329 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6331 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6332 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6334 SDValue RHSSwap = // = vrlw RHS, 16
6335 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6337 // Shrinkify inputs to v8i16.
6338 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6339 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6340 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6342 // Low parts multiplied together, generating 32-bit results (we ignore the
6344 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6345 LHS, RHS, DAG, dl, MVT::v4i32);
6347 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6348 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6349 // Shift the high parts up 16 bits.
6350 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6352 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6353 } else if (Op.getValueType() == MVT::v8i16) {
6354 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6356 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6358 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6359 LHS, RHS, Zero, DAG, dl);
6360 } else if (Op.getValueType() == MVT::v16i8) {
6361 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6362 bool isLittleEndian = Subtarget.isLittleEndian();
6364 // Multiply the even 8-bit parts, producing 16-bit sums.
6365 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6366 LHS, RHS, DAG, dl, MVT::v8i16);
6367 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6369 // Multiply the odd 8-bit parts, producing 16-bit sums.
6370 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6371 LHS, RHS, DAG, dl, MVT::v8i16);
6372 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6374 // Merge the results together. Because vmuleub and vmuloub are
6375 // instructions with a big-endian bias, we must reverse the
6376 // element numbering and reverse the meaning of "odd" and "even"
6377 // when generating little endian code.
6379 for (unsigned i = 0; i != 8; ++i) {
6380 if (isLittleEndian) {
6382 Ops[i*2+1] = 2*i+16;
6385 Ops[i*2+1] = 2*i+1+16;
6389 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6391 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6393 llvm_unreachable("Unknown mul to lower!");
6397 /// LowerOperation - Provide custom lowering hooks for some operations.
6399 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6400 switch (Op.getOpcode()) {
6401 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6402 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6403 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6404 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6405 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6406 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6407 case ISD::SETCC: return LowerSETCC(Op, DAG);
6408 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6409 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6411 return LowerVASTART(Op, DAG, Subtarget);
6414 return LowerVAARG(Op, DAG, Subtarget);
6417 return LowerVACOPY(Op, DAG, Subtarget);
6419 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6420 case ISD::DYNAMIC_STACKALLOC:
6421 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6423 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6424 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6426 case ISD::LOAD: return LowerLOAD(Op, DAG);
6427 case ISD::STORE: return LowerSTORE(Op, DAG);
6428 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6429 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6430 case ISD::FP_TO_UINT:
6431 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6433 case ISD::UINT_TO_FP:
6434 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6435 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6437 // Lower 64-bit shifts.
6438 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6439 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6440 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6442 // Vector-related lowering.
6443 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6444 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6445 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6446 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6447 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6448 case ISD::MUL: return LowerMUL(Op, DAG);
6450 // For counter-based loop handling.
6451 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6453 // Frame & Return address.
6454 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6455 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6459 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6460 SmallVectorImpl<SDValue>&Results,
6461 SelectionDAG &DAG) const {
6462 const TargetMachine &TM = getTargetMachine();
6464 switch (N->getOpcode()) {
6466 llvm_unreachable("Do not know how to custom type legalize this operation!");
6467 case ISD::INTRINSIC_W_CHAIN: {
6468 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6469 Intrinsic::ppc_is_decremented_ctr_nonzero)
6472 assert(N->getValueType(0) == MVT::i1 &&
6473 "Unexpected result type for CTR decrement intrinsic");
6474 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6475 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6476 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6479 Results.push_back(NewInt);
6480 Results.push_back(NewInt.getValue(1));
6484 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6485 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6488 EVT VT = N->getValueType(0);
6490 if (VT == MVT::i64) {
6491 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6493 Results.push_back(NewNode);
6494 Results.push_back(NewNode.getValue(1));
6498 case ISD::FP_ROUND_INREG: {
6499 assert(N->getValueType(0) == MVT::ppcf128);
6500 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6501 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6502 MVT::f64, N->getOperand(0),
6503 DAG.getIntPtrConstant(0));
6504 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6505 MVT::f64, N->getOperand(0),
6506 DAG.getIntPtrConstant(1));
6508 // Add the two halves of the long double in round-to-zero mode.
6509 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6511 // We know the low half is about to be thrown away, so just use something
6513 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6517 case ISD::FP_TO_SINT:
6518 // LowerFP_TO_INT() can only handle f32 and f64.
6519 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6521 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6527 //===----------------------------------------------------------------------===//
6528 // Other Lowering Code
6529 //===----------------------------------------------------------------------===//
6532 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6533 bool is64bit, unsigned BinOpcode) const {
6534 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6535 const TargetInstrInfo *TII =
6536 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6538 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6539 MachineFunction *F = BB->getParent();
6540 MachineFunction::iterator It = BB;
6543 unsigned dest = MI->getOperand(0).getReg();
6544 unsigned ptrA = MI->getOperand(1).getReg();
6545 unsigned ptrB = MI->getOperand(2).getReg();
6546 unsigned incr = MI->getOperand(3).getReg();
6547 DebugLoc dl = MI->getDebugLoc();
6549 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6550 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6551 F->insert(It, loopMBB);
6552 F->insert(It, exitMBB);
6553 exitMBB->splice(exitMBB->begin(), BB,
6554 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6555 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6557 MachineRegisterInfo &RegInfo = F->getRegInfo();
6558 unsigned TmpReg = (!BinOpcode) ? incr :
6559 RegInfo.createVirtualRegister(
6560 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6561 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6565 // fallthrough --> loopMBB
6566 BB->addSuccessor(loopMBB);
6569 // l[wd]arx dest, ptr
6570 // add r0, dest, incr
6571 // st[wd]cx. r0, ptr
6573 // fallthrough --> exitMBB
6575 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6576 .addReg(ptrA).addReg(ptrB);
6578 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6579 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6580 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6581 BuildMI(BB, dl, TII->get(PPC::BCC))
6582 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6583 BB->addSuccessor(loopMBB);
6584 BB->addSuccessor(exitMBB);
6593 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6594 MachineBasicBlock *BB,
6595 bool is8bit, // operation
6596 unsigned BinOpcode) const {
6597 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6598 const TargetInstrInfo *TII =
6599 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6600 // In 64 bit mode we have to use 64 bits for addresses, even though the
6601 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6602 // registers without caring whether they're 32 or 64, but here we're
6603 // doing actual arithmetic on the addresses.
6604 bool is64bit = Subtarget.isPPC64();
6605 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6607 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6608 MachineFunction *F = BB->getParent();
6609 MachineFunction::iterator It = BB;
6612 unsigned dest = MI->getOperand(0).getReg();
6613 unsigned ptrA = MI->getOperand(1).getReg();
6614 unsigned ptrB = MI->getOperand(2).getReg();
6615 unsigned incr = MI->getOperand(3).getReg();
6616 DebugLoc dl = MI->getDebugLoc();
6618 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6619 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6620 F->insert(It, loopMBB);
6621 F->insert(It, exitMBB);
6622 exitMBB->splice(exitMBB->begin(), BB,
6623 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6624 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6626 MachineRegisterInfo &RegInfo = F->getRegInfo();
6627 const TargetRegisterClass *RC =
6628 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6629 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6630 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6631 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6632 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6633 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6634 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6635 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6636 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6637 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6638 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6639 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6640 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6642 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6646 // fallthrough --> loopMBB
6647 BB->addSuccessor(loopMBB);
6649 // The 4-byte load must be aligned, while a char or short may be
6650 // anywhere in the word. Hence all this nasty bookkeeping code.
6651 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6652 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6653 // xori shift, shift1, 24 [16]
6654 // rlwinm ptr, ptr1, 0, 0, 29
6655 // slw incr2, incr, shift
6656 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6657 // slw mask, mask2, shift
6659 // lwarx tmpDest, ptr
6660 // add tmp, tmpDest, incr2
6661 // andc tmp2, tmpDest, mask
6662 // and tmp3, tmp, mask
6663 // or tmp4, tmp3, tmp2
6666 // fallthrough --> exitMBB
6667 // srw dest, tmpDest, shift
6668 if (ptrA != ZeroReg) {
6669 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6670 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6671 .addReg(ptrA).addReg(ptrB);
6675 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6676 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6677 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6678 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6680 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6681 .addReg(Ptr1Reg).addImm(0).addImm(61);
6683 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6684 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6685 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6686 .addReg(incr).addReg(ShiftReg);
6688 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6690 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6691 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6693 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6694 .addReg(Mask2Reg).addReg(ShiftReg);
6697 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6698 .addReg(ZeroReg).addReg(PtrReg);
6700 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6701 .addReg(Incr2Reg).addReg(TmpDestReg);
6702 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6703 .addReg(TmpDestReg).addReg(MaskReg);
6704 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6705 .addReg(TmpReg).addReg(MaskReg);
6706 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6707 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6708 BuildMI(BB, dl, TII->get(PPC::STWCX))
6709 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6710 BuildMI(BB, dl, TII->get(PPC::BCC))
6711 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6712 BB->addSuccessor(loopMBB);
6713 BB->addSuccessor(exitMBB);
6718 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6723 llvm::MachineBasicBlock*
6724 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6725 MachineBasicBlock *MBB) const {
6726 DebugLoc DL = MI->getDebugLoc();
6727 const TargetInstrInfo *TII =
6728 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6730 MachineFunction *MF = MBB->getParent();
6731 MachineRegisterInfo &MRI = MF->getRegInfo();
6733 const BasicBlock *BB = MBB->getBasicBlock();
6734 MachineFunction::iterator I = MBB;
6738 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6739 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6741 unsigned DstReg = MI->getOperand(0).getReg();
6742 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6743 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6744 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6745 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6747 MVT PVT = getPointerTy();
6748 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6749 "Invalid Pointer Size!");
6750 // For v = setjmp(buf), we generate
6753 // SjLjSetup mainMBB
6759 // buf[LabelOffset] = LR
6763 // v = phi(main, restore)
6766 MachineBasicBlock *thisMBB = MBB;
6767 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6768 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6769 MF->insert(I, mainMBB);
6770 MF->insert(I, sinkMBB);
6772 MachineInstrBuilder MIB;
6774 // Transfer the remainder of BB and its successor edges to sinkMBB.
6775 sinkMBB->splice(sinkMBB->begin(), MBB,
6776 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6777 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6779 // Note that the structure of the jmp_buf used here is not compatible
6780 // with that used by libc, and is not designed to be. Specifically, it
6781 // stores only those 'reserved' registers that LLVM does not otherwise
6782 // understand how to spill. Also, by convention, by the time this
6783 // intrinsic is called, Clang has already stored the frame address in the
6784 // first slot of the buffer and stack address in the third. Following the
6785 // X86 target code, we'll store the jump address in the second slot. We also
6786 // need to save the TOC pointer (R2) to handle jumps between shared
6787 // libraries, and that will be stored in the fourth slot. The thread
6788 // identifier (R13) is not affected.
6791 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6792 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6793 const int64_t BPOffset = 4 * PVT.getStoreSize();
6795 // Prepare IP either in reg.
6796 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6797 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6798 unsigned BufReg = MI->getOperand(1).getReg();
6800 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6801 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6805 MIB.setMemRefs(MMOBegin, MMOEnd);
6808 // Naked functions never have a base pointer, and so we use r1. For all
6809 // other functions, this decision must be delayed until during PEI.
6811 if (MF->getFunction()->getAttributes().hasAttribute(
6812 AttributeSet::FunctionIndex, Attribute::Naked))
6813 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6815 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6817 MIB = BuildMI(*thisMBB, MI, DL,
6818 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6822 MIB.setMemRefs(MMOBegin, MMOEnd);
6825 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6826 const PPCRegisterInfo *TRI =
6827 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6828 MIB.addRegMask(TRI->getNoPreservedMask());
6830 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6832 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6834 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6836 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6837 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6841 MIB = BuildMI(mainMBB, DL,
6842 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6845 if (Subtarget.isPPC64()) {
6846 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6848 .addImm(LabelOffset)
6851 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6853 .addImm(LabelOffset)
6857 MIB.setMemRefs(MMOBegin, MMOEnd);
6859 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6860 mainMBB->addSuccessor(sinkMBB);
6863 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6864 TII->get(PPC::PHI), DstReg)
6865 .addReg(mainDstReg).addMBB(mainMBB)
6866 .addReg(restoreDstReg).addMBB(thisMBB);
6868 MI->eraseFromParent();
6873 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6874 MachineBasicBlock *MBB) const {
6875 DebugLoc DL = MI->getDebugLoc();
6876 const TargetInstrInfo *TII =
6877 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6879 MachineFunction *MF = MBB->getParent();
6880 MachineRegisterInfo &MRI = MF->getRegInfo();
6883 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6884 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6886 MVT PVT = getPointerTy();
6887 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6888 "Invalid Pointer Size!");
6890 const TargetRegisterClass *RC =
6891 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6892 unsigned Tmp = MRI.createVirtualRegister(RC);
6893 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6894 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6895 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6896 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6897 (Subtarget.isSVR4ABI() &&
6898 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6899 PPC::R29 : PPC::R30);
6901 MachineInstrBuilder MIB;
6903 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6904 const int64_t SPOffset = 2 * PVT.getStoreSize();
6905 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6906 const int64_t BPOffset = 4 * PVT.getStoreSize();
6908 unsigned BufReg = MI->getOperand(0).getReg();
6910 // Reload FP (the jumped-to function may not have had a
6911 // frame pointer, and if so, then its r31 will be restored
6913 if (PVT == MVT::i64) {
6914 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6918 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6922 MIB.setMemRefs(MMOBegin, MMOEnd);
6925 if (PVT == MVT::i64) {
6926 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6927 .addImm(LabelOffset)
6930 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6931 .addImm(LabelOffset)
6934 MIB.setMemRefs(MMOBegin, MMOEnd);
6937 if (PVT == MVT::i64) {
6938 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6942 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6946 MIB.setMemRefs(MMOBegin, MMOEnd);
6949 if (PVT == MVT::i64) {
6950 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6954 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6958 MIB.setMemRefs(MMOBegin, MMOEnd);
6961 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6962 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6966 MIB.setMemRefs(MMOBegin, MMOEnd);
6970 BuildMI(*MBB, MI, DL,
6971 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6972 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6974 MI->eraseFromParent();
6979 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6980 MachineBasicBlock *BB) const {
6981 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6982 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6983 return emitEHSjLjSetJmp(MI, BB);
6984 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6985 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6986 return emitEHSjLjLongJmp(MI, BB);
6989 const TargetInstrInfo *TII =
6990 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6992 // To "insert" these instructions we actually have to insert their
6993 // control-flow patterns.
6994 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6995 MachineFunction::iterator It = BB;
6998 MachineFunction *F = BB->getParent();
7000 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7001 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7002 MI->getOpcode() == PPC::SELECT_I4 ||
7003 MI->getOpcode() == PPC::SELECT_I8)) {
7004 SmallVector<MachineOperand, 2> Cond;
7005 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7006 MI->getOpcode() == PPC::SELECT_CC_I8)
7007 Cond.push_back(MI->getOperand(4));
7009 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7010 Cond.push_back(MI->getOperand(1));
7012 DebugLoc dl = MI->getDebugLoc();
7013 const TargetInstrInfo *TII =
7014 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7015 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7016 Cond, MI->getOperand(2).getReg(),
7017 MI->getOperand(3).getReg());
7018 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7019 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7020 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7021 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7022 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7023 MI->getOpcode() == PPC::SELECT_I4 ||
7024 MI->getOpcode() == PPC::SELECT_I8 ||
7025 MI->getOpcode() == PPC::SELECT_F4 ||
7026 MI->getOpcode() == PPC::SELECT_F8 ||
7027 MI->getOpcode() == PPC::SELECT_VRRC) {
7028 // The incoming instruction knows the destination vreg to set, the
7029 // condition code register to branch on, the true/false values to
7030 // select between, and a branch opcode to use.
7035 // cmpTY ccX, r1, r2
7037 // fallthrough --> copy0MBB
7038 MachineBasicBlock *thisMBB = BB;
7039 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7040 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7041 DebugLoc dl = MI->getDebugLoc();
7042 F->insert(It, copy0MBB);
7043 F->insert(It, sinkMBB);
7045 // Transfer the remainder of BB and its successor edges to sinkMBB.
7046 sinkMBB->splice(sinkMBB->begin(), BB,
7047 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7048 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7050 // Next, add the true and fallthrough blocks as its successors.
7051 BB->addSuccessor(copy0MBB);
7052 BB->addSuccessor(sinkMBB);
7054 if (MI->getOpcode() == PPC::SELECT_I4 ||
7055 MI->getOpcode() == PPC::SELECT_I8 ||
7056 MI->getOpcode() == PPC::SELECT_F4 ||
7057 MI->getOpcode() == PPC::SELECT_F8 ||
7058 MI->getOpcode() == PPC::SELECT_VRRC) {
7059 BuildMI(BB, dl, TII->get(PPC::BC))
7060 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7062 unsigned SelectPred = MI->getOperand(4).getImm();
7063 BuildMI(BB, dl, TII->get(PPC::BCC))
7064 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7068 // %FalseValue = ...
7069 // # fallthrough to sinkMBB
7072 // Update machine-CFG edges
7073 BB->addSuccessor(sinkMBB);
7076 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7079 BuildMI(*BB, BB->begin(), dl,
7080 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7081 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7082 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7084 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7085 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7086 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7087 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7088 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7089 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7090 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7091 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7093 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7094 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7095 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7096 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7097 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7098 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7099 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7100 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7102 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7103 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7104 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7105 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7106 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7107 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7108 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7109 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7111 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7112 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7113 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7114 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7115 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7116 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7117 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7118 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7120 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7121 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7122 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7123 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7124 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7125 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7126 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7127 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7129 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7130 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7131 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7132 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7133 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7134 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7135 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7136 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7138 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7139 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7140 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7141 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7142 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7143 BB = EmitAtomicBinary(MI, BB, false, 0);
7144 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7145 BB = EmitAtomicBinary(MI, BB, true, 0);
7147 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7148 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7149 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7151 unsigned dest = MI->getOperand(0).getReg();
7152 unsigned ptrA = MI->getOperand(1).getReg();
7153 unsigned ptrB = MI->getOperand(2).getReg();
7154 unsigned oldval = MI->getOperand(3).getReg();
7155 unsigned newval = MI->getOperand(4).getReg();
7156 DebugLoc dl = MI->getDebugLoc();
7158 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7159 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7160 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7161 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7162 F->insert(It, loop1MBB);
7163 F->insert(It, loop2MBB);
7164 F->insert(It, midMBB);
7165 F->insert(It, exitMBB);
7166 exitMBB->splice(exitMBB->begin(), BB,
7167 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7168 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7172 // fallthrough --> loopMBB
7173 BB->addSuccessor(loop1MBB);
7176 // l[wd]arx dest, ptr
7177 // cmp[wd] dest, oldval
7180 // st[wd]cx. newval, ptr
7184 // st[wd]cx. dest, ptr
7187 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7188 .addReg(ptrA).addReg(ptrB);
7189 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7190 .addReg(oldval).addReg(dest);
7191 BuildMI(BB, dl, TII->get(PPC::BCC))
7192 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7193 BB->addSuccessor(loop2MBB);
7194 BB->addSuccessor(midMBB);
7197 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7198 .addReg(newval).addReg(ptrA).addReg(ptrB);
7199 BuildMI(BB, dl, TII->get(PPC::BCC))
7200 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7201 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7202 BB->addSuccessor(loop1MBB);
7203 BB->addSuccessor(exitMBB);
7206 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7207 .addReg(dest).addReg(ptrA).addReg(ptrB);
7208 BB->addSuccessor(exitMBB);
7213 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7214 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7215 // We must use 64-bit registers for addresses when targeting 64-bit,
7216 // since we're actually doing arithmetic on them. Other registers
7218 bool is64bit = Subtarget.isPPC64();
7219 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7221 unsigned dest = MI->getOperand(0).getReg();
7222 unsigned ptrA = MI->getOperand(1).getReg();
7223 unsigned ptrB = MI->getOperand(2).getReg();
7224 unsigned oldval = MI->getOperand(3).getReg();
7225 unsigned newval = MI->getOperand(4).getReg();
7226 DebugLoc dl = MI->getDebugLoc();
7228 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7229 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7230 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7231 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7232 F->insert(It, loop1MBB);
7233 F->insert(It, loop2MBB);
7234 F->insert(It, midMBB);
7235 F->insert(It, exitMBB);
7236 exitMBB->splice(exitMBB->begin(), BB,
7237 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7238 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7240 MachineRegisterInfo &RegInfo = F->getRegInfo();
7241 const TargetRegisterClass *RC =
7242 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7243 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7244 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7245 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7246 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7247 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7248 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7249 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7250 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7251 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7252 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7253 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7254 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7255 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7256 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7258 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7259 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7262 // fallthrough --> loopMBB
7263 BB->addSuccessor(loop1MBB);
7265 // The 4-byte load must be aligned, while a char or short may be
7266 // anywhere in the word. Hence all this nasty bookkeeping code.
7267 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7268 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7269 // xori shift, shift1, 24 [16]
7270 // rlwinm ptr, ptr1, 0, 0, 29
7271 // slw newval2, newval, shift
7272 // slw oldval2, oldval,shift
7273 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7274 // slw mask, mask2, shift
7275 // and newval3, newval2, mask
7276 // and oldval3, oldval2, mask
7278 // lwarx tmpDest, ptr
7279 // and tmp, tmpDest, mask
7280 // cmpw tmp, oldval3
7283 // andc tmp2, tmpDest, mask
7284 // or tmp4, tmp2, newval3
7289 // stwcx. tmpDest, ptr
7291 // srw dest, tmpDest, shift
7292 if (ptrA != ZeroReg) {
7293 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7294 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7295 .addReg(ptrA).addReg(ptrB);
7299 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7300 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7301 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7302 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7304 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7305 .addReg(Ptr1Reg).addImm(0).addImm(61);
7307 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7308 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7309 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7310 .addReg(newval).addReg(ShiftReg);
7311 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7312 .addReg(oldval).addReg(ShiftReg);
7314 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7316 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7317 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7318 .addReg(Mask3Reg).addImm(65535);
7320 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7321 .addReg(Mask2Reg).addReg(ShiftReg);
7322 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7323 .addReg(NewVal2Reg).addReg(MaskReg);
7324 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7325 .addReg(OldVal2Reg).addReg(MaskReg);
7328 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7329 .addReg(ZeroReg).addReg(PtrReg);
7330 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7331 .addReg(TmpDestReg).addReg(MaskReg);
7332 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7333 .addReg(TmpReg).addReg(OldVal3Reg);
7334 BuildMI(BB, dl, TII->get(PPC::BCC))
7335 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7336 BB->addSuccessor(loop2MBB);
7337 BB->addSuccessor(midMBB);
7340 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7341 .addReg(TmpDestReg).addReg(MaskReg);
7342 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7343 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7344 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7345 .addReg(ZeroReg).addReg(PtrReg);
7346 BuildMI(BB, dl, TII->get(PPC::BCC))
7347 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7348 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7349 BB->addSuccessor(loop1MBB);
7350 BB->addSuccessor(exitMBB);
7353 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7354 .addReg(ZeroReg).addReg(PtrReg);
7355 BB->addSuccessor(exitMBB);
7360 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7362 } else if (MI->getOpcode() == PPC::FADDrtz) {
7363 // This pseudo performs an FADD with rounding mode temporarily forced
7364 // to round-to-zero. We emit this via custom inserter since the FPSCR
7365 // is not modeled at the SelectionDAG level.
7366 unsigned Dest = MI->getOperand(0).getReg();
7367 unsigned Src1 = MI->getOperand(1).getReg();
7368 unsigned Src2 = MI->getOperand(2).getReg();
7369 DebugLoc dl = MI->getDebugLoc();
7371 MachineRegisterInfo &RegInfo = F->getRegInfo();
7372 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7374 // Save FPSCR value.
7375 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7377 // Set rounding mode to round-to-zero.
7378 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7379 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7381 // Perform addition.
7382 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7384 // Restore FPSCR value.
7385 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7386 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7387 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7388 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7389 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7390 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7391 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7392 PPC::ANDIo8 : PPC::ANDIo;
7393 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7394 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7396 MachineRegisterInfo &RegInfo = F->getRegInfo();
7397 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7398 &PPC::GPRCRegClass :
7399 &PPC::G8RCRegClass);
7401 DebugLoc dl = MI->getDebugLoc();
7402 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7403 .addReg(MI->getOperand(1).getReg()).addImm(1);
7404 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7405 MI->getOperand(0).getReg())
7406 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7408 llvm_unreachable("Unexpected instr type to insert");
7411 MI->eraseFromParent(); // The pseudo instruction is gone now.
7415 //===----------------------------------------------------------------------===//
7416 // Target Optimization Hooks
7417 //===----------------------------------------------------------------------===//
7419 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7420 DAGCombinerInfo &DCI) const {
7421 if (DCI.isAfterLegalizeVectorOps())
7424 EVT VT = Op.getValueType();
7426 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7427 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7428 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7429 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7431 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7432 // For the reciprocal, we need to find the zero of the function:
7433 // F(X) = A X - 1 [which has a zero at X = 1/A]
7435 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7436 // does not require additional intermediate precision]
7438 // Convergence is quadratic, so we essentially double the number of digits
7439 // correct after every iteration. The minimum architected relative
7440 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7441 // 23 digits and double has 52 digits.
7442 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7443 if (VT.getScalarType() == MVT::f64)
7446 SelectionDAG &DAG = DCI.DAG;
7450 DAG.getConstantFP(1.0, VT.getScalarType());
7451 if (VT.isVector()) {
7452 assert(VT.getVectorNumElements() == 4 &&
7453 "Unknown vector type");
7454 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7455 FPOne, FPOne, FPOne, FPOne);
7458 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7459 DCI.AddToWorklist(Est.getNode());
7461 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7462 for (int i = 0; i < Iterations; ++i) {
7463 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7464 DCI.AddToWorklist(NewEst.getNode());
7466 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7467 DCI.AddToWorklist(NewEst.getNode());
7469 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7470 DCI.AddToWorklist(NewEst.getNode());
7472 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7473 DCI.AddToWorklist(Est.getNode());
7482 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7483 DAGCombinerInfo &DCI) const {
7484 if (DCI.isAfterLegalizeVectorOps())
7487 EVT VT = Op.getValueType();
7489 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7490 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7491 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7492 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7494 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7495 // For the reciprocal sqrt, we need to find the zero of the function:
7496 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7498 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7499 // As a result, we precompute A/2 prior to the iteration loop.
7501 // Convergence is quadratic, so we essentially double the number of digits
7502 // correct after every iteration. The minimum architected relative
7503 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7504 // 23 digits and double has 52 digits.
7505 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7506 if (VT.getScalarType() == MVT::f64)
7509 SelectionDAG &DAG = DCI.DAG;
7512 SDValue FPThreeHalves =
7513 DAG.getConstantFP(1.5, VT.getScalarType());
7514 if (VT.isVector()) {
7515 assert(VT.getVectorNumElements() == 4 &&
7516 "Unknown vector type");
7517 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7518 FPThreeHalves, FPThreeHalves,
7519 FPThreeHalves, FPThreeHalves);
7522 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7523 DCI.AddToWorklist(Est.getNode());
7525 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7526 // this entire sequence requires only one FP constant.
7527 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7528 DCI.AddToWorklist(HalfArg.getNode());
7530 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7531 DCI.AddToWorklist(HalfArg.getNode());
7533 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7534 for (int i = 0; i < Iterations; ++i) {
7535 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7536 DCI.AddToWorklist(NewEst.getNode());
7538 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7539 DCI.AddToWorklist(NewEst.getNode());
7541 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7542 DCI.AddToWorklist(NewEst.getNode());
7544 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7545 DCI.AddToWorklist(Est.getNode());
7554 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7555 unsigned Bytes, int Dist,
7556 SelectionDAG &DAG) {
7557 if (VT.getSizeInBits() / 8 != Bytes)
7560 SDValue BaseLoc = Base->getBasePtr();
7561 if (Loc.getOpcode() == ISD::FrameIndex) {
7562 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7564 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7565 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7566 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7567 int FS = MFI->getObjectSize(FI);
7568 int BFS = MFI->getObjectSize(BFI);
7569 if (FS != BFS || FS != (int)Bytes) return false;
7570 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7574 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7575 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7578 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7579 const GlobalValue *GV1 = nullptr;
7580 const GlobalValue *GV2 = nullptr;
7581 int64_t Offset1 = 0;
7582 int64_t Offset2 = 0;
7583 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7584 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7585 if (isGA1 && isGA2 && GV1 == GV2)
7586 return Offset1 == (Offset2 + Dist*Bytes);
7590 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7591 // not enforce equality of the chain operands.
7592 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7593 unsigned Bytes, int Dist,
7594 SelectionDAG &DAG) {
7595 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7596 EVT VT = LS->getMemoryVT();
7597 SDValue Loc = LS->getBasePtr();
7598 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7601 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7603 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7604 default: return false;
7605 case Intrinsic::ppc_altivec_lvx:
7606 case Intrinsic::ppc_altivec_lvxl:
7609 case Intrinsic::ppc_altivec_lvebx:
7612 case Intrinsic::ppc_altivec_lvehx:
7615 case Intrinsic::ppc_altivec_lvewx:
7620 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7623 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7625 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7626 default: return false;
7627 case Intrinsic::ppc_altivec_stvx:
7628 case Intrinsic::ppc_altivec_stvxl:
7631 case Intrinsic::ppc_altivec_stvebx:
7634 case Intrinsic::ppc_altivec_stvehx:
7637 case Intrinsic::ppc_altivec_stvewx:
7642 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7648 // Return true is there is a nearyby consecutive load to the one provided
7649 // (regardless of alignment). We search up and down the chain, looking though
7650 // token factors and other loads (but nothing else). As a result, a true result
7651 // indicates that it is safe to create a new consecutive load adjacent to the
7653 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7654 SDValue Chain = LD->getChain();
7655 EVT VT = LD->getMemoryVT();
7657 SmallSet<SDNode *, 16> LoadRoots;
7658 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7659 SmallSet<SDNode *, 16> Visited;
7661 // First, search up the chain, branching to follow all token-factor operands.
7662 // If we find a consecutive load, then we're done, otherwise, record all
7663 // nodes just above the top-level loads and token factors.
7664 while (!Queue.empty()) {
7665 SDNode *ChainNext = Queue.pop_back_val();
7666 if (!Visited.insert(ChainNext))
7669 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7670 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7673 if (!Visited.count(ChainLD->getChain().getNode()))
7674 Queue.push_back(ChainLD->getChain().getNode());
7675 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7676 for (const SDUse &O : ChainNext->ops())
7677 if (!Visited.count(O.getNode()))
7678 Queue.push_back(O.getNode());
7680 LoadRoots.insert(ChainNext);
7683 // Second, search down the chain, starting from the top-level nodes recorded
7684 // in the first phase. These top-level nodes are the nodes just above all
7685 // loads and token factors. Starting with their uses, recursively look though
7686 // all loads (just the chain uses) and token factors to find a consecutive
7691 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7692 IE = LoadRoots.end(); I != IE; ++I) {
7693 Queue.push_back(*I);
7695 while (!Queue.empty()) {
7696 SDNode *LoadRoot = Queue.pop_back_val();
7697 if (!Visited.insert(LoadRoot))
7700 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7701 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7704 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7705 UE = LoadRoot->use_end(); UI != UE; ++UI)
7706 if (((isa<MemSDNode>(*UI) &&
7707 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7708 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7709 Queue.push_back(*UI);
7716 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7717 DAGCombinerInfo &DCI) const {
7718 SelectionDAG &DAG = DCI.DAG;
7721 assert(Subtarget.useCRBits() &&
7722 "Expecting to be tracking CR bits");
7723 // If we're tracking CR bits, we need to be careful that we don't have:
7724 // trunc(binary-ops(zext(x), zext(y)))
7726 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7727 // such that we're unnecessarily moving things into GPRs when it would be
7728 // better to keep them in CR bits.
7730 // Note that trunc here can be an actual i1 trunc, or can be the effective
7731 // truncation that comes from a setcc or select_cc.
7732 if (N->getOpcode() == ISD::TRUNCATE &&
7733 N->getValueType(0) != MVT::i1)
7736 if (N->getOperand(0).getValueType() != MVT::i32 &&
7737 N->getOperand(0).getValueType() != MVT::i64)
7740 if (N->getOpcode() == ISD::SETCC ||
7741 N->getOpcode() == ISD::SELECT_CC) {
7742 // If we're looking at a comparison, then we need to make sure that the
7743 // high bits (all except for the first) don't matter the result.
7745 cast<CondCodeSDNode>(N->getOperand(
7746 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7747 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7749 if (ISD::isSignedIntSetCC(CC)) {
7750 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7751 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7753 } else if (ISD::isUnsignedIntSetCC(CC)) {
7754 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7755 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7756 !DAG.MaskedValueIsZero(N->getOperand(1),
7757 APInt::getHighBitsSet(OpBits, OpBits-1)))
7760 // This is neither a signed nor an unsigned comparison, just make sure
7761 // that the high bits are equal.
7762 APInt Op1Zero, Op1One;
7763 APInt Op2Zero, Op2One;
7764 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7765 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7767 // We don't really care about what is known about the first bit (if
7768 // anything), so clear it in all masks prior to comparing them.
7769 Op1Zero.clearBit(0); Op1One.clearBit(0);
7770 Op2Zero.clearBit(0); Op2One.clearBit(0);
7772 if (Op1Zero != Op2Zero || Op1One != Op2One)
7777 // We now know that the higher-order bits are irrelevant, we just need to
7778 // make sure that all of the intermediate operations are bit operations, and
7779 // all inputs are extensions.
7780 if (N->getOperand(0).getOpcode() != ISD::AND &&
7781 N->getOperand(0).getOpcode() != ISD::OR &&
7782 N->getOperand(0).getOpcode() != ISD::XOR &&
7783 N->getOperand(0).getOpcode() != ISD::SELECT &&
7784 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7785 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7786 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7787 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7788 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7791 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7792 N->getOperand(1).getOpcode() != ISD::AND &&
7793 N->getOperand(1).getOpcode() != ISD::OR &&
7794 N->getOperand(1).getOpcode() != ISD::XOR &&
7795 N->getOperand(1).getOpcode() != ISD::SELECT &&
7796 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7797 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7798 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7799 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7800 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7803 SmallVector<SDValue, 4> Inputs;
7804 SmallVector<SDValue, 8> BinOps, PromOps;
7805 SmallPtrSet<SDNode *, 16> Visited;
7807 for (unsigned i = 0; i < 2; ++i) {
7808 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7809 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7810 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7811 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7812 isa<ConstantSDNode>(N->getOperand(i)))
7813 Inputs.push_back(N->getOperand(i));
7815 BinOps.push_back(N->getOperand(i));
7817 if (N->getOpcode() == ISD::TRUNCATE)
7821 // Visit all inputs, collect all binary operations (and, or, xor and
7822 // select) that are all fed by extensions.
7823 while (!BinOps.empty()) {
7824 SDValue BinOp = BinOps.back();
7827 if (!Visited.insert(BinOp.getNode()))
7830 PromOps.push_back(BinOp);
7832 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7833 // The condition of the select is not promoted.
7834 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7836 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7839 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7840 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7841 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7842 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7843 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7844 Inputs.push_back(BinOp.getOperand(i));
7845 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7846 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7847 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7848 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7849 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7850 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7851 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7852 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7853 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7854 BinOps.push_back(BinOp.getOperand(i));
7856 // We have an input that is not an extension or another binary
7857 // operation; we'll abort this transformation.
7863 // Make sure that this is a self-contained cluster of operations (which
7864 // is not quite the same thing as saying that everything has only one
7866 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7867 if (isa<ConstantSDNode>(Inputs[i]))
7870 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7871 UE = Inputs[i].getNode()->use_end();
7874 if (User != N && !Visited.count(User))
7877 // Make sure that we're not going to promote the non-output-value
7878 // operand(s) or SELECT or SELECT_CC.
7879 // FIXME: Although we could sometimes handle this, and it does occur in
7880 // practice that one of the condition inputs to the select is also one of
7881 // the outputs, we currently can't deal with this.
7882 if (User->getOpcode() == ISD::SELECT) {
7883 if (User->getOperand(0) == Inputs[i])
7885 } else if (User->getOpcode() == ISD::SELECT_CC) {
7886 if (User->getOperand(0) == Inputs[i] ||
7887 User->getOperand(1) == Inputs[i])
7893 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7894 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7895 UE = PromOps[i].getNode()->use_end();
7898 if (User != N && !Visited.count(User))
7901 // Make sure that we're not going to promote the non-output-value
7902 // operand(s) or SELECT or SELECT_CC.
7903 // FIXME: Although we could sometimes handle this, and it does occur in
7904 // practice that one of the condition inputs to the select is also one of
7905 // the outputs, we currently can't deal with this.
7906 if (User->getOpcode() == ISD::SELECT) {
7907 if (User->getOperand(0) == PromOps[i])
7909 } else if (User->getOpcode() == ISD::SELECT_CC) {
7910 if (User->getOperand(0) == PromOps[i] ||
7911 User->getOperand(1) == PromOps[i])
7917 // Replace all inputs with the extension operand.
7918 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7919 // Constants may have users outside the cluster of to-be-promoted nodes,
7920 // and so we need to replace those as we do the promotions.
7921 if (isa<ConstantSDNode>(Inputs[i]))
7924 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7927 // Replace all operations (these are all the same, but have a different
7928 // (i1) return type). DAG.getNode will validate that the types of
7929 // a binary operator match, so go through the list in reverse so that
7930 // we've likely promoted both operands first. Any intermediate truncations or
7931 // extensions disappear.
7932 while (!PromOps.empty()) {
7933 SDValue PromOp = PromOps.back();
7936 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7937 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7938 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7939 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7940 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7941 PromOp.getOperand(0).getValueType() != MVT::i1) {
7942 // The operand is not yet ready (see comment below).
7943 PromOps.insert(PromOps.begin(), PromOp);
7947 SDValue RepValue = PromOp.getOperand(0);
7948 if (isa<ConstantSDNode>(RepValue))
7949 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7951 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7956 switch (PromOp.getOpcode()) {
7957 default: C = 0; break;
7958 case ISD::SELECT: C = 1; break;
7959 case ISD::SELECT_CC: C = 2; break;
7962 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7963 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7964 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7965 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7966 // The to-be-promoted operands of this node have not yet been
7967 // promoted (this should be rare because we're going through the
7968 // list backward, but if one of the operands has several users in
7969 // this cluster of to-be-promoted nodes, it is possible).
7970 PromOps.insert(PromOps.begin(), PromOp);
7974 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7975 PromOp.getNode()->op_end());
7977 // If there are any constant inputs, make sure they're replaced now.
7978 for (unsigned i = 0; i < 2; ++i)
7979 if (isa<ConstantSDNode>(Ops[C+i]))
7980 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7982 DAG.ReplaceAllUsesOfValueWith(PromOp,
7983 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7986 // Now we're left with the initial truncation itself.
7987 if (N->getOpcode() == ISD::TRUNCATE)
7988 return N->getOperand(0);
7990 // Otherwise, this is a comparison. The operands to be compared have just
7991 // changed type (to i1), but everything else is the same.
7992 return SDValue(N, 0);
7995 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7996 DAGCombinerInfo &DCI) const {
7997 SelectionDAG &DAG = DCI.DAG;
8000 // If we're tracking CR bits, we need to be careful that we don't have:
8001 // zext(binary-ops(trunc(x), trunc(y)))
8003 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8004 // such that we're unnecessarily moving things into CR bits that can more
8005 // efficiently stay in GPRs. Note that if we're not certain that the high
8006 // bits are set as required by the final extension, we still may need to do
8007 // some masking to get the proper behavior.
8009 // This same functionality is important on PPC64 when dealing with
8010 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8011 // the return values of functions. Because it is so similar, it is handled
8014 if (N->getValueType(0) != MVT::i32 &&
8015 N->getValueType(0) != MVT::i64)
8018 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8019 Subtarget.useCRBits()) ||
8020 (N->getOperand(0).getValueType() == MVT::i32 &&
8021 Subtarget.isPPC64())))
8024 if (N->getOperand(0).getOpcode() != ISD::AND &&
8025 N->getOperand(0).getOpcode() != ISD::OR &&
8026 N->getOperand(0).getOpcode() != ISD::XOR &&
8027 N->getOperand(0).getOpcode() != ISD::SELECT &&
8028 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8031 SmallVector<SDValue, 4> Inputs;
8032 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8033 SmallPtrSet<SDNode *, 16> Visited;
8035 // Visit all inputs, collect all binary operations (and, or, xor and
8036 // select) that are all fed by truncations.
8037 while (!BinOps.empty()) {
8038 SDValue BinOp = BinOps.back();
8041 if (!Visited.insert(BinOp.getNode()))
8044 PromOps.push_back(BinOp);
8046 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8047 // The condition of the select is not promoted.
8048 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8050 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8053 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8054 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8055 Inputs.push_back(BinOp.getOperand(i));
8056 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8057 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8058 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8059 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8060 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8061 BinOps.push_back(BinOp.getOperand(i));
8063 // We have an input that is not a truncation or another binary
8064 // operation; we'll abort this transformation.
8070 // Make sure that this is a self-contained cluster of operations (which
8071 // is not quite the same thing as saying that everything has only one
8073 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8074 if (isa<ConstantSDNode>(Inputs[i]))
8077 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8078 UE = Inputs[i].getNode()->use_end();
8081 if (User != N && !Visited.count(User))
8084 // Make sure that we're not going to promote the non-output-value
8085 // operand(s) or SELECT or SELECT_CC.
8086 // FIXME: Although we could sometimes handle this, and it does occur in
8087 // practice that one of the condition inputs to the select is also one of
8088 // the outputs, we currently can't deal with this.
8089 if (User->getOpcode() == ISD::SELECT) {
8090 if (User->getOperand(0) == Inputs[i])
8092 } else if (User->getOpcode() == ISD::SELECT_CC) {
8093 if (User->getOperand(0) == Inputs[i] ||
8094 User->getOperand(1) == Inputs[i])
8100 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8101 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8102 UE = PromOps[i].getNode()->use_end();
8105 if (User != N && !Visited.count(User))
8108 // Make sure that we're not going to promote the non-output-value
8109 // operand(s) or SELECT or SELECT_CC.
8110 // FIXME: Although we could sometimes handle this, and it does occur in
8111 // practice that one of the condition inputs to the select is also one of
8112 // the outputs, we currently can't deal with this.
8113 if (User->getOpcode() == ISD::SELECT) {
8114 if (User->getOperand(0) == PromOps[i])
8116 } else if (User->getOpcode() == ISD::SELECT_CC) {
8117 if (User->getOperand(0) == PromOps[i] ||
8118 User->getOperand(1) == PromOps[i])
8124 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8125 bool ReallyNeedsExt = false;
8126 if (N->getOpcode() != ISD::ANY_EXTEND) {
8127 // If all of the inputs are not already sign/zero extended, then
8128 // we'll still need to do that at the end.
8129 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8130 if (isa<ConstantSDNode>(Inputs[i]))
8134 Inputs[i].getOperand(0).getValueSizeInBits();
8135 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8137 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8138 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8139 APInt::getHighBitsSet(OpBits,
8140 OpBits-PromBits))) ||
8141 (N->getOpcode() == ISD::SIGN_EXTEND &&
8142 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8143 (OpBits-(PromBits-1)))) {
8144 ReallyNeedsExt = true;
8150 // Replace all inputs, either with the truncation operand, or a
8151 // truncation or extension to the final output type.
8152 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8153 // Constant inputs need to be replaced with the to-be-promoted nodes that
8154 // use them because they might have users outside of the cluster of
8156 if (isa<ConstantSDNode>(Inputs[i]))
8159 SDValue InSrc = Inputs[i].getOperand(0);
8160 if (Inputs[i].getValueType() == N->getValueType(0))
8161 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8162 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8163 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8164 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8165 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8166 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8167 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8169 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8170 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8173 // Replace all operations (these are all the same, but have a different
8174 // (promoted) return type). DAG.getNode will validate that the types of
8175 // a binary operator match, so go through the list in reverse so that
8176 // we've likely promoted both operands first.
8177 while (!PromOps.empty()) {
8178 SDValue PromOp = PromOps.back();
8182 switch (PromOp.getOpcode()) {
8183 default: C = 0; break;
8184 case ISD::SELECT: C = 1; break;
8185 case ISD::SELECT_CC: C = 2; break;
8188 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8189 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8190 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8191 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8192 // The to-be-promoted operands of this node have not yet been
8193 // promoted (this should be rare because we're going through the
8194 // list backward, but if one of the operands has several users in
8195 // this cluster of to-be-promoted nodes, it is possible).
8196 PromOps.insert(PromOps.begin(), PromOp);
8200 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8201 PromOp.getNode()->op_end());
8203 // If this node has constant inputs, then they'll need to be promoted here.
8204 for (unsigned i = 0; i < 2; ++i) {
8205 if (!isa<ConstantSDNode>(Ops[C+i]))
8207 if (Ops[C+i].getValueType() == N->getValueType(0))
8210 if (N->getOpcode() == ISD::SIGN_EXTEND)
8211 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8212 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8213 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8215 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8218 DAG.ReplaceAllUsesOfValueWith(PromOp,
8219 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8222 // Now we're left with the initial extension itself.
8223 if (!ReallyNeedsExt)
8224 return N->getOperand(0);
8226 // To zero extend, just mask off everything except for the first bit (in the
8228 if (N->getOpcode() == ISD::ZERO_EXTEND)
8229 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8230 DAG.getConstant(APInt::getLowBitsSet(
8231 N->getValueSizeInBits(0), PromBits),
8232 N->getValueType(0)));
8234 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8235 "Invalid extension type");
8236 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8238 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8239 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8240 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8241 N->getOperand(0), ShiftCst), ShiftCst);
8244 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8245 DAGCombinerInfo &DCI) const {
8246 const TargetMachine &TM = getTargetMachine();
8247 SelectionDAG &DAG = DCI.DAG;
8249 switch (N->getOpcode()) {
8252 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8253 if (C->isNullValue()) // 0 << V -> 0.
8254 return N->getOperand(0);
8258 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8259 if (C->isNullValue()) // 0 >>u V -> 0.
8260 return N->getOperand(0);
8264 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8265 if (C->isNullValue() || // 0 >>s V -> 0.
8266 C->isAllOnesValue()) // -1 >>s V -> -1.
8267 return N->getOperand(0);
8270 case ISD::SIGN_EXTEND:
8271 case ISD::ZERO_EXTEND:
8272 case ISD::ANY_EXTEND:
8273 return DAGCombineExtBoolTrunc(N, DCI);
8276 case ISD::SELECT_CC:
8277 return DAGCombineTruncBoolExt(N, DCI);
8279 assert(TM.Options.UnsafeFPMath &&
8280 "Reciprocal estimates require UnsafeFPMath");
8282 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
8284 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
8286 DCI.AddToWorklist(RV.getNode());
8287 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8288 N->getOperand(0), RV);
8290 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
8291 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8293 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8296 DCI.AddToWorklist(RV.getNode());
8297 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
8298 N->getValueType(0), RV);
8299 DCI.AddToWorklist(RV.getNode());
8300 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8301 N->getOperand(0), RV);
8303 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
8304 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
8306 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
8309 DCI.AddToWorklist(RV.getNode());
8310 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
8311 N->getValueType(0), RV,
8312 N->getOperand(1).getOperand(1));
8313 DCI.AddToWorklist(RV.getNode());
8314 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8315 N->getOperand(0), RV);
8319 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8321 DCI.AddToWorklist(RV.getNode());
8322 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8323 N->getOperand(0), RV);
8329 assert(TM.Options.UnsafeFPMath &&
8330 "Reciprocal estimates require UnsafeFPMath");
8332 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8334 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8336 DCI.AddToWorklist(RV.getNode());
8337 RV = DAGCombineFastRecip(RV, DCI);
8339 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8340 // this case and force the answer to 0.
8342 EVT VT = RV.getValueType();
8344 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8345 if (VT.isVector()) {
8346 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8347 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8351 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8352 N->getOperand(0), Zero, ISD::SETEQ);
8353 DCI.AddToWorklist(ZeroCmp.getNode());
8354 DCI.AddToWorklist(RV.getNode());
8356 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8364 case ISD::SINT_TO_FP:
8365 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8366 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8367 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8368 // We allow the src/dst to be either f32/f64, but the intermediate
8369 // type must be i64.
8370 if (N->getOperand(0).getValueType() == MVT::i64 &&
8371 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8372 SDValue Val = N->getOperand(0).getOperand(0);
8373 if (Val.getValueType() == MVT::f32) {
8374 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8375 DCI.AddToWorklist(Val.getNode());
8378 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8379 DCI.AddToWorklist(Val.getNode());
8380 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8381 DCI.AddToWorklist(Val.getNode());
8382 if (N->getValueType(0) == MVT::f32) {
8383 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8384 DAG.getIntPtrConstant(0));
8385 DCI.AddToWorklist(Val.getNode());
8388 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8389 // If the intermediate type is i32, we can avoid the load/store here
8396 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8397 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8398 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8399 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8400 N->getOperand(1).getValueType() == MVT::i32 &&
8401 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8402 SDValue Val = N->getOperand(1).getOperand(0);
8403 if (Val.getValueType() == MVT::f32) {
8404 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8405 DCI.AddToWorklist(Val.getNode());
8407 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8408 DCI.AddToWorklist(Val.getNode());
8411 N->getOperand(0), Val, N->getOperand(2),
8412 DAG.getValueType(N->getOperand(1).getValueType())
8415 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8416 DAG.getVTList(MVT::Other), Ops,
8417 cast<StoreSDNode>(N)->getMemoryVT(),
8418 cast<StoreSDNode>(N)->getMemOperand());
8419 DCI.AddToWorklist(Val.getNode());
8423 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8424 if (cast<StoreSDNode>(N)->isUnindexed() &&
8425 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8426 N->getOperand(1).getNode()->hasOneUse() &&
8427 (N->getOperand(1).getValueType() == MVT::i32 ||
8428 N->getOperand(1).getValueType() == MVT::i16 ||
8429 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8430 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8431 N->getOperand(1).getValueType() == MVT::i64))) {
8432 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8433 // Do an any-extend to 32-bits if this is a half-word input.
8434 if (BSwapOp.getValueType() == MVT::i16)
8435 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8438 N->getOperand(0), BSwapOp, N->getOperand(2),
8439 DAG.getValueType(N->getOperand(1).getValueType())
8442 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8443 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8444 cast<StoreSDNode>(N)->getMemOperand());
8448 LoadSDNode *LD = cast<LoadSDNode>(N);
8449 EVT VT = LD->getValueType(0);
8450 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8451 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8452 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8453 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8454 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8455 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8456 LD->getAlignment() < ABIAlignment) {
8457 // This is a type-legal unaligned Altivec load.
8458 SDValue Chain = LD->getChain();
8459 SDValue Ptr = LD->getBasePtr();
8460 bool isLittleEndian = Subtarget.isLittleEndian();
8462 // This implements the loading of unaligned vectors as described in
8463 // the venerable Apple Velocity Engine overview. Specifically:
8464 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8465 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8467 // The general idea is to expand a sequence of one or more unaligned
8468 // loads into an alignment-based permutation-control instruction (lvsl
8469 // or lvsr), a series of regular vector loads (which always truncate
8470 // their input address to an aligned address), and a series of
8471 // permutations. The results of these permutations are the requested
8472 // loaded values. The trick is that the last "extra" load is not taken
8473 // from the address you might suspect (sizeof(vector) bytes after the
8474 // last requested load), but rather sizeof(vector) - 1 bytes after the
8475 // last requested vector. The point of this is to avoid a page fault if
8476 // the base address happened to be aligned. This works because if the
8477 // base address is aligned, then adding less than a full vector length
8478 // will cause the last vector in the sequence to be (re)loaded.
8479 // Otherwise, the next vector will be fetched as you might suspect was
8482 // We might be able to reuse the permutation generation from
8483 // a different base address offset from this one by an aligned amount.
8484 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8485 // optimization later.
8486 Intrinsic::ID Intr = (isLittleEndian ?
8487 Intrinsic::ppc_altivec_lvsr :
8488 Intrinsic::ppc_altivec_lvsl);
8489 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8491 // Create the new MMO for the new base load. It is like the original MMO,
8492 // but represents an area in memory almost twice the vector size centered
8493 // on the original address. If the address is unaligned, we might start
8494 // reading up to (sizeof(vector)-1) bytes below the address of the
8495 // original unaligned load.
8496 MachineFunction &MF = DAG.getMachineFunction();
8497 MachineMemOperand *BaseMMO =
8498 MF.getMachineMemOperand(LD->getMemOperand(),
8499 -LD->getMemoryVT().getStoreSize()+1,
8500 2*LD->getMemoryVT().getStoreSize()-1);
8502 // Create the new base load.
8503 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8505 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8507 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8508 DAG.getVTList(MVT::v4i32, MVT::Other),
8509 BaseLoadOps, MVT::v4i32, BaseMMO);
8511 // Note that the value of IncOffset (which is provided to the next
8512 // load's pointer info offset value, and thus used to calculate the
8513 // alignment), and the value of IncValue (which is actually used to
8514 // increment the pointer value) are different! This is because we
8515 // require the next load to appear to be aligned, even though it
8516 // is actually offset from the base pointer by a lesser amount.
8517 int IncOffset = VT.getSizeInBits() / 8;
8518 int IncValue = IncOffset;
8520 // Walk (both up and down) the chain looking for another load at the real
8521 // (aligned) offset (the alignment of the other load does not matter in
8522 // this case). If found, then do not use the offset reduction trick, as
8523 // that will prevent the loads from being later combined (as they would
8524 // otherwise be duplicates).
8525 if (!findConsecutiveLoad(LD, DAG))
8528 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8529 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8531 MachineMemOperand *ExtraMMO =
8532 MF.getMachineMemOperand(LD->getMemOperand(),
8533 1, 2*LD->getMemoryVT().getStoreSize()-1);
8534 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8536 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8537 DAG.getVTList(MVT::v4i32, MVT::Other),
8538 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8540 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8541 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8543 // Because vperm has a big-endian bias, we must reverse the order
8544 // of the input vectors and complement the permute control vector
8545 // when generating little endian code. We have already handled the
8546 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8547 // and ExtraLoad here.
8550 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8551 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8553 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8554 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8556 if (VT != MVT::v4i32)
8557 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8559 // The output of the permutation is our loaded result, the TokenFactor is
8561 DCI.CombineTo(N, Perm, TF);
8562 return SDValue(N, 0);
8566 case ISD::INTRINSIC_WO_CHAIN: {
8567 bool isLittleEndian = Subtarget.isLittleEndian();
8568 Intrinsic::ID Intr = (isLittleEndian ?
8569 Intrinsic::ppc_altivec_lvsr :
8570 Intrinsic::ppc_altivec_lvsl);
8571 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8572 N->getOperand(1)->getOpcode() == ISD::ADD) {
8573 SDValue Add = N->getOperand(1);
8575 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8576 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8577 Add.getValueType().getScalarType().getSizeInBits()))) {
8578 SDNode *BasePtr = Add->getOperand(0).getNode();
8579 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8580 UE = BasePtr->use_end(); UI != UE; ++UI) {
8581 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8582 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8584 // We've found another LVSL/LVSR, and this address is an aligned
8585 // multiple of that one. The results will be the same, so use the
8586 // one we've just found instead.
8588 return SDValue(*UI, 0);
8597 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8598 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8599 N->getOperand(0).hasOneUse() &&
8600 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8601 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8602 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8603 N->getValueType(0) == MVT::i64))) {
8604 SDValue Load = N->getOperand(0);
8605 LoadSDNode *LD = cast<LoadSDNode>(Load);
8606 // Create the byte-swapping load.
8608 LD->getChain(), // Chain
8609 LD->getBasePtr(), // Ptr
8610 DAG.getValueType(N->getValueType(0)) // VT
8613 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8614 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8615 MVT::i64 : MVT::i32, MVT::Other),
8616 Ops, LD->getMemoryVT(), LD->getMemOperand());
8618 // If this is an i16 load, insert the truncate.
8619 SDValue ResVal = BSLoad;
8620 if (N->getValueType(0) == MVT::i16)
8621 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8623 // First, combine the bswap away. This makes the value produced by the
8625 DCI.CombineTo(N, ResVal);
8627 // Next, combine the load away, we give it a bogus result value but a real
8628 // chain result. The result value is dead because the bswap is dead.
8629 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8631 // Return N so it doesn't get rechecked!
8632 return SDValue(N, 0);
8636 case PPCISD::VCMP: {
8637 // If a VCMPo node already exists with exactly the same operands as this
8638 // node, use its result instead of this node (VCMPo computes both a CR6 and
8639 // a normal output).
8641 if (!N->getOperand(0).hasOneUse() &&
8642 !N->getOperand(1).hasOneUse() &&
8643 !N->getOperand(2).hasOneUse()) {
8645 // Scan all of the users of the LHS, looking for VCMPo's that match.
8646 SDNode *VCMPoNode = nullptr;
8648 SDNode *LHSN = N->getOperand(0).getNode();
8649 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8651 if (UI->getOpcode() == PPCISD::VCMPo &&
8652 UI->getOperand(1) == N->getOperand(1) &&
8653 UI->getOperand(2) == N->getOperand(2) &&
8654 UI->getOperand(0) == N->getOperand(0)) {
8659 // If there is no VCMPo node, or if the flag value has a single use, don't
8661 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8664 // Look at the (necessarily single) use of the flag value. If it has a
8665 // chain, this transformation is more complex. Note that multiple things
8666 // could use the value result, which we should ignore.
8667 SDNode *FlagUser = nullptr;
8668 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8669 FlagUser == nullptr; ++UI) {
8670 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8672 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8673 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8680 // If the user is a MFOCRF instruction, we know this is safe.
8681 // Otherwise we give up for right now.
8682 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8683 return SDValue(VCMPoNode, 0);
8688 SDValue Cond = N->getOperand(1);
8689 SDValue Target = N->getOperand(2);
8691 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8692 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8693 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8695 // We now need to make the intrinsic dead (it cannot be instruction
8697 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8698 assert(Cond.getNode()->hasOneUse() &&
8699 "Counter decrement has more than one use");
8701 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8702 N->getOperand(0), Target);
8707 // If this is a branch on an altivec predicate comparison, lower this so
8708 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8709 // lowering is done pre-legalize, because the legalizer lowers the predicate
8710 // compare down to code that is difficult to reassemble.
8711 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8712 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8714 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8715 // value. If so, pass-through the AND to get to the intrinsic.
8716 if (LHS.getOpcode() == ISD::AND &&
8717 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8718 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8719 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8720 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8721 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8723 LHS = LHS.getOperand(0);
8725 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8726 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8727 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8728 isa<ConstantSDNode>(RHS)) {
8729 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8730 "Counter decrement comparison is not EQ or NE");
8732 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8733 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8734 (CC == ISD::SETNE && !Val);
8736 // We now need to make the intrinsic dead (it cannot be instruction
8738 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8739 assert(LHS.getNode()->hasOneUse() &&
8740 "Counter decrement has more than one use");
8742 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8743 N->getOperand(0), N->getOperand(4));
8749 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8750 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8751 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8752 assert(isDot && "Can't compare against a vector result!");
8754 // If this is a comparison against something other than 0/1, then we know
8755 // that the condition is never/always true.
8756 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8757 if (Val != 0 && Val != 1) {
8758 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8759 return N->getOperand(0);
8760 // Always !=, turn it into an unconditional branch.
8761 return DAG.getNode(ISD::BR, dl, MVT::Other,
8762 N->getOperand(0), N->getOperand(4));
8765 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8767 // Create the PPCISD altivec 'dot' comparison node.
8769 LHS.getOperand(2), // LHS of compare
8770 LHS.getOperand(3), // RHS of compare
8771 DAG.getConstant(CompareOpc, MVT::i32)
8773 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8774 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8776 // Unpack the result based on how the target uses it.
8777 PPC::Predicate CompOpc;
8778 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8779 default: // Can't happen, don't crash on invalid number though.
8780 case 0: // Branch on the value of the EQ bit of CR6.
8781 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8783 case 1: // Branch on the inverted value of the EQ bit of CR6.
8784 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8786 case 2: // Branch on the value of the LT bit of CR6.
8787 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8789 case 3: // Branch on the inverted value of the LT bit of CR6.
8790 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8794 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8795 DAG.getConstant(CompOpc, MVT::i32),
8796 DAG.getRegister(PPC::CR6, MVT::i32),
8797 N->getOperand(4), CompNode.getValue(1));
8806 //===----------------------------------------------------------------------===//
8807 // Inline Assembly Support
8808 //===----------------------------------------------------------------------===//
8810 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8813 const SelectionDAG &DAG,
8814 unsigned Depth) const {
8815 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8816 switch (Op.getOpcode()) {
8818 case PPCISD::LBRX: {
8819 // lhbrx is known to have the top bits cleared out.
8820 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8821 KnownZero = 0xFFFF0000;
8824 case ISD::INTRINSIC_WO_CHAIN: {
8825 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8827 case Intrinsic::ppc_altivec_vcmpbfp_p:
8828 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8829 case Intrinsic::ppc_altivec_vcmpequb_p:
8830 case Intrinsic::ppc_altivec_vcmpequh_p:
8831 case Intrinsic::ppc_altivec_vcmpequw_p:
8832 case Intrinsic::ppc_altivec_vcmpgefp_p:
8833 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8834 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8835 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8836 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8837 case Intrinsic::ppc_altivec_vcmpgtub_p:
8838 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8839 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8840 KnownZero = ~1U; // All bits but the low one are known to be zero.
8848 /// getConstraintType - Given a constraint, return the type of
8849 /// constraint it is for this target.
8850 PPCTargetLowering::ConstraintType
8851 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8852 if (Constraint.size() == 1) {
8853 switch (Constraint[0]) {
8860 return C_RegisterClass;
8862 // FIXME: While Z does indicate a memory constraint, it specifically
8863 // indicates an r+r address (used in conjunction with the 'y' modifier
8864 // in the replacement string). Currently, we're forcing the base
8865 // register to be r0 in the asm printer (which is interpreted as zero)
8866 // and forming the complete address in the second register. This is
8870 } else if (Constraint == "wc") { // individual CR bits.
8871 return C_RegisterClass;
8872 } else if (Constraint == "wa" || Constraint == "wd" ||
8873 Constraint == "wf" || Constraint == "ws") {
8874 return C_RegisterClass; // VSX registers.
8876 return TargetLowering::getConstraintType(Constraint);
8879 /// Examine constraint type and operand type and determine a weight value.
8880 /// This object must already have been set up with the operand type
8881 /// and the current alternative constraint selected.
8882 TargetLowering::ConstraintWeight
8883 PPCTargetLowering::getSingleConstraintMatchWeight(
8884 AsmOperandInfo &info, const char *constraint) const {
8885 ConstraintWeight weight = CW_Invalid;
8886 Value *CallOperandVal = info.CallOperandVal;
8887 // If we don't have a value, we can't do a match,
8888 // but allow it at the lowest weight.
8889 if (!CallOperandVal)
8891 Type *type = CallOperandVal->getType();
8893 // Look at the constraint type.
8894 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8895 return CW_Register; // an individual CR bit.
8896 else if ((StringRef(constraint) == "wa" ||
8897 StringRef(constraint) == "wd" ||
8898 StringRef(constraint) == "wf") &&
8901 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8904 switch (*constraint) {
8906 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8909 if (type->isIntegerTy())
8910 weight = CW_Register;
8913 if (type->isFloatTy())
8914 weight = CW_Register;
8917 if (type->isDoubleTy())
8918 weight = CW_Register;
8921 if (type->isVectorTy())
8922 weight = CW_Register;
8925 weight = CW_Register;
8934 std::pair<unsigned, const TargetRegisterClass*>
8935 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8937 if (Constraint.size() == 1) {
8938 // GCC RS6000 Constraint Letters
8939 switch (Constraint[0]) {
8941 if (VT == MVT::i64 && Subtarget.isPPC64())
8942 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8943 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8945 if (VT == MVT::i64 && Subtarget.isPPC64())
8946 return std::make_pair(0U, &PPC::G8RCRegClass);
8947 return std::make_pair(0U, &PPC::GPRCRegClass);
8949 if (VT == MVT::f32 || VT == MVT::i32)
8950 return std::make_pair(0U, &PPC::F4RCRegClass);
8951 if (VT == MVT::f64 || VT == MVT::i64)
8952 return std::make_pair(0U, &PPC::F8RCRegClass);
8955 return std::make_pair(0U, &PPC::VRRCRegClass);
8957 return std::make_pair(0U, &PPC::CRRCRegClass);
8959 } else if (Constraint == "wc") { // an individual CR bit.
8960 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8961 } else if (Constraint == "wa" || Constraint == "wd" ||
8962 Constraint == "wf") {
8963 return std::make_pair(0U, &PPC::VSRCRegClass);
8964 } else if (Constraint == "ws") {
8965 return std::make_pair(0U, &PPC::VSFRCRegClass);
8968 std::pair<unsigned, const TargetRegisterClass*> R =
8969 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8971 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8972 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8973 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8975 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8976 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8977 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8978 PPC::GPRCRegClass.contains(R.first)) {
8979 const TargetRegisterInfo *TRI =
8980 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
8981 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8982 PPC::sub_32, &PPC::G8RCRegClass),
8983 &PPC::G8RCRegClass);
8990 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8991 /// vector. If it is invalid, don't add anything to Ops.
8992 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8993 std::string &Constraint,
8994 std::vector<SDValue>&Ops,
8995 SelectionDAG &DAG) const {
8998 // Only support length 1 constraints.
8999 if (Constraint.length() > 1) return;
9001 char Letter = Constraint[0];
9012 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9013 if (!CST) return; // Must be an immediate to match.
9014 unsigned Value = CST->getZExtValue();
9016 default: llvm_unreachable("Unknown constraint letter!");
9017 case 'I': // "I" is a signed 16-bit constant.
9018 if ((short)Value == (int)Value)
9019 Result = DAG.getTargetConstant(Value, Op.getValueType());
9021 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9022 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9023 if ((short)Value == 0)
9024 Result = DAG.getTargetConstant(Value, Op.getValueType());
9026 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9027 if ((Value >> 16) == 0)
9028 Result = DAG.getTargetConstant(Value, Op.getValueType());
9030 case 'M': // "M" is a constant that is greater than 31.
9032 Result = DAG.getTargetConstant(Value, Op.getValueType());
9034 case 'N': // "N" is a positive constant that is an exact power of two.
9035 if ((int)Value > 0 && isPowerOf2_32(Value))
9036 Result = DAG.getTargetConstant(Value, Op.getValueType());
9038 case 'O': // "O" is the constant zero.
9040 Result = DAG.getTargetConstant(Value, Op.getValueType());
9042 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9043 if ((short)-Value == (int)-Value)
9044 Result = DAG.getTargetConstant(Value, Op.getValueType());
9051 if (Result.getNode()) {
9052 Ops.push_back(Result);
9056 // Handle standard constraint letters.
9057 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9060 // isLegalAddressingMode - Return true if the addressing mode represented
9061 // by AM is legal for this target, for a load/store of the specified type.
9062 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9064 // FIXME: PPC does not allow r+i addressing modes for vectors!
9066 // PPC allows a sign-extended 16-bit immediate field.
9067 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9070 // No global is ever allowed as a base.
9074 // PPC only support r+r,
9076 case 0: // "r+i" or just "i", depending on HasBaseReg.
9079 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9081 // Otherwise we have r+r or r+i.
9084 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9086 // Allow 2*r as r+r.
9089 // No other scales are supported.
9096 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9097 SelectionDAG &DAG) const {
9098 MachineFunction &MF = DAG.getMachineFunction();
9099 MachineFrameInfo *MFI = MF.getFrameInfo();
9100 MFI->setReturnAddressIsTaken(true);
9102 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9106 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9108 // Make sure the function does not optimize away the store of the RA to
9110 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9111 FuncInfo->setLRStoreRequired();
9112 bool isPPC64 = Subtarget.isPPC64();
9113 bool isDarwinABI = Subtarget.isDarwinABI();
9116 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9119 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9120 isPPC64? MVT::i64 : MVT::i32);
9121 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9122 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9124 MachinePointerInfo(), false, false, false, 0);
9127 // Just load the return address off the stack.
9128 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9129 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9130 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9133 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9134 SelectionDAG &DAG) const {
9136 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9138 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9139 bool isPPC64 = PtrVT == MVT::i64;
9141 MachineFunction &MF = DAG.getMachineFunction();
9142 MachineFrameInfo *MFI = MF.getFrameInfo();
9143 MFI->setFrameAddressIsTaken(true);
9145 // Naked functions never have a frame pointer, and so we use r1. For all
9146 // other functions, this decision must be delayed until during PEI.
9148 if (MF.getFunction()->getAttributes().hasAttribute(
9149 AttributeSet::FunctionIndex, Attribute::Naked))
9150 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9152 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9154 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9157 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9158 FrameAddr, MachinePointerInfo(), false, false,
9163 // FIXME? Maybe this could be a TableGen attribute on some registers and
9164 // this table could be generated automatically from RegInfo.
9165 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9167 bool isPPC64 = Subtarget.isPPC64();
9168 bool isDarwinABI = Subtarget.isDarwinABI();
9170 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9171 (!isPPC64 && VT != MVT::i32))
9172 report_fatal_error("Invalid register global variable type");
9174 bool is64Bit = isPPC64 && VT == MVT::i64;
9175 unsigned Reg = StringSwitch<unsigned>(RegName)
9176 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9177 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9178 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9179 (is64Bit ? PPC::X13 : PPC::R13))
9184 report_fatal_error("Invalid register name global variable");
9188 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9189 // The PowerPC target isn't yet aware of offsets.
9193 /// getOptimalMemOpType - Returns the target specific optimal type for load
9194 /// and store operations as a result of memset, memcpy, and memmove
9195 /// lowering. If DstAlign is zero that means it's safe to destination
9196 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9197 /// means there isn't a need to check it against alignment requirement,
9198 /// probably because the source does not need to be loaded. If 'IsMemset' is
9199 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9200 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9201 /// source is constant so it does not need to be loaded.
9202 /// It returns EVT::Other if the type should be determined using generic
9203 /// target-independent logic.
9204 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9205 unsigned DstAlign, unsigned SrcAlign,
9206 bool IsMemset, bool ZeroMemset,
9208 MachineFunction &MF) const {
9209 if (Subtarget.isPPC64()) {
9216 /// \brief Returns true if it is beneficial to convert a load of a constant
9217 /// to just the constant itself.
9218 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9220 assert(Ty->isIntegerTy());
9222 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9223 if (BitSize == 0 || BitSize > 64)
9228 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9229 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9231 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9232 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9233 return NumBits1 == 64 && NumBits2 == 32;
9236 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9237 if (!VT1.isInteger() || !VT2.isInteger())
9239 unsigned NumBits1 = VT1.getSizeInBits();
9240 unsigned NumBits2 = VT2.getSizeInBits();
9241 return NumBits1 == 64 && NumBits2 == 32;
9244 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9245 return isInt<16>(Imm) || isUInt<16>(Imm);
9248 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9249 return isInt<16>(Imm) || isUInt<16>(Imm);
9252 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9256 if (DisablePPCUnaligned)
9259 // PowerPC supports unaligned memory access for simple non-vector types.
9260 // Although accessing unaligned addresses is not as efficient as accessing
9261 // aligned addresses, it is generally more efficient than manual expansion,
9262 // and generally only traps for software emulation when crossing page
9268 if (VT.getSimpleVT().isVector()) {
9269 if (Subtarget.hasVSX()) {
9270 if (VT != MVT::v2f64 && VT != MVT::v2i64)
9277 if (VT == MVT::ppcf128)
9286 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9287 VT = VT.getScalarType();
9292 switch (VT.getSimpleVT().SimpleTy) {
9304 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9305 EVT VT , unsigned DefinedValues) const {
9306 if (VT == MVT::v2i64)
9309 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9312 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9313 if (DisableILPPref || Subtarget.enableMachineScheduler())
9314 return TargetLowering::getSchedulingPreference(N);
9319 // Create a fast isel object.
9321 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9322 const TargetLibraryInfo *LibInfo) const {
9323 return PPC::createFastISel(FuncInfo, LibInfo);