1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/IR/CallingConv.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/Intrinsics.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/Target/TargetOptions.h"
41 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
42 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
44 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
45 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
47 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
48 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
50 // FIXME: Remove this once the bug has been fixed!
51 extern cl::opt<bool> ANDIGlueBug;
53 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
54 if (TM.getSubtargetImpl()->isDarwin())
55 return new TargetLoweringObjectFileMachO();
57 if (TM.getSubtargetImpl()->isSVR4ABI())
58 return new PPC64LinuxTargetObjectFile();
60 return new TargetLoweringObjectFileELF();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
65 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
69 // Use _setjmp/_longjmp instead of setjmp/longjmp.
70 setUseUnderscoreSetJmp(true);
71 setUseUnderscoreLongJmp(true);
73 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
74 // arguments are at least 4/8 bytes aligned.
75 bool isPPC64 = Subtarget->isPPC64();
76 setMinStackArgumentAlignment(isPPC64 ? 8:4);
78 // Set up the register classes.
79 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
80 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
81 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
83 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
85 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
87 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
89 // PowerPC has pre-inc load and store's.
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
101 if (Subtarget->useCRBits()) {
102 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
104 if (isPPC64 || Subtarget->hasFPCVT()) {
105 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
106 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
107 isPPC64 ? MVT::i64 : MVT::i32);
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
109 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
110 isPPC64 ? MVT::i64 : MVT::i32);
112 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
113 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
116 // PowerPC does not support direct load / store of condition registers
117 setOperationAction(ISD::LOAD, MVT::i1, Custom);
118 setOperationAction(ISD::STORE, MVT::i1, Custom);
120 // FIXME: Remove this once the ANDI glue bug is fixed:
122 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
124 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
125 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
126 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
129 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget->hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath &&
181 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget->hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath &&
186 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget->hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget->hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget->hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget->useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget->useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget->useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget->isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget->isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget->has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (PPCSubTarget.hasFPCVT()) {
372 if (Subtarget->has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget->use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget->hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
405 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
406 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
408 // add/sub are legal for all supported vector VT's.
409 setOperationAction(ISD::ADD , VT, Legal);
410 setOperationAction(ISD::SUB , VT, Legal);
412 // We promote all shuffles to v16i8.
413 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
414 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
416 // We promote all non-typed operations to v4i32.
417 setOperationAction(ISD::AND , VT, Promote);
418 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
419 setOperationAction(ISD::OR , VT, Promote);
420 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
421 setOperationAction(ISD::XOR , VT, Promote);
422 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
423 setOperationAction(ISD::LOAD , VT, Promote);
424 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
425 setOperationAction(ISD::SELECT, VT, Promote);
426 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
427 setOperationAction(ISD::STORE, VT, Promote);
428 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
430 // No other operations are legal.
431 setOperationAction(ISD::MUL , VT, Expand);
432 setOperationAction(ISD::SDIV, VT, Expand);
433 setOperationAction(ISD::SREM, VT, Expand);
434 setOperationAction(ISD::UDIV, VT, Expand);
435 setOperationAction(ISD::UREM, VT, Expand);
436 setOperationAction(ISD::FDIV, VT, Expand);
437 setOperationAction(ISD::FREM, VT, Expand);
438 setOperationAction(ISD::FNEG, VT, Expand);
439 setOperationAction(ISD::FSQRT, VT, Expand);
440 setOperationAction(ISD::FLOG, VT, Expand);
441 setOperationAction(ISD::FLOG10, VT, Expand);
442 setOperationAction(ISD::FLOG2, VT, Expand);
443 setOperationAction(ISD::FEXP, VT, Expand);
444 setOperationAction(ISD::FEXP2, VT, Expand);
445 setOperationAction(ISD::FSIN, VT, Expand);
446 setOperationAction(ISD::FCOS, VT, Expand);
447 setOperationAction(ISD::FABS, VT, Expand);
448 setOperationAction(ISD::FPOWI, VT, Expand);
449 setOperationAction(ISD::FFLOOR, VT, Expand);
450 setOperationAction(ISD::FCEIL, VT, Expand);
451 setOperationAction(ISD::FTRUNC, VT, Expand);
452 setOperationAction(ISD::FRINT, VT, Expand);
453 setOperationAction(ISD::FNEARBYINT, VT, Expand);
454 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
456 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
457 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
459 setOperationAction(ISD::UDIVREM, VT, Expand);
460 setOperationAction(ISD::SDIVREM, VT, Expand);
461 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
462 setOperationAction(ISD::FPOW, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget->useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget->hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget->hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget->has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget->useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget->useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget->isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget->useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (PPCSubTarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget->isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget->enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (PPCSubTarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = PPCSubTarget.isPPC64() ? 8 : 4;
755 if (PPCSubTarget.hasAltivec() || PPCSubTarget.hasQPX())
756 getMaxByValAlign(Ty, Align, PPCSubTarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
777 case PPCISD::LOAD: return "PPCISD::LOAD";
778 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
779 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
780 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
781 case PPCISD::SRL: return "PPCISD::SRL";
782 case PPCISD::SRA: return "PPCISD::SRA";
783 case PPCISD::SHL: return "PPCISD::SHL";
784 case PPCISD::CALL: return "PPCISD::CALL";
785 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
786 case PPCISD::MTCTR: return "PPCISD::MTCTR";
787 case PPCISD::BCTRL: return "PPCISD::BCTRL";
788 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
789 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
790 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
791 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
792 case PPCISD::VCMP: return "PPCISD::VCMP";
793 case PPCISD::VCMPo: return "PPCISD::VCMPo";
794 case PPCISD::LBRX: return "PPCISD::LBRX";
795 case PPCISD::STBRX: return "PPCISD::STBRX";
796 case PPCISD::LARX: return "PPCISD::LARX";
797 case PPCISD::STCX: return "PPCISD::STCX";
798 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
799 case PPCISD::BDNZ: return "PPCISD::BDNZ";
800 case PPCISD::BDZ: return "PPCISD::BDZ";
801 case PPCISD::MFFS: return "PPCISD::MFFS";
802 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
803 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
804 case PPCISD::CR6SET: return "PPCISD::CR6SET";
805 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
806 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
807 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
808 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
809 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
810 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
811 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
812 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
813 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
814 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
815 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
816 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
817 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
818 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
819 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
820 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
821 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
822 case PPCISD::SC: return "PPCISD::SC";
826 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
828 return PPCSubTarget.useCRBits() ? MVT::i1 : MVT::i32;
829 return VT.changeVectorElementTypeToInteger();
832 //===----------------------------------------------------------------------===//
833 // Node matching predicates, for use by the tblgen matching code.
834 //===----------------------------------------------------------------------===//
836 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
837 static bool isFloatingPointZero(SDValue Op) {
838 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
839 return CFP->getValueAPF().isZero();
840 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
841 // Maybe this has already been legalized into the constant pool?
842 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
843 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
844 return CFP->getValueAPF().isZero();
849 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
850 /// true if Op is undef or if it matches the specified value.
851 static bool isConstantOrUndef(int Op, int Val) {
852 return Op < 0 || Op == Val;
855 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
856 /// VPKUHUM instruction.
857 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
859 for (unsigned i = 0; i != 16; ++i)
860 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
863 for (unsigned i = 0; i != 8; ++i)
864 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
865 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
871 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
872 /// VPKUWUM instruction.
873 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
875 for (unsigned i = 0; i != 16; i += 2)
876 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
877 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
880 for (unsigned i = 0; i != 8; i += 2)
881 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
882 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
883 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
884 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
890 /// isVMerge - Common function, used to match vmrg* shuffles.
892 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
893 unsigned LHSStart, unsigned RHSStart) {
894 if (N->getValueType(0) != MVT::v16i8)
896 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
897 "Unsupported merge size!");
899 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
900 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
901 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
902 LHSStart+j+i*UnitSize) ||
903 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
904 RHSStart+j+i*UnitSize))
910 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
911 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
912 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
915 return isVMerge(N, UnitSize, 8, 24);
916 return isVMerge(N, UnitSize, 8, 8);
919 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
920 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
921 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
924 return isVMerge(N, UnitSize, 0, 16);
925 return isVMerge(N, UnitSize, 0, 0);
929 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
930 /// amount, otherwise return -1.
931 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
932 if (N->getValueType(0) != MVT::v16i8)
935 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
937 // Find the first non-undef value in the shuffle mask.
939 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
942 if (i == 16) return -1; // all undef.
944 // Otherwise, check to see if the rest of the elements are consecutively
945 // numbered from this value.
946 unsigned ShiftAmt = SVOp->getMaskElt(i);
947 if (ShiftAmt < i) return -1;
951 // Check the rest of the elements to see if they are consecutive.
952 for (++i; i != 16; ++i)
953 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
956 // Check the rest of the elements to see if they are consecutive.
957 for (++i; i != 16; ++i)
958 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
964 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
965 /// specifies a splat of a single element that is suitable for input to
966 /// VSPLTB/VSPLTH/VSPLTW.
967 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
968 assert(N->getValueType(0) == MVT::v16i8 &&
969 (EltSize == 1 || EltSize == 2 || EltSize == 4));
971 // This is a splat operation if each element of the permute is the same, and
972 // if the value doesn't reference the second vector.
973 unsigned ElementBase = N->getMaskElt(0);
975 // FIXME: Handle UNDEF elements too!
976 if (ElementBase >= 16)
979 // Check that the indices are consecutive, in the case of a multi-byte element
980 // splatted with a v16i8 mask.
981 for (unsigned i = 1; i != EltSize; ++i)
982 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
985 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
986 if (N->getMaskElt(i) < 0) continue;
987 for (unsigned j = 0; j != EltSize; ++j)
988 if (N->getMaskElt(i+j) != N->getMaskElt(j))
994 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
996 bool PPC::isAllNegativeZeroVector(SDNode *N) {
997 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
999 APInt APVal, APUndef;
1003 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1004 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1005 return CFP->getValueAPF().isNegZero();
1010 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1011 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1012 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
1013 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1014 assert(isSplatShuffleMask(SVOp, EltSize));
1015 return SVOp->getMaskElt(0) / EltSize;
1018 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1019 /// by using a vspltis[bhw] instruction of the specified element size, return
1020 /// the constant being splatted. The ByteSize field indicates the number of
1021 /// bytes of each element [124] -> [bhw].
1022 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1023 SDValue OpVal(nullptr, 0);
1025 // If ByteSize of the splat is bigger than the element size of the
1026 // build_vector, then we have a case where we are checking for a splat where
1027 // multiple elements of the buildvector are folded together into a single
1028 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1029 unsigned EltSize = 16/N->getNumOperands();
1030 if (EltSize < ByteSize) {
1031 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1032 SDValue UniquedVals[4];
1033 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1035 // See if all of the elements in the buildvector agree across.
1036 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1037 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1038 // If the element isn't a constant, bail fully out.
1039 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1042 if (!UniquedVals[i&(Multiple-1)].getNode())
1043 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1044 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1045 return SDValue(); // no match.
1048 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1049 // either constant or undef values that are identical for each chunk. See
1050 // if these chunks can form into a larger vspltis*.
1052 // Check to see if all of the leading entries are either 0 or -1. If
1053 // neither, then this won't fit into the immediate field.
1054 bool LeadingZero = true;
1055 bool LeadingOnes = true;
1056 for (unsigned i = 0; i != Multiple-1; ++i) {
1057 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1059 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1060 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1062 // Finally, check the least significant entry.
1064 if (!UniquedVals[Multiple-1].getNode())
1065 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1066 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1068 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1071 if (!UniquedVals[Multiple-1].getNode())
1072 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1073 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1074 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1075 return DAG.getTargetConstant(Val, MVT::i32);
1081 // Check to see if this buildvec has a single non-undef value in its elements.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 if (!OpVal.getNode())
1085 OpVal = N->getOperand(i);
1086 else if (OpVal != N->getOperand(i))
1090 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1092 unsigned ValSizeInBytes = EltSize;
1094 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1095 Value = CN->getZExtValue();
1096 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1097 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1098 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1101 // If the splat value is larger than the element value, then we can never do
1102 // this splat. The only case that we could fit the replicated bits into our
1103 // immediate field for would be zero, and we prefer to use vxor for it.
1104 if (ValSizeInBytes < ByteSize) return SDValue();
1106 // If the element value is larger than the splat value, cut it in half and
1107 // check to see if the two halves are equal. Continue doing this until we
1108 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1109 while (ValSizeInBytes > ByteSize) {
1110 ValSizeInBytes >>= 1;
1112 // If the top half equals the bottom half, we're still ok.
1113 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1114 (Value & ((1 << (8*ValSizeInBytes))-1)))
1118 // Properly sign extend the value.
1119 int MaskVal = SignExtend32(Value, ByteSize * 8);
1121 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1122 if (MaskVal == 0) return SDValue();
1124 // Finally, if this value fits in a 5 bit sext field, return it
1125 if (SignExtend32<5>(MaskVal) == MaskVal)
1126 return DAG.getTargetConstant(MaskVal, MVT::i32);
1130 //===----------------------------------------------------------------------===//
1131 // Addressing Mode Selection
1132 //===----------------------------------------------------------------------===//
1134 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1135 /// or 64-bit immediate, and if the value can be accurately represented as a
1136 /// sign extension from a 16-bit value. If so, this returns true and the
1138 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1139 if (N->getOpcode() != ISD::Constant)
1142 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1143 if (N->getValueType(0) == MVT::i32)
1144 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1146 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1148 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1149 return isIntS16Immediate(Op.getNode(), Imm);
1153 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1154 /// can be represented as an indexed [r+r] operation. Returns false if it
1155 /// can be more efficiently represented with [r+imm].
1156 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1158 SelectionDAG &DAG) const {
1160 if (N.getOpcode() == ISD::ADD) {
1161 if (isIntS16Immediate(N.getOperand(1), imm))
1162 return false; // r+i
1163 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1164 return false; // r+i
1166 Base = N.getOperand(0);
1167 Index = N.getOperand(1);
1169 } else if (N.getOpcode() == ISD::OR) {
1170 if (isIntS16Immediate(N.getOperand(1), imm))
1171 return false; // r+i can fold it if we can.
1173 // If this is an or of disjoint bitfields, we can codegen this as an add
1174 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1176 APInt LHSKnownZero, LHSKnownOne;
1177 APInt RHSKnownZero, RHSKnownOne;
1178 DAG.computeKnownBits(N.getOperand(0),
1179 LHSKnownZero, LHSKnownOne);
1181 if (LHSKnownZero.getBoolValue()) {
1182 DAG.computeKnownBits(N.getOperand(1),
1183 RHSKnownZero, RHSKnownOne);
1184 // If all of the bits are known zero on the LHS or RHS, the add won't
1186 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1187 Base = N.getOperand(0);
1188 Index = N.getOperand(1);
1197 // If we happen to be doing an i64 load or store into a stack slot that has
1198 // less than a 4-byte alignment, then the frame-index elimination may need to
1199 // use an indexed load or store instruction (because the offset may not be a
1200 // multiple of 4). The extra register needed to hold the offset comes from the
1201 // register scavenger, and it is possible that the scavenger will need to use
1202 // an emergency spill slot. As a result, we need to make sure that a spill slot
1203 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1205 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1206 // FIXME: This does not handle the LWA case.
1210 // NOTE: We'll exclude negative FIs here, which come from argument
1211 // lowering, because there are no known test cases triggering this problem
1212 // using packed structures (or similar). We can remove this exclusion if
1213 // we find such a test case. The reason why this is so test-case driven is
1214 // because this entire 'fixup' is only to prevent crashes (from the
1215 // register scavenger) on not-really-valid inputs. For example, if we have:
1217 // %b = bitcast i1* %a to i64*
1218 // store i64* a, i64 b
1219 // then the store should really be marked as 'align 1', but is not. If it
1220 // were marked as 'align 1' then the indexed form would have been
1221 // instruction-selected initially, and the problem this 'fixup' is preventing
1222 // won't happen regardless.
1226 MachineFunction &MF = DAG.getMachineFunction();
1227 MachineFrameInfo *MFI = MF.getFrameInfo();
1229 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1233 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1234 FuncInfo->setHasNonRISpills();
1237 /// Returns true if the address N can be represented by a base register plus
1238 /// a signed 16-bit displacement [r+imm], and if it is not better
1239 /// represented as reg+reg. If Aligned is true, only accept displacements
1240 /// suitable for STD and friends, i.e. multiples of 4.
1241 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1244 bool Aligned) const {
1245 // FIXME dl should come from parent load or store, not from address
1247 // If this can be more profitably realized as r+r, fail.
1248 if (SelectAddressRegReg(N, Disp, Base, DAG))
1251 if (N.getOpcode() == ISD::ADD) {
1253 if (isIntS16Immediate(N.getOperand(1), imm) &&
1254 (!Aligned || (imm & 3) == 0)) {
1255 Disp = DAG.getTargetConstant(imm, N.getValueType());
1256 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1257 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1258 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1260 Base = N.getOperand(0);
1262 return true; // [r+i]
1263 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1264 // Match LOAD (ADD (X, Lo(G))).
1265 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1266 && "Cannot handle constant offsets yet!");
1267 Disp = N.getOperand(1).getOperand(0); // The global address.
1268 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1269 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1270 Disp.getOpcode() == ISD::TargetConstantPool ||
1271 Disp.getOpcode() == ISD::TargetJumpTable);
1272 Base = N.getOperand(0);
1273 return true; // [&g+r]
1275 } else if (N.getOpcode() == ISD::OR) {
1277 if (isIntS16Immediate(N.getOperand(1), imm) &&
1278 (!Aligned || (imm & 3) == 0)) {
1279 // If this is an or of disjoint bitfields, we can codegen this as an add
1280 // (for better address arithmetic) if the LHS and RHS of the OR are
1281 // provably disjoint.
1282 APInt LHSKnownZero, LHSKnownOne;
1283 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1285 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1286 // If all of the bits are known zero on the LHS or RHS, the add won't
1288 Base = N.getOperand(0);
1289 Disp = DAG.getTargetConstant(imm, N.getValueType());
1293 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1294 // Loading from a constant address.
1296 // If this address fits entirely in a 16-bit sext immediate field, codegen
1299 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1300 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1301 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1302 CN->getValueType(0));
1306 // Handle 32-bit sext immediates with LIS + addr mode.
1307 if ((CN->getValueType(0) == MVT::i32 ||
1308 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1309 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1310 int Addr = (int)CN->getZExtValue();
1312 // Otherwise, break this down into an LIS + disp.
1313 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1315 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1316 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1317 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1322 Disp = DAG.getTargetConstant(0, getPointerTy());
1323 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1324 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1325 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1328 return true; // [r+0]
1331 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1332 /// represented as an indexed [r+r] operation.
1333 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1335 SelectionDAG &DAG) const {
1336 // Check to see if we can easily represent this as an [r+r] address. This
1337 // will fail if it thinks that the address is more profitably represented as
1338 // reg+imm, e.g. where imm = 0.
1339 if (SelectAddressRegReg(N, Base, Index, DAG))
1342 // If the operand is an addition, always emit this as [r+r], since this is
1343 // better (for code size, and execution, as the memop does the add for free)
1344 // than emitting an explicit add.
1345 if (N.getOpcode() == ISD::ADD) {
1346 Base = N.getOperand(0);
1347 Index = N.getOperand(1);
1351 // Otherwise, do it the hard way, using R0 as the base register.
1352 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1358 /// getPreIndexedAddressParts - returns true by value, base pointer and
1359 /// offset pointer and addressing mode by reference if the node's address
1360 /// can be legally represented as pre-indexed load / store address.
1361 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1363 ISD::MemIndexedMode &AM,
1364 SelectionDAG &DAG) const {
1365 if (DisablePPCPreinc) return false;
1371 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1372 Ptr = LD->getBasePtr();
1373 VT = LD->getMemoryVT();
1374 Alignment = LD->getAlignment();
1375 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1376 Ptr = ST->getBasePtr();
1377 VT = ST->getMemoryVT();
1378 Alignment = ST->getAlignment();
1383 // PowerPC doesn't have preinc load/store instructions for vectors.
1387 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1389 // Common code will reject creating a pre-inc form if the base pointer
1390 // is a frame index, or if N is a store and the base pointer is either
1391 // the same as or a predecessor of the value being stored. Check for
1392 // those situations here, and try with swapped Base/Offset instead.
1395 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1398 SDValue Val = cast<StoreSDNode>(N)->getValue();
1399 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1404 std::swap(Base, Offset);
1410 // LDU/STU can only handle immediates that are a multiple of 4.
1411 if (VT != MVT::i64) {
1412 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1415 // LDU/STU need an address with at least 4-byte alignment.
1419 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1423 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1424 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1425 // sext i32 to i64 when addr mode is r+i.
1426 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1427 LD->getExtensionType() == ISD::SEXTLOAD &&
1428 isa<ConstantSDNode>(Offset))
1436 //===----------------------------------------------------------------------===//
1437 // LowerOperation implementation
1438 //===----------------------------------------------------------------------===//
1440 /// GetLabelAccessInfo - Return true if we should reference labels using a
1441 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1442 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1443 unsigned &LoOpFlags,
1444 const GlobalValue *GV = nullptr) {
1445 HiOpFlags = PPCII::MO_HA;
1446 LoOpFlags = PPCII::MO_LO;
1448 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1449 // non-darwin platform. We don't support PIC on other platforms yet.
1450 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1451 TM.getSubtarget<PPCSubtarget>().isDarwin();
1453 HiOpFlags |= PPCII::MO_PIC_FLAG;
1454 LoOpFlags |= PPCII::MO_PIC_FLAG;
1457 // If this is a reference to a global value that requires a non-lazy-ptr, make
1458 // sure that instruction lowering adds it.
1459 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1460 HiOpFlags |= PPCII::MO_NLP_FLAG;
1461 LoOpFlags |= PPCII::MO_NLP_FLAG;
1463 if (GV->hasHiddenVisibility()) {
1464 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1465 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1472 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1473 SelectionDAG &DAG) {
1474 EVT PtrVT = HiPart.getValueType();
1475 SDValue Zero = DAG.getConstant(0, PtrVT);
1478 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1479 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1481 // With PIC, the first instruction is actually "GR+hi(&G)".
1483 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1484 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1486 // Generate non-pic code that has direct accesses to the constant pool.
1487 // The address of the global is just (hi(&g)+lo(&g)).
1488 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1491 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1492 SelectionDAG &DAG) const {
1493 EVT PtrVT = Op.getValueType();
1494 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1495 const Constant *C = CP->getConstVal();
1497 // 64-bit SVR4 ABI code is always position-independent.
1498 // The actual address of the GlobalValue is stored in the TOC.
1499 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1500 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1501 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1502 DAG.getRegister(PPC::X2, MVT::i64));
1505 unsigned MOHiFlag, MOLoFlag;
1506 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1508 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1510 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1511 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1514 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1515 EVT PtrVT = Op.getValueType();
1516 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1518 // 64-bit SVR4 ABI code is always position-independent.
1519 // The actual address of the GlobalValue is stored in the TOC.
1520 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1521 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1522 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1523 DAG.getRegister(PPC::X2, MVT::i64));
1526 unsigned MOHiFlag, MOLoFlag;
1527 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1528 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1529 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1530 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1533 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1534 SelectionDAG &DAG) const {
1535 EVT PtrVT = Op.getValueType();
1537 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1539 unsigned MOHiFlag, MOLoFlag;
1540 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1541 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1542 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1543 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1546 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1547 SelectionDAG &DAG) const {
1549 // FIXME: TLS addresses currently use medium model code sequences,
1550 // which is the most useful form. Eventually support for small and
1551 // large models could be added if users need it, at the cost of
1552 // additional complexity.
1553 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1555 const GlobalValue *GV = GA->getGlobal();
1556 EVT PtrVT = getPointerTy();
1557 bool is64bit = PPCSubTarget.isPPC64();
1559 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1561 if (Model == TLSModel::LocalExec) {
1562 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1563 PPCII::MO_TPREL_HA);
1564 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1565 PPCII::MO_TPREL_LO);
1566 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1567 is64bit ? MVT::i64 : MVT::i32);
1568 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1569 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1572 if (Model == TLSModel::InitialExec) {
1573 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1574 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1578 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1579 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1580 PtrVT, GOTReg, TGA);
1582 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1583 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1584 PtrVT, TGA, GOTPtr);
1585 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1588 if (Model == TLSModel::GeneralDynamic) {
1589 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1590 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1591 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1593 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1596 // We need a chain node, and don't have one handy. The underlying
1597 // call has no side effects, so using the function entry node
1599 SDValue Chain = DAG.getEntryNode();
1600 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1601 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1602 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1603 PtrVT, ParmReg, TGA);
1604 // The return value from GET_TLS_ADDR really is in X3 already, but
1605 // some hacks are needed here to tie everything together. The extra
1606 // copies dissolve during subsequent transforms.
1607 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1608 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1611 if (Model == TLSModel::LocalDynamic) {
1612 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1613 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1614 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1616 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1619 // We need a chain node, and don't have one handy. The underlying
1620 // call has no side effects, so using the function entry node
1622 SDValue Chain = DAG.getEntryNode();
1623 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1624 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1625 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1626 PtrVT, ParmReg, TGA);
1627 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1628 // some hacks are needed here to tie everything together. The extra
1629 // copies dissolve during subsequent transforms.
1630 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1631 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1632 Chain, ParmReg, TGA);
1633 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1636 llvm_unreachable("Unknown TLS model!");
1639 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1640 SelectionDAG &DAG) const {
1641 EVT PtrVT = Op.getValueType();
1642 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1644 const GlobalValue *GV = GSDN->getGlobal();
1646 // 64-bit SVR4 ABI code is always position-independent.
1647 // The actual address of the GlobalValue is stored in the TOC.
1648 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1649 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1650 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1651 DAG.getRegister(PPC::X2, MVT::i64));
1654 unsigned MOHiFlag, MOLoFlag;
1655 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1658 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1660 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1662 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1664 // If the global reference is actually to a non-lazy-pointer, we have to do an
1665 // extra load to get the address of the global.
1666 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1667 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1668 false, false, false, 0);
1672 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1673 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1676 if (Op.getValueType() == MVT::v2i64) {
1677 // When the operands themselves are v2i64 values, we need to do something
1678 // special because VSX has no underlying comparison operations for these.
1679 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1680 // Equality can be handled by casting to the legal type for Altivec
1681 // comparisons, everything else needs to be expanded.
1682 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1683 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1684 DAG.getSetCC(dl, MVT::v4i32,
1685 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1686 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1693 // We handle most of these in the usual way.
1697 // If we're comparing for equality to zero, expose the fact that this is
1698 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1699 // fold the new nodes.
1700 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1701 if (C->isNullValue() && CC == ISD::SETEQ) {
1702 EVT VT = Op.getOperand(0).getValueType();
1703 SDValue Zext = Op.getOperand(0);
1704 if (VT.bitsLT(MVT::i32)) {
1706 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1708 unsigned Log2b = Log2_32(VT.getSizeInBits());
1709 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1710 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1711 DAG.getConstant(Log2b, MVT::i32));
1712 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1714 // Leave comparisons against 0 and -1 alone for now, since they're usually
1715 // optimized. FIXME: revisit this when we can custom lower all setcc
1717 if (C->isAllOnesValue() || C->isNullValue())
1721 // If we have an integer seteq/setne, turn it into a compare against zero
1722 // by xor'ing the rhs with the lhs, which is faster than setting a
1723 // condition register, reading it back out, and masking the correct bit. The
1724 // normal approach here uses sub to do this instead of xor. Using xor exposes
1725 // the result to other bit-twiddling opportunities.
1726 EVT LHSVT = Op.getOperand(0).getValueType();
1727 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1728 EVT VT = Op.getValueType();
1729 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1731 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1736 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1737 const PPCSubtarget &Subtarget) const {
1738 SDNode *Node = Op.getNode();
1739 EVT VT = Node->getValueType(0);
1740 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1741 SDValue InChain = Node->getOperand(0);
1742 SDValue VAListPtr = Node->getOperand(1);
1743 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1746 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1749 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1750 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1752 InChain = GprIndex.getValue(1);
1754 if (VT == MVT::i64) {
1755 // Check if GprIndex is even
1756 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1757 DAG.getConstant(1, MVT::i32));
1758 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1759 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1760 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1761 DAG.getConstant(1, MVT::i32));
1762 // Align GprIndex to be even if it isn't
1763 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1767 // fpr index is 1 byte after gpr
1768 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1769 DAG.getConstant(1, MVT::i32));
1772 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1773 FprPtr, MachinePointerInfo(SV), MVT::i8,
1775 InChain = FprIndex.getValue(1);
1777 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1778 DAG.getConstant(8, MVT::i32));
1780 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1781 DAG.getConstant(4, MVT::i32));
1784 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1785 MachinePointerInfo(), false, false,
1787 InChain = OverflowArea.getValue(1);
1789 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1790 MachinePointerInfo(), false, false,
1792 InChain = RegSaveArea.getValue(1);
1794 // select overflow_area if index > 8
1795 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1796 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1798 // adjustment constant gpr_index * 4/8
1799 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1800 VT.isInteger() ? GprIndex : FprIndex,
1801 DAG.getConstant(VT.isInteger() ? 4 : 8,
1804 // OurReg = RegSaveArea + RegConstant
1805 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1808 // Floating types are 32 bytes into RegSaveArea
1809 if (VT.isFloatingPoint())
1810 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1811 DAG.getConstant(32, MVT::i32));
1813 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1814 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1815 VT.isInteger() ? GprIndex : FprIndex,
1816 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1819 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1820 VT.isInteger() ? VAListPtr : FprPtr,
1821 MachinePointerInfo(SV),
1822 MVT::i8, false, false, 0);
1824 // determine if we should load from reg_save_area or overflow_area
1825 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1827 // increase overflow_area by 4/8 if gpr/fpr > 8
1828 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1829 DAG.getConstant(VT.isInteger() ? 4 : 8,
1832 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1835 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1837 MachinePointerInfo(),
1838 MVT::i32, false, false, 0);
1840 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1841 false, false, false, 0);
1844 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1845 const PPCSubtarget &Subtarget) const {
1846 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1848 // We have to copy the entire va_list struct:
1849 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1850 return DAG.getMemcpy(Op.getOperand(0), Op,
1851 Op.getOperand(1), Op.getOperand(2),
1852 DAG.getConstant(12, MVT::i32), 8, false, true,
1853 MachinePointerInfo(), MachinePointerInfo());
1856 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1857 SelectionDAG &DAG) const {
1858 return Op.getOperand(0);
1861 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1862 SelectionDAG &DAG) const {
1863 SDValue Chain = Op.getOperand(0);
1864 SDValue Trmp = Op.getOperand(1); // trampoline
1865 SDValue FPtr = Op.getOperand(2); // nested function
1866 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1869 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1870 bool isPPC64 = (PtrVT == MVT::i64);
1872 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1875 TargetLowering::ArgListTy Args;
1876 TargetLowering::ArgListEntry Entry;
1878 Entry.Ty = IntPtrTy;
1879 Entry.Node = Trmp; Args.push_back(Entry);
1881 // TrampSize == (isPPC64 ? 48 : 40);
1882 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1883 isPPC64 ? MVT::i64 : MVT::i32);
1884 Args.push_back(Entry);
1886 Entry.Node = FPtr; Args.push_back(Entry);
1887 Entry.Node = Nest; Args.push_back(Entry);
1889 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1890 TargetLowering::CallLoweringInfo CLI(Chain,
1891 Type::getVoidTy(*DAG.getContext()),
1892 false, false, false, false, 0,
1894 /*isTailCall=*/false,
1895 /*doesNotRet=*/false,
1896 /*isReturnValueUsed=*/true,
1897 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1899 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1901 return CallResult.second;
1904 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1905 const PPCSubtarget &Subtarget) const {
1906 MachineFunction &MF = DAG.getMachineFunction();
1907 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1911 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1912 // vastart just stores the address of the VarArgsFrameIndex slot into the
1913 // memory location argument.
1914 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1915 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1916 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1917 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1918 MachinePointerInfo(SV),
1922 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1923 // We suppose the given va_list is already allocated.
1926 // char gpr; /* index into the array of 8 GPRs
1927 // * stored in the register save area
1928 // * gpr=0 corresponds to r3,
1929 // * gpr=1 to r4, etc.
1931 // char fpr; /* index into the array of 8 FPRs
1932 // * stored in the register save area
1933 // * fpr=0 corresponds to f1,
1934 // * fpr=1 to f2, etc.
1936 // char *overflow_arg_area;
1937 // /* location on stack that holds
1938 // * the next overflow argument
1940 // char *reg_save_area;
1941 // /* where r3:r10 and f1:f8 (if saved)
1947 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1948 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1951 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1953 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1955 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1958 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1959 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1961 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1962 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1964 uint64_t FPROffset = 1;
1965 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1967 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1969 // Store first byte : number of int regs
1970 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1972 MachinePointerInfo(SV),
1973 MVT::i8, false, false, 0);
1974 uint64_t nextOffset = FPROffset;
1975 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1978 // Store second byte : number of float regs
1979 SDValue secondStore =
1980 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1981 MachinePointerInfo(SV, nextOffset), MVT::i8,
1983 nextOffset += StackOffset;
1984 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1986 // Store second word : arguments given on stack
1987 SDValue thirdStore =
1988 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1989 MachinePointerInfo(SV, nextOffset),
1991 nextOffset += FrameOffset;
1992 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1994 // Store third word : arguments given in registers
1995 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1996 MachinePointerInfo(SV, nextOffset),
2001 #include "PPCGenCallingConv.inc"
2003 // Function whose sole purpose is to kill compiler warnings
2004 // stemming from unused functions included from PPCGenCallingConv.inc.
2005 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2006 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2009 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2010 CCValAssign::LocInfo &LocInfo,
2011 ISD::ArgFlagsTy &ArgFlags,
2016 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2018 CCValAssign::LocInfo &LocInfo,
2019 ISD::ArgFlagsTy &ArgFlags,
2021 static const MCPhysReg ArgRegs[] = {
2022 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2023 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2025 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2027 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2029 // Skip one register if the first unallocated register has an even register
2030 // number and there are still argument registers available which have not been
2031 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2032 // need to skip a register if RegNum is odd.
2033 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2034 State.AllocateReg(ArgRegs[RegNum]);
2037 // Always return false here, as this function only makes sure that the first
2038 // unallocated register has an odd register number and does not actually
2039 // allocate a register for the current argument.
2043 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2045 CCValAssign::LocInfo &LocInfo,
2046 ISD::ArgFlagsTy &ArgFlags,
2048 static const MCPhysReg ArgRegs[] = {
2049 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2053 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2055 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2057 // If there is only one Floating-point register left we need to put both f64
2058 // values of a split ppc_fp128 value on the stack.
2059 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2060 State.AllocateReg(ArgRegs[RegNum]);
2063 // Always return false here, as this function only makes sure that the two f64
2064 // values a ppc_fp128 value is split into are both passed in registers or both
2065 // passed on the stack and does not actually allocate a register for the
2066 // current argument.
2070 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2072 static const MCPhysReg *GetFPR() {
2073 static const MCPhysReg FPR[] = {
2074 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2075 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2081 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2083 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2084 unsigned PtrByteSize) {
2085 unsigned ArgSize = ArgVT.getStoreSize();
2086 if (Flags.isByVal())
2087 ArgSize = Flags.getByValSize();
2088 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2094 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2095 CallingConv::ID CallConv, bool isVarArg,
2096 const SmallVectorImpl<ISD::InputArg>
2098 SDLoc dl, SelectionDAG &DAG,
2099 SmallVectorImpl<SDValue> &InVals)
2101 if (PPCSubTarget.isSVR4ABI()) {
2102 if (PPCSubTarget.isPPC64())
2103 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2106 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2109 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2115 PPCTargetLowering::LowerFormalArguments_32SVR4(
2117 CallingConv::ID CallConv, bool isVarArg,
2118 const SmallVectorImpl<ISD::InputArg>
2120 SDLoc dl, SelectionDAG &DAG,
2121 SmallVectorImpl<SDValue> &InVals) const {
2123 // 32-bit SVR4 ABI Stack Frame Layout:
2124 // +-----------------------------------+
2125 // +--> | Back chain |
2126 // | +-----------------------------------+
2127 // | | Floating-point register save area |
2128 // | +-----------------------------------+
2129 // | | General register save area |
2130 // | +-----------------------------------+
2131 // | | CR save word |
2132 // | +-----------------------------------+
2133 // | | VRSAVE save word |
2134 // | +-----------------------------------+
2135 // | | Alignment padding |
2136 // | +-----------------------------------+
2137 // | | Vector register save area |
2138 // | +-----------------------------------+
2139 // | | Local variable space |
2140 // | +-----------------------------------+
2141 // | | Parameter list area |
2142 // | +-----------------------------------+
2143 // | | LR save word |
2144 // | +-----------------------------------+
2145 // SP--> +--- | Back chain |
2146 // +-----------------------------------+
2149 // System V Application Binary Interface PowerPC Processor Supplement
2150 // AltiVec Technology Programming Interface Manual
2152 MachineFunction &MF = DAG.getMachineFunction();
2153 MachineFrameInfo *MFI = MF.getFrameInfo();
2154 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2156 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2157 // Potential tail calls could cause overwriting of argument stack slots.
2158 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2159 (CallConv == CallingConv::Fast));
2160 unsigned PtrByteSize = 4;
2162 // Assign locations to all of the incoming arguments.
2163 SmallVector<CCValAssign, 16> ArgLocs;
2164 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2165 getTargetMachine(), ArgLocs, *DAG.getContext());
2167 // Reserve space for the linkage area on the stack.
2168 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2170 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2172 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2173 CCValAssign &VA = ArgLocs[i];
2175 // Arguments stored in registers.
2176 if (VA.isRegLoc()) {
2177 const TargetRegisterClass *RC;
2178 EVT ValVT = VA.getValVT();
2180 switch (ValVT.getSimpleVT().SimpleTy) {
2182 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2185 RC = &PPC::GPRCRegClass;
2188 RC = &PPC::F4RCRegClass;
2191 if (PPCSubTarget.hasVSX())
2192 RC = &PPC::VSFRCRegClass;
2194 RC = &PPC::F8RCRegClass;
2200 RC = &PPC::VRRCRegClass;
2204 RC = &PPC::VSHRCRegClass;
2208 // Transform the arguments stored in physical registers into virtual ones.
2209 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2210 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2211 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2213 if (ValVT == MVT::i1)
2214 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2216 InVals.push_back(ArgValue);
2218 // Argument stored in memory.
2219 assert(VA.isMemLoc());
2221 unsigned ArgSize = VA.getLocVT().getStoreSize();
2222 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2225 // Create load nodes to retrieve arguments from the stack.
2226 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2227 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2228 MachinePointerInfo(),
2229 false, false, false, 0));
2233 // Assign locations to all of the incoming aggregate by value arguments.
2234 // Aggregates passed by value are stored in the local variable space of the
2235 // caller's stack frame, right above the parameter list area.
2236 SmallVector<CCValAssign, 16> ByValArgLocs;
2237 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2238 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2240 // Reserve stack space for the allocations in CCInfo.
2241 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2243 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2245 // Area that is at least reserved in the caller of this function.
2246 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2248 // Set the size that is at least reserved in caller of this function. Tail
2249 // call optimized function's reserved stack space needs to be aligned so that
2250 // taking the difference between two stack areas will result in an aligned
2252 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2255 std::max(MinReservedArea,
2256 PPCFrameLowering::getMinCallFrameSize(false, false));
2258 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2259 getStackAlignment();
2260 unsigned AlignMask = TargetAlign-1;
2261 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2263 FI->setMinReservedArea(MinReservedArea);
2265 SmallVector<SDValue, 8> MemOps;
2267 // If the function takes variable number of arguments, make a frame index for
2268 // the start of the first vararg value... for expansion of llvm.va_start.
2270 static const MCPhysReg GPArgRegs[] = {
2271 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2272 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2274 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2276 static const MCPhysReg FPArgRegs[] = {
2277 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2280 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2282 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2284 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2287 // Make room for NumGPArgRegs and NumFPArgRegs.
2288 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2289 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2291 FuncInfo->setVarArgsStackOffset(
2292 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2293 CCInfo.getNextStackOffset(), true));
2295 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2296 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2298 // The fixed integer arguments of a variadic function are stored to the
2299 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2300 // the result of va_next.
2301 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2302 // Get an existing live-in vreg, or add a new one.
2303 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2305 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2307 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2308 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2309 MachinePointerInfo(), false, false, 0);
2310 MemOps.push_back(Store);
2311 // Increment the address by four for the next argument to store
2312 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2313 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2316 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2318 // The double arguments are stored to the VarArgsFrameIndex
2320 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2321 // Get an existing live-in vreg, or add a new one.
2322 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2324 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2326 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2327 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2328 MachinePointerInfo(), false, false, 0);
2329 MemOps.push_back(Store);
2330 // Increment the address by eight for the next argument to store
2331 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2333 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2337 if (!MemOps.empty())
2338 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2343 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2344 // value to MVT::i64 and then truncate to the correct register size.
2346 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2347 SelectionDAG &DAG, SDValue ArgVal,
2350 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2351 DAG.getValueType(ObjectVT));
2352 else if (Flags.isZExt())
2353 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2354 DAG.getValueType(ObjectVT));
2356 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2359 // Set the size that is at least reserved in caller of this function. Tail
2360 // call optimized functions' reserved stack space needs to be aligned so that
2361 // taking the difference between two stack areas will result in an aligned
2364 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2365 unsigned nAltivecParamsAtEnd,
2366 unsigned MinReservedArea,
2367 bool isPPC64) const {
2368 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2369 // Add the Altivec parameters at the end, if needed.
2370 if (nAltivecParamsAtEnd) {
2371 MinReservedArea = ((MinReservedArea+15)/16)*16;
2372 MinReservedArea += 16*nAltivecParamsAtEnd;
2375 std::max(MinReservedArea,
2376 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2377 unsigned TargetAlign
2378 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2379 getStackAlignment();
2380 unsigned AlignMask = TargetAlign-1;
2381 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2382 FI->setMinReservedArea(MinReservedArea);
2386 PPCTargetLowering::LowerFormalArguments_64SVR4(
2388 CallingConv::ID CallConv, bool isVarArg,
2389 const SmallVectorImpl<ISD::InputArg>
2391 SDLoc dl, SelectionDAG &DAG,
2392 SmallVectorImpl<SDValue> &InVals) const {
2393 // TODO: add description of PPC stack frame format, or at least some docs.
2395 MachineFunction &MF = DAG.getMachineFunction();
2396 MachineFrameInfo *MFI = MF.getFrameInfo();
2397 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2399 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2400 // Potential tail calls could cause overwriting of argument stack slots.
2401 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2402 (CallConv == CallingConv::Fast));
2403 unsigned PtrByteSize = 8;
2405 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2406 // Area that is at least reserved in caller of this function.
2407 unsigned MinReservedArea = ArgOffset;
2409 static const MCPhysReg GPR[] = {
2410 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2411 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2414 static const MCPhysReg *FPR = GetFPR();
2416 static const MCPhysReg VR[] = {
2417 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2418 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2420 static const MCPhysReg VSRH[] = {
2421 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2422 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2425 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2426 const unsigned Num_FPR_Regs = 13;
2427 const unsigned Num_VR_Regs = array_lengthof(VR);
2429 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2431 // Add DAG nodes to load the arguments or copy them out of registers. On
2432 // entry to a function on PPC, the arguments start after the linkage area,
2433 // although the first ones are often in registers.
2435 SmallVector<SDValue, 8> MemOps;
2436 unsigned nAltivecParamsAtEnd = 0;
2437 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2438 unsigned CurArgIdx = 0;
2439 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2441 bool needsLoad = false;
2442 EVT ObjectVT = Ins[ArgNo].VT;
2443 unsigned ObjSize = ObjectVT.getStoreSize();
2444 unsigned ArgSize = ObjSize;
2445 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2446 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2447 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2449 unsigned CurArgOffset = ArgOffset;
2451 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2452 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2453 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2454 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64) {
2456 MinReservedArea = ((MinReservedArea+15)/16)*16;
2457 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2461 nAltivecParamsAtEnd++;
2463 // Calculate min reserved area.
2464 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2468 // FIXME the codegen can be much improved in some cases.
2469 // We do not have to keep everything in memory.
2470 if (Flags.isByVal()) {
2471 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2472 ObjSize = Flags.getByValSize();
2473 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2474 // Empty aggregate parameters do not take up registers. Examples:
2478 // etc. However, we have to provide a place-holder in InVals, so
2479 // pretend we have an 8-byte item at the current address for that
2482 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2483 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2484 InVals.push_back(FIN);
2488 unsigned BVAlign = Flags.getByValAlign();
2490 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2491 CurArgOffset = ArgOffset;
2494 // All aggregates smaller than 8 bytes must be passed right-justified.
2495 if (ObjSize < PtrByteSize)
2496 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2497 // The value of the object is its address.
2498 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2499 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2500 InVals.push_back(FIN);
2503 if (GPR_idx != Num_GPR_Regs) {
2504 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2505 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2508 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2509 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2510 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2511 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2512 MachinePointerInfo(FuncArg),
2513 ObjType, false, false, 0);
2515 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2516 // store the whole register as-is to the parameter save area
2517 // slot. The address of the parameter was already calculated
2518 // above (InVals.push_back(FIN)) to be the right-justified
2519 // offset within the slot. For this store, we need a new
2520 // frame index that points at the beginning of the slot.
2521 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2522 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2523 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2524 MachinePointerInfo(FuncArg),
2528 MemOps.push_back(Store);
2531 // Whether we copied from a register or not, advance the offset
2532 // into the parameter save area by a full doubleword.
2533 ArgOffset += PtrByteSize;
2537 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2538 // Store whatever pieces of the object are in registers
2539 // to memory. ArgOffset will be the address of the beginning
2541 if (GPR_idx != Num_GPR_Regs) {
2543 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2544 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2545 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2546 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2547 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2548 MachinePointerInfo(FuncArg, j),
2550 MemOps.push_back(Store);
2552 ArgOffset += PtrByteSize;
2554 ArgOffset += ArgSize - j;
2561 switch (ObjectVT.getSimpleVT().SimpleTy) {
2562 default: llvm_unreachable("Unhandled argument type!");
2566 if (GPR_idx != Num_GPR_Regs) {
2567 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2568 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2570 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2571 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2572 // value to MVT::i64 and then truncate to the correct register size.
2573 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2578 ArgSize = PtrByteSize;
2585 // Every 8 bytes of argument space consumes one of the GPRs available for
2586 // argument passing.
2587 if (GPR_idx != Num_GPR_Regs) {
2590 if (FPR_idx != Num_FPR_Regs) {
2593 if (ObjectVT == MVT::f32)
2594 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2596 VReg = MF.addLiveIn(FPR[FPR_idx], PPCSubTarget.hasVSX() ?
2597 &PPC::VSFRCRegClass :
2598 &PPC::F8RCRegClass);
2600 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2604 ArgSize = PtrByteSize;
2615 // Note that vector arguments in registers don't reserve stack space,
2616 // except in varargs functions.
2617 if (VR_idx != Num_VR_Regs) {
2618 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2619 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2620 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2621 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2623 while ((ArgOffset % 16) != 0) {
2624 ArgOffset += PtrByteSize;
2625 if (GPR_idx != Num_GPR_Regs)
2629 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2633 // Vectors are aligned.
2634 ArgOffset = ((ArgOffset+15)/16)*16;
2635 CurArgOffset = ArgOffset;
2642 // We need to load the argument to a virtual register if we determined
2643 // above that we ran out of physical registers of the appropriate type.
2645 int FI = MFI->CreateFixedObject(ObjSize,
2646 CurArgOffset + (ArgSize - ObjSize),
2648 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2649 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2650 false, false, false, 0);
2653 InVals.push_back(ArgVal);
2656 // Set the size that is at least reserved in caller of this function. Tail
2657 // call optimized functions' reserved stack space needs to be aligned so that
2658 // taking the difference between two stack areas will result in an aligned
2660 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2662 // If the function takes variable number of arguments, make a frame index for
2663 // the start of the first vararg value... for expansion of llvm.va_start.
2665 int Depth = ArgOffset;
2667 FuncInfo->setVarArgsFrameIndex(
2668 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2669 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2671 // If this function is vararg, store any remaining integer argument regs
2672 // to their spots on the stack so that they may be loaded by deferencing the
2673 // result of va_next.
2674 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2675 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2676 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2677 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2678 MachinePointerInfo(), false, false, 0);
2679 MemOps.push_back(Store);
2680 // Increment the address by four for the next argument to store
2681 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2682 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2686 if (!MemOps.empty())
2687 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2693 PPCTargetLowering::LowerFormalArguments_Darwin(
2695 CallingConv::ID CallConv, bool isVarArg,
2696 const SmallVectorImpl<ISD::InputArg>
2698 SDLoc dl, SelectionDAG &DAG,
2699 SmallVectorImpl<SDValue> &InVals) const {
2700 // TODO: add description of PPC stack frame format, or at least some docs.
2702 MachineFunction &MF = DAG.getMachineFunction();
2703 MachineFrameInfo *MFI = MF.getFrameInfo();
2704 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2706 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2707 bool isPPC64 = PtrVT == MVT::i64;
2708 // Potential tail calls could cause overwriting of argument stack slots.
2709 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2710 (CallConv == CallingConv::Fast));
2711 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2713 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2714 // Area that is at least reserved in caller of this function.
2715 unsigned MinReservedArea = ArgOffset;
2717 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2718 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2719 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2721 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2722 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2723 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2726 static const MCPhysReg *FPR = GetFPR();
2728 static const MCPhysReg VR[] = {
2729 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2730 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2733 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2734 const unsigned Num_FPR_Regs = 13;
2735 const unsigned Num_VR_Regs = array_lengthof( VR);
2737 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2739 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2741 // In 32-bit non-varargs functions, the stack space for vectors is after the
2742 // stack space for non-vectors. We do not use this space unless we have
2743 // too many vectors to fit in registers, something that only occurs in
2744 // constructed examples:), but we have to walk the arglist to figure
2745 // that out...for the pathological case, compute VecArgOffset as the
2746 // start of the vector parameter area. Computing VecArgOffset is the
2747 // entire point of the following loop.
2748 unsigned VecArgOffset = ArgOffset;
2749 if (!isVarArg && !isPPC64) {
2750 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2752 EVT ObjectVT = Ins[ArgNo].VT;
2753 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2755 if (Flags.isByVal()) {
2756 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2757 unsigned ObjSize = Flags.getByValSize();
2759 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2760 VecArgOffset += ArgSize;
2764 switch(ObjectVT.getSimpleVT().SimpleTy) {
2765 default: llvm_unreachable("Unhandled argument type!");
2771 case MVT::i64: // PPC64
2773 // FIXME: We are guaranteed to be !isPPC64 at this point.
2774 // Does MVT::i64 apply?
2781 // Nothing to do, we're only looking at Nonvector args here.
2786 // We've found where the vector parameter area in memory is. Skip the
2787 // first 12 parameters; these don't use that memory.
2788 VecArgOffset = ((VecArgOffset+15)/16)*16;
2789 VecArgOffset += 12*16;
2791 // Add DAG nodes to load the arguments or copy them out of registers. On
2792 // entry to a function on PPC, the arguments start after the linkage area,
2793 // although the first ones are often in registers.
2795 SmallVector<SDValue, 8> MemOps;
2796 unsigned nAltivecParamsAtEnd = 0;
2797 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2798 unsigned CurArgIdx = 0;
2799 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2801 bool needsLoad = false;
2802 EVT ObjectVT = Ins[ArgNo].VT;
2803 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2804 unsigned ArgSize = ObjSize;
2805 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2806 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2807 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2809 unsigned CurArgOffset = ArgOffset;
2811 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2812 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2813 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2814 if (isVarArg || isPPC64) {
2815 MinReservedArea = ((MinReservedArea+15)/16)*16;
2816 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2819 } else nAltivecParamsAtEnd++;
2821 // Calculate min reserved area.
2822 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2826 // FIXME the codegen can be much improved in some cases.
2827 // We do not have to keep everything in memory.
2828 if (Flags.isByVal()) {
2829 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2830 ObjSize = Flags.getByValSize();
2831 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2832 // Objects of size 1 and 2 are right justified, everything else is
2833 // left justified. This means the memory address is adjusted forwards.
2834 if (ObjSize==1 || ObjSize==2) {
2835 CurArgOffset = CurArgOffset + (4 - ObjSize);
2837 // The value of the object is its address.
2838 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2839 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2840 InVals.push_back(FIN);
2841 if (ObjSize==1 || ObjSize==2) {
2842 if (GPR_idx != Num_GPR_Regs) {
2845 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2847 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2848 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2849 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2850 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2851 MachinePointerInfo(FuncArg),
2852 ObjType, false, false, 0);
2853 MemOps.push_back(Store);
2857 ArgOffset += PtrByteSize;
2861 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2862 // Store whatever pieces of the object are in registers
2863 // to memory. ArgOffset will be the address of the beginning
2865 if (GPR_idx != Num_GPR_Regs) {
2868 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2870 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2871 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2872 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2873 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2874 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2875 MachinePointerInfo(FuncArg, j),
2877 MemOps.push_back(Store);
2879 ArgOffset += PtrByteSize;
2881 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2888 switch (ObjectVT.getSimpleVT().SimpleTy) {
2889 default: llvm_unreachable("Unhandled argument type!");
2893 if (GPR_idx != Num_GPR_Regs) {
2894 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2895 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2897 if (ObjectVT == MVT::i1)
2898 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2903 ArgSize = PtrByteSize;
2905 // All int arguments reserve stack space in the Darwin ABI.
2906 ArgOffset += PtrByteSize;
2910 case MVT::i64: // PPC64
2911 if (GPR_idx != Num_GPR_Regs) {
2912 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2913 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2915 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2916 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2917 // value to MVT::i64 and then truncate to the correct register size.
2918 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2923 ArgSize = PtrByteSize;
2925 // All int arguments reserve stack space in the Darwin ABI.
2931 // Every 4 bytes of argument space consumes one of the GPRs available for
2932 // argument passing.
2933 if (GPR_idx != Num_GPR_Regs) {
2935 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2938 if (FPR_idx != Num_FPR_Regs) {
2941 if (ObjectVT == MVT::f32)
2942 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2944 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2946 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2952 // All FP arguments reserve stack space in the Darwin ABI.
2953 ArgOffset += isPPC64 ? 8 : ObjSize;
2959 // Note that vector arguments in registers don't reserve stack space,
2960 // except in varargs functions.
2961 if (VR_idx != Num_VR_Regs) {
2962 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2963 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2965 while ((ArgOffset % 16) != 0) {
2966 ArgOffset += PtrByteSize;
2967 if (GPR_idx != Num_GPR_Regs)
2971 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2975 if (!isVarArg && !isPPC64) {
2976 // Vectors go after all the nonvectors.
2977 CurArgOffset = VecArgOffset;
2980 // Vectors are aligned.
2981 ArgOffset = ((ArgOffset+15)/16)*16;
2982 CurArgOffset = ArgOffset;
2990 // We need to load the argument to a virtual register if we determined above
2991 // that we ran out of physical registers of the appropriate type.
2993 int FI = MFI->CreateFixedObject(ObjSize,
2994 CurArgOffset + (ArgSize - ObjSize),
2996 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2997 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2998 false, false, false, 0);
3001 InVals.push_back(ArgVal);
3004 // Set the size that is at least reserved in caller of this function. Tail
3005 // call optimized functions' reserved stack space needs to be aligned so that
3006 // taking the difference between two stack areas will result in an aligned
3008 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
3010 // If the function takes variable number of arguments, make a frame index for
3011 // the start of the first vararg value... for expansion of llvm.va_start.
3013 int Depth = ArgOffset;
3015 FuncInfo->setVarArgsFrameIndex(
3016 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3018 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3020 // If this function is vararg, store any remaining integer argument regs
3021 // to their spots on the stack so that they may be loaded by deferencing the
3022 // result of va_next.
3023 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3027 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3029 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3031 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3032 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3033 MachinePointerInfo(), false, false, 0);
3034 MemOps.push_back(Store);
3035 // Increment the address by four for the next argument to store
3036 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3037 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3041 if (!MemOps.empty())
3042 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3047 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
3048 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
3050 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
3054 const SmallVectorImpl<ISD::OutputArg>
3056 const SmallVectorImpl<SDValue> &OutVals,
3057 unsigned &nAltivecParamsAtEnd) {
3058 // Count how many bytes are to be pushed on the stack, including the linkage
3059 // area, and parameter passing area. We start with 24/48 bytes, which is
3060 // prereserved space for [SP][CR][LR][3 x unused].
3061 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
3062 unsigned NumOps = Outs.size();
3063 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3065 // Add up all the space actually used.
3066 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
3067 // they all go in registers, but we must reserve stack space for them for
3068 // possible use by the caller. In varargs or 64-bit calls, parameters are
3069 // assigned stack space in order, with padding so Altivec parameters are
3071 nAltivecParamsAtEnd = 0;
3072 for (unsigned i = 0; i != NumOps; ++i) {
3073 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3074 EVT ArgVT = Outs[i].VT;
3075 // Varargs Altivec parameters are padded to a 16 byte boundary.
3076 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
3077 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8 ||
3078 ArgVT==MVT::v2f64 || ArgVT==MVT::v2i64) {
3079 if (!isVarArg && !isPPC64) {
3080 // Non-varargs Altivec parameters go after all the non-Altivec
3081 // parameters; handle those later so we know how much padding we need.
3082 nAltivecParamsAtEnd++;
3085 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
3086 NumBytes = ((NumBytes+15)/16)*16;
3088 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3091 // Allow for Altivec parameters at the end, if needed.
3092 if (nAltivecParamsAtEnd) {
3093 NumBytes = ((NumBytes+15)/16)*16;
3094 NumBytes += 16*nAltivecParamsAtEnd;
3097 // The prolog code of the callee may store up to 8 GPR argument registers to
3098 // the stack, allowing va_start to index over them in memory if its varargs.
3099 // Because we cannot tell if this is needed on the caller side, we have to
3100 // conservatively assume that it is needed. As such, make sure we have at
3101 // least enough stack space for the caller to store the 8 GPRs.
3102 NumBytes = std::max(NumBytes,
3103 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
3105 // Tail call needs the stack to be aligned.
3106 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
3107 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
3108 getFrameLowering()->getStackAlignment();
3109 unsigned AlignMask = TargetAlign-1;
3110 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3116 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3117 /// adjusted to accommodate the arguments for the tailcall.
3118 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3119 unsigned ParamSize) {
3121 if (!isTailCall) return 0;
3123 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3124 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3125 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3126 // Remember only if the new adjustement is bigger.
3127 if (SPDiff < FI->getTailCallSPDelta())
3128 FI->setTailCallSPDelta(SPDiff);
3133 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3134 /// for tail call optimization. Targets which want to do tail call
3135 /// optimization should implement this function.
3137 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3138 CallingConv::ID CalleeCC,
3140 const SmallVectorImpl<ISD::InputArg> &Ins,
3141 SelectionDAG& DAG) const {
3142 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3145 // Variable argument functions are not supported.
3149 MachineFunction &MF = DAG.getMachineFunction();
3150 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3151 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3152 // Functions containing by val parameters are not supported.
3153 for (unsigned i = 0; i != Ins.size(); i++) {
3154 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3155 if (Flags.isByVal()) return false;
3158 // Non-PIC/GOT tail calls are supported.
3159 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3162 // At the moment we can only do local tail calls (in same module, hidden
3163 // or protected) if we are generating PIC.
3164 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3165 return G->getGlobal()->hasHiddenVisibility()
3166 || G->getGlobal()->hasProtectedVisibility();
3172 /// isCallCompatibleAddress - Return the immediate to use if the specified
3173 /// 32-bit value is representable in the immediate field of a BxA instruction.
3174 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3175 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3176 if (!C) return nullptr;
3178 int Addr = C->getZExtValue();
3179 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3180 SignExtend32<26>(Addr) != Addr)
3181 return nullptr; // Top 6 bits have to be sext of immediate.
3183 return DAG.getConstant((int)C->getZExtValue() >> 2,
3184 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3189 struct TailCallArgumentInfo {
3194 TailCallArgumentInfo() : FrameIdx(0) {}
3199 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3201 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3203 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3204 SmallVectorImpl<SDValue> &MemOpChains,
3206 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3207 SDValue Arg = TailCallArgs[i].Arg;
3208 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3209 int FI = TailCallArgs[i].FrameIdx;
3210 // Store relative to framepointer.
3211 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3212 MachinePointerInfo::getFixedStack(FI),
3217 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3218 /// the appropriate stack slot for the tail call optimized function call.
3219 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3220 MachineFunction &MF,
3229 // Calculate the new stack slot for the return address.
3230 int SlotSize = isPPC64 ? 8 : 4;
3231 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3233 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3234 NewRetAddrLoc, true);
3235 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3236 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3237 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3238 MachinePointerInfo::getFixedStack(NewRetAddr),
3241 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3242 // slot as the FP is never overwritten.
3245 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3246 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3248 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3249 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3250 MachinePointerInfo::getFixedStack(NewFPIdx),
3257 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3258 /// the position of the argument.
3260 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3261 SDValue Arg, int SPDiff, unsigned ArgOffset,
3262 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3263 int Offset = ArgOffset + SPDiff;
3264 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3265 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3266 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3267 SDValue FIN = DAG.getFrameIndex(FI, VT);
3268 TailCallArgumentInfo Info;
3270 Info.FrameIdxOp = FIN;
3272 TailCallArguments.push_back(Info);
3275 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3276 /// stack slot. Returns the chain as result and the loaded frame pointers in
3277 /// LROpOut/FPOpout. Used when tail calling.
3278 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3286 // Load the LR and FP stack slot for later adjusting.
3287 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3288 LROpOut = getReturnAddrFrameIndex(DAG);
3289 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3290 false, false, false, 0);
3291 Chain = SDValue(LROpOut.getNode(), 1);
3293 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3294 // slot as the FP is never overwritten.
3296 FPOpOut = getFramePointerFrameIndex(DAG);
3297 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3298 false, false, false, 0);
3299 Chain = SDValue(FPOpOut.getNode(), 1);
3305 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3306 /// by "Src" to address "Dst" of size "Size". Alignment information is
3307 /// specified by the specific parameter attribute. The copy will be passed as
3308 /// a byval function parameter.
3309 /// Sometimes what we are copying is the end of a larger object, the part that
3310 /// does not fit in registers.
3312 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3313 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3315 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3316 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3317 false, false, MachinePointerInfo(),
3318 MachinePointerInfo());
3321 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3324 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3325 SDValue Arg, SDValue PtrOff, int SPDiff,
3326 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3327 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3328 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3330 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3335 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3337 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3338 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3339 DAG.getConstant(ArgOffset, PtrVT));
3341 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3342 MachinePointerInfo(), false, false, 0));
3343 // Calculate and remember argument location.
3344 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3349 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3350 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3351 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3352 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3353 MachineFunction &MF = DAG.getMachineFunction();
3355 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3356 // might overwrite each other in case of tail call optimization.
3357 SmallVector<SDValue, 8> MemOpChains2;
3358 // Do not flag preceding copytoreg stuff together with the following stuff.
3360 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3362 if (!MemOpChains2.empty())
3363 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3365 // Store the return address to the appropriate stack slot.
3366 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3367 isPPC64, isDarwinABI, dl);
3369 // Emit callseq_end just before tailcall node.
3370 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3371 DAG.getIntPtrConstant(0, true), InFlag, dl);
3372 InFlag = Chain.getValue(1);
3376 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3377 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3378 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3379 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3380 const PPCSubtarget &PPCSubTarget) {
3382 bool isPPC64 = PPCSubTarget.isPPC64();
3383 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3385 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3386 NodeTys.push_back(MVT::Other); // Returns a chain
3387 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3389 unsigned CallOpc = PPCISD::CALL;
3391 bool needIndirectCall = true;
3392 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3393 // If this is an absolute destination address, use the munged value.
3394 Callee = SDValue(Dest, 0);
3395 needIndirectCall = false;
3398 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3399 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3400 // Use indirect calls for ALL functions calls in JIT mode, since the
3401 // far-call stubs may be outside relocation limits for a BL instruction.
3402 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3403 unsigned OpFlags = 0;
3404 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3405 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3406 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3407 (G->getGlobal()->isDeclaration() ||
3408 G->getGlobal()->isWeakForLinker())) {
3409 // PC-relative references to external symbols should go through $stub,
3410 // unless we're building with the leopard linker or later, which
3411 // automatically synthesizes these stubs.
3412 OpFlags = PPCII::MO_DARWIN_STUB;
3415 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3416 // every direct call is) turn it into a TargetGlobalAddress /
3417 // TargetExternalSymbol node so that legalize doesn't hack it.
3418 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3419 Callee.getValueType(),
3421 needIndirectCall = false;
3425 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3426 unsigned char OpFlags = 0;
3428 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3429 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3430 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3431 // PC-relative references to external symbols should go through $stub,
3432 // unless we're building with the leopard linker or later, which
3433 // automatically synthesizes these stubs.
3434 OpFlags = PPCII::MO_DARWIN_STUB;
3437 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3439 needIndirectCall = false;
3442 if (needIndirectCall) {
3443 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3444 // to do the call, we can't use PPCISD::CALL.
3445 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3447 if (isSVR4ABI && isPPC64) {
3448 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3449 // entry point, but to the function descriptor (the function entry point
3450 // address is part of the function descriptor though).
3451 // The function descriptor is a three doubleword structure with the
3452 // following fields: function entry point, TOC base address and
3453 // environment pointer.
3454 // Thus for a call through a function pointer, the following actions need
3456 // 1. Save the TOC of the caller in the TOC save area of its stack
3457 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3458 // 2. Load the address of the function entry point from the function
3460 // 3. Load the TOC of the callee from the function descriptor into r2.
3461 // 4. Load the environment pointer from the function descriptor into
3463 // 5. Branch to the function entry point address.
3464 // 6. On return of the callee, the TOC of the caller needs to be
3465 // restored (this is done in FinishCall()).
3467 // All those operations are flagged together to ensure that no other
3468 // operations can be scheduled in between. E.g. without flagging the
3469 // operations together, a TOC access in the caller could be scheduled
3470 // between the load of the callee TOC and the branch to the callee, which
3471 // results in the TOC access going through the TOC of the callee instead
3472 // of going through the TOC of the caller, which leads to incorrect code.
3474 // Load the address of the function entry point from the function
3476 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3477 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3478 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3479 Chain = LoadFuncPtr.getValue(1);
3480 InFlag = LoadFuncPtr.getValue(2);
3482 // Load environment pointer into r11.
3483 // Offset of the environment pointer within the function descriptor.
3484 SDValue PtrOff = DAG.getIntPtrConstant(16);
3486 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3487 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3489 Chain = LoadEnvPtr.getValue(1);
3490 InFlag = LoadEnvPtr.getValue(2);
3492 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3494 Chain = EnvVal.getValue(0);
3495 InFlag = EnvVal.getValue(1);
3497 // Load TOC of the callee into r2. We are using a target-specific load
3498 // with r2 hard coded, because the result of a target-independent load
3499 // would never go directly into r2, since r2 is a reserved register (which
3500 // prevents the register allocator from allocating it), resulting in an
3501 // additional register being allocated and an unnecessary move instruction
3503 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3504 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3506 Chain = LoadTOCPtr.getValue(0);
3507 InFlag = LoadTOCPtr.getValue(1);
3509 MTCTROps[0] = Chain;
3510 MTCTROps[1] = LoadFuncPtr;
3511 MTCTROps[2] = InFlag;
3514 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3515 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3516 InFlag = Chain.getValue(1);
3519 NodeTys.push_back(MVT::Other);
3520 NodeTys.push_back(MVT::Glue);
3521 Ops.push_back(Chain);
3522 CallOpc = PPCISD::BCTRL;
3523 Callee.setNode(nullptr);
3524 // Add use of X11 (holding environment pointer)
3525 if (isSVR4ABI && isPPC64)
3526 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3527 // Add CTR register as callee so a bctr can be emitted later.
3529 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3532 // If this is a direct call, pass the chain and the callee.
3533 if (Callee.getNode()) {
3534 Ops.push_back(Chain);
3535 Ops.push_back(Callee);
3537 // If this is a tail call add stack pointer delta.
3539 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3541 // Add argument registers to the end of the list so that they are known live
3543 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3544 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3545 RegsToPass[i].second.getValueType()));
3551 bool isLocalCall(const SDValue &Callee)
3553 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3554 return !G->getGlobal()->isDeclaration() &&
3555 !G->getGlobal()->isWeakForLinker();
3560 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3561 CallingConv::ID CallConv, bool isVarArg,
3562 const SmallVectorImpl<ISD::InputArg> &Ins,
3563 SDLoc dl, SelectionDAG &DAG,
3564 SmallVectorImpl<SDValue> &InVals) const {
3566 SmallVector<CCValAssign, 16> RVLocs;
3567 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3568 getTargetMachine(), RVLocs, *DAG.getContext());
3569 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3571 // Copy all of the result registers out of their specified physreg.
3572 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3573 CCValAssign &VA = RVLocs[i];
3574 assert(VA.isRegLoc() && "Can only return in registers!");
3576 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3577 VA.getLocReg(), VA.getLocVT(), InFlag);
3578 Chain = Val.getValue(1);
3579 InFlag = Val.getValue(2);
3581 switch (VA.getLocInfo()) {
3582 default: llvm_unreachable("Unknown loc info!");
3583 case CCValAssign::Full: break;
3584 case CCValAssign::AExt:
3585 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3587 case CCValAssign::ZExt:
3588 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3589 DAG.getValueType(VA.getValVT()));
3590 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3592 case CCValAssign::SExt:
3593 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3594 DAG.getValueType(VA.getValVT()));
3595 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3599 InVals.push_back(Val);
3606 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3607 bool isTailCall, bool isVarArg,
3609 SmallVector<std::pair<unsigned, SDValue>, 8>
3611 SDValue InFlag, SDValue Chain,
3613 int SPDiff, unsigned NumBytes,
3614 const SmallVectorImpl<ISD::InputArg> &Ins,
3615 SmallVectorImpl<SDValue> &InVals) const {
3616 std::vector<EVT> NodeTys;
3617 SmallVector<SDValue, 8> Ops;
3618 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3619 isTailCall, RegsToPass, Ops, NodeTys,
3622 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3623 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3624 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3626 // When performing tail call optimization the callee pops its arguments off
3627 // the stack. Account for this here so these bytes can be pushed back on in
3628 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3629 int BytesCalleePops =
3630 (CallConv == CallingConv::Fast &&
3631 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3633 // Add a register mask operand representing the call-preserved registers.
3634 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3635 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3636 assert(Mask && "Missing call preserved mask for calling convention");
3637 Ops.push_back(DAG.getRegisterMask(Mask));
3639 if (InFlag.getNode())
3640 Ops.push_back(InFlag);
3644 assert(((Callee.getOpcode() == ISD::Register &&
3645 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3646 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3647 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3648 isa<ConstantSDNode>(Callee)) &&
3649 "Expecting an global address, external symbol, absolute value or register");
3651 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3654 // Add a NOP immediately after the branch instruction when using the 64-bit
3655 // SVR4 ABI. At link time, if caller and callee are in a different module and
3656 // thus have a different TOC, the call will be replaced with a call to a stub
3657 // function which saves the current TOC, loads the TOC of the callee and
3658 // branches to the callee. The NOP will be replaced with a load instruction
3659 // which restores the TOC of the caller from the TOC save slot of the current
3660 // stack frame. If caller and callee belong to the same module (and have the
3661 // same TOC), the NOP will remain unchanged.
3663 bool needsTOCRestore = false;
3664 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3665 if (CallOpc == PPCISD::BCTRL) {
3666 // This is a call through a function pointer.
3667 // Restore the caller TOC from the save area into R2.
3668 // See PrepareCall() for more information about calls through function
3669 // pointers in the 64-bit SVR4 ABI.
3670 // We are using a target-specific load with r2 hard coded, because the
3671 // result of a target-independent load would never go directly into r2,
3672 // since r2 is a reserved register (which prevents the register allocator
3673 // from allocating it), resulting in an additional register being
3674 // allocated and an unnecessary move instruction being generated.
3675 needsTOCRestore = true;
3676 } else if ((CallOpc == PPCISD::CALL) &&
3677 (!isLocalCall(Callee) ||
3678 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3679 // Otherwise insert NOP for non-local calls.
3680 CallOpc = PPCISD::CALL_NOP;
3684 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3685 InFlag = Chain.getValue(1);
3687 if (needsTOCRestore) {
3688 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3689 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3690 InFlag = Chain.getValue(1);
3693 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3694 DAG.getIntPtrConstant(BytesCalleePops, true),
3697 InFlag = Chain.getValue(1);
3699 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3700 Ins, dl, DAG, InVals);
3704 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3705 SmallVectorImpl<SDValue> &InVals) const {
3706 SelectionDAG &DAG = CLI.DAG;
3708 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3709 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3710 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3711 SDValue Chain = CLI.Chain;
3712 SDValue Callee = CLI.Callee;
3713 bool &isTailCall = CLI.IsTailCall;
3714 CallingConv::ID CallConv = CLI.CallConv;
3715 bool isVarArg = CLI.IsVarArg;
3718 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3721 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3722 report_fatal_error("failed to perform tail call elimination on a call "
3723 "site marked musttail");
3725 if (PPCSubTarget.isSVR4ABI()) {
3726 if (PPCSubTarget.isPPC64())
3727 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3728 isTailCall, Outs, OutVals, Ins,
3731 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3732 isTailCall, Outs, OutVals, Ins,
3736 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3737 isTailCall, Outs, OutVals, Ins,
3742 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3743 CallingConv::ID CallConv, bool isVarArg,
3745 const SmallVectorImpl<ISD::OutputArg> &Outs,
3746 const SmallVectorImpl<SDValue> &OutVals,
3747 const SmallVectorImpl<ISD::InputArg> &Ins,
3748 SDLoc dl, SelectionDAG &DAG,
3749 SmallVectorImpl<SDValue> &InVals) const {
3750 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3751 // of the 32-bit SVR4 ABI stack frame layout.
3753 assert((CallConv == CallingConv::C ||
3754 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3756 unsigned PtrByteSize = 4;
3758 MachineFunction &MF = DAG.getMachineFunction();
3760 // Mark this function as potentially containing a function that contains a
3761 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3762 // and restoring the callers stack pointer in this functions epilog. This is
3763 // done because by tail calling the called function might overwrite the value
3764 // in this function's (MF) stack pointer stack slot 0(SP).
3765 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3766 CallConv == CallingConv::Fast)
3767 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3769 // Count how many bytes are to be pushed on the stack, including the linkage
3770 // area, parameter list area and the part of the local variable space which
3771 // contains copies of aggregates which are passed by value.
3773 // Assign locations to all of the outgoing arguments.
3774 SmallVector<CCValAssign, 16> ArgLocs;
3775 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3776 getTargetMachine(), ArgLocs, *DAG.getContext());
3778 // Reserve space for the linkage area on the stack.
3779 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3782 // Handle fixed and variable vector arguments differently.
3783 // Fixed vector arguments go into registers as long as registers are
3784 // available. Variable vector arguments always go into memory.
3785 unsigned NumArgs = Outs.size();
3787 for (unsigned i = 0; i != NumArgs; ++i) {
3788 MVT ArgVT = Outs[i].VT;
3789 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3792 if (Outs[i].IsFixed) {
3793 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3796 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3802 errs() << "Call operand #" << i << " has unhandled type "
3803 << EVT(ArgVT).getEVTString() << "\n";
3805 llvm_unreachable(nullptr);
3809 // All arguments are treated the same.
3810 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3813 // Assign locations to all of the outgoing aggregate by value arguments.
3814 SmallVector<CCValAssign, 16> ByValArgLocs;
3815 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3816 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3818 // Reserve stack space for the allocations in CCInfo.
3819 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3821 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3823 // Size of the linkage area, parameter list area and the part of the local
3824 // space variable where copies of aggregates which are passed by value are
3826 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3828 // Calculate by how many bytes the stack has to be adjusted in case of tail
3829 // call optimization.
3830 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3832 // Adjust the stack pointer for the new arguments...
3833 // These operations are automatically eliminated by the prolog/epilog pass
3834 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3836 SDValue CallSeqStart = Chain;
3838 // Load the return address and frame pointer so it can be moved somewhere else
3841 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3844 // Set up a copy of the stack pointer for use loading and storing any
3845 // arguments that may not fit in the registers available for argument
3847 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3849 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3850 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3851 SmallVector<SDValue, 8> MemOpChains;
3853 bool seenFloatArg = false;
3854 // Walk the register/memloc assignments, inserting copies/loads.
3855 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3858 CCValAssign &VA = ArgLocs[i];
3859 SDValue Arg = OutVals[i];
3860 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3862 if (Flags.isByVal()) {
3863 // Argument is an aggregate which is passed by value, thus we need to
3864 // create a copy of it in the local variable space of the current stack
3865 // frame (which is the stack frame of the caller) and pass the address of
3866 // this copy to the callee.
3867 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3868 CCValAssign &ByValVA = ByValArgLocs[j++];
3869 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3871 // Memory reserved in the local variable space of the callers stack frame.
3872 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3874 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3875 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3877 // Create a copy of the argument in the local area of the current
3879 SDValue MemcpyCall =
3880 CreateCopyOfByValArgument(Arg, PtrOff,
3881 CallSeqStart.getNode()->getOperand(0),
3884 // This must go outside the CALLSEQ_START..END.
3885 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3886 CallSeqStart.getNode()->getOperand(1),
3888 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3889 NewCallSeqStart.getNode());
3890 Chain = CallSeqStart = NewCallSeqStart;
3892 // Pass the address of the aggregate copy on the stack either in a
3893 // physical register or in the parameter list area of the current stack
3894 // frame to the callee.
3898 if (VA.isRegLoc()) {
3899 if (Arg.getValueType() == MVT::i1)
3900 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3902 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3903 // Put argument in a physical register.
3904 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3906 // Put argument in the parameter list area of the current stack frame.
3907 assert(VA.isMemLoc());
3908 unsigned LocMemOffset = VA.getLocMemOffset();
3911 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3912 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3914 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3915 MachinePointerInfo(),
3918 // Calculate and remember argument location.
3919 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3925 if (!MemOpChains.empty())
3926 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3928 // Build a sequence of copy-to-reg nodes chained together with token chain
3929 // and flag operands which copy the outgoing args into the appropriate regs.
3931 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3932 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3933 RegsToPass[i].second, InFlag);
3934 InFlag = Chain.getValue(1);
3937 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3940 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3941 SDValue Ops[] = { Chain, InFlag };
3943 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3944 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3946 InFlag = Chain.getValue(1);
3950 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3951 false, TailCallArguments);
3953 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3954 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3958 // Copy an argument into memory, being careful to do this outside the
3959 // call sequence for the call to which the argument belongs.
3961 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3962 SDValue CallSeqStart,
3963 ISD::ArgFlagsTy Flags,
3966 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3967 CallSeqStart.getNode()->getOperand(0),
3969 // The MEMCPY must go outside the CALLSEQ_START..END.
3970 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3971 CallSeqStart.getNode()->getOperand(1),
3973 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3974 NewCallSeqStart.getNode());
3975 return NewCallSeqStart;
3979 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3980 CallingConv::ID CallConv, bool isVarArg,
3982 const SmallVectorImpl<ISD::OutputArg> &Outs,
3983 const SmallVectorImpl<SDValue> &OutVals,
3984 const SmallVectorImpl<ISD::InputArg> &Ins,
3985 SDLoc dl, SelectionDAG &DAG,
3986 SmallVectorImpl<SDValue> &InVals) const {
3988 unsigned NumOps = Outs.size();
3990 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3991 unsigned PtrByteSize = 8;
3993 MachineFunction &MF = DAG.getMachineFunction();
3995 // Mark this function as potentially containing a function that contains a
3996 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3997 // and restoring the callers stack pointer in this functions epilog. This is
3998 // done because by tail calling the called function might overwrite the value
3999 // in this function's (MF) stack pointer stack slot 0(SP).
4000 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4001 CallConv == CallingConv::Fast)
4002 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4004 unsigned nAltivecParamsAtEnd = 0;
4006 // Count how many bytes are to be pushed on the stack, including the linkage
4007 // area, and parameter passing area. We start with at least 48 bytes, which
4008 // is reserved space for [SP][CR][LR][3 x unused].
4009 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
4012 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
4013 Outs, OutVals, nAltivecParamsAtEnd);
4015 // Calculate by how many bytes the stack has to be adjusted in case of tail
4016 // call optimization.
4017 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4019 // To protect arguments on the stack from being clobbered in a tail call,
4020 // force all the loads to happen before doing any other lowering.
4022 Chain = DAG.getStackArgumentTokenFactor(Chain);
4024 // Adjust the stack pointer for the new arguments...
4025 // These operations are automatically eliminated by the prolog/epilog pass
4026 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4028 SDValue CallSeqStart = Chain;
4030 // Load the return address and frame pointer so it can be move somewhere else
4033 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4036 // Set up a copy of the stack pointer for use loading and storing any
4037 // arguments that may not fit in the registers available for argument
4039 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4041 // Figure out which arguments are going to go in registers, and which in
4042 // memory. Also, if this is a vararg function, floating point operations
4043 // must be stored to our stack, and loaded into integer regs as well, if
4044 // any integer regs are available for argument passing.
4045 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
4046 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4048 static const MCPhysReg GPR[] = {
4049 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4050 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4052 static const MCPhysReg *FPR = GetFPR();
4054 static const MCPhysReg VR[] = {
4055 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4056 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4058 static const MCPhysReg VSRH[] = {
4059 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4060 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4063 const unsigned NumGPRs = array_lengthof(GPR);
4064 const unsigned NumFPRs = 13;
4065 const unsigned NumVRs = array_lengthof(VR);
4067 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4068 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4070 SmallVector<SDValue, 8> MemOpChains;
4071 for (unsigned i = 0; i != NumOps; ++i) {
4072 SDValue Arg = OutVals[i];
4073 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4075 // PtrOff will be used to store the current argument to the stack if a
4076 // register cannot be found for it.
4079 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4081 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4083 // Promote integers to 64-bit values.
4084 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4085 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4086 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4087 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4090 // FIXME memcpy is used way more than necessary. Correctness first.
4091 // Note: "by value" is code for passing a structure by value, not
4093 if (Flags.isByVal()) {
4094 // Note: Size includes alignment padding, so
4095 // struct x { short a; char b; }
4096 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4097 // These are the proper values we need for right-justifying the
4098 // aggregate in a parameter register.
4099 unsigned Size = Flags.getByValSize();
4101 // An empty aggregate parameter takes up no storage and no
4106 unsigned BVAlign = Flags.getByValAlign();
4108 if (BVAlign % PtrByteSize != 0)
4110 "ByVal alignment is not a multiple of the pointer size");
4112 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4115 // All aggregates smaller than 8 bytes must be passed right-justified.
4116 if (Size==1 || Size==2 || Size==4) {
4117 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4118 if (GPR_idx != NumGPRs) {
4119 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4120 MachinePointerInfo(), VT,
4122 MemOpChains.push_back(Load.getValue(1));
4123 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4125 ArgOffset += PtrByteSize;
4130 if (GPR_idx == NumGPRs && Size < 8) {
4131 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4132 PtrOff.getValueType());
4133 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4134 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4137 ArgOffset += PtrByteSize;
4140 // Copy entire object into memory. There are cases where gcc-generated
4141 // code assumes it is there, even if it could be put entirely into
4142 // registers. (This is not what the doc says.)
4144 // FIXME: The above statement is likely due to a misunderstanding of the
4145 // documents. All arguments must be copied into the parameter area BY
4146 // THE CALLEE in the event that the callee takes the address of any
4147 // formal argument. That has not yet been implemented. However, it is
4148 // reasonable to use the stack area as a staging area for the register
4151 // Skip this for small aggregates, as we will use the same slot for a
4152 // right-justified copy, below.
4154 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4158 // When a register is available, pass a small aggregate right-justified.
4159 if (Size < 8 && GPR_idx != NumGPRs) {
4160 // The easiest way to get this right-justified in a register
4161 // is to copy the structure into the rightmost portion of a
4162 // local variable slot, then load the whole slot into the
4164 // FIXME: The memcpy seems to produce pretty awful code for
4165 // small aggregates, particularly for packed ones.
4166 // FIXME: It would be preferable to use the slot in the
4167 // parameter save area instead of a new local variable.
4168 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4169 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4170 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4174 // Load the slot into the register.
4175 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4176 MachinePointerInfo(),
4177 false, false, false, 0);
4178 MemOpChains.push_back(Load.getValue(1));
4179 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4181 // Done with this argument.
4182 ArgOffset += PtrByteSize;
4186 // For aggregates larger than PtrByteSize, copy the pieces of the
4187 // object that fit into registers from the parameter save area.
4188 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4189 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4190 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4191 if (GPR_idx != NumGPRs) {
4192 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4193 MachinePointerInfo(),
4194 false, false, false, 0);
4195 MemOpChains.push_back(Load.getValue(1));
4196 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4197 ArgOffset += PtrByteSize;
4199 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4206 switch (Arg.getSimpleValueType().SimpleTy) {
4207 default: llvm_unreachable("Unexpected ValueType for argument!");
4211 if (GPR_idx != NumGPRs) {
4212 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4214 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4215 true, isTailCall, false, MemOpChains,
4216 TailCallArguments, dl);
4218 ArgOffset += PtrByteSize;
4222 if (FPR_idx != NumFPRs) {
4223 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4226 // A single float or an aggregate containing only a single float
4227 // must be passed right-justified in the stack doubleword, and
4228 // in the GPR, if one is available.
4230 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4231 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4232 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4236 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4237 MachinePointerInfo(), false, false, 0);
4238 MemOpChains.push_back(Store);
4240 // Float varargs are always shadowed in available integer registers
4241 if (GPR_idx != NumGPRs) {
4242 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4243 MachinePointerInfo(), false, false,
4245 MemOpChains.push_back(Load.getValue(1));
4246 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4248 } else if (GPR_idx != NumGPRs)
4249 // If we have any FPRs remaining, we may also have GPRs remaining.
4252 // Single-precision floating-point values are mapped to the
4253 // second (rightmost) word of the stack doubleword.
4254 if (Arg.getValueType() == MVT::f32) {
4255 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4256 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4259 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4260 true, isTailCall, false, MemOpChains,
4261 TailCallArguments, dl);
4272 // These go aligned on the stack, or in the corresponding R registers
4273 // when within range. The Darwin PPC ABI doc claims they also go in
4274 // V registers; in fact gcc does this only for arguments that are
4275 // prototyped, not for those that match the ... We do it for all
4276 // arguments, seems to work.
4277 while (ArgOffset % 16 !=0) {
4278 ArgOffset += PtrByteSize;
4279 if (GPR_idx != NumGPRs)
4282 // We could elide this store in the case where the object fits
4283 // entirely in R registers. Maybe later.
4284 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4285 DAG.getConstant(ArgOffset, PtrVT));
4286 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4287 MachinePointerInfo(), false, false, 0);
4288 MemOpChains.push_back(Store);
4289 if (VR_idx != NumVRs) {
4290 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4291 MachinePointerInfo(),
4292 false, false, false, 0);
4293 MemOpChains.push_back(Load.getValue(1));
4295 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4296 Arg.getSimpleValueType() == MVT::v2i64) ?
4297 VSRH[VR_idx] : VR[VR_idx];
4300 RegsToPass.push_back(std::make_pair(VReg, Load));
4303 for (unsigned i=0; i<16; i+=PtrByteSize) {
4304 if (GPR_idx == NumGPRs)
4306 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4307 DAG.getConstant(i, PtrVT));
4308 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4309 false, false, false, 0);
4310 MemOpChains.push_back(Load.getValue(1));
4311 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4316 // Non-varargs Altivec params generally go in registers, but have
4317 // stack space allocated at the end.
4318 if (VR_idx != NumVRs) {
4319 // Doesn't have GPR space allocated.
4320 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4321 Arg.getSimpleValueType() == MVT::v2i64) ?
4322 VSRH[VR_idx] : VR[VR_idx];
4325 RegsToPass.push_back(std::make_pair(VReg, Arg));
4327 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4328 true, isTailCall, true, MemOpChains,
4329 TailCallArguments, dl);
4336 if (!MemOpChains.empty())
4337 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4339 // Check if this is an indirect call (MTCTR/BCTRL).
4340 // See PrepareCall() for more information about calls through function
4341 // pointers in the 64-bit SVR4 ABI.
4343 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4344 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4345 !isBLACompatibleAddress(Callee, DAG)) {
4346 // Load r2 into a virtual register and store it to the TOC save area.
4347 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4348 // TOC save area offset.
4349 SDValue PtrOff = DAG.getIntPtrConstant(40);
4350 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4351 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4353 // R12 must contain the address of an indirect callee. This does not
4354 // mean the MTCTR instruction must use R12; it's easier to model this
4355 // as an extra parameter, so do that.
4356 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4359 // Build a sequence of copy-to-reg nodes chained together with token chain
4360 // and flag operands which copy the outgoing args into the appropriate regs.
4362 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4363 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4364 RegsToPass[i].second, InFlag);
4365 InFlag = Chain.getValue(1);
4369 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4370 FPOp, true, TailCallArguments);
4372 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4373 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4378 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4379 CallingConv::ID CallConv, bool isVarArg,
4381 const SmallVectorImpl<ISD::OutputArg> &Outs,
4382 const SmallVectorImpl<SDValue> &OutVals,
4383 const SmallVectorImpl<ISD::InputArg> &Ins,
4384 SDLoc dl, SelectionDAG &DAG,
4385 SmallVectorImpl<SDValue> &InVals) const {
4387 unsigned NumOps = Outs.size();
4389 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4390 bool isPPC64 = PtrVT == MVT::i64;
4391 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4393 MachineFunction &MF = DAG.getMachineFunction();
4395 // Mark this function as potentially containing a function that contains a
4396 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4397 // and restoring the callers stack pointer in this functions epilog. This is
4398 // done because by tail calling the called function might overwrite the value
4399 // in this function's (MF) stack pointer stack slot 0(SP).
4400 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4401 CallConv == CallingConv::Fast)
4402 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4404 unsigned nAltivecParamsAtEnd = 0;
4406 // Count how many bytes are to be pushed on the stack, including the linkage
4407 // area, and parameter passing area. We start with 24/48 bytes, which is
4408 // prereserved space for [SP][CR][LR][3 x unused].
4410 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4412 nAltivecParamsAtEnd);
4414 // Calculate by how many bytes the stack has to be adjusted in case of tail
4415 // call optimization.
4416 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4418 // To protect arguments on the stack from being clobbered in a tail call,
4419 // force all the loads to happen before doing any other lowering.
4421 Chain = DAG.getStackArgumentTokenFactor(Chain);
4423 // Adjust the stack pointer for the new arguments...
4424 // These operations are automatically eliminated by the prolog/epilog pass
4425 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4427 SDValue CallSeqStart = Chain;
4429 // Load the return address and frame pointer so it can be move somewhere else
4432 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4435 // Set up a copy of the stack pointer for use loading and storing any
4436 // arguments that may not fit in the registers available for argument
4440 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4442 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4444 // Figure out which arguments are going to go in registers, and which in
4445 // memory. Also, if this is a vararg function, floating point operations
4446 // must be stored to our stack, and loaded into integer regs as well, if
4447 // any integer regs are available for argument passing.
4448 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4449 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4451 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4452 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4453 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4455 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4456 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4457 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4459 static const MCPhysReg *FPR = GetFPR();
4461 static const MCPhysReg VR[] = {
4462 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4463 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4465 const unsigned NumGPRs = array_lengthof(GPR_32);
4466 const unsigned NumFPRs = 13;
4467 const unsigned NumVRs = array_lengthof(VR);
4469 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4471 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4472 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4474 SmallVector<SDValue, 8> MemOpChains;
4475 for (unsigned i = 0; i != NumOps; ++i) {
4476 SDValue Arg = OutVals[i];
4477 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4479 // PtrOff will be used to store the current argument to the stack if a
4480 // register cannot be found for it.
4483 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4485 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4487 // On PPC64, promote integers to 64-bit values.
4488 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4489 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4490 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4491 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4494 // FIXME memcpy is used way more than necessary. Correctness first.
4495 // Note: "by value" is code for passing a structure by value, not
4497 if (Flags.isByVal()) {
4498 unsigned Size = Flags.getByValSize();
4499 // Very small objects are passed right-justified. Everything else is
4500 // passed left-justified.
4501 if (Size==1 || Size==2) {
4502 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4503 if (GPR_idx != NumGPRs) {
4504 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4505 MachinePointerInfo(), VT,
4507 MemOpChains.push_back(Load.getValue(1));
4508 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4510 ArgOffset += PtrByteSize;
4512 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4513 PtrOff.getValueType());
4514 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4515 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4518 ArgOffset += PtrByteSize;
4522 // Copy entire object into memory. There are cases where gcc-generated
4523 // code assumes it is there, even if it could be put entirely into
4524 // registers. (This is not what the doc says.)
4525 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4529 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4530 // copy the pieces of the object that fit into registers from the
4531 // parameter save area.
4532 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4533 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4534 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4535 if (GPR_idx != NumGPRs) {
4536 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4537 MachinePointerInfo(),
4538 false, false, false, 0);
4539 MemOpChains.push_back(Load.getValue(1));
4540 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4541 ArgOffset += PtrByteSize;
4543 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4550 switch (Arg.getSimpleValueType().SimpleTy) {
4551 default: llvm_unreachable("Unexpected ValueType for argument!");
4555 if (GPR_idx != NumGPRs) {
4556 if (Arg.getValueType() == MVT::i1)
4557 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4559 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4561 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4562 isPPC64, isTailCall, false, MemOpChains,
4563 TailCallArguments, dl);
4565 ArgOffset += PtrByteSize;
4569 if (FPR_idx != NumFPRs) {
4570 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4573 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4574 MachinePointerInfo(), false, false, 0);
4575 MemOpChains.push_back(Store);
4577 // Float varargs are always shadowed in available integer registers
4578 if (GPR_idx != NumGPRs) {
4579 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4580 MachinePointerInfo(), false, false,
4582 MemOpChains.push_back(Load.getValue(1));
4583 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4585 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4586 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4587 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4588 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4589 MachinePointerInfo(),
4590 false, false, false, 0);
4591 MemOpChains.push_back(Load.getValue(1));
4592 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4595 // If we have any FPRs remaining, we may also have GPRs remaining.
4596 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4598 if (GPR_idx != NumGPRs)
4600 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4601 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4605 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4606 isPPC64, isTailCall, false, MemOpChains,
4607 TailCallArguments, dl);
4611 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4618 // These go aligned on the stack, or in the corresponding R registers
4619 // when within range. The Darwin PPC ABI doc claims they also go in
4620 // V registers; in fact gcc does this only for arguments that are
4621 // prototyped, not for those that match the ... We do it for all
4622 // arguments, seems to work.
4623 while (ArgOffset % 16 !=0) {
4624 ArgOffset += PtrByteSize;
4625 if (GPR_idx != NumGPRs)
4628 // We could elide this store in the case where the object fits
4629 // entirely in R registers. Maybe later.
4630 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4631 DAG.getConstant(ArgOffset, PtrVT));
4632 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4633 MachinePointerInfo(), false, false, 0);
4634 MemOpChains.push_back(Store);
4635 if (VR_idx != NumVRs) {
4636 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4637 MachinePointerInfo(),
4638 false, false, false, 0);
4639 MemOpChains.push_back(Load.getValue(1));
4640 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4643 for (unsigned i=0; i<16; i+=PtrByteSize) {
4644 if (GPR_idx == NumGPRs)
4646 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4647 DAG.getConstant(i, PtrVT));
4648 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4649 false, false, false, 0);
4650 MemOpChains.push_back(Load.getValue(1));
4651 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4656 // Non-varargs Altivec params generally go in registers, but have
4657 // stack space allocated at the end.
4658 if (VR_idx != NumVRs) {
4659 // Doesn't have GPR space allocated.
4660 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4661 } else if (nAltivecParamsAtEnd==0) {
4662 // We are emitting Altivec params in order.
4663 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4664 isPPC64, isTailCall, true, MemOpChains,
4665 TailCallArguments, dl);
4671 // If all Altivec parameters fit in registers, as they usually do,
4672 // they get stack space following the non-Altivec parameters. We
4673 // don't track this here because nobody below needs it.
4674 // If there are more Altivec parameters than fit in registers emit
4676 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4678 // Offset is aligned; skip 1st 12 params which go in V registers.
4679 ArgOffset = ((ArgOffset+15)/16)*16;
4681 for (unsigned i = 0; i != NumOps; ++i) {
4682 SDValue Arg = OutVals[i];
4683 EVT ArgType = Outs[i].VT;
4684 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4685 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4688 // We are emitting Altivec params in order.
4689 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4690 isPPC64, isTailCall, true, MemOpChains,
4691 TailCallArguments, dl);
4698 if (!MemOpChains.empty())
4699 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4701 // On Darwin, R12 must contain the address of an indirect callee. This does
4702 // not mean the MTCTR instruction must use R12; it's easier to model this as
4703 // an extra parameter, so do that.
4705 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4706 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4707 !isBLACompatibleAddress(Callee, DAG))
4708 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4709 PPC::R12), Callee));
4711 // Build a sequence of copy-to-reg nodes chained together with token chain
4712 // and flag operands which copy the outgoing args into the appropriate regs.
4714 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4715 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4716 RegsToPass[i].second, InFlag);
4717 InFlag = Chain.getValue(1);
4721 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4722 FPOp, true, TailCallArguments);
4724 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4725 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4730 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4731 MachineFunction &MF, bool isVarArg,
4732 const SmallVectorImpl<ISD::OutputArg> &Outs,
4733 LLVMContext &Context) const {
4734 SmallVector<CCValAssign, 16> RVLocs;
4735 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4737 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4741 PPCTargetLowering::LowerReturn(SDValue Chain,
4742 CallingConv::ID CallConv, bool isVarArg,
4743 const SmallVectorImpl<ISD::OutputArg> &Outs,
4744 const SmallVectorImpl<SDValue> &OutVals,
4745 SDLoc dl, SelectionDAG &DAG) const {
4747 SmallVector<CCValAssign, 16> RVLocs;
4748 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4749 getTargetMachine(), RVLocs, *DAG.getContext());
4750 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4753 SmallVector<SDValue, 4> RetOps(1, Chain);
4755 // Copy the result values into the output registers.
4756 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4757 CCValAssign &VA = RVLocs[i];
4758 assert(VA.isRegLoc() && "Can only return in registers!");
4760 SDValue Arg = OutVals[i];
4762 switch (VA.getLocInfo()) {
4763 default: llvm_unreachable("Unknown loc info!");
4764 case CCValAssign::Full: break;
4765 case CCValAssign::AExt:
4766 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4768 case CCValAssign::ZExt:
4769 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4771 case CCValAssign::SExt:
4772 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4776 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4777 Flag = Chain.getValue(1);
4778 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4781 RetOps[0] = Chain; // Update chain.
4783 // Add the flag if we have it.
4785 RetOps.push_back(Flag);
4787 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4790 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4791 const PPCSubtarget &Subtarget) const {
4792 // When we pop the dynamic allocation we need to restore the SP link.
4795 // Get the corect type for pointers.
4796 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4798 // Construct the stack pointer operand.
4799 bool isPPC64 = Subtarget.isPPC64();
4800 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4801 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4803 // Get the operands for the STACKRESTORE.
4804 SDValue Chain = Op.getOperand(0);
4805 SDValue SaveSP = Op.getOperand(1);
4807 // Load the old link SP.
4808 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4809 MachinePointerInfo(),
4810 false, false, false, 0);
4812 // Restore the stack pointer.
4813 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4815 // Store the old link SP.
4816 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4823 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4824 MachineFunction &MF = DAG.getMachineFunction();
4825 bool isPPC64 = PPCSubTarget.isPPC64();
4826 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4827 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4829 // Get current frame pointer save index. The users of this index will be
4830 // primarily DYNALLOC instructions.
4831 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4832 int RASI = FI->getReturnAddrSaveIndex();
4834 // If the frame pointer save index hasn't been defined yet.
4836 // Find out what the fix offset of the frame pointer save area.
4837 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4838 // Allocate the frame index for frame pointer save area.
4839 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4841 FI->setReturnAddrSaveIndex(RASI);
4843 return DAG.getFrameIndex(RASI, PtrVT);
4847 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4848 MachineFunction &MF = DAG.getMachineFunction();
4849 bool isPPC64 = PPCSubTarget.isPPC64();
4850 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4851 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4853 // Get current frame pointer save index. The users of this index will be
4854 // primarily DYNALLOC instructions.
4855 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4856 int FPSI = FI->getFramePointerSaveIndex();
4858 // If the frame pointer save index hasn't been defined yet.
4860 // Find out what the fix offset of the frame pointer save area.
4861 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4864 // Allocate the frame index for frame pointer save area.
4865 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4867 FI->setFramePointerSaveIndex(FPSI);
4869 return DAG.getFrameIndex(FPSI, PtrVT);
4872 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4874 const PPCSubtarget &Subtarget) const {
4876 SDValue Chain = Op.getOperand(0);
4877 SDValue Size = Op.getOperand(1);
4880 // Get the corect type for pointers.
4881 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4883 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4884 DAG.getConstant(0, PtrVT), Size);
4885 // Construct a node for the frame pointer save index.
4886 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4887 // Build a DYNALLOC node.
4888 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4889 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4890 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4893 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4894 SelectionDAG &DAG) const {
4896 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4897 DAG.getVTList(MVT::i32, MVT::Other),
4898 Op.getOperand(0), Op.getOperand(1));
4901 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4902 SelectionDAG &DAG) const {
4904 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4905 Op.getOperand(0), Op.getOperand(1));
4908 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4909 assert(Op.getValueType() == MVT::i1 &&
4910 "Custom lowering only for i1 loads");
4912 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4915 LoadSDNode *LD = cast<LoadSDNode>(Op);
4917 SDValue Chain = LD->getChain();
4918 SDValue BasePtr = LD->getBasePtr();
4919 MachineMemOperand *MMO = LD->getMemOperand();
4921 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4922 BasePtr, MVT::i8, MMO);
4923 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4925 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4926 return DAG.getMergeValues(Ops, dl);
4929 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4930 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4931 "Custom lowering only for i1 stores");
4933 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4936 StoreSDNode *ST = cast<StoreSDNode>(Op);
4938 SDValue Chain = ST->getChain();
4939 SDValue BasePtr = ST->getBasePtr();
4940 SDValue Value = ST->getValue();
4941 MachineMemOperand *MMO = ST->getMemOperand();
4943 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4944 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4947 // FIXME: Remove this once the ANDI glue bug is fixed:
4948 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4949 assert(Op.getValueType() == MVT::i1 &&
4950 "Custom lowering only for i1 results");
4953 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4957 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4959 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4960 // Not FP? Not a fsel.
4961 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4962 !Op.getOperand(2).getValueType().isFloatingPoint())
4965 // We might be able to do better than this under some circumstances, but in
4966 // general, fsel-based lowering of select is a finite-math-only optimization.
4967 // For more information, see section F.3 of the 2.06 ISA specification.
4968 if (!DAG.getTarget().Options.NoInfsFPMath ||
4969 !DAG.getTarget().Options.NoNaNsFPMath)
4972 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4974 EVT ResVT = Op.getValueType();
4975 EVT CmpVT = Op.getOperand(0).getValueType();
4976 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4977 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4980 // If the RHS of the comparison is a 0.0, we don't need to do the
4981 // subtraction at all.
4983 if (isFloatingPointZero(RHS))
4985 default: break; // SETUO etc aren't handled by fsel.
4989 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4990 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4991 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4992 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4993 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4994 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4995 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4998 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5001 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5002 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5003 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5006 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5009 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5010 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5011 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5012 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5017 default: break; // SETUO etc aren't handled by fsel.
5021 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5022 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5023 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5024 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5025 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5026 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5027 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5028 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5031 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5032 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5033 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5034 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5037 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5038 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5039 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5040 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5043 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5044 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5045 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5046 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5049 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5050 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5051 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5052 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5057 // FIXME: Split this code up when LegalizeDAGTypes lands.
5058 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5060 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5061 SDValue Src = Op.getOperand(0);
5062 if (Src.getValueType() == MVT::f32)
5063 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5066 switch (Op.getSimpleValueType().SimpleTy) {
5067 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5069 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5070 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5075 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
5076 "i64 FP_TO_UINT is supported only with FPCVT");
5077 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5083 // Convert the FP value to an int value through memory.
5084 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
5085 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
5086 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5087 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5088 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5090 // Emit a store to the stack slot.
5093 MachineFunction &MF = DAG.getMachineFunction();
5094 MachineMemOperand *MMO =
5095 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5096 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5097 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5098 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5100 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5101 MPI, false, false, 0);
5103 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5105 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5106 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5107 DAG.getConstant(4, FIPtr.getValueType()));
5108 MPI = MachinePointerInfo();
5111 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5112 false, false, false, 0);
5115 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5116 SelectionDAG &DAG) const {
5118 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5119 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5122 if (Op.getOperand(0).getValueType() == MVT::i1)
5123 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5124 DAG.getConstantFP(1.0, Op.getValueType()),
5125 DAG.getConstantFP(0.0, Op.getValueType()));
5127 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
5128 "UINT_TO_FP is supported only with FPCVT");
5130 // If we have FCFIDS, then use it when converting to single-precision.
5131 // Otherwise, convert to double-precision and then round.
5132 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5133 (Op.getOpcode() == ISD::UINT_TO_FP ?
5134 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5135 (Op.getOpcode() == ISD::UINT_TO_FP ?
5136 PPCISD::FCFIDU : PPCISD::FCFID);
5137 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5138 MVT::f32 : MVT::f64;
5140 if (Op.getOperand(0).getValueType() == MVT::i64) {
5141 SDValue SINT = Op.getOperand(0);
5142 // When converting to single-precision, we actually need to convert
5143 // to double-precision first and then round to single-precision.
5144 // To avoid double-rounding effects during that operation, we have
5145 // to prepare the input operand. Bits that might be truncated when
5146 // converting to double-precision are replaced by a bit that won't
5147 // be lost at this stage, but is below the single-precision rounding
5150 // However, if -enable-unsafe-fp-math is in effect, accept double
5151 // rounding to avoid the extra overhead.
5152 if (Op.getValueType() == MVT::f32 &&
5153 !PPCSubTarget.hasFPCVT() &&
5154 !DAG.getTarget().Options.UnsafeFPMath) {
5156 // Twiddle input to make sure the low 11 bits are zero. (If this
5157 // is the case, we are guaranteed the value will fit into the 53 bit
5158 // mantissa of an IEEE double-precision value without rounding.)
5159 // If any of those low 11 bits were not zero originally, make sure
5160 // bit 12 (value 2048) is set instead, so that the final rounding
5161 // to single-precision gets the correct result.
5162 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5163 SINT, DAG.getConstant(2047, MVT::i64));
5164 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5165 Round, DAG.getConstant(2047, MVT::i64));
5166 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5167 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5168 Round, DAG.getConstant(-2048, MVT::i64));
5170 // However, we cannot use that value unconditionally: if the magnitude
5171 // of the input value is small, the bit-twiddling we did above might
5172 // end up visibly changing the output. Fortunately, in that case, we
5173 // don't need to twiddle bits since the original input will convert
5174 // exactly to double-precision floating-point already. Therefore,
5175 // construct a conditional to use the original value if the top 11
5176 // bits are all sign-bit copies, and use the rounded value computed
5178 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5179 SINT, DAG.getConstant(53, MVT::i32));
5180 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5181 Cond, DAG.getConstant(1, MVT::i64));
5182 Cond = DAG.getSetCC(dl, MVT::i32,
5183 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5185 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5188 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5189 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5191 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
5192 FP = DAG.getNode(ISD::FP_ROUND, dl,
5193 MVT::f32, FP, DAG.getIntPtrConstant(0));
5197 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5198 "Unhandled INT_TO_FP type in custom expander!");
5199 // Since we only generate this in 64-bit mode, we can take advantage of
5200 // 64-bit registers. In particular, sign extend the input value into the
5201 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5202 // then lfd it and fcfid it.
5203 MachineFunction &MF = DAG.getMachineFunction();
5204 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5205 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5208 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
5209 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5210 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5212 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5213 MachinePointerInfo::getFixedStack(FrameIdx),
5216 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5217 "Expected an i32 store");
5218 MachineMemOperand *MMO =
5219 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5220 MachineMemOperand::MOLoad, 4, 4);
5221 SDValue Ops[] = { Store, FIdx };
5222 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5223 PPCISD::LFIWZX : PPCISD::LFIWAX,
5224 dl, DAG.getVTList(MVT::f64, MVT::Other),
5225 Ops, MVT::i32, MMO);
5227 assert(PPCSubTarget.isPPC64() &&
5228 "i32->FP without LFIWAX supported only on PPC64");
5230 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5231 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5233 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5236 // STD the extended value into the stack slot.
5237 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5238 MachinePointerInfo::getFixedStack(FrameIdx),
5241 // Load the value as a double.
5242 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5243 MachinePointerInfo::getFixedStack(FrameIdx),
5244 false, false, false, 0);
5247 // FCFID it and return it.
5248 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5249 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
5250 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5254 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5255 SelectionDAG &DAG) const {
5258 The rounding mode is in bits 30:31 of FPSR, and has the following
5265 FLT_ROUNDS, on the other hand, expects the following:
5272 To perform the conversion, we do:
5273 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5276 MachineFunction &MF = DAG.getMachineFunction();
5277 EVT VT = Op.getValueType();
5278 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5280 // Save FP Control Word to register
5282 MVT::f64, // return register
5283 MVT::Glue // unused in this context
5285 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5287 // Save FP register to stack slot
5288 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5289 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5290 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5291 StackSlot, MachinePointerInfo(), false, false,0);
5293 // Load FP Control Word from low 32 bits of stack slot.
5294 SDValue Four = DAG.getConstant(4, PtrVT);
5295 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5296 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5297 false, false, false, 0);
5299 // Transform as necessary
5301 DAG.getNode(ISD::AND, dl, MVT::i32,
5302 CWD, DAG.getConstant(3, MVT::i32));
5304 DAG.getNode(ISD::SRL, dl, MVT::i32,
5305 DAG.getNode(ISD::AND, dl, MVT::i32,
5306 DAG.getNode(ISD::XOR, dl, MVT::i32,
5307 CWD, DAG.getConstant(3, MVT::i32)),
5308 DAG.getConstant(3, MVT::i32)),
5309 DAG.getConstant(1, MVT::i32));
5312 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5314 return DAG.getNode((VT.getSizeInBits() < 16 ?
5315 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5318 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5319 EVT VT = Op.getValueType();
5320 unsigned BitWidth = VT.getSizeInBits();
5322 assert(Op.getNumOperands() == 3 &&
5323 VT == Op.getOperand(1).getValueType() &&
5326 // Expand into a bunch of logical ops. Note that these ops
5327 // depend on the PPC behavior for oversized shift amounts.
5328 SDValue Lo = Op.getOperand(0);
5329 SDValue Hi = Op.getOperand(1);
5330 SDValue Amt = Op.getOperand(2);
5331 EVT AmtVT = Amt.getValueType();
5333 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5334 DAG.getConstant(BitWidth, AmtVT), Amt);
5335 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5336 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5337 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5338 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5339 DAG.getConstant(-BitWidth, AmtVT));
5340 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5341 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5342 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5343 SDValue OutOps[] = { OutLo, OutHi };
5344 return DAG.getMergeValues(OutOps, dl);
5347 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5348 EVT VT = Op.getValueType();
5350 unsigned BitWidth = VT.getSizeInBits();
5351 assert(Op.getNumOperands() == 3 &&
5352 VT == Op.getOperand(1).getValueType() &&
5355 // Expand into a bunch of logical ops. Note that these ops
5356 // depend on the PPC behavior for oversized shift amounts.
5357 SDValue Lo = Op.getOperand(0);
5358 SDValue Hi = Op.getOperand(1);
5359 SDValue Amt = Op.getOperand(2);
5360 EVT AmtVT = Amt.getValueType();
5362 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5363 DAG.getConstant(BitWidth, AmtVT), Amt);
5364 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5365 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5366 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5367 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5368 DAG.getConstant(-BitWidth, AmtVT));
5369 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5370 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5371 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5372 SDValue OutOps[] = { OutLo, OutHi };
5373 return DAG.getMergeValues(OutOps, dl);
5376 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5378 EVT VT = Op.getValueType();
5379 unsigned BitWidth = VT.getSizeInBits();
5380 assert(Op.getNumOperands() == 3 &&
5381 VT == Op.getOperand(1).getValueType() &&
5384 // Expand into a bunch of logical ops, followed by a select_cc.
5385 SDValue Lo = Op.getOperand(0);
5386 SDValue Hi = Op.getOperand(1);
5387 SDValue Amt = Op.getOperand(2);
5388 EVT AmtVT = Amt.getValueType();
5390 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5391 DAG.getConstant(BitWidth, AmtVT), Amt);
5392 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5393 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5394 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5395 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5396 DAG.getConstant(-BitWidth, AmtVT));
5397 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5398 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5399 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5400 Tmp4, Tmp6, ISD::SETLE);
5401 SDValue OutOps[] = { OutLo, OutHi };
5402 return DAG.getMergeValues(OutOps, dl);
5405 //===----------------------------------------------------------------------===//
5406 // Vector related lowering.
5409 /// BuildSplatI - Build a canonical splati of Val with an element size of
5410 /// SplatSize. Cast the result to VT.
5411 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5412 SelectionDAG &DAG, SDLoc dl) {
5413 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5415 static const EVT VTys[] = { // canonical VT to use for each size.
5416 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5419 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5421 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5425 EVT CanonicalVT = VTys[SplatSize-1];
5427 // Build a canonical splat for this value.
5428 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5429 SmallVector<SDValue, 8> Ops;
5430 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5431 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5432 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5435 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5436 /// specified intrinsic ID.
5437 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5438 SelectionDAG &DAG, SDLoc dl,
5439 EVT DestVT = MVT::Other) {
5440 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5441 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5442 DAG.getConstant(IID, MVT::i32), Op);
5445 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5446 /// specified intrinsic ID.
5447 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5448 SelectionDAG &DAG, SDLoc dl,
5449 EVT DestVT = MVT::Other) {
5450 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5451 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5452 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5455 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5456 /// specified intrinsic ID.
5457 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5458 SDValue Op2, SelectionDAG &DAG,
5459 SDLoc dl, EVT DestVT = MVT::Other) {
5460 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5461 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5462 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5466 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5467 /// amount. The result has the specified value type.
5468 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5469 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5470 // Force LHS/RHS to be the right type.
5471 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5472 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5475 for (unsigned i = 0; i != 16; ++i)
5477 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5478 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5481 // If this is a case we can't handle, return null and let the default
5482 // expansion code take care of it. If we CAN select this case, and if it
5483 // selects to a single instruction, return Op. Otherwise, if we can codegen
5484 // this case more efficiently than a constant pool load, lower it to the
5485 // sequence of ops that should be used.
5486 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5487 SelectionDAG &DAG) const {
5489 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5490 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5492 // Check if this is a splat of a constant value.
5493 APInt APSplatBits, APSplatUndef;
5494 unsigned SplatBitSize;
5496 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5497 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5500 unsigned SplatBits = APSplatBits.getZExtValue();
5501 unsigned SplatUndef = APSplatUndef.getZExtValue();
5502 unsigned SplatSize = SplatBitSize / 8;
5504 // First, handle single instruction cases.
5507 if (SplatBits == 0) {
5508 // Canonicalize all zero vectors to be v4i32.
5509 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5510 SDValue Z = DAG.getConstant(0, MVT::i32);
5511 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5512 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5517 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5518 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5520 if (SextVal >= -16 && SextVal <= 15)
5521 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5524 // Two instruction sequences.
5526 // If this value is in the range [-32,30] and is even, use:
5527 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5528 // If this value is in the range [17,31] and is odd, use:
5529 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5530 // If this value is in the range [-31,-17] and is odd, use:
5531 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5532 // Note the last two are three-instruction sequences.
5533 if (SextVal >= -32 && SextVal <= 31) {
5534 // To avoid having these optimizations undone by constant folding,
5535 // we convert to a pseudo that will be expanded later into one of
5537 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5538 EVT VT = Op.getValueType();
5539 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5540 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5541 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5544 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5545 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5547 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5548 // Make -1 and vspltisw -1:
5549 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5551 // Make the VSLW intrinsic, computing 0x8000_0000.
5552 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5555 // xor by OnesV to invert it.
5556 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5557 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5560 // Check to see if this is a wide variety of vsplti*, binop self cases.
5561 static const signed char SplatCsts[] = {
5562 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5563 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5566 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5567 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5568 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5569 int i = SplatCsts[idx];
5571 // Figure out what shift amount will be used by altivec if shifted by i in
5573 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5575 // vsplti + shl self.
5576 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5577 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5578 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5579 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5580 Intrinsic::ppc_altivec_vslw
5582 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5583 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5586 // vsplti + srl self.
5587 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5588 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5589 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5590 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5591 Intrinsic::ppc_altivec_vsrw
5593 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5594 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5597 // vsplti + sra self.
5598 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5599 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5600 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5601 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5602 Intrinsic::ppc_altivec_vsraw
5604 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5605 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5608 // vsplti + rol self.
5609 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5610 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5611 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5612 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5613 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5614 Intrinsic::ppc_altivec_vrlw
5616 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5617 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5620 // t = vsplti c, result = vsldoi t, t, 1
5621 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5622 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5623 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5625 // t = vsplti c, result = vsldoi t, t, 2
5626 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5627 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5628 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5630 // t = vsplti c, result = vsldoi t, t, 3
5631 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5632 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5633 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5640 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5641 /// the specified operations to build the shuffle.
5642 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5643 SDValue RHS, SelectionDAG &DAG,
5645 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5646 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5647 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5650 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5662 if (OpNum == OP_COPY) {
5663 if (LHSID == (1*9+2)*9+3) return LHS;
5664 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5668 SDValue OpLHS, OpRHS;
5669 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5670 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5674 default: llvm_unreachable("Unknown i32 permute!");
5676 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5677 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5678 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5679 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5682 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5683 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5684 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5685 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5688 for (unsigned i = 0; i != 16; ++i)
5689 ShufIdxs[i] = (i&3)+0;
5692 for (unsigned i = 0; i != 16; ++i)
5693 ShufIdxs[i] = (i&3)+4;
5696 for (unsigned i = 0; i != 16; ++i)
5697 ShufIdxs[i] = (i&3)+8;
5700 for (unsigned i = 0; i != 16; ++i)
5701 ShufIdxs[i] = (i&3)+12;
5704 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5706 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5708 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5710 EVT VT = OpLHS.getValueType();
5711 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5712 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5713 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5714 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5717 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5718 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5719 /// return the code it can be lowered into. Worst case, it can always be
5720 /// lowered into a vperm.
5721 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5722 SelectionDAG &DAG) const {
5724 SDValue V1 = Op.getOperand(0);
5725 SDValue V2 = Op.getOperand(1);
5726 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5727 EVT VT = Op.getValueType();
5729 // Cases that are handled by instructions that take permute immediates
5730 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5731 // selected by the instruction selector.
5732 if (V2.getOpcode() == ISD::UNDEF) {
5733 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5734 PPC::isSplatShuffleMask(SVOp, 2) ||
5735 PPC::isSplatShuffleMask(SVOp, 4) ||
5736 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5737 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5738 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5739 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5740 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5741 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5742 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5743 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5744 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5749 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5750 // and produce a fixed permutation. If any of these match, do not lower to
5752 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5753 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5754 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5755 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5756 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5757 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5758 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5759 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5760 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5763 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5764 // perfect shuffle table to emit an optimal matching sequence.
5765 ArrayRef<int> PermMask = SVOp->getMask();
5767 unsigned PFIndexes[4];
5768 bool isFourElementShuffle = true;
5769 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5770 unsigned EltNo = 8; // Start out undef.
5771 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5772 if (PermMask[i*4+j] < 0)
5773 continue; // Undef, ignore it.
5775 unsigned ByteSource = PermMask[i*4+j];
5776 if ((ByteSource & 3) != j) {
5777 isFourElementShuffle = false;
5782 EltNo = ByteSource/4;
5783 } else if (EltNo != ByteSource/4) {
5784 isFourElementShuffle = false;
5788 PFIndexes[i] = EltNo;
5791 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5792 // perfect shuffle vector to determine if it is cost effective to do this as
5793 // discrete instructions, or whether we should use a vperm.
5794 if (isFourElementShuffle) {
5795 // Compute the index in the perfect shuffle table.
5796 unsigned PFTableIndex =
5797 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5799 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5800 unsigned Cost = (PFEntry >> 30);
5802 // Determining when to avoid vperm is tricky. Many things affect the cost
5803 // of vperm, particularly how many times the perm mask needs to be computed.
5804 // For example, if the perm mask can be hoisted out of a loop or is already
5805 // used (perhaps because there are multiple permutes with the same shuffle
5806 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5807 // the loop requires an extra register.
5809 // As a compromise, we only emit discrete instructions if the shuffle can be
5810 // generated in 3 or fewer operations. When we have loop information
5811 // available, if this block is within a loop, we should avoid using vperm
5812 // for 3-operation perms and use a constant pool load instead.
5814 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5817 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5818 // vector that will get spilled to the constant pool.
5819 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5821 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5822 // that it is in input element units, not in bytes. Convert now.
5823 EVT EltVT = V1.getValueType().getVectorElementType();
5824 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5826 SmallVector<SDValue, 16> ResultMask;
5827 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5828 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5830 for (unsigned j = 0; j != BytesPerElement; ++j)
5831 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5835 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5837 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5840 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5841 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5842 /// information about the intrinsic.
5843 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5845 unsigned IntrinsicID =
5846 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5849 switch (IntrinsicID) {
5850 default: return false;
5851 // Comparison predicates.
5852 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5853 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5854 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5855 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5856 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5857 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5858 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5859 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5860 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5861 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5862 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5863 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5864 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5866 // Normal Comparisons.
5867 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5868 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5869 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5870 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5871 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5872 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5873 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5874 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5875 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5876 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5877 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5878 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5879 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5884 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5885 /// lower, do it, otherwise return null.
5886 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5887 SelectionDAG &DAG) const {
5888 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5889 // opcode number of the comparison.
5893 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5894 return SDValue(); // Don't custom lower most intrinsics.
5896 // If this is a non-dot comparison, make the VCMP node and we are done.
5898 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5899 Op.getOperand(1), Op.getOperand(2),
5900 DAG.getConstant(CompareOpc, MVT::i32));
5901 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5904 // Create the PPCISD altivec 'dot' comparison node.
5906 Op.getOperand(2), // LHS
5907 Op.getOperand(3), // RHS
5908 DAG.getConstant(CompareOpc, MVT::i32)
5910 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5911 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5913 // Now that we have the comparison, emit a copy from the CR to a GPR.
5914 // This is flagged to the above dot comparison.
5915 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5916 DAG.getRegister(PPC::CR6, MVT::i32),
5917 CompNode.getValue(1));
5919 // Unpack the result based on how the target uses it.
5920 unsigned BitNo; // Bit # of CR6.
5921 bool InvertBit; // Invert result?
5922 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5923 default: // Can't happen, don't crash on invalid number though.
5924 case 0: // Return the value of the EQ bit of CR6.
5925 BitNo = 0; InvertBit = false;
5927 case 1: // Return the inverted value of the EQ bit of CR6.
5928 BitNo = 0; InvertBit = true;
5930 case 2: // Return the value of the LT bit of CR6.
5931 BitNo = 2; InvertBit = false;
5933 case 3: // Return the inverted value of the LT bit of CR6.
5934 BitNo = 2; InvertBit = true;
5938 // Shift the bit into the low position.
5939 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5940 DAG.getConstant(8-(3-BitNo), MVT::i32));
5942 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5943 DAG.getConstant(1, MVT::i32));
5945 // If we are supposed to, toggle the bit.
5947 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5948 DAG.getConstant(1, MVT::i32));
5952 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
5953 SelectionDAG &DAG) const {
5955 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
5956 // instructions), but for smaller types, we need to first extend up to v2i32
5957 // before doing going farther.
5958 if (Op.getValueType() == MVT::v2i64) {
5959 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
5960 if (ExtVT != MVT::v2i32) {
5961 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
5962 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
5963 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
5964 ExtVT.getVectorElementType(), 4)));
5965 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
5966 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
5967 DAG.getValueType(MVT::v2i32));
5976 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5977 SelectionDAG &DAG) const {
5979 // Create a stack slot that is 16-byte aligned.
5980 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5981 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5982 EVT PtrVT = getPointerTy();
5983 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5985 // Store the input value into Value#0 of the stack slot.
5986 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5987 Op.getOperand(0), FIdx, MachinePointerInfo(),
5990 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5991 false, false, false, 0);
5994 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5996 if (Op.getValueType() == MVT::v4i32) {
5997 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5999 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6000 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6002 SDValue RHSSwap = // = vrlw RHS, 16
6003 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6005 // Shrinkify inputs to v8i16.
6006 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6007 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6008 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6010 // Low parts multiplied together, generating 32-bit results (we ignore the
6012 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6013 LHS, RHS, DAG, dl, MVT::v4i32);
6015 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6016 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6017 // Shift the high parts up 16 bits.
6018 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6020 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6021 } else if (Op.getValueType() == MVT::v8i16) {
6022 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6024 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6026 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6027 LHS, RHS, Zero, DAG, dl);
6028 } else if (Op.getValueType() == MVT::v16i8) {
6029 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6031 // Multiply the even 8-bit parts, producing 16-bit sums.
6032 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6033 LHS, RHS, DAG, dl, MVT::v8i16);
6034 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6036 // Multiply the odd 8-bit parts, producing 16-bit sums.
6037 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6038 LHS, RHS, DAG, dl, MVT::v8i16);
6039 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6041 // Merge the results together.
6043 for (unsigned i = 0; i != 8; ++i) {
6045 Ops[i*2+1] = 2*i+1+16;
6047 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6049 llvm_unreachable("Unknown mul to lower!");
6053 /// LowerOperation - Provide custom lowering hooks for some operations.
6055 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6056 switch (Op.getOpcode()) {
6057 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6058 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6059 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6060 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6061 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6062 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6063 case ISD::SETCC: return LowerSETCC(Op, DAG);
6064 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6065 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6067 return LowerVASTART(Op, DAG, PPCSubTarget);
6070 return LowerVAARG(Op, DAG, PPCSubTarget);
6073 return LowerVACOPY(Op, DAG, PPCSubTarget);
6075 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
6076 case ISD::DYNAMIC_STACKALLOC:
6077 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
6079 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6080 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6082 case ISD::LOAD: return LowerLOAD(Op, DAG);
6083 case ISD::STORE: return LowerSTORE(Op, DAG);
6084 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6085 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6086 case ISD::FP_TO_UINT:
6087 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6089 case ISD::UINT_TO_FP:
6090 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6091 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6093 // Lower 64-bit shifts.
6094 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6095 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6096 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6098 // Vector-related lowering.
6099 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6100 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6101 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6102 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6103 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6104 case ISD::MUL: return LowerMUL(Op, DAG);
6106 // For counter-based loop handling.
6107 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6109 // Frame & Return address.
6110 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6111 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6115 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6116 SmallVectorImpl<SDValue>&Results,
6117 SelectionDAG &DAG) const {
6118 const TargetMachine &TM = getTargetMachine();
6120 switch (N->getOpcode()) {
6122 llvm_unreachable("Do not know how to custom type legalize this operation!");
6123 case ISD::INTRINSIC_W_CHAIN: {
6124 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6125 Intrinsic::ppc_is_decremented_ctr_nonzero)
6128 assert(N->getValueType(0) == MVT::i1 &&
6129 "Unexpected result type for CTR decrement intrinsic");
6130 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6131 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6132 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6135 Results.push_back(NewInt);
6136 Results.push_back(NewInt.getValue(1));
6140 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6141 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6144 EVT VT = N->getValueType(0);
6146 if (VT == MVT::i64) {
6147 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
6149 Results.push_back(NewNode);
6150 Results.push_back(NewNode.getValue(1));
6154 case ISD::FP_ROUND_INREG: {
6155 assert(N->getValueType(0) == MVT::ppcf128);
6156 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6157 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6158 MVT::f64, N->getOperand(0),
6159 DAG.getIntPtrConstant(0));
6160 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6161 MVT::f64, N->getOperand(0),
6162 DAG.getIntPtrConstant(1));
6164 // Add the two halves of the long double in round-to-zero mode.
6165 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6167 // We know the low half is about to be thrown away, so just use something
6169 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6173 case ISD::FP_TO_SINT:
6174 // LowerFP_TO_INT() can only handle f32 and f64.
6175 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6177 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6183 //===----------------------------------------------------------------------===//
6184 // Other Lowering Code
6185 //===----------------------------------------------------------------------===//
6188 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6189 bool is64bit, unsigned BinOpcode) const {
6190 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6191 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6193 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6194 MachineFunction *F = BB->getParent();
6195 MachineFunction::iterator It = BB;
6198 unsigned dest = MI->getOperand(0).getReg();
6199 unsigned ptrA = MI->getOperand(1).getReg();
6200 unsigned ptrB = MI->getOperand(2).getReg();
6201 unsigned incr = MI->getOperand(3).getReg();
6202 DebugLoc dl = MI->getDebugLoc();
6204 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6205 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6206 F->insert(It, loopMBB);
6207 F->insert(It, exitMBB);
6208 exitMBB->splice(exitMBB->begin(), BB,
6209 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6210 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6212 MachineRegisterInfo &RegInfo = F->getRegInfo();
6213 unsigned TmpReg = (!BinOpcode) ? incr :
6214 RegInfo.createVirtualRegister(
6215 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6216 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6220 // fallthrough --> loopMBB
6221 BB->addSuccessor(loopMBB);
6224 // l[wd]arx dest, ptr
6225 // add r0, dest, incr
6226 // st[wd]cx. r0, ptr
6228 // fallthrough --> exitMBB
6230 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6231 .addReg(ptrA).addReg(ptrB);
6233 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6234 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6235 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6236 BuildMI(BB, dl, TII->get(PPC::BCC))
6237 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6238 BB->addSuccessor(loopMBB);
6239 BB->addSuccessor(exitMBB);
6248 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6249 MachineBasicBlock *BB,
6250 bool is8bit, // operation
6251 unsigned BinOpcode) const {
6252 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6253 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6254 // In 64 bit mode we have to use 64 bits for addresses, even though the
6255 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6256 // registers without caring whether they're 32 or 64, but here we're
6257 // doing actual arithmetic on the addresses.
6258 bool is64bit = PPCSubTarget.isPPC64();
6259 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6261 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6262 MachineFunction *F = BB->getParent();
6263 MachineFunction::iterator It = BB;
6266 unsigned dest = MI->getOperand(0).getReg();
6267 unsigned ptrA = MI->getOperand(1).getReg();
6268 unsigned ptrB = MI->getOperand(2).getReg();
6269 unsigned incr = MI->getOperand(3).getReg();
6270 DebugLoc dl = MI->getDebugLoc();
6272 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6273 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6274 F->insert(It, loopMBB);
6275 F->insert(It, exitMBB);
6276 exitMBB->splice(exitMBB->begin(), BB,
6277 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6278 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6280 MachineRegisterInfo &RegInfo = F->getRegInfo();
6281 const TargetRegisterClass *RC =
6282 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6283 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6284 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6285 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6286 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6287 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6288 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6289 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6290 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6291 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6292 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6293 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6294 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6296 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6300 // fallthrough --> loopMBB
6301 BB->addSuccessor(loopMBB);
6303 // The 4-byte load must be aligned, while a char or short may be
6304 // anywhere in the word. Hence all this nasty bookkeeping code.
6305 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6306 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6307 // xori shift, shift1, 24 [16]
6308 // rlwinm ptr, ptr1, 0, 0, 29
6309 // slw incr2, incr, shift
6310 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6311 // slw mask, mask2, shift
6313 // lwarx tmpDest, ptr
6314 // add tmp, tmpDest, incr2
6315 // andc tmp2, tmpDest, mask
6316 // and tmp3, tmp, mask
6317 // or tmp4, tmp3, tmp2
6320 // fallthrough --> exitMBB
6321 // srw dest, tmpDest, shift
6322 if (ptrA != ZeroReg) {
6323 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6324 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6325 .addReg(ptrA).addReg(ptrB);
6329 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6330 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6331 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6332 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6334 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6335 .addReg(Ptr1Reg).addImm(0).addImm(61);
6337 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6338 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6339 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6340 .addReg(incr).addReg(ShiftReg);
6342 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6344 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6345 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6347 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6348 .addReg(Mask2Reg).addReg(ShiftReg);
6351 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6352 .addReg(ZeroReg).addReg(PtrReg);
6354 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6355 .addReg(Incr2Reg).addReg(TmpDestReg);
6356 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6357 .addReg(TmpDestReg).addReg(MaskReg);
6358 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6359 .addReg(TmpReg).addReg(MaskReg);
6360 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6361 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6362 BuildMI(BB, dl, TII->get(PPC::STWCX))
6363 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6364 BuildMI(BB, dl, TII->get(PPC::BCC))
6365 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6366 BB->addSuccessor(loopMBB);
6367 BB->addSuccessor(exitMBB);
6372 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6377 llvm::MachineBasicBlock*
6378 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6379 MachineBasicBlock *MBB) const {
6380 DebugLoc DL = MI->getDebugLoc();
6381 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6383 MachineFunction *MF = MBB->getParent();
6384 MachineRegisterInfo &MRI = MF->getRegInfo();
6386 const BasicBlock *BB = MBB->getBasicBlock();
6387 MachineFunction::iterator I = MBB;
6391 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6392 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6394 unsigned DstReg = MI->getOperand(0).getReg();
6395 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6396 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6397 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6398 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6400 MVT PVT = getPointerTy();
6401 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6402 "Invalid Pointer Size!");
6403 // For v = setjmp(buf), we generate
6406 // SjLjSetup mainMBB
6412 // buf[LabelOffset] = LR
6416 // v = phi(main, restore)
6419 MachineBasicBlock *thisMBB = MBB;
6420 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6421 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6422 MF->insert(I, mainMBB);
6423 MF->insert(I, sinkMBB);
6425 MachineInstrBuilder MIB;
6427 // Transfer the remainder of BB and its successor edges to sinkMBB.
6428 sinkMBB->splice(sinkMBB->begin(), MBB,
6429 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6430 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6432 // Note that the structure of the jmp_buf used here is not compatible
6433 // with that used by libc, and is not designed to be. Specifically, it
6434 // stores only those 'reserved' registers that LLVM does not otherwise
6435 // understand how to spill. Also, by convention, by the time this
6436 // intrinsic is called, Clang has already stored the frame address in the
6437 // first slot of the buffer and stack address in the third. Following the
6438 // X86 target code, we'll store the jump address in the second slot. We also
6439 // need to save the TOC pointer (R2) to handle jumps between shared
6440 // libraries, and that will be stored in the fourth slot. The thread
6441 // identifier (R13) is not affected.
6444 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6445 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6446 const int64_t BPOffset = 4 * PVT.getStoreSize();
6448 // Prepare IP either in reg.
6449 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6450 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6451 unsigned BufReg = MI->getOperand(1).getReg();
6453 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6454 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6458 MIB.setMemRefs(MMOBegin, MMOEnd);
6461 // Naked functions never have a base pointer, and so we use r1. For all
6462 // other functions, this decision must be delayed until during PEI.
6464 if (MF->getFunction()->getAttributes().hasAttribute(
6465 AttributeSet::FunctionIndex, Attribute::Naked))
6466 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6468 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6470 MIB = BuildMI(*thisMBB, MI, DL,
6471 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6475 MIB.setMemRefs(MMOBegin, MMOEnd);
6478 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6479 const PPCRegisterInfo *TRI =
6480 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6481 MIB.addRegMask(TRI->getNoPreservedMask());
6483 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6485 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6487 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6489 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6490 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6494 MIB = BuildMI(mainMBB, DL,
6495 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6498 if (PPCSubTarget.isPPC64()) {
6499 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6501 .addImm(LabelOffset)
6504 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6506 .addImm(LabelOffset)
6510 MIB.setMemRefs(MMOBegin, MMOEnd);
6512 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6513 mainMBB->addSuccessor(sinkMBB);
6516 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6517 TII->get(PPC::PHI), DstReg)
6518 .addReg(mainDstReg).addMBB(mainMBB)
6519 .addReg(restoreDstReg).addMBB(thisMBB);
6521 MI->eraseFromParent();
6526 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6527 MachineBasicBlock *MBB) const {
6528 DebugLoc DL = MI->getDebugLoc();
6529 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6531 MachineFunction *MF = MBB->getParent();
6532 MachineRegisterInfo &MRI = MF->getRegInfo();
6535 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6536 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6538 MVT PVT = getPointerTy();
6539 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6540 "Invalid Pointer Size!");
6542 const TargetRegisterClass *RC =
6543 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6544 unsigned Tmp = MRI.createVirtualRegister(RC);
6545 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6546 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6547 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6548 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6550 MachineInstrBuilder MIB;
6552 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6553 const int64_t SPOffset = 2 * PVT.getStoreSize();
6554 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6555 const int64_t BPOffset = 4 * PVT.getStoreSize();
6557 unsigned BufReg = MI->getOperand(0).getReg();
6559 // Reload FP (the jumped-to function may not have had a
6560 // frame pointer, and if so, then its r31 will be restored
6562 if (PVT == MVT::i64) {
6563 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6567 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6571 MIB.setMemRefs(MMOBegin, MMOEnd);
6574 if (PVT == MVT::i64) {
6575 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6576 .addImm(LabelOffset)
6579 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6580 .addImm(LabelOffset)
6583 MIB.setMemRefs(MMOBegin, MMOEnd);
6586 if (PVT == MVT::i64) {
6587 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6591 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6595 MIB.setMemRefs(MMOBegin, MMOEnd);
6598 if (PVT == MVT::i64) {
6599 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6603 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6607 MIB.setMemRefs(MMOBegin, MMOEnd);
6610 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6611 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6615 MIB.setMemRefs(MMOBegin, MMOEnd);
6619 BuildMI(*MBB, MI, DL,
6620 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6621 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6623 MI->eraseFromParent();
6628 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6629 MachineBasicBlock *BB) const {
6630 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6631 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6632 return emitEHSjLjSetJmp(MI, BB);
6633 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6634 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6635 return emitEHSjLjLongJmp(MI, BB);
6638 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6640 // To "insert" these instructions we actually have to insert their
6641 // control-flow patterns.
6642 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6643 MachineFunction::iterator It = BB;
6646 MachineFunction *F = BB->getParent();
6648 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6649 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6650 MI->getOpcode() == PPC::SELECT_I4 ||
6651 MI->getOpcode() == PPC::SELECT_I8)) {
6652 SmallVector<MachineOperand, 2> Cond;
6653 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6654 MI->getOpcode() == PPC::SELECT_CC_I8)
6655 Cond.push_back(MI->getOperand(4));
6657 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6658 Cond.push_back(MI->getOperand(1));
6660 DebugLoc dl = MI->getDebugLoc();
6661 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6662 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6663 Cond, MI->getOperand(2).getReg(),
6664 MI->getOperand(3).getReg());
6665 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6666 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6667 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6668 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6669 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6670 MI->getOpcode() == PPC::SELECT_I4 ||
6671 MI->getOpcode() == PPC::SELECT_I8 ||
6672 MI->getOpcode() == PPC::SELECT_F4 ||
6673 MI->getOpcode() == PPC::SELECT_F8 ||
6674 MI->getOpcode() == PPC::SELECT_VRRC) {
6675 // The incoming instruction knows the destination vreg to set, the
6676 // condition code register to branch on, the true/false values to
6677 // select between, and a branch opcode to use.
6682 // cmpTY ccX, r1, r2
6684 // fallthrough --> copy0MBB
6685 MachineBasicBlock *thisMBB = BB;
6686 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6687 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6688 DebugLoc dl = MI->getDebugLoc();
6689 F->insert(It, copy0MBB);
6690 F->insert(It, sinkMBB);
6692 // Transfer the remainder of BB and its successor edges to sinkMBB.
6693 sinkMBB->splice(sinkMBB->begin(), BB,
6694 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6695 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6697 // Next, add the true and fallthrough blocks as its successors.
6698 BB->addSuccessor(copy0MBB);
6699 BB->addSuccessor(sinkMBB);
6701 if (MI->getOpcode() == PPC::SELECT_I4 ||
6702 MI->getOpcode() == PPC::SELECT_I8 ||
6703 MI->getOpcode() == PPC::SELECT_F4 ||
6704 MI->getOpcode() == PPC::SELECT_F8 ||
6705 MI->getOpcode() == PPC::SELECT_VRRC) {
6706 BuildMI(BB, dl, TII->get(PPC::BC))
6707 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6709 unsigned SelectPred = MI->getOperand(4).getImm();
6710 BuildMI(BB, dl, TII->get(PPC::BCC))
6711 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6715 // %FalseValue = ...
6716 // # fallthrough to sinkMBB
6719 // Update machine-CFG edges
6720 BB->addSuccessor(sinkMBB);
6723 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6726 BuildMI(*BB, BB->begin(), dl,
6727 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6728 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6729 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6731 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6732 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6733 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6734 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6735 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6736 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6737 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6738 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6740 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6741 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6742 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6743 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6744 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6745 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6746 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6747 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6749 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6750 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6751 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6752 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6754 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6755 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6756 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6758 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6759 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6760 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6761 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6763 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6765 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6767 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6768 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6769 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6770 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6772 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6774 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6776 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6777 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6778 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6779 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6781 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6783 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6785 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6786 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6787 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6788 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6789 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6790 BB = EmitAtomicBinary(MI, BB, false, 0);
6791 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6792 BB = EmitAtomicBinary(MI, BB, true, 0);
6794 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6795 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6796 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6798 unsigned dest = MI->getOperand(0).getReg();
6799 unsigned ptrA = MI->getOperand(1).getReg();
6800 unsigned ptrB = MI->getOperand(2).getReg();
6801 unsigned oldval = MI->getOperand(3).getReg();
6802 unsigned newval = MI->getOperand(4).getReg();
6803 DebugLoc dl = MI->getDebugLoc();
6805 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6806 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6807 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6808 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6809 F->insert(It, loop1MBB);
6810 F->insert(It, loop2MBB);
6811 F->insert(It, midMBB);
6812 F->insert(It, exitMBB);
6813 exitMBB->splice(exitMBB->begin(), BB,
6814 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6815 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6819 // fallthrough --> loopMBB
6820 BB->addSuccessor(loop1MBB);
6823 // l[wd]arx dest, ptr
6824 // cmp[wd] dest, oldval
6827 // st[wd]cx. newval, ptr
6831 // st[wd]cx. dest, ptr
6834 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6835 .addReg(ptrA).addReg(ptrB);
6836 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6837 .addReg(oldval).addReg(dest);
6838 BuildMI(BB, dl, TII->get(PPC::BCC))
6839 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6840 BB->addSuccessor(loop2MBB);
6841 BB->addSuccessor(midMBB);
6844 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6845 .addReg(newval).addReg(ptrA).addReg(ptrB);
6846 BuildMI(BB, dl, TII->get(PPC::BCC))
6847 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6848 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6849 BB->addSuccessor(loop1MBB);
6850 BB->addSuccessor(exitMBB);
6853 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6854 .addReg(dest).addReg(ptrA).addReg(ptrB);
6855 BB->addSuccessor(exitMBB);
6860 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6861 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6862 // We must use 64-bit registers for addresses when targeting 64-bit,
6863 // since we're actually doing arithmetic on them. Other registers
6865 bool is64bit = PPCSubTarget.isPPC64();
6866 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6868 unsigned dest = MI->getOperand(0).getReg();
6869 unsigned ptrA = MI->getOperand(1).getReg();
6870 unsigned ptrB = MI->getOperand(2).getReg();
6871 unsigned oldval = MI->getOperand(3).getReg();
6872 unsigned newval = MI->getOperand(4).getReg();
6873 DebugLoc dl = MI->getDebugLoc();
6875 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6876 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6877 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6878 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6879 F->insert(It, loop1MBB);
6880 F->insert(It, loop2MBB);
6881 F->insert(It, midMBB);
6882 F->insert(It, exitMBB);
6883 exitMBB->splice(exitMBB->begin(), BB,
6884 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6885 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6887 MachineRegisterInfo &RegInfo = F->getRegInfo();
6888 const TargetRegisterClass *RC =
6889 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6890 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6891 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6892 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6893 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6894 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6895 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6896 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6897 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6898 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6899 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6900 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6901 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6902 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6903 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6905 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6906 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6909 // fallthrough --> loopMBB
6910 BB->addSuccessor(loop1MBB);
6912 // The 4-byte load must be aligned, while a char or short may be
6913 // anywhere in the word. Hence all this nasty bookkeeping code.
6914 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6915 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6916 // xori shift, shift1, 24 [16]
6917 // rlwinm ptr, ptr1, 0, 0, 29
6918 // slw newval2, newval, shift
6919 // slw oldval2, oldval,shift
6920 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6921 // slw mask, mask2, shift
6922 // and newval3, newval2, mask
6923 // and oldval3, oldval2, mask
6925 // lwarx tmpDest, ptr
6926 // and tmp, tmpDest, mask
6927 // cmpw tmp, oldval3
6930 // andc tmp2, tmpDest, mask
6931 // or tmp4, tmp2, newval3
6936 // stwcx. tmpDest, ptr
6938 // srw dest, tmpDest, shift
6939 if (ptrA != ZeroReg) {
6940 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6941 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6942 .addReg(ptrA).addReg(ptrB);
6946 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6947 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6948 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6949 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6951 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6952 .addReg(Ptr1Reg).addImm(0).addImm(61);
6954 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6955 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6956 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6957 .addReg(newval).addReg(ShiftReg);
6958 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6959 .addReg(oldval).addReg(ShiftReg);
6961 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6963 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6964 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6965 .addReg(Mask3Reg).addImm(65535);
6967 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6968 .addReg(Mask2Reg).addReg(ShiftReg);
6969 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6970 .addReg(NewVal2Reg).addReg(MaskReg);
6971 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6972 .addReg(OldVal2Reg).addReg(MaskReg);
6975 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6976 .addReg(ZeroReg).addReg(PtrReg);
6977 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6978 .addReg(TmpDestReg).addReg(MaskReg);
6979 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6980 .addReg(TmpReg).addReg(OldVal3Reg);
6981 BuildMI(BB, dl, TII->get(PPC::BCC))
6982 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6983 BB->addSuccessor(loop2MBB);
6984 BB->addSuccessor(midMBB);
6987 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6988 .addReg(TmpDestReg).addReg(MaskReg);
6989 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6990 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6991 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6992 .addReg(ZeroReg).addReg(PtrReg);
6993 BuildMI(BB, dl, TII->get(PPC::BCC))
6994 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6995 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6996 BB->addSuccessor(loop1MBB);
6997 BB->addSuccessor(exitMBB);
7000 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7001 .addReg(ZeroReg).addReg(PtrReg);
7002 BB->addSuccessor(exitMBB);
7007 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7009 } else if (MI->getOpcode() == PPC::FADDrtz) {
7010 // This pseudo performs an FADD with rounding mode temporarily forced
7011 // to round-to-zero. We emit this via custom inserter since the FPSCR
7012 // is not modeled at the SelectionDAG level.
7013 unsigned Dest = MI->getOperand(0).getReg();
7014 unsigned Src1 = MI->getOperand(1).getReg();
7015 unsigned Src2 = MI->getOperand(2).getReg();
7016 DebugLoc dl = MI->getDebugLoc();
7018 MachineRegisterInfo &RegInfo = F->getRegInfo();
7019 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7021 // Save FPSCR value.
7022 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7024 // Set rounding mode to round-to-zero.
7025 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7026 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7028 // Perform addition.
7029 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7031 // Restore FPSCR value.
7032 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7033 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7034 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7035 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7036 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7037 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7038 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7039 PPC::ANDIo8 : PPC::ANDIo;
7040 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7041 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7043 MachineRegisterInfo &RegInfo = F->getRegInfo();
7044 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7045 &PPC::GPRCRegClass :
7046 &PPC::G8RCRegClass);
7048 DebugLoc dl = MI->getDebugLoc();
7049 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7050 .addReg(MI->getOperand(1).getReg()).addImm(1);
7051 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7052 MI->getOperand(0).getReg())
7053 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7055 llvm_unreachable("Unexpected instr type to insert");
7058 MI->eraseFromParent(); // The pseudo instruction is gone now.
7062 //===----------------------------------------------------------------------===//
7063 // Target Optimization Hooks
7064 //===----------------------------------------------------------------------===//
7066 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7067 DAGCombinerInfo &DCI) const {
7068 if (DCI.isAfterLegalizeVectorOps())
7071 EVT VT = Op.getValueType();
7073 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
7074 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
7075 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec()) ||
7076 (VT == MVT::v2f64 && PPCSubTarget.hasVSX())) {
7078 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7079 // For the reciprocal, we need to find the zero of the function:
7080 // F(X) = A X - 1 [which has a zero at X = 1/A]
7082 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7083 // does not require additional intermediate precision]
7085 // Convergence is quadratic, so we essentially double the number of digits
7086 // correct after every iteration. The minimum architected relative
7087 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7088 // 23 digits and double has 52 digits.
7089 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
7090 if (VT.getScalarType() == MVT::f64)
7093 SelectionDAG &DAG = DCI.DAG;
7097 DAG.getConstantFP(1.0, VT.getScalarType());
7098 if (VT.isVector()) {
7099 assert(VT.getVectorNumElements() == 4 &&
7100 "Unknown vector type");
7101 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7102 FPOne, FPOne, FPOne, FPOne);
7105 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7106 DCI.AddToWorklist(Est.getNode());
7108 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7109 for (int i = 0; i < Iterations; ++i) {
7110 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7111 DCI.AddToWorklist(NewEst.getNode());
7113 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7114 DCI.AddToWorklist(NewEst.getNode());
7116 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7117 DCI.AddToWorklist(NewEst.getNode());
7119 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7120 DCI.AddToWorklist(Est.getNode());
7129 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7130 DAGCombinerInfo &DCI) const {
7131 if (DCI.isAfterLegalizeVectorOps())
7134 EVT VT = Op.getValueType();
7136 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
7137 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
7138 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec()) ||
7139 (VT == MVT::v2f64 && PPCSubTarget.hasVSX())) {
7141 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7142 // For the reciprocal sqrt, we need to find the zero of the function:
7143 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7145 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7146 // As a result, we precompute A/2 prior to the iteration loop.
7148 // Convergence is quadratic, so we essentially double the number of digits
7149 // correct after every iteration. The minimum architected relative
7150 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7151 // 23 digits and double has 52 digits.
7152 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
7153 if (VT.getScalarType() == MVT::f64)
7156 SelectionDAG &DAG = DCI.DAG;
7159 SDValue FPThreeHalves =
7160 DAG.getConstantFP(1.5, VT.getScalarType());
7161 if (VT.isVector()) {
7162 assert(VT.getVectorNumElements() == 4 &&
7163 "Unknown vector type");
7164 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7165 FPThreeHalves, FPThreeHalves,
7166 FPThreeHalves, FPThreeHalves);
7169 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7170 DCI.AddToWorklist(Est.getNode());
7172 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7173 // this entire sequence requires only one FP constant.
7174 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7175 DCI.AddToWorklist(HalfArg.getNode());
7177 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7178 DCI.AddToWorklist(HalfArg.getNode());
7180 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7181 for (int i = 0; i < Iterations; ++i) {
7182 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7183 DCI.AddToWorklist(NewEst.getNode());
7185 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7186 DCI.AddToWorklist(NewEst.getNode());
7188 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7189 DCI.AddToWorklist(NewEst.getNode());
7191 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7192 DCI.AddToWorklist(Est.getNode());
7201 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7202 // not enforce equality of the chain operands.
7203 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7204 unsigned Bytes, int Dist,
7205 SelectionDAG &DAG) {
7206 EVT VT = LS->getMemoryVT();
7207 if (VT.getSizeInBits() / 8 != Bytes)
7210 SDValue Loc = LS->getBasePtr();
7211 SDValue BaseLoc = Base->getBasePtr();
7212 if (Loc.getOpcode() == ISD::FrameIndex) {
7213 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7215 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7216 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7217 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7218 int FS = MFI->getObjectSize(FI);
7219 int BFS = MFI->getObjectSize(BFI);
7220 if (FS != BFS || FS != (int)Bytes) return false;
7221 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7225 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7226 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7229 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7230 const GlobalValue *GV1 = nullptr;
7231 const GlobalValue *GV2 = nullptr;
7232 int64_t Offset1 = 0;
7233 int64_t Offset2 = 0;
7234 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7235 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7236 if (isGA1 && isGA2 && GV1 == GV2)
7237 return Offset1 == (Offset2 + Dist*Bytes);
7241 // Return true is there is a nearyby consecutive load to the one provided
7242 // (regardless of alignment). We search up and down the chain, looking though
7243 // token factors and other loads (but nothing else). As a result, a true
7244 // results indicates that it is safe to create a new consecutive load adjacent
7245 // to the load provided.
7246 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7247 SDValue Chain = LD->getChain();
7248 EVT VT = LD->getMemoryVT();
7250 SmallSet<SDNode *, 16> LoadRoots;
7251 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7252 SmallSet<SDNode *, 16> Visited;
7254 // First, search up the chain, branching to follow all token-factor operands.
7255 // If we find a consecutive load, then we're done, otherwise, record all
7256 // nodes just above the top-level loads and token factors.
7257 while (!Queue.empty()) {
7258 SDNode *ChainNext = Queue.pop_back_val();
7259 if (!Visited.insert(ChainNext))
7262 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7263 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7266 if (!Visited.count(ChainLD->getChain().getNode()))
7267 Queue.push_back(ChainLD->getChain().getNode());
7268 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7269 for (SDNode::op_iterator O = ChainNext->op_begin(),
7270 OE = ChainNext->op_end(); O != OE; ++O)
7271 if (!Visited.count(O->getNode()))
7272 Queue.push_back(O->getNode());
7274 LoadRoots.insert(ChainNext);
7277 // Second, search down the chain, starting from the top-level nodes recorded
7278 // in the first phase. These top-level nodes are the nodes just above all
7279 // loads and token factors. Starting with their uses, recursively look though
7280 // all loads (just the chain uses) and token factors to find a consecutive
7285 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7286 IE = LoadRoots.end(); I != IE; ++I) {
7287 Queue.push_back(*I);
7289 while (!Queue.empty()) {
7290 SDNode *LoadRoot = Queue.pop_back_val();
7291 if (!Visited.insert(LoadRoot))
7294 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7295 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7298 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7299 UE = LoadRoot->use_end(); UI != UE; ++UI)
7300 if (((isa<LoadSDNode>(*UI) &&
7301 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7302 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7303 Queue.push_back(*UI);
7310 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7311 DAGCombinerInfo &DCI) const {
7312 SelectionDAG &DAG = DCI.DAG;
7315 assert(PPCSubTarget.useCRBits() &&
7316 "Expecting to be tracking CR bits");
7317 // If we're tracking CR bits, we need to be careful that we don't have:
7318 // trunc(binary-ops(zext(x), zext(y)))
7320 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7321 // such that we're unnecessarily moving things into GPRs when it would be
7322 // better to keep them in CR bits.
7324 // Note that trunc here can be an actual i1 trunc, or can be the effective
7325 // truncation that comes from a setcc or select_cc.
7326 if (N->getOpcode() == ISD::TRUNCATE &&
7327 N->getValueType(0) != MVT::i1)
7330 if (N->getOperand(0).getValueType() != MVT::i32 &&
7331 N->getOperand(0).getValueType() != MVT::i64)
7334 if (N->getOpcode() == ISD::SETCC ||
7335 N->getOpcode() == ISD::SELECT_CC) {
7336 // If we're looking at a comparison, then we need to make sure that the
7337 // high bits (all except for the first) don't matter the result.
7339 cast<CondCodeSDNode>(N->getOperand(
7340 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7341 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7343 if (ISD::isSignedIntSetCC(CC)) {
7344 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7345 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7347 } else if (ISD::isUnsignedIntSetCC(CC)) {
7348 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7349 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7350 !DAG.MaskedValueIsZero(N->getOperand(1),
7351 APInt::getHighBitsSet(OpBits, OpBits-1)))
7354 // This is neither a signed nor an unsigned comparison, just make sure
7355 // that the high bits are equal.
7356 APInt Op1Zero, Op1One;
7357 APInt Op2Zero, Op2One;
7358 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7359 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7361 // We don't really care about what is known about the first bit (if
7362 // anything), so clear it in all masks prior to comparing them.
7363 Op1Zero.clearBit(0); Op1One.clearBit(0);
7364 Op2Zero.clearBit(0); Op2One.clearBit(0);
7366 if (Op1Zero != Op2Zero || Op1One != Op2One)
7371 // We now know that the higher-order bits are irrelevant, we just need to
7372 // make sure that all of the intermediate operations are bit operations, and
7373 // all inputs are extensions.
7374 if (N->getOperand(0).getOpcode() != ISD::AND &&
7375 N->getOperand(0).getOpcode() != ISD::OR &&
7376 N->getOperand(0).getOpcode() != ISD::XOR &&
7377 N->getOperand(0).getOpcode() != ISD::SELECT &&
7378 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7379 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7380 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7381 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7382 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7385 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7386 N->getOperand(1).getOpcode() != ISD::AND &&
7387 N->getOperand(1).getOpcode() != ISD::OR &&
7388 N->getOperand(1).getOpcode() != ISD::XOR &&
7389 N->getOperand(1).getOpcode() != ISD::SELECT &&
7390 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7391 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7392 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7393 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7394 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7397 SmallVector<SDValue, 4> Inputs;
7398 SmallVector<SDValue, 8> BinOps, PromOps;
7399 SmallPtrSet<SDNode *, 16> Visited;
7401 for (unsigned i = 0; i < 2; ++i) {
7402 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7403 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7404 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7405 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7406 isa<ConstantSDNode>(N->getOperand(i)))
7407 Inputs.push_back(N->getOperand(i));
7409 BinOps.push_back(N->getOperand(i));
7411 if (N->getOpcode() == ISD::TRUNCATE)
7415 // Visit all inputs, collect all binary operations (and, or, xor and
7416 // select) that are all fed by extensions.
7417 while (!BinOps.empty()) {
7418 SDValue BinOp = BinOps.back();
7421 if (!Visited.insert(BinOp.getNode()))
7424 PromOps.push_back(BinOp);
7426 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7427 // The condition of the select is not promoted.
7428 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7430 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7433 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7434 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7435 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7436 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7437 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7438 Inputs.push_back(BinOp.getOperand(i));
7439 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7440 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7441 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7442 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7443 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7444 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7445 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7446 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7447 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7448 BinOps.push_back(BinOp.getOperand(i));
7450 // We have an input that is not an extension or another binary
7451 // operation; we'll abort this transformation.
7457 // Make sure that this is a self-contained cluster of operations (which
7458 // is not quite the same thing as saying that everything has only one
7460 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7461 if (isa<ConstantSDNode>(Inputs[i]))
7464 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7465 UE = Inputs[i].getNode()->use_end();
7468 if (User != N && !Visited.count(User))
7471 // Make sure that we're not going to promote the non-output-value
7472 // operand(s) or SELECT or SELECT_CC.
7473 // FIXME: Although we could sometimes handle this, and it does occur in
7474 // practice that one of the condition inputs to the select is also one of
7475 // the outputs, we currently can't deal with this.
7476 if (User->getOpcode() == ISD::SELECT) {
7477 if (User->getOperand(0) == Inputs[i])
7479 } else if (User->getOpcode() == ISD::SELECT_CC) {
7480 if (User->getOperand(0) == Inputs[i] ||
7481 User->getOperand(1) == Inputs[i])
7487 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7488 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7489 UE = PromOps[i].getNode()->use_end();
7492 if (User != N && !Visited.count(User))
7495 // Make sure that we're not going to promote the non-output-value
7496 // operand(s) or SELECT or SELECT_CC.
7497 // FIXME: Although we could sometimes handle this, and it does occur in
7498 // practice that one of the condition inputs to the select is also one of
7499 // the outputs, we currently can't deal with this.
7500 if (User->getOpcode() == ISD::SELECT) {
7501 if (User->getOperand(0) == PromOps[i])
7503 } else if (User->getOpcode() == ISD::SELECT_CC) {
7504 if (User->getOperand(0) == PromOps[i] ||
7505 User->getOperand(1) == PromOps[i])
7511 // Replace all inputs with the extension operand.
7512 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7513 // Constants may have users outside the cluster of to-be-promoted nodes,
7514 // and so we need to replace those as we do the promotions.
7515 if (isa<ConstantSDNode>(Inputs[i]))
7518 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7521 // Replace all operations (these are all the same, but have a different
7522 // (i1) return type). DAG.getNode will validate that the types of
7523 // a binary operator match, so go through the list in reverse so that
7524 // we've likely promoted both operands first. Any intermediate truncations or
7525 // extensions disappear.
7526 while (!PromOps.empty()) {
7527 SDValue PromOp = PromOps.back();
7530 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7531 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7532 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7533 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7534 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7535 PromOp.getOperand(0).getValueType() != MVT::i1) {
7536 // The operand is not yet ready (see comment below).
7537 PromOps.insert(PromOps.begin(), PromOp);
7541 SDValue RepValue = PromOp.getOperand(0);
7542 if (isa<ConstantSDNode>(RepValue))
7543 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7545 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7550 switch (PromOp.getOpcode()) {
7551 default: C = 0; break;
7552 case ISD::SELECT: C = 1; break;
7553 case ISD::SELECT_CC: C = 2; break;
7556 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7557 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7558 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7559 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7560 // The to-be-promoted operands of this node have not yet been
7561 // promoted (this should be rare because we're going through the
7562 // list backward, but if one of the operands has several users in
7563 // this cluster of to-be-promoted nodes, it is possible).
7564 PromOps.insert(PromOps.begin(), PromOp);
7568 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7569 PromOp.getNode()->op_end());
7571 // If there are any constant inputs, make sure they're replaced now.
7572 for (unsigned i = 0; i < 2; ++i)
7573 if (isa<ConstantSDNode>(Ops[C+i]))
7574 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7576 DAG.ReplaceAllUsesOfValueWith(PromOp,
7577 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7580 // Now we're left with the initial truncation itself.
7581 if (N->getOpcode() == ISD::TRUNCATE)
7582 return N->getOperand(0);
7584 // Otherwise, this is a comparison. The operands to be compared have just
7585 // changed type (to i1), but everything else is the same.
7586 return SDValue(N, 0);
7589 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7590 DAGCombinerInfo &DCI) const {
7591 SelectionDAG &DAG = DCI.DAG;
7594 // If we're tracking CR bits, we need to be careful that we don't have:
7595 // zext(binary-ops(trunc(x), trunc(y)))
7597 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7598 // such that we're unnecessarily moving things into CR bits that can more
7599 // efficiently stay in GPRs. Note that if we're not certain that the high
7600 // bits are set as required by the final extension, we still may need to do
7601 // some masking to get the proper behavior.
7603 // This same functionality is important on PPC64 when dealing with
7604 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7605 // the return values of functions. Because it is so similar, it is handled
7608 if (N->getValueType(0) != MVT::i32 &&
7609 N->getValueType(0) != MVT::i64)
7612 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7613 PPCSubTarget.useCRBits()) ||
7614 (N->getOperand(0).getValueType() == MVT::i32 &&
7615 PPCSubTarget.isPPC64())))
7618 if (N->getOperand(0).getOpcode() != ISD::AND &&
7619 N->getOperand(0).getOpcode() != ISD::OR &&
7620 N->getOperand(0).getOpcode() != ISD::XOR &&
7621 N->getOperand(0).getOpcode() != ISD::SELECT &&
7622 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7625 SmallVector<SDValue, 4> Inputs;
7626 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7627 SmallPtrSet<SDNode *, 16> Visited;
7629 // Visit all inputs, collect all binary operations (and, or, xor and
7630 // select) that are all fed by truncations.
7631 while (!BinOps.empty()) {
7632 SDValue BinOp = BinOps.back();
7635 if (!Visited.insert(BinOp.getNode()))
7638 PromOps.push_back(BinOp);
7640 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7641 // The condition of the select is not promoted.
7642 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7644 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7647 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7648 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7649 Inputs.push_back(BinOp.getOperand(i));
7650 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7651 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7652 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7653 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7654 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7655 BinOps.push_back(BinOp.getOperand(i));
7657 // We have an input that is not a truncation or another binary
7658 // operation; we'll abort this transformation.
7664 // Make sure that this is a self-contained cluster of operations (which
7665 // is not quite the same thing as saying that everything has only one
7667 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7668 if (isa<ConstantSDNode>(Inputs[i]))
7671 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7672 UE = Inputs[i].getNode()->use_end();
7675 if (User != N && !Visited.count(User))
7678 // Make sure that we're not going to promote the non-output-value
7679 // operand(s) or SELECT or SELECT_CC.
7680 // FIXME: Although we could sometimes handle this, and it does occur in
7681 // practice that one of the condition inputs to the select is also one of
7682 // the outputs, we currently can't deal with this.
7683 if (User->getOpcode() == ISD::SELECT) {
7684 if (User->getOperand(0) == Inputs[i])
7686 } else if (User->getOpcode() == ISD::SELECT_CC) {
7687 if (User->getOperand(0) == Inputs[i] ||
7688 User->getOperand(1) == Inputs[i])
7694 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7695 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7696 UE = PromOps[i].getNode()->use_end();
7699 if (User != N && !Visited.count(User))
7702 // Make sure that we're not going to promote the non-output-value
7703 // operand(s) or SELECT or SELECT_CC.
7704 // FIXME: Although we could sometimes handle this, and it does occur in
7705 // practice that one of the condition inputs to the select is also one of
7706 // the outputs, we currently can't deal with this.
7707 if (User->getOpcode() == ISD::SELECT) {
7708 if (User->getOperand(0) == PromOps[i])
7710 } else if (User->getOpcode() == ISD::SELECT_CC) {
7711 if (User->getOperand(0) == PromOps[i] ||
7712 User->getOperand(1) == PromOps[i])
7718 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7719 bool ReallyNeedsExt = false;
7720 if (N->getOpcode() != ISD::ANY_EXTEND) {
7721 // If all of the inputs are not already sign/zero extended, then
7722 // we'll still need to do that at the end.
7723 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7724 if (isa<ConstantSDNode>(Inputs[i]))
7728 Inputs[i].getOperand(0).getValueSizeInBits();
7729 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7731 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7732 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7733 APInt::getHighBitsSet(OpBits,
7734 OpBits-PromBits))) ||
7735 (N->getOpcode() == ISD::SIGN_EXTEND &&
7736 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7737 (OpBits-(PromBits-1)))) {
7738 ReallyNeedsExt = true;
7744 // Replace all inputs, either with the truncation operand, or a
7745 // truncation or extension to the final output type.
7746 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7747 // Constant inputs need to be replaced with the to-be-promoted nodes that
7748 // use them because they might have users outside of the cluster of
7750 if (isa<ConstantSDNode>(Inputs[i]))
7753 SDValue InSrc = Inputs[i].getOperand(0);
7754 if (Inputs[i].getValueType() == N->getValueType(0))
7755 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7756 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7757 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7758 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7759 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7760 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7761 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7763 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7764 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7767 // Replace all operations (these are all the same, but have a different
7768 // (promoted) return type). DAG.getNode will validate that the types of
7769 // a binary operator match, so go through the list in reverse so that
7770 // we've likely promoted both operands first.
7771 while (!PromOps.empty()) {
7772 SDValue PromOp = PromOps.back();
7776 switch (PromOp.getOpcode()) {
7777 default: C = 0; break;
7778 case ISD::SELECT: C = 1; break;
7779 case ISD::SELECT_CC: C = 2; break;
7782 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7783 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7784 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7785 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7786 // The to-be-promoted operands of this node have not yet been
7787 // promoted (this should be rare because we're going through the
7788 // list backward, but if one of the operands has several users in
7789 // this cluster of to-be-promoted nodes, it is possible).
7790 PromOps.insert(PromOps.begin(), PromOp);
7794 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7795 PromOp.getNode()->op_end());
7797 // If this node has constant inputs, then they'll need to be promoted here.
7798 for (unsigned i = 0; i < 2; ++i) {
7799 if (!isa<ConstantSDNode>(Ops[C+i]))
7801 if (Ops[C+i].getValueType() == N->getValueType(0))
7804 if (N->getOpcode() == ISD::SIGN_EXTEND)
7805 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7806 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7807 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7809 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7812 DAG.ReplaceAllUsesOfValueWith(PromOp,
7813 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7816 // Now we're left with the initial extension itself.
7817 if (!ReallyNeedsExt)
7818 return N->getOperand(0);
7820 // To zero extend, just mask off everything except for the first bit (in the
7822 if (N->getOpcode() == ISD::ZERO_EXTEND)
7823 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7824 DAG.getConstant(APInt::getLowBitsSet(
7825 N->getValueSizeInBits(0), PromBits),
7826 N->getValueType(0)));
7828 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7829 "Invalid extension type");
7830 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7832 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7833 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7834 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7835 N->getOperand(0), ShiftCst), ShiftCst);
7838 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7839 DAGCombinerInfo &DCI) const {
7840 const TargetMachine &TM = getTargetMachine();
7841 SelectionDAG &DAG = DCI.DAG;
7843 switch (N->getOpcode()) {
7846 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7847 if (C->isNullValue()) // 0 << V -> 0.
7848 return N->getOperand(0);
7852 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7853 if (C->isNullValue()) // 0 >>u V -> 0.
7854 return N->getOperand(0);
7858 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7859 if (C->isNullValue() || // 0 >>s V -> 0.
7860 C->isAllOnesValue()) // -1 >>s V -> -1.
7861 return N->getOperand(0);
7864 case ISD::SIGN_EXTEND:
7865 case ISD::ZERO_EXTEND:
7866 case ISD::ANY_EXTEND:
7867 return DAGCombineExtBoolTrunc(N, DCI);
7870 case ISD::SELECT_CC:
7871 return DAGCombineTruncBoolExt(N, DCI);
7873 assert(TM.Options.UnsafeFPMath &&
7874 "Reciprocal estimates require UnsafeFPMath");
7876 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7878 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7880 DCI.AddToWorklist(RV.getNode());
7881 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7882 N->getOperand(0), RV);
7884 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7885 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7887 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7890 DCI.AddToWorklist(RV.getNode());
7891 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7892 N->getValueType(0), RV);
7893 DCI.AddToWorklist(RV.getNode());
7894 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7895 N->getOperand(0), RV);
7897 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7898 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7900 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7903 DCI.AddToWorklist(RV.getNode());
7904 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7905 N->getValueType(0), RV,
7906 N->getOperand(1).getOperand(1));
7907 DCI.AddToWorklist(RV.getNode());
7908 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7909 N->getOperand(0), RV);
7913 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7915 DCI.AddToWorklist(RV.getNode());
7916 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7917 N->getOperand(0), RV);
7923 assert(TM.Options.UnsafeFPMath &&
7924 "Reciprocal estimates require UnsafeFPMath");
7926 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7928 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7930 DCI.AddToWorklist(RV.getNode());
7931 RV = DAGCombineFastRecip(RV, DCI);
7933 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
7934 // this case and force the answer to 0.
7936 EVT VT = RV.getValueType();
7938 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
7939 if (VT.isVector()) {
7940 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
7941 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
7945 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
7946 N->getOperand(0), Zero, ISD::SETEQ);
7947 DCI.AddToWorklist(ZeroCmp.getNode());
7948 DCI.AddToWorklist(RV.getNode());
7950 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
7958 case ISD::SINT_TO_FP:
7959 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7960 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7961 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7962 // We allow the src/dst to be either f32/f64, but the intermediate
7963 // type must be i64.
7964 if (N->getOperand(0).getValueType() == MVT::i64 &&
7965 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7966 SDValue Val = N->getOperand(0).getOperand(0);
7967 if (Val.getValueType() == MVT::f32) {
7968 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7969 DCI.AddToWorklist(Val.getNode());
7972 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7973 DCI.AddToWorklist(Val.getNode());
7974 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7975 DCI.AddToWorklist(Val.getNode());
7976 if (N->getValueType(0) == MVT::f32) {
7977 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7978 DAG.getIntPtrConstant(0));
7979 DCI.AddToWorklist(Val.getNode());
7982 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7983 // If the intermediate type is i32, we can avoid the load/store here
7990 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7991 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7992 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7993 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7994 N->getOperand(1).getValueType() == MVT::i32 &&
7995 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7996 SDValue Val = N->getOperand(1).getOperand(0);
7997 if (Val.getValueType() == MVT::f32) {
7998 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7999 DCI.AddToWorklist(Val.getNode());
8001 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8002 DCI.AddToWorklist(Val.getNode());
8005 N->getOperand(0), Val, N->getOperand(2),
8006 DAG.getValueType(N->getOperand(1).getValueType())
8009 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8010 DAG.getVTList(MVT::Other), Ops,
8011 cast<StoreSDNode>(N)->getMemoryVT(),
8012 cast<StoreSDNode>(N)->getMemOperand());
8013 DCI.AddToWorklist(Val.getNode());
8017 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8018 if (cast<StoreSDNode>(N)->isUnindexed() &&
8019 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8020 N->getOperand(1).getNode()->hasOneUse() &&
8021 (N->getOperand(1).getValueType() == MVT::i32 ||
8022 N->getOperand(1).getValueType() == MVT::i16 ||
8023 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8024 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8025 N->getOperand(1).getValueType() == MVT::i64))) {
8026 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8027 // Do an any-extend to 32-bits if this is a half-word input.
8028 if (BSwapOp.getValueType() == MVT::i16)
8029 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8032 N->getOperand(0), BSwapOp, N->getOperand(2),
8033 DAG.getValueType(N->getOperand(1).getValueType())
8036 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8037 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8038 cast<StoreSDNode>(N)->getMemOperand());
8042 LoadSDNode *LD = cast<LoadSDNode>(N);
8043 EVT VT = LD->getValueType(0);
8044 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8045 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8046 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8047 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8048 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8049 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8050 LD->getAlignment() < ABIAlignment) {
8051 // This is a type-legal unaligned Altivec load.
8052 SDValue Chain = LD->getChain();
8053 SDValue Ptr = LD->getBasePtr();
8055 // This implements the loading of unaligned vectors as described in
8056 // the venerable Apple Velocity Engine overview. Specifically:
8057 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8058 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8060 // The general idea is to expand a sequence of one or more unaligned
8061 // loads into a alignment-based permutation-control instruction (lvsl),
8062 // a series of regular vector loads (which always truncate their
8063 // input address to an aligned address), and a series of permutations.
8064 // The results of these permutations are the requested loaded values.
8065 // The trick is that the last "extra" load is not taken from the address
8066 // you might suspect (sizeof(vector) bytes after the last requested
8067 // load), but rather sizeof(vector) - 1 bytes after the last
8068 // requested vector. The point of this is to avoid a page fault if the
8069 // base address happened to be aligned. This works because if the base
8070 // address is aligned, then adding less than a full vector length will
8071 // cause the last vector in the sequence to be (re)loaded. Otherwise,
8072 // the next vector will be fetched as you might suspect was necessary.
8074 // We might be able to reuse the permutation generation from
8075 // a different base address offset from this one by an aligned amount.
8076 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8077 // optimization later.
8078 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
8079 DAG, dl, MVT::v16i8);
8081 // Refine the alignment of the original load (a "new" load created here
8082 // which was identical to the first except for the alignment would be
8083 // merged with the existing node regardless).
8084 MachineFunction &MF = DAG.getMachineFunction();
8085 MachineMemOperand *MMO =
8086 MF.getMachineMemOperand(LD->getPointerInfo(),
8087 LD->getMemOperand()->getFlags(),
8088 LD->getMemoryVT().getStoreSize(),
8090 LD->refineAlignment(MMO);
8091 SDValue BaseLoad = SDValue(LD, 0);
8093 // Note that the value of IncOffset (which is provided to the next
8094 // load's pointer info offset value, and thus used to calculate the
8095 // alignment), and the value of IncValue (which is actually used to
8096 // increment the pointer value) are different! This is because we
8097 // require the next load to appear to be aligned, even though it
8098 // is actually offset from the base pointer by a lesser amount.
8099 int IncOffset = VT.getSizeInBits() / 8;
8100 int IncValue = IncOffset;
8102 // Walk (both up and down) the chain looking for another load at the real
8103 // (aligned) offset (the alignment of the other load does not matter in
8104 // this case). If found, then do not use the offset reduction trick, as
8105 // that will prevent the loads from being later combined (as they would
8106 // otherwise be duplicates).
8107 if (!findConsecutiveLoad(LD, DAG))
8110 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8111 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8114 DAG.getLoad(VT, dl, Chain, Ptr,
8115 LD->getPointerInfo().getWithOffset(IncOffset),
8116 LD->isVolatile(), LD->isNonTemporal(),
8117 LD->isInvariant(), ABIAlignment);
8119 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8120 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8122 if (BaseLoad.getValueType() != MVT::v4i32)
8123 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8125 if (ExtraLoad.getValueType() != MVT::v4i32)
8126 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8128 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8129 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8131 if (VT != MVT::v4i32)
8132 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8134 // Now we need to be really careful about how we update the users of the
8135 // original load. We cannot just call DCI.CombineTo (or
8136 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8137 // uses created here (the permutation for example) that need to stay.
8138 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8140 SDUse &Use = UI.getUse();
8142 // Note: BaseLoad is checked here because it might not be N, but a
8144 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8145 User == TF.getNode() || Use.getResNo() > 1) {
8150 SDValue To = Use.getResNo() ? TF : Perm;
8153 SmallVector<SDValue, 8> Ops;
8154 for (SDNode::op_iterator O = User->op_begin(),
8155 OE = User->op_end(); O != OE; ++O) {
8162 DAG.UpdateNodeOperands(User, Ops);
8165 return SDValue(N, 0);
8169 case ISD::INTRINSIC_WO_CHAIN:
8170 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
8171 Intrinsic::ppc_altivec_lvsl &&
8172 N->getOperand(1)->getOpcode() == ISD::ADD) {
8173 SDValue Add = N->getOperand(1);
8175 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8176 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8177 Add.getValueType().getScalarType().getSizeInBits()))) {
8178 SDNode *BasePtr = Add->getOperand(0).getNode();
8179 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8180 UE = BasePtr->use_end(); UI != UE; ++UI) {
8181 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8182 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8183 Intrinsic::ppc_altivec_lvsl) {
8184 // We've found another LVSL, and this address if an aligned
8185 // multiple of that one. The results will be the same, so use the
8186 // one we've just found instead.
8188 return SDValue(*UI, 0);
8196 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8197 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8198 N->getOperand(0).hasOneUse() &&
8199 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8200 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8201 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8202 N->getValueType(0) == MVT::i64))) {
8203 SDValue Load = N->getOperand(0);
8204 LoadSDNode *LD = cast<LoadSDNode>(Load);
8205 // Create the byte-swapping load.
8207 LD->getChain(), // Chain
8208 LD->getBasePtr(), // Ptr
8209 DAG.getValueType(N->getValueType(0)) // VT
8212 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8213 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8214 MVT::i64 : MVT::i32, MVT::Other),
8215 Ops, LD->getMemoryVT(), LD->getMemOperand());
8217 // If this is an i16 load, insert the truncate.
8218 SDValue ResVal = BSLoad;
8219 if (N->getValueType(0) == MVT::i16)
8220 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8222 // First, combine the bswap away. This makes the value produced by the
8224 DCI.CombineTo(N, ResVal);
8226 // Next, combine the load away, we give it a bogus result value but a real
8227 // chain result. The result value is dead because the bswap is dead.
8228 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8230 // Return N so it doesn't get rechecked!
8231 return SDValue(N, 0);
8235 case PPCISD::VCMP: {
8236 // If a VCMPo node already exists with exactly the same operands as this
8237 // node, use its result instead of this node (VCMPo computes both a CR6 and
8238 // a normal output).
8240 if (!N->getOperand(0).hasOneUse() &&
8241 !N->getOperand(1).hasOneUse() &&
8242 !N->getOperand(2).hasOneUse()) {
8244 // Scan all of the users of the LHS, looking for VCMPo's that match.
8245 SDNode *VCMPoNode = nullptr;
8247 SDNode *LHSN = N->getOperand(0).getNode();
8248 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8250 if (UI->getOpcode() == PPCISD::VCMPo &&
8251 UI->getOperand(1) == N->getOperand(1) &&
8252 UI->getOperand(2) == N->getOperand(2) &&
8253 UI->getOperand(0) == N->getOperand(0)) {
8258 // If there is no VCMPo node, or if the flag value has a single use, don't
8260 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8263 // Look at the (necessarily single) use of the flag value. If it has a
8264 // chain, this transformation is more complex. Note that multiple things
8265 // could use the value result, which we should ignore.
8266 SDNode *FlagUser = nullptr;
8267 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8268 FlagUser == nullptr; ++UI) {
8269 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8271 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8272 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8279 // If the user is a MFOCRF instruction, we know this is safe.
8280 // Otherwise we give up for right now.
8281 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8282 return SDValue(VCMPoNode, 0);
8287 SDValue Cond = N->getOperand(1);
8288 SDValue Target = N->getOperand(2);
8290 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8291 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8292 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8294 // We now need to make the intrinsic dead (it cannot be instruction
8296 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8297 assert(Cond.getNode()->hasOneUse() &&
8298 "Counter decrement has more than one use");
8300 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8301 N->getOperand(0), Target);
8306 // If this is a branch on an altivec predicate comparison, lower this so
8307 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8308 // lowering is done pre-legalize, because the legalizer lowers the predicate
8309 // compare down to code that is difficult to reassemble.
8310 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8311 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8313 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8314 // value. If so, pass-through the AND to get to the intrinsic.
8315 if (LHS.getOpcode() == ISD::AND &&
8316 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8317 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8318 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8319 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8320 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8322 LHS = LHS.getOperand(0);
8324 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8325 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8326 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8327 isa<ConstantSDNode>(RHS)) {
8328 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8329 "Counter decrement comparison is not EQ or NE");
8331 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8332 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8333 (CC == ISD::SETNE && !Val);
8335 // We now need to make the intrinsic dead (it cannot be instruction
8337 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8338 assert(LHS.getNode()->hasOneUse() &&
8339 "Counter decrement has more than one use");
8341 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8342 N->getOperand(0), N->getOperand(4));
8348 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8349 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8350 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8351 assert(isDot && "Can't compare against a vector result!");
8353 // If this is a comparison against something other than 0/1, then we know
8354 // that the condition is never/always true.
8355 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8356 if (Val != 0 && Val != 1) {
8357 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8358 return N->getOperand(0);
8359 // Always !=, turn it into an unconditional branch.
8360 return DAG.getNode(ISD::BR, dl, MVT::Other,
8361 N->getOperand(0), N->getOperand(4));
8364 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8366 // Create the PPCISD altivec 'dot' comparison node.
8368 LHS.getOperand(2), // LHS of compare
8369 LHS.getOperand(3), // RHS of compare
8370 DAG.getConstant(CompareOpc, MVT::i32)
8372 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8373 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8375 // Unpack the result based on how the target uses it.
8376 PPC::Predicate CompOpc;
8377 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8378 default: // Can't happen, don't crash on invalid number though.
8379 case 0: // Branch on the value of the EQ bit of CR6.
8380 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8382 case 1: // Branch on the inverted value of the EQ bit of CR6.
8383 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8385 case 2: // Branch on the value of the LT bit of CR6.
8386 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8388 case 3: // Branch on the inverted value of the LT bit of CR6.
8389 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8393 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8394 DAG.getConstant(CompOpc, MVT::i32),
8395 DAG.getRegister(PPC::CR6, MVT::i32),
8396 N->getOperand(4), CompNode.getValue(1));
8405 //===----------------------------------------------------------------------===//
8406 // Inline Assembly Support
8407 //===----------------------------------------------------------------------===//
8409 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8412 const SelectionDAG &DAG,
8413 unsigned Depth) const {
8414 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8415 switch (Op.getOpcode()) {
8417 case PPCISD::LBRX: {
8418 // lhbrx is known to have the top bits cleared out.
8419 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8420 KnownZero = 0xFFFF0000;
8423 case ISD::INTRINSIC_WO_CHAIN: {
8424 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8426 case Intrinsic::ppc_altivec_vcmpbfp_p:
8427 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8428 case Intrinsic::ppc_altivec_vcmpequb_p:
8429 case Intrinsic::ppc_altivec_vcmpequh_p:
8430 case Intrinsic::ppc_altivec_vcmpequw_p:
8431 case Intrinsic::ppc_altivec_vcmpgefp_p:
8432 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8433 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8434 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8435 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8436 case Intrinsic::ppc_altivec_vcmpgtub_p:
8437 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8438 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8439 KnownZero = ~1U; // All bits but the low one are known to be zero.
8447 /// getConstraintType - Given a constraint, return the type of
8448 /// constraint it is for this target.
8449 PPCTargetLowering::ConstraintType
8450 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8451 if (Constraint.size() == 1) {
8452 switch (Constraint[0]) {
8459 return C_RegisterClass;
8461 // FIXME: While Z does indicate a memory constraint, it specifically
8462 // indicates an r+r address (used in conjunction with the 'y' modifier
8463 // in the replacement string). Currently, we're forcing the base
8464 // register to be r0 in the asm printer (which is interpreted as zero)
8465 // and forming the complete address in the second register. This is
8469 } else if (Constraint == "wc") { // individual CR bits.
8470 return C_RegisterClass;
8471 } else if (Constraint == "wa" || Constraint == "wd" ||
8472 Constraint == "wf" || Constraint == "ws") {
8473 return C_RegisterClass; // VSX registers.
8475 return TargetLowering::getConstraintType(Constraint);
8478 /// Examine constraint type and operand type and determine a weight value.
8479 /// This object must already have been set up with the operand type
8480 /// and the current alternative constraint selected.
8481 TargetLowering::ConstraintWeight
8482 PPCTargetLowering::getSingleConstraintMatchWeight(
8483 AsmOperandInfo &info, const char *constraint) const {
8484 ConstraintWeight weight = CW_Invalid;
8485 Value *CallOperandVal = info.CallOperandVal;
8486 // If we don't have a value, we can't do a match,
8487 // but allow it at the lowest weight.
8488 if (!CallOperandVal)
8490 Type *type = CallOperandVal->getType();
8492 // Look at the constraint type.
8493 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8494 return CW_Register; // an individual CR bit.
8495 else if ((StringRef(constraint) == "wa" ||
8496 StringRef(constraint) == "wd" ||
8497 StringRef(constraint) == "wf") &&
8500 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8503 switch (*constraint) {
8505 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8508 if (type->isIntegerTy())
8509 weight = CW_Register;
8512 if (type->isFloatTy())
8513 weight = CW_Register;
8516 if (type->isDoubleTy())
8517 weight = CW_Register;
8520 if (type->isVectorTy())
8521 weight = CW_Register;
8524 weight = CW_Register;
8533 std::pair<unsigned, const TargetRegisterClass*>
8534 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8536 if (Constraint.size() == 1) {
8537 // GCC RS6000 Constraint Letters
8538 switch (Constraint[0]) {
8540 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
8541 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8542 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8544 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
8545 return std::make_pair(0U, &PPC::G8RCRegClass);
8546 return std::make_pair(0U, &PPC::GPRCRegClass);
8548 if (VT == MVT::f32 || VT == MVT::i32)
8549 return std::make_pair(0U, &PPC::F4RCRegClass);
8550 if (VT == MVT::f64 || VT == MVT::i64)
8551 return std::make_pair(0U, &PPC::F8RCRegClass);
8554 return std::make_pair(0U, &PPC::VRRCRegClass);
8556 return std::make_pair(0U, &PPC::CRRCRegClass);
8558 } else if (Constraint == "wc") { // an individual CR bit.
8559 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8560 } else if (Constraint == "wa" || Constraint == "wd" ||
8561 Constraint == "wf") {
8562 return std::make_pair(0U, &PPC::VSRCRegClass);
8563 } else if (Constraint == "ws") {
8564 return std::make_pair(0U, &PPC::VSFRCRegClass);
8567 std::pair<unsigned, const TargetRegisterClass*> R =
8568 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8570 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8571 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8572 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8574 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8575 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8576 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
8577 PPC::GPRCRegClass.contains(R.first)) {
8578 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8579 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8580 PPC::sub_32, &PPC::G8RCRegClass),
8581 &PPC::G8RCRegClass);
8588 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8589 /// vector. If it is invalid, don't add anything to Ops.
8590 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8591 std::string &Constraint,
8592 std::vector<SDValue>&Ops,
8593 SelectionDAG &DAG) const {
8596 // Only support length 1 constraints.
8597 if (Constraint.length() > 1) return;
8599 char Letter = Constraint[0];
8610 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8611 if (!CST) return; // Must be an immediate to match.
8612 unsigned Value = CST->getZExtValue();
8614 default: llvm_unreachable("Unknown constraint letter!");
8615 case 'I': // "I" is a signed 16-bit constant.
8616 if ((short)Value == (int)Value)
8617 Result = DAG.getTargetConstant(Value, Op.getValueType());
8619 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8620 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8621 if ((short)Value == 0)
8622 Result = DAG.getTargetConstant(Value, Op.getValueType());
8624 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8625 if ((Value >> 16) == 0)
8626 Result = DAG.getTargetConstant(Value, Op.getValueType());
8628 case 'M': // "M" is a constant that is greater than 31.
8630 Result = DAG.getTargetConstant(Value, Op.getValueType());
8632 case 'N': // "N" is a positive constant that is an exact power of two.
8633 if ((int)Value > 0 && isPowerOf2_32(Value))
8634 Result = DAG.getTargetConstant(Value, Op.getValueType());
8636 case 'O': // "O" is the constant zero.
8638 Result = DAG.getTargetConstant(Value, Op.getValueType());
8640 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8641 if ((short)-Value == (int)-Value)
8642 Result = DAG.getTargetConstant(Value, Op.getValueType());
8649 if (Result.getNode()) {
8650 Ops.push_back(Result);
8654 // Handle standard constraint letters.
8655 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8658 // isLegalAddressingMode - Return true if the addressing mode represented
8659 // by AM is legal for this target, for a load/store of the specified type.
8660 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8662 // FIXME: PPC does not allow r+i addressing modes for vectors!
8664 // PPC allows a sign-extended 16-bit immediate field.
8665 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8668 // No global is ever allowed as a base.
8672 // PPC only support r+r,
8674 case 0: // "r+i" or just "i", depending on HasBaseReg.
8677 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8679 // Otherwise we have r+r or r+i.
8682 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8684 // Allow 2*r as r+r.
8687 // No other scales are supported.
8694 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8695 SelectionDAG &DAG) const {
8696 MachineFunction &MF = DAG.getMachineFunction();
8697 MachineFrameInfo *MFI = MF.getFrameInfo();
8698 MFI->setReturnAddressIsTaken(true);
8700 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8704 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8706 // Make sure the function does not optimize away the store of the RA to
8708 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8709 FuncInfo->setLRStoreRequired();
8710 bool isPPC64 = PPCSubTarget.isPPC64();
8711 bool isDarwinABI = PPCSubTarget.isDarwinABI();
8714 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8717 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8718 isPPC64? MVT::i64 : MVT::i32);
8719 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8720 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8722 MachinePointerInfo(), false, false, false, 0);
8725 // Just load the return address off the stack.
8726 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8727 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8728 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8731 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8732 SelectionDAG &DAG) const {
8734 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8736 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8737 bool isPPC64 = PtrVT == MVT::i64;
8739 MachineFunction &MF = DAG.getMachineFunction();
8740 MachineFrameInfo *MFI = MF.getFrameInfo();
8741 MFI->setFrameAddressIsTaken(true);
8743 // Naked functions never have a frame pointer, and so we use r1. For all
8744 // other functions, this decision must be delayed until during PEI.
8746 if (MF.getFunction()->getAttributes().hasAttribute(
8747 AttributeSet::FunctionIndex, Attribute::Naked))
8748 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8750 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8752 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8755 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8756 FrameAddr, MachinePointerInfo(), false, false,
8761 // FIXME? Maybe this could be a TableGen attribute on some registers and
8762 // this table could be generated automatically from RegInfo.
8763 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8765 bool isPPC64 = PPCSubTarget.isPPC64();
8766 bool isDarwinABI = PPCSubTarget.isDarwinABI();
8768 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8769 (!isPPC64 && VT != MVT::i32))
8770 report_fatal_error("Invalid register global variable type");
8772 bool is64Bit = isPPC64 && VT == MVT::i64;
8773 unsigned Reg = StringSwitch<unsigned>(RegName)
8774 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8775 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8776 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8777 (is64Bit ? PPC::X13 : PPC::R13))
8782 report_fatal_error("Invalid register name global variable");
8786 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8787 // The PowerPC target isn't yet aware of offsets.
8791 /// getOptimalMemOpType - Returns the target specific optimal type for load
8792 /// and store operations as a result of memset, memcpy, and memmove
8793 /// lowering. If DstAlign is zero that means it's safe to destination
8794 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8795 /// means there isn't a need to check it against alignment requirement,
8796 /// probably because the source does not need to be loaded. If 'IsMemset' is
8797 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8798 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8799 /// source is constant so it does not need to be loaded.
8800 /// It returns EVT::Other if the type should be determined using generic
8801 /// target-independent logic.
8802 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8803 unsigned DstAlign, unsigned SrcAlign,
8804 bool IsMemset, bool ZeroMemset,
8806 MachineFunction &MF) const {
8807 if (this->PPCSubTarget.isPPC64()) {
8814 /// \brief Returns true if it is beneficial to convert a load of a constant
8815 /// to just the constant itself.
8816 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8818 assert(Ty->isIntegerTy());
8820 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8821 if (BitSize == 0 || BitSize > 64)
8826 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8827 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8829 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8830 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8831 return NumBits1 == 64 && NumBits2 == 32;
8834 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8835 if (!VT1.isInteger() || !VT2.isInteger())
8837 unsigned NumBits1 = VT1.getSizeInBits();
8838 unsigned NumBits2 = VT2.getSizeInBits();
8839 return NumBits1 == 64 && NumBits2 == 32;
8842 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8843 return isInt<16>(Imm) || isUInt<16>(Imm);
8846 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8847 return isInt<16>(Imm) || isUInt<16>(Imm);
8850 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8853 if (DisablePPCUnaligned)
8856 // PowerPC supports unaligned memory access for simple non-vector types.
8857 // Although accessing unaligned addresses is not as efficient as accessing
8858 // aligned addresses, it is generally more efficient than manual expansion,
8859 // and generally only traps for software emulation when crossing page
8865 if (VT.getSimpleVT().isVector()) {
8866 if (PPCSubTarget.hasVSX()) {
8867 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8874 if (VT == MVT::ppcf128)
8883 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8884 VT = VT.getScalarType();
8889 switch (VT.getSimpleVT().SimpleTy) {
8901 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
8902 EVT VT , unsigned DefinedValues) const {
8903 if (VT == MVT::v2i64)
8906 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
8909 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
8910 if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
8911 return TargetLowering::getSchedulingPreference(N);
8916 // Create a fast isel object.
8918 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
8919 const TargetLibraryInfo *LibInfo) const {
8920 return PPC::createFastISel(FuncInfo, LibInfo);