1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Constants.h"
29 #include "llvm/Function.h"
30 #include "llvm/Intrinsics.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Target/TargetOptions.h"
33 #include "llvm/Support/CommandLine.h"
36 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
37 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
40 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
41 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
45 // Use _setjmp/_longjmp instead of setjmp/longjmp.
46 setUseUnderscoreSetJmp(true);
47 setUseUnderscoreLongJmp(true);
49 // Set up the register classes.
50 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
51 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
52 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
54 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
55 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Expand);
56 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
58 // PowerPC does not have truncstore for i1.
59 setStoreXAction(MVT::i1, Promote);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
76 // PowerPC has no intrinsics for these particular operations
77 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
78 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
79 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
81 // PowerPC has no SREM/UREM instructions
82 setOperationAction(ISD::SREM, MVT::i32, Expand);
83 setOperationAction(ISD::UREM, MVT::i32, Expand);
84 setOperationAction(ISD::SREM, MVT::i64, Expand);
85 setOperationAction(ISD::UREM, MVT::i64, Expand);
87 // We don't support sin/cos/sqrt/fmod
88 setOperationAction(ISD::FSIN , MVT::f64, Expand);
89 setOperationAction(ISD::FCOS , MVT::f64, Expand);
90 setOperationAction(ISD::FREM , MVT::f64, Expand);
91 setOperationAction(ISD::FSIN , MVT::f32, Expand);
92 setOperationAction(ISD::FCOS , MVT::f32, Expand);
93 setOperationAction(ISD::FREM , MVT::f32, Expand);
95 // If we're enabling GP optimizations, use hardware square root
96 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
97 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
98 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
101 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
102 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
104 // PowerPC does not have BSWAP, CTPOP or CTTZ
105 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
106 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
107 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
108 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
109 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
110 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
112 // PowerPC does not have ROTR
113 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
115 // PowerPC does not have Select
116 setOperationAction(ISD::SELECT, MVT::i32, Expand);
117 setOperationAction(ISD::SELECT, MVT::i64, Expand);
118 setOperationAction(ISD::SELECT, MVT::f32, Expand);
119 setOperationAction(ISD::SELECT, MVT::f64, Expand);
121 // PowerPC wants to turn select_cc of FP into fsel when possible.
122 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
123 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
125 // PowerPC wants to optimize integer setcc a bit
126 setOperationAction(ISD::SETCC, MVT::i32, Custom);
128 // PowerPC does not have BRCOND which requires SetCC
129 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
131 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
133 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
134 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
136 // PowerPC does not have [U|S]INT_TO_FP
137 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
138 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
140 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
141 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
142 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
143 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
145 // We cannot sextinreg(i1). Expand to shifts.
146 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
148 // Support label based line numbers.
149 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
150 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
151 if (!TM.getSubtarget<PPCSubtarget>().isDarwin()) {
152 setOperationAction(ISD::LABEL, MVT::Other, Expand);
154 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
155 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
156 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
157 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
160 // We want to legalize GlobalAddress and ConstantPool nodes into the
161 // appropriate instructions to materialize the address.
162 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
163 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
164 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
165 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
166 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
167 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
168 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
169 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
171 // RET must be custom lowered, to meet ABI requirements
172 setOperationAction(ISD::RET , MVT::Other, Custom);
174 setOperationAction(ISD::ADJUST_TRAMP, MVT::i32, Expand);
175 setOperationAction(ISD::ADJUST_TRAMP, MVT::i64, Expand);
177 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
178 setOperationAction(ISD::VASTART , MVT::Other, Custom);
180 // VAARG is custom lowered with ELF 32 ABI
181 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
182 setOperationAction(ISD::VAARG, MVT::Other, Custom);
184 setOperationAction(ISD::VAARG, MVT::Other, Expand);
186 // Use the default implementation.
187 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
188 setOperationAction(ISD::VAEND , MVT::Other, Expand);
189 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
190 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
191 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
192 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
194 // We want to custom lower some of our intrinsics.
195 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
197 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
198 // They also have instructions for converting between i64 and fp.
199 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
200 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
201 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
202 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
203 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
205 // FIXME: disable this lowered code. This generates 64-bit register values,
206 // and we don't model the fact that the top part is clobbered by calls. We
207 // need to flag these together so that the value isn't live across a call.
208 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
210 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
211 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
213 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
214 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
217 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
218 // 64 bit PowerPC implementations can support i64 types directly
219 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
220 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
221 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
223 // 32 bit PowerPC wants to expand i64 shifts itself.
224 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
225 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
226 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
229 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
230 // First set operation action for all vector types to expand. Then we
231 // will selectively turn on ones that can be effectively codegen'd.
232 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
233 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
234 // add/sub are legal for all supported vector VT's.
235 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
236 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
238 // We promote all shuffles to v16i8.
239 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
240 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
242 // We promote all non-typed operations to v4i32.
243 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
244 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
245 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
246 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
247 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
248 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
249 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
250 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
251 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
252 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
253 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
254 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
256 // No other operations are legal.
257 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
258 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
259 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
260 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
261 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
262 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
263 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
264 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
265 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
266 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
268 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
271 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
272 // with merges, splats, etc.
273 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
275 setOperationAction(ISD::AND , MVT::v4i32, Legal);
276 setOperationAction(ISD::OR , MVT::v4i32, Legal);
277 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
278 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
279 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
280 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
282 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
283 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
284 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
285 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
287 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
288 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
289 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
290 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
292 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
293 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
295 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
296 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
297 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
298 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
301 setSetCCResultType(MVT::i32);
302 setShiftAmountType(MVT::i32);
303 setSetCCResultContents(ZeroOrOneSetCCResult);
305 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
306 setStackPointerRegisterToSaveRestore(PPC::X1);
307 setExceptionPointerRegister(PPC::X3);
308 setExceptionSelectorRegister(PPC::X4);
310 setStackPointerRegisterToSaveRestore(PPC::R1);
311 setExceptionPointerRegister(PPC::R3);
312 setExceptionSelectorRegister(PPC::R4);
315 // We have target-specific dag combine patterns for the following nodes:
316 setTargetDAGCombine(ISD::SINT_TO_FP);
317 setTargetDAGCombine(ISD::STORE);
318 setTargetDAGCombine(ISD::BR_CC);
319 setTargetDAGCombine(ISD::BSWAP);
321 computeRegisterProperties();
324 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
327 case PPCISD::FSEL: return "PPCISD::FSEL";
328 case PPCISD::FCFID: return "PPCISD::FCFID";
329 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
330 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
331 case PPCISD::STFIWX: return "PPCISD::STFIWX";
332 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
333 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
334 case PPCISD::VPERM: return "PPCISD::VPERM";
335 case PPCISD::Hi: return "PPCISD::Hi";
336 case PPCISD::Lo: return "PPCISD::Lo";
337 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
338 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
339 case PPCISD::SRL: return "PPCISD::SRL";
340 case PPCISD::SRA: return "PPCISD::SRA";
341 case PPCISD::SHL: return "PPCISD::SHL";
342 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
343 case PPCISD::STD_32: return "PPCISD::STD_32";
344 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
345 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
346 case PPCISD::MTCTR: return "PPCISD::MTCTR";
347 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
348 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
349 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
350 case PPCISD::MFCR: return "PPCISD::MFCR";
351 case PPCISD::VCMP: return "PPCISD::VCMP";
352 case PPCISD::VCMPo: return "PPCISD::VCMPo";
353 case PPCISD::LBRX: return "PPCISD::LBRX";
354 case PPCISD::STBRX: return "PPCISD::STBRX";
355 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
359 //===----------------------------------------------------------------------===//
360 // Node matching predicates, for use by the tblgen matching code.
361 //===----------------------------------------------------------------------===//
363 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
364 static bool isFloatingPointZero(SDOperand Op) {
365 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
366 return CFP->getValueAPF().isZero();
367 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
368 // Maybe this has already been legalized into the constant pool?
369 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
370 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
371 return CFP->getValueAPF().isZero();
376 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
377 /// true if Op is undef or if it matches the specified value.
378 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
379 return Op.getOpcode() == ISD::UNDEF ||
380 cast<ConstantSDNode>(Op)->getValue() == Val;
383 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
384 /// VPKUHUM instruction.
385 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
387 for (unsigned i = 0; i != 16; ++i)
388 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
391 for (unsigned i = 0; i != 8; ++i)
392 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
393 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
399 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
400 /// VPKUWUM instruction.
401 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
403 for (unsigned i = 0; i != 16; i += 2)
404 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
405 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
408 for (unsigned i = 0; i != 8; i += 2)
409 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
410 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
411 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
412 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
418 /// isVMerge - Common function, used to match vmrg* shuffles.
420 static bool isVMerge(SDNode *N, unsigned UnitSize,
421 unsigned LHSStart, unsigned RHSStart) {
422 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
423 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
424 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
425 "Unsupported merge size!");
427 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
428 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
429 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
430 LHSStart+j+i*UnitSize) ||
431 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
432 RHSStart+j+i*UnitSize))
438 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
439 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
440 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
442 return isVMerge(N, UnitSize, 8, 24);
443 return isVMerge(N, UnitSize, 8, 8);
446 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
447 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
448 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
450 return isVMerge(N, UnitSize, 0, 16);
451 return isVMerge(N, UnitSize, 0, 0);
455 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
456 /// amount, otherwise return -1.
457 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
458 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
459 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
460 // Find the first non-undef value in the shuffle mask.
462 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
465 if (i == 16) return -1; // all undef.
467 // Otherwise, check to see if the rest of the elements are consequtively
468 // numbered from this value.
469 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
470 if (ShiftAmt < i) return -1;
474 // Check the rest of the elements to see if they are consequtive.
475 for (++i; i != 16; ++i)
476 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
479 // Check the rest of the elements to see if they are consequtive.
480 for (++i; i != 16; ++i)
481 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
488 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
489 /// specifies a splat of a single element that is suitable for input to
490 /// VSPLTB/VSPLTH/VSPLTW.
491 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
492 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
493 N->getNumOperands() == 16 &&
494 (EltSize == 1 || EltSize == 2 || EltSize == 4));
496 // This is a splat operation if each element of the permute is the same, and
497 // if the value doesn't reference the second vector.
498 unsigned ElementBase = 0;
499 SDOperand Elt = N->getOperand(0);
500 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
501 ElementBase = EltV->getValue();
503 return false; // FIXME: Handle UNDEF elements too!
505 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
508 // Check that they are consequtive.
509 for (unsigned i = 1; i != EltSize; ++i) {
510 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
511 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
515 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
516 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
517 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
518 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
519 "Invalid VECTOR_SHUFFLE mask!");
520 for (unsigned j = 0; j != EltSize; ++j)
521 if (N->getOperand(i+j) != N->getOperand(j))
528 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
530 bool PPC::isAllNegativeZeroVector(SDNode *N) {
531 assert(N->getOpcode() == ISD::BUILD_VECTOR);
532 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
533 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
534 return CFP->getValueAPF().isNegZero();
538 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
539 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
540 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
541 assert(isSplatShuffleMask(N, EltSize));
542 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
545 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
546 /// by using a vspltis[bhw] instruction of the specified element size, return
547 /// the constant being splatted. The ByteSize field indicates the number of
548 /// bytes of each element [124] -> [bhw].
549 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
550 SDOperand OpVal(0, 0);
552 // If ByteSize of the splat is bigger than the element size of the
553 // build_vector, then we have a case where we are checking for a splat where
554 // multiple elements of the buildvector are folded together into a single
555 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
556 unsigned EltSize = 16/N->getNumOperands();
557 if (EltSize < ByteSize) {
558 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
559 SDOperand UniquedVals[4];
560 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
562 // See if all of the elements in the buildvector agree across.
563 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
564 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
565 // If the element isn't a constant, bail fully out.
566 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
569 if (UniquedVals[i&(Multiple-1)].Val == 0)
570 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
571 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
572 return SDOperand(); // no match.
575 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
576 // either constant or undef values that are identical for each chunk. See
577 // if these chunks can form into a larger vspltis*.
579 // Check to see if all of the leading entries are either 0 or -1. If
580 // neither, then this won't fit into the immediate field.
581 bool LeadingZero = true;
582 bool LeadingOnes = true;
583 for (unsigned i = 0; i != Multiple-1; ++i) {
584 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
586 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
587 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
589 // Finally, check the least significant entry.
591 if (UniquedVals[Multiple-1].Val == 0)
592 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
593 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
595 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
598 if (UniquedVals[Multiple-1].Val == 0)
599 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
600 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
601 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
602 return DAG.getTargetConstant(Val, MVT::i32);
608 // Check to see if this buildvec has a single non-undef value in its elements.
609 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
610 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
612 OpVal = N->getOperand(i);
613 else if (OpVal != N->getOperand(i))
617 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
619 unsigned ValSizeInBytes = 0;
621 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
622 Value = CN->getValue();
623 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
624 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
625 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
626 Value = FloatToBits(CN->getValueAPF().convertToFloat());
630 // If the splat value is larger than the element value, then we can never do
631 // this splat. The only case that we could fit the replicated bits into our
632 // immediate field for would be zero, and we prefer to use vxor for it.
633 if (ValSizeInBytes < ByteSize) return SDOperand();
635 // If the element value is larger than the splat value, cut it in half and
636 // check to see if the two halves are equal. Continue doing this until we
637 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
638 while (ValSizeInBytes > ByteSize) {
639 ValSizeInBytes >>= 1;
641 // If the top half equals the bottom half, we're still ok.
642 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
643 (Value & ((1 << (8*ValSizeInBytes))-1)))
647 // Properly sign extend the value.
648 int ShAmt = (4-ByteSize)*8;
649 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
651 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
652 if (MaskVal == 0) return SDOperand();
654 // Finally, if this value fits in a 5 bit sext field, return it
655 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
656 return DAG.getTargetConstant(MaskVal, MVT::i32);
660 //===----------------------------------------------------------------------===//
661 // Addressing Mode Selection
662 //===----------------------------------------------------------------------===//
664 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
665 /// or 64-bit immediate, and if the value can be accurately represented as a
666 /// sign extension from a 16-bit value. If so, this returns true and the
668 static bool isIntS16Immediate(SDNode *N, short &Imm) {
669 if (N->getOpcode() != ISD::Constant)
672 Imm = (short)cast<ConstantSDNode>(N)->getValue();
673 if (N->getValueType(0) == MVT::i32)
674 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
676 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
678 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
679 return isIntS16Immediate(Op.Val, Imm);
683 /// SelectAddressRegReg - Given the specified addressed, check to see if it
684 /// can be represented as an indexed [r+r] operation. Returns false if it
685 /// can be more efficiently represented with [r+imm].
686 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
690 if (N.getOpcode() == ISD::ADD) {
691 if (isIntS16Immediate(N.getOperand(1), imm))
693 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
696 Base = N.getOperand(0);
697 Index = N.getOperand(1);
699 } else if (N.getOpcode() == ISD::OR) {
700 if (isIntS16Immediate(N.getOperand(1), imm))
701 return false; // r+i can fold it if we can.
703 // If this is an or of disjoint bitfields, we can codegen this as an add
704 // (for better address arithmetic) if the LHS and RHS of the OR are provably
706 uint64_t LHSKnownZero, LHSKnownOne;
707 uint64_t RHSKnownZero, RHSKnownOne;
708 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
711 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
712 // If all of the bits are known zero on the LHS or RHS, the add won't
714 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
715 Base = N.getOperand(0);
716 Index = N.getOperand(1);
725 /// Returns true if the address N can be represented by a base register plus
726 /// a signed 16-bit displacement [r+imm], and if it is not better
727 /// represented as reg+reg.
728 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
729 SDOperand &Base, SelectionDAG &DAG){
730 // If this can be more profitably realized as r+r, fail.
731 if (SelectAddressRegReg(N, Disp, Base, DAG))
734 if (N.getOpcode() == ISD::ADD) {
736 if (isIntS16Immediate(N.getOperand(1), imm)) {
737 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
738 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
739 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
741 Base = N.getOperand(0);
743 return true; // [r+i]
744 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
745 // Match LOAD (ADD (X, Lo(G))).
746 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
747 && "Cannot handle constant offsets yet!");
748 Disp = N.getOperand(1).getOperand(0); // The global address.
749 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
750 Disp.getOpcode() == ISD::TargetConstantPool ||
751 Disp.getOpcode() == ISD::TargetJumpTable);
752 Base = N.getOperand(0);
753 return true; // [&g+r]
755 } else if (N.getOpcode() == ISD::OR) {
757 if (isIntS16Immediate(N.getOperand(1), imm)) {
758 // If this is an or of disjoint bitfields, we can codegen this as an add
759 // (for better address arithmetic) if the LHS and RHS of the OR are
760 // provably disjoint.
761 uint64_t LHSKnownZero, LHSKnownOne;
762 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
763 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
764 // If all of the bits are known zero on the LHS or RHS, the add won't
766 Base = N.getOperand(0);
767 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
771 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
772 // Loading from a constant address.
774 // If this address fits entirely in a 16-bit sext immediate field, codegen
777 if (isIntS16Immediate(CN, Imm)) {
778 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
779 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
783 // Handle 32-bit sext immediates with LIS + addr mode.
784 if (CN->getValueType(0) == MVT::i32 ||
785 (int64_t)CN->getValue() == (int)CN->getValue()) {
786 int Addr = (int)CN->getValue();
788 // Otherwise, break this down into an LIS + disp.
789 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
791 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
792 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
793 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
798 Disp = DAG.getTargetConstant(0, getPointerTy());
799 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
800 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
803 return true; // [r+0]
806 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
807 /// represented as an indexed [r+r] operation.
808 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
811 // Check to see if we can easily represent this as an [r+r] address. This
812 // will fail if it thinks that the address is more profitably represented as
813 // reg+imm, e.g. where imm = 0.
814 if (SelectAddressRegReg(N, Base, Index, DAG))
817 // If the operand is an addition, always emit this as [r+r], since this is
818 // better (for code size, and execution, as the memop does the add for free)
819 // than emitting an explicit add.
820 if (N.getOpcode() == ISD::ADD) {
821 Base = N.getOperand(0);
822 Index = N.getOperand(1);
826 // Otherwise, do it the hard way, using R0 as the base register.
827 Base = DAG.getRegister(PPC::R0, N.getValueType());
832 /// SelectAddressRegImmShift - Returns true if the address N can be
833 /// represented by a base register plus a signed 14-bit displacement
834 /// [r+imm*4]. Suitable for use by STD and friends.
835 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
838 // If this can be more profitably realized as r+r, fail.
839 if (SelectAddressRegReg(N, Disp, Base, DAG))
842 if (N.getOpcode() == ISD::ADD) {
844 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
845 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
846 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
847 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
849 Base = N.getOperand(0);
851 return true; // [r+i]
852 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
853 // Match LOAD (ADD (X, Lo(G))).
854 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
855 && "Cannot handle constant offsets yet!");
856 Disp = N.getOperand(1).getOperand(0); // The global address.
857 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
858 Disp.getOpcode() == ISD::TargetConstantPool ||
859 Disp.getOpcode() == ISD::TargetJumpTable);
860 Base = N.getOperand(0);
861 return true; // [&g+r]
863 } else if (N.getOpcode() == ISD::OR) {
865 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
866 // If this is an or of disjoint bitfields, we can codegen this as an add
867 // (for better address arithmetic) if the LHS and RHS of the OR are
868 // provably disjoint.
869 uint64_t LHSKnownZero, LHSKnownOne;
870 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
871 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
872 // If all of the bits are known zero on the LHS or RHS, the add won't
874 Base = N.getOperand(0);
875 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
879 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
880 // Loading from a constant address. Verify low two bits are clear.
881 if ((CN->getValue() & 3) == 0) {
882 // If this address fits entirely in a 14-bit sext immediate field, codegen
885 if (isIntS16Immediate(CN, Imm)) {
886 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
887 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
891 // Fold the low-part of 32-bit absolute addresses into addr mode.
892 if (CN->getValueType(0) == MVT::i32 ||
893 (int64_t)CN->getValue() == (int)CN->getValue()) {
894 int Addr = (int)CN->getValue();
896 // Otherwise, break this down into an LIS + disp.
897 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
899 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
900 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
901 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
907 Disp = DAG.getTargetConstant(0, getPointerTy());
908 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
909 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
912 return true; // [r+0]
916 /// getPreIndexedAddressParts - returns true by value, base pointer and
917 /// offset pointer and addressing mode by reference if the node's address
918 /// can be legally represented as pre-indexed load / store address.
919 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
921 ISD::MemIndexedMode &AM,
923 // Disabled by default for now.
924 if (!EnablePPCPreinc) return false;
928 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
929 Ptr = LD->getBasePtr();
930 VT = LD->getLoadedVT();
932 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
934 Ptr = ST->getBasePtr();
935 VT = ST->getStoredVT();
939 // PowerPC doesn't have preinc load/store instructions for vectors.
940 if (MVT::isVector(VT))
943 // TODO: Check reg+reg first.
945 // LDU/STU use reg+imm*4, others use reg+imm.
946 if (VT != MVT::i64) {
948 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
952 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
956 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
957 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
958 // sext i32 to i64 when addr mode is r+i.
959 if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 &&
960 LD->getExtensionType() == ISD::SEXTLOAD &&
961 isa<ConstantSDNode>(Offset))
969 //===----------------------------------------------------------------------===//
970 // LowerOperation implementation
971 //===----------------------------------------------------------------------===//
973 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
974 MVT::ValueType PtrVT = Op.getValueType();
975 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
976 Constant *C = CP->getConstVal();
977 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
978 SDOperand Zero = DAG.getConstant(0, PtrVT);
980 const TargetMachine &TM = DAG.getTarget();
982 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
983 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
985 // If this is a non-darwin platform, we don't support non-static relo models
987 if (TM.getRelocationModel() == Reloc::Static ||
988 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
989 // Generate non-pic code that has direct accesses to the constant pool.
990 // The address of the global is just (hi(&g)+lo(&g)).
991 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
994 if (TM.getRelocationModel() == Reloc::PIC_) {
995 // With PIC, the first instruction is actually "GR+hi(&G)".
996 Hi = DAG.getNode(ISD::ADD, PtrVT,
997 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1000 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1004 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1005 MVT::ValueType PtrVT = Op.getValueType();
1006 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1007 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1008 SDOperand Zero = DAG.getConstant(0, PtrVT);
1010 const TargetMachine &TM = DAG.getTarget();
1012 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1013 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1015 // If this is a non-darwin platform, we don't support non-static relo models
1017 if (TM.getRelocationModel() == Reloc::Static ||
1018 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1019 // Generate non-pic code that has direct accesses to the constant pool.
1020 // The address of the global is just (hi(&g)+lo(&g)).
1021 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1024 if (TM.getRelocationModel() == Reloc::PIC_) {
1025 // With PIC, the first instruction is actually "GR+hi(&G)".
1026 Hi = DAG.getNode(ISD::ADD, PtrVT,
1027 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1030 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1034 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1035 assert(0 && "TLS not implemented for PPC.");
1038 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1039 MVT::ValueType PtrVT = Op.getValueType();
1040 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1041 GlobalValue *GV = GSDN->getGlobal();
1042 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1043 SDOperand Zero = DAG.getConstant(0, PtrVT);
1045 const TargetMachine &TM = DAG.getTarget();
1047 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1048 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1050 // If this is a non-darwin platform, we don't support non-static relo models
1052 if (TM.getRelocationModel() == Reloc::Static ||
1053 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1054 // Generate non-pic code that has direct accesses to globals.
1055 // The address of the global is just (hi(&g)+lo(&g)).
1056 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1059 if (TM.getRelocationModel() == Reloc::PIC_) {
1060 // With PIC, the first instruction is actually "GR+hi(&G)".
1061 Hi = DAG.getNode(ISD::ADD, PtrVT,
1062 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1065 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1067 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1070 // If the global is weak or external, we have to go through the lazy
1072 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1075 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1076 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1078 // If we're comparing for equality to zero, expose the fact that this is
1079 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1080 // fold the new nodes.
1081 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1082 if (C->isNullValue() && CC == ISD::SETEQ) {
1083 MVT::ValueType VT = Op.getOperand(0).getValueType();
1084 SDOperand Zext = Op.getOperand(0);
1085 if (VT < MVT::i32) {
1087 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1089 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1090 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1091 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1092 DAG.getConstant(Log2b, MVT::i32));
1093 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1095 // Leave comparisons against 0 and -1 alone for now, since they're usually
1096 // optimized. FIXME: revisit this when we can custom lower all setcc
1098 if (C->isAllOnesValue() || C->isNullValue())
1102 // If we have an integer seteq/setne, turn it into a compare against zero
1103 // by xor'ing the rhs with the lhs, which is faster than setting a
1104 // condition register, reading it back out, and masking the correct bit. The
1105 // normal approach here uses sub to do this instead of xor. Using xor exposes
1106 // the result to other bit-twiddling opportunities.
1107 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1108 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1109 MVT::ValueType VT = Op.getValueType();
1110 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1112 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1117 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1118 int VarArgsFrameIndex,
1119 int VarArgsStackOffset,
1120 unsigned VarArgsNumGPR,
1121 unsigned VarArgsNumFPR,
1122 const PPCSubtarget &Subtarget) {
1124 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1127 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1128 int VarArgsFrameIndex,
1129 int VarArgsStackOffset,
1130 unsigned VarArgsNumGPR,
1131 unsigned VarArgsNumFPR,
1132 const PPCSubtarget &Subtarget) {
1134 if (Subtarget.isMachoABI()) {
1135 // vastart just stores the address of the VarArgsFrameIndex slot into the
1136 // memory location argument.
1137 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1138 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1139 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1140 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV->getValue(),
1144 // For ELF 32 ABI we follow the layout of the va_list struct.
1145 // We suppose the given va_list is already allocated.
1148 // char gpr; /* index into the array of 8 GPRs
1149 // * stored in the register save area
1150 // * gpr=0 corresponds to r3,
1151 // * gpr=1 to r4, etc.
1153 // char fpr; /* index into the array of 8 FPRs
1154 // * stored in the register save area
1155 // * fpr=0 corresponds to f1,
1156 // * fpr=1 to f2, etc.
1158 // char *overflow_arg_area;
1159 // /* location on stack that holds
1160 // * the next overflow argument
1162 // char *reg_save_area;
1163 // /* where r3:r10 and f1:f8 (if saved)
1169 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1170 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1173 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1175 SDOperand StackOffset = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1176 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1178 SDOperand ConstFrameOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8,
1180 SDOperand ConstStackOffset = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8 - 1,
1182 SDOperand ConstFPROffset = DAG.getConstant(1, PtrVT);
1184 SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
1186 // Store first byte : number of int regs
1187 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1188 Op.getOperand(1), SV->getValue(),
1190 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1193 // Store second byte : number of float regs
1194 SDOperand secondStore = DAG.getStore(firstStore, ArgFPR, nextPtr,
1195 SV->getValue(), SV->getOffset());
1196 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1198 // Store second word : arguments given on stack
1199 SDOperand thirdStore = DAG.getStore(secondStore, StackOffset, nextPtr,
1200 SV->getValue(), SV->getOffset());
1201 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1203 // Store third word : arguments given in registers
1204 return DAG.getStore(thirdStore, FR, nextPtr, SV->getValue(),
1209 #include "PPCGenCallingConv.inc"
1211 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1212 /// depending on which subtarget is selected.
1213 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1214 if (Subtarget.isMachoABI()) {
1215 static const unsigned FPR[] = {
1216 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1217 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1223 static const unsigned FPR[] = {
1224 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1230 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1231 int &VarArgsFrameIndex,
1232 int &VarArgsStackOffset,
1233 unsigned &VarArgsNumGPR,
1234 unsigned &VarArgsNumFPR,
1235 const PPCSubtarget &Subtarget) {
1236 // TODO: add description of PPC stack frame format, or at least some docs.
1238 MachineFunction &MF = DAG.getMachineFunction();
1239 MachineFrameInfo *MFI = MF.getFrameInfo();
1240 SSARegMap *RegMap = MF.getSSARegMap();
1241 SmallVector<SDOperand, 8> ArgValues;
1242 SDOperand Root = Op.getOperand(0);
1244 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1245 bool isPPC64 = PtrVT == MVT::i64;
1246 bool isMachoABI = Subtarget.isMachoABI();
1247 bool isELF32_ABI = Subtarget.isELF32_ABI();
1248 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1250 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1252 static const unsigned GPR_32[] = { // 32-bit registers.
1253 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1254 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1256 static const unsigned GPR_64[] = { // 64-bit registers.
1257 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1258 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1261 static const unsigned *FPR = GetFPR(Subtarget);
1263 static const unsigned VR[] = {
1264 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1265 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1268 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1269 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1270 const unsigned Num_VR_Regs = array_lengthof( VR);
1272 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1274 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1276 // Add DAG nodes to load the arguments or copy them out of registers. On
1277 // entry to a function on PPC, the arguments start after the linkage area,
1278 // although the first ones are often in registers.
1280 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1281 // represented with two words (long long or double) must be copied to an
1282 // even GPR_idx value or to an even ArgOffset value.
1284 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1286 bool needsLoad = false;
1287 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1288 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1289 unsigned ArgSize = ObjSize;
1290 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1291 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1292 // See if next argument requires stack alignment in ELF
1293 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1294 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1295 (!(Flags & AlignFlag)));
1297 unsigned CurArgOffset = ArgOffset;
1299 default: assert(0 && "Unhandled argument type!");
1301 // Double word align in ELF
1302 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1303 if (GPR_idx != Num_GPR_Regs) {
1304 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1305 MF.addLiveIn(GPR[GPR_idx], VReg);
1306 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1310 ArgSize = PtrByteSize;
1312 // Stack align in ELF
1313 if (needsLoad && Expand && isELF32_ABI)
1314 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1315 // All int arguments reserve stack space in Macho ABI.
1316 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1319 case MVT::i64: // PPC64
1320 if (GPR_idx != Num_GPR_Regs) {
1321 unsigned VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1322 MF.addLiveIn(GPR[GPR_idx], VReg);
1323 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1328 // All int arguments reserve stack space in Macho ABI.
1329 if (isMachoABI || needsLoad) ArgOffset += 8;
1334 // Every 4 bytes of argument space consumes one of the GPRs available for
1335 // argument passing.
1336 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1338 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1341 if (FPR_idx != Num_FPR_Regs) {
1343 if (ObjectVT == MVT::f32)
1344 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1346 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1347 MF.addLiveIn(FPR[FPR_idx], VReg);
1348 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1354 // Stack align in ELF
1355 if (needsLoad && Expand && isELF32_ABI)
1356 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1357 // All FP arguments reserve stack space in Macho ABI.
1358 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1364 // Note that vector arguments in registers don't reserve stack space.
1365 if (VR_idx != Num_VR_Regs) {
1366 unsigned VReg = RegMap->createVirtualRegister(&PPC::VRRCRegClass);
1367 MF.addLiveIn(VR[VR_idx], VReg);
1368 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1371 // This should be simple, but requires getting 16-byte aligned stack
1373 assert(0 && "Loading VR argument not implemented yet!");
1379 // We need to load the argument to a virtual register if we determined above
1380 // that we ran out of physical registers of the appropriate type
1382 // If the argument is actually used, emit a load from the right stack
1384 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1385 int FI = MFI->CreateFixedObject(ObjSize,
1386 CurArgOffset + (ArgSize - ObjSize));
1387 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1388 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1390 // Don't emit a dead load.
1391 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1395 ArgValues.push_back(ArgVal);
1398 // If the function takes variable number of arguments, make a frame index for
1399 // the start of the first vararg value... for expansion of llvm.va_start.
1400 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1405 VarArgsNumGPR = GPR_idx;
1406 VarArgsNumFPR = FPR_idx;
1408 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1410 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1411 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1412 MVT::getSizeInBits(PtrVT)/8);
1414 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1421 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1423 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1425 SmallVector<SDOperand, 8> MemOps;
1427 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1428 // stored to the VarArgsFrameIndex on the stack.
1430 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1431 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1432 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1433 MemOps.push_back(Store);
1434 // Increment the address by four for the next argument to store
1435 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1436 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1440 // If this function is vararg, store any remaining integer argument regs
1441 // to their spots on the stack so that they may be loaded by deferencing the
1442 // result of va_next.
1443 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1446 VReg = RegMap->createVirtualRegister(&PPC::G8RCRegClass);
1448 VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1450 MF.addLiveIn(GPR[GPR_idx], VReg);
1451 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1452 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1453 MemOps.push_back(Store);
1454 // Increment the address by four for the next argument to store
1455 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1456 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1459 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1462 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1463 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1464 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1465 MemOps.push_back(Store);
1466 // Increment the address by eight for the next argument to store
1467 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1469 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1472 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1474 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1476 MF.addLiveIn(FPR[FPR_idx], VReg);
1477 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1478 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1479 MemOps.push_back(Store);
1480 // Increment the address by eight for the next argument to store
1481 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1483 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1487 if (!MemOps.empty())
1488 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1491 ArgValues.push_back(Root);
1493 // Return the new list of results.
1494 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1495 Op.Val->value_end());
1496 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1499 /// isCallCompatibleAddress - Return the immediate to use if the specified
1500 /// 32-bit value is representable in the immediate field of a BxA instruction.
1501 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1502 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1505 int Addr = C->getValue();
1506 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1507 (Addr << 6 >> 6) != Addr)
1508 return 0; // Top 6 bits have to be sext of immediate.
1510 return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
1514 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1515 const PPCSubtarget &Subtarget) {
1516 SDOperand Chain = Op.getOperand(0);
1517 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1518 SDOperand Callee = Op.getOperand(4);
1519 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1521 bool isMachoABI = Subtarget.isMachoABI();
1522 bool isELF32_ABI = Subtarget.isELF32_ABI();
1524 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1525 bool isPPC64 = PtrVT == MVT::i64;
1526 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1528 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1529 // SelectExpr to use to put the arguments in the appropriate registers.
1530 std::vector<SDOperand> args_to_use;
1532 // Count how many bytes are to be pushed on the stack, including the linkage
1533 // area, and parameter passing area. We start with 24/48 bytes, which is
1534 // prereserved space for [SP][CR][LR][3 x unused].
1535 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1537 // Add up all the space actually used.
1538 for (unsigned i = 0; i != NumOps; ++i) {
1539 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1540 ArgSize = std::max(ArgSize, PtrByteSize);
1541 NumBytes += ArgSize;
1544 // The prolog code of the callee may store up to 8 GPR argument registers to
1545 // the stack, allowing va_start to index over them in memory if its varargs.
1546 // Because we cannot tell if this is needed on the caller side, we have to
1547 // conservatively assume that it is needed. As such, make sure we have at
1548 // least enough stack space for the caller to store the 8 GPRs.
1549 NumBytes = std::max(NumBytes,
1550 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1552 // Adjust the stack pointer for the new arguments...
1553 // These operations are automatically eliminated by the prolog/epilog pass
1554 Chain = DAG.getCALLSEQ_START(Chain,
1555 DAG.getConstant(NumBytes, PtrVT));
1557 // Set up a copy of the stack pointer for use loading and storing any
1558 // arguments that may not fit in the registers available for argument
1562 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1564 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1566 // Figure out which arguments are going to go in registers, and which in
1567 // memory. Also, if this is a vararg function, floating point operations
1568 // must be stored to our stack, and loaded into integer regs as well, if
1569 // any integer regs are available for argument passing.
1570 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1571 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1573 static const unsigned GPR_32[] = { // 32-bit registers.
1574 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1575 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1577 static const unsigned GPR_64[] = { // 64-bit registers.
1578 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1579 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1581 static const unsigned *FPR = GetFPR(Subtarget);
1583 static const unsigned VR[] = {
1584 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1585 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1587 const unsigned NumGPRs = array_lengthof(GPR_32);
1588 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1589 const unsigned NumVRs = array_lengthof( VR);
1591 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1593 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1594 SmallVector<SDOperand, 8> MemOpChains;
1595 for (unsigned i = 0; i != NumOps; ++i) {
1597 SDOperand Arg = Op.getOperand(5+2*i);
1598 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1599 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1600 // See if next argument requires stack alignment in ELF
1601 unsigned next = 5+2*(i+1)+1;
1602 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1603 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1604 (!(Flags & AlignFlag)));
1606 // PtrOff will be used to store the current argument to the stack if a
1607 // register cannot be found for it.
1610 // Stack align in ELF 32
1611 if (isELF32_ABI && Expand)
1612 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1613 StackPtr.getValueType());
1615 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1617 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1619 // On PPC64, promote integers to 64-bit values.
1620 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1621 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1623 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1626 switch (Arg.getValueType()) {
1627 default: assert(0 && "Unexpected ValueType for argument!");
1630 // Double word align in ELF
1631 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1632 if (GPR_idx != NumGPRs) {
1633 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1635 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1638 if (inMem || isMachoABI) {
1639 // Stack align in ELF
1640 if (isELF32_ABI && Expand)
1641 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1643 ArgOffset += PtrByteSize;
1649 // Float varargs need to be promoted to double.
1650 if (Arg.getValueType() == MVT::f32)
1651 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1654 if (FPR_idx != NumFPRs) {
1655 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1658 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1659 MemOpChains.push_back(Store);
1661 // Float varargs are always shadowed in available integer registers
1662 if (GPR_idx != NumGPRs) {
1663 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1664 MemOpChains.push_back(Load.getValue(1));
1665 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1668 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1669 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1670 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1671 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1672 MemOpChains.push_back(Load.getValue(1));
1673 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1677 // If we have any FPRs remaining, we may also have GPRs remaining.
1678 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1681 if (GPR_idx != NumGPRs)
1683 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1684 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1689 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1692 if (inMem || isMachoABI) {
1693 // Stack align in ELF
1694 if (isELF32_ABI && Expand)
1695 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1699 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1706 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1707 assert(VR_idx != NumVRs &&
1708 "Don't support passing more than 12 vector args yet!");
1709 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1713 if (!MemOpChains.empty())
1714 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1715 &MemOpChains[0], MemOpChains.size());
1717 // Build a sequence of copy-to-reg nodes chained together with token chain
1718 // and flag operands which copy the outgoing args into the appropriate regs.
1720 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1721 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1723 InFlag = Chain.getValue(1);
1726 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1727 if (isVarArg && isELF32_ABI) {
1728 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1729 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1730 InFlag = Chain.getValue(1);
1733 std::vector<MVT::ValueType> NodeTys;
1734 NodeTys.push_back(MVT::Other); // Returns a chain
1735 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1737 SmallVector<SDOperand, 8> Ops;
1738 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1740 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1741 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1742 // node so that legalize doesn't hack it.
1743 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1744 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1745 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1746 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1747 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1748 // If this is an absolute destination address, use the munged value.
1749 Callee = SDOperand(Dest, 0);
1751 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1752 // to do the call, we can't use PPCISD::CALL.
1753 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1754 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1755 InFlag = Chain.getValue(1);
1757 // Copy the callee address into R12 on darwin.
1759 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1760 InFlag = Chain.getValue(1);
1764 NodeTys.push_back(MVT::Other);
1765 NodeTys.push_back(MVT::Flag);
1766 Ops.push_back(Chain);
1767 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1771 // If this is a direct call, pass the chain and the callee.
1773 Ops.push_back(Chain);
1774 Ops.push_back(Callee);
1777 // Add argument registers to the end of the list so that they are known live
1779 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1780 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1781 RegsToPass[i].second.getValueType()));
1784 Ops.push_back(InFlag);
1785 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1786 InFlag = Chain.getValue(1);
1788 SDOperand ResultVals[3];
1789 unsigned NumResults = 0;
1792 // If the call has results, copy the values out of the ret val registers.
1793 switch (Op.Val->getValueType(0)) {
1794 default: assert(0 && "Unexpected ret value!");
1795 case MVT::Other: break;
1797 if (Op.Val->getValueType(1) == MVT::i32) {
1798 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1799 ResultVals[0] = Chain.getValue(0);
1800 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1801 Chain.getValue(2)).getValue(1);
1802 ResultVals[1] = Chain.getValue(0);
1804 NodeTys.push_back(MVT::i32);
1806 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1807 ResultVals[0] = Chain.getValue(0);
1810 NodeTys.push_back(MVT::i32);
1813 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1814 ResultVals[0] = Chain.getValue(0);
1816 NodeTys.push_back(MVT::i64);
1820 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1821 InFlag).getValue(1);
1822 ResultVals[0] = Chain.getValue(0);
1824 NodeTys.push_back(Op.Val->getValueType(0));
1830 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1831 InFlag).getValue(1);
1832 ResultVals[0] = Chain.getValue(0);
1834 NodeTys.push_back(Op.Val->getValueType(0));
1838 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1839 DAG.getConstant(NumBytes, PtrVT));
1840 NodeTys.push_back(MVT::Other);
1842 // If the function returns void, just return the chain.
1843 if (NumResults == 0)
1846 // Otherwise, merge everything together with a MERGE_VALUES node.
1847 ResultVals[NumResults++] = Chain;
1848 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1849 ResultVals, NumResults);
1850 return Res.getValue(Op.ResNo);
1853 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1854 SmallVector<CCValAssign, 16> RVLocs;
1855 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1856 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1857 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1858 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1860 // If this is the first return lowered for this function, add the regs to the
1861 // liveout set for the function.
1862 if (DAG.getMachineFunction().liveout_empty()) {
1863 for (unsigned i = 0; i != RVLocs.size(); ++i)
1864 DAG.getMachineFunction().addLiveOut(RVLocs[i].getLocReg());
1867 SDOperand Chain = Op.getOperand(0);
1870 // Copy the result values into the output registers.
1871 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1872 CCValAssign &VA = RVLocs[i];
1873 assert(VA.isRegLoc() && "Can only return in registers!");
1874 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1875 Flag = Chain.getValue(1);
1879 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1881 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1884 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1885 const PPCSubtarget &Subtarget) {
1886 // When we pop the dynamic allocation we need to restore the SP link.
1888 // Get the corect type for pointers.
1889 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1891 // Construct the stack pointer operand.
1892 bool IsPPC64 = Subtarget.isPPC64();
1893 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1894 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1896 // Get the operands for the STACKRESTORE.
1897 SDOperand Chain = Op.getOperand(0);
1898 SDOperand SaveSP = Op.getOperand(1);
1900 // Load the old link SP.
1901 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1903 // Restore the stack pointer.
1904 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1906 // Store the old link SP.
1907 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1910 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1911 const PPCSubtarget &Subtarget) {
1912 MachineFunction &MF = DAG.getMachineFunction();
1913 bool IsPPC64 = Subtarget.isPPC64();
1914 bool isMachoABI = Subtarget.isMachoABI();
1916 // Get current frame pointer save index. The users of this index will be
1917 // primarily DYNALLOC instructions.
1918 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1919 int FPSI = FI->getFramePointerSaveIndex();
1921 // If the frame pointer save index hasn't been defined yet.
1923 // Find out what the fix offset of the frame pointer save area.
1924 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1926 // Allocate the frame index for frame pointer save area.
1927 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1929 FI->setFramePointerSaveIndex(FPSI);
1933 SDOperand Chain = Op.getOperand(0);
1934 SDOperand Size = Op.getOperand(1);
1936 // Get the corect type for pointers.
1937 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1939 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
1940 DAG.getConstant(0, PtrVT), Size);
1941 // Construct a node for the frame pointer save index.
1942 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
1943 // Build a DYNALLOC node.
1944 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
1945 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
1946 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
1950 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
1952 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
1953 // Not FP? Not a fsel.
1954 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
1955 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
1958 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1960 // Cannot handle SETEQ/SETNE.
1961 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
1963 MVT::ValueType ResVT = Op.getValueType();
1964 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
1965 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
1966 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
1968 // If the RHS of the comparison is a 0.0, we don't need to do the
1969 // subtraction at all.
1970 if (isFloatingPointZero(RHS))
1972 default: break; // SETUO etc aren't handled by fsel.
1976 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1980 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1981 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1982 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
1986 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1990 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
1991 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
1992 return DAG.getNode(PPCISD::FSEL, ResVT,
1993 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
1998 default: break; // SETUO etc aren't handled by fsel.
2002 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2003 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2004 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2005 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2009 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2010 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2011 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2012 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2016 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2017 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2018 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2019 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2023 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2024 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2025 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2026 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2031 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2032 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2033 SDOperand Src = Op.getOperand(0);
2034 if (Src.getValueType() == MVT::f32)
2035 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2038 switch (Op.getValueType()) {
2039 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2041 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2044 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2048 // Convert the FP value to an int value through memory.
2049 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
2050 if (Op.getValueType() == MVT::i32)
2051 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
2055 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2056 if (Op.getOperand(0).getValueType() == MVT::i64) {
2057 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2058 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2059 if (Op.getValueType() == MVT::f32)
2060 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2064 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2065 "Unhandled SINT_TO_FP type in custom expander!");
2066 // Since we only generate this in 64-bit mode, we can take advantage of
2067 // 64-bit registers. In particular, sign extend the input value into the
2068 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2069 // then lfd it and fcfid it.
2070 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2071 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2072 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2073 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2075 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2078 // STD the extended value into the stack slot.
2079 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2080 DAG.getEntryNode(), Ext64, FIdx,
2081 DAG.getSrcValue(NULL));
2082 // Load the value as a double.
2083 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2085 // FCFID it and return it.
2086 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2087 if (Op.getValueType() == MVT::f32)
2088 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
2092 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2093 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2094 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2096 // Expand into a bunch of logical ops. Note that these ops
2097 // depend on the PPC behavior for oversized shift amounts.
2098 SDOperand Lo = Op.getOperand(0);
2099 SDOperand Hi = Op.getOperand(1);
2100 SDOperand Amt = Op.getOperand(2);
2102 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2103 DAG.getConstant(32, MVT::i32), Amt);
2104 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2105 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2106 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2107 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2108 DAG.getConstant(-32U, MVT::i32));
2109 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2110 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2111 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2112 SDOperand OutOps[] = { OutLo, OutHi };
2113 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2117 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2118 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2119 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2121 // Otherwise, expand into a bunch of logical ops. Note that these ops
2122 // depend on the PPC behavior for oversized shift amounts.
2123 SDOperand Lo = Op.getOperand(0);
2124 SDOperand Hi = Op.getOperand(1);
2125 SDOperand Amt = Op.getOperand(2);
2127 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2128 DAG.getConstant(32, MVT::i32), Amt);
2129 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2130 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2131 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2132 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2133 DAG.getConstant(-32U, MVT::i32));
2134 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2135 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2136 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2137 SDOperand OutOps[] = { OutLo, OutHi };
2138 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2142 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2143 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2144 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2146 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2147 SDOperand Lo = Op.getOperand(0);
2148 SDOperand Hi = Op.getOperand(1);
2149 SDOperand Amt = Op.getOperand(2);
2151 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2152 DAG.getConstant(32, MVT::i32), Amt);
2153 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2154 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2155 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2156 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2157 DAG.getConstant(-32U, MVT::i32));
2158 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2159 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2160 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2161 Tmp4, Tmp6, ISD::SETLE);
2162 SDOperand OutOps[] = { OutLo, OutHi };
2163 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2167 //===----------------------------------------------------------------------===//
2168 // Vector related lowering.
2171 // If this is a vector of constants or undefs, get the bits. A bit in
2172 // UndefBits is set if the corresponding element of the vector is an
2173 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2174 // zero. Return true if this is not an array of constants, false if it is.
2176 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2177 uint64_t UndefBits[2]) {
2178 // Start with zero'd results.
2179 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2181 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2182 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2183 SDOperand OpVal = BV->getOperand(i);
2185 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2186 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2188 uint64_t EltBits = 0;
2189 if (OpVal.getOpcode() == ISD::UNDEF) {
2190 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2191 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2193 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2194 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2195 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2196 assert(CN->getValueType(0) == MVT::f32 &&
2197 "Only one legal FP vector type!");
2198 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2200 // Nonconstant element.
2204 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2207 //printf("%llx %llx %llx %llx\n",
2208 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2212 // If this is a splat (repetition) of a value across the whole vector, return
2213 // the smallest size that splats it. For example, "0x01010101010101..." is a
2214 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2215 // SplatSize = 1 byte.
2216 static bool isConstantSplat(const uint64_t Bits128[2],
2217 const uint64_t Undef128[2],
2218 unsigned &SplatBits, unsigned &SplatUndef,
2219 unsigned &SplatSize) {
2221 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2222 // the same as the lower 64-bits, ignoring undefs.
2223 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2224 return false; // Can't be a splat if two pieces don't match.
2226 uint64_t Bits64 = Bits128[0] | Bits128[1];
2227 uint64_t Undef64 = Undef128[0] & Undef128[1];
2229 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2231 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2232 return false; // Can't be a splat if two pieces don't match.
2234 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2235 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2237 // If the top 16-bits are different than the lower 16-bits, ignoring
2238 // undefs, we have an i32 splat.
2239 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2241 SplatUndef = Undef32;
2246 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2247 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2249 // If the top 8-bits are different than the lower 8-bits, ignoring
2250 // undefs, we have an i16 splat.
2251 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2253 SplatUndef = Undef16;
2258 // Otherwise, we have an 8-bit splat.
2259 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2260 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2265 /// BuildSplatI - Build a canonical splati of Val with an element size of
2266 /// SplatSize. Cast the result to VT.
2267 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2268 SelectionDAG &DAG) {
2269 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2271 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2272 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2275 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2277 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2281 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2283 // Build a canonical splat for this value.
2284 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2285 SmallVector<SDOperand, 8> Ops;
2286 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2287 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2288 &Ops[0], Ops.size());
2289 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2292 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2293 /// specified intrinsic ID.
2294 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2296 MVT::ValueType DestVT = MVT::Other) {
2297 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2298 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2299 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2302 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2303 /// specified intrinsic ID.
2304 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2305 SDOperand Op2, SelectionDAG &DAG,
2306 MVT::ValueType DestVT = MVT::Other) {
2307 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2308 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2309 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2313 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2314 /// amount. The result has the specified value type.
2315 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2316 MVT::ValueType VT, SelectionDAG &DAG) {
2317 // Force LHS/RHS to be the right type.
2318 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2319 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2322 for (unsigned i = 0; i != 16; ++i)
2323 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2324 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2325 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2326 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2329 // If this is a case we can't handle, return null and let the default
2330 // expansion code take care of it. If we CAN select this case, and if it
2331 // selects to a single instruction, return Op. Otherwise, if we can codegen
2332 // this case more efficiently than a constant pool load, lower it to the
2333 // sequence of ops that should be used.
2334 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2335 // If this is a vector of constants or undefs, get the bits. A bit in
2336 // UndefBits is set if the corresponding element of the vector is an
2337 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2339 uint64_t VectorBits[2];
2340 uint64_t UndefBits[2];
2341 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2342 return SDOperand(); // Not a constant vector.
2344 // If this is a splat (repetition) of a value across the whole vector, return
2345 // the smallest size that splats it. For example, "0x01010101010101..." is a
2346 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2347 // SplatSize = 1 byte.
2348 unsigned SplatBits, SplatUndef, SplatSize;
2349 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2350 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2352 // First, handle single instruction cases.
2355 if (SplatBits == 0) {
2356 // Canonicalize all zero vectors to be v4i32.
2357 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2358 SDOperand Z = DAG.getConstant(0, MVT::i32);
2359 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2360 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2365 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2366 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2367 if (SextVal >= -16 && SextVal <= 15)
2368 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2371 // Two instruction sequences.
2373 // If this value is in the range [-32,30] and is even, use:
2374 // tmp = VSPLTI[bhw], result = add tmp, tmp
2375 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2376 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2377 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2380 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2381 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2383 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2384 // Make -1 and vspltisw -1:
2385 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2387 // Make the VSLW intrinsic, computing 0x8000_0000.
2388 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2391 // xor by OnesV to invert it.
2392 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2393 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2396 // Check to see if this is a wide variety of vsplti*, binop self cases.
2397 unsigned SplatBitSize = SplatSize*8;
2398 static const signed char SplatCsts[] = {
2399 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2400 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2403 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2404 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2405 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2406 int i = SplatCsts[idx];
2408 // Figure out what shift amount will be used by altivec if shifted by i in
2410 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2412 // vsplti + shl self.
2413 if (SextVal == (i << (int)TypeShiftAmt)) {
2414 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2415 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2416 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2417 Intrinsic::ppc_altivec_vslw
2419 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2420 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2423 // vsplti + srl self.
2424 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2425 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2426 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2427 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2428 Intrinsic::ppc_altivec_vsrw
2430 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2431 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2434 // vsplti + sra self.
2435 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2436 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2437 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2438 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2439 Intrinsic::ppc_altivec_vsraw
2441 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2442 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2445 // vsplti + rol self.
2446 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2447 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2448 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2449 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2450 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2451 Intrinsic::ppc_altivec_vrlw
2453 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2454 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2457 // t = vsplti c, result = vsldoi t, t, 1
2458 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2459 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2460 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2462 // t = vsplti c, result = vsldoi t, t, 2
2463 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2464 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2465 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2467 // t = vsplti c, result = vsldoi t, t, 3
2468 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2469 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2470 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2474 // Three instruction sequences.
2476 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2477 if (SextVal >= 0 && SextVal <= 31) {
2478 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2479 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2480 LHS = DAG.getNode(ISD::SUB, Op.getValueType(), LHS, RHS);
2481 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2483 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2484 if (SextVal >= -31 && SextVal <= 0) {
2485 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2486 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2487 LHS = DAG.getNode(ISD::ADD, Op.getValueType(), LHS, RHS);
2488 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2495 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2496 /// the specified operations to build the shuffle.
2497 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2498 SDOperand RHS, SelectionDAG &DAG) {
2499 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2500 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2501 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2504 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2516 if (OpNum == OP_COPY) {
2517 if (LHSID == (1*9+2)*9+3) return LHS;
2518 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2522 SDOperand OpLHS, OpRHS;
2523 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2524 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2526 unsigned ShufIdxs[16];
2528 default: assert(0 && "Unknown i32 permute!");
2530 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2531 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2532 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2533 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2536 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2537 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2538 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2539 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2542 for (unsigned i = 0; i != 16; ++i)
2543 ShufIdxs[i] = (i&3)+0;
2546 for (unsigned i = 0; i != 16; ++i)
2547 ShufIdxs[i] = (i&3)+4;
2550 for (unsigned i = 0; i != 16; ++i)
2551 ShufIdxs[i] = (i&3)+8;
2554 for (unsigned i = 0; i != 16; ++i)
2555 ShufIdxs[i] = (i&3)+12;
2558 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2560 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2562 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2565 for (unsigned i = 0; i != 16; ++i)
2566 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2568 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2569 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2572 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2573 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2574 /// return the code it can be lowered into. Worst case, it can always be
2575 /// lowered into a vperm.
2576 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2577 SDOperand V1 = Op.getOperand(0);
2578 SDOperand V2 = Op.getOperand(1);
2579 SDOperand PermMask = Op.getOperand(2);
2581 // Cases that are handled by instructions that take permute immediates
2582 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2583 // selected by the instruction selector.
2584 if (V2.getOpcode() == ISD::UNDEF) {
2585 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2586 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2587 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2588 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2589 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2590 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2591 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2592 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2593 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2594 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2595 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2596 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2601 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2602 // and produce a fixed permutation. If any of these match, do not lower to
2604 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2605 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2606 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2607 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2608 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2609 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2610 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2611 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2612 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2615 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2616 // perfect shuffle table to emit an optimal matching sequence.
2617 unsigned PFIndexes[4];
2618 bool isFourElementShuffle = true;
2619 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2620 unsigned EltNo = 8; // Start out undef.
2621 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2622 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2623 continue; // Undef, ignore it.
2625 unsigned ByteSource =
2626 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2627 if ((ByteSource & 3) != j) {
2628 isFourElementShuffle = false;
2633 EltNo = ByteSource/4;
2634 } else if (EltNo != ByteSource/4) {
2635 isFourElementShuffle = false;
2639 PFIndexes[i] = EltNo;
2642 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2643 // perfect shuffle vector to determine if it is cost effective to do this as
2644 // discrete instructions, or whether we should use a vperm.
2645 if (isFourElementShuffle) {
2646 // Compute the index in the perfect shuffle table.
2647 unsigned PFTableIndex =
2648 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2650 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2651 unsigned Cost = (PFEntry >> 30);
2653 // Determining when to avoid vperm is tricky. Many things affect the cost
2654 // of vperm, particularly how many times the perm mask needs to be computed.
2655 // For example, if the perm mask can be hoisted out of a loop or is already
2656 // used (perhaps because there are multiple permutes with the same shuffle
2657 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2658 // the loop requires an extra register.
2660 // As a compromise, we only emit discrete instructions if the shuffle can be
2661 // generated in 3 or fewer operations. When we have loop information
2662 // available, if this block is within a loop, we should avoid using vperm
2663 // for 3-operation perms and use a constant pool load instead.
2665 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2668 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2669 // vector that will get spilled to the constant pool.
2670 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2672 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2673 // that it is in input element units, not in bytes. Convert now.
2674 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2675 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2677 SmallVector<SDOperand, 16> ResultMask;
2678 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2680 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2683 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2685 for (unsigned j = 0; j != BytesPerElement; ++j)
2686 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2690 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2691 &ResultMask[0], ResultMask.size());
2692 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2695 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2696 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2697 /// information about the intrinsic.
2698 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2700 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2703 switch (IntrinsicID) {
2704 default: return false;
2705 // Comparison predicates.
2706 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2707 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2708 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2709 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2710 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2711 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2712 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2713 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2714 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2715 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2716 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2717 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2718 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2720 // Normal Comparisons.
2721 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2722 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2723 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2724 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2725 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2726 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2727 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2728 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2729 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2730 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2731 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2732 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2733 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2738 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2739 /// lower, do it, otherwise return null.
2740 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2741 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2742 // opcode number of the comparison.
2745 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2746 return SDOperand(); // Don't custom lower most intrinsics.
2748 // If this is a non-dot comparison, make the VCMP node and we are done.
2750 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2751 Op.getOperand(1), Op.getOperand(2),
2752 DAG.getConstant(CompareOpc, MVT::i32));
2753 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2756 // Create the PPCISD altivec 'dot' comparison node.
2758 Op.getOperand(2), // LHS
2759 Op.getOperand(3), // RHS
2760 DAG.getConstant(CompareOpc, MVT::i32)
2762 std::vector<MVT::ValueType> VTs;
2763 VTs.push_back(Op.getOperand(2).getValueType());
2764 VTs.push_back(MVT::Flag);
2765 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2767 // Now that we have the comparison, emit a copy from the CR to a GPR.
2768 // This is flagged to the above dot comparison.
2769 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2770 DAG.getRegister(PPC::CR6, MVT::i32),
2771 CompNode.getValue(1));
2773 // Unpack the result based on how the target uses it.
2774 unsigned BitNo; // Bit # of CR6.
2775 bool InvertBit; // Invert result?
2776 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2777 default: // Can't happen, don't crash on invalid number though.
2778 case 0: // Return the value of the EQ bit of CR6.
2779 BitNo = 0; InvertBit = false;
2781 case 1: // Return the inverted value of the EQ bit of CR6.
2782 BitNo = 0; InvertBit = true;
2784 case 2: // Return the value of the LT bit of CR6.
2785 BitNo = 2; InvertBit = false;
2787 case 3: // Return the inverted value of the LT bit of CR6.
2788 BitNo = 2; InvertBit = true;
2792 // Shift the bit into the low position.
2793 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2794 DAG.getConstant(8-(3-BitNo), MVT::i32));
2796 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2797 DAG.getConstant(1, MVT::i32));
2799 // If we are supposed to, toggle the bit.
2801 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2802 DAG.getConstant(1, MVT::i32));
2806 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2807 // Create a stack slot that is 16-byte aligned.
2808 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2809 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
2810 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2811 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2813 // Store the input value into Value#0 of the stack slot.
2814 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
2815 Op.getOperand(0), FIdx, NULL, 0);
2817 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
2820 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
2821 if (Op.getValueType() == MVT::v4i32) {
2822 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2824 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
2825 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
2827 SDOperand RHSSwap = // = vrlw RHS, 16
2828 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
2830 // Shrinkify inputs to v8i16.
2831 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
2832 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
2833 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
2835 // Low parts multiplied together, generating 32-bit results (we ignore the
2837 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
2838 LHS, RHS, DAG, MVT::v4i32);
2840 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
2841 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
2842 // Shift the high parts up 16 bits.
2843 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
2844 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
2845 } else if (Op.getValueType() == MVT::v8i16) {
2846 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2848 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
2850 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
2851 LHS, RHS, Zero, DAG);
2852 } else if (Op.getValueType() == MVT::v16i8) {
2853 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2855 // Multiply the even 8-bit parts, producing 16-bit sums.
2856 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
2857 LHS, RHS, DAG, MVT::v8i16);
2858 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
2860 // Multiply the odd 8-bit parts, producing 16-bit sums.
2861 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
2862 LHS, RHS, DAG, MVT::v8i16);
2863 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
2865 // Merge the results together.
2867 for (unsigned i = 0; i != 8; ++i) {
2868 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
2869 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
2871 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
2872 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2874 assert(0 && "Unknown mul to lower!");
2879 /// LowerOperation - Provide custom lowering hooks for some operations.
2881 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
2882 switch (Op.getOpcode()) {
2883 default: assert(0 && "Wasn't expecting to be able to lower this!");
2884 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
2885 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
2886 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
2887 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
2888 case ISD::SETCC: return LowerSETCC(Op, DAG);
2890 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2891 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2894 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
2895 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
2897 case ISD::FORMAL_ARGUMENTS:
2898 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
2899 VarArgsStackOffset, VarArgsNumGPR,
2900 VarArgsNumFPR, PPCSubTarget);
2902 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
2903 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
2904 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
2905 case ISD::DYNAMIC_STACKALLOC:
2906 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
2908 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
2909 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
2910 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
2912 // Lower 64-bit shifts.
2913 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
2914 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
2915 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
2917 // Vector-related lowering.
2918 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
2919 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
2920 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
2921 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
2922 case ISD::MUL: return LowerMUL(Op, DAG);
2924 // Frame & Return address. Currently unimplemented
2925 case ISD::RETURNADDR: break;
2926 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
2931 //===----------------------------------------------------------------------===//
2932 // Other Lowering Code
2933 //===----------------------------------------------------------------------===//
2936 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
2937 MachineBasicBlock *BB) {
2938 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
2939 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
2940 MI->getOpcode() == PPC::SELECT_CC_I8 ||
2941 MI->getOpcode() == PPC::SELECT_CC_F4 ||
2942 MI->getOpcode() == PPC::SELECT_CC_F8 ||
2943 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
2944 "Unexpected instr type to insert");
2946 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
2947 // control-flow pattern. The incoming instruction knows the destination vreg
2948 // to set, the condition code register to branch on, the true/false values to
2949 // select between, and a branch opcode to use.
2950 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2951 ilist<MachineBasicBlock>::iterator It = BB;
2957 // cmpTY ccX, r1, r2
2959 // fallthrough --> copy0MBB
2960 MachineBasicBlock *thisMBB = BB;
2961 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2962 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2963 unsigned SelectPred = MI->getOperand(4).getImm();
2964 BuildMI(BB, TII->get(PPC::BCC))
2965 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
2966 MachineFunction *F = BB->getParent();
2967 F->getBasicBlockList().insert(It, copy0MBB);
2968 F->getBasicBlockList().insert(It, sinkMBB);
2969 // Update machine-CFG edges by first adding all successors of the current
2970 // block to the new block which will contain the Phi node for the select.
2971 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
2972 e = BB->succ_end(); i != e; ++i)
2973 sinkMBB->addSuccessor(*i);
2974 // Next, remove all successors of the current block, and add the true
2975 // and fallthrough blocks as its successors.
2976 while(!BB->succ_empty())
2977 BB->removeSuccessor(BB->succ_begin());
2978 BB->addSuccessor(copy0MBB);
2979 BB->addSuccessor(sinkMBB);
2982 // %FalseValue = ...
2983 // # fallthrough to sinkMBB
2986 // Update machine-CFG edges
2987 BB->addSuccessor(sinkMBB);
2990 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2993 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
2994 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
2995 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
2997 delete MI; // The pseudo instruction is gone now.
3001 //===----------------------------------------------------------------------===//
3002 // Target Optimization Hooks
3003 //===----------------------------------------------------------------------===//
3005 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3006 DAGCombinerInfo &DCI) const {
3007 TargetMachine &TM = getTargetMachine();
3008 SelectionDAG &DAG = DCI.DAG;
3009 switch (N->getOpcode()) {
3012 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3013 if (C->getValue() == 0) // 0 << V -> 0.
3014 return N->getOperand(0);
3018 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3019 if (C->getValue() == 0) // 0 >>u V -> 0.
3020 return N->getOperand(0);
3024 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3025 if (C->getValue() == 0 || // 0 >>s V -> 0.
3026 C->isAllOnesValue()) // -1 >>s V -> -1.
3027 return N->getOperand(0);
3031 case ISD::SINT_TO_FP:
3032 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3033 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3034 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3035 // We allow the src/dst to be either f32/f64, but the intermediate
3036 // type must be i64.
3037 if (N->getOperand(0).getValueType() == MVT::i64) {
3038 SDOperand Val = N->getOperand(0).getOperand(0);
3039 if (Val.getValueType() == MVT::f32) {
3040 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3041 DCI.AddToWorklist(Val.Val);
3044 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3045 DCI.AddToWorklist(Val.Val);
3046 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3047 DCI.AddToWorklist(Val.Val);
3048 if (N->getValueType(0) == MVT::f32) {
3049 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
3050 DCI.AddToWorklist(Val.Val);
3053 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3054 // If the intermediate type is i32, we can avoid the load/store here
3061 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3062 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3063 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3064 N->getOperand(1).getValueType() == MVT::i32) {
3065 SDOperand Val = N->getOperand(1).getOperand(0);
3066 if (Val.getValueType() == MVT::f32) {
3067 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3068 DCI.AddToWorklist(Val.Val);
3070 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3071 DCI.AddToWorklist(Val.Val);
3073 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3074 N->getOperand(2), N->getOperand(3));
3075 DCI.AddToWorklist(Val.Val);
3079 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3080 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3081 N->getOperand(1).Val->hasOneUse() &&
3082 (N->getOperand(1).getValueType() == MVT::i32 ||
3083 N->getOperand(1).getValueType() == MVT::i16)) {
3084 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3085 // Do an any-extend to 32-bits if this is a half-word input.
3086 if (BSwapOp.getValueType() == MVT::i16)
3087 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3089 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3090 N->getOperand(2), N->getOperand(3),
3091 DAG.getValueType(N->getOperand(1).getValueType()));
3095 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3096 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3097 N->getOperand(0).hasOneUse() &&
3098 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3099 SDOperand Load = N->getOperand(0);
3100 LoadSDNode *LD = cast<LoadSDNode>(Load);
3101 // Create the byte-swapping load.
3102 std::vector<MVT::ValueType> VTs;
3103 VTs.push_back(MVT::i32);
3104 VTs.push_back(MVT::Other);
3105 SDOperand SV = DAG.getSrcValue(LD->getSrcValue(), LD->getSrcValueOffset());
3107 LD->getChain(), // Chain
3108 LD->getBasePtr(), // Ptr
3110 DAG.getValueType(N->getValueType(0)) // VT
3112 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3114 // If this is an i16 load, insert the truncate.
3115 SDOperand ResVal = BSLoad;
3116 if (N->getValueType(0) == MVT::i16)
3117 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3119 // First, combine the bswap away. This makes the value produced by the
3121 DCI.CombineTo(N, ResVal);
3123 // Next, combine the load away, we give it a bogus result value but a real
3124 // chain result. The result value is dead because the bswap is dead.
3125 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3127 // Return N so it doesn't get rechecked!
3128 return SDOperand(N, 0);
3132 case PPCISD::VCMP: {
3133 // If a VCMPo node already exists with exactly the same operands as this
3134 // node, use its result instead of this node (VCMPo computes both a CR6 and
3135 // a normal output).
3137 if (!N->getOperand(0).hasOneUse() &&
3138 !N->getOperand(1).hasOneUse() &&
3139 !N->getOperand(2).hasOneUse()) {
3141 // Scan all of the users of the LHS, looking for VCMPo's that match.
3142 SDNode *VCMPoNode = 0;
3144 SDNode *LHSN = N->getOperand(0).Val;
3145 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3147 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3148 (*UI)->getOperand(1) == N->getOperand(1) &&
3149 (*UI)->getOperand(2) == N->getOperand(2) &&
3150 (*UI)->getOperand(0) == N->getOperand(0)) {
3155 // If there is no VCMPo node, or if the flag value has a single use, don't
3157 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3160 // Look at the (necessarily single) use of the flag value. If it has a
3161 // chain, this transformation is more complex. Note that multiple things
3162 // could use the value result, which we should ignore.
3163 SDNode *FlagUser = 0;
3164 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3165 FlagUser == 0; ++UI) {
3166 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3168 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3169 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3176 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3177 // give up for right now.
3178 if (FlagUser->getOpcode() == PPCISD::MFCR)
3179 return SDOperand(VCMPoNode, 0);
3184 // If this is a branch on an altivec predicate comparison, lower this so
3185 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3186 // lowering is done pre-legalize, because the legalizer lowers the predicate
3187 // compare down to code that is difficult to reassemble.
3188 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3189 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3193 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3194 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3195 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3196 assert(isDot && "Can't compare against a vector result!");
3198 // If this is a comparison against something other than 0/1, then we know
3199 // that the condition is never/always true.
3200 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3201 if (Val != 0 && Val != 1) {
3202 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3203 return N->getOperand(0);
3204 // Always !=, turn it into an unconditional branch.
3205 return DAG.getNode(ISD::BR, MVT::Other,
3206 N->getOperand(0), N->getOperand(4));
3209 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3211 // Create the PPCISD altivec 'dot' comparison node.
3212 std::vector<MVT::ValueType> VTs;
3214 LHS.getOperand(2), // LHS of compare
3215 LHS.getOperand(3), // RHS of compare
3216 DAG.getConstant(CompareOpc, MVT::i32)
3218 VTs.push_back(LHS.getOperand(2).getValueType());
3219 VTs.push_back(MVT::Flag);
3220 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3222 // Unpack the result based on how the target uses it.
3223 PPC::Predicate CompOpc;
3224 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3225 default: // Can't happen, don't crash on invalid number though.
3226 case 0: // Branch on the value of the EQ bit of CR6.
3227 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3229 case 1: // Branch on the inverted value of the EQ bit of CR6.
3230 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3232 case 2: // Branch on the value of the LT bit of CR6.
3233 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3235 case 3: // Branch on the inverted value of the LT bit of CR6.
3236 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3240 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3241 DAG.getConstant(CompOpc, MVT::i32),
3242 DAG.getRegister(PPC::CR6, MVT::i32),
3243 N->getOperand(4), CompNode.getValue(1));
3252 //===----------------------------------------------------------------------===//
3253 // Inline Assembly Support
3254 //===----------------------------------------------------------------------===//
3256 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3258 uint64_t &KnownZero,
3260 const SelectionDAG &DAG,
3261 unsigned Depth) const {
3264 switch (Op.getOpcode()) {
3266 case PPCISD::LBRX: {
3267 // lhbrx is known to have the top bits cleared out.
3268 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3269 KnownZero = 0xFFFF0000;
3272 case ISD::INTRINSIC_WO_CHAIN: {
3273 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3275 case Intrinsic::ppc_altivec_vcmpbfp_p:
3276 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3277 case Intrinsic::ppc_altivec_vcmpequb_p:
3278 case Intrinsic::ppc_altivec_vcmpequh_p:
3279 case Intrinsic::ppc_altivec_vcmpequw_p:
3280 case Intrinsic::ppc_altivec_vcmpgefp_p:
3281 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3282 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3283 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3284 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3285 case Intrinsic::ppc_altivec_vcmpgtub_p:
3286 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3287 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3288 KnownZero = ~1U; // All bits but the low one are known to be zero.
3296 /// getConstraintType - Given a constraint, return the type of
3297 /// constraint it is for this target.
3298 PPCTargetLowering::ConstraintType
3299 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3300 if (Constraint.size() == 1) {
3301 switch (Constraint[0]) {
3308 return C_RegisterClass;
3311 return TargetLowering::getConstraintType(Constraint);
3314 std::pair<unsigned, const TargetRegisterClass*>
3315 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3316 MVT::ValueType VT) const {
3317 if (Constraint.size() == 1) {
3318 // GCC RS6000 Constraint Letters
3319 switch (Constraint[0]) {
3322 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3323 return std::make_pair(0U, PPC::G8RCRegisterClass);
3324 return std::make_pair(0U, PPC::GPRCRegisterClass);
3327 return std::make_pair(0U, PPC::F4RCRegisterClass);
3328 else if (VT == MVT::f64)
3329 return std::make_pair(0U, PPC::F8RCRegisterClass);
3332 return std::make_pair(0U, PPC::VRRCRegisterClass);
3334 return std::make_pair(0U, PPC::CRRCRegisterClass);
3338 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3342 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3343 /// vector. If it is invalid, don't add anything to Ops.
3344 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3345 std::vector<SDOperand>&Ops,
3346 SelectionDAG &DAG) {
3347 SDOperand Result(0,0);
3358 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3359 if (!CST) return; // Must be an immediate to match.
3360 unsigned Value = CST->getValue();
3362 default: assert(0 && "Unknown constraint letter!");
3363 case 'I': // "I" is a signed 16-bit constant.
3364 if ((short)Value == (int)Value)
3365 Result = DAG.getTargetConstant(Value, Op.getValueType());
3367 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3368 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3369 if ((short)Value == 0)
3370 Result = DAG.getTargetConstant(Value, Op.getValueType());
3372 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3373 if ((Value >> 16) == 0)
3374 Result = DAG.getTargetConstant(Value, Op.getValueType());
3376 case 'M': // "M" is a constant that is greater than 31.
3378 Result = DAG.getTargetConstant(Value, Op.getValueType());
3380 case 'N': // "N" is a positive constant that is an exact power of two.
3381 if ((int)Value > 0 && isPowerOf2_32(Value))
3382 Result = DAG.getTargetConstant(Value, Op.getValueType());
3384 case 'O': // "O" is the constant zero.
3386 Result = DAG.getTargetConstant(Value, Op.getValueType());
3388 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3389 if ((short)-Value == (int)-Value)
3390 Result = DAG.getTargetConstant(Value, Op.getValueType());
3398 Ops.push_back(Result);
3402 // Handle standard constraint letters.
3403 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3406 // isLegalAddressingMode - Return true if the addressing mode represented
3407 // by AM is legal for this target, for a load/store of the specified type.
3408 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3409 const Type *Ty) const {
3410 // FIXME: PPC does not allow r+i addressing modes for vectors!
3412 // PPC allows a sign-extended 16-bit immediate field.
3413 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3416 // No global is ever allowed as a base.
3420 // PPC only support r+r,
3422 case 0: // "r+i" or just "i", depending on HasBaseReg.
3425 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3427 // Otherwise we have r+r or r+i.
3430 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3432 // Allow 2*r as r+r.
3435 // No other scales are supported.
3442 /// isLegalAddressImmediate - Return true if the integer value can be used
3443 /// as the offset of the target addressing mode for load / store of the
3445 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3446 // PPC allows a sign-extended 16-bit immediate field.
3447 return (V > -(1 << 16) && V < (1 << 16)-1);
3450 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3454 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG)
3456 // Depths > 0 not supported yet!
3457 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3460 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3461 bool isPPC64 = PtrVT == MVT::i64;
3463 MachineFunction &MF = DAG.getMachineFunction();
3464 MachineFrameInfo *MFI = MF.getFrameInfo();
3465 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3466 && MFI->getStackSize();
3469 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3472 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,