1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
27 #include "llvm/IR/CallingConv.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DerivedTypes.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Intrinsics.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
55 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
57 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
58 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
60 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
61 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
63 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
64 if (TM.getSubtargetImpl()->isDarwin())
65 return new TargetLoweringObjectFileMachO();
67 return new TargetLoweringObjectFileELF();
70 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
71 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
73 PPCRegInfo = TM.getRegisterInfo();
77 // Use _setjmp/_longjmp instead of setjmp/longjmp.
78 setUseUnderscoreSetJmp(true);
79 setUseUnderscoreLongJmp(true);
81 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
82 // arguments are at least 4/8 bytes aligned.
83 bool isPPC64 = Subtarget->isPPC64();
84 setMinStackArgumentAlignment(isPPC64 ? 8:4);
86 // Set up the register classes.
87 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
88 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
89 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
91 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
92 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
93 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
95 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
97 // PowerPC has pre-inc load and store's.
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
99 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
100 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
101 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
102 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
103 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
104 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
105 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
106 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
107 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
109 // This is used in the ppcf128->int sequence. Note it has different semantics
110 // from FP_ROUND: that rounds to nearest, this rounds to zero.
111 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
113 // We do not currently implement these libm ops for PowerPC.
114 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
115 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
116 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
117 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
118 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
120 // PowerPC has no SREM/UREM instructions
121 setOperationAction(ISD::SREM, MVT::i32, Expand);
122 setOperationAction(ISD::UREM, MVT::i32, Expand);
123 setOperationAction(ISD::SREM, MVT::i64, Expand);
124 setOperationAction(ISD::UREM, MVT::i64, Expand);
126 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
127 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
128 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
129 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
130 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
131 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
132 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
133 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
134 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
136 // We don't support sin/cos/sqrt/fmod/pow
137 setOperationAction(ISD::FSIN , MVT::f64, Expand);
138 setOperationAction(ISD::FCOS , MVT::f64, Expand);
139 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
140 setOperationAction(ISD::FREM , MVT::f64, Expand);
141 setOperationAction(ISD::FPOW , MVT::f64, Expand);
142 setOperationAction(ISD::FMA , MVT::f64, Legal);
143 setOperationAction(ISD::FSIN , MVT::f32, Expand);
144 setOperationAction(ISD::FCOS , MVT::f32, Expand);
145 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
146 setOperationAction(ISD::FREM , MVT::f32, Expand);
147 setOperationAction(ISD::FPOW , MVT::f32, Expand);
148 setOperationAction(ISD::FMA , MVT::f32, Legal);
150 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
152 // If we're enabling GP optimizations, use hardware square root
153 if (!Subtarget->hasFSQRT()) {
154 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
155 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
158 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
159 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
161 // PowerPC does not have BSWAP, CTPOP or CTTZ
162 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
163 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
164 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
165 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
166 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
167 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
168 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
169 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
170 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
171 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
173 // PowerPC does not have ROTR
174 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
175 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
177 // PowerPC does not have Select
178 setOperationAction(ISD::SELECT, MVT::i32, Expand);
179 setOperationAction(ISD::SELECT, MVT::i64, Expand);
180 setOperationAction(ISD::SELECT, MVT::f32, Expand);
181 setOperationAction(ISD::SELECT, MVT::f64, Expand);
183 // PowerPC wants to turn select_cc of FP into fsel when possible.
184 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
185 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
187 // PowerPC wants to optimize integer setcc a bit
188 setOperationAction(ISD::SETCC, MVT::i32, Custom);
190 // PowerPC does not have BRCOND which requires SetCC
191 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
193 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
195 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
196 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
198 // PowerPC does not have [U|S]INT_TO_FP
199 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
200 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
202 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
203 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
204 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
205 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
207 // We cannot sextinreg(i1). Expand to shifts.
208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
210 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
211 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
212 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
213 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
215 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intened to support
216 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
217 // support continuation, user-level threading, and etc.. As a result, no
218 // other SjLj exception interfaces are implemented and please don't build
219 // your own exception handling based on them.
220 // LLVM/Clang supports zero-cost DWARF exception handling.
221 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
222 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
224 // We want to legalize GlobalAddress and ConstantPool nodes into the
225 // appropriate instructions to materialize the address.
226 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
227 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
228 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
229 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
230 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
231 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
232 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
233 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
234 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
235 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
238 setOperationAction(ISD::TRAP, MVT::Other, Legal);
240 // TRAMPOLINE is custom lowered.
241 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
242 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
244 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
245 setOperationAction(ISD::VASTART , MVT::Other, Custom);
247 if (Subtarget->isSVR4ABI()) {
249 // VAARG always uses double-word chunks, so promote anything smaller.
250 setOperationAction(ISD::VAARG, MVT::i1, Promote);
251 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
252 setOperationAction(ISD::VAARG, MVT::i8, Promote);
253 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
254 setOperationAction(ISD::VAARG, MVT::i16, Promote);
255 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
256 setOperationAction(ISD::VAARG, MVT::i32, Promote);
257 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
258 setOperationAction(ISD::VAARG, MVT::Other, Expand);
260 // VAARG is custom lowered with the 32-bit SVR4 ABI.
261 setOperationAction(ISD::VAARG, MVT::Other, Custom);
262 setOperationAction(ISD::VAARG, MVT::i64, Custom);
265 setOperationAction(ISD::VAARG, MVT::Other, Expand);
267 // Use the default implementation.
268 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
269 setOperationAction(ISD::VAEND , MVT::Other, Expand);
270 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
271 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
272 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
273 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
275 // We want to custom lower some of our intrinsics.
276 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
278 // Comparisons that require checking two conditions.
279 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
280 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
281 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
282 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
283 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
284 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
285 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
286 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
287 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
288 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
289 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
290 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
292 if (Subtarget->has64BitSupport()) {
293 // They also have instructions for converting between i64 and fp.
294 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
295 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
296 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
297 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
298 // This is just the low 32 bits of a (signed) fp->i64 conversion.
299 // We cannot do this with Promote because i64 is not a legal type.
300 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
302 // FIXME: disable this lowered code. This generates 64-bit register values,
303 // and we don't model the fact that the top part is clobbered by calls. We
304 // need to flag these together so that the value isn't live across a call.
305 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
307 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
308 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
311 if (Subtarget->use64BitRegs()) {
312 // 64-bit PowerPC implementations can support i64 types directly
313 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
314 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
315 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
316 // 64-bit PowerPC wants to expand i128 shifts itself.
317 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
318 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
319 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
321 // 32-bit PowerPC wants to expand i64 shifts itself.
322 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
323 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
324 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
327 if (Subtarget->hasAltivec()) {
328 // First set operation action for all vector types to expand. Then we
329 // will selectively turn on ones that can be effectively codegen'd.
330 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
331 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
332 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
334 // add/sub are legal for all supported vector VT's.
335 setOperationAction(ISD::ADD , VT, Legal);
336 setOperationAction(ISD::SUB , VT, Legal);
338 // We promote all shuffles to v16i8.
339 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
340 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
342 // We promote all non-typed operations to v4i32.
343 setOperationAction(ISD::AND , VT, Promote);
344 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
345 setOperationAction(ISD::OR , VT, Promote);
346 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
347 setOperationAction(ISD::XOR , VT, Promote);
348 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
349 setOperationAction(ISD::LOAD , VT, Promote);
350 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
351 setOperationAction(ISD::SELECT, VT, Promote);
352 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
353 setOperationAction(ISD::STORE, VT, Promote);
354 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
356 // No other operations are legal.
357 setOperationAction(ISD::MUL , VT, Expand);
358 setOperationAction(ISD::SDIV, VT, Expand);
359 setOperationAction(ISD::SREM, VT, Expand);
360 setOperationAction(ISD::UDIV, VT, Expand);
361 setOperationAction(ISD::UREM, VT, Expand);
362 setOperationAction(ISD::FDIV, VT, Expand);
363 setOperationAction(ISD::FNEG, VT, Expand);
364 setOperationAction(ISD::FSQRT, VT, Expand);
365 setOperationAction(ISD::FLOG, VT, Expand);
366 setOperationAction(ISD::FLOG10, VT, Expand);
367 setOperationAction(ISD::FLOG2, VT, Expand);
368 setOperationAction(ISD::FEXP, VT, Expand);
369 setOperationAction(ISD::FEXP2, VT, Expand);
370 setOperationAction(ISD::FSIN, VT, Expand);
371 setOperationAction(ISD::FCOS, VT, Expand);
372 setOperationAction(ISD::FABS, VT, Expand);
373 setOperationAction(ISD::FPOWI, VT, Expand);
374 setOperationAction(ISD::FFLOOR, VT, Expand);
375 setOperationAction(ISD::FCEIL, VT, Expand);
376 setOperationAction(ISD::FTRUNC, VT, Expand);
377 setOperationAction(ISD::FRINT, VT, Expand);
378 setOperationAction(ISD::FNEARBYINT, VT, Expand);
379 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
380 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
381 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
382 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
383 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
384 setOperationAction(ISD::UDIVREM, VT, Expand);
385 setOperationAction(ISD::SDIVREM, VT, Expand);
386 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
387 setOperationAction(ISD::FPOW, VT, Expand);
388 setOperationAction(ISD::CTPOP, VT, Expand);
389 setOperationAction(ISD::CTLZ, VT, Expand);
390 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
391 setOperationAction(ISD::CTTZ, VT, Expand);
392 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
393 setOperationAction(ISD::VSELECT, VT, Expand);
394 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
396 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
397 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
398 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
399 setTruncStoreAction(VT, InnerVT, Expand);
401 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
402 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
403 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
406 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
407 // with merges, splats, etc.
408 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
410 setOperationAction(ISD::AND , MVT::v4i32, Legal);
411 setOperationAction(ISD::OR , MVT::v4i32, Legal);
412 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
413 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
414 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
415 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
416 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
417 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
418 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
419 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
420 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
421 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
422 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
423 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
425 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
426 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
427 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
428 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
430 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
431 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
432 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
433 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
434 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
436 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
437 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
439 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
440 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
441 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
442 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
444 // Altivec does not contain unordered floating-point compare instructions
445 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
446 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
447 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
448 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
449 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
450 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
453 if (Subtarget->has64BitSupport()) {
454 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
455 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
458 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
459 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
460 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
461 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
463 setBooleanContents(ZeroOrOneBooleanContent);
464 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
467 setStackPointerRegisterToSaveRestore(PPC::X1);
468 setExceptionPointerRegister(PPC::X3);
469 setExceptionSelectorRegister(PPC::X4);
471 setStackPointerRegisterToSaveRestore(PPC::R1);
472 setExceptionPointerRegister(PPC::R3);
473 setExceptionSelectorRegister(PPC::R4);
476 // We have target-specific dag combine patterns for the following nodes:
477 setTargetDAGCombine(ISD::SINT_TO_FP);
478 setTargetDAGCombine(ISD::STORE);
479 setTargetDAGCombine(ISD::BR_CC);
480 setTargetDAGCombine(ISD::BSWAP);
482 // Darwin long double math library functions have $LDBL128 appended.
483 if (Subtarget->isDarwin()) {
484 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
485 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
486 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
487 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
488 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
489 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
490 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
491 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
492 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
493 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
496 setMinFunctionAlignment(2);
497 if (PPCSubTarget.isDarwin())
498 setPrefFunctionAlignment(4);
500 if (isPPC64 && Subtarget->isJITCodeModel())
501 // Temporary workaround for the inability of PPC64 JIT to handle jump
503 setSupportJumpTables(false);
505 setInsertFencesForAtomic(true);
507 setSchedulingPreference(Sched::Hybrid);
509 computeRegisterProperties();
511 // The Freescale cores does better with aggressive inlining of memcpy and
512 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
513 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
514 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
515 MaxStoresPerMemset = 32;
516 MaxStoresPerMemsetOptSize = 16;
517 MaxStoresPerMemcpy = 32;
518 MaxStoresPerMemcpyOptSize = 8;
519 MaxStoresPerMemmove = 32;
520 MaxStoresPerMemmoveOptSize = 8;
522 setPrefFunctionAlignment(4);
523 BenefitFromCodePlacementOpt = true;
527 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
528 /// function arguments in the caller parameter area.
529 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
530 const TargetMachine &TM = getTargetMachine();
531 // Darwin passes everything on 4 byte boundary.
532 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
535 // 16byte and wider vectors are passed on 16byte boundary.
536 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
537 if (VTy->getBitWidth() >= 128)
540 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
541 if (PPCSubTarget.isPPC64())
547 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
550 case PPCISD::FSEL: return "PPCISD::FSEL";
551 case PPCISD::FCFID: return "PPCISD::FCFID";
552 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
553 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
554 case PPCISD::STFIWX: return "PPCISD::STFIWX";
555 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
556 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
557 case PPCISD::VPERM: return "PPCISD::VPERM";
558 case PPCISD::Hi: return "PPCISD::Hi";
559 case PPCISD::Lo: return "PPCISD::Lo";
560 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
561 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
562 case PPCISD::LOAD: return "PPCISD::LOAD";
563 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
564 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
565 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
566 case PPCISD::SRL: return "PPCISD::SRL";
567 case PPCISD::SRA: return "PPCISD::SRA";
568 case PPCISD::SHL: return "PPCISD::SHL";
569 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
570 case PPCISD::STD_32: return "PPCISD::STD_32";
571 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
572 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4";
573 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
574 case PPCISD::NOP: return "PPCISD::NOP";
575 case PPCISD::MTCTR: return "PPCISD::MTCTR";
576 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
577 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
578 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
579 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
580 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
581 case PPCISD::MFCR: return "PPCISD::MFCR";
582 case PPCISD::VCMP: return "PPCISD::VCMP";
583 case PPCISD::VCMPo: return "PPCISD::VCMPo";
584 case PPCISD::LBRX: return "PPCISD::LBRX";
585 case PPCISD::STBRX: return "PPCISD::STBRX";
586 case PPCISD::LARX: return "PPCISD::LARX";
587 case PPCISD::STCX: return "PPCISD::STCX";
588 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
589 case PPCISD::MFFS: return "PPCISD::MFFS";
590 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
591 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
592 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
593 case PPCISD::MTFSF: return "PPCISD::MTFSF";
594 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
595 case PPCISD::CR6SET: return "PPCISD::CR6SET";
596 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
597 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
598 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
599 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
600 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
601 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
602 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
603 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
604 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
605 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
606 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
607 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
608 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
609 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
610 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
611 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
615 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
618 return VT.changeVectorElementTypeToInteger();
621 //===----------------------------------------------------------------------===//
622 // Node matching predicates, for use by the tblgen matching code.
623 //===----------------------------------------------------------------------===//
625 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
626 static bool isFloatingPointZero(SDValue Op) {
627 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
628 return CFP->getValueAPF().isZero();
629 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
630 // Maybe this has already been legalized into the constant pool?
631 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
632 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
633 return CFP->getValueAPF().isZero();
638 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
639 /// true if Op is undef or if it matches the specified value.
640 static bool isConstantOrUndef(int Op, int Val) {
641 return Op < 0 || Op == Val;
644 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
645 /// VPKUHUM instruction.
646 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
648 for (unsigned i = 0; i != 16; ++i)
649 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
652 for (unsigned i = 0; i != 8; ++i)
653 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
654 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
660 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
661 /// VPKUWUM instruction.
662 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
664 for (unsigned i = 0; i != 16; i += 2)
665 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
666 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
669 for (unsigned i = 0; i != 8; i += 2)
670 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
671 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
672 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
673 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
679 /// isVMerge - Common function, used to match vmrg* shuffles.
681 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
682 unsigned LHSStart, unsigned RHSStart) {
683 assert(N->getValueType(0) == MVT::v16i8 &&
684 "PPC only supports shuffles by bytes!");
685 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
686 "Unsupported merge size!");
688 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
689 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
690 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
691 LHSStart+j+i*UnitSize) ||
692 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
693 RHSStart+j+i*UnitSize))
699 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
700 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
701 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
704 return isVMerge(N, UnitSize, 8, 24);
705 return isVMerge(N, UnitSize, 8, 8);
708 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
709 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
710 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
713 return isVMerge(N, UnitSize, 0, 16);
714 return isVMerge(N, UnitSize, 0, 0);
718 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
719 /// amount, otherwise return -1.
720 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
721 assert(N->getValueType(0) == MVT::v16i8 &&
722 "PPC only supports shuffles by bytes!");
724 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
726 // Find the first non-undef value in the shuffle mask.
728 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
731 if (i == 16) return -1; // all undef.
733 // Otherwise, check to see if the rest of the elements are consecutively
734 // numbered from this value.
735 unsigned ShiftAmt = SVOp->getMaskElt(i);
736 if (ShiftAmt < i) return -1;
740 // Check the rest of the elements to see if they are consecutive.
741 for (++i; i != 16; ++i)
742 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
745 // Check the rest of the elements to see if they are consecutive.
746 for (++i; i != 16; ++i)
747 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
753 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
754 /// specifies a splat of a single element that is suitable for input to
755 /// VSPLTB/VSPLTH/VSPLTW.
756 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
757 assert(N->getValueType(0) == MVT::v16i8 &&
758 (EltSize == 1 || EltSize == 2 || EltSize == 4));
760 // This is a splat operation if each element of the permute is the same, and
761 // if the value doesn't reference the second vector.
762 unsigned ElementBase = N->getMaskElt(0);
764 // FIXME: Handle UNDEF elements too!
765 if (ElementBase >= 16)
768 // Check that the indices are consecutive, in the case of a multi-byte element
769 // splatted with a v16i8 mask.
770 for (unsigned i = 1; i != EltSize; ++i)
771 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
774 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
775 if (N->getMaskElt(i) < 0) continue;
776 for (unsigned j = 0; j != EltSize; ++j)
777 if (N->getMaskElt(i+j) != N->getMaskElt(j))
783 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
785 bool PPC::isAllNegativeZeroVector(SDNode *N) {
786 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
788 APInt APVal, APUndef;
792 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
793 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
794 return CFP->getValueAPF().isNegZero();
799 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
800 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
801 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
802 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
803 assert(isSplatShuffleMask(SVOp, EltSize));
804 return SVOp->getMaskElt(0) / EltSize;
807 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
808 /// by using a vspltis[bhw] instruction of the specified element size, return
809 /// the constant being splatted. The ByteSize field indicates the number of
810 /// bytes of each element [124] -> [bhw].
811 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
814 // If ByteSize of the splat is bigger than the element size of the
815 // build_vector, then we have a case where we are checking for a splat where
816 // multiple elements of the buildvector are folded together into a single
817 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
818 unsigned EltSize = 16/N->getNumOperands();
819 if (EltSize < ByteSize) {
820 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
821 SDValue UniquedVals[4];
822 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
824 // See if all of the elements in the buildvector agree across.
825 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
826 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
827 // If the element isn't a constant, bail fully out.
828 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
831 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
832 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
833 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
834 return SDValue(); // no match.
837 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
838 // either constant or undef values that are identical for each chunk. See
839 // if these chunks can form into a larger vspltis*.
841 // Check to see if all of the leading entries are either 0 or -1. If
842 // neither, then this won't fit into the immediate field.
843 bool LeadingZero = true;
844 bool LeadingOnes = true;
845 for (unsigned i = 0; i != Multiple-1; ++i) {
846 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
848 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
849 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
851 // Finally, check the least significant entry.
853 if (UniquedVals[Multiple-1].getNode() == 0)
854 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
855 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
857 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
860 if (UniquedVals[Multiple-1].getNode() == 0)
861 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
862 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
863 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
864 return DAG.getTargetConstant(Val, MVT::i32);
870 // Check to see if this buildvec has a single non-undef value in its elements.
871 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
872 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
873 if (OpVal.getNode() == 0)
874 OpVal = N->getOperand(i);
875 else if (OpVal != N->getOperand(i))
879 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
881 unsigned ValSizeInBytes = EltSize;
883 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
884 Value = CN->getZExtValue();
885 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
886 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
887 Value = FloatToBits(CN->getValueAPF().convertToFloat());
890 // If the splat value is larger than the element value, then we can never do
891 // this splat. The only case that we could fit the replicated bits into our
892 // immediate field for would be zero, and we prefer to use vxor for it.
893 if (ValSizeInBytes < ByteSize) return SDValue();
895 // If the element value is larger than the splat value, cut it in half and
896 // check to see if the two halves are equal. Continue doing this until we
897 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
898 while (ValSizeInBytes > ByteSize) {
899 ValSizeInBytes >>= 1;
901 // If the top half equals the bottom half, we're still ok.
902 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
903 (Value & ((1 << (8*ValSizeInBytes))-1)))
907 // Properly sign extend the value.
908 int MaskVal = SignExtend32(Value, ByteSize * 8);
910 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
911 if (MaskVal == 0) return SDValue();
913 // Finally, if this value fits in a 5 bit sext field, return it
914 if (SignExtend32<5>(MaskVal) == MaskVal)
915 return DAG.getTargetConstant(MaskVal, MVT::i32);
919 //===----------------------------------------------------------------------===//
920 // Addressing Mode Selection
921 //===----------------------------------------------------------------------===//
923 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
924 /// or 64-bit immediate, and if the value can be accurately represented as a
925 /// sign extension from a 16-bit value. If so, this returns true and the
927 static bool isIntS16Immediate(SDNode *N, short &Imm) {
928 if (N->getOpcode() != ISD::Constant)
931 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
932 if (N->getValueType(0) == MVT::i32)
933 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
935 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
937 static bool isIntS16Immediate(SDValue Op, short &Imm) {
938 return isIntS16Immediate(Op.getNode(), Imm);
942 /// SelectAddressRegReg - Given the specified addressed, check to see if it
943 /// can be represented as an indexed [r+r] operation. Returns false if it
944 /// can be more efficiently represented with [r+imm].
945 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
947 SelectionDAG &DAG) const {
949 if (N.getOpcode() == ISD::ADD) {
950 if (isIntS16Immediate(N.getOperand(1), imm))
952 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
955 Base = N.getOperand(0);
956 Index = N.getOperand(1);
958 } else if (N.getOpcode() == ISD::OR) {
959 if (isIntS16Immediate(N.getOperand(1), imm))
960 return false; // r+i can fold it if we can.
962 // If this is an or of disjoint bitfields, we can codegen this as an add
963 // (for better address arithmetic) if the LHS and RHS of the OR are provably
965 APInt LHSKnownZero, LHSKnownOne;
966 APInt RHSKnownZero, RHSKnownOne;
967 DAG.ComputeMaskedBits(N.getOperand(0),
968 LHSKnownZero, LHSKnownOne);
970 if (LHSKnownZero.getBoolValue()) {
971 DAG.ComputeMaskedBits(N.getOperand(1),
972 RHSKnownZero, RHSKnownOne);
973 // If all of the bits are known zero on the LHS or RHS, the add won't
975 if (~(LHSKnownZero | RHSKnownZero) == 0) {
976 Base = N.getOperand(0);
977 Index = N.getOperand(1);
986 /// Returns true if the address N can be represented by a base register plus
987 /// a signed 16-bit displacement [r+imm], and if it is not better
988 /// represented as reg+reg.
989 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
991 SelectionDAG &DAG) const {
992 // FIXME dl should come from parent load or store, not from address
993 DebugLoc dl = N.getDebugLoc();
994 // If this can be more profitably realized as r+r, fail.
995 if (SelectAddressRegReg(N, Disp, Base, DAG))
998 if (N.getOpcode() == ISD::ADD) {
1000 if (isIntS16Immediate(N.getOperand(1), imm)) {
1001 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1002 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1003 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1005 Base = N.getOperand(0);
1007 return true; // [r+i]
1008 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1009 // Match LOAD (ADD (X, Lo(G))).
1010 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1011 && "Cannot handle constant offsets yet!");
1012 Disp = N.getOperand(1).getOperand(0); // The global address.
1013 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1014 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1015 Disp.getOpcode() == ISD::TargetConstantPool ||
1016 Disp.getOpcode() == ISD::TargetJumpTable);
1017 Base = N.getOperand(0);
1018 return true; // [&g+r]
1020 } else if (N.getOpcode() == ISD::OR) {
1022 if (isIntS16Immediate(N.getOperand(1), imm)) {
1023 // If this is an or of disjoint bitfields, we can codegen this as an add
1024 // (for better address arithmetic) if the LHS and RHS of the OR are
1025 // provably disjoint.
1026 APInt LHSKnownZero, LHSKnownOne;
1027 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1029 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1030 // If all of the bits are known zero on the LHS or RHS, the add won't
1032 Base = N.getOperand(0);
1033 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1037 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1038 // Loading from a constant address.
1040 // If this address fits entirely in a 16-bit sext immediate field, codegen
1043 if (isIntS16Immediate(CN, Imm)) {
1044 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1045 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1046 CN->getValueType(0));
1050 // Handle 32-bit sext immediates with LIS + addr mode.
1051 if (CN->getValueType(0) == MVT::i32 ||
1052 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1053 int Addr = (int)CN->getZExtValue();
1055 // Otherwise, break this down into an LIS + disp.
1056 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1058 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1059 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1060 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1065 Disp = DAG.getTargetConstant(0, getPointerTy());
1066 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1067 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1070 return true; // [r+0]
1073 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1074 /// represented as an indexed [r+r] operation.
1075 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1077 SelectionDAG &DAG) const {
1078 // Check to see if we can easily represent this as an [r+r] address. This
1079 // will fail if it thinks that the address is more profitably represented as
1080 // reg+imm, e.g. where imm = 0.
1081 if (SelectAddressRegReg(N, Base, Index, DAG))
1084 // If the operand is an addition, always emit this as [r+r], since this is
1085 // better (for code size, and execution, as the memop does the add for free)
1086 // than emitting an explicit add.
1087 if (N.getOpcode() == ISD::ADD) {
1088 Base = N.getOperand(0);
1089 Index = N.getOperand(1);
1093 // Otherwise, do it the hard way, using R0 as the base register.
1094 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1100 /// SelectAddressRegImmShift - Returns true if the address N can be
1101 /// represented by a base register plus a signed 14-bit displacement
1102 /// [r+imm*4]. Suitable for use by STD and friends.
1103 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1105 SelectionDAG &DAG) const {
1106 // FIXME dl should come from the parent load or store, not the address
1107 DebugLoc dl = N.getDebugLoc();
1108 // If this can be more profitably realized as r+r, fail.
1109 if (SelectAddressRegReg(N, Disp, Base, DAG))
1112 if (N.getOpcode() == ISD::ADD) {
1114 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1115 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1116 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1117 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1119 Base = N.getOperand(0);
1121 return true; // [r+i]
1122 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1123 // Match LOAD (ADD (X, Lo(G))).
1124 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1125 && "Cannot handle constant offsets yet!");
1126 Disp = N.getOperand(1).getOperand(0); // The global address.
1127 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1128 Disp.getOpcode() == ISD::TargetConstantPool ||
1129 Disp.getOpcode() == ISD::TargetJumpTable);
1130 Base = N.getOperand(0);
1131 return true; // [&g+r]
1133 } else if (N.getOpcode() == ISD::OR) {
1135 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1136 // If this is an or of disjoint bitfields, we can codegen this as an add
1137 // (for better address arithmetic) if the LHS and RHS of the OR are
1138 // provably disjoint.
1139 APInt LHSKnownZero, LHSKnownOne;
1140 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1141 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1142 // If all of the bits are known zero on the LHS or RHS, the add won't
1144 Base = N.getOperand(0);
1145 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1149 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1150 // Loading from a constant address. Verify low two bits are clear.
1151 if ((CN->getZExtValue() & 3) == 0) {
1152 // If this address fits entirely in a 14-bit sext immediate field, codegen
1155 if (isIntS16Immediate(CN, Imm)) {
1156 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1157 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1158 CN->getValueType(0));
1162 // Fold the low-part of 32-bit absolute addresses into addr mode.
1163 if (CN->getValueType(0) == MVT::i32 ||
1164 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1165 int Addr = (int)CN->getZExtValue();
1167 // Otherwise, break this down into an LIS + disp.
1168 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1169 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1170 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1171 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1177 Disp = DAG.getTargetConstant(0, getPointerTy());
1178 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1179 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1182 return true; // [r+0]
1186 /// getPreIndexedAddressParts - returns true by value, base pointer and
1187 /// offset pointer and addressing mode by reference if the node's address
1188 /// can be legally represented as pre-indexed load / store address.
1189 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1191 ISD::MemIndexedMode &AM,
1192 SelectionDAG &DAG) const {
1193 if (DisablePPCPreinc) return false;
1198 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1199 Ptr = LD->getBasePtr();
1200 VT = LD->getMemoryVT();
1201 Alignment = LD->getAlignment();
1202 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1203 Ptr = ST->getBasePtr();
1204 VT = ST->getMemoryVT();
1205 Alignment = ST->getAlignment();
1209 // PowerPC doesn't have preinc load/store instructions for vectors.
1213 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) {
1218 // LDU/STU use reg+imm*4, others use reg+imm.
1219 if (VT != MVT::i64) {
1221 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1224 // LDU/STU need an address with at least 4-byte alignment.
1229 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1233 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1234 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1235 // sext i32 to i64 when addr mode is r+i.
1236 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1237 LD->getExtensionType() == ISD::SEXTLOAD &&
1238 isa<ConstantSDNode>(Offset))
1246 //===----------------------------------------------------------------------===//
1247 // LowerOperation implementation
1248 //===----------------------------------------------------------------------===//
1250 /// GetLabelAccessInfo - Return true if we should reference labels using a
1251 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1252 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1253 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1254 HiOpFlags = PPCII::MO_HA16;
1255 LoOpFlags = PPCII::MO_LO16;
1257 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1258 // non-darwin platform. We don't support PIC on other platforms yet.
1259 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1260 TM.getSubtarget<PPCSubtarget>().isDarwin();
1262 HiOpFlags |= PPCII::MO_PIC_FLAG;
1263 LoOpFlags |= PPCII::MO_PIC_FLAG;
1266 // If this is a reference to a global value that requires a non-lazy-ptr, make
1267 // sure that instruction lowering adds it.
1268 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1269 HiOpFlags |= PPCII::MO_NLP_FLAG;
1270 LoOpFlags |= PPCII::MO_NLP_FLAG;
1272 if (GV->hasHiddenVisibility()) {
1273 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1274 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1281 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1282 SelectionDAG &DAG) {
1283 EVT PtrVT = HiPart.getValueType();
1284 SDValue Zero = DAG.getConstant(0, PtrVT);
1285 DebugLoc DL = HiPart.getDebugLoc();
1287 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1288 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1290 // With PIC, the first instruction is actually "GR+hi(&G)".
1292 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1293 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1295 // Generate non-pic code that has direct accesses to the constant pool.
1296 // The address of the global is just (hi(&g)+lo(&g)).
1297 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1300 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1301 SelectionDAG &DAG) const {
1302 EVT PtrVT = Op.getValueType();
1303 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1304 const Constant *C = CP->getConstVal();
1306 // 64-bit SVR4 ABI code is always position-independent.
1307 // The actual address of the GlobalValue is stored in the TOC.
1308 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1309 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1310 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1311 DAG.getRegister(PPC::X2, MVT::i64));
1314 unsigned MOHiFlag, MOLoFlag;
1315 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1317 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1319 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1320 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1323 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1324 EVT PtrVT = Op.getValueType();
1325 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1327 // 64-bit SVR4 ABI code is always position-independent.
1328 // The actual address of the GlobalValue is stored in the TOC.
1329 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1330 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1331 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1332 DAG.getRegister(PPC::X2, MVT::i64));
1335 unsigned MOHiFlag, MOLoFlag;
1336 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1337 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1338 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1339 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1342 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1343 SelectionDAG &DAG) const {
1344 EVT PtrVT = Op.getValueType();
1346 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1348 unsigned MOHiFlag, MOLoFlag;
1349 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1350 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1351 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1352 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1355 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1356 SelectionDAG &DAG) const {
1358 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1359 DebugLoc dl = GA->getDebugLoc();
1360 const GlobalValue *GV = GA->getGlobal();
1361 EVT PtrVT = getPointerTy();
1362 bool is64bit = PPCSubTarget.isPPC64();
1364 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1366 if (Model == TLSModel::LocalExec) {
1367 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1368 PPCII::MO_TPREL16_HA);
1369 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1370 PPCII::MO_TPREL16_LO);
1371 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1372 is64bit ? MVT::i64 : MVT::i32);
1373 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1374 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1378 llvm_unreachable("only local-exec is currently supported for ppc32");
1380 if (Model == TLSModel::InitialExec) {
1381 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1382 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1383 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1384 PtrVT, GOTReg, TGA);
1385 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1386 PtrVT, TGA, TPOffsetHi);
1387 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGA);
1390 if (Model == TLSModel::GeneralDynamic) {
1391 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1392 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1393 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1395 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1398 // We need a chain node, and don't have one handy. The underlying
1399 // call has no side effects, so using the function entry node
1401 SDValue Chain = DAG.getEntryNode();
1402 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1403 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1404 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1405 PtrVT, ParmReg, TGA);
1406 // The return value from GET_TLS_ADDR really is in X3 already, but
1407 // some hacks are needed here to tie everything together. The extra
1408 // copies dissolve during subsequent transforms.
1409 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1410 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1413 if (Model == TLSModel::LocalDynamic) {
1414 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1415 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1416 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1418 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1421 // We need a chain node, and don't have one handy. The underlying
1422 // call has no side effects, so using the function entry node
1424 SDValue Chain = DAG.getEntryNode();
1425 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1426 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1427 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1428 PtrVT, ParmReg, TGA);
1429 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1430 // some hacks are needed here to tie everything together. The extra
1431 // copies dissolve during subsequent transforms.
1432 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1433 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1434 Chain, ParmReg, TGA);
1435 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1438 llvm_unreachable("Unknown TLS model!");
1441 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1442 SelectionDAG &DAG) const {
1443 EVT PtrVT = Op.getValueType();
1444 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1445 DebugLoc DL = GSDN->getDebugLoc();
1446 const GlobalValue *GV = GSDN->getGlobal();
1448 // 64-bit SVR4 ABI code is always position-independent.
1449 // The actual address of the GlobalValue is stored in the TOC.
1450 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1451 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1452 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1453 DAG.getRegister(PPC::X2, MVT::i64));
1456 unsigned MOHiFlag, MOLoFlag;
1457 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1460 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1462 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1464 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1466 // If the global reference is actually to a non-lazy-pointer, we have to do an
1467 // extra load to get the address of the global.
1468 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1469 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1470 false, false, false, 0);
1474 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1475 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1476 DebugLoc dl = Op.getDebugLoc();
1478 // If we're comparing for equality to zero, expose the fact that this is
1479 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1480 // fold the new nodes.
1481 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1482 if (C->isNullValue() && CC == ISD::SETEQ) {
1483 EVT VT = Op.getOperand(0).getValueType();
1484 SDValue Zext = Op.getOperand(0);
1485 if (VT.bitsLT(MVT::i32)) {
1487 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1489 unsigned Log2b = Log2_32(VT.getSizeInBits());
1490 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1491 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1492 DAG.getConstant(Log2b, MVT::i32));
1493 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1495 // Leave comparisons against 0 and -1 alone for now, since they're usually
1496 // optimized. FIXME: revisit this when we can custom lower all setcc
1498 if (C->isAllOnesValue() || C->isNullValue())
1502 // If we have an integer seteq/setne, turn it into a compare against zero
1503 // by xor'ing the rhs with the lhs, which is faster than setting a
1504 // condition register, reading it back out, and masking the correct bit. The
1505 // normal approach here uses sub to do this instead of xor. Using xor exposes
1506 // the result to other bit-twiddling opportunities.
1507 EVT LHSVT = Op.getOperand(0).getValueType();
1508 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1509 EVT VT = Op.getValueType();
1510 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1512 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1517 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1518 const PPCSubtarget &Subtarget) const {
1519 SDNode *Node = Op.getNode();
1520 EVT VT = Node->getValueType(0);
1521 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1522 SDValue InChain = Node->getOperand(0);
1523 SDValue VAListPtr = Node->getOperand(1);
1524 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1525 DebugLoc dl = Node->getDebugLoc();
1527 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1530 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1531 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1533 InChain = GprIndex.getValue(1);
1535 if (VT == MVT::i64) {
1536 // Check if GprIndex is even
1537 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1538 DAG.getConstant(1, MVT::i32));
1539 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1540 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1541 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1542 DAG.getConstant(1, MVT::i32));
1543 // Align GprIndex to be even if it isn't
1544 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1548 // fpr index is 1 byte after gpr
1549 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1550 DAG.getConstant(1, MVT::i32));
1553 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1554 FprPtr, MachinePointerInfo(SV), MVT::i8,
1556 InChain = FprIndex.getValue(1);
1558 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1559 DAG.getConstant(8, MVT::i32));
1561 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1562 DAG.getConstant(4, MVT::i32));
1565 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1566 MachinePointerInfo(), false, false,
1568 InChain = OverflowArea.getValue(1);
1570 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1571 MachinePointerInfo(), false, false,
1573 InChain = RegSaveArea.getValue(1);
1575 // select overflow_area if index > 8
1576 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1577 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1579 // adjustment constant gpr_index * 4/8
1580 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1581 VT.isInteger() ? GprIndex : FprIndex,
1582 DAG.getConstant(VT.isInteger() ? 4 : 8,
1585 // OurReg = RegSaveArea + RegConstant
1586 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1589 // Floating types are 32 bytes into RegSaveArea
1590 if (VT.isFloatingPoint())
1591 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1592 DAG.getConstant(32, MVT::i32));
1594 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1595 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1596 VT.isInteger() ? GprIndex : FprIndex,
1597 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1600 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1601 VT.isInteger() ? VAListPtr : FprPtr,
1602 MachinePointerInfo(SV),
1603 MVT::i8, false, false, 0);
1605 // determine if we should load from reg_save_area or overflow_area
1606 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1608 // increase overflow_area by 4/8 if gpr/fpr > 8
1609 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1610 DAG.getConstant(VT.isInteger() ? 4 : 8,
1613 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1616 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1618 MachinePointerInfo(),
1619 MVT::i32, false, false, 0);
1621 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1622 false, false, false, 0);
1625 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1626 SelectionDAG &DAG) const {
1627 return Op.getOperand(0);
1630 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1631 SelectionDAG &DAG) const {
1632 SDValue Chain = Op.getOperand(0);
1633 SDValue Trmp = Op.getOperand(1); // trampoline
1634 SDValue FPtr = Op.getOperand(2); // nested function
1635 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1636 DebugLoc dl = Op.getDebugLoc();
1638 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1639 bool isPPC64 = (PtrVT == MVT::i64);
1641 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1644 TargetLowering::ArgListTy Args;
1645 TargetLowering::ArgListEntry Entry;
1647 Entry.Ty = IntPtrTy;
1648 Entry.Node = Trmp; Args.push_back(Entry);
1650 // TrampSize == (isPPC64 ? 48 : 40);
1651 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1652 isPPC64 ? MVT::i64 : MVT::i32);
1653 Args.push_back(Entry);
1655 Entry.Node = FPtr; Args.push_back(Entry);
1656 Entry.Node = Nest; Args.push_back(Entry);
1658 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1659 TargetLowering::CallLoweringInfo CLI(Chain,
1660 Type::getVoidTy(*DAG.getContext()),
1661 false, false, false, false, 0,
1663 /*isTailCall=*/false,
1664 /*doesNotRet=*/false,
1665 /*isReturnValueUsed=*/true,
1666 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1668 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1670 return CallResult.second;
1673 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1674 const PPCSubtarget &Subtarget) const {
1675 MachineFunction &MF = DAG.getMachineFunction();
1676 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1678 DebugLoc dl = Op.getDebugLoc();
1680 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1681 // vastart just stores the address of the VarArgsFrameIndex slot into the
1682 // memory location argument.
1683 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1684 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1685 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1686 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1687 MachinePointerInfo(SV),
1691 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1692 // We suppose the given va_list is already allocated.
1695 // char gpr; /* index into the array of 8 GPRs
1696 // * stored in the register save area
1697 // * gpr=0 corresponds to r3,
1698 // * gpr=1 to r4, etc.
1700 // char fpr; /* index into the array of 8 FPRs
1701 // * stored in the register save area
1702 // * fpr=0 corresponds to f1,
1703 // * fpr=1 to f2, etc.
1705 // char *overflow_arg_area;
1706 // /* location on stack that holds
1707 // * the next overflow argument
1709 // char *reg_save_area;
1710 // /* where r3:r10 and f1:f8 (if saved)
1716 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1717 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1720 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1722 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1724 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1727 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1728 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1730 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1731 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1733 uint64_t FPROffset = 1;
1734 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1736 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1738 // Store first byte : number of int regs
1739 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1741 MachinePointerInfo(SV),
1742 MVT::i8, false, false, 0);
1743 uint64_t nextOffset = FPROffset;
1744 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1747 // Store second byte : number of float regs
1748 SDValue secondStore =
1749 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1750 MachinePointerInfo(SV, nextOffset), MVT::i8,
1752 nextOffset += StackOffset;
1753 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1755 // Store second word : arguments given on stack
1756 SDValue thirdStore =
1757 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1758 MachinePointerInfo(SV, nextOffset),
1760 nextOffset += FrameOffset;
1761 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1763 // Store third word : arguments given in registers
1764 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1765 MachinePointerInfo(SV, nextOffset),
1770 #include "PPCGenCallingConv.inc"
1772 static bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1773 CCValAssign::LocInfo &LocInfo,
1774 ISD::ArgFlagsTy &ArgFlags,
1779 static bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1781 CCValAssign::LocInfo &LocInfo,
1782 ISD::ArgFlagsTy &ArgFlags,
1784 static const uint16_t ArgRegs[] = {
1785 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1786 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1788 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1790 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1792 // Skip one register if the first unallocated register has an even register
1793 // number and there are still argument registers available which have not been
1794 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1795 // need to skip a register if RegNum is odd.
1796 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1797 State.AllocateReg(ArgRegs[RegNum]);
1800 // Always return false here, as this function only makes sure that the first
1801 // unallocated register has an odd register number and does not actually
1802 // allocate a register for the current argument.
1806 static bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1808 CCValAssign::LocInfo &LocInfo,
1809 ISD::ArgFlagsTy &ArgFlags,
1811 static const uint16_t ArgRegs[] = {
1812 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1816 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1818 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1820 // If there is only one Floating-point register left we need to put both f64
1821 // values of a split ppc_fp128 value on the stack.
1822 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1823 State.AllocateReg(ArgRegs[RegNum]);
1826 // Always return false here, as this function only makes sure that the two f64
1827 // values a ppc_fp128 value is split into are both passed in registers or both
1828 // passed on the stack and does not actually allocate a register for the
1829 // current argument.
1833 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1835 static const uint16_t *GetFPR() {
1836 static const uint16_t FPR[] = {
1837 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1838 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1844 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1846 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1847 unsigned PtrByteSize) {
1848 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1849 if (Flags.isByVal())
1850 ArgSize = Flags.getByValSize();
1851 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1857 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1858 CallingConv::ID CallConv, bool isVarArg,
1859 const SmallVectorImpl<ISD::InputArg>
1861 DebugLoc dl, SelectionDAG &DAG,
1862 SmallVectorImpl<SDValue> &InVals)
1864 if (PPCSubTarget.isSVR4ABI()) {
1865 if (PPCSubTarget.isPPC64())
1866 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1869 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1872 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1878 PPCTargetLowering::LowerFormalArguments_32SVR4(
1880 CallingConv::ID CallConv, bool isVarArg,
1881 const SmallVectorImpl<ISD::InputArg>
1883 DebugLoc dl, SelectionDAG &DAG,
1884 SmallVectorImpl<SDValue> &InVals) const {
1886 // 32-bit SVR4 ABI Stack Frame Layout:
1887 // +-----------------------------------+
1888 // +--> | Back chain |
1889 // | +-----------------------------------+
1890 // | | Floating-point register save area |
1891 // | +-----------------------------------+
1892 // | | General register save area |
1893 // | +-----------------------------------+
1894 // | | CR save word |
1895 // | +-----------------------------------+
1896 // | | VRSAVE save word |
1897 // | +-----------------------------------+
1898 // | | Alignment padding |
1899 // | +-----------------------------------+
1900 // | | Vector register save area |
1901 // | +-----------------------------------+
1902 // | | Local variable space |
1903 // | +-----------------------------------+
1904 // | | Parameter list area |
1905 // | +-----------------------------------+
1906 // | | LR save word |
1907 // | +-----------------------------------+
1908 // SP--> +--- | Back chain |
1909 // +-----------------------------------+
1912 // System V Application Binary Interface PowerPC Processor Supplement
1913 // AltiVec Technology Programming Interface Manual
1915 MachineFunction &MF = DAG.getMachineFunction();
1916 MachineFrameInfo *MFI = MF.getFrameInfo();
1917 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1919 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1920 // Potential tail calls could cause overwriting of argument stack slots.
1921 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1922 (CallConv == CallingConv::Fast));
1923 unsigned PtrByteSize = 4;
1925 // Assign locations to all of the incoming arguments.
1926 SmallVector<CCValAssign, 16> ArgLocs;
1927 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1928 getTargetMachine(), ArgLocs, *DAG.getContext());
1930 // Reserve space for the linkage area on the stack.
1931 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1933 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
1935 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1936 CCValAssign &VA = ArgLocs[i];
1938 // Arguments stored in registers.
1939 if (VA.isRegLoc()) {
1940 const TargetRegisterClass *RC;
1941 EVT ValVT = VA.getValVT();
1943 switch (ValVT.getSimpleVT().SimpleTy) {
1945 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1947 RC = &PPC::GPRCRegClass;
1950 RC = &PPC::F4RCRegClass;
1953 RC = &PPC::F8RCRegClass;
1959 RC = &PPC::VRRCRegClass;
1963 // Transform the arguments stored in physical registers into virtual ones.
1964 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1965 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1967 InVals.push_back(ArgValue);
1969 // Argument stored in memory.
1970 assert(VA.isMemLoc());
1972 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1973 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1976 // Create load nodes to retrieve arguments from the stack.
1977 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1978 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1979 MachinePointerInfo(),
1980 false, false, false, 0));
1984 // Assign locations to all of the incoming aggregate by value arguments.
1985 // Aggregates passed by value are stored in the local variable space of the
1986 // caller's stack frame, right above the parameter list area.
1987 SmallVector<CCValAssign, 16> ByValArgLocs;
1988 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1989 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1991 // Reserve stack space for the allocations in CCInfo.
1992 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1994 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
1996 // Area that is at least reserved in the caller of this function.
1997 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1999 // Set the size that is at least reserved in caller of this function. Tail
2000 // call optimized function's reserved stack space needs to be aligned so that
2001 // taking the difference between two stack areas will result in an aligned
2003 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2006 std::max(MinReservedArea,
2007 PPCFrameLowering::getMinCallFrameSize(false, false));
2009 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2010 getStackAlignment();
2011 unsigned AlignMask = TargetAlign-1;
2012 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2014 FI->setMinReservedArea(MinReservedArea);
2016 SmallVector<SDValue, 8> MemOps;
2018 // If the function takes variable number of arguments, make a frame index for
2019 // the start of the first vararg value... for expansion of llvm.va_start.
2021 static const uint16_t GPArgRegs[] = {
2022 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2023 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2025 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2027 static const uint16_t FPArgRegs[] = {
2028 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2031 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2033 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2035 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2038 // Make room for NumGPArgRegs and NumFPArgRegs.
2039 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2040 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2042 FuncInfo->setVarArgsStackOffset(
2043 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2044 CCInfo.getNextStackOffset(), true));
2046 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2047 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2049 // The fixed integer arguments of a variadic function are stored to the
2050 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2051 // the result of va_next.
2052 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2053 // Get an existing live-in vreg, or add a new one.
2054 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2056 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2058 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2059 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2060 MachinePointerInfo(), false, false, 0);
2061 MemOps.push_back(Store);
2062 // Increment the address by four for the next argument to store
2063 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2064 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2067 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2069 // The double arguments are stored to the VarArgsFrameIndex
2071 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2072 // Get an existing live-in vreg, or add a new one.
2073 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2075 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2077 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2078 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2079 MachinePointerInfo(), false, false, 0);
2080 MemOps.push_back(Store);
2081 // Increment the address by eight for the next argument to store
2082 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2084 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2088 if (!MemOps.empty())
2089 Chain = DAG.getNode(ISD::TokenFactor, dl,
2090 MVT::Other, &MemOps[0], MemOps.size());
2095 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2096 // value to MVT::i64 and then truncate to the correct register size.
2098 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2099 SelectionDAG &DAG, SDValue ArgVal,
2100 DebugLoc dl) const {
2102 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2103 DAG.getValueType(ObjectVT));
2104 else if (Flags.isZExt())
2105 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2106 DAG.getValueType(ObjectVT));
2108 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2111 // Set the size that is at least reserved in caller of this function. Tail
2112 // call optimized functions' reserved stack space needs to be aligned so that
2113 // taking the difference between two stack areas will result in an aligned
2116 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2117 unsigned nAltivecParamsAtEnd,
2118 unsigned MinReservedArea,
2119 bool isPPC64) const {
2120 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2121 // Add the Altivec parameters at the end, if needed.
2122 if (nAltivecParamsAtEnd) {
2123 MinReservedArea = ((MinReservedArea+15)/16)*16;
2124 MinReservedArea += 16*nAltivecParamsAtEnd;
2127 std::max(MinReservedArea,
2128 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2129 unsigned TargetAlign
2130 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2131 getStackAlignment();
2132 unsigned AlignMask = TargetAlign-1;
2133 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2134 FI->setMinReservedArea(MinReservedArea);
2138 PPCTargetLowering::LowerFormalArguments_64SVR4(
2140 CallingConv::ID CallConv, bool isVarArg,
2141 const SmallVectorImpl<ISD::InputArg>
2143 DebugLoc dl, SelectionDAG &DAG,
2144 SmallVectorImpl<SDValue> &InVals) const {
2145 // TODO: add description of PPC stack frame format, or at least some docs.
2147 MachineFunction &MF = DAG.getMachineFunction();
2148 MachineFrameInfo *MFI = MF.getFrameInfo();
2149 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2151 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2152 // Potential tail calls could cause overwriting of argument stack slots.
2153 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2154 (CallConv == CallingConv::Fast));
2155 unsigned PtrByteSize = 8;
2157 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2158 // Area that is at least reserved in caller of this function.
2159 unsigned MinReservedArea = ArgOffset;
2161 static const uint16_t GPR[] = {
2162 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2163 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2166 static const uint16_t *FPR = GetFPR();
2168 static const uint16_t VR[] = {
2169 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2170 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2173 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2174 const unsigned Num_FPR_Regs = 13;
2175 const unsigned Num_VR_Regs = array_lengthof(VR);
2177 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2179 // Add DAG nodes to load the arguments or copy them out of registers. On
2180 // entry to a function on PPC, the arguments start after the linkage area,
2181 // although the first ones are often in registers.
2183 SmallVector<SDValue, 8> MemOps;
2184 unsigned nAltivecParamsAtEnd = 0;
2185 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2186 unsigned CurArgIdx = 0;
2187 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2189 bool needsLoad = false;
2190 EVT ObjectVT = Ins[ArgNo].VT;
2191 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2192 unsigned ArgSize = ObjSize;
2193 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2194 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2195 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2197 unsigned CurArgOffset = ArgOffset;
2199 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2200 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2201 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2203 MinReservedArea = ((MinReservedArea+15)/16)*16;
2204 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2208 nAltivecParamsAtEnd++;
2210 // Calculate min reserved area.
2211 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2215 // FIXME the codegen can be much improved in some cases.
2216 // We do not have to keep everything in memory.
2217 if (Flags.isByVal()) {
2218 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2219 ObjSize = Flags.getByValSize();
2220 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2221 // Empty aggregate parameters do not take up registers. Examples:
2225 // etc. However, we have to provide a place-holder in InVals, so
2226 // pretend we have an 8-byte item at the current address for that
2229 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2230 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2231 InVals.push_back(FIN);
2234 // All aggregates smaller than 8 bytes must be passed right-justified.
2235 if (ObjSize < PtrByteSize)
2236 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2237 // The value of the object is its address.
2238 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2239 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2240 InVals.push_back(FIN);
2243 if (GPR_idx != Num_GPR_Regs) {
2244 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2245 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2248 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2249 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2250 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2251 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2252 MachinePointerInfo(FuncArg, CurArgOffset),
2253 ObjType, false, false, 0);
2255 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2256 // store the whole register as-is to the parameter save area
2257 // slot. The address of the parameter was already calculated
2258 // above (InVals.push_back(FIN)) to be the right-justified
2259 // offset within the slot. For this store, we need a new
2260 // frame index that points at the beginning of the slot.
2261 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2262 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2263 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2264 MachinePointerInfo(FuncArg, ArgOffset),
2268 MemOps.push_back(Store);
2271 // Whether we copied from a register or not, advance the offset
2272 // into the parameter save area by a full doubleword.
2273 ArgOffset += PtrByteSize;
2277 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2278 // Store whatever pieces of the object are in registers
2279 // to memory. ArgOffset will be the address of the beginning
2281 if (GPR_idx != Num_GPR_Regs) {
2283 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2284 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2285 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2286 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2287 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2288 MachinePointerInfo(FuncArg, ArgOffset),
2290 MemOps.push_back(Store);
2292 ArgOffset += PtrByteSize;
2294 ArgOffset += ArgSize - j;
2301 switch (ObjectVT.getSimpleVT().SimpleTy) {
2302 default: llvm_unreachable("Unhandled argument type!");
2305 if (GPR_idx != Num_GPR_Regs) {
2306 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2307 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2309 if (ObjectVT == MVT::i32)
2310 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2311 // value to MVT::i64 and then truncate to the correct register size.
2312 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2317 ArgSize = PtrByteSize;
2324 // Every 8 bytes of argument space consumes one of the GPRs available for
2325 // argument passing.
2326 if (GPR_idx != Num_GPR_Regs) {
2329 if (FPR_idx != Num_FPR_Regs) {
2332 if (ObjectVT == MVT::f32)
2333 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2335 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2337 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2341 ArgSize = PtrByteSize;
2350 // Note that vector arguments in registers don't reserve stack space,
2351 // except in varargs functions.
2352 if (VR_idx != Num_VR_Regs) {
2353 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2354 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2356 while ((ArgOffset % 16) != 0) {
2357 ArgOffset += PtrByteSize;
2358 if (GPR_idx != Num_GPR_Regs)
2362 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2366 // Vectors are aligned.
2367 ArgOffset = ((ArgOffset+15)/16)*16;
2368 CurArgOffset = ArgOffset;
2375 // We need to load the argument to a virtual register if we determined
2376 // above that we ran out of physical registers of the appropriate type.
2378 int FI = MFI->CreateFixedObject(ObjSize,
2379 CurArgOffset + (ArgSize - ObjSize),
2381 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2382 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2383 false, false, false, 0);
2386 InVals.push_back(ArgVal);
2389 // Set the size that is at least reserved in caller of this function. Tail
2390 // call optimized functions' reserved stack space needs to be aligned so that
2391 // taking the difference between two stack areas will result in an aligned
2393 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2395 // If the function takes variable number of arguments, make a frame index for
2396 // the start of the first vararg value... for expansion of llvm.va_start.
2398 int Depth = ArgOffset;
2400 FuncInfo->setVarArgsFrameIndex(
2401 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2402 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2404 // If this function is vararg, store any remaining integer argument regs
2405 // to their spots on the stack so that they may be loaded by deferencing the
2406 // result of va_next.
2407 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2408 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2409 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2410 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2411 MachinePointerInfo(), false, false, 0);
2412 MemOps.push_back(Store);
2413 // Increment the address by four for the next argument to store
2414 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2415 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2419 if (!MemOps.empty())
2420 Chain = DAG.getNode(ISD::TokenFactor, dl,
2421 MVT::Other, &MemOps[0], MemOps.size());
2427 PPCTargetLowering::LowerFormalArguments_Darwin(
2429 CallingConv::ID CallConv, bool isVarArg,
2430 const SmallVectorImpl<ISD::InputArg>
2432 DebugLoc dl, SelectionDAG &DAG,
2433 SmallVectorImpl<SDValue> &InVals) const {
2434 // TODO: add description of PPC stack frame format, or at least some docs.
2436 MachineFunction &MF = DAG.getMachineFunction();
2437 MachineFrameInfo *MFI = MF.getFrameInfo();
2438 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2440 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2441 bool isPPC64 = PtrVT == MVT::i64;
2442 // Potential tail calls could cause overwriting of argument stack slots.
2443 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2444 (CallConv == CallingConv::Fast));
2445 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2447 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2448 // Area that is at least reserved in caller of this function.
2449 unsigned MinReservedArea = ArgOffset;
2451 static const uint16_t GPR_32[] = { // 32-bit registers.
2452 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2453 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2455 static const uint16_t GPR_64[] = { // 64-bit registers.
2456 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2457 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2460 static const uint16_t *FPR = GetFPR();
2462 static const uint16_t VR[] = {
2463 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2464 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2467 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2468 const unsigned Num_FPR_Regs = 13;
2469 const unsigned Num_VR_Regs = array_lengthof( VR);
2471 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2473 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2475 // In 32-bit non-varargs functions, the stack space for vectors is after the
2476 // stack space for non-vectors. We do not use this space unless we have
2477 // too many vectors to fit in registers, something that only occurs in
2478 // constructed examples:), but we have to walk the arglist to figure
2479 // that out...for the pathological case, compute VecArgOffset as the
2480 // start of the vector parameter area. Computing VecArgOffset is the
2481 // entire point of the following loop.
2482 unsigned VecArgOffset = ArgOffset;
2483 if (!isVarArg && !isPPC64) {
2484 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2486 EVT ObjectVT = Ins[ArgNo].VT;
2487 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2489 if (Flags.isByVal()) {
2490 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2491 unsigned ObjSize = Flags.getByValSize();
2493 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2494 VecArgOffset += ArgSize;
2498 switch(ObjectVT.getSimpleVT().SimpleTy) {
2499 default: llvm_unreachable("Unhandled argument type!");
2504 case MVT::i64: // PPC64
2506 // FIXME: We are guaranteed to be !isPPC64 at this point.
2507 // Does MVT::i64 apply?
2514 // Nothing to do, we're only looking at Nonvector args here.
2519 // We've found where the vector parameter area in memory is. Skip the
2520 // first 12 parameters; these don't use that memory.
2521 VecArgOffset = ((VecArgOffset+15)/16)*16;
2522 VecArgOffset += 12*16;
2524 // Add DAG nodes to load the arguments or copy them out of registers. On
2525 // entry to a function on PPC, the arguments start after the linkage area,
2526 // although the first ones are often in registers.
2528 SmallVector<SDValue, 8> MemOps;
2529 unsigned nAltivecParamsAtEnd = 0;
2530 // FIXME: FuncArg and Ins[ArgNo] must reference the same argument.
2531 // When passing anonymous aggregates, this is currently not true.
2532 // See LowerFormalArguments_64SVR4 for a fix.
2533 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2534 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2536 bool needsLoad = false;
2537 EVT ObjectVT = Ins[ArgNo].VT;
2538 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2539 unsigned ArgSize = ObjSize;
2540 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2542 unsigned CurArgOffset = ArgOffset;
2544 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2545 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2546 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2547 if (isVarArg || isPPC64) {
2548 MinReservedArea = ((MinReservedArea+15)/16)*16;
2549 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2552 } else nAltivecParamsAtEnd++;
2554 // Calculate min reserved area.
2555 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2559 // FIXME the codegen can be much improved in some cases.
2560 // We do not have to keep everything in memory.
2561 if (Flags.isByVal()) {
2562 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2563 ObjSize = Flags.getByValSize();
2564 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2565 // Objects of size 1 and 2 are right justified, everything else is
2566 // left justified. This means the memory address is adjusted forwards.
2567 if (ObjSize==1 || ObjSize==2) {
2568 CurArgOffset = CurArgOffset + (4 - ObjSize);
2570 // The value of the object is its address.
2571 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2572 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2573 InVals.push_back(FIN);
2574 if (ObjSize==1 || ObjSize==2) {
2575 if (GPR_idx != Num_GPR_Regs) {
2578 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2580 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2581 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2582 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2583 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2584 MachinePointerInfo(FuncArg,
2586 ObjType, false, false, 0);
2587 MemOps.push_back(Store);
2591 ArgOffset += PtrByteSize;
2595 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2596 // Store whatever pieces of the object are in registers
2597 // to memory. ArgOffset will be the address of the beginning
2599 if (GPR_idx != Num_GPR_Regs) {
2602 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2604 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2605 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2606 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2607 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2608 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2609 MachinePointerInfo(FuncArg, ArgOffset),
2611 MemOps.push_back(Store);
2613 ArgOffset += PtrByteSize;
2615 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2622 switch (ObjectVT.getSimpleVT().SimpleTy) {
2623 default: llvm_unreachable("Unhandled argument type!");
2626 if (GPR_idx != Num_GPR_Regs) {
2627 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2628 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2632 ArgSize = PtrByteSize;
2634 // All int arguments reserve stack space in the Darwin ABI.
2635 ArgOffset += PtrByteSize;
2639 case MVT::i64: // PPC64
2640 if (GPR_idx != Num_GPR_Regs) {
2641 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2642 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2644 if (ObjectVT == MVT::i32)
2645 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2646 // value to MVT::i64 and then truncate to the correct register size.
2647 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2652 ArgSize = PtrByteSize;
2654 // All int arguments reserve stack space in the Darwin ABI.
2660 // Every 4 bytes of argument space consumes one of the GPRs available for
2661 // argument passing.
2662 if (GPR_idx != Num_GPR_Regs) {
2664 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2667 if (FPR_idx != Num_FPR_Regs) {
2670 if (ObjectVT == MVT::f32)
2671 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2673 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2675 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2681 // All FP arguments reserve stack space in the Darwin ABI.
2682 ArgOffset += isPPC64 ? 8 : ObjSize;
2688 // Note that vector arguments in registers don't reserve stack space,
2689 // except in varargs functions.
2690 if (VR_idx != Num_VR_Regs) {
2691 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2692 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2694 while ((ArgOffset % 16) != 0) {
2695 ArgOffset += PtrByteSize;
2696 if (GPR_idx != Num_GPR_Regs)
2700 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2704 if (!isVarArg && !isPPC64) {
2705 // Vectors go after all the nonvectors.
2706 CurArgOffset = VecArgOffset;
2709 // Vectors are aligned.
2710 ArgOffset = ((ArgOffset+15)/16)*16;
2711 CurArgOffset = ArgOffset;
2719 // We need to load the argument to a virtual register if we determined above
2720 // that we ran out of physical registers of the appropriate type.
2722 int FI = MFI->CreateFixedObject(ObjSize,
2723 CurArgOffset + (ArgSize - ObjSize),
2725 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2726 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2727 false, false, false, 0);
2730 InVals.push_back(ArgVal);
2733 // Set the size that is at least reserved in caller of this function. Tail
2734 // call optimized functions' reserved stack space needs to be aligned so that
2735 // taking the difference between two stack areas will result in an aligned
2737 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2739 // If the function takes variable number of arguments, make a frame index for
2740 // the start of the first vararg value... for expansion of llvm.va_start.
2742 int Depth = ArgOffset;
2744 FuncInfo->setVarArgsFrameIndex(
2745 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2747 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2749 // If this function is vararg, store any remaining integer argument regs
2750 // to their spots on the stack so that they may be loaded by deferencing the
2751 // result of va_next.
2752 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2756 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2758 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2760 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2761 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2762 MachinePointerInfo(), false, false, 0);
2763 MemOps.push_back(Store);
2764 // Increment the address by four for the next argument to store
2765 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2766 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2770 if (!MemOps.empty())
2771 Chain = DAG.getNode(ISD::TokenFactor, dl,
2772 MVT::Other, &MemOps[0], MemOps.size());
2777 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2778 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2780 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2784 const SmallVectorImpl<ISD::OutputArg>
2786 const SmallVectorImpl<SDValue> &OutVals,
2787 unsigned &nAltivecParamsAtEnd) {
2788 // Count how many bytes are to be pushed on the stack, including the linkage
2789 // area, and parameter passing area. We start with 24/48 bytes, which is
2790 // prereserved space for [SP][CR][LR][3 x unused].
2791 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2792 unsigned NumOps = Outs.size();
2793 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2795 // Add up all the space actually used.
2796 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2797 // they all go in registers, but we must reserve stack space for them for
2798 // possible use by the caller. In varargs or 64-bit calls, parameters are
2799 // assigned stack space in order, with padding so Altivec parameters are
2801 nAltivecParamsAtEnd = 0;
2802 for (unsigned i = 0; i != NumOps; ++i) {
2803 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2804 EVT ArgVT = Outs[i].VT;
2805 // Varargs Altivec parameters are padded to a 16 byte boundary.
2806 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2807 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2808 if (!isVarArg && !isPPC64) {
2809 // Non-varargs Altivec parameters go after all the non-Altivec
2810 // parameters; handle those later so we know how much padding we need.
2811 nAltivecParamsAtEnd++;
2814 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2815 NumBytes = ((NumBytes+15)/16)*16;
2817 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2820 // Allow for Altivec parameters at the end, if needed.
2821 if (nAltivecParamsAtEnd) {
2822 NumBytes = ((NumBytes+15)/16)*16;
2823 NumBytes += 16*nAltivecParamsAtEnd;
2826 // The prolog code of the callee may store up to 8 GPR argument registers to
2827 // the stack, allowing va_start to index over them in memory if its varargs.
2828 // Because we cannot tell if this is needed on the caller side, we have to
2829 // conservatively assume that it is needed. As such, make sure we have at
2830 // least enough stack space for the caller to store the 8 GPRs.
2831 NumBytes = std::max(NumBytes,
2832 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2834 // Tail call needs the stack to be aligned.
2835 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2836 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2837 getFrameLowering()->getStackAlignment();
2838 unsigned AlignMask = TargetAlign-1;
2839 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2845 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2846 /// adjusted to accommodate the arguments for the tailcall.
2847 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2848 unsigned ParamSize) {
2850 if (!isTailCall) return 0;
2852 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2853 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2854 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2855 // Remember only if the new adjustement is bigger.
2856 if (SPDiff < FI->getTailCallSPDelta())
2857 FI->setTailCallSPDelta(SPDiff);
2862 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2863 /// for tail call optimization. Targets which want to do tail call
2864 /// optimization should implement this function.
2866 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2867 CallingConv::ID CalleeCC,
2869 const SmallVectorImpl<ISD::InputArg> &Ins,
2870 SelectionDAG& DAG) const {
2871 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2874 // Variable argument functions are not supported.
2878 MachineFunction &MF = DAG.getMachineFunction();
2879 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2880 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2881 // Functions containing by val parameters are not supported.
2882 for (unsigned i = 0; i != Ins.size(); i++) {
2883 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2884 if (Flags.isByVal()) return false;
2887 // Non PIC/GOT tail calls are supported.
2888 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2891 // At the moment we can only do local tail calls (in same module, hidden
2892 // or protected) if we are generating PIC.
2893 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2894 return G->getGlobal()->hasHiddenVisibility()
2895 || G->getGlobal()->hasProtectedVisibility();
2901 /// isCallCompatibleAddress - Return the immediate to use if the specified
2902 /// 32-bit value is representable in the immediate field of a BxA instruction.
2903 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2904 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2907 int Addr = C->getZExtValue();
2908 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2909 SignExtend32<26>(Addr) != Addr)
2910 return 0; // Top 6 bits have to be sext of immediate.
2912 return DAG.getConstant((int)C->getZExtValue() >> 2,
2913 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2918 struct TailCallArgumentInfo {
2923 TailCallArgumentInfo() : FrameIdx(0) {}
2928 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2930 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2932 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2933 SmallVector<SDValue, 8> &MemOpChains,
2935 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2936 SDValue Arg = TailCallArgs[i].Arg;
2937 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2938 int FI = TailCallArgs[i].FrameIdx;
2939 // Store relative to framepointer.
2940 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2941 MachinePointerInfo::getFixedStack(FI),
2946 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2947 /// the appropriate stack slot for the tail call optimized function call.
2948 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2949 MachineFunction &MF,
2958 // Calculate the new stack slot for the return address.
2959 int SlotSize = isPPC64 ? 8 : 4;
2960 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2962 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2963 NewRetAddrLoc, true);
2964 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2965 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2966 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2967 MachinePointerInfo::getFixedStack(NewRetAddr),
2970 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2971 // slot as the FP is never overwritten.
2974 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2975 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2977 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2978 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2979 MachinePointerInfo::getFixedStack(NewFPIdx),
2986 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2987 /// the position of the argument.
2989 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2990 SDValue Arg, int SPDiff, unsigned ArgOffset,
2991 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2992 int Offset = ArgOffset + SPDiff;
2993 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2994 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2995 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2996 SDValue FIN = DAG.getFrameIndex(FI, VT);
2997 TailCallArgumentInfo Info;
2999 Info.FrameIdxOp = FIN;
3001 TailCallArguments.push_back(Info);
3004 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3005 /// stack slot. Returns the chain as result and the loaded frame pointers in
3006 /// LROpOut/FPOpout. Used when tail calling.
3007 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3013 DebugLoc dl) const {
3015 // Load the LR and FP stack slot for later adjusting.
3016 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3017 LROpOut = getReturnAddrFrameIndex(DAG);
3018 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3019 false, false, false, 0);
3020 Chain = SDValue(LROpOut.getNode(), 1);
3022 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3023 // slot as the FP is never overwritten.
3025 FPOpOut = getFramePointerFrameIndex(DAG);
3026 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3027 false, false, false, 0);
3028 Chain = SDValue(FPOpOut.getNode(), 1);
3034 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3035 /// by "Src" to address "Dst" of size "Size". Alignment information is
3036 /// specified by the specific parameter attribute. The copy will be passed as
3037 /// a byval function parameter.
3038 /// Sometimes what we are copying is the end of a larger object, the part that
3039 /// does not fit in registers.
3041 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3042 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3044 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3045 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3046 false, false, MachinePointerInfo(0),
3047 MachinePointerInfo(0));
3050 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3053 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3054 SDValue Arg, SDValue PtrOff, int SPDiff,
3055 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3056 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
3057 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
3059 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3064 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3066 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3067 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3068 DAG.getConstant(ArgOffset, PtrVT));
3070 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3071 MachinePointerInfo(), false, false, 0));
3072 // Calculate and remember argument location.
3073 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3078 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3079 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3080 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3081 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3082 MachineFunction &MF = DAG.getMachineFunction();
3084 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3085 // might overwrite each other in case of tail call optimization.
3086 SmallVector<SDValue, 8> MemOpChains2;
3087 // Do not flag preceding copytoreg stuff together with the following stuff.
3089 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3091 if (!MemOpChains2.empty())
3092 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3093 &MemOpChains2[0], MemOpChains2.size());
3095 // Store the return address to the appropriate stack slot.
3096 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3097 isPPC64, isDarwinABI, dl);
3099 // Emit callseq_end just before tailcall node.
3100 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3101 DAG.getIntPtrConstant(0, true), InFlag);
3102 InFlag = Chain.getValue(1);
3106 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3107 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3108 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3109 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3110 const PPCSubtarget &PPCSubTarget) {
3112 bool isPPC64 = PPCSubTarget.isPPC64();
3113 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3115 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3116 NodeTys.push_back(MVT::Other); // Returns a chain
3117 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3119 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
3121 bool needIndirectCall = true;
3122 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3123 // If this is an absolute destination address, use the munged value.
3124 Callee = SDValue(Dest, 0);
3125 needIndirectCall = false;
3128 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3129 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3130 // Use indirect calls for ALL functions calls in JIT mode, since the
3131 // far-call stubs may be outside relocation limits for a BL instruction.
3132 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3133 unsigned OpFlags = 0;
3134 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3135 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3136 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3137 (G->getGlobal()->isDeclaration() ||
3138 G->getGlobal()->isWeakForLinker())) {
3139 // PC-relative references to external symbols should go through $stub,
3140 // unless we're building with the leopard linker or later, which
3141 // automatically synthesizes these stubs.
3142 OpFlags = PPCII::MO_DARWIN_STUB;
3145 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3146 // every direct call is) turn it into a TargetGlobalAddress /
3147 // TargetExternalSymbol node so that legalize doesn't hack it.
3148 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3149 Callee.getValueType(),
3151 needIndirectCall = false;
3155 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3156 unsigned char OpFlags = 0;
3158 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3159 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3160 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3161 // PC-relative references to external symbols should go through $stub,
3162 // unless we're building with the leopard linker or later, which
3163 // automatically synthesizes these stubs.
3164 OpFlags = PPCII::MO_DARWIN_STUB;
3167 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3169 needIndirectCall = false;
3172 if (needIndirectCall) {
3173 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3174 // to do the call, we can't use PPCISD::CALL.
3175 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3177 if (isSVR4ABI && isPPC64) {
3178 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3179 // entry point, but to the function descriptor (the function entry point
3180 // address is part of the function descriptor though).
3181 // The function descriptor is a three doubleword structure with the
3182 // following fields: function entry point, TOC base address and
3183 // environment pointer.
3184 // Thus for a call through a function pointer, the following actions need
3186 // 1. Save the TOC of the caller in the TOC save area of its stack
3187 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3188 // 2. Load the address of the function entry point from the function
3190 // 3. Load the TOC of the callee from the function descriptor into r2.
3191 // 4. Load the environment pointer from the function descriptor into
3193 // 5. Branch to the function entry point address.
3194 // 6. On return of the callee, the TOC of the caller needs to be
3195 // restored (this is done in FinishCall()).
3197 // All those operations are flagged together to ensure that no other
3198 // operations can be scheduled in between. E.g. without flagging the
3199 // operations together, a TOC access in the caller could be scheduled
3200 // between the load of the callee TOC and the branch to the callee, which
3201 // results in the TOC access going through the TOC of the callee instead
3202 // of going through the TOC of the caller, which leads to incorrect code.
3204 // Load the address of the function entry point from the function
3206 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3207 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3208 InFlag.getNode() ? 3 : 2);
3209 Chain = LoadFuncPtr.getValue(1);
3210 InFlag = LoadFuncPtr.getValue(2);
3212 // Load environment pointer into r11.
3213 // Offset of the environment pointer within the function descriptor.
3214 SDValue PtrOff = DAG.getIntPtrConstant(16);
3216 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3217 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3219 Chain = LoadEnvPtr.getValue(1);
3220 InFlag = LoadEnvPtr.getValue(2);
3222 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3224 Chain = EnvVal.getValue(0);
3225 InFlag = EnvVal.getValue(1);
3227 // Load TOC of the callee into r2. We are using a target-specific load
3228 // with r2 hard coded, because the result of a target-independent load
3229 // would never go directly into r2, since r2 is a reserved register (which
3230 // prevents the register allocator from allocating it), resulting in an
3231 // additional register being allocated and an unnecessary move instruction
3233 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3234 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3236 Chain = LoadTOCPtr.getValue(0);
3237 InFlag = LoadTOCPtr.getValue(1);
3239 MTCTROps[0] = Chain;
3240 MTCTROps[1] = LoadFuncPtr;
3241 MTCTROps[2] = InFlag;
3244 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3245 2 + (InFlag.getNode() != 0));
3246 InFlag = Chain.getValue(1);
3249 NodeTys.push_back(MVT::Other);
3250 NodeTys.push_back(MVT::Glue);
3251 Ops.push_back(Chain);
3252 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
3254 // Add CTR register as callee so a bctr can be emitted later.
3256 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3259 // If this is a direct call, pass the chain and the callee.
3260 if (Callee.getNode()) {
3261 Ops.push_back(Chain);
3262 Ops.push_back(Callee);
3264 // If this is a tail call add stack pointer delta.
3266 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3268 // Add argument registers to the end of the list so that they are known live
3270 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3271 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3272 RegsToPass[i].second.getValueType()));
3278 bool isLocalCall(const SDValue &Callee)
3280 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3281 return !G->getGlobal()->isDeclaration() &&
3282 !G->getGlobal()->isWeakForLinker();
3287 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3288 CallingConv::ID CallConv, bool isVarArg,
3289 const SmallVectorImpl<ISD::InputArg> &Ins,
3290 DebugLoc dl, SelectionDAG &DAG,
3291 SmallVectorImpl<SDValue> &InVals) const {
3293 SmallVector<CCValAssign, 16> RVLocs;
3294 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3295 getTargetMachine(), RVLocs, *DAG.getContext());
3296 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3298 // Copy all of the result registers out of their specified physreg.
3299 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3300 CCValAssign &VA = RVLocs[i];
3301 assert(VA.isRegLoc() && "Can only return in registers!");
3303 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3304 VA.getLocReg(), VA.getLocVT(), InFlag);
3305 Chain = Val.getValue(1);
3306 InFlag = Val.getValue(2);
3308 switch (VA.getLocInfo()) {
3309 default: llvm_unreachable("Unknown loc info!");
3310 case CCValAssign::Full: break;
3311 case CCValAssign::AExt:
3312 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3314 case CCValAssign::ZExt:
3315 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3316 DAG.getValueType(VA.getValVT()));
3317 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3319 case CCValAssign::SExt:
3320 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3321 DAG.getValueType(VA.getValVT()));
3322 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3326 InVals.push_back(Val);
3333 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3334 bool isTailCall, bool isVarArg,
3336 SmallVector<std::pair<unsigned, SDValue>, 8>
3338 SDValue InFlag, SDValue Chain,
3340 int SPDiff, unsigned NumBytes,
3341 const SmallVectorImpl<ISD::InputArg> &Ins,
3342 SmallVectorImpl<SDValue> &InVals) const {
3343 std::vector<EVT> NodeTys;
3344 SmallVector<SDValue, 8> Ops;
3345 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3346 isTailCall, RegsToPass, Ops, NodeTys,
3349 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3350 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3351 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3353 // When performing tail call optimization the callee pops its arguments off
3354 // the stack. Account for this here so these bytes can be pushed back on in
3355 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3356 int BytesCalleePops =
3357 (CallConv == CallingConv::Fast &&
3358 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3360 // Add a register mask operand representing the call-preserved registers.
3361 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3362 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3363 assert(Mask && "Missing call preserved mask for calling convention");
3364 Ops.push_back(DAG.getRegisterMask(Mask));
3366 if (InFlag.getNode())
3367 Ops.push_back(InFlag);
3371 assert(((Callee.getOpcode() == ISD::Register &&
3372 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3373 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3374 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3375 isa<ConstantSDNode>(Callee)) &&
3376 "Expecting an global address, external symbol, absolute value or register");
3378 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3381 // Add a NOP immediately after the branch instruction when using the 64-bit
3382 // SVR4 ABI. At link time, if caller and callee are in a different module and
3383 // thus have a different TOC, the call will be replaced with a call to a stub
3384 // function which saves the current TOC, loads the TOC of the callee and
3385 // branches to the callee. The NOP will be replaced with a load instruction
3386 // which restores the TOC of the caller from the TOC save slot of the current
3387 // stack frame. If caller and callee belong to the same module (and have the
3388 // same TOC), the NOP will remain unchanged.
3390 bool needsTOCRestore = false;
3391 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3392 if (CallOpc == PPCISD::BCTRL_SVR4) {
3393 // This is a call through a function pointer.
3394 // Restore the caller TOC from the save area into R2.
3395 // See PrepareCall() for more information about calls through function
3396 // pointers in the 64-bit SVR4 ABI.
3397 // We are using a target-specific load with r2 hard coded, because the
3398 // result of a target-independent load would never go directly into r2,
3399 // since r2 is a reserved register (which prevents the register allocator
3400 // from allocating it), resulting in an additional register being
3401 // allocated and an unnecessary move instruction being generated.
3402 needsTOCRestore = true;
3403 } else if ((CallOpc == PPCISD::CALL_SVR4) && !isLocalCall(Callee)) {
3404 // Otherwise insert NOP for non-local calls.
3405 CallOpc = PPCISD::CALL_NOP_SVR4;
3409 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3410 InFlag = Chain.getValue(1);
3412 if (needsTOCRestore) {
3413 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3414 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3415 InFlag = Chain.getValue(1);
3418 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3419 DAG.getIntPtrConstant(BytesCalleePops, true),
3422 InFlag = Chain.getValue(1);
3424 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3425 Ins, dl, DAG, InVals);
3429 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3430 SmallVectorImpl<SDValue> &InVals) const {
3431 SelectionDAG &DAG = CLI.DAG;
3432 DebugLoc &dl = CLI.DL;
3433 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3434 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3435 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3436 SDValue Chain = CLI.Chain;
3437 SDValue Callee = CLI.Callee;
3438 bool &isTailCall = CLI.IsTailCall;
3439 CallingConv::ID CallConv = CLI.CallConv;
3440 bool isVarArg = CLI.IsVarArg;
3443 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3446 if (PPCSubTarget.isSVR4ABI()) {
3447 if (PPCSubTarget.isPPC64())
3448 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3449 isTailCall, Outs, OutVals, Ins,
3452 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3453 isTailCall, Outs, OutVals, Ins,
3457 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3458 isTailCall, Outs, OutVals, Ins,
3463 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3464 CallingConv::ID CallConv, bool isVarArg,
3466 const SmallVectorImpl<ISD::OutputArg> &Outs,
3467 const SmallVectorImpl<SDValue> &OutVals,
3468 const SmallVectorImpl<ISD::InputArg> &Ins,
3469 DebugLoc dl, SelectionDAG &DAG,
3470 SmallVectorImpl<SDValue> &InVals) const {
3471 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3472 // of the 32-bit SVR4 ABI stack frame layout.
3474 assert((CallConv == CallingConv::C ||
3475 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3477 unsigned PtrByteSize = 4;
3479 MachineFunction &MF = DAG.getMachineFunction();
3481 // Mark this function as potentially containing a function that contains a
3482 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3483 // and restoring the callers stack pointer in this functions epilog. This is
3484 // done because by tail calling the called function might overwrite the value
3485 // in this function's (MF) stack pointer stack slot 0(SP).
3486 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3487 CallConv == CallingConv::Fast)
3488 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3490 // Count how many bytes are to be pushed on the stack, including the linkage
3491 // area, parameter list area and the part of the local variable space which
3492 // contains copies of aggregates which are passed by value.
3494 // Assign locations to all of the outgoing arguments.
3495 SmallVector<CCValAssign, 16> ArgLocs;
3496 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3497 getTargetMachine(), ArgLocs, *DAG.getContext());
3499 // Reserve space for the linkage area on the stack.
3500 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3503 // Handle fixed and variable vector arguments differently.
3504 // Fixed vector arguments go into registers as long as registers are
3505 // available. Variable vector arguments always go into memory.
3506 unsigned NumArgs = Outs.size();
3508 for (unsigned i = 0; i != NumArgs; ++i) {
3509 MVT ArgVT = Outs[i].VT;
3510 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3513 if (Outs[i].IsFixed) {
3514 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3517 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3523 errs() << "Call operand #" << i << " has unhandled type "
3524 << EVT(ArgVT).getEVTString() << "\n";
3526 llvm_unreachable(0);
3530 // All arguments are treated the same.
3531 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3534 // Assign locations to all of the outgoing aggregate by value arguments.
3535 SmallVector<CCValAssign, 16> ByValArgLocs;
3536 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3537 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3539 // Reserve stack space for the allocations in CCInfo.
3540 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3542 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3544 // Size of the linkage area, parameter list area and the part of the local
3545 // space variable where copies of aggregates which are passed by value are
3547 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3549 // Calculate by how many bytes the stack has to be adjusted in case of tail
3550 // call optimization.
3551 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3553 // Adjust the stack pointer for the new arguments...
3554 // These operations are automatically eliminated by the prolog/epilog pass
3555 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3556 SDValue CallSeqStart = Chain;
3558 // Load the return address and frame pointer so it can be moved somewhere else
3561 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3564 // Set up a copy of the stack pointer for use loading and storing any
3565 // arguments that may not fit in the registers available for argument
3567 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3569 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3570 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3571 SmallVector<SDValue, 8> MemOpChains;
3573 bool seenFloatArg = false;
3574 // Walk the register/memloc assignments, inserting copies/loads.
3575 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3578 CCValAssign &VA = ArgLocs[i];
3579 SDValue Arg = OutVals[i];
3580 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3582 if (Flags.isByVal()) {
3583 // Argument is an aggregate which is passed by value, thus we need to
3584 // create a copy of it in the local variable space of the current stack
3585 // frame (which is the stack frame of the caller) and pass the address of
3586 // this copy to the callee.
3587 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3588 CCValAssign &ByValVA = ByValArgLocs[j++];
3589 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3591 // Memory reserved in the local variable space of the callers stack frame.
3592 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3594 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3595 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3597 // Create a copy of the argument in the local area of the current
3599 SDValue MemcpyCall =
3600 CreateCopyOfByValArgument(Arg, PtrOff,
3601 CallSeqStart.getNode()->getOperand(0),
3604 // This must go outside the CALLSEQ_START..END.
3605 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3606 CallSeqStart.getNode()->getOperand(1));
3607 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3608 NewCallSeqStart.getNode());
3609 Chain = CallSeqStart = NewCallSeqStart;
3611 // Pass the address of the aggregate copy on the stack either in a
3612 // physical register or in the parameter list area of the current stack
3613 // frame to the callee.
3617 if (VA.isRegLoc()) {
3618 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3619 // Put argument in a physical register.
3620 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3622 // Put argument in the parameter list area of the current stack frame.
3623 assert(VA.isMemLoc());
3624 unsigned LocMemOffset = VA.getLocMemOffset();
3627 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3628 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3630 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3631 MachinePointerInfo(),
3634 // Calculate and remember argument location.
3635 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3641 if (!MemOpChains.empty())
3642 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3643 &MemOpChains[0], MemOpChains.size());
3645 // Build a sequence of copy-to-reg nodes chained together with token chain
3646 // and flag operands which copy the outgoing args into the appropriate regs.
3648 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3649 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3650 RegsToPass[i].second, InFlag);
3651 InFlag = Chain.getValue(1);
3654 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3657 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3658 SDValue Ops[] = { Chain, InFlag };
3660 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3661 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3663 InFlag = Chain.getValue(1);
3667 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3668 false, TailCallArguments);
3670 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3671 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3675 // Copy an argument into memory, being careful to do this outside the
3676 // call sequence for the call to which the argument belongs.
3678 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3679 SDValue CallSeqStart,
3680 ISD::ArgFlagsTy Flags,
3682 DebugLoc dl) const {
3683 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3684 CallSeqStart.getNode()->getOperand(0),
3686 // The MEMCPY must go outside the CALLSEQ_START..END.
3687 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3688 CallSeqStart.getNode()->getOperand(1));
3689 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3690 NewCallSeqStart.getNode());
3691 return NewCallSeqStart;
3695 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3696 CallingConv::ID CallConv, bool isVarArg,
3698 const SmallVectorImpl<ISD::OutputArg> &Outs,
3699 const SmallVectorImpl<SDValue> &OutVals,
3700 const SmallVectorImpl<ISD::InputArg> &Ins,
3701 DebugLoc dl, SelectionDAG &DAG,
3702 SmallVectorImpl<SDValue> &InVals) const {
3704 unsigned NumOps = Outs.size();
3706 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3707 unsigned PtrByteSize = 8;
3709 MachineFunction &MF = DAG.getMachineFunction();
3711 // Mark this function as potentially containing a function that contains a
3712 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3713 // and restoring the callers stack pointer in this functions epilog. This is
3714 // done because by tail calling the called function might overwrite the value
3715 // in this function's (MF) stack pointer stack slot 0(SP).
3716 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3717 CallConv == CallingConv::Fast)
3718 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3720 unsigned nAltivecParamsAtEnd = 0;
3722 // Count how many bytes are to be pushed on the stack, including the linkage
3723 // area, and parameter passing area. We start with at least 48 bytes, which
3724 // is reserved space for [SP][CR][LR][3 x unused].
3725 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3728 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3729 Outs, OutVals, nAltivecParamsAtEnd);
3731 // Calculate by how many bytes the stack has to be adjusted in case of tail
3732 // call optimization.
3733 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3735 // To protect arguments on the stack from being clobbered in a tail call,
3736 // force all the loads to happen before doing any other lowering.
3738 Chain = DAG.getStackArgumentTokenFactor(Chain);
3740 // Adjust the stack pointer for the new arguments...
3741 // These operations are automatically eliminated by the prolog/epilog pass
3742 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3743 SDValue CallSeqStart = Chain;
3745 // Load the return address and frame pointer so it can be move somewhere else
3748 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3751 // Set up a copy of the stack pointer for use loading and storing any
3752 // arguments that may not fit in the registers available for argument
3754 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3756 // Figure out which arguments are going to go in registers, and which in
3757 // memory. Also, if this is a vararg function, floating point operations
3758 // must be stored to our stack, and loaded into integer regs as well, if
3759 // any integer regs are available for argument passing.
3760 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3761 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3763 static const uint16_t GPR[] = {
3764 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3765 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3767 static const uint16_t *FPR = GetFPR();
3769 static const uint16_t VR[] = {
3770 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3771 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3773 const unsigned NumGPRs = array_lengthof(GPR);
3774 const unsigned NumFPRs = 13;
3775 const unsigned NumVRs = array_lengthof(VR);
3777 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3778 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3780 SmallVector<SDValue, 8> MemOpChains;
3781 for (unsigned i = 0; i != NumOps; ++i) {
3782 SDValue Arg = OutVals[i];
3783 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3785 // PtrOff will be used to store the current argument to the stack if a
3786 // register cannot be found for it.
3789 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3791 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3793 // Promote integers to 64-bit values.
3794 if (Arg.getValueType() == MVT::i32) {
3795 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3796 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3797 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3800 // FIXME memcpy is used way more than necessary. Correctness first.
3801 // Note: "by value" is code for passing a structure by value, not
3803 if (Flags.isByVal()) {
3804 // Note: Size includes alignment padding, so
3805 // struct x { short a; char b; }
3806 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3807 // These are the proper values we need for right-justifying the
3808 // aggregate in a parameter register.
3809 unsigned Size = Flags.getByValSize();
3811 // An empty aggregate parameter takes up no storage and no
3816 // All aggregates smaller than 8 bytes must be passed right-justified.
3817 if (Size==1 || Size==2 || Size==4) {
3818 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3819 if (GPR_idx != NumGPRs) {
3820 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3821 MachinePointerInfo(), VT,
3823 MemOpChains.push_back(Load.getValue(1));
3824 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3826 ArgOffset += PtrByteSize;
3831 if (GPR_idx == NumGPRs && Size < 8) {
3832 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3833 PtrOff.getValueType());
3834 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3835 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3838 ArgOffset += PtrByteSize;
3841 // Copy entire object into memory. There are cases where gcc-generated
3842 // code assumes it is there, even if it could be put entirely into
3843 // registers. (This is not what the doc says.)
3845 // FIXME: The above statement is likely due to a misunderstanding of the
3846 // documents. All arguments must be copied into the parameter area BY
3847 // THE CALLEE in the event that the callee takes the address of any
3848 // formal argument. That has not yet been implemented. However, it is
3849 // reasonable to use the stack area as a staging area for the register
3852 // Skip this for small aggregates, as we will use the same slot for a
3853 // right-justified copy, below.
3855 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3859 // When a register is available, pass a small aggregate right-justified.
3860 if (Size < 8 && GPR_idx != NumGPRs) {
3861 // The easiest way to get this right-justified in a register
3862 // is to copy the structure into the rightmost portion of a
3863 // local variable slot, then load the whole slot into the
3865 // FIXME: The memcpy seems to produce pretty awful code for
3866 // small aggregates, particularly for packed ones.
3867 // FIXME: It would be preferable to use the slot in the
3868 // parameter save area instead of a new local variable.
3869 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3870 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3871 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3875 // Load the slot into the register.
3876 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3877 MachinePointerInfo(),
3878 false, false, false, 0);
3879 MemOpChains.push_back(Load.getValue(1));
3880 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3882 // Done with this argument.
3883 ArgOffset += PtrByteSize;
3887 // For aggregates larger than PtrByteSize, copy the pieces of the
3888 // object that fit into registers from the parameter save area.
3889 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3890 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3891 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3892 if (GPR_idx != NumGPRs) {
3893 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3894 MachinePointerInfo(),
3895 false, false, false, 0);
3896 MemOpChains.push_back(Load.getValue(1));
3897 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3898 ArgOffset += PtrByteSize;
3900 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3907 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3908 default: llvm_unreachable("Unexpected ValueType for argument!");
3911 if (GPR_idx != NumGPRs) {
3912 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3914 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3915 true, isTailCall, false, MemOpChains,
3916 TailCallArguments, dl);
3918 ArgOffset += PtrByteSize;
3922 if (FPR_idx != NumFPRs) {
3923 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3926 // A single float or an aggregate containing only a single float
3927 // must be passed right-justified in the stack doubleword, and
3928 // in the GPR, if one is available.
3930 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3931 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3932 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3936 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3937 MachinePointerInfo(), false, false, 0);
3938 MemOpChains.push_back(Store);
3940 // Float varargs are always shadowed in available integer registers
3941 if (GPR_idx != NumGPRs) {
3942 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3943 MachinePointerInfo(), false, false,
3945 MemOpChains.push_back(Load.getValue(1));
3946 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3948 } else if (GPR_idx != NumGPRs)
3949 // If we have any FPRs remaining, we may also have GPRs remaining.
3952 // Single-precision floating-point values are mapped to the
3953 // second (rightmost) word of the stack doubleword.
3954 if (Arg.getValueType() == MVT::f32) {
3955 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3956 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3959 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3960 true, isTailCall, false, MemOpChains,
3961 TailCallArguments, dl);
3970 // These go aligned on the stack, or in the corresponding R registers
3971 // when within range. The Darwin PPC ABI doc claims they also go in
3972 // V registers; in fact gcc does this only for arguments that are
3973 // prototyped, not for those that match the ... We do it for all
3974 // arguments, seems to work.
3975 while (ArgOffset % 16 !=0) {
3976 ArgOffset += PtrByteSize;
3977 if (GPR_idx != NumGPRs)
3980 // We could elide this store in the case where the object fits
3981 // entirely in R registers. Maybe later.
3982 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3983 DAG.getConstant(ArgOffset, PtrVT));
3984 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3985 MachinePointerInfo(), false, false, 0);
3986 MemOpChains.push_back(Store);
3987 if (VR_idx != NumVRs) {
3988 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3989 MachinePointerInfo(),
3990 false, false, false, 0);
3991 MemOpChains.push_back(Load.getValue(1));
3992 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3995 for (unsigned i=0; i<16; i+=PtrByteSize) {
3996 if (GPR_idx == NumGPRs)
3998 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3999 DAG.getConstant(i, PtrVT));
4000 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4001 false, false, false, 0);
4002 MemOpChains.push_back(Load.getValue(1));
4003 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4008 // Non-varargs Altivec params generally go in registers, but have
4009 // stack space allocated at the end.
4010 if (VR_idx != NumVRs) {
4011 // Doesn't have GPR space allocated.
4012 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4014 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4015 true, isTailCall, true, MemOpChains,
4016 TailCallArguments, dl);
4023 if (!MemOpChains.empty())
4024 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4025 &MemOpChains[0], MemOpChains.size());
4027 // Check if this is an indirect call (MTCTR/BCTRL).
4028 // See PrepareCall() for more information about calls through function
4029 // pointers in the 64-bit SVR4 ABI.
4031 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4032 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4033 !isBLACompatibleAddress(Callee, DAG)) {
4034 // Load r2 into a virtual register and store it to the TOC save area.
4035 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4036 // TOC save area offset.
4037 SDValue PtrOff = DAG.getIntPtrConstant(40);
4038 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4039 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4041 // R12 must contain the address of an indirect callee. This does not
4042 // mean the MTCTR instruction must use R12; it's easier to model this
4043 // as an extra parameter, so do that.
4044 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4047 // Build a sequence of copy-to-reg nodes chained together with token chain
4048 // and flag operands which copy the outgoing args into the appropriate regs.
4050 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4051 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4052 RegsToPass[i].second, InFlag);
4053 InFlag = Chain.getValue(1);
4057 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4058 FPOp, true, TailCallArguments);
4060 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4061 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4066 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4067 CallingConv::ID CallConv, bool isVarArg,
4069 const SmallVectorImpl<ISD::OutputArg> &Outs,
4070 const SmallVectorImpl<SDValue> &OutVals,
4071 const SmallVectorImpl<ISD::InputArg> &Ins,
4072 DebugLoc dl, SelectionDAG &DAG,
4073 SmallVectorImpl<SDValue> &InVals) const {
4075 unsigned NumOps = Outs.size();
4077 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4078 bool isPPC64 = PtrVT == MVT::i64;
4079 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4081 MachineFunction &MF = DAG.getMachineFunction();
4083 // Mark this function as potentially containing a function that contains a
4084 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4085 // and restoring the callers stack pointer in this functions epilog. This is
4086 // done because by tail calling the called function might overwrite the value
4087 // in this function's (MF) stack pointer stack slot 0(SP).
4088 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4089 CallConv == CallingConv::Fast)
4090 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4092 unsigned nAltivecParamsAtEnd = 0;
4094 // Count how many bytes are to be pushed on the stack, including the linkage
4095 // area, and parameter passing area. We start with 24/48 bytes, which is
4096 // prereserved space for [SP][CR][LR][3 x unused].
4098 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4100 nAltivecParamsAtEnd);
4102 // Calculate by how many bytes the stack has to be adjusted in case of tail
4103 // call optimization.
4104 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4106 // To protect arguments on the stack from being clobbered in a tail call,
4107 // force all the loads to happen before doing any other lowering.
4109 Chain = DAG.getStackArgumentTokenFactor(Chain);
4111 // Adjust the stack pointer for the new arguments...
4112 // These operations are automatically eliminated by the prolog/epilog pass
4113 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4114 SDValue CallSeqStart = Chain;
4116 // Load the return address and frame pointer so it can be move somewhere else
4119 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4122 // Set up a copy of the stack pointer for use loading and storing any
4123 // arguments that may not fit in the registers available for argument
4127 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4129 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4131 // Figure out which arguments are going to go in registers, and which in
4132 // memory. Also, if this is a vararg function, floating point operations
4133 // must be stored to our stack, and loaded into integer regs as well, if
4134 // any integer regs are available for argument passing.
4135 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4136 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4138 static const uint16_t GPR_32[] = { // 32-bit registers.
4139 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4140 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4142 static const uint16_t GPR_64[] = { // 64-bit registers.
4143 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4144 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4146 static const uint16_t *FPR = GetFPR();
4148 static const uint16_t VR[] = {
4149 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4150 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4152 const unsigned NumGPRs = array_lengthof(GPR_32);
4153 const unsigned NumFPRs = 13;
4154 const unsigned NumVRs = array_lengthof(VR);
4156 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4158 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4159 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4161 SmallVector<SDValue, 8> MemOpChains;
4162 for (unsigned i = 0; i != NumOps; ++i) {
4163 SDValue Arg = OutVals[i];
4164 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4166 // PtrOff will be used to store the current argument to the stack if a
4167 // register cannot be found for it.
4170 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4172 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4174 // On PPC64, promote integers to 64-bit values.
4175 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4176 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4177 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4178 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4181 // FIXME memcpy is used way more than necessary. Correctness first.
4182 // Note: "by value" is code for passing a structure by value, not
4184 if (Flags.isByVal()) {
4185 unsigned Size = Flags.getByValSize();
4186 // Very small objects are passed right-justified. Everything else is
4187 // passed left-justified.
4188 if (Size==1 || Size==2) {
4189 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4190 if (GPR_idx != NumGPRs) {
4191 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4192 MachinePointerInfo(), VT,
4194 MemOpChains.push_back(Load.getValue(1));
4195 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4197 ArgOffset += PtrByteSize;
4199 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4200 PtrOff.getValueType());
4201 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4202 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4205 ArgOffset += PtrByteSize;
4209 // Copy entire object into memory. There are cases where gcc-generated
4210 // code assumes it is there, even if it could be put entirely into
4211 // registers. (This is not what the doc says.)
4212 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4216 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4217 // copy the pieces of the object that fit into registers from the
4218 // parameter save area.
4219 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4220 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4221 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4222 if (GPR_idx != NumGPRs) {
4223 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4224 MachinePointerInfo(),
4225 false, false, false, 0);
4226 MemOpChains.push_back(Load.getValue(1));
4227 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4228 ArgOffset += PtrByteSize;
4230 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4237 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4238 default: llvm_unreachable("Unexpected ValueType for argument!");
4241 if (GPR_idx != NumGPRs) {
4242 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4244 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4245 isPPC64, isTailCall, false, MemOpChains,
4246 TailCallArguments, dl);
4248 ArgOffset += PtrByteSize;
4252 if (FPR_idx != NumFPRs) {
4253 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4256 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4257 MachinePointerInfo(), false, false, 0);
4258 MemOpChains.push_back(Store);
4260 // Float varargs are always shadowed in available integer registers
4261 if (GPR_idx != NumGPRs) {
4262 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4263 MachinePointerInfo(), false, false,
4265 MemOpChains.push_back(Load.getValue(1));
4266 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4268 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4269 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4270 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4271 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4272 MachinePointerInfo(),
4273 false, false, false, 0);
4274 MemOpChains.push_back(Load.getValue(1));
4275 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4278 // If we have any FPRs remaining, we may also have GPRs remaining.
4279 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4281 if (GPR_idx != NumGPRs)
4283 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4284 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4288 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4289 isPPC64, isTailCall, false, MemOpChains,
4290 TailCallArguments, dl);
4294 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4301 // These go aligned on the stack, or in the corresponding R registers
4302 // when within range. The Darwin PPC ABI doc claims they also go in
4303 // V registers; in fact gcc does this only for arguments that are
4304 // prototyped, not for those that match the ... We do it for all
4305 // arguments, seems to work.
4306 while (ArgOffset % 16 !=0) {
4307 ArgOffset += PtrByteSize;
4308 if (GPR_idx != NumGPRs)
4311 // We could elide this store in the case where the object fits
4312 // entirely in R registers. Maybe later.
4313 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4314 DAG.getConstant(ArgOffset, PtrVT));
4315 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4316 MachinePointerInfo(), false, false, 0);
4317 MemOpChains.push_back(Store);
4318 if (VR_idx != NumVRs) {
4319 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4320 MachinePointerInfo(),
4321 false, false, false, 0);
4322 MemOpChains.push_back(Load.getValue(1));
4323 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4326 for (unsigned i=0; i<16; i+=PtrByteSize) {
4327 if (GPR_idx == NumGPRs)
4329 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4330 DAG.getConstant(i, PtrVT));
4331 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4332 false, false, false, 0);
4333 MemOpChains.push_back(Load.getValue(1));
4334 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4339 // Non-varargs Altivec params generally go in registers, but have
4340 // stack space allocated at the end.
4341 if (VR_idx != NumVRs) {
4342 // Doesn't have GPR space allocated.
4343 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4344 } else if (nAltivecParamsAtEnd==0) {
4345 // We are emitting Altivec params in order.
4346 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4347 isPPC64, isTailCall, true, MemOpChains,
4348 TailCallArguments, dl);
4354 // If all Altivec parameters fit in registers, as they usually do,
4355 // they get stack space following the non-Altivec parameters. We
4356 // don't track this here because nobody below needs it.
4357 // If there are more Altivec parameters than fit in registers emit
4359 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4361 // Offset is aligned; skip 1st 12 params which go in V registers.
4362 ArgOffset = ((ArgOffset+15)/16)*16;
4364 for (unsigned i = 0; i != NumOps; ++i) {
4365 SDValue Arg = OutVals[i];
4366 EVT ArgType = Outs[i].VT;
4367 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4368 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4371 // We are emitting Altivec params in order.
4372 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4373 isPPC64, isTailCall, true, MemOpChains,
4374 TailCallArguments, dl);
4381 if (!MemOpChains.empty())
4382 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4383 &MemOpChains[0], MemOpChains.size());
4385 // On Darwin, R12 must contain the address of an indirect callee. This does
4386 // not mean the MTCTR instruction must use R12; it's easier to model this as
4387 // an extra parameter, so do that.
4389 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4390 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4391 !isBLACompatibleAddress(Callee, DAG))
4392 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4393 PPC::R12), Callee));
4395 // Build a sequence of copy-to-reg nodes chained together with token chain
4396 // and flag operands which copy the outgoing args into the appropriate regs.
4398 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4399 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4400 RegsToPass[i].second, InFlag);
4401 InFlag = Chain.getValue(1);
4405 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4406 FPOp, true, TailCallArguments);
4408 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4409 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4414 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4415 MachineFunction &MF, bool isVarArg,
4416 const SmallVectorImpl<ISD::OutputArg> &Outs,
4417 LLVMContext &Context) const {
4418 SmallVector<CCValAssign, 16> RVLocs;
4419 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4421 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4425 PPCTargetLowering::LowerReturn(SDValue Chain,
4426 CallingConv::ID CallConv, bool isVarArg,
4427 const SmallVectorImpl<ISD::OutputArg> &Outs,
4428 const SmallVectorImpl<SDValue> &OutVals,
4429 DebugLoc dl, SelectionDAG &DAG) const {
4431 SmallVector<CCValAssign, 16> RVLocs;
4432 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4433 getTargetMachine(), RVLocs, *DAG.getContext());
4434 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4437 SmallVector<SDValue, 4> RetOps(1, Chain);
4439 // Copy the result values into the output registers.
4440 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4441 CCValAssign &VA = RVLocs[i];
4442 assert(VA.isRegLoc() && "Can only return in registers!");
4444 SDValue Arg = OutVals[i];
4446 switch (VA.getLocInfo()) {
4447 default: llvm_unreachable("Unknown loc info!");
4448 case CCValAssign::Full: break;
4449 case CCValAssign::AExt:
4450 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4452 case CCValAssign::ZExt:
4453 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4455 case CCValAssign::SExt:
4456 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4460 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4461 Flag = Chain.getValue(1);
4462 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4465 RetOps[0] = Chain; // Update chain.
4467 // Add the flag if we have it.
4469 RetOps.push_back(Flag);
4471 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4472 &RetOps[0], RetOps.size());
4475 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4476 const PPCSubtarget &Subtarget) const {
4477 // When we pop the dynamic allocation we need to restore the SP link.
4478 DebugLoc dl = Op.getDebugLoc();
4480 // Get the corect type for pointers.
4481 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4483 // Construct the stack pointer operand.
4484 bool isPPC64 = Subtarget.isPPC64();
4485 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4486 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4488 // Get the operands for the STACKRESTORE.
4489 SDValue Chain = Op.getOperand(0);
4490 SDValue SaveSP = Op.getOperand(1);
4492 // Load the old link SP.
4493 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4494 MachinePointerInfo(),
4495 false, false, false, 0);
4497 // Restore the stack pointer.
4498 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4500 // Store the old link SP.
4501 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4508 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4509 MachineFunction &MF = DAG.getMachineFunction();
4510 bool isPPC64 = PPCSubTarget.isPPC64();
4511 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4512 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4514 // Get current frame pointer save index. The users of this index will be
4515 // primarily DYNALLOC instructions.
4516 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4517 int RASI = FI->getReturnAddrSaveIndex();
4519 // If the frame pointer save index hasn't been defined yet.
4521 // Find out what the fix offset of the frame pointer save area.
4522 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4523 // Allocate the frame index for frame pointer save area.
4524 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4526 FI->setReturnAddrSaveIndex(RASI);
4528 return DAG.getFrameIndex(RASI, PtrVT);
4532 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4533 MachineFunction &MF = DAG.getMachineFunction();
4534 bool isPPC64 = PPCSubTarget.isPPC64();
4535 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4536 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4538 // Get current frame pointer save index. The users of this index will be
4539 // primarily DYNALLOC instructions.
4540 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4541 int FPSI = FI->getFramePointerSaveIndex();
4543 // If the frame pointer save index hasn't been defined yet.
4545 // Find out what the fix offset of the frame pointer save area.
4546 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4549 // Allocate the frame index for frame pointer save area.
4550 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4552 FI->setFramePointerSaveIndex(FPSI);
4554 return DAG.getFrameIndex(FPSI, PtrVT);
4557 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4559 const PPCSubtarget &Subtarget) const {
4561 SDValue Chain = Op.getOperand(0);
4562 SDValue Size = Op.getOperand(1);
4563 DebugLoc dl = Op.getDebugLoc();
4565 // Get the corect type for pointers.
4566 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4568 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4569 DAG.getConstant(0, PtrVT), Size);
4570 // Construct a node for the frame pointer save index.
4571 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4572 // Build a DYNALLOC node.
4573 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4574 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4575 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4578 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4579 SelectionDAG &DAG) const {
4580 DebugLoc DL = Op.getDebugLoc();
4581 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4582 DAG.getVTList(MVT::i32, MVT::Other),
4583 Op.getOperand(0), Op.getOperand(1));
4586 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4587 SelectionDAG &DAG) const {
4588 DebugLoc DL = Op.getDebugLoc();
4589 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4590 Op.getOperand(0), Op.getOperand(1));
4593 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4595 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4596 // Not FP? Not a fsel.
4597 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4598 !Op.getOperand(2).getValueType().isFloatingPoint())
4601 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4603 // Cannot handle SETEQ/SETNE.
4604 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
4606 EVT ResVT = Op.getValueType();
4607 EVT CmpVT = Op.getOperand(0).getValueType();
4608 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4609 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4610 DebugLoc dl = Op.getDebugLoc();
4612 // If the RHS of the comparison is a 0.0, we don't need to do the
4613 // subtraction at all.
4614 if (isFloatingPointZero(RHS))
4616 default: break; // SETUO etc aren't handled by fsel.
4619 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4622 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4623 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4624 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4627 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4630 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4631 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4632 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4633 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4638 default: break; // SETUO etc aren't handled by fsel.
4641 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4642 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4643 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4644 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4647 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4648 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4649 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4650 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4653 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4654 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4655 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4656 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4659 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4660 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4661 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4662 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4667 // FIXME: Split this code up when LegalizeDAGTypes lands.
4668 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4669 DebugLoc dl) const {
4670 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4671 SDValue Src = Op.getOperand(0);
4672 if (Src.getValueType() == MVT::f32)
4673 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4676 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4677 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4679 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4684 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
4688 // Convert the FP value to an int value through memory.
4689 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
4691 // Emit a store to the stack slot.
4692 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4693 MachinePointerInfo(), false, false, 0);
4695 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4697 if (Op.getValueType() == MVT::i32)
4698 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4699 DAG.getConstant(4, FIPtr.getValueType()));
4700 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
4701 false, false, false, 0);
4704 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
4705 SelectionDAG &DAG) const {
4706 DebugLoc dl = Op.getDebugLoc();
4707 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4708 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4711 if (Op.getOperand(0).getValueType() == MVT::i64) {
4712 SDValue SINT = Op.getOperand(0);
4713 // When converting to single-precision, we actually need to convert
4714 // to double-precision first and then round to single-precision.
4715 // To avoid double-rounding effects during that operation, we have
4716 // to prepare the input operand. Bits that might be truncated when
4717 // converting to double-precision are replaced by a bit that won't
4718 // be lost at this stage, but is below the single-precision rounding
4721 // However, if -enable-unsafe-fp-math is in effect, accept double
4722 // rounding to avoid the extra overhead.
4723 if (Op.getValueType() == MVT::f32 &&
4724 !DAG.getTarget().Options.UnsafeFPMath) {
4726 // Twiddle input to make sure the low 11 bits are zero. (If this
4727 // is the case, we are guaranteed the value will fit into the 53 bit
4728 // mantissa of an IEEE double-precision value without rounding.)
4729 // If any of those low 11 bits were not zero originally, make sure
4730 // bit 12 (value 2048) is set instead, so that the final rounding
4731 // to single-precision gets the correct result.
4732 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4733 SINT, DAG.getConstant(2047, MVT::i64));
4734 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4735 Round, DAG.getConstant(2047, MVT::i64));
4736 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4737 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4738 Round, DAG.getConstant(-2048, MVT::i64));
4740 // However, we cannot use that value unconditionally: if the magnitude
4741 // of the input value is small, the bit-twiddling we did above might
4742 // end up visibly changing the output. Fortunately, in that case, we
4743 // don't need to twiddle bits since the original input will convert
4744 // exactly to double-precision floating-point already. Therefore,
4745 // construct a conditional to use the original value if the top 11
4746 // bits are all sign-bit copies, and use the rounded value computed
4748 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4749 SINT, DAG.getConstant(53, MVT::i32));
4750 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4751 Cond, DAG.getConstant(1, MVT::i64));
4752 Cond = DAG.getSetCC(dl, MVT::i32,
4753 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4755 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4757 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4758 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
4759 if (Op.getValueType() == MVT::f32)
4760 FP = DAG.getNode(ISD::FP_ROUND, dl,
4761 MVT::f32, FP, DAG.getIntPtrConstant(0));
4765 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4766 "Unhandled SINT_TO_FP type in custom expander!");
4767 // Since we only generate this in 64-bit mode, we can take advantage of
4768 // 64-bit registers. In particular, sign extend the input value into the
4769 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4770 // then lfd it and fcfid it.
4771 MachineFunction &MF = DAG.getMachineFunction();
4772 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4773 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4774 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4775 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4777 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
4780 // STD the extended value into the stack slot.
4781 MachineMemOperand *MMO =
4782 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4783 MachineMemOperand::MOStore, 8, 8);
4784 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
4786 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
4787 Ops, 4, MVT::i64, MMO);
4788 // Load the value as a double.
4789 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
4790 false, false, false, 0);
4792 // FCFID it and return it.
4793 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
4794 if (Op.getValueType() == MVT::f32)
4795 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4799 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4800 SelectionDAG &DAG) const {
4801 DebugLoc dl = Op.getDebugLoc();
4803 The rounding mode is in bits 30:31 of FPSR, and has the following
4810 FLT_ROUNDS, on the other hand, expects the following:
4817 To perform the conversion, we do:
4818 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4821 MachineFunction &MF = DAG.getMachineFunction();
4822 EVT VT = Op.getValueType();
4823 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4824 SDValue MFFSreg, InFlag;
4826 // Save FP Control Word to register
4828 MVT::f64, // return register
4829 MVT::Glue // unused in this context
4831 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4833 // Save FP register to stack slot
4834 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4835 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4836 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4837 StackSlot, MachinePointerInfo(), false, false,0);
4839 // Load FP Control Word from low 32 bits of stack slot.
4840 SDValue Four = DAG.getConstant(4, PtrVT);
4841 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4842 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4843 false, false, false, 0);
4845 // Transform as necessary
4847 DAG.getNode(ISD::AND, dl, MVT::i32,
4848 CWD, DAG.getConstant(3, MVT::i32));
4850 DAG.getNode(ISD::SRL, dl, MVT::i32,
4851 DAG.getNode(ISD::AND, dl, MVT::i32,
4852 DAG.getNode(ISD::XOR, dl, MVT::i32,
4853 CWD, DAG.getConstant(3, MVT::i32)),
4854 DAG.getConstant(3, MVT::i32)),
4855 DAG.getConstant(1, MVT::i32));
4858 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4860 return DAG.getNode((VT.getSizeInBits() < 16 ?
4861 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4864 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4865 EVT VT = Op.getValueType();
4866 unsigned BitWidth = VT.getSizeInBits();
4867 DebugLoc dl = Op.getDebugLoc();
4868 assert(Op.getNumOperands() == 3 &&
4869 VT == Op.getOperand(1).getValueType() &&
4872 // Expand into a bunch of logical ops. Note that these ops
4873 // depend on the PPC behavior for oversized shift amounts.
4874 SDValue Lo = Op.getOperand(0);
4875 SDValue Hi = Op.getOperand(1);
4876 SDValue Amt = Op.getOperand(2);
4877 EVT AmtVT = Amt.getValueType();
4879 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4880 DAG.getConstant(BitWidth, AmtVT), Amt);
4881 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4882 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4883 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
4884 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4885 DAG.getConstant(-BitWidth, AmtVT));
4886 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
4887 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4888 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
4889 SDValue OutOps[] = { OutLo, OutHi };
4890 return DAG.getMergeValues(OutOps, 2, dl);
4893 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4894 EVT VT = Op.getValueType();
4895 DebugLoc dl = Op.getDebugLoc();
4896 unsigned BitWidth = VT.getSizeInBits();
4897 assert(Op.getNumOperands() == 3 &&
4898 VT == Op.getOperand(1).getValueType() &&
4901 // Expand into a bunch of logical ops. Note that these ops
4902 // depend on the PPC behavior for oversized shift amounts.
4903 SDValue Lo = Op.getOperand(0);
4904 SDValue Hi = Op.getOperand(1);
4905 SDValue Amt = Op.getOperand(2);
4906 EVT AmtVT = Amt.getValueType();
4908 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4909 DAG.getConstant(BitWidth, AmtVT), Amt);
4910 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4911 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4912 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4913 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4914 DAG.getConstant(-BitWidth, AmtVT));
4915 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
4916 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4917 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
4918 SDValue OutOps[] = { OutLo, OutHi };
4919 return DAG.getMergeValues(OutOps, 2, dl);
4922 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
4923 DebugLoc dl = Op.getDebugLoc();
4924 EVT VT = Op.getValueType();
4925 unsigned BitWidth = VT.getSizeInBits();
4926 assert(Op.getNumOperands() == 3 &&
4927 VT == Op.getOperand(1).getValueType() &&
4930 // Expand into a bunch of logical ops, followed by a select_cc.
4931 SDValue Lo = Op.getOperand(0);
4932 SDValue Hi = Op.getOperand(1);
4933 SDValue Amt = Op.getOperand(2);
4934 EVT AmtVT = Amt.getValueType();
4936 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4937 DAG.getConstant(BitWidth, AmtVT), Amt);
4938 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4939 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4940 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4941 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4942 DAG.getConstant(-BitWidth, AmtVT));
4943 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
4944 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
4945 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
4946 Tmp4, Tmp6, ISD::SETLE);
4947 SDValue OutOps[] = { OutLo, OutHi };
4948 return DAG.getMergeValues(OutOps, 2, dl);
4951 //===----------------------------------------------------------------------===//
4952 // Vector related lowering.
4955 /// BuildSplatI - Build a canonical splati of Val with an element size of
4956 /// SplatSize. Cast the result to VT.
4957 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
4958 SelectionDAG &DAG, DebugLoc dl) {
4959 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
4961 static const EVT VTys[] = { // canonical VT to use for each size.
4962 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
4965 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
4967 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
4971 EVT CanonicalVT = VTys[SplatSize-1];
4973 // Build a canonical splat for this value.
4974 SDValue Elt = DAG.getConstant(Val, MVT::i32);
4975 SmallVector<SDValue, 8> Ops;
4976 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
4977 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
4978 &Ops[0], Ops.size());
4979 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
4982 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
4983 /// specified intrinsic ID.
4984 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
4985 SelectionDAG &DAG, DebugLoc dl,
4986 EVT DestVT = MVT::Other) {
4987 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
4988 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4989 DAG.getConstant(IID, MVT::i32), LHS, RHS);
4992 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
4993 /// specified intrinsic ID.
4994 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
4995 SDValue Op2, SelectionDAG &DAG,
4996 DebugLoc dl, EVT DestVT = MVT::Other) {
4997 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
4998 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4999 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5003 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5004 /// amount. The result has the specified value type.
5005 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5006 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
5007 // Force LHS/RHS to be the right type.
5008 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5009 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5012 for (unsigned i = 0; i != 16; ++i)
5014 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5015 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5018 // If this is a case we can't handle, return null and let the default
5019 // expansion code take care of it. If we CAN select this case, and if it
5020 // selects to a single instruction, return Op. Otherwise, if we can codegen
5021 // this case more efficiently than a constant pool load, lower it to the
5022 // sequence of ops that should be used.
5023 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5024 SelectionDAG &DAG) const {
5025 DebugLoc dl = Op.getDebugLoc();
5026 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5027 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5029 // Check if this is a splat of a constant value.
5030 APInt APSplatBits, APSplatUndef;
5031 unsigned SplatBitSize;
5033 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5034 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5037 unsigned SplatBits = APSplatBits.getZExtValue();
5038 unsigned SplatUndef = APSplatUndef.getZExtValue();
5039 unsigned SplatSize = SplatBitSize / 8;
5041 // First, handle single instruction cases.
5044 if (SplatBits == 0) {
5045 // Canonicalize all zero vectors to be v4i32.
5046 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5047 SDValue Z = DAG.getConstant(0, MVT::i32);
5048 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5049 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5054 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5055 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5057 if (SextVal >= -16 && SextVal <= 15)
5058 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5061 // Two instruction sequences.
5063 // If this value is in the range [-32,30] and is even, use:
5064 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5065 // If this value is in the range [17,31] and is odd, use:
5066 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5067 // If this value is in the range [-31,-17] and is odd, use:
5068 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5069 // Note the last two are three-instruction sequences.
5070 if (SextVal >= -32 && SextVal <= 31) {
5071 // To avoid having these optimizations undone by constant folding,
5072 // we convert to a pseudo that will be expanded later into one of
5074 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5075 EVT VT = Op.getValueType();
5076 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5077 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5078 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5081 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5082 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5084 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5085 // Make -1 and vspltisw -1:
5086 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5088 // Make the VSLW intrinsic, computing 0x8000_0000.
5089 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5092 // xor by OnesV to invert it.
5093 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5094 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5097 // Check to see if this is a wide variety of vsplti*, binop self cases.
5098 static const signed char SplatCsts[] = {
5099 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5100 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5103 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5104 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5105 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5106 int i = SplatCsts[idx];
5108 // Figure out what shift amount will be used by altivec if shifted by i in
5110 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5112 // vsplti + shl self.
5113 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5114 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5115 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5116 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5117 Intrinsic::ppc_altivec_vslw
5119 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5120 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5123 // vsplti + srl self.
5124 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5125 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5126 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5127 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5128 Intrinsic::ppc_altivec_vsrw
5130 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5131 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5134 // vsplti + sra self.
5135 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5136 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5137 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5138 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5139 Intrinsic::ppc_altivec_vsraw
5141 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5142 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5145 // vsplti + rol self.
5146 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5147 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5148 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5149 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5150 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5151 Intrinsic::ppc_altivec_vrlw
5153 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5154 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5157 // t = vsplti c, result = vsldoi t, t, 1
5158 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5159 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5160 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5162 // t = vsplti c, result = vsldoi t, t, 2
5163 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5164 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5165 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5167 // t = vsplti c, result = vsldoi t, t, 3
5168 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5169 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5170 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5177 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5178 /// the specified operations to build the shuffle.
5179 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5180 SDValue RHS, SelectionDAG &DAG,
5182 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5183 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5184 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5187 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5199 if (OpNum == OP_COPY) {
5200 if (LHSID == (1*9+2)*9+3) return LHS;
5201 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5205 SDValue OpLHS, OpRHS;
5206 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5207 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5211 default: llvm_unreachable("Unknown i32 permute!");
5213 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5214 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5215 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5216 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5219 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5220 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5221 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5222 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5225 for (unsigned i = 0; i != 16; ++i)
5226 ShufIdxs[i] = (i&3)+0;
5229 for (unsigned i = 0; i != 16; ++i)
5230 ShufIdxs[i] = (i&3)+4;
5233 for (unsigned i = 0; i != 16; ++i)
5234 ShufIdxs[i] = (i&3)+8;
5237 for (unsigned i = 0; i != 16; ++i)
5238 ShufIdxs[i] = (i&3)+12;
5241 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5243 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5245 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5247 EVT VT = OpLHS.getValueType();
5248 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5249 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5250 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5251 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5254 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5255 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5256 /// return the code it can be lowered into. Worst case, it can always be
5257 /// lowered into a vperm.
5258 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5259 SelectionDAG &DAG) const {
5260 DebugLoc dl = Op.getDebugLoc();
5261 SDValue V1 = Op.getOperand(0);
5262 SDValue V2 = Op.getOperand(1);
5263 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5264 EVT VT = Op.getValueType();
5266 // Cases that are handled by instructions that take permute immediates
5267 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5268 // selected by the instruction selector.
5269 if (V2.getOpcode() == ISD::UNDEF) {
5270 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5271 PPC::isSplatShuffleMask(SVOp, 2) ||
5272 PPC::isSplatShuffleMask(SVOp, 4) ||
5273 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5274 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5275 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5276 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5277 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5278 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5279 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5280 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5281 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5286 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5287 // and produce a fixed permutation. If any of these match, do not lower to
5289 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5290 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5291 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5292 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5293 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5294 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5295 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5296 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5297 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5300 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5301 // perfect shuffle table to emit an optimal matching sequence.
5302 ArrayRef<int> PermMask = SVOp->getMask();
5304 unsigned PFIndexes[4];
5305 bool isFourElementShuffle = true;
5306 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5307 unsigned EltNo = 8; // Start out undef.
5308 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5309 if (PermMask[i*4+j] < 0)
5310 continue; // Undef, ignore it.
5312 unsigned ByteSource = PermMask[i*4+j];
5313 if ((ByteSource & 3) != j) {
5314 isFourElementShuffle = false;
5319 EltNo = ByteSource/4;
5320 } else if (EltNo != ByteSource/4) {
5321 isFourElementShuffle = false;
5325 PFIndexes[i] = EltNo;
5328 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5329 // perfect shuffle vector to determine if it is cost effective to do this as
5330 // discrete instructions, or whether we should use a vperm.
5331 if (isFourElementShuffle) {
5332 // Compute the index in the perfect shuffle table.
5333 unsigned PFTableIndex =
5334 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5336 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5337 unsigned Cost = (PFEntry >> 30);
5339 // Determining when to avoid vperm is tricky. Many things affect the cost
5340 // of vperm, particularly how many times the perm mask needs to be computed.
5341 // For example, if the perm mask can be hoisted out of a loop or is already
5342 // used (perhaps because there are multiple permutes with the same shuffle
5343 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5344 // the loop requires an extra register.
5346 // As a compromise, we only emit discrete instructions if the shuffle can be
5347 // generated in 3 or fewer operations. When we have loop information
5348 // available, if this block is within a loop, we should avoid using vperm
5349 // for 3-operation perms and use a constant pool load instead.
5351 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5354 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5355 // vector that will get spilled to the constant pool.
5356 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5358 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5359 // that it is in input element units, not in bytes. Convert now.
5360 EVT EltVT = V1.getValueType().getVectorElementType();
5361 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5363 SmallVector<SDValue, 16> ResultMask;
5364 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5365 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5367 for (unsigned j = 0; j != BytesPerElement; ++j)
5368 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5372 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5373 &ResultMask[0], ResultMask.size());
5374 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5377 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5378 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5379 /// information about the intrinsic.
5380 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5382 unsigned IntrinsicID =
5383 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5386 switch (IntrinsicID) {
5387 default: return false;
5388 // Comparison predicates.
5389 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5390 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5391 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5392 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5393 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5394 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5395 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5396 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5397 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5398 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5399 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5400 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5401 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5403 // Normal Comparisons.
5404 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5405 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5406 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5407 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5408 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5409 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5410 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5411 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5412 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5413 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5414 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5415 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5416 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5421 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5422 /// lower, do it, otherwise return null.
5423 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5424 SelectionDAG &DAG) const {
5425 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5426 // opcode number of the comparison.
5427 DebugLoc dl = Op.getDebugLoc();
5430 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5431 return SDValue(); // Don't custom lower most intrinsics.
5433 // If this is a non-dot comparison, make the VCMP node and we are done.
5435 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5436 Op.getOperand(1), Op.getOperand(2),
5437 DAG.getConstant(CompareOpc, MVT::i32));
5438 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5441 // Create the PPCISD altivec 'dot' comparison node.
5443 Op.getOperand(2), // LHS
5444 Op.getOperand(3), // RHS
5445 DAG.getConstant(CompareOpc, MVT::i32)
5447 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5448 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5450 // Now that we have the comparison, emit a copy from the CR to a GPR.
5451 // This is flagged to the above dot comparison.
5452 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5453 DAG.getRegister(PPC::CR6, MVT::i32),
5454 CompNode.getValue(1));
5456 // Unpack the result based on how the target uses it.
5457 unsigned BitNo; // Bit # of CR6.
5458 bool InvertBit; // Invert result?
5459 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5460 default: // Can't happen, don't crash on invalid number though.
5461 case 0: // Return the value of the EQ bit of CR6.
5462 BitNo = 0; InvertBit = false;
5464 case 1: // Return the inverted value of the EQ bit of CR6.
5465 BitNo = 0; InvertBit = true;
5467 case 2: // Return the value of the LT bit of CR6.
5468 BitNo = 2; InvertBit = false;
5470 case 3: // Return the inverted value of the LT bit of CR6.
5471 BitNo = 2; InvertBit = true;
5475 // Shift the bit into the low position.
5476 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5477 DAG.getConstant(8-(3-BitNo), MVT::i32));
5479 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5480 DAG.getConstant(1, MVT::i32));
5482 // If we are supposed to, toggle the bit.
5484 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5485 DAG.getConstant(1, MVT::i32));
5489 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5490 SelectionDAG &DAG) const {
5491 DebugLoc dl = Op.getDebugLoc();
5492 // Create a stack slot that is 16-byte aligned.
5493 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5494 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5495 EVT PtrVT = getPointerTy();
5496 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5498 // Store the input value into Value#0 of the stack slot.
5499 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5500 Op.getOperand(0), FIdx, MachinePointerInfo(),
5503 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5504 false, false, false, 0);
5507 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5508 DebugLoc dl = Op.getDebugLoc();
5509 if (Op.getValueType() == MVT::v4i32) {
5510 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5512 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5513 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5515 SDValue RHSSwap = // = vrlw RHS, 16
5516 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5518 // Shrinkify inputs to v8i16.
5519 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5520 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5521 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5523 // Low parts multiplied together, generating 32-bit results (we ignore the
5525 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5526 LHS, RHS, DAG, dl, MVT::v4i32);
5528 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5529 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5530 // Shift the high parts up 16 bits.
5531 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5533 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5534 } else if (Op.getValueType() == MVT::v8i16) {
5535 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5537 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5539 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5540 LHS, RHS, Zero, DAG, dl);
5541 } else if (Op.getValueType() == MVT::v16i8) {
5542 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5544 // Multiply the even 8-bit parts, producing 16-bit sums.
5545 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5546 LHS, RHS, DAG, dl, MVT::v8i16);
5547 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5549 // Multiply the odd 8-bit parts, producing 16-bit sums.
5550 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5551 LHS, RHS, DAG, dl, MVT::v8i16);
5552 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5554 // Merge the results together.
5556 for (unsigned i = 0; i != 8; ++i) {
5558 Ops[i*2+1] = 2*i+1+16;
5560 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5562 llvm_unreachable("Unknown mul to lower!");
5566 /// LowerOperation - Provide custom lowering hooks for some operations.
5568 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5569 switch (Op.getOpcode()) {
5570 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5571 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5572 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5573 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5574 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5575 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5576 case ISD::SETCC: return LowerSETCC(Op, DAG);
5577 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5578 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5580 return LowerVASTART(Op, DAG, PPCSubTarget);
5583 return LowerVAARG(Op, DAG, PPCSubTarget);
5585 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5586 case ISD::DYNAMIC_STACKALLOC:
5587 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5589 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5590 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5592 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5593 case ISD::FP_TO_UINT:
5594 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5596 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5597 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5599 // Lower 64-bit shifts.
5600 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5601 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5602 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5604 // Vector-related lowering.
5605 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5606 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5607 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5608 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5609 case ISD::MUL: return LowerMUL(Op, DAG);
5611 // Frame & Return address.
5612 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5613 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5617 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5618 SmallVectorImpl<SDValue>&Results,
5619 SelectionDAG &DAG) const {
5620 const TargetMachine &TM = getTargetMachine();
5621 DebugLoc dl = N->getDebugLoc();
5622 switch (N->getOpcode()) {
5624 llvm_unreachable("Do not know how to custom type legalize this operation!");
5626 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5627 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5630 EVT VT = N->getValueType(0);
5632 if (VT == MVT::i64) {
5633 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5635 Results.push_back(NewNode);
5636 Results.push_back(NewNode.getValue(1));
5640 case ISD::FP_ROUND_INREG: {
5641 assert(N->getValueType(0) == MVT::ppcf128);
5642 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5643 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5644 MVT::f64, N->getOperand(0),
5645 DAG.getIntPtrConstant(0));
5646 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5647 MVT::f64, N->getOperand(0),
5648 DAG.getIntPtrConstant(1));
5650 // This sequence changes FPSCR to do round-to-zero, adds the two halves
5651 // of the long double, and puts FPSCR back the way it was. We do not
5652 // actually model FPSCR.
5653 std::vector<EVT> NodeTys;
5654 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
5656 NodeTys.push_back(MVT::f64); // Return register
5657 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
5658 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5659 MFFSreg = Result.getValue(0);
5660 InFlag = Result.getValue(1);
5663 NodeTys.push_back(MVT::Glue); // Returns a flag
5664 Ops[0] = DAG.getConstant(31, MVT::i32);
5666 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
5667 InFlag = Result.getValue(0);
5670 NodeTys.push_back(MVT::Glue); // Returns a flag
5671 Ops[0] = DAG.getConstant(30, MVT::i32);
5673 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
5674 InFlag = Result.getValue(0);
5677 NodeTys.push_back(MVT::f64); // result of add
5678 NodeTys.push_back(MVT::Glue); // Returns a flag
5682 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
5683 FPreg = Result.getValue(0);
5684 InFlag = Result.getValue(1);
5687 NodeTys.push_back(MVT::f64);
5688 Ops[0] = DAG.getConstant(1, MVT::i32);
5692 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
5693 FPreg = Result.getValue(0);
5695 // We know the low half is about to be thrown away, so just use something
5697 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5701 case ISD::FP_TO_SINT:
5702 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5708 //===----------------------------------------------------------------------===//
5709 // Other Lowering Code
5710 //===----------------------------------------------------------------------===//
5713 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5714 bool is64bit, unsigned BinOpcode) const {
5715 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5716 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5718 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5719 MachineFunction *F = BB->getParent();
5720 MachineFunction::iterator It = BB;
5723 unsigned dest = MI->getOperand(0).getReg();
5724 unsigned ptrA = MI->getOperand(1).getReg();
5725 unsigned ptrB = MI->getOperand(2).getReg();
5726 unsigned incr = MI->getOperand(3).getReg();
5727 DebugLoc dl = MI->getDebugLoc();
5729 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5730 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5731 F->insert(It, loopMBB);
5732 F->insert(It, exitMBB);
5733 exitMBB->splice(exitMBB->begin(), BB,
5734 llvm::next(MachineBasicBlock::iterator(MI)),
5736 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5738 MachineRegisterInfo &RegInfo = F->getRegInfo();
5739 unsigned TmpReg = (!BinOpcode) ? incr :
5740 RegInfo.createVirtualRegister(
5741 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5742 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5746 // fallthrough --> loopMBB
5747 BB->addSuccessor(loopMBB);
5750 // l[wd]arx dest, ptr
5751 // add r0, dest, incr
5752 // st[wd]cx. r0, ptr
5754 // fallthrough --> exitMBB
5756 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5757 .addReg(ptrA).addReg(ptrB);
5759 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5760 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5761 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5762 BuildMI(BB, dl, TII->get(PPC::BCC))
5763 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5764 BB->addSuccessor(loopMBB);
5765 BB->addSuccessor(exitMBB);
5774 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5775 MachineBasicBlock *BB,
5776 bool is8bit, // operation
5777 unsigned BinOpcode) const {
5778 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5779 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5780 // In 64 bit mode we have to use 64 bits for addresses, even though the
5781 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5782 // registers without caring whether they're 32 or 64, but here we're
5783 // doing actual arithmetic on the addresses.
5784 bool is64bit = PPCSubTarget.isPPC64();
5785 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5787 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5788 MachineFunction *F = BB->getParent();
5789 MachineFunction::iterator It = BB;
5792 unsigned dest = MI->getOperand(0).getReg();
5793 unsigned ptrA = MI->getOperand(1).getReg();
5794 unsigned ptrB = MI->getOperand(2).getReg();
5795 unsigned incr = MI->getOperand(3).getReg();
5796 DebugLoc dl = MI->getDebugLoc();
5798 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5799 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5800 F->insert(It, loopMBB);
5801 F->insert(It, exitMBB);
5802 exitMBB->splice(exitMBB->begin(), BB,
5803 llvm::next(MachineBasicBlock::iterator(MI)),
5805 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5807 MachineRegisterInfo &RegInfo = F->getRegInfo();
5808 const TargetRegisterClass *RC =
5809 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5810 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5811 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5812 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5813 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5814 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5815 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5816 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5817 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5818 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5819 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5820 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5821 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5823 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5827 // fallthrough --> loopMBB
5828 BB->addSuccessor(loopMBB);
5830 // The 4-byte load must be aligned, while a char or short may be
5831 // anywhere in the word. Hence all this nasty bookkeeping code.
5832 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5833 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5834 // xori shift, shift1, 24 [16]
5835 // rlwinm ptr, ptr1, 0, 0, 29
5836 // slw incr2, incr, shift
5837 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5838 // slw mask, mask2, shift
5840 // lwarx tmpDest, ptr
5841 // add tmp, tmpDest, incr2
5842 // andc tmp2, tmpDest, mask
5843 // and tmp3, tmp, mask
5844 // or tmp4, tmp3, tmp2
5847 // fallthrough --> exitMBB
5848 // srw dest, tmpDest, shift
5849 if (ptrA != ZeroReg) {
5850 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5851 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5852 .addReg(ptrA).addReg(ptrB);
5856 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5857 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5858 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5859 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5861 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5862 .addReg(Ptr1Reg).addImm(0).addImm(61);
5864 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5865 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5866 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5867 .addReg(incr).addReg(ShiftReg);
5869 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5871 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5872 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5874 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5875 .addReg(Mask2Reg).addReg(ShiftReg);
5878 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5879 .addReg(ZeroReg).addReg(PtrReg);
5881 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5882 .addReg(Incr2Reg).addReg(TmpDestReg);
5883 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5884 .addReg(TmpDestReg).addReg(MaskReg);
5885 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5886 .addReg(TmpReg).addReg(MaskReg);
5887 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5888 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5889 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5890 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5891 BuildMI(BB, dl, TII->get(PPC::BCC))
5892 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5893 BB->addSuccessor(loopMBB);
5894 BB->addSuccessor(exitMBB);
5899 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5904 llvm::MachineBasicBlock*
5905 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
5906 MachineBasicBlock *MBB) const {
5907 DebugLoc DL = MI->getDebugLoc();
5908 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5910 MachineFunction *MF = MBB->getParent();
5911 MachineRegisterInfo &MRI = MF->getRegInfo();
5913 const BasicBlock *BB = MBB->getBasicBlock();
5914 MachineFunction::iterator I = MBB;
5918 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
5919 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
5921 unsigned DstReg = MI->getOperand(0).getReg();
5922 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
5923 assert(RC->hasType(MVT::i32) && "Invalid destination!");
5924 unsigned mainDstReg = MRI.createVirtualRegister(RC);
5925 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
5927 MVT PVT = getPointerTy();
5928 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
5929 "Invalid Pointer Size!");
5930 // For v = setjmp(buf), we generate
5933 // SjLjSetup mainMBB
5939 // buf[LabelOffset] = LR
5943 // v = phi(main, restore)
5946 MachineBasicBlock *thisMBB = MBB;
5947 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
5948 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
5949 MF->insert(I, mainMBB);
5950 MF->insert(I, sinkMBB);
5952 MachineInstrBuilder MIB;
5954 // Transfer the remainder of BB and its successor edges to sinkMBB.
5955 sinkMBB->splice(sinkMBB->begin(), MBB,
5956 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
5957 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
5959 // Note that the structure of the jmp_buf used here is not compatible
5960 // with that used by libc, and is not designed to be. Specifically, it
5961 // stores only those 'reserved' registers that LLVM does not otherwise
5962 // understand how to spill. Also, by convention, by the time this
5963 // intrinsic is called, Clang has already stored the frame address in the
5964 // first slot of the buffer and stack address in the third. Following the
5965 // X86 target code, we'll store the jump address in the second slot. We also
5966 // need to save the TOC pointer (R2) to handle jumps between shared
5967 // libraries, and that will be stored in the fourth slot. The thread
5968 // identifier (R13) is not affected.
5971 const int64_t LabelOffset = 1 * PVT.getStoreSize();
5972 const int64_t TOCOffset = 3 * PVT.getStoreSize();
5974 // Prepare IP either in reg.
5975 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
5976 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
5977 unsigned BufReg = MI->getOperand(1).getReg();
5979 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
5980 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
5982 .addImm(TOCOffset / 4)
5985 MIB.setMemRefs(MMOBegin, MMOEnd);
5989 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCL)).addMBB(mainMBB);
5990 MIB.addRegMask(PPCRegInfo->getNoPreservedMask());
5992 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
5994 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
5996 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
5998 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
5999 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6003 MIB = BuildMI(mainMBB, DL,
6004 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6007 if (PPCSubTarget.isPPC64()) {
6008 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6010 .addImm(LabelOffset / 4)
6013 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6015 .addImm(LabelOffset)
6019 MIB.setMemRefs(MMOBegin, MMOEnd);
6021 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6022 mainMBB->addSuccessor(sinkMBB);
6025 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6026 TII->get(PPC::PHI), DstReg)
6027 .addReg(mainDstReg).addMBB(mainMBB)
6028 .addReg(restoreDstReg).addMBB(thisMBB);
6030 MI->eraseFromParent();
6035 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6036 MachineBasicBlock *MBB) const {
6037 DebugLoc DL = MI->getDebugLoc();
6038 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6040 MachineFunction *MF = MBB->getParent();
6041 MachineRegisterInfo &MRI = MF->getRegInfo();
6044 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6045 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6047 MVT PVT = getPointerTy();
6048 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6049 "Invalid Pointer Size!");
6051 const TargetRegisterClass *RC =
6052 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6053 unsigned Tmp = MRI.createVirtualRegister(RC);
6054 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6055 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6056 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6058 MachineInstrBuilder MIB;
6060 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6061 const int64_t SPOffset = 2 * PVT.getStoreSize();
6062 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6064 unsigned BufReg = MI->getOperand(0).getReg();
6066 // Reload FP (the jumped-to function may not have had a
6067 // frame pointer, and if so, then its r31 will be restored
6069 if (PVT == MVT::i64) {
6070 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6074 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6078 MIB.setMemRefs(MMOBegin, MMOEnd);
6081 if (PVT == MVT::i64) {
6082 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6083 .addImm(LabelOffset / 4)
6086 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6087 .addImm(LabelOffset)
6090 MIB.setMemRefs(MMOBegin, MMOEnd);
6093 if (PVT == MVT::i64) {
6094 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6095 .addImm(SPOffset / 4)
6098 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6102 MIB.setMemRefs(MMOBegin, MMOEnd);
6104 // FIXME: When we also support base pointers, that register must also be
6108 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6109 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6110 .addImm(TOCOffset / 4)
6113 MIB.setMemRefs(MMOBegin, MMOEnd);
6117 BuildMI(*MBB, MI, DL,
6118 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6119 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6121 MI->eraseFromParent();
6126 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6127 MachineBasicBlock *BB) const {
6128 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6129 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6130 return emitEHSjLjSetJmp(MI, BB);
6131 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6132 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6133 return emitEHSjLjLongJmp(MI, BB);
6136 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6138 // To "insert" these instructions we actually have to insert their
6139 // control-flow patterns.
6140 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6141 MachineFunction::iterator It = BB;
6144 MachineFunction *F = BB->getParent();
6146 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6147 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6148 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ?
6149 PPC::ISEL8 : PPC::ISEL;
6150 unsigned SelectPred = MI->getOperand(4).getImm();
6151 DebugLoc dl = MI->getDebugLoc();
6153 // The SelectPred is ((BI << 5) | BO) for a BCC
6154 unsigned BO = SelectPred & 0xF;
6155 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel");
6157 unsigned TrueOpNo, FalseOpNo;
6164 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred);
6167 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
6168 .addReg(MI->getOperand(TrueOpNo).getReg())
6169 .addReg(MI->getOperand(FalseOpNo).getReg())
6170 .addImm(SelectPred).addReg(MI->getOperand(1).getReg());
6171 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6172 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6173 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6174 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6175 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6178 // The incoming instruction knows the destination vreg to set, the
6179 // condition code register to branch on, the true/false values to
6180 // select between, and a branch opcode to use.
6185 // cmpTY ccX, r1, r2
6187 // fallthrough --> copy0MBB
6188 MachineBasicBlock *thisMBB = BB;
6189 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6190 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6191 unsigned SelectPred = MI->getOperand(4).getImm();
6192 DebugLoc dl = MI->getDebugLoc();
6193 F->insert(It, copy0MBB);
6194 F->insert(It, sinkMBB);
6196 // Transfer the remainder of BB and its successor edges to sinkMBB.
6197 sinkMBB->splice(sinkMBB->begin(), BB,
6198 llvm::next(MachineBasicBlock::iterator(MI)),
6200 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6202 // Next, add the true and fallthrough blocks as its successors.
6203 BB->addSuccessor(copy0MBB);
6204 BB->addSuccessor(sinkMBB);
6206 BuildMI(BB, dl, TII->get(PPC::BCC))
6207 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6210 // %FalseValue = ...
6211 // # fallthrough to sinkMBB
6214 // Update machine-CFG edges
6215 BB->addSuccessor(sinkMBB);
6218 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6221 BuildMI(*BB, BB->begin(), dl,
6222 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6223 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6224 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6226 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6227 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6228 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6229 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6230 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6231 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6232 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6233 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6235 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6236 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6237 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6238 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6239 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6240 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6241 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6242 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6244 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6245 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6246 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6247 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6248 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6249 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6250 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6251 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6253 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6254 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6255 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6256 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6257 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6258 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6259 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6260 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6262 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6263 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6264 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6265 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6266 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6267 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6268 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6269 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6271 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6272 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6273 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6274 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6275 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6276 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6277 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6278 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6280 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6281 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6282 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6283 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6284 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6285 BB = EmitAtomicBinary(MI, BB, false, 0);
6286 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6287 BB = EmitAtomicBinary(MI, BB, true, 0);
6289 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6290 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6291 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6293 unsigned dest = MI->getOperand(0).getReg();
6294 unsigned ptrA = MI->getOperand(1).getReg();
6295 unsigned ptrB = MI->getOperand(2).getReg();
6296 unsigned oldval = MI->getOperand(3).getReg();
6297 unsigned newval = MI->getOperand(4).getReg();
6298 DebugLoc dl = MI->getDebugLoc();
6300 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6301 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6302 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6303 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6304 F->insert(It, loop1MBB);
6305 F->insert(It, loop2MBB);
6306 F->insert(It, midMBB);
6307 F->insert(It, exitMBB);
6308 exitMBB->splice(exitMBB->begin(), BB,
6309 llvm::next(MachineBasicBlock::iterator(MI)),
6311 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6315 // fallthrough --> loopMBB
6316 BB->addSuccessor(loop1MBB);
6319 // l[wd]arx dest, ptr
6320 // cmp[wd] dest, oldval
6323 // st[wd]cx. newval, ptr
6327 // st[wd]cx. dest, ptr
6330 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6331 .addReg(ptrA).addReg(ptrB);
6332 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6333 .addReg(oldval).addReg(dest);
6334 BuildMI(BB, dl, TII->get(PPC::BCC))
6335 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6336 BB->addSuccessor(loop2MBB);
6337 BB->addSuccessor(midMBB);
6340 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6341 .addReg(newval).addReg(ptrA).addReg(ptrB);
6342 BuildMI(BB, dl, TII->get(PPC::BCC))
6343 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6344 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6345 BB->addSuccessor(loop1MBB);
6346 BB->addSuccessor(exitMBB);
6349 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6350 .addReg(dest).addReg(ptrA).addReg(ptrB);
6351 BB->addSuccessor(exitMBB);
6356 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6357 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6358 // We must use 64-bit registers for addresses when targeting 64-bit,
6359 // since we're actually doing arithmetic on them. Other registers
6361 bool is64bit = PPCSubTarget.isPPC64();
6362 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6364 unsigned dest = MI->getOperand(0).getReg();
6365 unsigned ptrA = MI->getOperand(1).getReg();
6366 unsigned ptrB = MI->getOperand(2).getReg();
6367 unsigned oldval = MI->getOperand(3).getReg();
6368 unsigned newval = MI->getOperand(4).getReg();
6369 DebugLoc dl = MI->getDebugLoc();
6371 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6372 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6373 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6374 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6375 F->insert(It, loop1MBB);
6376 F->insert(It, loop2MBB);
6377 F->insert(It, midMBB);
6378 F->insert(It, exitMBB);
6379 exitMBB->splice(exitMBB->begin(), BB,
6380 llvm::next(MachineBasicBlock::iterator(MI)),
6382 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6384 MachineRegisterInfo &RegInfo = F->getRegInfo();
6385 const TargetRegisterClass *RC =
6386 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6387 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6388 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6389 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6390 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6391 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6392 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6393 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6394 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6395 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6396 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6397 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6398 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6399 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6400 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6402 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6403 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6406 // fallthrough --> loopMBB
6407 BB->addSuccessor(loop1MBB);
6409 // The 4-byte load must be aligned, while a char or short may be
6410 // anywhere in the word. Hence all this nasty bookkeeping code.
6411 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6412 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6413 // xori shift, shift1, 24 [16]
6414 // rlwinm ptr, ptr1, 0, 0, 29
6415 // slw newval2, newval, shift
6416 // slw oldval2, oldval,shift
6417 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6418 // slw mask, mask2, shift
6419 // and newval3, newval2, mask
6420 // and oldval3, oldval2, mask
6422 // lwarx tmpDest, ptr
6423 // and tmp, tmpDest, mask
6424 // cmpw tmp, oldval3
6427 // andc tmp2, tmpDest, mask
6428 // or tmp4, tmp2, newval3
6433 // stwcx. tmpDest, ptr
6435 // srw dest, tmpDest, shift
6436 if (ptrA != ZeroReg) {
6437 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6438 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6439 .addReg(ptrA).addReg(ptrB);
6443 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6444 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6445 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6446 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6448 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6449 .addReg(Ptr1Reg).addImm(0).addImm(61);
6451 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6452 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6453 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6454 .addReg(newval).addReg(ShiftReg);
6455 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6456 .addReg(oldval).addReg(ShiftReg);
6458 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6460 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6461 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6462 .addReg(Mask3Reg).addImm(65535);
6464 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6465 .addReg(Mask2Reg).addReg(ShiftReg);
6466 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6467 .addReg(NewVal2Reg).addReg(MaskReg);
6468 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6469 .addReg(OldVal2Reg).addReg(MaskReg);
6472 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6473 .addReg(ZeroReg).addReg(PtrReg);
6474 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6475 .addReg(TmpDestReg).addReg(MaskReg);
6476 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6477 .addReg(TmpReg).addReg(OldVal3Reg);
6478 BuildMI(BB, dl, TII->get(PPC::BCC))
6479 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6480 BB->addSuccessor(loop2MBB);
6481 BB->addSuccessor(midMBB);
6484 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6485 .addReg(TmpDestReg).addReg(MaskReg);
6486 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6487 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6488 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6489 .addReg(ZeroReg).addReg(PtrReg);
6490 BuildMI(BB, dl, TII->get(PPC::BCC))
6491 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6492 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6493 BB->addSuccessor(loop1MBB);
6494 BB->addSuccessor(exitMBB);
6497 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6498 .addReg(ZeroReg).addReg(PtrReg);
6499 BB->addSuccessor(exitMBB);
6504 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6507 llvm_unreachable("Unexpected instr type to insert");
6510 MI->eraseFromParent(); // The pseudo instruction is gone now.
6514 //===----------------------------------------------------------------------===//
6515 // Target Optimization Hooks
6516 //===----------------------------------------------------------------------===//
6518 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6519 DAGCombinerInfo &DCI) const {
6520 const TargetMachine &TM = getTargetMachine();
6521 SelectionDAG &DAG = DCI.DAG;
6522 DebugLoc dl = N->getDebugLoc();
6523 switch (N->getOpcode()) {
6526 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6527 if (C->isNullValue()) // 0 << V -> 0.
6528 return N->getOperand(0);
6532 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6533 if (C->isNullValue()) // 0 >>u V -> 0.
6534 return N->getOperand(0);
6538 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6539 if (C->isNullValue() || // 0 >>s V -> 0.
6540 C->isAllOnesValue()) // -1 >>s V -> -1.
6541 return N->getOperand(0);
6545 case ISD::SINT_TO_FP:
6546 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6547 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6548 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6549 // We allow the src/dst to be either f32/f64, but the intermediate
6550 // type must be i64.
6551 if (N->getOperand(0).getValueType() == MVT::i64 &&
6552 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6553 SDValue Val = N->getOperand(0).getOperand(0);
6554 if (Val.getValueType() == MVT::f32) {
6555 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6556 DCI.AddToWorklist(Val.getNode());
6559 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6560 DCI.AddToWorklist(Val.getNode());
6561 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6562 DCI.AddToWorklist(Val.getNode());
6563 if (N->getValueType(0) == MVT::f32) {
6564 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6565 DAG.getIntPtrConstant(0));
6566 DCI.AddToWorklist(Val.getNode());
6569 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6570 // If the intermediate type is i32, we can avoid the load/store here
6577 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6578 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6579 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6580 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6581 N->getOperand(1).getValueType() == MVT::i32 &&
6582 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6583 SDValue Val = N->getOperand(1).getOperand(0);
6584 if (Val.getValueType() == MVT::f32) {
6585 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6586 DCI.AddToWorklist(Val.getNode());
6588 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6589 DCI.AddToWorklist(Val.getNode());
6591 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
6592 N->getOperand(2), N->getOperand(3));
6593 DCI.AddToWorklist(Val.getNode());
6597 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6598 if (cast<StoreSDNode>(N)->isUnindexed() &&
6599 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6600 N->getOperand(1).getNode()->hasOneUse() &&
6601 (N->getOperand(1).getValueType() == MVT::i32 ||
6602 N->getOperand(1).getValueType() == MVT::i16)) {
6603 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6604 // Do an any-extend to 32-bits if this is a half-word input.
6605 if (BSwapOp.getValueType() == MVT::i16)
6606 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6609 N->getOperand(0), BSwapOp, N->getOperand(2),
6610 DAG.getValueType(N->getOperand(1).getValueType())
6613 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
6614 Ops, array_lengthof(Ops),
6615 cast<StoreSDNode>(N)->getMemoryVT(),
6616 cast<StoreSDNode>(N)->getMemOperand());
6620 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
6621 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
6622 N->getOperand(0).hasOneUse() &&
6623 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
6624 SDValue Load = N->getOperand(0);
6625 LoadSDNode *LD = cast<LoadSDNode>(Load);
6626 // Create the byte-swapping load.
6628 LD->getChain(), // Chain
6629 LD->getBasePtr(), // Ptr
6630 DAG.getValueType(N->getValueType(0)) // VT
6633 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
6634 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
6635 LD->getMemoryVT(), LD->getMemOperand());
6637 // If this is an i16 load, insert the truncate.
6638 SDValue ResVal = BSLoad;
6639 if (N->getValueType(0) == MVT::i16)
6640 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
6642 // First, combine the bswap away. This makes the value produced by the
6644 DCI.CombineTo(N, ResVal);
6646 // Next, combine the load away, we give it a bogus result value but a real
6647 // chain result. The result value is dead because the bswap is dead.
6648 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
6650 // Return N so it doesn't get rechecked!
6651 return SDValue(N, 0);
6655 case PPCISD::VCMP: {
6656 // If a VCMPo node already exists with exactly the same operands as this
6657 // node, use its result instead of this node (VCMPo computes both a CR6 and
6658 // a normal output).
6660 if (!N->getOperand(0).hasOneUse() &&
6661 !N->getOperand(1).hasOneUse() &&
6662 !N->getOperand(2).hasOneUse()) {
6664 // Scan all of the users of the LHS, looking for VCMPo's that match.
6665 SDNode *VCMPoNode = 0;
6667 SDNode *LHSN = N->getOperand(0).getNode();
6668 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
6670 if (UI->getOpcode() == PPCISD::VCMPo &&
6671 UI->getOperand(1) == N->getOperand(1) &&
6672 UI->getOperand(2) == N->getOperand(2) &&
6673 UI->getOperand(0) == N->getOperand(0)) {
6678 // If there is no VCMPo node, or if the flag value has a single use, don't
6680 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
6683 // Look at the (necessarily single) use of the flag value. If it has a
6684 // chain, this transformation is more complex. Note that multiple things
6685 // could use the value result, which we should ignore.
6686 SDNode *FlagUser = 0;
6687 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
6688 FlagUser == 0; ++UI) {
6689 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
6691 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
6692 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
6699 // If the user is a MFCR instruction, we know this is safe. Otherwise we
6700 // give up for right now.
6701 if (FlagUser->getOpcode() == PPCISD::MFCR)
6702 return SDValue(VCMPoNode, 0);
6707 // If this is a branch on an altivec predicate comparison, lower this so
6708 // that we don't have to do a MFCR: instead, branch directly on CR6. This
6709 // lowering is done pre-legalize, because the legalizer lowers the predicate
6710 // compare down to code that is difficult to reassemble.
6711 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
6712 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
6716 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
6717 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
6718 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
6719 assert(isDot && "Can't compare against a vector result!");
6721 // If this is a comparison against something other than 0/1, then we know
6722 // that the condition is never/always true.
6723 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
6724 if (Val != 0 && Val != 1) {
6725 if (CC == ISD::SETEQ) // Cond never true, remove branch.
6726 return N->getOperand(0);
6727 // Always !=, turn it into an unconditional branch.
6728 return DAG.getNode(ISD::BR, dl, MVT::Other,
6729 N->getOperand(0), N->getOperand(4));
6732 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
6734 // Create the PPCISD altivec 'dot' comparison node.
6736 LHS.getOperand(2), // LHS of compare
6737 LHS.getOperand(3), // RHS of compare
6738 DAG.getConstant(CompareOpc, MVT::i32)
6740 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
6741 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
6743 // Unpack the result based on how the target uses it.
6744 PPC::Predicate CompOpc;
6745 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
6746 default: // Can't happen, don't crash on invalid number though.
6747 case 0: // Branch on the value of the EQ bit of CR6.
6748 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
6750 case 1: // Branch on the inverted value of the EQ bit of CR6.
6751 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
6753 case 2: // Branch on the value of the LT bit of CR6.
6754 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
6756 case 3: // Branch on the inverted value of the LT bit of CR6.
6757 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
6761 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
6762 DAG.getConstant(CompOpc, MVT::i32),
6763 DAG.getRegister(PPC::CR6, MVT::i32),
6764 N->getOperand(4), CompNode.getValue(1));
6773 //===----------------------------------------------------------------------===//
6774 // Inline Assembly Support
6775 //===----------------------------------------------------------------------===//
6777 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6780 const SelectionDAG &DAG,
6781 unsigned Depth) const {
6782 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
6783 switch (Op.getOpcode()) {
6785 case PPCISD::LBRX: {
6786 // lhbrx is known to have the top bits cleared out.
6787 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
6788 KnownZero = 0xFFFF0000;
6791 case ISD::INTRINSIC_WO_CHAIN: {
6792 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
6794 case Intrinsic::ppc_altivec_vcmpbfp_p:
6795 case Intrinsic::ppc_altivec_vcmpeqfp_p:
6796 case Intrinsic::ppc_altivec_vcmpequb_p:
6797 case Intrinsic::ppc_altivec_vcmpequh_p:
6798 case Intrinsic::ppc_altivec_vcmpequw_p:
6799 case Intrinsic::ppc_altivec_vcmpgefp_p:
6800 case Intrinsic::ppc_altivec_vcmpgtfp_p:
6801 case Intrinsic::ppc_altivec_vcmpgtsb_p:
6802 case Intrinsic::ppc_altivec_vcmpgtsh_p:
6803 case Intrinsic::ppc_altivec_vcmpgtsw_p:
6804 case Intrinsic::ppc_altivec_vcmpgtub_p:
6805 case Intrinsic::ppc_altivec_vcmpgtuh_p:
6806 case Intrinsic::ppc_altivec_vcmpgtuw_p:
6807 KnownZero = ~1U; // All bits but the low one are known to be zero.
6815 /// getConstraintType - Given a constraint, return the type of
6816 /// constraint it is for this target.
6817 PPCTargetLowering::ConstraintType
6818 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
6819 if (Constraint.size() == 1) {
6820 switch (Constraint[0]) {
6827 return C_RegisterClass;
6829 // FIXME: While Z does indicate a memory constraint, it specifically
6830 // indicates an r+r address (used in conjunction with the 'y' modifier
6831 // in the replacement string). Currently, we're forcing the base
6832 // register to be r0 in the asm printer (which is interpreted as zero)
6833 // and forming the complete address in the second register. This is
6838 return TargetLowering::getConstraintType(Constraint);
6841 /// Examine constraint type and operand type and determine a weight value.
6842 /// This object must already have been set up with the operand type
6843 /// and the current alternative constraint selected.
6844 TargetLowering::ConstraintWeight
6845 PPCTargetLowering::getSingleConstraintMatchWeight(
6846 AsmOperandInfo &info, const char *constraint) const {
6847 ConstraintWeight weight = CW_Invalid;
6848 Value *CallOperandVal = info.CallOperandVal;
6849 // If we don't have a value, we can't do a match,
6850 // but allow it at the lowest weight.
6851 if (CallOperandVal == NULL)
6853 Type *type = CallOperandVal->getType();
6854 // Look at the constraint type.
6855 switch (*constraint) {
6857 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6860 if (type->isIntegerTy())
6861 weight = CW_Register;
6864 if (type->isFloatTy())
6865 weight = CW_Register;
6868 if (type->isDoubleTy())
6869 weight = CW_Register;
6872 if (type->isVectorTy())
6873 weight = CW_Register;
6876 weight = CW_Register;
6885 std::pair<unsigned, const TargetRegisterClass*>
6886 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6888 if (Constraint.size() == 1) {
6889 // GCC RS6000 Constraint Letters
6890 switch (Constraint[0]) {
6892 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
6893 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
6894 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
6896 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
6897 return std::make_pair(0U, &PPC::G8RCRegClass);
6898 return std::make_pair(0U, &PPC::GPRCRegClass);
6900 if (VT == MVT::f32 || VT == MVT::i32)
6901 return std::make_pair(0U, &PPC::F4RCRegClass);
6902 if (VT == MVT::f64 || VT == MVT::i64)
6903 return std::make_pair(0U, &PPC::F8RCRegClass);
6906 return std::make_pair(0U, &PPC::VRRCRegClass);
6908 return std::make_pair(0U, &PPC::CRRCRegClass);
6912 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6916 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6917 /// vector. If it is invalid, don't add anything to Ops.
6918 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6919 std::string &Constraint,
6920 std::vector<SDValue>&Ops,
6921 SelectionDAG &DAG) const {
6922 SDValue Result(0,0);
6924 // Only support length 1 constraints.
6925 if (Constraint.length() > 1) return;
6927 char Letter = Constraint[0];
6938 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
6939 if (!CST) return; // Must be an immediate to match.
6940 unsigned Value = CST->getZExtValue();
6942 default: llvm_unreachable("Unknown constraint letter!");
6943 case 'I': // "I" is a signed 16-bit constant.
6944 if ((short)Value == (int)Value)
6945 Result = DAG.getTargetConstant(Value, Op.getValueType());
6947 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
6948 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
6949 if ((short)Value == 0)
6950 Result = DAG.getTargetConstant(Value, Op.getValueType());
6952 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
6953 if ((Value >> 16) == 0)
6954 Result = DAG.getTargetConstant(Value, Op.getValueType());
6956 case 'M': // "M" is a constant that is greater than 31.
6958 Result = DAG.getTargetConstant(Value, Op.getValueType());
6960 case 'N': // "N" is a positive constant that is an exact power of two.
6961 if ((int)Value > 0 && isPowerOf2_32(Value))
6962 Result = DAG.getTargetConstant(Value, Op.getValueType());
6964 case 'O': // "O" is the constant zero.
6966 Result = DAG.getTargetConstant(Value, Op.getValueType());
6968 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
6969 if ((short)-Value == (int)-Value)
6970 Result = DAG.getTargetConstant(Value, Op.getValueType());
6977 if (Result.getNode()) {
6978 Ops.push_back(Result);
6982 // Handle standard constraint letters.
6983 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6986 // isLegalAddressingMode - Return true if the addressing mode represented
6987 // by AM is legal for this target, for a load/store of the specified type.
6988 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6990 // FIXME: PPC does not allow r+i addressing modes for vectors!
6992 // PPC allows a sign-extended 16-bit immediate field.
6993 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
6996 // No global is ever allowed as a base.
7000 // PPC only support r+r,
7002 case 0: // "r+i" or just "i", depending on HasBaseReg.
7005 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7007 // Otherwise we have r+r or r+i.
7010 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7012 // Allow 2*r as r+r.
7015 // No other scales are supported.
7022 /// isLegalAddressImmediate - Return true if the integer value can be used
7023 /// as the offset of the target addressing mode for load / store of the
7025 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
7026 // PPC allows a sign-extended 16-bit immediate field.
7027 return (V > -(1 << 16) && V < (1 << 16)-1);
7030 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
7034 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7035 SelectionDAG &DAG) const {
7036 MachineFunction &MF = DAG.getMachineFunction();
7037 MachineFrameInfo *MFI = MF.getFrameInfo();
7038 MFI->setReturnAddressIsTaken(true);
7040 DebugLoc dl = Op.getDebugLoc();
7041 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7043 // Make sure the function does not optimize away the store of the RA to
7045 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7046 FuncInfo->setLRStoreRequired();
7047 bool isPPC64 = PPCSubTarget.isPPC64();
7048 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7051 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7054 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7055 isPPC64? MVT::i64 : MVT::i32);
7056 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7057 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7059 MachinePointerInfo(), false, false, false, 0);
7062 // Just load the return address off the stack.
7063 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7064 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7065 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7068 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7069 SelectionDAG &DAG) const {
7070 DebugLoc dl = Op.getDebugLoc();
7071 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7073 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7074 bool isPPC64 = PtrVT == MVT::i64;
7076 MachineFunction &MF = DAG.getMachineFunction();
7077 MachineFrameInfo *MFI = MF.getFrameInfo();
7078 MFI->setFrameAddressIsTaken(true);
7080 // Naked functions never have a frame pointer, and so we use r1. For all
7081 // other functions, this decision must be delayed until during PEI.
7083 if (MF.getFunction()->getAttributes().hasAttribute(
7084 AttributeSet::FunctionIndex, Attribute::Naked))
7085 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7087 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7089 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7092 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7093 FrameAddr, MachinePointerInfo(), false, false,
7099 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7100 // The PowerPC target isn't yet aware of offsets.
7104 /// getOptimalMemOpType - Returns the target specific optimal type for load
7105 /// and store operations as a result of memset, memcpy, and memmove
7106 /// lowering. If DstAlign is zero that means it's safe to destination
7107 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7108 /// means there isn't a need to check it against alignment requirement,
7109 /// probably because the source does not need to be loaded. If 'IsMemset' is
7110 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7111 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7112 /// source is constant so it does not need to be loaded.
7113 /// It returns EVT::Other if the type should be determined using generic
7114 /// target-independent logic.
7115 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7116 unsigned DstAlign, unsigned SrcAlign,
7117 bool IsMemset, bool ZeroMemset,
7119 MachineFunction &MF) const {
7120 if (this->PPCSubTarget.isPPC64()) {
7127 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7129 if (DisablePPCUnaligned)
7132 // PowerPC supports unaligned memory access for simple non-vector types.
7133 // Although accessing unaligned addresses is not as efficient as accessing
7134 // aligned addresses, it is generally more efficient than manual expansion,
7135 // and generally only traps for software emulation when crossing page
7141 if (VT.getSimpleVT().isVector())
7144 if (VT == MVT::ppcf128)
7153 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
7154 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
7155 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
7156 /// is expanded to mul + add.
7157 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
7161 switch (VT.getSimpleVT().SimpleTy) {
7173 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7175 return TargetLowering::getSchedulingPreference(N);