1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Function.h"
23 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
24 : TargetLowering(TM) {
26 // Fold away setcc operations if possible.
27 setSetCCIsExpensive();
29 // Set up the register classes.
30 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
31 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
32 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
34 // PowerPC has no intrinsics for these particular operations
35 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
36 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
37 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
39 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
40 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
41 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
43 // PowerPC has no SREM/UREM instructions
44 setOperationAction(ISD::SREM, MVT::i32, Expand);
45 setOperationAction(ISD::UREM, MVT::i32, Expand);
47 // We don't support sin/cos/sqrt/fmod
48 setOperationAction(ISD::FSIN , MVT::f64, Expand);
49 setOperationAction(ISD::FCOS , MVT::f64, Expand);
50 setOperationAction(ISD::SREM , MVT::f64, Expand);
51 setOperationAction(ISD::FSIN , MVT::f32, Expand);
52 setOperationAction(ISD::FCOS , MVT::f32, Expand);
53 setOperationAction(ISD::SREM , MVT::f32, Expand);
55 // If we're enabling GP optimizations, use hardware square root
56 if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
57 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
58 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
61 // PowerPC does not have CTPOP or CTTZ
62 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
63 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
65 // PowerPC does not have Select
66 setOperationAction(ISD::SELECT, MVT::i32, Expand);
67 setOperationAction(ISD::SELECT, MVT::f32, Expand);
68 setOperationAction(ISD::SELECT, MVT::f64, Expand);
70 // PowerPC does not have BRCOND* which requires SetCC
71 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
72 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
74 // PowerPC does not have FP_TO_UINT
75 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
77 setSetCCResultContents(ZeroOrOneSetCCResult);
78 addLegalFPImmediate(+0.0); // Necessary for FSEL
79 addLegalFPImmediate(-0.0); //
81 computeRegisterProperties();
84 std::vector<SDOperand>
85 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
87 // add beautiful description of PPC stack frame format, or at least some docs
89 MachineFunction &MF = DAG.getMachineFunction();
90 MachineFrameInfo *MFI = MF.getFrameInfo();
91 MachineBasicBlock& BB = MF.front();
92 std::vector<SDOperand> ArgValues;
94 // Due to the rather complicated nature of the PowerPC ABI, rather than a
95 // fixed size array of physical args, for the sake of simplicity let the STL
96 // handle tracking them for us.
97 std::vector<unsigned> argVR, argPR, argOp;
98 unsigned ArgOffset = 24;
99 unsigned GPR_remaining = 8;
100 unsigned FPR_remaining = 13;
101 unsigned GPR_idx = 0, FPR_idx = 0;
102 static const unsigned GPR[] = {
103 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
104 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
106 static const unsigned FPR[] = {
107 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
108 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
111 // Add DAG nodes to load the arguments... On entry to a function on PPC,
112 // the arguments start at offset 24, although they are likely to be passed
114 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
115 SDOperand newroot, argt;
117 bool needsLoad = false;
118 bool ArgLive = !I->use_empty();
119 MVT::ValueType ObjectVT = getValueType(I->getType());
122 default: assert(0 && "Unhandled argument type!");
129 if (GPR_remaining > 0) {
130 MF.addLiveIn(GPR[GPR_idx]);
131 argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
133 if (ObjectVT != MVT::i32)
134 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
139 case MVT::i64: ObjSize = 8;
141 if (GPR_remaining > 0) {
142 SDOperand argHi, argLo;
143 MF.addLiveIn(GPR[GPR_idx]);
144 argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
145 // If we have two or more remaining argument registers, then both halves
146 // of the i64 can be sourced from there. Otherwise, the lower half will
147 // have to come off the stack. This can happen when an i64 is preceded
148 // by 28 bytes of arguments.
149 if (GPR_remaining > 1) {
150 MF.addLiveIn(GPR[GPR_idx+1]);
151 argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
153 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
154 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
155 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
156 DAG.getSrcValue(NULL));
158 // Build the outgoing arg thingy
159 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
167 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
169 if (FPR_remaining > 0) {
170 MF.addLiveIn(FPR[FPR_idx]);
171 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
181 // We need to load the argument to a virtual register if we determined above
182 // that we ran out of physical registers of the appropriate type
184 unsigned SubregOffset = 0;
185 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
186 if (ObjectVT == MVT::i16) SubregOffset = 2;
187 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
188 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
189 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
190 DAG.getConstant(SubregOffset, MVT::i32));
191 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
192 DAG.getSrcValue(NULL));
195 // Every 4 bytes of argument space consumes one of the GPRs available for
197 if (GPR_remaining > 0) {
198 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
199 GPR_remaining -= delta;
202 ArgOffset += ObjSize;
204 DAG.setRoot(newroot.getValue(1));
206 ArgValues.push_back(argt);
209 // If the function takes variable number of arguments, make a frame index for
210 // the start of the first vararg value... for expansion of llvm.va_start.
212 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
213 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
214 // If this function is vararg, store any remaining integer argument regs
215 // to their spots on the stack so that they may be loaded by deferencing the
216 // result of va_next.
217 std::vector<SDOperand> MemOps;
218 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
219 MF.addLiveIn(GPR[GPR_idx]);
220 SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
221 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
222 Val, FIN, DAG.getSrcValue(NULL));
223 MemOps.push_back(Store);
224 // Increment the address by four for the next argument to store
225 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
226 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
228 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
231 // Finally, inform the code generator which regs we return values in.
232 switch (getValueType(F.getReturnType())) {
233 default: assert(0 && "Unknown type!");
234 case MVT::isVoid: break;
239 MF.addLiveOut(PPC::R3);
242 MF.addLiveOut(PPC::R3);
243 MF.addLiveOut(PPC::R4);
247 MF.addLiveOut(PPC::F1);
254 std::pair<SDOperand, SDOperand>
255 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
256 const Type *RetTy, bool isVarArg,
257 unsigned CallingConv, bool isTailCall,
258 SDOperand Callee, ArgListTy &Args,
260 // args_to_use will accumulate outgoing args for the ISD::CALL case in
261 // SelectExpr to use to put the arguments in the appropriate registers.
262 std::vector<SDOperand> args_to_use;
264 // Count how many bytes are to be pushed on the stack, including the linkage
265 // area, and parameter passing area.
266 unsigned NumBytes = 24;
269 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
270 DAG.getConstant(NumBytes, getPointerTy()));
272 for (unsigned i = 0, e = Args.size(); i != e; ++i)
273 switch (getValueType(Args[i].second)) {
274 default: assert(0 && "Unknown value type!");
288 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
289 // plus 32 bytes of argument space in case any called code gets funky on us.
290 // (Required by ABI to support var arg)
291 if (NumBytes < 56) NumBytes = 56;
293 // Adjust the stack pointer for the new arguments...
294 // These operations are automatically eliminated by the prolog/epilog pass
295 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
296 DAG.getConstant(NumBytes, getPointerTy()));
298 // Set up a copy of the stack pointer for use loading and storing any
299 // arguments that may not fit in the registers available for argument
301 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
304 // Figure out which arguments are going to go in registers, and which in
305 // memory. Also, if this is a vararg function, floating point operations
306 // must be stored to our stack, and loaded into integer regs as well, if
307 // any integer regs are available for argument passing.
308 unsigned ArgOffset = 24;
309 unsigned GPR_remaining = 8;
310 unsigned FPR_remaining = 13;
312 std::vector<SDOperand> MemOps;
313 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
314 // PtrOff will be used to store the current argument to the stack if a
315 // register cannot be found for it.
316 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
317 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
318 MVT::ValueType ArgVT = getValueType(Args[i].second);
321 default: assert(0 && "Unexpected ValueType for argument!");
325 // Promote the integer to 32 bits. If the input type is signed use a
326 // sign extend, otherwise use a zero extend.
327 if (Args[i].second->isSigned())
328 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
330 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
333 if (GPR_remaining > 0) {
334 args_to_use.push_back(Args[i].first);
337 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
338 Args[i].first, PtrOff,
339 DAG.getSrcValue(NULL)));
344 // If we have one free GPR left, we can place the upper half of the i64
345 // in it, and store the other half to the stack. If we have two or more
346 // free GPRs, then we can pass both halves of the i64 in registers.
347 if (GPR_remaining > 0) {
348 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
349 Args[i].first, DAG.getConstant(1, MVT::i32));
350 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
351 Args[i].first, DAG.getConstant(0, MVT::i32));
352 args_to_use.push_back(Hi);
354 if (GPR_remaining > 0) {
355 args_to_use.push_back(Lo);
358 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
359 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
360 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
361 Lo, PtrOff, DAG.getSrcValue(NULL)));
364 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
365 Args[i].first, PtrOff,
366 DAG.getSrcValue(NULL)));
372 if (FPR_remaining > 0) {
373 args_to_use.push_back(Args[i].first);
376 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
377 Args[i].first, PtrOff,
378 DAG.getSrcValue(NULL));
379 MemOps.push_back(Store);
380 // Float varargs are always shadowed in available integer registers
381 if (GPR_remaining > 0) {
382 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
383 DAG.getSrcValue(NULL));
384 MemOps.push_back(Load);
385 args_to_use.push_back(Load);
388 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
389 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
390 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
391 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
392 DAG.getSrcValue(NULL));
393 MemOps.push_back(Load);
394 args_to_use.push_back(Load);
398 // If we have any FPRs remaining, we may also have GPRs remaining.
399 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
401 if (GPR_remaining > 0) {
402 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
405 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
406 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
411 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
412 Args[i].first, PtrOff,
413 DAG.getSrcValue(NULL)));
415 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
420 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
423 std::vector<MVT::ValueType> RetVals;
424 MVT::ValueType RetTyVT = getValueType(RetTy);
425 if (RetTyVT != MVT::isVoid)
426 RetVals.push_back(RetTyVT);
427 RetVals.push_back(MVT::Other);
429 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
430 Chain, Callee, args_to_use), 0);
431 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
432 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
433 DAG.getConstant(NumBytes, getPointerTy()));
434 return std::make_pair(TheCall, Chain);
437 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
438 Value *VAListV, SelectionDAG &DAG) {
439 // vastart just stores the address of the VarArgsFrameIndex slot into the
440 // memory location argument.
441 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
442 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
443 DAG.getSrcValue(VAListV));
446 std::pair<SDOperand,SDOperand>
447 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
448 SDOperand VAListP, Value *VAListV,
449 const Type *ArgTy, SelectionDAG &DAG) {
450 MVT::ValueType ArgVT = getValueType(ArgTy);
453 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
454 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
456 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
459 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
460 "Other types should have been promoted for varargs!");
463 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
464 DAG.getConstant(Amt, VAList.getValueType()));
465 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
466 VAList, VAListP, DAG.getSrcValue(VAListV));
467 return std::make_pair(Result, Chain);
471 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
472 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
474 assert(0 && "LowerFrameReturnAddress unimplemented");