1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 // FIXME: Remove this once soft-float is supported.
43 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
44 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
47 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
49 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
50 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
52 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
53 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
55 // FIXME: Remove this once the bug has been fixed!
56 extern cl::opt<bool> ANDIGlueBug;
58 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
59 : TargetLowering(TM, TM.getObjFileLowering()),
60 Subtarget(*TM.getSubtargetImpl()) {
63 // Use _setjmp/_longjmp instead of setjmp/longjmp.
64 setUseUnderscoreSetJmp(true);
65 setUseUnderscoreLongJmp(true);
67 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
68 // arguments are at least 4/8 bytes aligned.
69 bool isPPC64 = Subtarget.isPPC64();
70 setMinStackArgumentAlignment(isPPC64 ? 8:4);
72 // Set up the register classes.
73 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
74 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
75 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
77 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
78 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
79 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
81 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
83 // PowerPC has pre-inc load and store's.
84 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
89 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
95 if (Subtarget.useCRBits()) {
96 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
98 if (isPPC64 || Subtarget.hasFPCVT()) {
99 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
100 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
101 isPPC64 ? MVT::i64 : MVT::i32);
102 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
103 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
104 isPPC64 ? MVT::i64 : MVT::i32);
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
110 // PowerPC does not support direct load / store of condition registers
111 setOperationAction(ISD::LOAD, MVT::i1, Custom);
112 setOperationAction(ISD::STORE, MVT::i1, Custom);
114 // FIXME: Remove this once the ANDI glue bug is fixed:
116 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
118 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
119 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
120 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
121 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
122 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
123 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
125 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
128 // This is used in the ppcf128->int sequence. Note it has different semantics
129 // from FP_ROUND: that rounds to nearest, this rounds to zero.
130 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
132 // We do not currently implement these libm ops for PowerPC.
133 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
134 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
140 // PowerPC has no SREM/UREM instructions
141 setOperationAction(ISD::SREM, MVT::i32, Expand);
142 setOperationAction(ISD::UREM, MVT::i32, Expand);
143 setOperationAction(ISD::SREM, MVT::i64, Expand);
144 setOperationAction(ISD::UREM, MVT::i64, Expand);
146 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
147 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
148 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
149 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
150 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
151 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
152 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
154 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
156 // We don't support sin/cos/sqrt/fmod/pow
157 setOperationAction(ISD::FSIN , MVT::f64, Expand);
158 setOperationAction(ISD::FCOS , MVT::f64, Expand);
159 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
160 setOperationAction(ISD::FREM , MVT::f64, Expand);
161 setOperationAction(ISD::FPOW , MVT::f64, Expand);
162 setOperationAction(ISD::FMA , MVT::f64, Legal);
163 setOperationAction(ISD::FSIN , MVT::f32, Expand);
164 setOperationAction(ISD::FCOS , MVT::f32, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
166 setOperationAction(ISD::FREM , MVT::f32, Expand);
167 setOperationAction(ISD::FPOW , MVT::f32, Expand);
168 setOperationAction(ISD::FMA , MVT::f32, Legal);
170 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
172 // If we're enabling GP optimizations, use hardware square root
173 if (!Subtarget.hasFSQRT() &&
174 !(TM.Options.UnsafeFPMath &&
175 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
176 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
181 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
183 if (Subtarget.hasFCPSGN()) {
184 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
185 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
187 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
191 if (Subtarget.hasFPRND()) {
192 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
193 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
194 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
195 setOperationAction(ISD::FROUND, MVT::f64, Legal);
197 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
200 setOperationAction(ISD::FROUND, MVT::f32, Legal);
203 // PowerPC does not have BSWAP, CTPOP or CTTZ
204 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
205 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
206 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
207 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
208 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
209 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
210 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
211 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
213 if (Subtarget.hasPOPCNTD()) {
214 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
215 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
217 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
218 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
221 // PowerPC does not have ROTR
222 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
223 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
225 if (!Subtarget.useCRBits()) {
226 // PowerPC does not have Select
227 setOperationAction(ISD::SELECT, MVT::i32, Expand);
228 setOperationAction(ISD::SELECT, MVT::i64, Expand);
229 setOperationAction(ISD::SELECT, MVT::f32, Expand);
230 setOperationAction(ISD::SELECT, MVT::f64, Expand);
233 // PowerPC wants to turn select_cc of FP into fsel when possible.
234 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
235 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
237 // PowerPC wants to optimize integer setcc a bit
238 if (!Subtarget.useCRBits())
239 setOperationAction(ISD::SETCC, MVT::i32, Custom);
241 // PowerPC does not have BRCOND which requires SetCC
242 if (!Subtarget.useCRBits())
243 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
245 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
247 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
248 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
250 // PowerPC does not have [U|S]INT_TO_FP
251 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
252 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
254 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
256 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
257 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
259 // We cannot sextinreg(i1). Expand to shifts.
260 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
262 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
263 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
264 // support continuation, user-level threading, and etc.. As a result, no
265 // other SjLj exception interfaces are implemented and please don't build
266 // your own exception handling based on them.
267 // LLVM/Clang supports zero-cost DWARF exception handling.
268 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
269 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
271 // We want to legalize GlobalAddress and ConstantPool nodes into the
272 // appropriate instructions to materialize the address.
273 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
275 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
277 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
278 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
285 setOperationAction(ISD::TRAP, MVT::Other, Legal);
287 // TRAMPOLINE is custom lowered.
288 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
289 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
291 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
292 setOperationAction(ISD::VASTART , MVT::Other, Custom);
294 if (Subtarget.isSVR4ABI()) {
296 // VAARG always uses double-word chunks, so promote anything smaller.
297 setOperationAction(ISD::VAARG, MVT::i1, Promote);
298 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
299 setOperationAction(ISD::VAARG, MVT::i8, Promote);
300 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
301 setOperationAction(ISD::VAARG, MVT::i16, Promote);
302 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
303 setOperationAction(ISD::VAARG, MVT::i32, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::Other, Expand);
307 // VAARG is custom lowered with the 32-bit SVR4 ABI.
308 setOperationAction(ISD::VAARG, MVT::Other, Custom);
309 setOperationAction(ISD::VAARG, MVT::i64, Custom);
312 setOperationAction(ISD::VAARG, MVT::Other, Expand);
314 if (Subtarget.isSVR4ABI() && !isPPC64)
315 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
316 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
318 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
320 // Use the default implementation.
321 setOperationAction(ISD::VAEND , MVT::Other, Expand);
322 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
323 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
324 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
325 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
327 // We want to custom lower some of our intrinsics.
328 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
330 // To handle counter-based loop conditions.
331 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
333 // Comparisons that require checking two conditions.
334 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
335 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
336 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
337 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
338 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
339 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
340 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
347 if (Subtarget.has64BitSupport()) {
348 // They also have instructions for converting between i64 and fp.
349 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
350 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
351 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
352 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
353 // This is just the low 32 bits of a (signed) fp->i64 conversion.
354 // We cannot do this with Promote because i64 is not a legal type.
355 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
357 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
358 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
360 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
364 // With the instructions enabled under FPCVT, we can do everything.
365 if (Subtarget.hasFPCVT()) {
366 if (Subtarget.has64BitSupport()) {
367 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
368 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
369 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
370 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
379 if (Subtarget.use64BitRegs()) {
380 // 64-bit PowerPC implementations can support i64 types directly
381 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
382 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
383 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
384 // 64-bit PowerPC wants to expand i128 shifts itself.
385 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
386 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
387 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
389 // 32-bit PowerPC wants to expand i64 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
395 if (Subtarget.hasAltivec()) {
396 // First set operation action for all vector types to expand. Then we
397 // will selectively turn on ones that can be effectively codegen'd.
398 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
399 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
400 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
402 // add/sub are legal for all supported vector VT's.
403 setOperationAction(ISD::ADD , VT, Legal);
404 setOperationAction(ISD::SUB , VT, Legal);
406 // We promote all shuffles to v16i8.
407 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
408 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
410 // We promote all non-typed operations to v4i32.
411 setOperationAction(ISD::AND , VT, Promote);
412 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
413 setOperationAction(ISD::OR , VT, Promote);
414 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
415 setOperationAction(ISD::XOR , VT, Promote);
416 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
417 setOperationAction(ISD::LOAD , VT, Promote);
418 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
419 setOperationAction(ISD::SELECT, VT, Promote);
420 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
421 setOperationAction(ISD::STORE, VT, Promote);
422 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
424 // No other operations are legal.
425 setOperationAction(ISD::MUL , VT, Expand);
426 setOperationAction(ISD::SDIV, VT, Expand);
427 setOperationAction(ISD::SREM, VT, Expand);
428 setOperationAction(ISD::UDIV, VT, Expand);
429 setOperationAction(ISD::UREM, VT, Expand);
430 setOperationAction(ISD::FDIV, VT, Expand);
431 setOperationAction(ISD::FREM, VT, Expand);
432 setOperationAction(ISD::FNEG, VT, Expand);
433 setOperationAction(ISD::FSQRT, VT, Expand);
434 setOperationAction(ISD::FLOG, VT, Expand);
435 setOperationAction(ISD::FLOG10, VT, Expand);
436 setOperationAction(ISD::FLOG2, VT, Expand);
437 setOperationAction(ISD::FEXP, VT, Expand);
438 setOperationAction(ISD::FEXP2, VT, Expand);
439 setOperationAction(ISD::FSIN, VT, Expand);
440 setOperationAction(ISD::FCOS, VT, Expand);
441 setOperationAction(ISD::FABS, VT, Expand);
442 setOperationAction(ISD::FPOWI, VT, Expand);
443 setOperationAction(ISD::FFLOOR, VT, Expand);
444 setOperationAction(ISD::FCEIL, VT, Expand);
445 setOperationAction(ISD::FTRUNC, VT, Expand);
446 setOperationAction(ISD::FRINT, VT, Expand);
447 setOperationAction(ISD::FNEARBYINT, VT, Expand);
448 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
449 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
450 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
451 setOperationAction(ISD::MULHU, VT, Expand);
452 setOperationAction(ISD::MULHS, VT, Expand);
453 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
454 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
455 setOperationAction(ISD::UDIVREM, VT, Expand);
456 setOperationAction(ISD::SDIVREM, VT, Expand);
457 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
458 setOperationAction(ISD::FPOW, VT, Expand);
459 setOperationAction(ISD::BSWAP, VT, Expand);
460 setOperationAction(ISD::CTPOP, VT, Expand);
461 setOperationAction(ISD::CTLZ, VT, Expand);
462 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
463 setOperationAction(ISD::CTTZ, VT, Expand);
464 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
465 setOperationAction(ISD::VSELECT, VT, Expand);
466 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
468 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
469 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
470 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
471 setTruncStoreAction(VT, InnerVT, Expand);
473 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
474 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
475 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
478 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
479 // with merges, splats, etc.
480 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
482 setOperationAction(ISD::AND , MVT::v4i32, Legal);
483 setOperationAction(ISD::OR , MVT::v4i32, Legal);
484 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
485 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
486 setOperationAction(ISD::SELECT, MVT::v4i32,
487 Subtarget.useCRBits() ? Legal : Expand);
488 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
489 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
490 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
491 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
492 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
493 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
494 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
495 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
496 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
498 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
499 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
500 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
501 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
503 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
504 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
506 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
507 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
508 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
511 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
512 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
513 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
515 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
516 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
518 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
519 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
520 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
523 // Altivec does not contain unordered floating-point compare instructions
524 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
525 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
526 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
527 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
529 if (Subtarget.hasVSX()) {
530 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
531 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
533 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
534 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
535 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
536 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
537 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
539 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
541 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
542 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
544 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
545 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
547 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
548 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
549 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
550 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
551 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
553 // Share the Altivec comparison restrictions.
554 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
555 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
556 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
557 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
559 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
560 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
562 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
564 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
566 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
567 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
569 // VSX v2i64 only supports non-arithmetic operations.
570 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
571 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
573 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
574 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
575 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
577 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
579 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
580 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
581 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
582 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
584 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
586 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
587 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
588 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
589 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
591 // Vector operation legalization checks the result type of
592 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
593 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
594 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
595 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
596 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
598 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
602 if (Subtarget.has64BitSupport()) {
603 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
604 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
608 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
609 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
612 setBooleanContents(ZeroOrOneBooleanContent);
613 // Altivec instructions set fields to all zeros or all ones.
614 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
617 // These libcalls are not available in 32-bit.
618 setLibcallName(RTLIB::SHL_I128, nullptr);
619 setLibcallName(RTLIB::SRL_I128, nullptr);
620 setLibcallName(RTLIB::SRA_I128, nullptr);
624 setStackPointerRegisterToSaveRestore(PPC::X1);
625 setExceptionPointerRegister(PPC::X3);
626 setExceptionSelectorRegister(PPC::X4);
628 setStackPointerRegisterToSaveRestore(PPC::R1);
629 setExceptionPointerRegister(PPC::R3);
630 setExceptionSelectorRegister(PPC::R4);
633 // We have target-specific dag combine patterns for the following nodes:
634 setTargetDAGCombine(ISD::SINT_TO_FP);
635 setTargetDAGCombine(ISD::LOAD);
636 setTargetDAGCombine(ISD::STORE);
637 setTargetDAGCombine(ISD::BR_CC);
638 if (Subtarget.useCRBits())
639 setTargetDAGCombine(ISD::BRCOND);
640 setTargetDAGCombine(ISD::BSWAP);
641 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
643 setTargetDAGCombine(ISD::SIGN_EXTEND);
644 setTargetDAGCombine(ISD::ZERO_EXTEND);
645 setTargetDAGCombine(ISD::ANY_EXTEND);
647 if (Subtarget.useCRBits()) {
648 setTargetDAGCombine(ISD::TRUNCATE);
649 setTargetDAGCombine(ISD::SETCC);
650 setTargetDAGCombine(ISD::SELECT_CC);
653 // Use reciprocal estimates.
654 if (TM.Options.UnsafeFPMath) {
655 setTargetDAGCombine(ISD::FDIV);
656 setTargetDAGCombine(ISD::FSQRT);
659 // Darwin long double math library functions have $LDBL128 appended.
660 if (Subtarget.isDarwin()) {
661 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
662 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
663 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
664 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
665 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
666 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
667 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
668 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
669 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
670 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
673 // With 32 condition bits, we don't need to sink (and duplicate) compares
674 // aggressively in CodeGenPrep.
675 if (Subtarget.useCRBits())
676 setHasMultipleConditionRegisters();
678 setMinFunctionAlignment(2);
679 if (Subtarget.isDarwin())
680 setPrefFunctionAlignment(4);
682 setInsertFencesForAtomic(true);
684 if (Subtarget.enableMachineScheduler())
685 setSchedulingPreference(Sched::Source);
687 setSchedulingPreference(Sched::Hybrid);
689 computeRegisterProperties();
691 // The Freescale cores does better with aggressive inlining of memcpy and
692 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
693 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
694 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
695 MaxStoresPerMemset = 32;
696 MaxStoresPerMemsetOptSize = 16;
697 MaxStoresPerMemcpy = 32;
698 MaxStoresPerMemcpyOptSize = 8;
699 MaxStoresPerMemmove = 32;
700 MaxStoresPerMemmoveOptSize = 8;
702 setPrefFunctionAlignment(4);
706 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
707 /// the desired ByVal argument alignment.
708 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
709 unsigned MaxMaxAlign) {
710 if (MaxAlign == MaxMaxAlign)
712 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
713 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
715 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
717 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
718 unsigned EltAlign = 0;
719 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
720 if (EltAlign > MaxAlign)
722 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
723 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
724 unsigned EltAlign = 0;
725 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
726 if (EltAlign > MaxAlign)
728 if (MaxAlign == MaxMaxAlign)
734 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
735 /// function arguments in the caller parameter area.
736 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
737 // Darwin passes everything on 4 byte boundary.
738 if (Subtarget.isDarwin())
741 // 16byte and wider vectors are passed on 16byte boundary.
742 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
743 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
744 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
745 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
749 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
751 default: return nullptr;
752 case PPCISD::FSEL: return "PPCISD::FSEL";
753 case PPCISD::FCFID: return "PPCISD::FCFID";
754 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
755 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
756 case PPCISD::FRE: return "PPCISD::FRE";
757 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
758 case PPCISD::STFIWX: return "PPCISD::STFIWX";
759 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
760 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
761 case PPCISD::VPERM: return "PPCISD::VPERM";
762 case PPCISD::Hi: return "PPCISD::Hi";
763 case PPCISD::Lo: return "PPCISD::Lo";
764 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
765 case PPCISD::LOAD: return "PPCISD::LOAD";
766 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
767 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
768 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
769 case PPCISD::SRL: return "PPCISD::SRL";
770 case PPCISD::SRA: return "PPCISD::SRA";
771 case PPCISD::SHL: return "PPCISD::SHL";
772 case PPCISD::CALL: return "PPCISD::CALL";
773 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
774 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
775 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
776 case PPCISD::MTCTR: return "PPCISD::MTCTR";
777 case PPCISD::BCTRL: return "PPCISD::BCTRL";
778 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
779 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
780 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
781 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
782 case PPCISD::VCMP: return "PPCISD::VCMP";
783 case PPCISD::VCMPo: return "PPCISD::VCMPo";
784 case PPCISD::LBRX: return "PPCISD::LBRX";
785 case PPCISD::STBRX: return "PPCISD::STBRX";
786 case PPCISD::LARX: return "PPCISD::LARX";
787 case PPCISD::STCX: return "PPCISD::STCX";
788 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
789 case PPCISD::BDNZ: return "PPCISD::BDNZ";
790 case PPCISD::BDZ: return "PPCISD::BDZ";
791 case PPCISD::MFFS: return "PPCISD::MFFS";
792 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
793 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
794 case PPCISD::CR6SET: return "PPCISD::CR6SET";
795 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
796 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
797 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
798 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
799 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
800 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
801 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
802 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
803 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
804 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
805 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
806 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
807 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
808 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
809 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
810 case PPCISD::SC: return "PPCISD::SC";
814 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
816 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
817 return VT.changeVectorElementTypeToInteger();
820 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
821 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
825 //===----------------------------------------------------------------------===//
826 // Node matching predicates, for use by the tblgen matching code.
827 //===----------------------------------------------------------------------===//
829 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
830 static bool isFloatingPointZero(SDValue Op) {
831 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
832 return CFP->getValueAPF().isZero();
833 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
834 // Maybe this has already been legalized into the constant pool?
835 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
836 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
837 return CFP->getValueAPF().isZero();
842 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
843 /// true if Op is undef or if it matches the specified value.
844 static bool isConstantOrUndef(int Op, int Val) {
845 return Op < 0 || Op == Val;
848 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
849 /// VPKUHUM instruction.
850 /// The ShuffleKind distinguishes between big-endian operations with
851 /// two different inputs (0), either-endian operations with two identical
852 /// inputs (1), and little-endian operantion with two different inputs (2).
853 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
854 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
856 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
857 if (ShuffleKind == 0) {
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
863 } else if (ShuffleKind == 2) {
866 for (unsigned i = 0; i != 16; ++i)
867 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
869 } else if (ShuffleKind == 1) {
870 unsigned j = IsLE ? 0 : 1;
871 for (unsigned i = 0; i != 8; ++i)
872 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
873 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
879 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
880 /// VPKUWUM instruction.
881 /// The ShuffleKind distinguishes between big-endian operations with
882 /// two different inputs (0), either-endian operations with two identical
883 /// inputs (1), and little-endian operantion with two different inputs (2).
884 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
885 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
887 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
888 if (ShuffleKind == 0) {
891 for (unsigned i = 0; i != 16; i += 2)
892 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
893 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
895 } else if (ShuffleKind == 2) {
898 for (unsigned i = 0; i != 16; i += 2)
899 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
900 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
902 } else if (ShuffleKind == 1) {
903 unsigned j = IsLE ? 0 : 2;
904 for (unsigned i = 0; i != 8; i += 2)
905 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
906 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
907 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
908 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
914 /// isVMerge - Common function, used to match vmrg* shuffles.
916 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
917 unsigned LHSStart, unsigned RHSStart) {
918 if (N->getValueType(0) != MVT::v16i8)
920 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
921 "Unsupported merge size!");
923 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
924 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
925 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
926 LHSStart+j+i*UnitSize) ||
927 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
928 RHSStart+j+i*UnitSize))
934 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
935 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
936 /// The ShuffleKind distinguishes between big-endian merges with two
937 /// different inputs (0), either-endian merges with two identical inputs (1),
938 /// and little-endian merges with two different inputs (2). For the latter,
939 /// the input operands are swapped (see PPCInstrAltivec.td).
940 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
941 unsigned ShuffleKind, SelectionDAG &DAG) {
942 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
943 if (ShuffleKind == 1) // unary
944 return isVMerge(N, UnitSize, 0, 0);
945 else if (ShuffleKind == 2) // swapped
946 return isVMerge(N, UnitSize, 0, 16);
950 if (ShuffleKind == 1) // unary
951 return isVMerge(N, UnitSize, 8, 8);
952 else if (ShuffleKind == 0) // normal
953 return isVMerge(N, UnitSize, 8, 24);
959 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
960 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
961 /// The ShuffleKind distinguishes between big-endian merges with two
962 /// different inputs (0), either-endian merges with two identical inputs (1),
963 /// and little-endian merges with two different inputs (2). For the latter,
964 /// the input operands are swapped (see PPCInstrAltivec.td).
965 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
966 unsigned ShuffleKind, SelectionDAG &DAG) {
967 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
968 if (ShuffleKind == 1) // unary
969 return isVMerge(N, UnitSize, 8, 8);
970 else if (ShuffleKind == 2) // swapped
971 return isVMerge(N, UnitSize, 8, 24);
975 if (ShuffleKind == 1) // unary
976 return isVMerge(N, UnitSize, 0, 0);
977 else if (ShuffleKind == 0) // normal
978 return isVMerge(N, UnitSize, 0, 16);
985 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
986 /// amount, otherwise return -1.
987 /// The ShuffleKind distinguishes between big-endian operations with two
988 /// different inputs (0), either-endian operations with two identical inputs
989 /// (1), and little-endian operations with two different inputs (2). For the
990 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
991 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
993 if (N->getValueType(0) != MVT::v16i8)
996 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
998 // Find the first non-undef value in the shuffle mask.
1000 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1003 if (i == 16) return -1; // all undef.
1005 // Otherwise, check to see if the rest of the elements are consecutively
1006 // numbered from this value.
1007 unsigned ShiftAmt = SVOp->getMaskElt(i);
1008 if (ShiftAmt < i) return -1;
1011 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1014 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1015 // Check the rest of the elements to see if they are consecutive.
1016 for (++i; i != 16; ++i)
1017 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1019 } else if (ShuffleKind == 1) {
1020 // Check the rest of the elements to see if they are consecutive.
1021 for (++i; i != 16; ++i)
1022 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1027 if (ShuffleKind == 2 && isLE)
1028 ShiftAmt = 16 - ShiftAmt;
1033 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1034 /// specifies a splat of a single element that is suitable for input to
1035 /// VSPLTB/VSPLTH/VSPLTW.
1036 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1037 assert(N->getValueType(0) == MVT::v16i8 &&
1038 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1040 // This is a splat operation if each element of the permute is the same, and
1041 // if the value doesn't reference the second vector.
1042 unsigned ElementBase = N->getMaskElt(0);
1044 // FIXME: Handle UNDEF elements too!
1045 if (ElementBase >= 16)
1048 // Check that the indices are consecutive, in the case of a multi-byte element
1049 // splatted with a v16i8 mask.
1050 for (unsigned i = 1; i != EltSize; ++i)
1051 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1054 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1055 if (N->getMaskElt(i) < 0) continue;
1056 for (unsigned j = 0; j != EltSize; ++j)
1057 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1063 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1065 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1066 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1068 APInt APVal, APUndef;
1072 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1073 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1074 return CFP->getValueAPF().isNegZero();
1079 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1080 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1081 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1082 SelectionDAG &DAG) {
1083 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1084 assert(isSplatShuffleMask(SVOp, EltSize));
1085 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1086 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1088 return SVOp->getMaskElt(0) / EltSize;
1091 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1092 /// by using a vspltis[bhw] instruction of the specified element size, return
1093 /// the constant being splatted. The ByteSize field indicates the number of
1094 /// bytes of each element [124] -> [bhw].
1095 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1096 SDValue OpVal(nullptr, 0);
1098 // If ByteSize of the splat is bigger than the element size of the
1099 // build_vector, then we have a case where we are checking for a splat where
1100 // multiple elements of the buildvector are folded together into a single
1101 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1102 unsigned EltSize = 16/N->getNumOperands();
1103 if (EltSize < ByteSize) {
1104 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1105 SDValue UniquedVals[4];
1106 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1108 // See if all of the elements in the buildvector agree across.
1109 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1110 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1111 // If the element isn't a constant, bail fully out.
1112 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1115 if (!UniquedVals[i&(Multiple-1)].getNode())
1116 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1117 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1118 return SDValue(); // no match.
1121 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1122 // either constant or undef values that are identical for each chunk. See
1123 // if these chunks can form into a larger vspltis*.
1125 // Check to see if all of the leading entries are either 0 or -1. If
1126 // neither, then this won't fit into the immediate field.
1127 bool LeadingZero = true;
1128 bool LeadingOnes = true;
1129 for (unsigned i = 0; i != Multiple-1; ++i) {
1130 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1132 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1133 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1135 // Finally, check the least significant entry.
1137 if (!UniquedVals[Multiple-1].getNode())
1138 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1139 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1141 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1144 if (!UniquedVals[Multiple-1].getNode())
1145 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1146 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1147 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1148 return DAG.getTargetConstant(Val, MVT::i32);
1154 // Check to see if this buildvec has a single non-undef value in its elements.
1155 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1156 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1157 if (!OpVal.getNode())
1158 OpVal = N->getOperand(i);
1159 else if (OpVal != N->getOperand(i))
1163 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1165 unsigned ValSizeInBytes = EltSize;
1167 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1168 Value = CN->getZExtValue();
1169 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1170 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1171 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1174 // If the splat value is larger than the element value, then we can never do
1175 // this splat. The only case that we could fit the replicated bits into our
1176 // immediate field for would be zero, and we prefer to use vxor for it.
1177 if (ValSizeInBytes < ByteSize) return SDValue();
1179 // If the element value is larger than the splat value, cut it in half and
1180 // check to see if the two halves are equal. Continue doing this until we
1181 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1182 while (ValSizeInBytes > ByteSize) {
1183 ValSizeInBytes >>= 1;
1185 // If the top half equals the bottom half, we're still ok.
1186 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1187 (Value & ((1 << (8*ValSizeInBytes))-1)))
1191 // Properly sign extend the value.
1192 int MaskVal = SignExtend32(Value, ByteSize * 8);
1194 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1195 if (MaskVal == 0) return SDValue();
1197 // Finally, if this value fits in a 5 bit sext field, return it
1198 if (SignExtend32<5>(MaskVal) == MaskVal)
1199 return DAG.getTargetConstant(MaskVal, MVT::i32);
1203 //===----------------------------------------------------------------------===//
1204 // Addressing Mode Selection
1205 //===----------------------------------------------------------------------===//
1207 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1208 /// or 64-bit immediate, and if the value can be accurately represented as a
1209 /// sign extension from a 16-bit value. If so, this returns true and the
1211 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1212 if (!isa<ConstantSDNode>(N))
1215 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1216 if (N->getValueType(0) == MVT::i32)
1217 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1219 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1221 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1222 return isIntS16Immediate(Op.getNode(), Imm);
1226 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1227 /// can be represented as an indexed [r+r] operation. Returns false if it
1228 /// can be more efficiently represented with [r+imm].
1229 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1231 SelectionDAG &DAG) const {
1233 if (N.getOpcode() == ISD::ADD) {
1234 if (isIntS16Immediate(N.getOperand(1), imm))
1235 return false; // r+i
1236 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1237 return false; // r+i
1239 Base = N.getOperand(0);
1240 Index = N.getOperand(1);
1242 } else if (N.getOpcode() == ISD::OR) {
1243 if (isIntS16Immediate(N.getOperand(1), imm))
1244 return false; // r+i can fold it if we can.
1246 // If this is an or of disjoint bitfields, we can codegen this as an add
1247 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1249 APInt LHSKnownZero, LHSKnownOne;
1250 APInt RHSKnownZero, RHSKnownOne;
1251 DAG.computeKnownBits(N.getOperand(0),
1252 LHSKnownZero, LHSKnownOne);
1254 if (LHSKnownZero.getBoolValue()) {
1255 DAG.computeKnownBits(N.getOperand(1),
1256 RHSKnownZero, RHSKnownOne);
1257 // If all of the bits are known zero on the LHS or RHS, the add won't
1259 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1260 Base = N.getOperand(0);
1261 Index = N.getOperand(1);
1270 // If we happen to be doing an i64 load or store into a stack slot that has
1271 // less than a 4-byte alignment, then the frame-index elimination may need to
1272 // use an indexed load or store instruction (because the offset may not be a
1273 // multiple of 4). The extra register needed to hold the offset comes from the
1274 // register scavenger, and it is possible that the scavenger will need to use
1275 // an emergency spill slot. As a result, we need to make sure that a spill slot
1276 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1278 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1279 // FIXME: This does not handle the LWA case.
1283 // NOTE: We'll exclude negative FIs here, which come from argument
1284 // lowering, because there are no known test cases triggering this problem
1285 // using packed structures (or similar). We can remove this exclusion if
1286 // we find such a test case. The reason why this is so test-case driven is
1287 // because this entire 'fixup' is only to prevent crashes (from the
1288 // register scavenger) on not-really-valid inputs. For example, if we have:
1290 // %b = bitcast i1* %a to i64*
1291 // store i64* a, i64 b
1292 // then the store should really be marked as 'align 1', but is not. If it
1293 // were marked as 'align 1' then the indexed form would have been
1294 // instruction-selected initially, and the problem this 'fixup' is preventing
1295 // won't happen regardless.
1299 MachineFunction &MF = DAG.getMachineFunction();
1300 MachineFrameInfo *MFI = MF.getFrameInfo();
1302 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1306 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1307 FuncInfo->setHasNonRISpills();
1310 /// Returns true if the address N can be represented by a base register plus
1311 /// a signed 16-bit displacement [r+imm], and if it is not better
1312 /// represented as reg+reg. If Aligned is true, only accept displacements
1313 /// suitable for STD and friends, i.e. multiples of 4.
1314 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1317 bool Aligned) const {
1318 // FIXME dl should come from parent load or store, not from address
1320 // If this can be more profitably realized as r+r, fail.
1321 if (SelectAddressRegReg(N, Disp, Base, DAG))
1324 if (N.getOpcode() == ISD::ADD) {
1326 if (isIntS16Immediate(N.getOperand(1), imm) &&
1327 (!Aligned || (imm & 3) == 0)) {
1328 Disp = DAG.getTargetConstant(imm, N.getValueType());
1329 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1330 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1331 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1333 Base = N.getOperand(0);
1335 return true; // [r+i]
1336 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1337 // Match LOAD (ADD (X, Lo(G))).
1338 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1339 && "Cannot handle constant offsets yet!");
1340 Disp = N.getOperand(1).getOperand(0); // The global address.
1341 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1342 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1343 Disp.getOpcode() == ISD::TargetConstantPool ||
1344 Disp.getOpcode() == ISD::TargetJumpTable);
1345 Base = N.getOperand(0);
1346 return true; // [&g+r]
1348 } else if (N.getOpcode() == ISD::OR) {
1350 if (isIntS16Immediate(N.getOperand(1), imm) &&
1351 (!Aligned || (imm & 3) == 0)) {
1352 // If this is an or of disjoint bitfields, we can codegen this as an add
1353 // (for better address arithmetic) if the LHS and RHS of the OR are
1354 // provably disjoint.
1355 APInt LHSKnownZero, LHSKnownOne;
1356 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1358 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1359 // If all of the bits are known zero on the LHS or RHS, the add won't
1361 if (FrameIndexSDNode *FI =
1362 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1363 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1364 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1366 Base = N.getOperand(0);
1368 Disp = DAG.getTargetConstant(imm, N.getValueType());
1372 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1373 // Loading from a constant address.
1375 // If this address fits entirely in a 16-bit sext immediate field, codegen
1378 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1379 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1380 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1381 CN->getValueType(0));
1385 // Handle 32-bit sext immediates with LIS + addr mode.
1386 if ((CN->getValueType(0) == MVT::i32 ||
1387 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1388 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1389 int Addr = (int)CN->getZExtValue();
1391 // Otherwise, break this down into an LIS + disp.
1392 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1394 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1395 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1396 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1401 Disp = DAG.getTargetConstant(0, getPointerTy());
1402 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1403 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1404 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1407 return true; // [r+0]
1410 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1411 /// represented as an indexed [r+r] operation.
1412 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1414 SelectionDAG &DAG) const {
1415 // Check to see if we can easily represent this as an [r+r] address. This
1416 // will fail if it thinks that the address is more profitably represented as
1417 // reg+imm, e.g. where imm = 0.
1418 if (SelectAddressRegReg(N, Base, Index, DAG))
1421 // If the operand is an addition, always emit this as [r+r], since this is
1422 // better (for code size, and execution, as the memop does the add for free)
1423 // than emitting an explicit add.
1424 if (N.getOpcode() == ISD::ADD) {
1425 Base = N.getOperand(0);
1426 Index = N.getOperand(1);
1430 // Otherwise, do it the hard way, using R0 as the base register.
1431 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1437 /// getPreIndexedAddressParts - returns true by value, base pointer and
1438 /// offset pointer and addressing mode by reference if the node's address
1439 /// can be legally represented as pre-indexed load / store address.
1440 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1442 ISD::MemIndexedMode &AM,
1443 SelectionDAG &DAG) const {
1444 if (DisablePPCPreinc) return false;
1450 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1451 Ptr = LD->getBasePtr();
1452 VT = LD->getMemoryVT();
1453 Alignment = LD->getAlignment();
1454 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1455 Ptr = ST->getBasePtr();
1456 VT = ST->getMemoryVT();
1457 Alignment = ST->getAlignment();
1462 // PowerPC doesn't have preinc load/store instructions for vectors.
1466 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1468 // Common code will reject creating a pre-inc form if the base pointer
1469 // is a frame index, or if N is a store and the base pointer is either
1470 // the same as or a predecessor of the value being stored. Check for
1471 // those situations here, and try with swapped Base/Offset instead.
1474 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1477 SDValue Val = cast<StoreSDNode>(N)->getValue();
1478 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1483 std::swap(Base, Offset);
1489 // LDU/STU can only handle immediates that are a multiple of 4.
1490 if (VT != MVT::i64) {
1491 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1494 // LDU/STU need an address with at least 4-byte alignment.
1498 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1502 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1503 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1504 // sext i32 to i64 when addr mode is r+i.
1505 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1506 LD->getExtensionType() == ISD::SEXTLOAD &&
1507 isa<ConstantSDNode>(Offset))
1515 //===----------------------------------------------------------------------===//
1516 // LowerOperation implementation
1517 //===----------------------------------------------------------------------===//
1519 /// GetLabelAccessInfo - Return true if we should reference labels using a
1520 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1521 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1522 unsigned &LoOpFlags,
1523 const GlobalValue *GV = nullptr) {
1524 HiOpFlags = PPCII::MO_HA;
1525 LoOpFlags = PPCII::MO_LO;
1527 // Don't use the pic base if not in PIC relocation model.
1528 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1531 HiOpFlags |= PPCII::MO_PIC_FLAG;
1532 LoOpFlags |= PPCII::MO_PIC_FLAG;
1535 // If this is a reference to a global value that requires a non-lazy-ptr, make
1536 // sure that instruction lowering adds it.
1537 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1538 HiOpFlags |= PPCII::MO_NLP_FLAG;
1539 LoOpFlags |= PPCII::MO_NLP_FLAG;
1541 if (GV->hasHiddenVisibility()) {
1542 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1543 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1550 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1551 SelectionDAG &DAG) {
1552 EVT PtrVT = HiPart.getValueType();
1553 SDValue Zero = DAG.getConstant(0, PtrVT);
1556 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1557 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1559 // With PIC, the first instruction is actually "GR+hi(&G)".
1561 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1562 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1564 // Generate non-pic code that has direct accesses to the constant pool.
1565 // The address of the global is just (hi(&g)+lo(&g)).
1566 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1569 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1570 SelectionDAG &DAG) const {
1571 EVT PtrVT = Op.getValueType();
1572 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1573 const Constant *C = CP->getConstVal();
1575 // 64-bit SVR4 ABI code is always position-independent.
1576 // The actual address of the GlobalValue is stored in the TOC.
1577 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1578 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1579 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1580 DAG.getRegister(PPC::X2, MVT::i64));
1583 unsigned MOHiFlag, MOLoFlag;
1584 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1586 if (isPIC && Subtarget.isSVR4ABI()) {
1587 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1588 PPCII::MO_PIC_FLAG);
1590 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1591 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1595 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1597 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1598 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1601 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1602 EVT PtrVT = Op.getValueType();
1603 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1605 // 64-bit SVR4 ABI code is always position-independent.
1606 // The actual address of the GlobalValue is stored in the TOC.
1607 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1608 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1609 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1610 DAG.getRegister(PPC::X2, MVT::i64));
1613 unsigned MOHiFlag, MOLoFlag;
1614 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1616 if (isPIC && Subtarget.isSVR4ABI()) {
1617 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1618 PPCII::MO_PIC_FLAG);
1620 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1621 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1624 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1625 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1626 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1629 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1630 SelectionDAG &DAG) const {
1631 EVT PtrVT = Op.getValueType();
1632 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1633 const BlockAddress *BA = BASDN->getBlockAddress();
1635 // 64-bit SVR4 ABI code is always position-independent.
1636 // The actual BlockAddress is stored in the TOC.
1637 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1638 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1639 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1640 DAG.getRegister(PPC::X2, MVT::i64));
1643 unsigned MOHiFlag, MOLoFlag;
1644 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1645 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1646 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1647 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1650 // Generate a call to __tls_get_addr for the given GOT entry Op.
1651 std::pair<SDValue,SDValue>
1652 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1653 SelectionDAG &DAG) const {
1655 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1656 TargetLowering::ArgListTy Args;
1657 TargetLowering::ArgListEntry Entry;
1659 Entry.Ty = IntPtrTy;
1660 Args.push_back(Entry);
1662 TargetLowering::CallLoweringInfo CLI(DAG);
1663 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1664 .setCallee(CallingConv::C, IntPtrTy,
1665 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1666 std::move(Args), 0);
1668 return LowerCallTo(CLI);
1671 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1672 SelectionDAG &DAG) const {
1674 // FIXME: TLS addresses currently use medium model code sequences,
1675 // which is the most useful form. Eventually support for small and
1676 // large models could be added if users need it, at the cost of
1677 // additional complexity.
1678 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1680 const GlobalValue *GV = GA->getGlobal();
1681 EVT PtrVT = getPointerTy();
1682 bool is64bit = Subtarget.isPPC64();
1683 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1684 PICLevel::Level picLevel = M->getPICLevel();
1686 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1688 if (Model == TLSModel::LocalExec) {
1689 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1690 PPCII::MO_TPREL_HA);
1691 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1692 PPCII::MO_TPREL_LO);
1693 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1694 is64bit ? MVT::i64 : MVT::i32);
1695 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1696 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1699 if (Model == TLSModel::InitialExec) {
1700 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1701 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1705 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1706 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1707 PtrVT, GOTReg, TGA);
1709 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1710 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1711 PtrVT, TGA, GOTPtr);
1712 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1715 if (Model == TLSModel::GeneralDynamic) {
1716 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1720 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1721 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1724 if (picLevel == PICLevel::Small)
1725 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1727 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1729 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1731 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1732 return CallResult.first;
1735 if (Model == TLSModel::LocalDynamic) {
1736 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1740 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1741 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1744 if (picLevel == PICLevel::Small)
1745 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1747 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1749 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1751 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1752 SDValue TLSAddr = CallResult.first;
1753 SDValue Chain = CallResult.second;
1754 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1755 Chain, TLSAddr, TGA);
1756 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1759 llvm_unreachable("Unknown TLS model!");
1762 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1763 SelectionDAG &DAG) const {
1764 EVT PtrVT = Op.getValueType();
1765 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1767 const GlobalValue *GV = GSDN->getGlobal();
1769 // 64-bit SVR4 ABI code is always position-independent.
1770 // The actual address of the GlobalValue is stored in the TOC.
1771 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1772 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1773 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1774 DAG.getRegister(PPC::X2, MVT::i64));
1777 unsigned MOHiFlag, MOLoFlag;
1778 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1780 if (isPIC && Subtarget.isSVR4ABI()) {
1781 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1783 PPCII::MO_PIC_FLAG);
1784 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1785 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1789 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1791 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1793 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1795 // If the global reference is actually to a non-lazy-pointer, we have to do an
1796 // extra load to get the address of the global.
1797 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1798 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1799 false, false, false, 0);
1803 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1804 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1807 if (Op.getValueType() == MVT::v2i64) {
1808 // When the operands themselves are v2i64 values, we need to do something
1809 // special because VSX has no underlying comparison operations for these.
1810 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1811 // Equality can be handled by casting to the legal type for Altivec
1812 // comparisons, everything else needs to be expanded.
1813 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1814 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1815 DAG.getSetCC(dl, MVT::v4i32,
1816 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1817 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1824 // We handle most of these in the usual way.
1828 // If we're comparing for equality to zero, expose the fact that this is
1829 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1830 // fold the new nodes.
1831 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1832 if (C->isNullValue() && CC == ISD::SETEQ) {
1833 EVT VT = Op.getOperand(0).getValueType();
1834 SDValue Zext = Op.getOperand(0);
1835 if (VT.bitsLT(MVT::i32)) {
1837 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1839 unsigned Log2b = Log2_32(VT.getSizeInBits());
1840 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1841 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1842 DAG.getConstant(Log2b, MVT::i32));
1843 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1845 // Leave comparisons against 0 and -1 alone for now, since they're usually
1846 // optimized. FIXME: revisit this when we can custom lower all setcc
1848 if (C->isAllOnesValue() || C->isNullValue())
1852 // If we have an integer seteq/setne, turn it into a compare against zero
1853 // by xor'ing the rhs with the lhs, which is faster than setting a
1854 // condition register, reading it back out, and masking the correct bit. The
1855 // normal approach here uses sub to do this instead of xor. Using xor exposes
1856 // the result to other bit-twiddling opportunities.
1857 EVT LHSVT = Op.getOperand(0).getValueType();
1858 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1859 EVT VT = Op.getValueType();
1860 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1862 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1867 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1868 const PPCSubtarget &Subtarget) const {
1869 SDNode *Node = Op.getNode();
1870 EVT VT = Node->getValueType(0);
1871 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1872 SDValue InChain = Node->getOperand(0);
1873 SDValue VAListPtr = Node->getOperand(1);
1874 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1877 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1880 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1881 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1882 false, false, false, 0);
1883 InChain = GprIndex.getValue(1);
1885 if (VT == MVT::i64) {
1886 // Check if GprIndex is even
1887 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1888 DAG.getConstant(1, MVT::i32));
1889 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1890 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1891 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1892 DAG.getConstant(1, MVT::i32));
1893 // Align GprIndex to be even if it isn't
1894 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1898 // fpr index is 1 byte after gpr
1899 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1900 DAG.getConstant(1, MVT::i32));
1903 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1904 FprPtr, MachinePointerInfo(SV), MVT::i8,
1905 false, false, false, 0);
1906 InChain = FprIndex.getValue(1);
1908 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1909 DAG.getConstant(8, MVT::i32));
1911 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1912 DAG.getConstant(4, MVT::i32));
1915 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1916 MachinePointerInfo(), false, false,
1918 InChain = OverflowArea.getValue(1);
1920 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1921 MachinePointerInfo(), false, false,
1923 InChain = RegSaveArea.getValue(1);
1925 // select overflow_area if index > 8
1926 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1927 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1929 // adjustment constant gpr_index * 4/8
1930 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1931 VT.isInteger() ? GprIndex : FprIndex,
1932 DAG.getConstant(VT.isInteger() ? 4 : 8,
1935 // OurReg = RegSaveArea + RegConstant
1936 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1939 // Floating types are 32 bytes into RegSaveArea
1940 if (VT.isFloatingPoint())
1941 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1942 DAG.getConstant(32, MVT::i32));
1944 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1945 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1946 VT.isInteger() ? GprIndex : FprIndex,
1947 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1950 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1951 VT.isInteger() ? VAListPtr : FprPtr,
1952 MachinePointerInfo(SV),
1953 MVT::i8, false, false, 0);
1955 // determine if we should load from reg_save_area or overflow_area
1956 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1958 // increase overflow_area by 4/8 if gpr/fpr > 8
1959 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1960 DAG.getConstant(VT.isInteger() ? 4 : 8,
1963 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1966 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1968 MachinePointerInfo(),
1969 MVT::i32, false, false, 0);
1971 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1972 false, false, false, 0);
1975 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1976 const PPCSubtarget &Subtarget) const {
1977 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1979 // We have to copy the entire va_list struct:
1980 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1981 return DAG.getMemcpy(Op.getOperand(0), Op,
1982 Op.getOperand(1), Op.getOperand(2),
1983 DAG.getConstant(12, MVT::i32), 8, false, true,
1984 MachinePointerInfo(), MachinePointerInfo());
1987 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1988 SelectionDAG &DAG) const {
1989 return Op.getOperand(0);
1992 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1993 SelectionDAG &DAG) const {
1994 SDValue Chain = Op.getOperand(0);
1995 SDValue Trmp = Op.getOperand(1); // trampoline
1996 SDValue FPtr = Op.getOperand(2); // nested function
1997 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2000 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2001 bool isPPC64 = (PtrVT == MVT::i64);
2003 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2006 TargetLowering::ArgListTy Args;
2007 TargetLowering::ArgListEntry Entry;
2009 Entry.Ty = IntPtrTy;
2010 Entry.Node = Trmp; Args.push_back(Entry);
2012 // TrampSize == (isPPC64 ? 48 : 40);
2013 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2014 isPPC64 ? MVT::i64 : MVT::i32);
2015 Args.push_back(Entry);
2017 Entry.Node = FPtr; Args.push_back(Entry);
2018 Entry.Node = Nest; Args.push_back(Entry);
2020 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2021 TargetLowering::CallLoweringInfo CLI(DAG);
2022 CLI.setDebugLoc(dl).setChain(Chain)
2023 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2024 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2025 std::move(Args), 0);
2027 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2028 return CallResult.second;
2031 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2032 const PPCSubtarget &Subtarget) const {
2033 MachineFunction &MF = DAG.getMachineFunction();
2034 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2038 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2039 // vastart just stores the address of the VarArgsFrameIndex slot into the
2040 // memory location argument.
2041 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2042 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2043 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2044 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2045 MachinePointerInfo(SV),
2049 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2050 // We suppose the given va_list is already allocated.
2053 // char gpr; /* index into the array of 8 GPRs
2054 // * stored in the register save area
2055 // * gpr=0 corresponds to r3,
2056 // * gpr=1 to r4, etc.
2058 // char fpr; /* index into the array of 8 FPRs
2059 // * stored in the register save area
2060 // * fpr=0 corresponds to f1,
2061 // * fpr=1 to f2, etc.
2063 // char *overflow_arg_area;
2064 // /* location on stack that holds
2065 // * the next overflow argument
2067 // char *reg_save_area;
2068 // /* where r3:r10 and f1:f8 (if saved)
2074 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2075 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2078 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2080 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2082 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2085 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2086 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2088 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2089 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2091 uint64_t FPROffset = 1;
2092 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2094 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2096 // Store first byte : number of int regs
2097 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2099 MachinePointerInfo(SV),
2100 MVT::i8, false, false, 0);
2101 uint64_t nextOffset = FPROffset;
2102 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2105 // Store second byte : number of float regs
2106 SDValue secondStore =
2107 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2108 MachinePointerInfo(SV, nextOffset), MVT::i8,
2110 nextOffset += StackOffset;
2111 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2113 // Store second word : arguments given on stack
2114 SDValue thirdStore =
2115 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2116 MachinePointerInfo(SV, nextOffset),
2118 nextOffset += FrameOffset;
2119 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2121 // Store third word : arguments given in registers
2122 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2123 MachinePointerInfo(SV, nextOffset),
2128 #include "PPCGenCallingConv.inc"
2130 // Function whose sole purpose is to kill compiler warnings
2131 // stemming from unused functions included from PPCGenCallingConv.inc.
2132 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2133 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2136 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2137 CCValAssign::LocInfo &LocInfo,
2138 ISD::ArgFlagsTy &ArgFlags,
2143 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2145 CCValAssign::LocInfo &LocInfo,
2146 ISD::ArgFlagsTy &ArgFlags,
2148 static const MCPhysReg ArgRegs[] = {
2149 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2150 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2152 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2154 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2156 // Skip one register if the first unallocated register has an even register
2157 // number and there are still argument registers available which have not been
2158 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2159 // need to skip a register if RegNum is odd.
2160 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2161 State.AllocateReg(ArgRegs[RegNum]);
2164 // Always return false here, as this function only makes sure that the first
2165 // unallocated register has an odd register number and does not actually
2166 // allocate a register for the current argument.
2170 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2172 CCValAssign::LocInfo &LocInfo,
2173 ISD::ArgFlagsTy &ArgFlags,
2175 static const MCPhysReg ArgRegs[] = {
2176 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2180 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2182 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2184 // If there is only one Floating-point register left we need to put both f64
2185 // values of a split ppc_fp128 value on the stack.
2186 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2187 State.AllocateReg(ArgRegs[RegNum]);
2190 // Always return false here, as this function only makes sure that the two f64
2191 // values a ppc_fp128 value is split into are both passed in registers or both
2192 // passed on the stack and does not actually allocate a register for the
2193 // current argument.
2197 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2199 static const MCPhysReg *GetFPR() {
2200 static const MCPhysReg FPR[] = {
2201 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2202 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2208 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2210 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2211 unsigned PtrByteSize) {
2212 unsigned ArgSize = ArgVT.getStoreSize();
2213 if (Flags.isByVal())
2214 ArgSize = Flags.getByValSize();
2216 // Round up to multiples of the pointer size, except for array members,
2217 // which are always packed.
2218 if (!Flags.isInConsecutiveRegs())
2219 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2224 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2226 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2227 ISD::ArgFlagsTy Flags,
2228 unsigned PtrByteSize) {
2229 unsigned Align = PtrByteSize;
2231 // Altivec parameters are padded to a 16 byte boundary.
2232 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2233 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2234 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2237 // ByVal parameters are aligned as requested.
2238 if (Flags.isByVal()) {
2239 unsigned BVAlign = Flags.getByValAlign();
2240 if (BVAlign > PtrByteSize) {
2241 if (BVAlign % PtrByteSize != 0)
2243 "ByVal alignment is not a multiple of the pointer size");
2249 // Array members are always packed to their original alignment.
2250 if (Flags.isInConsecutiveRegs()) {
2251 // If the array member was split into multiple registers, the first
2252 // needs to be aligned to the size of the full type. (Except for
2253 // ppcf128, which is only aligned as its f64 components.)
2254 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2255 Align = OrigVT.getStoreSize();
2257 Align = ArgVT.getStoreSize();
2263 /// CalculateStackSlotUsed - Return whether this argument will use its
2264 /// stack slot (instead of being passed in registers). ArgOffset,
2265 /// AvailableFPRs, and AvailableVRs must hold the current argument
2266 /// position, and will be updated to account for this argument.
2267 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2268 ISD::ArgFlagsTy Flags,
2269 unsigned PtrByteSize,
2270 unsigned LinkageSize,
2271 unsigned ParamAreaSize,
2272 unsigned &ArgOffset,
2273 unsigned &AvailableFPRs,
2274 unsigned &AvailableVRs) {
2275 bool UseMemory = false;
2277 // Respect alignment of argument on the stack.
2279 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2280 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2281 // If there's no space left in the argument save area, we must
2282 // use memory (this check also catches zero-sized arguments).
2283 if (ArgOffset >= LinkageSize + ParamAreaSize)
2286 // Allocate argument on the stack.
2287 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2288 if (Flags.isInConsecutiveRegsLast())
2289 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2290 // If we overran the argument save area, we must use memory
2291 // (this check catches arguments passed partially in memory)
2292 if (ArgOffset > LinkageSize + ParamAreaSize)
2295 // However, if the argument is actually passed in an FPR or a VR,
2296 // we don't use memory after all.
2297 if (!Flags.isByVal()) {
2298 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2299 if (AvailableFPRs > 0) {
2303 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2304 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2305 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2306 if (AvailableVRs > 0) {
2315 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2316 /// ensure minimum alignment required for target.
2317 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2318 unsigned NumBytes) {
2319 unsigned TargetAlign =
2320 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2321 unsigned AlignMask = TargetAlign - 1;
2322 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2327 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2328 CallingConv::ID CallConv, bool isVarArg,
2329 const SmallVectorImpl<ISD::InputArg>
2331 SDLoc dl, SelectionDAG &DAG,
2332 SmallVectorImpl<SDValue> &InVals)
2334 if (Subtarget.isSVR4ABI()) {
2335 if (Subtarget.isPPC64())
2336 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2339 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2342 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2348 PPCTargetLowering::LowerFormalArguments_32SVR4(
2350 CallingConv::ID CallConv, bool isVarArg,
2351 const SmallVectorImpl<ISD::InputArg>
2353 SDLoc dl, SelectionDAG &DAG,
2354 SmallVectorImpl<SDValue> &InVals) const {
2356 // 32-bit SVR4 ABI Stack Frame Layout:
2357 // +-----------------------------------+
2358 // +--> | Back chain |
2359 // | +-----------------------------------+
2360 // | | Floating-point register save area |
2361 // | +-----------------------------------+
2362 // | | General register save area |
2363 // | +-----------------------------------+
2364 // | | CR save word |
2365 // | +-----------------------------------+
2366 // | | VRSAVE save word |
2367 // | +-----------------------------------+
2368 // | | Alignment padding |
2369 // | +-----------------------------------+
2370 // | | Vector register save area |
2371 // | +-----------------------------------+
2372 // | | Local variable space |
2373 // | +-----------------------------------+
2374 // | | Parameter list area |
2375 // | +-----------------------------------+
2376 // | | LR save word |
2377 // | +-----------------------------------+
2378 // SP--> +--- | Back chain |
2379 // +-----------------------------------+
2382 // System V Application Binary Interface PowerPC Processor Supplement
2383 // AltiVec Technology Programming Interface Manual
2385 MachineFunction &MF = DAG.getMachineFunction();
2386 MachineFrameInfo *MFI = MF.getFrameInfo();
2387 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2389 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2390 // Potential tail calls could cause overwriting of argument stack slots.
2391 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2392 (CallConv == CallingConv::Fast));
2393 unsigned PtrByteSize = 4;
2395 // Assign locations to all of the incoming arguments.
2396 SmallVector<CCValAssign, 16> ArgLocs;
2397 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2400 // Reserve space for the linkage area on the stack.
2401 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2402 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2404 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2406 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2407 CCValAssign &VA = ArgLocs[i];
2409 // Arguments stored in registers.
2410 if (VA.isRegLoc()) {
2411 const TargetRegisterClass *RC;
2412 EVT ValVT = VA.getValVT();
2414 switch (ValVT.getSimpleVT().SimpleTy) {
2416 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2419 RC = &PPC::GPRCRegClass;
2422 RC = &PPC::F4RCRegClass;
2425 if (Subtarget.hasVSX())
2426 RC = &PPC::VSFRCRegClass;
2428 RC = &PPC::F8RCRegClass;
2434 RC = &PPC::VRRCRegClass;
2438 RC = &PPC::VSHRCRegClass;
2442 // Transform the arguments stored in physical registers into virtual ones.
2443 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2444 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2445 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2447 if (ValVT == MVT::i1)
2448 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2450 InVals.push_back(ArgValue);
2452 // Argument stored in memory.
2453 assert(VA.isMemLoc());
2455 unsigned ArgSize = VA.getLocVT().getStoreSize();
2456 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2459 // Create load nodes to retrieve arguments from the stack.
2460 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2461 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2462 MachinePointerInfo(),
2463 false, false, false, 0));
2467 // Assign locations to all of the incoming aggregate by value arguments.
2468 // Aggregates passed by value are stored in the local variable space of the
2469 // caller's stack frame, right above the parameter list area.
2470 SmallVector<CCValAssign, 16> ByValArgLocs;
2471 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2472 ByValArgLocs, *DAG.getContext());
2474 // Reserve stack space for the allocations in CCInfo.
2475 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2477 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2479 // Area that is at least reserved in the caller of this function.
2480 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2481 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2483 // Set the size that is at least reserved in caller of this function. Tail
2484 // call optimized function's reserved stack space needs to be aligned so that
2485 // taking the difference between two stack areas will result in an aligned
2487 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2488 FuncInfo->setMinReservedArea(MinReservedArea);
2490 SmallVector<SDValue, 8> MemOps;
2492 // If the function takes variable number of arguments, make a frame index for
2493 // the start of the first vararg value... for expansion of llvm.va_start.
2495 static const MCPhysReg GPArgRegs[] = {
2496 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2497 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2499 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2501 static const MCPhysReg FPArgRegs[] = {
2502 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2505 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2506 if (DisablePPCFloatInVariadic)
2509 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2511 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2514 // Make room for NumGPArgRegs and NumFPArgRegs.
2515 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2516 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2518 FuncInfo->setVarArgsStackOffset(
2519 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2520 CCInfo.getNextStackOffset(), true));
2522 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2523 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2525 // The fixed integer arguments of a variadic function are stored to the
2526 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2527 // the result of va_next.
2528 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2529 // Get an existing live-in vreg, or add a new one.
2530 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2532 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2534 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2535 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2536 MachinePointerInfo(), false, false, 0);
2537 MemOps.push_back(Store);
2538 // Increment the address by four for the next argument to store
2539 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2540 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2543 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2545 // The double arguments are stored to the VarArgsFrameIndex
2547 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2548 // Get an existing live-in vreg, or add a new one.
2549 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2551 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2553 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2554 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2555 MachinePointerInfo(), false, false, 0);
2556 MemOps.push_back(Store);
2557 // Increment the address by eight for the next argument to store
2558 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2560 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2564 if (!MemOps.empty())
2565 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2570 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2571 // value to MVT::i64 and then truncate to the correct register size.
2573 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2574 SelectionDAG &DAG, SDValue ArgVal,
2577 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2578 DAG.getValueType(ObjectVT));
2579 else if (Flags.isZExt())
2580 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2581 DAG.getValueType(ObjectVT));
2583 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2587 PPCTargetLowering::LowerFormalArguments_64SVR4(
2589 CallingConv::ID CallConv, bool isVarArg,
2590 const SmallVectorImpl<ISD::InputArg>
2592 SDLoc dl, SelectionDAG &DAG,
2593 SmallVectorImpl<SDValue> &InVals) const {
2594 // TODO: add description of PPC stack frame format, or at least some docs.
2596 bool isELFv2ABI = Subtarget.isELFv2ABI();
2597 bool isLittleEndian = Subtarget.isLittleEndian();
2598 MachineFunction &MF = DAG.getMachineFunction();
2599 MachineFrameInfo *MFI = MF.getFrameInfo();
2600 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2602 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2603 // Potential tail calls could cause overwriting of argument stack slots.
2604 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2605 (CallConv == CallingConv::Fast));
2606 unsigned PtrByteSize = 8;
2608 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2611 static const MCPhysReg GPR[] = {
2612 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2613 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2616 static const MCPhysReg *FPR = GetFPR();
2618 static const MCPhysReg VR[] = {
2619 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2620 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2622 static const MCPhysReg VSRH[] = {
2623 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2624 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2627 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2628 const unsigned Num_FPR_Regs = 13;
2629 const unsigned Num_VR_Regs = array_lengthof(VR);
2631 // Do a first pass over the arguments to determine whether the ABI
2632 // guarantees that our caller has allocated the parameter save area
2633 // on its stack frame. In the ELFv1 ABI, this is always the case;
2634 // in the ELFv2 ABI, it is true if this is a vararg function or if
2635 // any parameter is located in a stack slot.
2637 bool HasParameterArea = !isELFv2ABI || isVarArg;
2638 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2639 unsigned NumBytes = LinkageSize;
2640 unsigned AvailableFPRs = Num_FPR_Regs;
2641 unsigned AvailableVRs = Num_VR_Regs;
2642 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2643 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2644 PtrByteSize, LinkageSize, ParamAreaSize,
2645 NumBytes, AvailableFPRs, AvailableVRs))
2646 HasParameterArea = true;
2648 // Add DAG nodes to load the arguments or copy them out of registers. On
2649 // entry to a function on PPC, the arguments start after the linkage area,
2650 // although the first ones are often in registers.
2652 unsigned ArgOffset = LinkageSize;
2653 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2654 SmallVector<SDValue, 8> MemOps;
2655 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2656 unsigned CurArgIdx = 0;
2657 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2659 bool needsLoad = false;
2660 EVT ObjectVT = Ins[ArgNo].VT;
2661 EVT OrigVT = Ins[ArgNo].ArgVT;
2662 unsigned ObjSize = ObjectVT.getStoreSize();
2663 unsigned ArgSize = ObjSize;
2664 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2665 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2666 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2668 /* Respect alignment of argument on the stack. */
2670 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2671 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2672 unsigned CurArgOffset = ArgOffset;
2674 /* Compute GPR index associated with argument offset. */
2675 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2676 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2678 // FIXME the codegen can be much improved in some cases.
2679 // We do not have to keep everything in memory.
2680 if (Flags.isByVal()) {
2681 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2682 ObjSize = Flags.getByValSize();
2683 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2684 // Empty aggregate parameters do not take up registers. Examples:
2688 // etc. However, we have to provide a place-holder in InVals, so
2689 // pretend we have an 8-byte item at the current address for that
2692 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2693 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2694 InVals.push_back(FIN);
2698 // Create a stack object covering all stack doublewords occupied
2699 // by the argument. If the argument is (fully or partially) on
2700 // the stack, or if the argument is fully in registers but the
2701 // caller has allocated the parameter save anyway, we can refer
2702 // directly to the caller's stack frame. Otherwise, create a
2703 // local copy in our own frame.
2705 if (HasParameterArea ||
2706 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2707 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2709 FI = MFI->CreateStackObject(ArgSize, Align, false);
2710 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2712 // Handle aggregates smaller than 8 bytes.
2713 if (ObjSize < PtrByteSize) {
2714 // The value of the object is its address, which differs from the
2715 // address of the enclosing doubleword on big-endian systems.
2717 if (!isLittleEndian) {
2718 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2719 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2721 InVals.push_back(Arg);
2723 if (GPR_idx != Num_GPR_Regs) {
2724 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2725 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2728 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2729 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2730 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2731 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2732 MachinePointerInfo(FuncArg),
2733 ObjType, false, false, 0);
2735 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2736 // store the whole register as-is to the parameter save area
2738 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2739 MachinePointerInfo(FuncArg),
2743 MemOps.push_back(Store);
2745 // Whether we copied from a register or not, advance the offset
2746 // into the parameter save area by a full doubleword.
2747 ArgOffset += PtrByteSize;
2751 // The value of the object is its address, which is the address of
2752 // its first stack doubleword.
2753 InVals.push_back(FIN);
2755 // Store whatever pieces of the object are in registers to memory.
2756 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2757 if (GPR_idx == Num_GPR_Regs)
2760 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2761 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2764 SDValue Off = DAG.getConstant(j, PtrVT);
2765 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2767 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2768 MachinePointerInfo(FuncArg, j),
2770 MemOps.push_back(Store);
2773 ArgOffset += ArgSize;
2777 switch (ObjectVT.getSimpleVT().SimpleTy) {
2778 default: llvm_unreachable("Unhandled argument type!");
2782 // These can be scalar arguments or elements of an integer array type
2783 // passed directly. Clang may use those instead of "byval" aggregate
2784 // types to avoid forcing arguments to memory unnecessarily.
2785 if (GPR_idx != Num_GPR_Regs) {
2786 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2787 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2789 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2790 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2791 // value to MVT::i64 and then truncate to the correct register size.
2792 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2795 ArgSize = PtrByteSize;
2802 // These can be scalar arguments or elements of a float array type
2803 // passed directly. The latter are used to implement ELFv2 homogenous
2804 // float aggregates.
2805 if (FPR_idx != Num_FPR_Regs) {
2808 if (ObjectVT == MVT::f32)
2809 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2811 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2812 &PPC::VSFRCRegClass :
2813 &PPC::F8RCRegClass);
2815 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2817 } else if (GPR_idx != Num_GPR_Regs) {
2818 // This can only ever happen in the presence of f32 array types,
2819 // since otherwise we never run out of FPRs before running out
2821 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2822 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2824 if (ObjectVT == MVT::f32) {
2825 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2826 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2827 DAG.getConstant(32, MVT::i32));
2828 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2831 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2836 // When passing an array of floats, the array occupies consecutive
2837 // space in the argument area; only round up to the next doubleword
2838 // at the end of the array. Otherwise, each float takes 8 bytes.
2839 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2840 ArgOffset += ArgSize;
2841 if (Flags.isInConsecutiveRegsLast())
2842 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2850 // These can be scalar arguments or elements of a vector array type
2851 // passed directly. The latter are used to implement ELFv2 homogenous
2852 // vector aggregates.
2853 if (VR_idx != Num_VR_Regs) {
2854 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2855 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2856 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2857 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2866 // We need to load the argument to a virtual register if we determined
2867 // above that we ran out of physical registers of the appropriate type.
2869 if (ObjSize < ArgSize && !isLittleEndian)
2870 CurArgOffset += ArgSize - ObjSize;
2871 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2872 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2873 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2874 false, false, false, 0);
2877 InVals.push_back(ArgVal);
2880 // Area that is at least reserved in the caller of this function.
2881 unsigned MinReservedArea;
2882 if (HasParameterArea)
2883 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2885 MinReservedArea = LinkageSize;
2887 // Set the size that is at least reserved in caller of this function. Tail
2888 // call optimized functions' reserved stack space needs to be aligned so that
2889 // taking the difference between two stack areas will result in an aligned
2891 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2892 FuncInfo->setMinReservedArea(MinReservedArea);
2894 // If the function takes variable number of arguments, make a frame index for
2895 // the start of the first vararg value... for expansion of llvm.va_start.
2897 int Depth = ArgOffset;
2899 FuncInfo->setVarArgsFrameIndex(
2900 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2901 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2903 // If this function is vararg, store any remaining integer argument regs
2904 // to their spots on the stack so that they may be loaded by deferencing the
2905 // result of va_next.
2906 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2907 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2908 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2909 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2910 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2911 MachinePointerInfo(), false, false, 0);
2912 MemOps.push_back(Store);
2913 // Increment the address by four for the next argument to store
2914 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2915 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2919 if (!MemOps.empty())
2920 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2926 PPCTargetLowering::LowerFormalArguments_Darwin(
2928 CallingConv::ID CallConv, bool isVarArg,
2929 const SmallVectorImpl<ISD::InputArg>
2931 SDLoc dl, SelectionDAG &DAG,
2932 SmallVectorImpl<SDValue> &InVals) const {
2933 // TODO: add description of PPC stack frame format, or at least some docs.
2935 MachineFunction &MF = DAG.getMachineFunction();
2936 MachineFrameInfo *MFI = MF.getFrameInfo();
2937 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2939 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2940 bool isPPC64 = PtrVT == MVT::i64;
2941 // Potential tail calls could cause overwriting of argument stack slots.
2942 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2943 (CallConv == CallingConv::Fast));
2944 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2946 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2948 unsigned ArgOffset = LinkageSize;
2949 // Area that is at least reserved in caller of this function.
2950 unsigned MinReservedArea = ArgOffset;
2952 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2953 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2954 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2956 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2957 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2958 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2961 static const MCPhysReg *FPR = GetFPR();
2963 static const MCPhysReg VR[] = {
2964 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2965 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2968 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2969 const unsigned Num_FPR_Regs = 13;
2970 const unsigned Num_VR_Regs = array_lengthof( VR);
2972 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2974 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2976 // In 32-bit non-varargs functions, the stack space for vectors is after the
2977 // stack space for non-vectors. We do not use this space unless we have
2978 // too many vectors to fit in registers, something that only occurs in
2979 // constructed examples:), but we have to walk the arglist to figure
2980 // that out...for the pathological case, compute VecArgOffset as the
2981 // start of the vector parameter area. Computing VecArgOffset is the
2982 // entire point of the following loop.
2983 unsigned VecArgOffset = ArgOffset;
2984 if (!isVarArg && !isPPC64) {
2985 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2987 EVT ObjectVT = Ins[ArgNo].VT;
2988 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2990 if (Flags.isByVal()) {
2991 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2992 unsigned ObjSize = Flags.getByValSize();
2994 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2995 VecArgOffset += ArgSize;
2999 switch(ObjectVT.getSimpleVT().SimpleTy) {
3000 default: llvm_unreachable("Unhandled argument type!");
3006 case MVT::i64: // PPC64
3008 // FIXME: We are guaranteed to be !isPPC64 at this point.
3009 // Does MVT::i64 apply?
3016 // Nothing to do, we're only looking at Nonvector args here.
3021 // We've found where the vector parameter area in memory is. Skip the
3022 // first 12 parameters; these don't use that memory.
3023 VecArgOffset = ((VecArgOffset+15)/16)*16;
3024 VecArgOffset += 12*16;
3026 // Add DAG nodes to load the arguments or copy them out of registers. On
3027 // entry to a function on PPC, the arguments start after the linkage area,
3028 // although the first ones are often in registers.
3030 SmallVector<SDValue, 8> MemOps;
3031 unsigned nAltivecParamsAtEnd = 0;
3032 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3033 unsigned CurArgIdx = 0;
3034 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3036 bool needsLoad = false;
3037 EVT ObjectVT = Ins[ArgNo].VT;
3038 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3039 unsigned ArgSize = ObjSize;
3040 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3041 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3042 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3044 unsigned CurArgOffset = ArgOffset;
3046 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3047 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3048 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3049 if (isVarArg || isPPC64) {
3050 MinReservedArea = ((MinReservedArea+15)/16)*16;
3051 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3054 } else nAltivecParamsAtEnd++;
3056 // Calculate min reserved area.
3057 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3061 // FIXME the codegen can be much improved in some cases.
3062 // We do not have to keep everything in memory.
3063 if (Flags.isByVal()) {
3064 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3065 ObjSize = Flags.getByValSize();
3066 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3067 // Objects of size 1 and 2 are right justified, everything else is
3068 // left justified. This means the memory address is adjusted forwards.
3069 if (ObjSize==1 || ObjSize==2) {
3070 CurArgOffset = CurArgOffset + (4 - ObjSize);
3072 // The value of the object is its address.
3073 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3074 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3075 InVals.push_back(FIN);
3076 if (ObjSize==1 || ObjSize==2) {
3077 if (GPR_idx != Num_GPR_Regs) {
3080 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3082 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3083 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3084 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3085 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3086 MachinePointerInfo(FuncArg),
3087 ObjType, false, false, 0);
3088 MemOps.push_back(Store);
3092 ArgOffset += PtrByteSize;
3096 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3097 // Store whatever pieces of the object are in registers
3098 // to memory. ArgOffset will be the address of the beginning
3100 if (GPR_idx != Num_GPR_Regs) {
3103 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3105 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3106 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3107 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3108 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3109 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3110 MachinePointerInfo(FuncArg, j),
3112 MemOps.push_back(Store);
3114 ArgOffset += PtrByteSize;
3116 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3123 switch (ObjectVT.getSimpleVT().SimpleTy) {
3124 default: llvm_unreachable("Unhandled argument type!");
3128 if (GPR_idx != Num_GPR_Regs) {
3129 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3130 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3132 if (ObjectVT == MVT::i1)
3133 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3138 ArgSize = PtrByteSize;
3140 // All int arguments reserve stack space in the Darwin ABI.
3141 ArgOffset += PtrByteSize;
3145 case MVT::i64: // PPC64
3146 if (GPR_idx != Num_GPR_Regs) {
3147 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3148 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3150 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3151 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3152 // value to MVT::i64 and then truncate to the correct register size.
3153 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3158 ArgSize = PtrByteSize;
3160 // All int arguments reserve stack space in the Darwin ABI.
3166 // Every 4 bytes of argument space consumes one of the GPRs available for
3167 // argument passing.
3168 if (GPR_idx != Num_GPR_Regs) {
3170 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3173 if (FPR_idx != Num_FPR_Regs) {
3176 if (ObjectVT == MVT::f32)
3177 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3179 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3181 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3187 // All FP arguments reserve stack space in the Darwin ABI.
3188 ArgOffset += isPPC64 ? 8 : ObjSize;
3194 // Note that vector arguments in registers don't reserve stack space,
3195 // except in varargs functions.
3196 if (VR_idx != Num_VR_Regs) {
3197 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3198 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3200 while ((ArgOffset % 16) != 0) {
3201 ArgOffset += PtrByteSize;
3202 if (GPR_idx != Num_GPR_Regs)
3206 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3210 if (!isVarArg && !isPPC64) {
3211 // Vectors go after all the nonvectors.
3212 CurArgOffset = VecArgOffset;
3215 // Vectors are aligned.
3216 ArgOffset = ((ArgOffset+15)/16)*16;
3217 CurArgOffset = ArgOffset;
3225 // We need to load the argument to a virtual register if we determined above
3226 // that we ran out of physical registers of the appropriate type.
3228 int FI = MFI->CreateFixedObject(ObjSize,
3229 CurArgOffset + (ArgSize - ObjSize),
3231 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3232 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3233 false, false, false, 0);
3236 InVals.push_back(ArgVal);
3239 // Allow for Altivec parameters at the end, if needed.
3240 if (nAltivecParamsAtEnd) {
3241 MinReservedArea = ((MinReservedArea+15)/16)*16;
3242 MinReservedArea += 16*nAltivecParamsAtEnd;
3245 // Area that is at least reserved in the caller of this function.
3246 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3248 // Set the size that is at least reserved in caller of this function. Tail
3249 // call optimized functions' reserved stack space needs to be aligned so that
3250 // taking the difference between two stack areas will result in an aligned
3252 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3253 FuncInfo->setMinReservedArea(MinReservedArea);
3255 // If the function takes variable number of arguments, make a frame index for
3256 // the start of the first vararg value... for expansion of llvm.va_start.
3258 int Depth = ArgOffset;
3260 FuncInfo->setVarArgsFrameIndex(
3261 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3263 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3265 // If this function is vararg, store any remaining integer argument regs
3266 // to their spots on the stack so that they may be loaded by deferencing the
3267 // result of va_next.
3268 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3272 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3274 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3276 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3277 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3278 MachinePointerInfo(), false, false, 0);
3279 MemOps.push_back(Store);
3280 // Increment the address by four for the next argument to store
3281 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3282 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3286 if (!MemOps.empty())
3287 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3292 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3293 /// adjusted to accommodate the arguments for the tailcall.
3294 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3295 unsigned ParamSize) {
3297 if (!isTailCall) return 0;
3299 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3300 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3301 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3302 // Remember only if the new adjustement is bigger.
3303 if (SPDiff < FI->getTailCallSPDelta())
3304 FI->setTailCallSPDelta(SPDiff);
3309 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3310 /// for tail call optimization. Targets which want to do tail call
3311 /// optimization should implement this function.
3313 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3314 CallingConv::ID CalleeCC,
3316 const SmallVectorImpl<ISD::InputArg> &Ins,
3317 SelectionDAG& DAG) const {
3318 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3321 // Variable argument functions are not supported.
3325 MachineFunction &MF = DAG.getMachineFunction();
3326 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3327 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3328 // Functions containing by val parameters are not supported.
3329 for (unsigned i = 0; i != Ins.size(); i++) {
3330 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3331 if (Flags.isByVal()) return false;
3334 // Non-PIC/GOT tail calls are supported.
3335 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3338 // At the moment we can only do local tail calls (in same module, hidden
3339 // or protected) if we are generating PIC.
3340 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3341 return G->getGlobal()->hasHiddenVisibility()
3342 || G->getGlobal()->hasProtectedVisibility();
3348 /// isCallCompatibleAddress - Return the immediate to use if the specified
3349 /// 32-bit value is representable in the immediate field of a BxA instruction.
3350 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3351 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3352 if (!C) return nullptr;
3354 int Addr = C->getZExtValue();
3355 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3356 SignExtend32<26>(Addr) != Addr)
3357 return nullptr; // Top 6 bits have to be sext of immediate.
3359 return DAG.getConstant((int)C->getZExtValue() >> 2,
3360 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3365 struct TailCallArgumentInfo {
3370 TailCallArgumentInfo() : FrameIdx(0) {}
3375 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3377 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3379 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3380 SmallVectorImpl<SDValue> &MemOpChains,
3382 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3383 SDValue Arg = TailCallArgs[i].Arg;
3384 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3385 int FI = TailCallArgs[i].FrameIdx;
3386 // Store relative to framepointer.
3387 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3388 MachinePointerInfo::getFixedStack(FI),
3393 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3394 /// the appropriate stack slot for the tail call optimized function call.
3395 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3396 MachineFunction &MF,
3405 // Calculate the new stack slot for the return address.
3406 int SlotSize = isPPC64 ? 8 : 4;
3407 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3409 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3410 NewRetAddrLoc, true);
3411 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3412 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3413 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3414 MachinePointerInfo::getFixedStack(NewRetAddr),
3417 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3418 // slot as the FP is never overwritten.
3421 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3422 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3424 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3425 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3426 MachinePointerInfo::getFixedStack(NewFPIdx),
3433 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3434 /// the position of the argument.
3436 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3437 SDValue Arg, int SPDiff, unsigned ArgOffset,
3438 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3439 int Offset = ArgOffset + SPDiff;
3440 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3441 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3442 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3443 SDValue FIN = DAG.getFrameIndex(FI, VT);
3444 TailCallArgumentInfo Info;
3446 Info.FrameIdxOp = FIN;
3448 TailCallArguments.push_back(Info);
3451 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3452 /// stack slot. Returns the chain as result and the loaded frame pointers in
3453 /// LROpOut/FPOpout. Used when tail calling.
3454 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3462 // Load the LR and FP stack slot for later adjusting.
3463 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3464 LROpOut = getReturnAddrFrameIndex(DAG);
3465 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3466 false, false, false, 0);
3467 Chain = SDValue(LROpOut.getNode(), 1);
3469 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3470 // slot as the FP is never overwritten.
3472 FPOpOut = getFramePointerFrameIndex(DAG);
3473 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3474 false, false, false, 0);
3475 Chain = SDValue(FPOpOut.getNode(), 1);
3481 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3482 /// by "Src" to address "Dst" of size "Size". Alignment information is
3483 /// specified by the specific parameter attribute. The copy will be passed as
3484 /// a byval function parameter.
3485 /// Sometimes what we are copying is the end of a larger object, the part that
3486 /// does not fit in registers.
3488 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3489 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3491 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3492 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3493 false, false, MachinePointerInfo(),
3494 MachinePointerInfo());
3497 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3500 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3501 SDValue Arg, SDValue PtrOff, int SPDiff,
3502 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3503 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3504 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3506 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3511 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3513 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3514 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3515 DAG.getConstant(ArgOffset, PtrVT));
3517 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3518 MachinePointerInfo(), false, false, 0));
3519 // Calculate and remember argument location.
3520 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3525 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3526 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3527 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3528 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3529 MachineFunction &MF = DAG.getMachineFunction();
3531 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3532 // might overwrite each other in case of tail call optimization.
3533 SmallVector<SDValue, 8> MemOpChains2;
3534 // Do not flag preceding copytoreg stuff together with the following stuff.
3536 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3538 if (!MemOpChains2.empty())
3539 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3541 // Store the return address to the appropriate stack slot.
3542 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3543 isPPC64, isDarwinABI, dl);
3545 // Emit callseq_end just before tailcall node.
3546 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3547 DAG.getIntPtrConstant(0, true), InFlag, dl);
3548 InFlag = Chain.getValue(1);
3552 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3553 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3554 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3555 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3556 const PPCSubtarget &Subtarget) {
3558 bool isPPC64 = Subtarget.isPPC64();
3559 bool isSVR4ABI = Subtarget.isSVR4ABI();
3560 bool isELFv2ABI = Subtarget.isELFv2ABI();
3562 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3563 NodeTys.push_back(MVT::Other); // Returns a chain
3564 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3566 unsigned CallOpc = PPCISD::CALL;
3568 bool needIndirectCall = true;
3569 if (!isSVR4ABI || !isPPC64)
3570 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3571 // If this is an absolute destination address, use the munged value.
3572 Callee = SDValue(Dest, 0);
3573 needIndirectCall = false;
3576 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3577 unsigned OpFlags = 0;
3578 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3579 (Subtarget.getTargetTriple().isMacOSX() &&
3580 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3581 (G->getGlobal()->isDeclaration() ||
3582 G->getGlobal()->isWeakForLinker())) ||
3583 (Subtarget.isTargetELF() && !isPPC64 &&
3584 !G->getGlobal()->hasLocalLinkage() &&
3585 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3586 // PC-relative references to external symbols should go through $stub,
3587 // unless we're building with the leopard linker or later, which
3588 // automatically synthesizes these stubs.
3589 OpFlags = PPCII::MO_PLT_OR_STUB;
3592 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3593 // every direct call is) turn it into a TargetGlobalAddress /
3594 // TargetExternalSymbol node so that legalize doesn't hack it.
3595 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3596 Callee.getValueType(), 0, OpFlags);
3597 needIndirectCall = false;
3600 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3601 unsigned char OpFlags = 0;
3603 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3604 (Subtarget.getTargetTriple().isMacOSX() &&
3605 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3606 (Subtarget.isTargetELF() && !isPPC64 &&
3607 DAG.getTarget().getRelocationModel() == Reloc::PIC_) ) {
3608 // PC-relative references to external symbols should go through $stub,
3609 // unless we're building with the leopard linker or later, which
3610 // automatically synthesizes these stubs.
3611 OpFlags = PPCII::MO_PLT_OR_STUB;
3614 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3616 needIndirectCall = false;
3619 if (needIndirectCall) {
3620 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3621 // to do the call, we can't use PPCISD::CALL.
3622 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3624 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3625 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3626 // entry point, but to the function descriptor (the function entry point
3627 // address is part of the function descriptor though).
3628 // The function descriptor is a three doubleword structure with the
3629 // following fields: function entry point, TOC base address and
3630 // environment pointer.
3631 // Thus for a call through a function pointer, the following actions need
3633 // 1. Save the TOC of the caller in the TOC save area of its stack
3634 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3635 // 2. Load the address of the function entry point from the function
3637 // 3. Load the TOC of the callee from the function descriptor into r2.
3638 // 4. Load the environment pointer from the function descriptor into
3640 // 5. Branch to the function entry point address.
3641 // 6. On return of the callee, the TOC of the caller needs to be
3642 // restored (this is done in FinishCall()).
3644 // All those operations are flagged together to ensure that no other
3645 // operations can be scheduled in between. E.g. without flagging the
3646 // operations together, a TOC access in the caller could be scheduled
3647 // between the load of the callee TOC and the branch to the callee, which
3648 // results in the TOC access going through the TOC of the callee instead
3649 // of going through the TOC of the caller, which leads to incorrect code.
3651 // Load the address of the function entry point from the function
3653 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3654 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3655 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3656 Chain = LoadFuncPtr.getValue(1);
3657 InFlag = LoadFuncPtr.getValue(2);
3659 // Load environment pointer into r11.
3660 // Offset of the environment pointer within the function descriptor.
3661 SDValue PtrOff = DAG.getIntPtrConstant(16);
3663 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3664 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3666 Chain = LoadEnvPtr.getValue(1);
3667 InFlag = LoadEnvPtr.getValue(2);
3669 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3671 Chain = EnvVal.getValue(0);
3672 InFlag = EnvVal.getValue(1);
3674 // Load TOC of the callee into r2. We are using a target-specific load
3675 // with r2 hard coded, because the result of a target-independent load
3676 // would never go directly into r2, since r2 is a reserved register (which
3677 // prevents the register allocator from allocating it), resulting in an
3678 // additional register being allocated and an unnecessary move instruction
3680 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3681 SDValue TOCOff = DAG.getIntPtrConstant(8);
3682 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3683 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3685 Chain = LoadTOCPtr.getValue(0);
3686 InFlag = LoadTOCPtr.getValue(1);
3688 MTCTROps[0] = Chain;
3689 MTCTROps[1] = LoadFuncPtr;
3690 MTCTROps[2] = InFlag;
3693 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3694 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3695 InFlag = Chain.getValue(1);
3698 NodeTys.push_back(MVT::Other);
3699 NodeTys.push_back(MVT::Glue);
3700 Ops.push_back(Chain);
3701 CallOpc = PPCISD::BCTRL;
3702 Callee.setNode(nullptr);
3703 // Add use of X11 (holding environment pointer)
3704 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3705 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3706 // Add CTR register as callee so a bctr can be emitted later.
3708 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3711 // If this is a direct call, pass the chain and the callee.
3712 if (Callee.getNode()) {
3713 Ops.push_back(Chain);
3714 Ops.push_back(Callee);
3716 // If this is a call to __tls_get_addr, find the symbol whose address
3717 // is to be taken and add it to the list. This will be used to
3718 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3719 // We find the symbol by walking the chain to the CopyFromReg, walking
3720 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3721 // pulling the symbol from that node.
3722 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3723 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3724 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3725 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3726 SDValue TGTAddr = AddI->getOperand(1);
3727 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3728 "Didn't find target global TLS address where we expected one");
3729 Ops.push_back(TGTAddr);
3730 CallOpc = PPCISD::CALL_TLS;
3733 // If this is a tail call add stack pointer delta.
3735 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3737 // Add argument registers to the end of the list so that they are known live
3739 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3740 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3741 RegsToPass[i].second.getValueType()));
3743 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3744 if (Callee.getNode() && isELFv2ABI)
3745 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3751 bool isLocalCall(const SDValue &Callee)
3753 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3754 return !G->getGlobal()->isDeclaration() &&
3755 !G->getGlobal()->isWeakForLinker();
3760 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3761 CallingConv::ID CallConv, bool isVarArg,
3762 const SmallVectorImpl<ISD::InputArg> &Ins,
3763 SDLoc dl, SelectionDAG &DAG,
3764 SmallVectorImpl<SDValue> &InVals) const {
3766 SmallVector<CCValAssign, 16> RVLocs;
3767 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3769 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3771 // Copy all of the result registers out of their specified physreg.
3772 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3773 CCValAssign &VA = RVLocs[i];
3774 assert(VA.isRegLoc() && "Can only return in registers!");
3776 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3777 VA.getLocReg(), VA.getLocVT(), InFlag);
3778 Chain = Val.getValue(1);
3779 InFlag = Val.getValue(2);
3781 switch (VA.getLocInfo()) {
3782 default: llvm_unreachable("Unknown loc info!");
3783 case CCValAssign::Full: break;
3784 case CCValAssign::AExt:
3785 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3787 case CCValAssign::ZExt:
3788 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3789 DAG.getValueType(VA.getValVT()));
3790 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3792 case CCValAssign::SExt:
3793 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3794 DAG.getValueType(VA.getValVT()));
3795 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3799 InVals.push_back(Val);
3806 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3807 bool isTailCall, bool isVarArg,
3809 SmallVector<std::pair<unsigned, SDValue>, 8>
3811 SDValue InFlag, SDValue Chain,
3813 int SPDiff, unsigned NumBytes,
3814 const SmallVectorImpl<ISD::InputArg> &Ins,
3815 SmallVectorImpl<SDValue> &InVals) const {
3817 bool isELFv2ABI = Subtarget.isELFv2ABI();
3818 std::vector<EVT> NodeTys;
3819 SmallVector<SDValue, 8> Ops;
3820 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3821 isTailCall, RegsToPass, Ops, NodeTys,
3824 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3825 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3826 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3828 // When performing tail call optimization the callee pops its arguments off
3829 // the stack. Account for this here so these bytes can be pushed back on in
3830 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3831 int BytesCalleePops =
3832 (CallConv == CallingConv::Fast &&
3833 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3835 // Add a register mask operand representing the call-preserved registers.
3836 const TargetRegisterInfo *TRI =
3837 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3838 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3839 assert(Mask && "Missing call preserved mask for calling convention");
3840 Ops.push_back(DAG.getRegisterMask(Mask));
3842 if (InFlag.getNode())
3843 Ops.push_back(InFlag);
3847 assert(((Callee.getOpcode() == ISD::Register &&
3848 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3849 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3850 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3851 isa<ConstantSDNode>(Callee)) &&
3852 "Expecting an global address, external symbol, absolute value or register");
3854 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3857 // Add a NOP immediately after the branch instruction when using the 64-bit
3858 // SVR4 ABI. At link time, if caller and callee are in a different module and
3859 // thus have a different TOC, the call will be replaced with a call to a stub
3860 // function which saves the current TOC, loads the TOC of the callee and
3861 // branches to the callee. The NOP will be replaced with a load instruction
3862 // which restores the TOC of the caller from the TOC save slot of the current
3863 // stack frame. If caller and callee belong to the same module (and have the
3864 // same TOC), the NOP will remain unchanged.
3866 bool needsTOCRestore = false;
3867 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3868 if (CallOpc == PPCISD::BCTRL) {
3869 // This is a call through a function pointer.
3870 // Restore the caller TOC from the save area into R2.
3871 // See PrepareCall() for more information about calls through function
3872 // pointers in the 64-bit SVR4 ABI.
3873 // We are using a target-specific load with r2 hard coded, because the
3874 // result of a target-independent load would never go directly into r2,
3875 // since r2 is a reserved register (which prevents the register allocator
3876 // from allocating it), resulting in an additional register being
3877 // allocated and an unnecessary move instruction being generated.
3878 needsTOCRestore = true;
3879 } else if ((CallOpc == PPCISD::CALL) &&
3880 (!isLocalCall(Callee) ||
3881 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3882 // Otherwise insert NOP for non-local calls.
3883 CallOpc = PPCISD::CALL_NOP;
3884 } else if (CallOpc == PPCISD::CALL_TLS)
3885 // For 64-bit SVR4, TLS calls are always non-local.
3886 CallOpc = PPCISD::CALL_NOP_TLS;
3889 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3890 InFlag = Chain.getValue(1);
3892 if (needsTOCRestore) {
3893 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3894 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3895 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3896 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3897 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3898 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3899 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3900 InFlag = Chain.getValue(1);
3903 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3904 DAG.getIntPtrConstant(BytesCalleePops, true),
3907 InFlag = Chain.getValue(1);
3909 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3910 Ins, dl, DAG, InVals);
3914 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3915 SmallVectorImpl<SDValue> &InVals) const {
3916 SelectionDAG &DAG = CLI.DAG;
3918 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3919 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3920 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3921 SDValue Chain = CLI.Chain;
3922 SDValue Callee = CLI.Callee;
3923 bool &isTailCall = CLI.IsTailCall;
3924 CallingConv::ID CallConv = CLI.CallConv;
3925 bool isVarArg = CLI.IsVarArg;
3928 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3931 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3932 report_fatal_error("failed to perform tail call elimination on a call "
3933 "site marked musttail");
3935 if (Subtarget.isSVR4ABI()) {
3936 if (Subtarget.isPPC64())
3937 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3938 isTailCall, Outs, OutVals, Ins,
3941 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3942 isTailCall, Outs, OutVals, Ins,
3946 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3947 isTailCall, Outs, OutVals, Ins,
3952 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3953 CallingConv::ID CallConv, bool isVarArg,
3955 const SmallVectorImpl<ISD::OutputArg> &Outs,
3956 const SmallVectorImpl<SDValue> &OutVals,
3957 const SmallVectorImpl<ISD::InputArg> &Ins,
3958 SDLoc dl, SelectionDAG &DAG,
3959 SmallVectorImpl<SDValue> &InVals) const {
3960 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3961 // of the 32-bit SVR4 ABI stack frame layout.
3963 assert((CallConv == CallingConv::C ||
3964 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3966 unsigned PtrByteSize = 4;
3968 MachineFunction &MF = DAG.getMachineFunction();
3970 // Mark this function as potentially containing a function that contains a
3971 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3972 // and restoring the callers stack pointer in this functions epilog. This is
3973 // done because by tail calling the called function might overwrite the value
3974 // in this function's (MF) stack pointer stack slot 0(SP).
3975 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3976 CallConv == CallingConv::Fast)
3977 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3979 // Count how many bytes are to be pushed on the stack, including the linkage
3980 // area, parameter list area and the part of the local variable space which
3981 // contains copies of aggregates which are passed by value.
3983 // Assign locations to all of the outgoing arguments.
3984 SmallVector<CCValAssign, 16> ArgLocs;
3985 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
3988 // Reserve space for the linkage area on the stack.
3989 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
3993 // Handle fixed and variable vector arguments differently.
3994 // Fixed vector arguments go into registers as long as registers are
3995 // available. Variable vector arguments always go into memory.
3996 unsigned NumArgs = Outs.size();
3998 for (unsigned i = 0; i != NumArgs; ++i) {
3999 MVT ArgVT = Outs[i].VT;
4000 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4003 if (Outs[i].IsFixed) {
4004 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4007 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4013 errs() << "Call operand #" << i << " has unhandled type "
4014 << EVT(ArgVT).getEVTString() << "\n";
4016 llvm_unreachable(nullptr);
4020 // All arguments are treated the same.
4021 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4024 // Assign locations to all of the outgoing aggregate by value arguments.
4025 SmallVector<CCValAssign, 16> ByValArgLocs;
4026 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4027 ByValArgLocs, *DAG.getContext());
4029 // Reserve stack space for the allocations in CCInfo.
4030 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4032 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4034 // Size of the linkage area, parameter list area and the part of the local
4035 // space variable where copies of aggregates which are passed by value are
4037 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4039 // Calculate by how many bytes the stack has to be adjusted in case of tail
4040 // call optimization.
4041 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4043 // Adjust the stack pointer for the new arguments...
4044 // These operations are automatically eliminated by the prolog/epilog pass
4045 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4047 SDValue CallSeqStart = Chain;
4049 // Load the return address and frame pointer so it can be moved somewhere else
4052 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4055 // Set up a copy of the stack pointer for use loading and storing any
4056 // arguments that may not fit in the registers available for argument
4058 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4060 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4061 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4062 SmallVector<SDValue, 8> MemOpChains;
4064 bool seenFloatArg = false;
4065 // Walk the register/memloc assignments, inserting copies/loads.
4066 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4069 CCValAssign &VA = ArgLocs[i];
4070 SDValue Arg = OutVals[i];
4071 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4073 if (Flags.isByVal()) {
4074 // Argument is an aggregate which is passed by value, thus we need to
4075 // create a copy of it in the local variable space of the current stack
4076 // frame (which is the stack frame of the caller) and pass the address of
4077 // this copy to the callee.
4078 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4079 CCValAssign &ByValVA = ByValArgLocs[j++];
4080 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4082 // Memory reserved in the local variable space of the callers stack frame.
4083 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4085 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4086 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4088 // Create a copy of the argument in the local area of the current
4090 SDValue MemcpyCall =
4091 CreateCopyOfByValArgument(Arg, PtrOff,
4092 CallSeqStart.getNode()->getOperand(0),
4095 // This must go outside the CALLSEQ_START..END.
4096 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4097 CallSeqStart.getNode()->getOperand(1),
4099 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4100 NewCallSeqStart.getNode());
4101 Chain = CallSeqStart = NewCallSeqStart;
4103 // Pass the address of the aggregate copy on the stack either in a
4104 // physical register or in the parameter list area of the current stack
4105 // frame to the callee.
4109 if (VA.isRegLoc()) {
4110 if (Arg.getValueType() == MVT::i1)
4111 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4113 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4114 // Put argument in a physical register.
4115 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4117 // Put argument in the parameter list area of the current stack frame.
4118 assert(VA.isMemLoc());
4119 unsigned LocMemOffset = VA.getLocMemOffset();
4122 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4123 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4125 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4126 MachinePointerInfo(),
4129 // Calculate and remember argument location.
4130 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4136 if (!MemOpChains.empty())
4137 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4139 // Build a sequence of copy-to-reg nodes chained together with token chain
4140 // and flag operands which copy the outgoing args into the appropriate regs.
4142 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4143 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4144 RegsToPass[i].second, InFlag);
4145 InFlag = Chain.getValue(1);
4148 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4151 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4152 SDValue Ops[] = { Chain, InFlag };
4154 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4155 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4157 InFlag = Chain.getValue(1);
4161 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4162 false, TailCallArguments);
4164 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4165 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4169 // Copy an argument into memory, being careful to do this outside the
4170 // call sequence for the call to which the argument belongs.
4172 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4173 SDValue CallSeqStart,
4174 ISD::ArgFlagsTy Flags,
4177 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4178 CallSeqStart.getNode()->getOperand(0),
4180 // The MEMCPY must go outside the CALLSEQ_START..END.
4181 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4182 CallSeqStart.getNode()->getOperand(1),
4184 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4185 NewCallSeqStart.getNode());
4186 return NewCallSeqStart;
4190 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4191 CallingConv::ID CallConv, bool isVarArg,
4193 const SmallVectorImpl<ISD::OutputArg> &Outs,
4194 const SmallVectorImpl<SDValue> &OutVals,
4195 const SmallVectorImpl<ISD::InputArg> &Ins,
4196 SDLoc dl, SelectionDAG &DAG,
4197 SmallVectorImpl<SDValue> &InVals) const {
4199 bool isELFv2ABI = Subtarget.isELFv2ABI();
4200 bool isLittleEndian = Subtarget.isLittleEndian();
4201 unsigned NumOps = Outs.size();
4203 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4204 unsigned PtrByteSize = 8;
4206 MachineFunction &MF = DAG.getMachineFunction();
4208 // Mark this function as potentially containing a function that contains a
4209 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4210 // and restoring the callers stack pointer in this functions epilog. This is
4211 // done because by tail calling the called function might overwrite the value
4212 // in this function's (MF) stack pointer stack slot 0(SP).
4213 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4214 CallConv == CallingConv::Fast)
4215 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4217 // Count how many bytes are to be pushed on the stack, including the linkage
4218 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4219 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4220 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4221 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4223 unsigned NumBytes = LinkageSize;
4225 // Add up all the space actually used.
4226 for (unsigned i = 0; i != NumOps; ++i) {
4227 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4228 EVT ArgVT = Outs[i].VT;
4229 EVT OrigVT = Outs[i].ArgVT;
4231 /* Respect alignment of argument on the stack. */
4233 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4234 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4236 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4237 if (Flags.isInConsecutiveRegsLast())
4238 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4241 unsigned NumBytesActuallyUsed = NumBytes;
4243 // The prolog code of the callee may store up to 8 GPR argument registers to
4244 // the stack, allowing va_start to index over them in memory if its varargs.
4245 // Because we cannot tell if this is needed on the caller side, we have to
4246 // conservatively assume that it is needed. As such, make sure we have at
4247 // least enough stack space for the caller to store the 8 GPRs.
4248 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4249 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4251 // Tail call needs the stack to be aligned.
4252 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4253 CallConv == CallingConv::Fast)
4254 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4256 // Calculate by how many bytes the stack has to be adjusted in case of tail
4257 // call optimization.
4258 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4260 // To protect arguments on the stack from being clobbered in a tail call,
4261 // force all the loads to happen before doing any other lowering.
4263 Chain = DAG.getStackArgumentTokenFactor(Chain);
4265 // Adjust the stack pointer for the new arguments...
4266 // These operations are automatically eliminated by the prolog/epilog pass
4267 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4269 SDValue CallSeqStart = Chain;
4271 // Load the return address and frame pointer so it can be move somewhere else
4274 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4277 // Set up a copy of the stack pointer for use loading and storing any
4278 // arguments that may not fit in the registers available for argument
4280 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4282 // Figure out which arguments are going to go in registers, and which in
4283 // memory. Also, if this is a vararg function, floating point operations
4284 // must be stored to our stack, and loaded into integer regs as well, if
4285 // any integer regs are available for argument passing.
4286 unsigned ArgOffset = LinkageSize;
4287 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4289 static const MCPhysReg GPR[] = {
4290 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4291 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4293 static const MCPhysReg *FPR = GetFPR();
4295 static const MCPhysReg VR[] = {
4296 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4297 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4299 static const MCPhysReg VSRH[] = {
4300 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4301 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4304 const unsigned NumGPRs = array_lengthof(GPR);
4305 const unsigned NumFPRs = 13;
4306 const unsigned NumVRs = array_lengthof(VR);
4308 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4309 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4311 SmallVector<SDValue, 8> MemOpChains;
4312 for (unsigned i = 0; i != NumOps; ++i) {
4313 SDValue Arg = OutVals[i];
4314 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4315 EVT ArgVT = Outs[i].VT;
4316 EVT OrigVT = Outs[i].ArgVT;
4318 /* Respect alignment of argument on the stack. */
4320 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4321 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4323 /* Compute GPR index associated with argument offset. */
4324 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4325 GPR_idx = std::min(GPR_idx, NumGPRs);
4327 // PtrOff will be used to store the current argument to the stack if a
4328 // register cannot be found for it.
4331 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4333 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4335 // Promote integers to 64-bit values.
4336 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4337 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4338 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4339 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4342 // FIXME memcpy is used way more than necessary. Correctness first.
4343 // Note: "by value" is code for passing a structure by value, not
4345 if (Flags.isByVal()) {
4346 // Note: Size includes alignment padding, so
4347 // struct x { short a; char b; }
4348 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4349 // These are the proper values we need for right-justifying the
4350 // aggregate in a parameter register.
4351 unsigned Size = Flags.getByValSize();
4353 // An empty aggregate parameter takes up no storage and no
4358 // All aggregates smaller than 8 bytes must be passed right-justified.
4359 if (Size==1 || Size==2 || Size==4) {
4360 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4361 if (GPR_idx != NumGPRs) {
4362 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4363 MachinePointerInfo(), VT,
4364 false, false, false, 0);
4365 MemOpChains.push_back(Load.getValue(1));
4366 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4368 ArgOffset += PtrByteSize;
4373 if (GPR_idx == NumGPRs && Size < 8) {
4374 SDValue AddPtr = PtrOff;
4375 if (!isLittleEndian) {
4376 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4377 PtrOff.getValueType());
4378 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4380 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4383 ArgOffset += PtrByteSize;
4386 // Copy entire object into memory. There are cases where gcc-generated
4387 // code assumes it is there, even if it could be put entirely into
4388 // registers. (This is not what the doc says.)
4390 // FIXME: The above statement is likely due to a misunderstanding of the
4391 // documents. All arguments must be copied into the parameter area BY
4392 // THE CALLEE in the event that the callee takes the address of any
4393 // formal argument. That has not yet been implemented. However, it is
4394 // reasonable to use the stack area as a staging area for the register
4397 // Skip this for small aggregates, as we will use the same slot for a
4398 // right-justified copy, below.
4400 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4404 // When a register is available, pass a small aggregate right-justified.
4405 if (Size < 8 && GPR_idx != NumGPRs) {
4406 // The easiest way to get this right-justified in a register
4407 // is to copy the structure into the rightmost portion of a
4408 // local variable slot, then load the whole slot into the
4410 // FIXME: The memcpy seems to produce pretty awful code for
4411 // small aggregates, particularly for packed ones.
4412 // FIXME: It would be preferable to use the slot in the
4413 // parameter save area instead of a new local variable.
4414 SDValue AddPtr = PtrOff;
4415 if (!isLittleEndian) {
4416 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4417 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4419 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4423 // Load the slot into the register.
4424 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4425 MachinePointerInfo(),
4426 false, false, false, 0);
4427 MemOpChains.push_back(Load.getValue(1));
4428 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4430 // Done with this argument.
4431 ArgOffset += PtrByteSize;
4435 // For aggregates larger than PtrByteSize, copy the pieces of the
4436 // object that fit into registers from the parameter save area.
4437 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4438 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4439 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4440 if (GPR_idx != NumGPRs) {
4441 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4442 MachinePointerInfo(),
4443 false, false, false, 0);
4444 MemOpChains.push_back(Load.getValue(1));
4445 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4446 ArgOffset += PtrByteSize;
4448 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4455 switch (Arg.getSimpleValueType().SimpleTy) {
4456 default: llvm_unreachable("Unexpected ValueType for argument!");
4460 // These can be scalar arguments or elements of an integer array type
4461 // passed directly. Clang may use those instead of "byval" aggregate
4462 // types to avoid forcing arguments to memory unnecessarily.
4463 if (GPR_idx != NumGPRs) {
4464 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4466 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4467 true, isTailCall, false, MemOpChains,
4468 TailCallArguments, dl);
4470 ArgOffset += PtrByteSize;
4474 // These can be scalar arguments or elements of a float array type
4475 // passed directly. The latter are used to implement ELFv2 homogenous
4476 // float aggregates.
4478 // Named arguments go into FPRs first, and once they overflow, the
4479 // remaining arguments go into GPRs and then the parameter save area.
4480 // Unnamed arguments for vararg functions always go to GPRs and
4481 // then the parameter save area. For now, put all arguments to vararg
4482 // routines always in both locations (FPR *and* GPR or stack slot).
4483 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4485 // First load the argument into the next available FPR.
4486 if (FPR_idx != NumFPRs)
4487 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4489 // Next, load the argument into GPR or stack slot if needed.
4490 if (!NeedGPROrStack)
4492 else if (GPR_idx != NumGPRs) {
4493 // In the non-vararg case, this can only ever happen in the
4494 // presence of f32 array types, since otherwise we never run
4495 // out of FPRs before running out of GPRs.
4498 // Double values are always passed in a single GPR.
4499 if (Arg.getValueType() != MVT::f32) {
4500 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4502 // Non-array float values are extended and passed in a GPR.
4503 } else if (!Flags.isInConsecutiveRegs()) {
4504 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4505 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4507 // If we have an array of floats, we collect every odd element
4508 // together with its predecessor into one GPR.
4509 } else if (ArgOffset % PtrByteSize != 0) {
4511 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4512 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4513 if (!isLittleEndian)
4515 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4517 // The final element, if even, goes into the first half of a GPR.
4518 } else if (Flags.isInConsecutiveRegsLast()) {
4519 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4520 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4521 if (!isLittleEndian)
4522 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4523 DAG.getConstant(32, MVT::i32));
4525 // Non-final even elements are skipped; they will be handled
4526 // together the with subsequent argument on the next go-around.
4530 if (ArgVal.getNode())
4531 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4533 // Single-precision floating-point values are mapped to the
4534 // second (rightmost) word of the stack doubleword.
4535 if (Arg.getValueType() == MVT::f32 &&
4536 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4537 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4538 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4541 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4542 true, isTailCall, false, MemOpChains,
4543 TailCallArguments, dl);
4545 // When passing an array of floats, the array occupies consecutive
4546 // space in the argument area; only round up to the next doubleword
4547 // at the end of the array. Otherwise, each float takes 8 bytes.
4548 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4549 Flags.isInConsecutiveRegs()) ? 4 : 8;
4550 if (Flags.isInConsecutiveRegsLast())
4551 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4560 // These can be scalar arguments or elements of a vector array type
4561 // passed directly. The latter are used to implement ELFv2 homogenous
4562 // vector aggregates.
4564 // For a varargs call, named arguments go into VRs or on the stack as
4565 // usual; unnamed arguments always go to the stack or the corresponding
4566 // GPRs when within range. For now, we always put the value in both
4567 // locations (or even all three).
4569 // We could elide this store in the case where the object fits
4570 // entirely in R registers. Maybe later.
4571 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4572 MachinePointerInfo(), false, false, 0);
4573 MemOpChains.push_back(Store);
4574 if (VR_idx != NumVRs) {
4575 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4576 MachinePointerInfo(),
4577 false, false, false, 0);
4578 MemOpChains.push_back(Load.getValue(1));
4580 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4581 Arg.getSimpleValueType() == MVT::v2i64) ?
4582 VSRH[VR_idx] : VR[VR_idx];
4585 RegsToPass.push_back(std::make_pair(VReg, Load));
4588 for (unsigned i=0; i<16; i+=PtrByteSize) {
4589 if (GPR_idx == NumGPRs)
4591 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4592 DAG.getConstant(i, PtrVT));
4593 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4594 false, false, false, 0);
4595 MemOpChains.push_back(Load.getValue(1));
4596 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4601 // Non-varargs Altivec params go into VRs or on the stack.
4602 if (VR_idx != NumVRs) {
4603 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4604 Arg.getSimpleValueType() == MVT::v2i64) ?
4605 VSRH[VR_idx] : VR[VR_idx];
4608 RegsToPass.push_back(std::make_pair(VReg, Arg));
4610 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4611 true, isTailCall, true, MemOpChains,
4612 TailCallArguments, dl);
4619 assert(NumBytesActuallyUsed == ArgOffset);
4620 (void)NumBytesActuallyUsed;
4622 if (!MemOpChains.empty())
4623 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4625 // Check if this is an indirect call (MTCTR/BCTRL).
4626 // See PrepareCall() for more information about calls through function
4627 // pointers in the 64-bit SVR4 ABI.
4629 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4630 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4631 // Load r2 into a virtual register and store it to the TOC save area.
4632 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4633 // TOC save area offset.
4634 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4635 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4636 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4637 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4639 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4640 // This does not mean the MTCTR instruction must use R12; it's easier
4641 // to model this as an extra parameter, so do that.
4643 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4646 // Build a sequence of copy-to-reg nodes chained together with token chain
4647 // and flag operands which copy the outgoing args into the appropriate regs.
4649 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4650 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4651 RegsToPass[i].second, InFlag);
4652 InFlag = Chain.getValue(1);
4656 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4657 FPOp, true, TailCallArguments);
4659 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4660 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4665 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4666 CallingConv::ID CallConv, bool isVarArg,
4668 const SmallVectorImpl<ISD::OutputArg> &Outs,
4669 const SmallVectorImpl<SDValue> &OutVals,
4670 const SmallVectorImpl<ISD::InputArg> &Ins,
4671 SDLoc dl, SelectionDAG &DAG,
4672 SmallVectorImpl<SDValue> &InVals) const {
4674 unsigned NumOps = Outs.size();
4676 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4677 bool isPPC64 = PtrVT == MVT::i64;
4678 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4680 MachineFunction &MF = DAG.getMachineFunction();
4682 // Mark this function as potentially containing a function that contains a
4683 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4684 // and restoring the callers stack pointer in this functions epilog. This is
4685 // done because by tail calling the called function might overwrite the value
4686 // in this function's (MF) stack pointer stack slot 0(SP).
4687 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4688 CallConv == CallingConv::Fast)
4689 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4691 // Count how many bytes are to be pushed on the stack, including the linkage
4692 // area, and parameter passing area. We start with 24/48 bytes, which is
4693 // prereserved space for [SP][CR][LR][3 x unused].
4694 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4696 unsigned NumBytes = LinkageSize;
4698 // Add up all the space actually used.
4699 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4700 // they all go in registers, but we must reserve stack space for them for
4701 // possible use by the caller. In varargs or 64-bit calls, parameters are
4702 // assigned stack space in order, with padding so Altivec parameters are
4704 unsigned nAltivecParamsAtEnd = 0;
4705 for (unsigned i = 0; i != NumOps; ++i) {
4706 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4707 EVT ArgVT = Outs[i].VT;
4708 // Varargs Altivec parameters are padded to a 16 byte boundary.
4709 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4710 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4711 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4712 if (!isVarArg && !isPPC64) {
4713 // Non-varargs Altivec parameters go after all the non-Altivec
4714 // parameters; handle those later so we know how much padding we need.
4715 nAltivecParamsAtEnd++;
4718 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4719 NumBytes = ((NumBytes+15)/16)*16;
4721 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4724 // Allow for Altivec parameters at the end, if needed.
4725 if (nAltivecParamsAtEnd) {
4726 NumBytes = ((NumBytes+15)/16)*16;
4727 NumBytes += 16*nAltivecParamsAtEnd;
4730 // The prolog code of the callee may store up to 8 GPR argument registers to
4731 // the stack, allowing va_start to index over them in memory if its varargs.
4732 // Because we cannot tell if this is needed on the caller side, we have to
4733 // conservatively assume that it is needed. As such, make sure we have at
4734 // least enough stack space for the caller to store the 8 GPRs.
4735 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4737 // Tail call needs the stack to be aligned.
4738 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4739 CallConv == CallingConv::Fast)
4740 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4742 // Calculate by how many bytes the stack has to be adjusted in case of tail
4743 // call optimization.
4744 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4746 // To protect arguments on the stack from being clobbered in a tail call,
4747 // force all the loads to happen before doing any other lowering.
4749 Chain = DAG.getStackArgumentTokenFactor(Chain);
4751 // Adjust the stack pointer for the new arguments...
4752 // These operations are automatically eliminated by the prolog/epilog pass
4753 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4755 SDValue CallSeqStart = Chain;
4757 // Load the return address and frame pointer so it can be move somewhere else
4760 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4763 // Set up a copy of the stack pointer for use loading and storing any
4764 // arguments that may not fit in the registers available for argument
4768 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4770 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4772 // Figure out which arguments are going to go in registers, and which in
4773 // memory. Also, if this is a vararg function, floating point operations
4774 // must be stored to our stack, and loaded into integer regs as well, if
4775 // any integer regs are available for argument passing.
4776 unsigned ArgOffset = LinkageSize;
4777 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4779 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4780 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4781 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4783 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4784 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4785 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4787 static const MCPhysReg *FPR = GetFPR();
4789 static const MCPhysReg VR[] = {
4790 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4791 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4793 const unsigned NumGPRs = array_lengthof(GPR_32);
4794 const unsigned NumFPRs = 13;
4795 const unsigned NumVRs = array_lengthof(VR);
4797 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4799 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4800 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4802 SmallVector<SDValue, 8> MemOpChains;
4803 for (unsigned i = 0; i != NumOps; ++i) {
4804 SDValue Arg = OutVals[i];
4805 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4807 // PtrOff will be used to store the current argument to the stack if a
4808 // register cannot be found for it.
4811 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4813 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4815 // On PPC64, promote integers to 64-bit values.
4816 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4817 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4818 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4819 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4822 // FIXME memcpy is used way more than necessary. Correctness first.
4823 // Note: "by value" is code for passing a structure by value, not
4825 if (Flags.isByVal()) {
4826 unsigned Size = Flags.getByValSize();
4827 // Very small objects are passed right-justified. Everything else is
4828 // passed left-justified.
4829 if (Size==1 || Size==2) {
4830 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4831 if (GPR_idx != NumGPRs) {
4832 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4833 MachinePointerInfo(), VT,
4834 false, false, false, 0);
4835 MemOpChains.push_back(Load.getValue(1));
4836 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4838 ArgOffset += PtrByteSize;
4840 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4841 PtrOff.getValueType());
4842 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4843 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4846 ArgOffset += PtrByteSize;
4850 // Copy entire object into memory. There are cases where gcc-generated
4851 // code assumes it is there, even if it could be put entirely into
4852 // registers. (This is not what the doc says.)
4853 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4857 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4858 // copy the pieces of the object that fit into registers from the
4859 // parameter save area.
4860 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4861 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4862 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4863 if (GPR_idx != NumGPRs) {
4864 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4865 MachinePointerInfo(),
4866 false, false, false, 0);
4867 MemOpChains.push_back(Load.getValue(1));
4868 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4869 ArgOffset += PtrByteSize;
4871 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4878 switch (Arg.getSimpleValueType().SimpleTy) {
4879 default: llvm_unreachable("Unexpected ValueType for argument!");
4883 if (GPR_idx != NumGPRs) {
4884 if (Arg.getValueType() == MVT::i1)
4885 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4887 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4889 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4890 isPPC64, isTailCall, false, MemOpChains,
4891 TailCallArguments, dl);
4893 ArgOffset += PtrByteSize;
4897 if (FPR_idx != NumFPRs) {
4898 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4901 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4902 MachinePointerInfo(), false, false, 0);
4903 MemOpChains.push_back(Store);
4905 // Float varargs are always shadowed in available integer registers
4906 if (GPR_idx != NumGPRs) {
4907 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4908 MachinePointerInfo(), false, false,
4910 MemOpChains.push_back(Load.getValue(1));
4911 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4913 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4914 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4915 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4916 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4917 MachinePointerInfo(),
4918 false, false, false, 0);
4919 MemOpChains.push_back(Load.getValue(1));
4920 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4923 // If we have any FPRs remaining, we may also have GPRs remaining.
4924 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4926 if (GPR_idx != NumGPRs)
4928 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4929 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4933 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4934 isPPC64, isTailCall, false, MemOpChains,
4935 TailCallArguments, dl);
4939 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4946 // These go aligned on the stack, or in the corresponding R registers
4947 // when within range. The Darwin PPC ABI doc claims they also go in
4948 // V registers; in fact gcc does this only for arguments that are
4949 // prototyped, not for those that match the ... We do it for all
4950 // arguments, seems to work.
4951 while (ArgOffset % 16 !=0) {
4952 ArgOffset += PtrByteSize;
4953 if (GPR_idx != NumGPRs)
4956 // We could elide this store in the case where the object fits
4957 // entirely in R registers. Maybe later.
4958 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4959 DAG.getConstant(ArgOffset, PtrVT));
4960 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4961 MachinePointerInfo(), false, false, 0);
4962 MemOpChains.push_back(Store);
4963 if (VR_idx != NumVRs) {
4964 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4965 MachinePointerInfo(),
4966 false, false, false, 0);
4967 MemOpChains.push_back(Load.getValue(1));
4968 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4971 for (unsigned i=0; i<16; i+=PtrByteSize) {
4972 if (GPR_idx == NumGPRs)
4974 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4975 DAG.getConstant(i, PtrVT));
4976 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4977 false, false, false, 0);
4978 MemOpChains.push_back(Load.getValue(1));
4979 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4984 // Non-varargs Altivec params generally go in registers, but have
4985 // stack space allocated at the end.
4986 if (VR_idx != NumVRs) {
4987 // Doesn't have GPR space allocated.
4988 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4989 } else if (nAltivecParamsAtEnd==0) {
4990 // We are emitting Altivec params in order.
4991 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4992 isPPC64, isTailCall, true, MemOpChains,
4993 TailCallArguments, dl);
4999 // If all Altivec parameters fit in registers, as they usually do,
5000 // they get stack space following the non-Altivec parameters. We
5001 // don't track this here because nobody below needs it.
5002 // If there are more Altivec parameters than fit in registers emit
5004 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5006 // Offset is aligned; skip 1st 12 params which go in V registers.
5007 ArgOffset = ((ArgOffset+15)/16)*16;
5009 for (unsigned i = 0; i != NumOps; ++i) {
5010 SDValue Arg = OutVals[i];
5011 EVT ArgType = Outs[i].VT;
5012 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5013 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5016 // We are emitting Altivec params in order.
5017 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5018 isPPC64, isTailCall, true, MemOpChains,
5019 TailCallArguments, dl);
5026 if (!MemOpChains.empty())
5027 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5029 // On Darwin, R12 must contain the address of an indirect callee. This does
5030 // not mean the MTCTR instruction must use R12; it's easier to model this as
5031 // an extra parameter, so do that.
5033 !dyn_cast<GlobalAddressSDNode>(Callee) &&
5034 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
5035 !isBLACompatibleAddress(Callee, DAG))
5036 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5037 PPC::R12), Callee));
5039 // Build a sequence of copy-to-reg nodes chained together with token chain
5040 // and flag operands which copy the outgoing args into the appropriate regs.
5042 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5043 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5044 RegsToPass[i].second, InFlag);
5045 InFlag = Chain.getValue(1);
5049 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5050 FPOp, true, TailCallArguments);
5052 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5053 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5058 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5059 MachineFunction &MF, bool isVarArg,
5060 const SmallVectorImpl<ISD::OutputArg> &Outs,
5061 LLVMContext &Context) const {
5062 SmallVector<CCValAssign, 16> RVLocs;
5063 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5064 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5068 PPCTargetLowering::LowerReturn(SDValue Chain,
5069 CallingConv::ID CallConv, bool isVarArg,
5070 const SmallVectorImpl<ISD::OutputArg> &Outs,
5071 const SmallVectorImpl<SDValue> &OutVals,
5072 SDLoc dl, SelectionDAG &DAG) const {
5074 SmallVector<CCValAssign, 16> RVLocs;
5075 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5077 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5080 SmallVector<SDValue, 4> RetOps(1, Chain);
5082 // Copy the result values into the output registers.
5083 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5084 CCValAssign &VA = RVLocs[i];
5085 assert(VA.isRegLoc() && "Can only return in registers!");
5087 SDValue Arg = OutVals[i];
5089 switch (VA.getLocInfo()) {
5090 default: llvm_unreachable("Unknown loc info!");
5091 case CCValAssign::Full: break;
5092 case CCValAssign::AExt:
5093 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5095 case CCValAssign::ZExt:
5096 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5098 case CCValAssign::SExt:
5099 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5103 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5104 Flag = Chain.getValue(1);
5105 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5108 RetOps[0] = Chain; // Update chain.
5110 // Add the flag if we have it.
5112 RetOps.push_back(Flag);
5114 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5117 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5118 const PPCSubtarget &Subtarget) const {
5119 // When we pop the dynamic allocation we need to restore the SP link.
5122 // Get the corect type for pointers.
5123 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5125 // Construct the stack pointer operand.
5126 bool isPPC64 = Subtarget.isPPC64();
5127 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5128 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5130 // Get the operands for the STACKRESTORE.
5131 SDValue Chain = Op.getOperand(0);
5132 SDValue SaveSP = Op.getOperand(1);
5134 // Load the old link SP.
5135 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5136 MachinePointerInfo(),
5137 false, false, false, 0);
5139 // Restore the stack pointer.
5140 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5142 // Store the old link SP.
5143 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5150 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5151 MachineFunction &MF = DAG.getMachineFunction();
5152 bool isPPC64 = Subtarget.isPPC64();
5153 bool isDarwinABI = Subtarget.isDarwinABI();
5154 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5156 // Get current frame pointer save index. The users of this index will be
5157 // primarily DYNALLOC instructions.
5158 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5159 int RASI = FI->getReturnAddrSaveIndex();
5161 // If the frame pointer save index hasn't been defined yet.
5163 // Find out what the fix offset of the frame pointer save area.
5164 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5165 // Allocate the frame index for frame pointer save area.
5166 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
5168 FI->setReturnAddrSaveIndex(RASI);
5170 return DAG.getFrameIndex(RASI, PtrVT);
5174 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5175 MachineFunction &MF = DAG.getMachineFunction();
5176 bool isPPC64 = Subtarget.isPPC64();
5177 bool isDarwinABI = Subtarget.isDarwinABI();
5178 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5180 // Get current frame pointer save index. The users of this index will be
5181 // primarily DYNALLOC instructions.
5182 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5183 int FPSI = FI->getFramePointerSaveIndex();
5185 // If the frame pointer save index hasn't been defined yet.
5187 // Find out what the fix offset of the frame pointer save area.
5188 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5191 // Allocate the frame index for frame pointer save area.
5192 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5194 FI->setFramePointerSaveIndex(FPSI);
5196 return DAG.getFrameIndex(FPSI, PtrVT);
5199 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5201 const PPCSubtarget &Subtarget) const {
5203 SDValue Chain = Op.getOperand(0);
5204 SDValue Size = Op.getOperand(1);
5207 // Get the corect type for pointers.
5208 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5210 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5211 DAG.getConstant(0, PtrVT), Size);
5212 // Construct a node for the frame pointer save index.
5213 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5214 // Build a DYNALLOC node.
5215 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5216 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5217 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5220 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5221 SelectionDAG &DAG) const {
5223 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5224 DAG.getVTList(MVT::i32, MVT::Other),
5225 Op.getOperand(0), Op.getOperand(1));
5228 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5229 SelectionDAG &DAG) const {
5231 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5232 Op.getOperand(0), Op.getOperand(1));
5235 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5236 assert(Op.getValueType() == MVT::i1 &&
5237 "Custom lowering only for i1 loads");
5239 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5242 LoadSDNode *LD = cast<LoadSDNode>(Op);
5244 SDValue Chain = LD->getChain();
5245 SDValue BasePtr = LD->getBasePtr();
5246 MachineMemOperand *MMO = LD->getMemOperand();
5248 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5249 BasePtr, MVT::i8, MMO);
5250 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5252 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5253 return DAG.getMergeValues(Ops, dl);
5256 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5257 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5258 "Custom lowering only for i1 stores");
5260 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5263 StoreSDNode *ST = cast<StoreSDNode>(Op);
5265 SDValue Chain = ST->getChain();
5266 SDValue BasePtr = ST->getBasePtr();
5267 SDValue Value = ST->getValue();
5268 MachineMemOperand *MMO = ST->getMemOperand();
5270 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5271 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5274 // FIXME: Remove this once the ANDI glue bug is fixed:
5275 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5276 assert(Op.getValueType() == MVT::i1 &&
5277 "Custom lowering only for i1 results");
5280 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5284 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5286 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5287 // Not FP? Not a fsel.
5288 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5289 !Op.getOperand(2).getValueType().isFloatingPoint())
5292 // We might be able to do better than this under some circumstances, but in
5293 // general, fsel-based lowering of select is a finite-math-only optimization.
5294 // For more information, see section F.3 of the 2.06 ISA specification.
5295 if (!DAG.getTarget().Options.NoInfsFPMath ||
5296 !DAG.getTarget().Options.NoNaNsFPMath)
5299 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5301 EVT ResVT = Op.getValueType();
5302 EVT CmpVT = Op.getOperand(0).getValueType();
5303 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5304 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5307 // If the RHS of the comparison is a 0.0, we don't need to do the
5308 // subtraction at all.
5310 if (isFloatingPointZero(RHS))
5312 default: break; // SETUO etc aren't handled by fsel.
5316 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5317 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5318 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5319 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5320 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5321 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5322 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5325 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5328 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5329 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5330 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5333 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5336 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5337 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5338 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5339 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5344 default: break; // SETUO etc aren't handled by fsel.
5348 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5349 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5350 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5351 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5352 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5353 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5354 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5355 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5358 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5359 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5360 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5361 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5364 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5365 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5366 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5367 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5370 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5371 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5372 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5373 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5376 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5377 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5378 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5379 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5384 // FIXME: Split this code up when LegalizeDAGTypes lands.
5385 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5387 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5388 SDValue Src = Op.getOperand(0);
5389 if (Src.getValueType() == MVT::f32)
5390 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5393 switch (Op.getSimpleValueType().SimpleTy) {
5394 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5396 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5397 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5402 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5403 "i64 FP_TO_UINT is supported only with FPCVT");
5404 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5410 // Convert the FP value to an int value through memory.
5411 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5412 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5413 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5414 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5415 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5417 // Emit a store to the stack slot.
5420 MachineFunction &MF = DAG.getMachineFunction();
5421 MachineMemOperand *MMO =
5422 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5423 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5424 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5425 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5427 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5428 MPI, false, false, 0);
5430 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5432 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5433 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5434 DAG.getConstant(4, FIPtr.getValueType()));
5435 MPI = MachinePointerInfo();
5438 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5439 false, false, false, 0);
5442 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5443 SelectionDAG &DAG) const {
5445 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5446 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5449 if (Op.getOperand(0).getValueType() == MVT::i1)
5450 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5451 DAG.getConstantFP(1.0, Op.getValueType()),
5452 DAG.getConstantFP(0.0, Op.getValueType()));
5454 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5455 "UINT_TO_FP is supported only with FPCVT");
5457 // If we have FCFIDS, then use it when converting to single-precision.
5458 // Otherwise, convert to double-precision and then round.
5459 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5460 (Op.getOpcode() == ISD::UINT_TO_FP ?
5461 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5462 (Op.getOpcode() == ISD::UINT_TO_FP ?
5463 PPCISD::FCFIDU : PPCISD::FCFID);
5464 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5465 MVT::f32 : MVT::f64;
5467 if (Op.getOperand(0).getValueType() == MVT::i64) {
5468 SDValue SINT = Op.getOperand(0);
5469 // When converting to single-precision, we actually need to convert
5470 // to double-precision first and then round to single-precision.
5471 // To avoid double-rounding effects during that operation, we have
5472 // to prepare the input operand. Bits that might be truncated when
5473 // converting to double-precision are replaced by a bit that won't
5474 // be lost at this stage, but is below the single-precision rounding
5477 // However, if -enable-unsafe-fp-math is in effect, accept double
5478 // rounding to avoid the extra overhead.
5479 if (Op.getValueType() == MVT::f32 &&
5480 !Subtarget.hasFPCVT() &&
5481 !DAG.getTarget().Options.UnsafeFPMath) {
5483 // Twiddle input to make sure the low 11 bits are zero. (If this
5484 // is the case, we are guaranteed the value will fit into the 53 bit
5485 // mantissa of an IEEE double-precision value without rounding.)
5486 // If any of those low 11 bits were not zero originally, make sure
5487 // bit 12 (value 2048) is set instead, so that the final rounding
5488 // to single-precision gets the correct result.
5489 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5490 SINT, DAG.getConstant(2047, MVT::i64));
5491 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5492 Round, DAG.getConstant(2047, MVT::i64));
5493 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5494 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5495 Round, DAG.getConstant(-2048, MVT::i64));
5497 // However, we cannot use that value unconditionally: if the magnitude
5498 // of the input value is small, the bit-twiddling we did above might
5499 // end up visibly changing the output. Fortunately, in that case, we
5500 // don't need to twiddle bits since the original input will convert
5501 // exactly to double-precision floating-point already. Therefore,
5502 // construct a conditional to use the original value if the top 11
5503 // bits are all sign-bit copies, and use the rounded value computed
5505 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5506 SINT, DAG.getConstant(53, MVT::i32));
5507 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5508 Cond, DAG.getConstant(1, MVT::i64));
5509 Cond = DAG.getSetCC(dl, MVT::i32,
5510 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5512 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5515 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5516 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5518 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5519 FP = DAG.getNode(ISD::FP_ROUND, dl,
5520 MVT::f32, FP, DAG.getIntPtrConstant(0));
5524 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5525 "Unhandled INT_TO_FP type in custom expander!");
5526 // Since we only generate this in 64-bit mode, we can take advantage of
5527 // 64-bit registers. In particular, sign extend the input value into the
5528 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5529 // then lfd it and fcfid it.
5530 MachineFunction &MF = DAG.getMachineFunction();
5531 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5532 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5535 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5536 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5537 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5539 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5540 MachinePointerInfo::getFixedStack(FrameIdx),
5543 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5544 "Expected an i32 store");
5545 MachineMemOperand *MMO =
5546 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5547 MachineMemOperand::MOLoad, 4, 4);
5548 SDValue Ops[] = { Store, FIdx };
5549 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5550 PPCISD::LFIWZX : PPCISD::LFIWAX,
5551 dl, DAG.getVTList(MVT::f64, MVT::Other),
5552 Ops, MVT::i32, MMO);
5554 assert(Subtarget.isPPC64() &&
5555 "i32->FP without LFIWAX supported only on PPC64");
5557 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5558 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5560 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5563 // STD the extended value into the stack slot.
5564 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5565 MachinePointerInfo::getFixedStack(FrameIdx),
5568 // Load the value as a double.
5569 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5570 MachinePointerInfo::getFixedStack(FrameIdx),
5571 false, false, false, 0);
5574 // FCFID it and return it.
5575 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5576 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5577 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5581 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5582 SelectionDAG &DAG) const {
5585 The rounding mode is in bits 30:31 of FPSR, and has the following
5592 FLT_ROUNDS, on the other hand, expects the following:
5599 To perform the conversion, we do:
5600 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5603 MachineFunction &MF = DAG.getMachineFunction();
5604 EVT VT = Op.getValueType();
5605 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5607 // Save FP Control Word to register
5609 MVT::f64, // return register
5610 MVT::Glue // unused in this context
5612 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5614 // Save FP register to stack slot
5615 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5616 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5617 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5618 StackSlot, MachinePointerInfo(), false, false,0);
5620 // Load FP Control Word from low 32 bits of stack slot.
5621 SDValue Four = DAG.getConstant(4, PtrVT);
5622 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5623 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5624 false, false, false, 0);
5626 // Transform as necessary
5628 DAG.getNode(ISD::AND, dl, MVT::i32,
5629 CWD, DAG.getConstant(3, MVT::i32));
5631 DAG.getNode(ISD::SRL, dl, MVT::i32,
5632 DAG.getNode(ISD::AND, dl, MVT::i32,
5633 DAG.getNode(ISD::XOR, dl, MVT::i32,
5634 CWD, DAG.getConstant(3, MVT::i32)),
5635 DAG.getConstant(3, MVT::i32)),
5636 DAG.getConstant(1, MVT::i32));
5639 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5641 return DAG.getNode((VT.getSizeInBits() < 16 ?
5642 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5645 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5646 EVT VT = Op.getValueType();
5647 unsigned BitWidth = VT.getSizeInBits();
5649 assert(Op.getNumOperands() == 3 &&
5650 VT == Op.getOperand(1).getValueType() &&
5653 // Expand into a bunch of logical ops. Note that these ops
5654 // depend on the PPC behavior for oversized shift amounts.
5655 SDValue Lo = Op.getOperand(0);
5656 SDValue Hi = Op.getOperand(1);
5657 SDValue Amt = Op.getOperand(2);
5658 EVT AmtVT = Amt.getValueType();
5660 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5661 DAG.getConstant(BitWidth, AmtVT), Amt);
5662 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5663 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5664 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5665 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5666 DAG.getConstant(-BitWidth, AmtVT));
5667 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5668 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5669 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5670 SDValue OutOps[] = { OutLo, OutHi };
5671 return DAG.getMergeValues(OutOps, dl);
5674 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5675 EVT VT = Op.getValueType();
5677 unsigned BitWidth = VT.getSizeInBits();
5678 assert(Op.getNumOperands() == 3 &&
5679 VT == Op.getOperand(1).getValueType() &&
5682 // Expand into a bunch of logical ops. Note that these ops
5683 // depend on the PPC behavior for oversized shift amounts.
5684 SDValue Lo = Op.getOperand(0);
5685 SDValue Hi = Op.getOperand(1);
5686 SDValue Amt = Op.getOperand(2);
5687 EVT AmtVT = Amt.getValueType();
5689 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5690 DAG.getConstant(BitWidth, AmtVT), Amt);
5691 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5692 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5693 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5694 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5695 DAG.getConstant(-BitWidth, AmtVT));
5696 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5697 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5698 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5699 SDValue OutOps[] = { OutLo, OutHi };
5700 return DAG.getMergeValues(OutOps, dl);
5703 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5705 EVT VT = Op.getValueType();
5706 unsigned BitWidth = VT.getSizeInBits();
5707 assert(Op.getNumOperands() == 3 &&
5708 VT == Op.getOperand(1).getValueType() &&
5711 // Expand into a bunch of logical ops, followed by a select_cc.
5712 SDValue Lo = Op.getOperand(0);
5713 SDValue Hi = Op.getOperand(1);
5714 SDValue Amt = Op.getOperand(2);
5715 EVT AmtVT = Amt.getValueType();
5717 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5718 DAG.getConstant(BitWidth, AmtVT), Amt);
5719 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5720 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5721 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5722 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5723 DAG.getConstant(-BitWidth, AmtVT));
5724 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5725 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5726 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5727 Tmp4, Tmp6, ISD::SETLE);
5728 SDValue OutOps[] = { OutLo, OutHi };
5729 return DAG.getMergeValues(OutOps, dl);
5732 //===----------------------------------------------------------------------===//
5733 // Vector related lowering.
5736 /// BuildSplatI - Build a canonical splati of Val with an element size of
5737 /// SplatSize. Cast the result to VT.
5738 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5739 SelectionDAG &DAG, SDLoc dl) {
5740 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5742 static const EVT VTys[] = { // canonical VT to use for each size.
5743 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5746 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5748 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5752 EVT CanonicalVT = VTys[SplatSize-1];
5754 // Build a canonical splat for this value.
5755 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5756 SmallVector<SDValue, 8> Ops;
5757 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5758 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5759 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5762 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5763 /// specified intrinsic ID.
5764 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5765 SelectionDAG &DAG, SDLoc dl,
5766 EVT DestVT = MVT::Other) {
5767 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5768 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5769 DAG.getConstant(IID, MVT::i32), Op);
5772 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5773 /// specified intrinsic ID.
5774 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5775 SelectionDAG &DAG, SDLoc dl,
5776 EVT DestVT = MVT::Other) {
5777 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5778 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5779 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5782 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5783 /// specified intrinsic ID.
5784 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5785 SDValue Op2, SelectionDAG &DAG,
5786 SDLoc dl, EVT DestVT = MVT::Other) {
5787 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5788 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5789 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5793 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5794 /// amount. The result has the specified value type.
5795 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5796 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5797 // Force LHS/RHS to be the right type.
5798 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5799 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5802 for (unsigned i = 0; i != 16; ++i)
5804 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5805 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5808 // If this is a case we can't handle, return null and let the default
5809 // expansion code take care of it. If we CAN select this case, and if it
5810 // selects to a single instruction, return Op. Otherwise, if we can codegen
5811 // this case more efficiently than a constant pool load, lower it to the
5812 // sequence of ops that should be used.
5813 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5814 SelectionDAG &DAG) const {
5816 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5817 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5819 // Check if this is a splat of a constant value.
5820 APInt APSplatBits, APSplatUndef;
5821 unsigned SplatBitSize;
5823 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5824 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5827 unsigned SplatBits = APSplatBits.getZExtValue();
5828 unsigned SplatUndef = APSplatUndef.getZExtValue();
5829 unsigned SplatSize = SplatBitSize / 8;
5831 // First, handle single instruction cases.
5834 if (SplatBits == 0) {
5835 // Canonicalize all zero vectors to be v4i32.
5836 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5837 SDValue Z = DAG.getConstant(0, MVT::i32);
5838 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5839 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5844 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5845 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5847 if (SextVal >= -16 && SextVal <= 15)
5848 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5851 // Two instruction sequences.
5853 // If this value is in the range [-32,30] and is even, use:
5854 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5855 // If this value is in the range [17,31] and is odd, use:
5856 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5857 // If this value is in the range [-31,-17] and is odd, use:
5858 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5859 // Note the last two are three-instruction sequences.
5860 if (SextVal >= -32 && SextVal <= 31) {
5861 // To avoid having these optimizations undone by constant folding,
5862 // we convert to a pseudo that will be expanded later into one of
5864 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5865 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5866 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5867 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5868 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5869 if (VT == Op.getValueType())
5872 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5875 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5876 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5878 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5879 // Make -1 and vspltisw -1:
5880 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5882 // Make the VSLW intrinsic, computing 0x8000_0000.
5883 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5886 // xor by OnesV to invert it.
5887 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5888 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5891 // The remaining cases assume either big endian element order or
5892 // a splat-size that equates to the element size of the vector
5893 // to be built. An example that doesn't work for little endian is
5894 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5895 // and a vector element size of 16 bits. The code below will
5896 // produce the vector in big endian element order, which for little
5897 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5899 // For now, just avoid these optimizations in that case.
5900 // FIXME: Develop correct optimizations for LE with mismatched
5901 // splat and element sizes.
5903 if (Subtarget.isLittleEndian() &&
5904 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5907 // Check to see if this is a wide variety of vsplti*, binop self cases.
5908 static const signed char SplatCsts[] = {
5909 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5910 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5913 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5914 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5915 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5916 int i = SplatCsts[idx];
5918 // Figure out what shift amount will be used by altivec if shifted by i in
5920 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5922 // vsplti + shl self.
5923 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5924 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5925 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5926 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5927 Intrinsic::ppc_altivec_vslw
5929 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5930 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5933 // vsplti + srl self.
5934 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5935 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5936 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5937 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5938 Intrinsic::ppc_altivec_vsrw
5940 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5941 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5944 // vsplti + sra self.
5945 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5946 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5947 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5948 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5949 Intrinsic::ppc_altivec_vsraw
5951 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5952 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5955 // vsplti + rol self.
5956 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5957 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5958 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5959 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5960 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5961 Intrinsic::ppc_altivec_vrlw
5963 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5964 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5967 // t = vsplti c, result = vsldoi t, t, 1
5968 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5969 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5970 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5972 // t = vsplti c, result = vsldoi t, t, 2
5973 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5974 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5975 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5977 // t = vsplti c, result = vsldoi t, t, 3
5978 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5979 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5980 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5987 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5988 /// the specified operations to build the shuffle.
5989 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5990 SDValue RHS, SelectionDAG &DAG,
5992 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5993 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5994 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5997 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6009 if (OpNum == OP_COPY) {
6010 if (LHSID == (1*9+2)*9+3) return LHS;
6011 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6015 SDValue OpLHS, OpRHS;
6016 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6017 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6021 default: llvm_unreachable("Unknown i32 permute!");
6023 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6024 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6025 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6026 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6029 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6030 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6031 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6032 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6035 for (unsigned i = 0; i != 16; ++i)
6036 ShufIdxs[i] = (i&3)+0;
6039 for (unsigned i = 0; i != 16; ++i)
6040 ShufIdxs[i] = (i&3)+4;
6043 for (unsigned i = 0; i != 16; ++i)
6044 ShufIdxs[i] = (i&3)+8;
6047 for (unsigned i = 0; i != 16; ++i)
6048 ShufIdxs[i] = (i&3)+12;
6051 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6053 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6055 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6057 EVT VT = OpLHS.getValueType();
6058 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6059 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6060 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6061 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6064 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6065 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6066 /// return the code it can be lowered into. Worst case, it can always be
6067 /// lowered into a vperm.
6068 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6069 SelectionDAG &DAG) const {
6071 SDValue V1 = Op.getOperand(0);
6072 SDValue V2 = Op.getOperand(1);
6073 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6074 EVT VT = Op.getValueType();
6075 bool isLittleEndian = Subtarget.isLittleEndian();
6077 // Cases that are handled by instructions that take permute immediates
6078 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6079 // selected by the instruction selector.
6080 if (V2.getOpcode() == ISD::UNDEF) {
6081 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6082 PPC::isSplatShuffleMask(SVOp, 2) ||
6083 PPC::isSplatShuffleMask(SVOp, 4) ||
6084 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6085 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6086 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6087 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6088 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6089 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6090 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6091 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6092 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6097 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6098 // and produce a fixed permutation. If any of these match, do not lower to
6100 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6101 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6102 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6103 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6104 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6105 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6106 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6107 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6108 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6109 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6112 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6113 // perfect shuffle table to emit an optimal matching sequence.
6114 ArrayRef<int> PermMask = SVOp->getMask();
6116 unsigned PFIndexes[4];
6117 bool isFourElementShuffle = true;
6118 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6119 unsigned EltNo = 8; // Start out undef.
6120 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6121 if (PermMask[i*4+j] < 0)
6122 continue; // Undef, ignore it.
6124 unsigned ByteSource = PermMask[i*4+j];
6125 if ((ByteSource & 3) != j) {
6126 isFourElementShuffle = false;
6131 EltNo = ByteSource/4;
6132 } else if (EltNo != ByteSource/4) {
6133 isFourElementShuffle = false;
6137 PFIndexes[i] = EltNo;
6140 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6141 // perfect shuffle vector to determine if it is cost effective to do this as
6142 // discrete instructions, or whether we should use a vperm.
6143 // For now, we skip this for little endian until such time as we have a
6144 // little-endian perfect shuffle table.
6145 if (isFourElementShuffle && !isLittleEndian) {
6146 // Compute the index in the perfect shuffle table.
6147 unsigned PFTableIndex =
6148 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6150 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6151 unsigned Cost = (PFEntry >> 30);
6153 // Determining when to avoid vperm is tricky. Many things affect the cost
6154 // of vperm, particularly how many times the perm mask needs to be computed.
6155 // For example, if the perm mask can be hoisted out of a loop or is already
6156 // used (perhaps because there are multiple permutes with the same shuffle
6157 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6158 // the loop requires an extra register.
6160 // As a compromise, we only emit discrete instructions if the shuffle can be
6161 // generated in 3 or fewer operations. When we have loop information
6162 // available, if this block is within a loop, we should avoid using vperm
6163 // for 3-operation perms and use a constant pool load instead.
6165 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6168 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6169 // vector that will get spilled to the constant pool.
6170 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6172 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6173 // that it is in input element units, not in bytes. Convert now.
6175 // For little endian, the order of the input vectors is reversed, and
6176 // the permutation mask is complemented with respect to 31. This is
6177 // necessary to produce proper semantics with the big-endian-biased vperm
6179 EVT EltVT = V1.getValueType().getVectorElementType();
6180 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6182 SmallVector<SDValue, 16> ResultMask;
6183 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6184 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6186 for (unsigned j = 0; j != BytesPerElement; ++j)
6188 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6191 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6195 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6198 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6201 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6205 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6206 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6207 /// information about the intrinsic.
6208 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6210 unsigned IntrinsicID =
6211 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6214 switch (IntrinsicID) {
6215 default: return false;
6216 // Comparison predicates.
6217 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6218 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6219 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6220 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6221 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6222 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6223 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6224 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6225 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6226 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6227 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6228 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6229 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6231 // Normal Comparisons.
6232 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6233 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6234 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6235 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6236 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6237 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6238 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6239 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6240 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6241 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6242 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6243 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6244 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6249 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6250 /// lower, do it, otherwise return null.
6251 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6252 SelectionDAG &DAG) const {
6253 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6254 // opcode number of the comparison.
6258 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6259 return SDValue(); // Don't custom lower most intrinsics.
6261 // If this is a non-dot comparison, make the VCMP node and we are done.
6263 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6264 Op.getOperand(1), Op.getOperand(2),
6265 DAG.getConstant(CompareOpc, MVT::i32));
6266 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6269 // Create the PPCISD altivec 'dot' comparison node.
6271 Op.getOperand(2), // LHS
6272 Op.getOperand(3), // RHS
6273 DAG.getConstant(CompareOpc, MVT::i32)
6275 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6276 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6278 // Now that we have the comparison, emit a copy from the CR to a GPR.
6279 // This is flagged to the above dot comparison.
6280 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6281 DAG.getRegister(PPC::CR6, MVT::i32),
6282 CompNode.getValue(1));
6284 // Unpack the result based on how the target uses it.
6285 unsigned BitNo; // Bit # of CR6.
6286 bool InvertBit; // Invert result?
6287 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6288 default: // Can't happen, don't crash on invalid number though.
6289 case 0: // Return the value of the EQ bit of CR6.
6290 BitNo = 0; InvertBit = false;
6292 case 1: // Return the inverted value of the EQ bit of CR6.
6293 BitNo = 0; InvertBit = true;
6295 case 2: // Return the value of the LT bit of CR6.
6296 BitNo = 2; InvertBit = false;
6298 case 3: // Return the inverted value of the LT bit of CR6.
6299 BitNo = 2; InvertBit = true;
6303 // Shift the bit into the low position.
6304 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6305 DAG.getConstant(8-(3-BitNo), MVT::i32));
6307 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6308 DAG.getConstant(1, MVT::i32));
6310 // If we are supposed to, toggle the bit.
6312 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6313 DAG.getConstant(1, MVT::i32));
6317 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6318 SelectionDAG &DAG) const {
6320 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6321 // instructions), but for smaller types, we need to first extend up to v2i32
6322 // before doing going farther.
6323 if (Op.getValueType() == MVT::v2i64) {
6324 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6325 if (ExtVT != MVT::v2i32) {
6326 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6327 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6328 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6329 ExtVT.getVectorElementType(), 4)));
6330 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6331 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6332 DAG.getValueType(MVT::v2i32));
6341 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6342 SelectionDAG &DAG) const {
6344 // Create a stack slot that is 16-byte aligned.
6345 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6346 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6347 EVT PtrVT = getPointerTy();
6348 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6350 // Store the input value into Value#0 of the stack slot.
6351 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6352 Op.getOperand(0), FIdx, MachinePointerInfo(),
6355 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6356 false, false, false, 0);
6359 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6361 if (Op.getValueType() == MVT::v4i32) {
6362 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6364 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6365 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6367 SDValue RHSSwap = // = vrlw RHS, 16
6368 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6370 // Shrinkify inputs to v8i16.
6371 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6372 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6373 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6375 // Low parts multiplied together, generating 32-bit results (we ignore the
6377 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6378 LHS, RHS, DAG, dl, MVT::v4i32);
6380 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6381 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6382 // Shift the high parts up 16 bits.
6383 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6385 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6386 } else if (Op.getValueType() == MVT::v8i16) {
6387 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6389 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6391 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6392 LHS, RHS, Zero, DAG, dl);
6393 } else if (Op.getValueType() == MVT::v16i8) {
6394 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6395 bool isLittleEndian = Subtarget.isLittleEndian();
6397 // Multiply the even 8-bit parts, producing 16-bit sums.
6398 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6399 LHS, RHS, DAG, dl, MVT::v8i16);
6400 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6402 // Multiply the odd 8-bit parts, producing 16-bit sums.
6403 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6404 LHS, RHS, DAG, dl, MVT::v8i16);
6405 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6407 // Merge the results together. Because vmuleub and vmuloub are
6408 // instructions with a big-endian bias, we must reverse the
6409 // element numbering and reverse the meaning of "odd" and "even"
6410 // when generating little endian code.
6412 for (unsigned i = 0; i != 8; ++i) {
6413 if (isLittleEndian) {
6415 Ops[i*2+1] = 2*i+16;
6418 Ops[i*2+1] = 2*i+1+16;
6422 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6424 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6426 llvm_unreachable("Unknown mul to lower!");
6430 /// LowerOperation - Provide custom lowering hooks for some operations.
6432 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6433 switch (Op.getOpcode()) {
6434 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6435 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6436 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6437 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6438 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6439 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6440 case ISD::SETCC: return LowerSETCC(Op, DAG);
6441 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6442 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6444 return LowerVASTART(Op, DAG, Subtarget);
6447 return LowerVAARG(Op, DAG, Subtarget);
6450 return LowerVACOPY(Op, DAG, Subtarget);
6452 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6453 case ISD::DYNAMIC_STACKALLOC:
6454 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6456 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6457 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6459 case ISD::LOAD: return LowerLOAD(Op, DAG);
6460 case ISD::STORE: return LowerSTORE(Op, DAG);
6461 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6462 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6463 case ISD::FP_TO_UINT:
6464 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6466 case ISD::UINT_TO_FP:
6467 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6468 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6470 // Lower 64-bit shifts.
6471 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6472 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6473 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6475 // Vector-related lowering.
6476 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6477 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6478 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6479 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6480 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6481 case ISD::MUL: return LowerMUL(Op, DAG);
6483 // For counter-based loop handling.
6484 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6486 // Frame & Return address.
6487 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6488 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6492 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6493 SmallVectorImpl<SDValue>&Results,
6494 SelectionDAG &DAG) const {
6495 const TargetMachine &TM = getTargetMachine();
6497 switch (N->getOpcode()) {
6499 llvm_unreachable("Do not know how to custom type legalize this operation!");
6500 case ISD::INTRINSIC_W_CHAIN: {
6501 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6502 Intrinsic::ppc_is_decremented_ctr_nonzero)
6505 assert(N->getValueType(0) == MVT::i1 &&
6506 "Unexpected result type for CTR decrement intrinsic");
6507 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6508 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6509 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6512 Results.push_back(NewInt);
6513 Results.push_back(NewInt.getValue(1));
6517 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6518 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6521 EVT VT = N->getValueType(0);
6523 if (VT == MVT::i64) {
6524 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6526 Results.push_back(NewNode);
6527 Results.push_back(NewNode.getValue(1));
6531 case ISD::FP_ROUND_INREG: {
6532 assert(N->getValueType(0) == MVT::ppcf128);
6533 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6534 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6535 MVT::f64, N->getOperand(0),
6536 DAG.getIntPtrConstant(0));
6537 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6538 MVT::f64, N->getOperand(0),
6539 DAG.getIntPtrConstant(1));
6541 // Add the two halves of the long double in round-to-zero mode.
6542 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6544 // We know the low half is about to be thrown away, so just use something
6546 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6550 case ISD::FP_TO_SINT:
6551 // LowerFP_TO_INT() can only handle f32 and f64.
6552 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6554 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6560 //===----------------------------------------------------------------------===//
6561 // Other Lowering Code
6562 //===----------------------------------------------------------------------===//
6564 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6565 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6566 Function *Func = Intrinsic::getDeclaration(M, Id);
6567 return Builder.CreateCall(Func);
6570 // The mappings for emitLeading/TrailingFence is taken from
6571 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6572 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6573 AtomicOrdering Ord, bool IsStore,
6574 bool IsLoad) const {
6575 if (Ord == SequentiallyConsistent)
6576 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6577 else if (isAtLeastRelease(Ord))
6578 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6583 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6584 AtomicOrdering Ord, bool IsStore,
6585 bool IsLoad) const {
6586 if (IsLoad && isAtLeastAcquire(Ord))
6587 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6588 // FIXME: this is too conservative, a dependent branch + isync is enough.
6589 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6590 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6591 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6597 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6598 bool is64bit, unsigned BinOpcode) const {
6599 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6600 const TargetInstrInfo *TII =
6601 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6603 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6604 MachineFunction *F = BB->getParent();
6605 MachineFunction::iterator It = BB;
6608 unsigned dest = MI->getOperand(0).getReg();
6609 unsigned ptrA = MI->getOperand(1).getReg();
6610 unsigned ptrB = MI->getOperand(2).getReg();
6611 unsigned incr = MI->getOperand(3).getReg();
6612 DebugLoc dl = MI->getDebugLoc();
6614 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6615 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6616 F->insert(It, loopMBB);
6617 F->insert(It, exitMBB);
6618 exitMBB->splice(exitMBB->begin(), BB,
6619 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6620 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6622 MachineRegisterInfo &RegInfo = F->getRegInfo();
6623 unsigned TmpReg = (!BinOpcode) ? incr :
6624 RegInfo.createVirtualRegister(
6625 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6626 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6630 // fallthrough --> loopMBB
6631 BB->addSuccessor(loopMBB);
6634 // l[wd]arx dest, ptr
6635 // add r0, dest, incr
6636 // st[wd]cx. r0, ptr
6638 // fallthrough --> exitMBB
6640 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6641 .addReg(ptrA).addReg(ptrB);
6643 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6644 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6645 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6646 BuildMI(BB, dl, TII->get(PPC::BCC))
6647 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6648 BB->addSuccessor(loopMBB);
6649 BB->addSuccessor(exitMBB);
6658 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6659 MachineBasicBlock *BB,
6660 bool is8bit, // operation
6661 unsigned BinOpcode) const {
6662 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6663 const TargetInstrInfo *TII =
6664 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6665 // In 64 bit mode we have to use 64 bits for addresses, even though the
6666 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6667 // registers without caring whether they're 32 or 64, but here we're
6668 // doing actual arithmetic on the addresses.
6669 bool is64bit = Subtarget.isPPC64();
6670 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6672 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6673 MachineFunction *F = BB->getParent();
6674 MachineFunction::iterator It = BB;
6677 unsigned dest = MI->getOperand(0).getReg();
6678 unsigned ptrA = MI->getOperand(1).getReg();
6679 unsigned ptrB = MI->getOperand(2).getReg();
6680 unsigned incr = MI->getOperand(3).getReg();
6681 DebugLoc dl = MI->getDebugLoc();
6683 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6684 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6685 F->insert(It, loopMBB);
6686 F->insert(It, exitMBB);
6687 exitMBB->splice(exitMBB->begin(), BB,
6688 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6689 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6691 MachineRegisterInfo &RegInfo = F->getRegInfo();
6692 const TargetRegisterClass *RC =
6693 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6694 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6695 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6696 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6697 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6698 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6699 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6700 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6701 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6702 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6703 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6704 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6705 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6707 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6711 // fallthrough --> loopMBB
6712 BB->addSuccessor(loopMBB);
6714 // The 4-byte load must be aligned, while a char or short may be
6715 // anywhere in the word. Hence all this nasty bookkeeping code.
6716 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6717 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6718 // xori shift, shift1, 24 [16]
6719 // rlwinm ptr, ptr1, 0, 0, 29
6720 // slw incr2, incr, shift
6721 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6722 // slw mask, mask2, shift
6724 // lwarx tmpDest, ptr
6725 // add tmp, tmpDest, incr2
6726 // andc tmp2, tmpDest, mask
6727 // and tmp3, tmp, mask
6728 // or tmp4, tmp3, tmp2
6731 // fallthrough --> exitMBB
6732 // srw dest, tmpDest, shift
6733 if (ptrA != ZeroReg) {
6734 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6735 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6736 .addReg(ptrA).addReg(ptrB);
6740 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6741 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6742 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6743 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6745 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6746 .addReg(Ptr1Reg).addImm(0).addImm(61);
6748 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6749 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6750 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6751 .addReg(incr).addReg(ShiftReg);
6753 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6755 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6756 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6758 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6759 .addReg(Mask2Reg).addReg(ShiftReg);
6762 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6763 .addReg(ZeroReg).addReg(PtrReg);
6765 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6766 .addReg(Incr2Reg).addReg(TmpDestReg);
6767 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6768 .addReg(TmpDestReg).addReg(MaskReg);
6769 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6770 .addReg(TmpReg).addReg(MaskReg);
6771 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6772 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6773 BuildMI(BB, dl, TII->get(PPC::STWCX))
6774 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6775 BuildMI(BB, dl, TII->get(PPC::BCC))
6776 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6777 BB->addSuccessor(loopMBB);
6778 BB->addSuccessor(exitMBB);
6783 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6788 llvm::MachineBasicBlock*
6789 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6790 MachineBasicBlock *MBB) const {
6791 DebugLoc DL = MI->getDebugLoc();
6792 const TargetInstrInfo *TII =
6793 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6795 MachineFunction *MF = MBB->getParent();
6796 MachineRegisterInfo &MRI = MF->getRegInfo();
6798 const BasicBlock *BB = MBB->getBasicBlock();
6799 MachineFunction::iterator I = MBB;
6803 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6804 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6806 unsigned DstReg = MI->getOperand(0).getReg();
6807 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6808 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6809 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6810 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6812 MVT PVT = getPointerTy();
6813 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6814 "Invalid Pointer Size!");
6815 // For v = setjmp(buf), we generate
6818 // SjLjSetup mainMBB
6824 // buf[LabelOffset] = LR
6828 // v = phi(main, restore)
6831 MachineBasicBlock *thisMBB = MBB;
6832 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6833 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6834 MF->insert(I, mainMBB);
6835 MF->insert(I, sinkMBB);
6837 MachineInstrBuilder MIB;
6839 // Transfer the remainder of BB and its successor edges to sinkMBB.
6840 sinkMBB->splice(sinkMBB->begin(), MBB,
6841 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6842 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6844 // Note that the structure of the jmp_buf used here is not compatible
6845 // with that used by libc, and is not designed to be. Specifically, it
6846 // stores only those 'reserved' registers that LLVM does not otherwise
6847 // understand how to spill. Also, by convention, by the time this
6848 // intrinsic is called, Clang has already stored the frame address in the
6849 // first slot of the buffer and stack address in the third. Following the
6850 // X86 target code, we'll store the jump address in the second slot. We also
6851 // need to save the TOC pointer (R2) to handle jumps between shared
6852 // libraries, and that will be stored in the fourth slot. The thread
6853 // identifier (R13) is not affected.
6856 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6857 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6858 const int64_t BPOffset = 4 * PVT.getStoreSize();
6860 // Prepare IP either in reg.
6861 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6862 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6863 unsigned BufReg = MI->getOperand(1).getReg();
6865 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6866 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6870 MIB.setMemRefs(MMOBegin, MMOEnd);
6873 // Naked functions never have a base pointer, and so we use r1. For all
6874 // other functions, this decision must be delayed until during PEI.
6876 if (MF->getFunction()->getAttributes().hasAttribute(
6877 AttributeSet::FunctionIndex, Attribute::Naked))
6878 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6880 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6882 MIB = BuildMI(*thisMBB, MI, DL,
6883 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6887 MIB.setMemRefs(MMOBegin, MMOEnd);
6890 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6891 const PPCRegisterInfo *TRI =
6892 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
6893 MIB.addRegMask(TRI->getNoPreservedMask());
6895 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6897 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6899 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6901 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6902 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6906 MIB = BuildMI(mainMBB, DL,
6907 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6910 if (Subtarget.isPPC64()) {
6911 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6913 .addImm(LabelOffset)
6916 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6918 .addImm(LabelOffset)
6922 MIB.setMemRefs(MMOBegin, MMOEnd);
6924 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6925 mainMBB->addSuccessor(sinkMBB);
6928 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6929 TII->get(PPC::PHI), DstReg)
6930 .addReg(mainDstReg).addMBB(mainMBB)
6931 .addReg(restoreDstReg).addMBB(thisMBB);
6933 MI->eraseFromParent();
6938 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6939 MachineBasicBlock *MBB) const {
6940 DebugLoc DL = MI->getDebugLoc();
6941 const TargetInstrInfo *TII =
6942 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6944 MachineFunction *MF = MBB->getParent();
6945 MachineRegisterInfo &MRI = MF->getRegInfo();
6948 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6949 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6951 MVT PVT = getPointerTy();
6952 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6953 "Invalid Pointer Size!");
6955 const TargetRegisterClass *RC =
6956 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6957 unsigned Tmp = MRI.createVirtualRegister(RC);
6958 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6959 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6960 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6961 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
6962 (Subtarget.isSVR4ABI() &&
6963 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
6964 PPC::R29 : PPC::R30);
6966 MachineInstrBuilder MIB;
6968 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6969 const int64_t SPOffset = 2 * PVT.getStoreSize();
6970 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6971 const int64_t BPOffset = 4 * PVT.getStoreSize();
6973 unsigned BufReg = MI->getOperand(0).getReg();
6975 // Reload FP (the jumped-to function may not have had a
6976 // frame pointer, and if so, then its r31 will be restored
6978 if (PVT == MVT::i64) {
6979 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6983 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6987 MIB.setMemRefs(MMOBegin, MMOEnd);
6990 if (PVT == MVT::i64) {
6991 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6992 .addImm(LabelOffset)
6995 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6996 .addImm(LabelOffset)
6999 MIB.setMemRefs(MMOBegin, MMOEnd);
7002 if (PVT == MVT::i64) {
7003 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7007 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7011 MIB.setMemRefs(MMOBegin, MMOEnd);
7014 if (PVT == MVT::i64) {
7015 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7019 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7023 MIB.setMemRefs(MMOBegin, MMOEnd);
7026 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7027 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7031 MIB.setMemRefs(MMOBegin, MMOEnd);
7035 BuildMI(*MBB, MI, DL,
7036 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7037 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7039 MI->eraseFromParent();
7044 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7045 MachineBasicBlock *BB) const {
7046 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7047 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7048 return emitEHSjLjSetJmp(MI, BB);
7049 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7050 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7051 return emitEHSjLjLongJmp(MI, BB);
7054 const TargetInstrInfo *TII =
7055 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7057 // To "insert" these instructions we actually have to insert their
7058 // control-flow patterns.
7059 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7060 MachineFunction::iterator It = BB;
7063 MachineFunction *F = BB->getParent();
7065 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7066 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7067 MI->getOpcode() == PPC::SELECT_I4 ||
7068 MI->getOpcode() == PPC::SELECT_I8)) {
7069 SmallVector<MachineOperand, 2> Cond;
7070 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7071 MI->getOpcode() == PPC::SELECT_CC_I8)
7072 Cond.push_back(MI->getOperand(4));
7074 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7075 Cond.push_back(MI->getOperand(1));
7077 DebugLoc dl = MI->getDebugLoc();
7078 const TargetInstrInfo *TII =
7079 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7080 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7081 Cond, MI->getOperand(2).getReg(),
7082 MI->getOperand(3).getReg());
7083 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7084 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7085 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7086 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7087 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7088 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7089 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7090 MI->getOpcode() == PPC::SELECT_I4 ||
7091 MI->getOpcode() == PPC::SELECT_I8 ||
7092 MI->getOpcode() == PPC::SELECT_F4 ||
7093 MI->getOpcode() == PPC::SELECT_F8 ||
7094 MI->getOpcode() == PPC::SELECT_VRRC ||
7095 MI->getOpcode() == PPC::SELECT_VSFRC ||
7096 MI->getOpcode() == PPC::SELECT_VSRC) {
7097 // The incoming instruction knows the destination vreg to set, the
7098 // condition code register to branch on, the true/false values to
7099 // select between, and a branch opcode to use.
7104 // cmpTY ccX, r1, r2
7106 // fallthrough --> copy0MBB
7107 MachineBasicBlock *thisMBB = BB;
7108 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7109 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7110 DebugLoc dl = MI->getDebugLoc();
7111 F->insert(It, copy0MBB);
7112 F->insert(It, sinkMBB);
7114 // Transfer the remainder of BB and its successor edges to sinkMBB.
7115 sinkMBB->splice(sinkMBB->begin(), BB,
7116 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7117 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7119 // Next, add the true and fallthrough blocks as its successors.
7120 BB->addSuccessor(copy0MBB);
7121 BB->addSuccessor(sinkMBB);
7123 if (MI->getOpcode() == PPC::SELECT_I4 ||
7124 MI->getOpcode() == PPC::SELECT_I8 ||
7125 MI->getOpcode() == PPC::SELECT_F4 ||
7126 MI->getOpcode() == PPC::SELECT_F8 ||
7127 MI->getOpcode() == PPC::SELECT_VRRC ||
7128 MI->getOpcode() == PPC::SELECT_VSFRC ||
7129 MI->getOpcode() == PPC::SELECT_VSRC) {
7130 BuildMI(BB, dl, TII->get(PPC::BC))
7131 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7133 unsigned SelectPred = MI->getOperand(4).getImm();
7134 BuildMI(BB, dl, TII->get(PPC::BCC))
7135 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7139 // %FalseValue = ...
7140 // # fallthrough to sinkMBB
7143 // Update machine-CFG edges
7144 BB->addSuccessor(sinkMBB);
7147 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7150 BuildMI(*BB, BB->begin(), dl,
7151 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7152 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7153 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7155 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7156 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7157 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7158 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7159 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7160 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7161 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7162 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7164 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7165 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7166 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7167 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7168 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7169 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7170 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7171 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7173 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7174 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7175 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7176 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7177 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7178 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7179 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7180 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7182 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7183 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7184 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7185 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7186 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7187 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7188 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7189 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7191 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7192 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7193 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7194 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7195 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7196 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7197 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7198 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7200 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7201 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7202 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7203 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7204 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7205 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7206 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7207 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7209 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7210 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7211 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7212 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7213 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7214 BB = EmitAtomicBinary(MI, BB, false, 0);
7215 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7216 BB = EmitAtomicBinary(MI, BB, true, 0);
7218 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7219 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7220 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7222 unsigned dest = MI->getOperand(0).getReg();
7223 unsigned ptrA = MI->getOperand(1).getReg();
7224 unsigned ptrB = MI->getOperand(2).getReg();
7225 unsigned oldval = MI->getOperand(3).getReg();
7226 unsigned newval = MI->getOperand(4).getReg();
7227 DebugLoc dl = MI->getDebugLoc();
7229 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7230 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7231 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7232 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7233 F->insert(It, loop1MBB);
7234 F->insert(It, loop2MBB);
7235 F->insert(It, midMBB);
7236 F->insert(It, exitMBB);
7237 exitMBB->splice(exitMBB->begin(), BB,
7238 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7239 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7243 // fallthrough --> loopMBB
7244 BB->addSuccessor(loop1MBB);
7247 // l[wd]arx dest, ptr
7248 // cmp[wd] dest, oldval
7251 // st[wd]cx. newval, ptr
7255 // st[wd]cx. dest, ptr
7258 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7259 .addReg(ptrA).addReg(ptrB);
7260 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7261 .addReg(oldval).addReg(dest);
7262 BuildMI(BB, dl, TII->get(PPC::BCC))
7263 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7264 BB->addSuccessor(loop2MBB);
7265 BB->addSuccessor(midMBB);
7268 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7269 .addReg(newval).addReg(ptrA).addReg(ptrB);
7270 BuildMI(BB, dl, TII->get(PPC::BCC))
7271 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7272 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7273 BB->addSuccessor(loop1MBB);
7274 BB->addSuccessor(exitMBB);
7277 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7278 .addReg(dest).addReg(ptrA).addReg(ptrB);
7279 BB->addSuccessor(exitMBB);
7284 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7285 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7286 // We must use 64-bit registers for addresses when targeting 64-bit,
7287 // since we're actually doing arithmetic on them. Other registers
7289 bool is64bit = Subtarget.isPPC64();
7290 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7292 unsigned dest = MI->getOperand(0).getReg();
7293 unsigned ptrA = MI->getOperand(1).getReg();
7294 unsigned ptrB = MI->getOperand(2).getReg();
7295 unsigned oldval = MI->getOperand(3).getReg();
7296 unsigned newval = MI->getOperand(4).getReg();
7297 DebugLoc dl = MI->getDebugLoc();
7299 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7300 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7301 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7302 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7303 F->insert(It, loop1MBB);
7304 F->insert(It, loop2MBB);
7305 F->insert(It, midMBB);
7306 F->insert(It, exitMBB);
7307 exitMBB->splice(exitMBB->begin(), BB,
7308 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7309 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7311 MachineRegisterInfo &RegInfo = F->getRegInfo();
7312 const TargetRegisterClass *RC =
7313 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
7314 (const TargetRegisterClass *) &PPC::GPRCRegClass;
7315 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7316 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7317 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7318 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7319 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7320 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7321 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7322 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7323 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7324 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7325 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7326 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7327 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7329 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7330 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7333 // fallthrough --> loopMBB
7334 BB->addSuccessor(loop1MBB);
7336 // The 4-byte load must be aligned, while a char or short may be
7337 // anywhere in the word. Hence all this nasty bookkeeping code.
7338 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7339 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7340 // xori shift, shift1, 24 [16]
7341 // rlwinm ptr, ptr1, 0, 0, 29
7342 // slw newval2, newval, shift
7343 // slw oldval2, oldval,shift
7344 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7345 // slw mask, mask2, shift
7346 // and newval3, newval2, mask
7347 // and oldval3, oldval2, mask
7349 // lwarx tmpDest, ptr
7350 // and tmp, tmpDest, mask
7351 // cmpw tmp, oldval3
7354 // andc tmp2, tmpDest, mask
7355 // or tmp4, tmp2, newval3
7360 // stwcx. tmpDest, ptr
7362 // srw dest, tmpDest, shift
7363 if (ptrA != ZeroReg) {
7364 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7365 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7366 .addReg(ptrA).addReg(ptrB);
7370 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7371 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7372 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7373 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7375 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7376 .addReg(Ptr1Reg).addImm(0).addImm(61);
7378 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7379 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7380 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7381 .addReg(newval).addReg(ShiftReg);
7382 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7383 .addReg(oldval).addReg(ShiftReg);
7385 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7387 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7388 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7389 .addReg(Mask3Reg).addImm(65535);
7391 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7392 .addReg(Mask2Reg).addReg(ShiftReg);
7393 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7394 .addReg(NewVal2Reg).addReg(MaskReg);
7395 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7396 .addReg(OldVal2Reg).addReg(MaskReg);
7399 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7400 .addReg(ZeroReg).addReg(PtrReg);
7401 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7402 .addReg(TmpDestReg).addReg(MaskReg);
7403 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7404 .addReg(TmpReg).addReg(OldVal3Reg);
7405 BuildMI(BB, dl, TII->get(PPC::BCC))
7406 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7407 BB->addSuccessor(loop2MBB);
7408 BB->addSuccessor(midMBB);
7411 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7412 .addReg(TmpDestReg).addReg(MaskReg);
7413 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7414 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7415 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7416 .addReg(ZeroReg).addReg(PtrReg);
7417 BuildMI(BB, dl, TII->get(PPC::BCC))
7418 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7419 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7420 BB->addSuccessor(loop1MBB);
7421 BB->addSuccessor(exitMBB);
7424 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7425 .addReg(ZeroReg).addReg(PtrReg);
7426 BB->addSuccessor(exitMBB);
7431 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7433 } else if (MI->getOpcode() == PPC::FADDrtz) {
7434 // This pseudo performs an FADD with rounding mode temporarily forced
7435 // to round-to-zero. We emit this via custom inserter since the FPSCR
7436 // is not modeled at the SelectionDAG level.
7437 unsigned Dest = MI->getOperand(0).getReg();
7438 unsigned Src1 = MI->getOperand(1).getReg();
7439 unsigned Src2 = MI->getOperand(2).getReg();
7440 DebugLoc dl = MI->getDebugLoc();
7442 MachineRegisterInfo &RegInfo = F->getRegInfo();
7443 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7445 // Save FPSCR value.
7446 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7448 // Set rounding mode to round-to-zero.
7449 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7450 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7452 // Perform addition.
7453 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7455 // Restore FPSCR value.
7456 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7457 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7458 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7459 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7460 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7461 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7462 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7463 PPC::ANDIo8 : PPC::ANDIo;
7464 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7465 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7467 MachineRegisterInfo &RegInfo = F->getRegInfo();
7468 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7469 &PPC::GPRCRegClass :
7470 &PPC::G8RCRegClass);
7472 DebugLoc dl = MI->getDebugLoc();
7473 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7474 .addReg(MI->getOperand(1).getReg()).addImm(1);
7475 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7476 MI->getOperand(0).getReg())
7477 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7479 llvm_unreachable("Unexpected instr type to insert");
7482 MI->eraseFromParent(); // The pseudo instruction is gone now.
7486 //===----------------------------------------------------------------------===//
7487 // Target Optimization Hooks
7488 //===----------------------------------------------------------------------===//
7490 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7491 DAGCombinerInfo &DCI,
7492 unsigned &RefinementSteps,
7493 bool &UseOneConstNR) const {
7494 EVT VT = Operand.getValueType();
7495 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7496 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7497 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7498 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7499 // Convergence is quadratic, so we essentially double the number of digits
7500 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7501 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7502 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7503 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7504 if (VT.getScalarType() == MVT::f64)
7506 UseOneConstNR = true;
7507 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7512 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7513 DAGCombinerInfo &DCI,
7514 unsigned &RefinementSteps) const {
7515 EVT VT = Operand.getValueType();
7516 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7517 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7518 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7519 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7520 // Convergence is quadratic, so we essentially double the number of digits
7521 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7522 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7523 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7524 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7525 if (VT.getScalarType() == MVT::f64)
7527 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7532 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7533 unsigned Bytes, int Dist,
7534 SelectionDAG &DAG) {
7535 if (VT.getSizeInBits() / 8 != Bytes)
7538 SDValue BaseLoc = Base->getBasePtr();
7539 if (Loc.getOpcode() == ISD::FrameIndex) {
7540 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7542 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7543 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7544 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7545 int FS = MFI->getObjectSize(FI);
7546 int BFS = MFI->getObjectSize(BFI);
7547 if (FS != BFS || FS != (int)Bytes) return false;
7548 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7552 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7553 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7556 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7557 const GlobalValue *GV1 = nullptr;
7558 const GlobalValue *GV2 = nullptr;
7559 int64_t Offset1 = 0;
7560 int64_t Offset2 = 0;
7561 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7562 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7563 if (isGA1 && isGA2 && GV1 == GV2)
7564 return Offset1 == (Offset2 + Dist*Bytes);
7568 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7569 // not enforce equality of the chain operands.
7570 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7571 unsigned Bytes, int Dist,
7572 SelectionDAG &DAG) {
7573 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7574 EVT VT = LS->getMemoryVT();
7575 SDValue Loc = LS->getBasePtr();
7576 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7579 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7581 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7582 default: return false;
7583 case Intrinsic::ppc_altivec_lvx:
7584 case Intrinsic::ppc_altivec_lvxl:
7585 case Intrinsic::ppc_vsx_lxvw4x:
7588 case Intrinsic::ppc_vsx_lxvd2x:
7591 case Intrinsic::ppc_altivec_lvebx:
7594 case Intrinsic::ppc_altivec_lvehx:
7597 case Intrinsic::ppc_altivec_lvewx:
7602 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7605 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7607 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7608 default: return false;
7609 case Intrinsic::ppc_altivec_stvx:
7610 case Intrinsic::ppc_altivec_stvxl:
7611 case Intrinsic::ppc_vsx_stxvw4x:
7614 case Intrinsic::ppc_vsx_stxvd2x:
7617 case Intrinsic::ppc_altivec_stvebx:
7620 case Intrinsic::ppc_altivec_stvehx:
7623 case Intrinsic::ppc_altivec_stvewx:
7628 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7634 // Return true is there is a nearyby consecutive load to the one provided
7635 // (regardless of alignment). We search up and down the chain, looking though
7636 // token factors and other loads (but nothing else). As a result, a true result
7637 // indicates that it is safe to create a new consecutive load adjacent to the
7639 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7640 SDValue Chain = LD->getChain();
7641 EVT VT = LD->getMemoryVT();
7643 SmallSet<SDNode *, 16> LoadRoots;
7644 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7645 SmallSet<SDNode *, 16> Visited;
7647 // First, search up the chain, branching to follow all token-factor operands.
7648 // If we find a consecutive load, then we're done, otherwise, record all
7649 // nodes just above the top-level loads and token factors.
7650 while (!Queue.empty()) {
7651 SDNode *ChainNext = Queue.pop_back_val();
7652 if (!Visited.insert(ChainNext))
7655 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7656 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7659 if (!Visited.count(ChainLD->getChain().getNode()))
7660 Queue.push_back(ChainLD->getChain().getNode());
7661 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7662 for (const SDUse &O : ChainNext->ops())
7663 if (!Visited.count(O.getNode()))
7664 Queue.push_back(O.getNode());
7666 LoadRoots.insert(ChainNext);
7669 // Second, search down the chain, starting from the top-level nodes recorded
7670 // in the first phase. These top-level nodes are the nodes just above all
7671 // loads and token factors. Starting with their uses, recursively look though
7672 // all loads (just the chain uses) and token factors to find a consecutive
7677 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7678 IE = LoadRoots.end(); I != IE; ++I) {
7679 Queue.push_back(*I);
7681 while (!Queue.empty()) {
7682 SDNode *LoadRoot = Queue.pop_back_val();
7683 if (!Visited.insert(LoadRoot))
7686 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7687 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7690 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7691 UE = LoadRoot->use_end(); UI != UE; ++UI)
7692 if (((isa<MemSDNode>(*UI) &&
7693 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7694 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7695 Queue.push_back(*UI);
7702 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7703 DAGCombinerInfo &DCI) const {
7704 SelectionDAG &DAG = DCI.DAG;
7707 assert(Subtarget.useCRBits() &&
7708 "Expecting to be tracking CR bits");
7709 // If we're tracking CR bits, we need to be careful that we don't have:
7710 // trunc(binary-ops(zext(x), zext(y)))
7712 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7713 // such that we're unnecessarily moving things into GPRs when it would be
7714 // better to keep them in CR bits.
7716 // Note that trunc here can be an actual i1 trunc, or can be the effective
7717 // truncation that comes from a setcc or select_cc.
7718 if (N->getOpcode() == ISD::TRUNCATE &&
7719 N->getValueType(0) != MVT::i1)
7722 if (N->getOperand(0).getValueType() != MVT::i32 &&
7723 N->getOperand(0).getValueType() != MVT::i64)
7726 if (N->getOpcode() == ISD::SETCC ||
7727 N->getOpcode() == ISD::SELECT_CC) {
7728 // If we're looking at a comparison, then we need to make sure that the
7729 // high bits (all except for the first) don't matter the result.
7731 cast<CondCodeSDNode>(N->getOperand(
7732 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7733 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7735 if (ISD::isSignedIntSetCC(CC)) {
7736 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7737 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7739 } else if (ISD::isUnsignedIntSetCC(CC)) {
7740 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7741 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7742 !DAG.MaskedValueIsZero(N->getOperand(1),
7743 APInt::getHighBitsSet(OpBits, OpBits-1)))
7746 // This is neither a signed nor an unsigned comparison, just make sure
7747 // that the high bits are equal.
7748 APInt Op1Zero, Op1One;
7749 APInt Op2Zero, Op2One;
7750 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7751 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7753 // We don't really care about what is known about the first bit (if
7754 // anything), so clear it in all masks prior to comparing them.
7755 Op1Zero.clearBit(0); Op1One.clearBit(0);
7756 Op2Zero.clearBit(0); Op2One.clearBit(0);
7758 if (Op1Zero != Op2Zero || Op1One != Op2One)
7763 // We now know that the higher-order bits are irrelevant, we just need to
7764 // make sure that all of the intermediate operations are bit operations, and
7765 // all inputs are extensions.
7766 if (N->getOperand(0).getOpcode() != ISD::AND &&
7767 N->getOperand(0).getOpcode() != ISD::OR &&
7768 N->getOperand(0).getOpcode() != ISD::XOR &&
7769 N->getOperand(0).getOpcode() != ISD::SELECT &&
7770 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7771 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7772 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7773 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7774 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7777 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7778 N->getOperand(1).getOpcode() != ISD::AND &&
7779 N->getOperand(1).getOpcode() != ISD::OR &&
7780 N->getOperand(1).getOpcode() != ISD::XOR &&
7781 N->getOperand(1).getOpcode() != ISD::SELECT &&
7782 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7783 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7784 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7785 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7786 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7789 SmallVector<SDValue, 4> Inputs;
7790 SmallVector<SDValue, 8> BinOps, PromOps;
7791 SmallPtrSet<SDNode *, 16> Visited;
7793 for (unsigned i = 0; i < 2; ++i) {
7794 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7795 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7796 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7797 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7798 isa<ConstantSDNode>(N->getOperand(i)))
7799 Inputs.push_back(N->getOperand(i));
7801 BinOps.push_back(N->getOperand(i));
7803 if (N->getOpcode() == ISD::TRUNCATE)
7807 // Visit all inputs, collect all binary operations (and, or, xor and
7808 // select) that are all fed by extensions.
7809 while (!BinOps.empty()) {
7810 SDValue BinOp = BinOps.back();
7813 if (!Visited.insert(BinOp.getNode()))
7816 PromOps.push_back(BinOp);
7818 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7819 // The condition of the select is not promoted.
7820 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7822 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7825 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7826 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7827 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7828 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7829 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7830 Inputs.push_back(BinOp.getOperand(i));
7831 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7832 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7833 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7834 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7835 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7836 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7837 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7838 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7839 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7840 BinOps.push_back(BinOp.getOperand(i));
7842 // We have an input that is not an extension or another binary
7843 // operation; we'll abort this transformation.
7849 // Make sure that this is a self-contained cluster of operations (which
7850 // is not quite the same thing as saying that everything has only one
7852 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7853 if (isa<ConstantSDNode>(Inputs[i]))
7856 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7857 UE = Inputs[i].getNode()->use_end();
7860 if (User != N && !Visited.count(User))
7863 // Make sure that we're not going to promote the non-output-value
7864 // operand(s) or SELECT or SELECT_CC.
7865 // FIXME: Although we could sometimes handle this, and it does occur in
7866 // practice that one of the condition inputs to the select is also one of
7867 // the outputs, we currently can't deal with this.
7868 if (User->getOpcode() == ISD::SELECT) {
7869 if (User->getOperand(0) == Inputs[i])
7871 } else if (User->getOpcode() == ISD::SELECT_CC) {
7872 if (User->getOperand(0) == Inputs[i] ||
7873 User->getOperand(1) == Inputs[i])
7879 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7880 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7881 UE = PromOps[i].getNode()->use_end();
7884 if (User != N && !Visited.count(User))
7887 // Make sure that we're not going to promote the non-output-value
7888 // operand(s) or SELECT or SELECT_CC.
7889 // FIXME: Although we could sometimes handle this, and it does occur in
7890 // practice that one of the condition inputs to the select is also one of
7891 // the outputs, we currently can't deal with this.
7892 if (User->getOpcode() == ISD::SELECT) {
7893 if (User->getOperand(0) == PromOps[i])
7895 } else if (User->getOpcode() == ISD::SELECT_CC) {
7896 if (User->getOperand(0) == PromOps[i] ||
7897 User->getOperand(1) == PromOps[i])
7903 // Replace all inputs with the extension operand.
7904 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7905 // Constants may have users outside the cluster of to-be-promoted nodes,
7906 // and so we need to replace those as we do the promotions.
7907 if (isa<ConstantSDNode>(Inputs[i]))
7910 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7913 // Replace all operations (these are all the same, but have a different
7914 // (i1) return type). DAG.getNode will validate that the types of
7915 // a binary operator match, so go through the list in reverse so that
7916 // we've likely promoted both operands first. Any intermediate truncations or
7917 // extensions disappear.
7918 while (!PromOps.empty()) {
7919 SDValue PromOp = PromOps.back();
7922 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7923 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7924 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7925 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7926 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7927 PromOp.getOperand(0).getValueType() != MVT::i1) {
7928 // The operand is not yet ready (see comment below).
7929 PromOps.insert(PromOps.begin(), PromOp);
7933 SDValue RepValue = PromOp.getOperand(0);
7934 if (isa<ConstantSDNode>(RepValue))
7935 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7937 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7942 switch (PromOp.getOpcode()) {
7943 default: C = 0; break;
7944 case ISD::SELECT: C = 1; break;
7945 case ISD::SELECT_CC: C = 2; break;
7948 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7949 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7950 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7951 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7952 // The to-be-promoted operands of this node have not yet been
7953 // promoted (this should be rare because we're going through the
7954 // list backward, but if one of the operands has several users in
7955 // this cluster of to-be-promoted nodes, it is possible).
7956 PromOps.insert(PromOps.begin(), PromOp);
7960 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7961 PromOp.getNode()->op_end());
7963 // If there are any constant inputs, make sure they're replaced now.
7964 for (unsigned i = 0; i < 2; ++i)
7965 if (isa<ConstantSDNode>(Ops[C+i]))
7966 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7968 DAG.ReplaceAllUsesOfValueWith(PromOp,
7969 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7972 // Now we're left with the initial truncation itself.
7973 if (N->getOpcode() == ISD::TRUNCATE)
7974 return N->getOperand(0);
7976 // Otherwise, this is a comparison. The operands to be compared have just
7977 // changed type (to i1), but everything else is the same.
7978 return SDValue(N, 0);
7981 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7982 DAGCombinerInfo &DCI) const {
7983 SelectionDAG &DAG = DCI.DAG;
7986 // If we're tracking CR bits, we need to be careful that we don't have:
7987 // zext(binary-ops(trunc(x), trunc(y)))
7989 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7990 // such that we're unnecessarily moving things into CR bits that can more
7991 // efficiently stay in GPRs. Note that if we're not certain that the high
7992 // bits are set as required by the final extension, we still may need to do
7993 // some masking to get the proper behavior.
7995 // This same functionality is important on PPC64 when dealing with
7996 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7997 // the return values of functions. Because it is so similar, it is handled
8000 if (N->getValueType(0) != MVT::i32 &&
8001 N->getValueType(0) != MVT::i64)
8004 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8005 Subtarget.useCRBits()) ||
8006 (N->getOperand(0).getValueType() == MVT::i32 &&
8007 Subtarget.isPPC64())))
8010 if (N->getOperand(0).getOpcode() != ISD::AND &&
8011 N->getOperand(0).getOpcode() != ISD::OR &&
8012 N->getOperand(0).getOpcode() != ISD::XOR &&
8013 N->getOperand(0).getOpcode() != ISD::SELECT &&
8014 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8017 SmallVector<SDValue, 4> Inputs;
8018 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8019 SmallPtrSet<SDNode *, 16> Visited;
8021 // Visit all inputs, collect all binary operations (and, or, xor and
8022 // select) that are all fed by truncations.
8023 while (!BinOps.empty()) {
8024 SDValue BinOp = BinOps.back();
8027 if (!Visited.insert(BinOp.getNode()))
8030 PromOps.push_back(BinOp);
8032 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8033 // The condition of the select is not promoted.
8034 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8036 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8039 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8040 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8041 Inputs.push_back(BinOp.getOperand(i));
8042 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8043 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8044 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8045 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8046 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8047 BinOps.push_back(BinOp.getOperand(i));
8049 // We have an input that is not a truncation or another binary
8050 // operation; we'll abort this transformation.
8056 // Make sure that this is a self-contained cluster of operations (which
8057 // is not quite the same thing as saying that everything has only one
8059 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8060 if (isa<ConstantSDNode>(Inputs[i]))
8063 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8064 UE = Inputs[i].getNode()->use_end();
8067 if (User != N && !Visited.count(User))
8070 // Make sure that we're not going to promote the non-output-value
8071 // operand(s) or SELECT or SELECT_CC.
8072 // FIXME: Although we could sometimes handle this, and it does occur in
8073 // practice that one of the condition inputs to the select is also one of
8074 // the outputs, we currently can't deal with this.
8075 if (User->getOpcode() == ISD::SELECT) {
8076 if (User->getOperand(0) == Inputs[i])
8078 } else if (User->getOpcode() == ISD::SELECT_CC) {
8079 if (User->getOperand(0) == Inputs[i] ||
8080 User->getOperand(1) == Inputs[i])
8086 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8087 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8088 UE = PromOps[i].getNode()->use_end();
8091 if (User != N && !Visited.count(User))
8094 // Make sure that we're not going to promote the non-output-value
8095 // operand(s) or SELECT or SELECT_CC.
8096 // FIXME: Although we could sometimes handle this, and it does occur in
8097 // practice that one of the condition inputs to the select is also one of
8098 // the outputs, we currently can't deal with this.
8099 if (User->getOpcode() == ISD::SELECT) {
8100 if (User->getOperand(0) == PromOps[i])
8102 } else if (User->getOpcode() == ISD::SELECT_CC) {
8103 if (User->getOperand(0) == PromOps[i] ||
8104 User->getOperand(1) == PromOps[i])
8110 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8111 bool ReallyNeedsExt = false;
8112 if (N->getOpcode() != ISD::ANY_EXTEND) {
8113 // If all of the inputs are not already sign/zero extended, then
8114 // we'll still need to do that at the end.
8115 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8116 if (isa<ConstantSDNode>(Inputs[i]))
8120 Inputs[i].getOperand(0).getValueSizeInBits();
8121 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8123 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8124 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8125 APInt::getHighBitsSet(OpBits,
8126 OpBits-PromBits))) ||
8127 (N->getOpcode() == ISD::SIGN_EXTEND &&
8128 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8129 (OpBits-(PromBits-1)))) {
8130 ReallyNeedsExt = true;
8136 // Replace all inputs, either with the truncation operand, or a
8137 // truncation or extension to the final output type.
8138 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8139 // Constant inputs need to be replaced with the to-be-promoted nodes that
8140 // use them because they might have users outside of the cluster of
8142 if (isa<ConstantSDNode>(Inputs[i]))
8145 SDValue InSrc = Inputs[i].getOperand(0);
8146 if (Inputs[i].getValueType() == N->getValueType(0))
8147 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8148 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8149 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8150 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8151 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8152 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8153 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8155 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8156 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8159 // Replace all operations (these are all the same, but have a different
8160 // (promoted) return type). DAG.getNode will validate that the types of
8161 // a binary operator match, so go through the list in reverse so that
8162 // we've likely promoted both operands first.
8163 while (!PromOps.empty()) {
8164 SDValue PromOp = PromOps.back();
8168 switch (PromOp.getOpcode()) {
8169 default: C = 0; break;
8170 case ISD::SELECT: C = 1; break;
8171 case ISD::SELECT_CC: C = 2; break;
8174 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8175 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8176 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8177 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8178 // The to-be-promoted operands of this node have not yet been
8179 // promoted (this should be rare because we're going through the
8180 // list backward, but if one of the operands has several users in
8181 // this cluster of to-be-promoted nodes, it is possible).
8182 PromOps.insert(PromOps.begin(), PromOp);
8186 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8187 PromOp.getNode()->op_end());
8189 // If this node has constant inputs, then they'll need to be promoted here.
8190 for (unsigned i = 0; i < 2; ++i) {
8191 if (!isa<ConstantSDNode>(Ops[C+i]))
8193 if (Ops[C+i].getValueType() == N->getValueType(0))
8196 if (N->getOpcode() == ISD::SIGN_EXTEND)
8197 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8198 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8199 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8201 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8204 DAG.ReplaceAllUsesOfValueWith(PromOp,
8205 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8208 // Now we're left with the initial extension itself.
8209 if (!ReallyNeedsExt)
8210 return N->getOperand(0);
8212 // To zero extend, just mask off everything except for the first bit (in the
8214 if (N->getOpcode() == ISD::ZERO_EXTEND)
8215 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8216 DAG.getConstant(APInt::getLowBitsSet(
8217 N->getValueSizeInBits(0), PromBits),
8218 N->getValueType(0)));
8220 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8221 "Invalid extension type");
8222 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8224 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8225 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8226 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8227 N->getOperand(0), ShiftCst), ShiftCst);
8230 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8231 DAGCombinerInfo &DCI) const {
8232 const TargetMachine &TM = getTargetMachine();
8233 SelectionDAG &DAG = DCI.DAG;
8235 switch (N->getOpcode()) {
8238 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8239 if (C->isNullValue()) // 0 << V -> 0.
8240 return N->getOperand(0);
8244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8245 if (C->isNullValue()) // 0 >>u V -> 0.
8246 return N->getOperand(0);
8250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8251 if (C->isNullValue() || // 0 >>s V -> 0.
8252 C->isAllOnesValue()) // -1 >>s V -> -1.
8253 return N->getOperand(0);
8256 case ISD::SIGN_EXTEND:
8257 case ISD::ZERO_EXTEND:
8258 case ISD::ANY_EXTEND:
8259 return DAGCombineExtBoolTrunc(N, DCI);
8262 case ISD::SELECT_CC:
8263 return DAGCombineTruncBoolExt(N, DCI);
8264 case ISD::SINT_TO_FP:
8265 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8266 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8267 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8268 // We allow the src/dst to be either f32/f64, but the intermediate
8269 // type must be i64.
8270 if (N->getOperand(0).getValueType() == MVT::i64 &&
8271 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8272 SDValue Val = N->getOperand(0).getOperand(0);
8273 if (Val.getValueType() == MVT::f32) {
8274 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8275 DCI.AddToWorklist(Val.getNode());
8278 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8279 DCI.AddToWorklist(Val.getNode());
8280 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8281 DCI.AddToWorklist(Val.getNode());
8282 if (N->getValueType(0) == MVT::f32) {
8283 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8284 DAG.getIntPtrConstant(0));
8285 DCI.AddToWorklist(Val.getNode());
8288 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8289 // If the intermediate type is i32, we can avoid the load/store here
8296 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8297 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8298 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8299 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8300 N->getOperand(1).getValueType() == MVT::i32 &&
8301 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8302 SDValue Val = N->getOperand(1).getOperand(0);
8303 if (Val.getValueType() == MVT::f32) {
8304 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8305 DCI.AddToWorklist(Val.getNode());
8307 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8308 DCI.AddToWorklist(Val.getNode());
8311 N->getOperand(0), Val, N->getOperand(2),
8312 DAG.getValueType(N->getOperand(1).getValueType())
8315 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8316 DAG.getVTList(MVT::Other), Ops,
8317 cast<StoreSDNode>(N)->getMemoryVT(),
8318 cast<StoreSDNode>(N)->getMemOperand());
8319 DCI.AddToWorklist(Val.getNode());
8323 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8324 if (cast<StoreSDNode>(N)->isUnindexed() &&
8325 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8326 N->getOperand(1).getNode()->hasOneUse() &&
8327 (N->getOperand(1).getValueType() == MVT::i32 ||
8328 N->getOperand(1).getValueType() == MVT::i16 ||
8329 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8330 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8331 N->getOperand(1).getValueType() == MVT::i64))) {
8332 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8333 // Do an any-extend to 32-bits if this is a half-word input.
8334 if (BSwapOp.getValueType() == MVT::i16)
8335 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8338 N->getOperand(0), BSwapOp, N->getOperand(2),
8339 DAG.getValueType(N->getOperand(1).getValueType())
8342 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8343 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8344 cast<StoreSDNode>(N)->getMemOperand());
8348 LoadSDNode *LD = cast<LoadSDNode>(N);
8349 EVT VT = LD->getValueType(0);
8350 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8351 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8352 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8353 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8354 // P8 and later hardware should just use LOAD.
8355 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8356 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8357 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8358 LD->getAlignment() < ABIAlignment) {
8359 // This is a type-legal unaligned Altivec load.
8360 SDValue Chain = LD->getChain();
8361 SDValue Ptr = LD->getBasePtr();
8362 bool isLittleEndian = Subtarget.isLittleEndian();
8364 // This implements the loading of unaligned vectors as described in
8365 // the venerable Apple Velocity Engine overview. Specifically:
8366 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8367 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8369 // The general idea is to expand a sequence of one or more unaligned
8370 // loads into an alignment-based permutation-control instruction (lvsl
8371 // or lvsr), a series of regular vector loads (which always truncate
8372 // their input address to an aligned address), and a series of
8373 // permutations. The results of these permutations are the requested
8374 // loaded values. The trick is that the last "extra" load is not taken
8375 // from the address you might suspect (sizeof(vector) bytes after the
8376 // last requested load), but rather sizeof(vector) - 1 bytes after the
8377 // last requested vector. The point of this is to avoid a page fault if
8378 // the base address happened to be aligned. This works because if the
8379 // base address is aligned, then adding less than a full vector length
8380 // will cause the last vector in the sequence to be (re)loaded.
8381 // Otherwise, the next vector will be fetched as you might suspect was
8384 // We might be able to reuse the permutation generation from
8385 // a different base address offset from this one by an aligned amount.
8386 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8387 // optimization later.
8388 Intrinsic::ID Intr = (isLittleEndian ?
8389 Intrinsic::ppc_altivec_lvsr :
8390 Intrinsic::ppc_altivec_lvsl);
8391 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8393 // Create the new MMO for the new base load. It is like the original MMO,
8394 // but represents an area in memory almost twice the vector size centered
8395 // on the original address. If the address is unaligned, we might start
8396 // reading up to (sizeof(vector)-1) bytes below the address of the
8397 // original unaligned load.
8398 MachineFunction &MF = DAG.getMachineFunction();
8399 MachineMemOperand *BaseMMO =
8400 MF.getMachineMemOperand(LD->getMemOperand(),
8401 -LD->getMemoryVT().getStoreSize()+1,
8402 2*LD->getMemoryVT().getStoreSize()-1);
8404 // Create the new base load.
8405 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8407 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8409 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8410 DAG.getVTList(MVT::v4i32, MVT::Other),
8411 BaseLoadOps, MVT::v4i32, BaseMMO);
8413 // Note that the value of IncOffset (which is provided to the next
8414 // load's pointer info offset value, and thus used to calculate the
8415 // alignment), and the value of IncValue (which is actually used to
8416 // increment the pointer value) are different! This is because we
8417 // require the next load to appear to be aligned, even though it
8418 // is actually offset from the base pointer by a lesser amount.
8419 int IncOffset = VT.getSizeInBits() / 8;
8420 int IncValue = IncOffset;
8422 // Walk (both up and down) the chain looking for another load at the real
8423 // (aligned) offset (the alignment of the other load does not matter in
8424 // this case). If found, then do not use the offset reduction trick, as
8425 // that will prevent the loads from being later combined (as they would
8426 // otherwise be duplicates).
8427 if (!findConsecutiveLoad(LD, DAG))
8430 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8431 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8433 MachineMemOperand *ExtraMMO =
8434 MF.getMachineMemOperand(LD->getMemOperand(),
8435 1, 2*LD->getMemoryVT().getStoreSize()-1);
8436 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8438 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8439 DAG.getVTList(MVT::v4i32, MVT::Other),
8440 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8442 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8443 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8445 // Because vperm has a big-endian bias, we must reverse the order
8446 // of the input vectors and complement the permute control vector
8447 // when generating little endian code. We have already handled the
8448 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8449 // and ExtraLoad here.
8452 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8453 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8455 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8456 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8458 if (VT != MVT::v4i32)
8459 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8461 // The output of the permutation is our loaded result, the TokenFactor is
8463 DCI.CombineTo(N, Perm, TF);
8464 return SDValue(N, 0);
8468 case ISD::INTRINSIC_WO_CHAIN: {
8469 bool isLittleEndian = Subtarget.isLittleEndian();
8470 Intrinsic::ID Intr = (isLittleEndian ?
8471 Intrinsic::ppc_altivec_lvsr :
8472 Intrinsic::ppc_altivec_lvsl);
8473 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8474 N->getOperand(1)->getOpcode() == ISD::ADD) {
8475 SDValue Add = N->getOperand(1);
8477 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8478 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8479 Add.getValueType().getScalarType().getSizeInBits()))) {
8480 SDNode *BasePtr = Add->getOperand(0).getNode();
8481 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8482 UE = BasePtr->use_end(); UI != UE; ++UI) {
8483 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8484 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8486 // We've found another LVSL/LVSR, and this address is an aligned
8487 // multiple of that one. The results will be the same, so use the
8488 // one we've just found instead.
8490 return SDValue(*UI, 0);
8499 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8500 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8501 N->getOperand(0).hasOneUse() &&
8502 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8503 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8504 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8505 N->getValueType(0) == MVT::i64))) {
8506 SDValue Load = N->getOperand(0);
8507 LoadSDNode *LD = cast<LoadSDNode>(Load);
8508 // Create the byte-swapping load.
8510 LD->getChain(), // Chain
8511 LD->getBasePtr(), // Ptr
8512 DAG.getValueType(N->getValueType(0)) // VT
8515 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8516 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8517 MVT::i64 : MVT::i32, MVT::Other),
8518 Ops, LD->getMemoryVT(), LD->getMemOperand());
8520 // If this is an i16 load, insert the truncate.
8521 SDValue ResVal = BSLoad;
8522 if (N->getValueType(0) == MVT::i16)
8523 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8525 // First, combine the bswap away. This makes the value produced by the
8527 DCI.CombineTo(N, ResVal);
8529 // Next, combine the load away, we give it a bogus result value but a real
8530 // chain result. The result value is dead because the bswap is dead.
8531 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8533 // Return N so it doesn't get rechecked!
8534 return SDValue(N, 0);
8538 case PPCISD::VCMP: {
8539 // If a VCMPo node already exists with exactly the same operands as this
8540 // node, use its result instead of this node (VCMPo computes both a CR6 and
8541 // a normal output).
8543 if (!N->getOperand(0).hasOneUse() &&
8544 !N->getOperand(1).hasOneUse() &&
8545 !N->getOperand(2).hasOneUse()) {
8547 // Scan all of the users of the LHS, looking for VCMPo's that match.
8548 SDNode *VCMPoNode = nullptr;
8550 SDNode *LHSN = N->getOperand(0).getNode();
8551 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8553 if (UI->getOpcode() == PPCISD::VCMPo &&
8554 UI->getOperand(1) == N->getOperand(1) &&
8555 UI->getOperand(2) == N->getOperand(2) &&
8556 UI->getOperand(0) == N->getOperand(0)) {
8561 // If there is no VCMPo node, or if the flag value has a single use, don't
8563 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8566 // Look at the (necessarily single) use of the flag value. If it has a
8567 // chain, this transformation is more complex. Note that multiple things
8568 // could use the value result, which we should ignore.
8569 SDNode *FlagUser = nullptr;
8570 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8571 FlagUser == nullptr; ++UI) {
8572 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8574 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8575 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8582 // If the user is a MFOCRF instruction, we know this is safe.
8583 // Otherwise we give up for right now.
8584 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8585 return SDValue(VCMPoNode, 0);
8590 SDValue Cond = N->getOperand(1);
8591 SDValue Target = N->getOperand(2);
8593 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8594 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8595 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8597 // We now need to make the intrinsic dead (it cannot be instruction
8599 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8600 assert(Cond.getNode()->hasOneUse() &&
8601 "Counter decrement has more than one use");
8603 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8604 N->getOperand(0), Target);
8609 // If this is a branch on an altivec predicate comparison, lower this so
8610 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8611 // lowering is done pre-legalize, because the legalizer lowers the predicate
8612 // compare down to code that is difficult to reassemble.
8613 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8614 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8616 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8617 // value. If so, pass-through the AND to get to the intrinsic.
8618 if (LHS.getOpcode() == ISD::AND &&
8619 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8620 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8621 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8622 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8623 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8625 LHS = LHS.getOperand(0);
8627 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8628 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8629 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8630 isa<ConstantSDNode>(RHS)) {
8631 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8632 "Counter decrement comparison is not EQ or NE");
8634 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8635 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8636 (CC == ISD::SETNE && !Val);
8638 // We now need to make the intrinsic dead (it cannot be instruction
8640 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8641 assert(LHS.getNode()->hasOneUse() &&
8642 "Counter decrement has more than one use");
8644 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8645 N->getOperand(0), N->getOperand(4));
8651 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8652 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8653 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8654 assert(isDot && "Can't compare against a vector result!");
8656 // If this is a comparison against something other than 0/1, then we know
8657 // that the condition is never/always true.
8658 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8659 if (Val != 0 && Val != 1) {
8660 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8661 return N->getOperand(0);
8662 // Always !=, turn it into an unconditional branch.
8663 return DAG.getNode(ISD::BR, dl, MVT::Other,
8664 N->getOperand(0), N->getOperand(4));
8667 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8669 // Create the PPCISD altivec 'dot' comparison node.
8671 LHS.getOperand(2), // LHS of compare
8672 LHS.getOperand(3), // RHS of compare
8673 DAG.getConstant(CompareOpc, MVT::i32)
8675 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8676 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8678 // Unpack the result based on how the target uses it.
8679 PPC::Predicate CompOpc;
8680 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8681 default: // Can't happen, don't crash on invalid number though.
8682 case 0: // Branch on the value of the EQ bit of CR6.
8683 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8685 case 1: // Branch on the inverted value of the EQ bit of CR6.
8686 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8688 case 2: // Branch on the value of the LT bit of CR6.
8689 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8691 case 3: // Branch on the inverted value of the LT bit of CR6.
8692 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8696 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8697 DAG.getConstant(CompOpc, MVT::i32),
8698 DAG.getRegister(PPC::CR6, MVT::i32),
8699 N->getOperand(4), CompNode.getValue(1));
8708 //===----------------------------------------------------------------------===//
8709 // Inline Assembly Support
8710 //===----------------------------------------------------------------------===//
8712 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8715 const SelectionDAG &DAG,
8716 unsigned Depth) const {
8717 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8718 switch (Op.getOpcode()) {
8720 case PPCISD::LBRX: {
8721 // lhbrx is known to have the top bits cleared out.
8722 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8723 KnownZero = 0xFFFF0000;
8726 case ISD::INTRINSIC_WO_CHAIN: {
8727 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8729 case Intrinsic::ppc_altivec_vcmpbfp_p:
8730 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8731 case Intrinsic::ppc_altivec_vcmpequb_p:
8732 case Intrinsic::ppc_altivec_vcmpequh_p:
8733 case Intrinsic::ppc_altivec_vcmpequw_p:
8734 case Intrinsic::ppc_altivec_vcmpgefp_p:
8735 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8736 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8737 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8738 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8739 case Intrinsic::ppc_altivec_vcmpgtub_p:
8740 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8741 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8742 KnownZero = ~1U; // All bits but the low one are known to be zero.
8750 /// getConstraintType - Given a constraint, return the type of
8751 /// constraint it is for this target.
8752 PPCTargetLowering::ConstraintType
8753 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8754 if (Constraint.size() == 1) {
8755 switch (Constraint[0]) {
8762 return C_RegisterClass;
8764 // FIXME: While Z does indicate a memory constraint, it specifically
8765 // indicates an r+r address (used in conjunction with the 'y' modifier
8766 // in the replacement string). Currently, we're forcing the base
8767 // register to be r0 in the asm printer (which is interpreted as zero)
8768 // and forming the complete address in the second register. This is
8772 } else if (Constraint == "wc") { // individual CR bits.
8773 return C_RegisterClass;
8774 } else if (Constraint == "wa" || Constraint == "wd" ||
8775 Constraint == "wf" || Constraint == "ws") {
8776 return C_RegisterClass; // VSX registers.
8778 return TargetLowering::getConstraintType(Constraint);
8781 /// Examine constraint type and operand type and determine a weight value.
8782 /// This object must already have been set up with the operand type
8783 /// and the current alternative constraint selected.
8784 TargetLowering::ConstraintWeight
8785 PPCTargetLowering::getSingleConstraintMatchWeight(
8786 AsmOperandInfo &info, const char *constraint) const {
8787 ConstraintWeight weight = CW_Invalid;
8788 Value *CallOperandVal = info.CallOperandVal;
8789 // If we don't have a value, we can't do a match,
8790 // but allow it at the lowest weight.
8791 if (!CallOperandVal)
8793 Type *type = CallOperandVal->getType();
8795 // Look at the constraint type.
8796 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8797 return CW_Register; // an individual CR bit.
8798 else if ((StringRef(constraint) == "wa" ||
8799 StringRef(constraint) == "wd" ||
8800 StringRef(constraint) == "wf") &&
8803 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8806 switch (*constraint) {
8808 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8811 if (type->isIntegerTy())
8812 weight = CW_Register;
8815 if (type->isFloatTy())
8816 weight = CW_Register;
8819 if (type->isDoubleTy())
8820 weight = CW_Register;
8823 if (type->isVectorTy())
8824 weight = CW_Register;
8827 weight = CW_Register;
8836 std::pair<unsigned, const TargetRegisterClass*>
8837 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8839 if (Constraint.size() == 1) {
8840 // GCC RS6000 Constraint Letters
8841 switch (Constraint[0]) {
8843 if (VT == MVT::i64 && Subtarget.isPPC64())
8844 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8845 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8847 if (VT == MVT::i64 && Subtarget.isPPC64())
8848 return std::make_pair(0U, &PPC::G8RCRegClass);
8849 return std::make_pair(0U, &PPC::GPRCRegClass);
8851 if (VT == MVT::f32 || VT == MVT::i32)
8852 return std::make_pair(0U, &PPC::F4RCRegClass);
8853 if (VT == MVT::f64 || VT == MVT::i64)
8854 return std::make_pair(0U, &PPC::F8RCRegClass);
8857 return std::make_pair(0U, &PPC::VRRCRegClass);
8859 return std::make_pair(0U, &PPC::CRRCRegClass);
8861 } else if (Constraint == "wc") { // an individual CR bit.
8862 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8863 } else if (Constraint == "wa" || Constraint == "wd" ||
8864 Constraint == "wf") {
8865 return std::make_pair(0U, &PPC::VSRCRegClass);
8866 } else if (Constraint == "ws") {
8867 return std::make_pair(0U, &PPC::VSFRCRegClass);
8870 std::pair<unsigned, const TargetRegisterClass*> R =
8871 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8873 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8874 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8875 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8877 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8878 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8879 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8880 PPC::GPRCRegClass.contains(R.first)) {
8881 const TargetRegisterInfo *TRI =
8882 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
8883 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8884 PPC::sub_32, &PPC::G8RCRegClass),
8885 &PPC::G8RCRegClass);
8892 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8893 /// vector. If it is invalid, don't add anything to Ops.
8894 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8895 std::string &Constraint,
8896 std::vector<SDValue>&Ops,
8897 SelectionDAG &DAG) const {
8900 // Only support length 1 constraints.
8901 if (Constraint.length() > 1) return;
8903 char Letter = Constraint[0];
8914 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8915 if (!CST) return; // Must be an immediate to match.
8916 unsigned Value = CST->getZExtValue();
8918 default: llvm_unreachable("Unknown constraint letter!");
8919 case 'I': // "I" is a signed 16-bit constant.
8920 if ((short)Value == (int)Value)
8921 Result = DAG.getTargetConstant(Value, Op.getValueType());
8923 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8924 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8925 if ((short)Value == 0)
8926 Result = DAG.getTargetConstant(Value, Op.getValueType());
8928 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8929 if ((Value >> 16) == 0)
8930 Result = DAG.getTargetConstant(Value, Op.getValueType());
8932 case 'M': // "M" is a constant that is greater than 31.
8934 Result = DAG.getTargetConstant(Value, Op.getValueType());
8936 case 'N': // "N" is a positive constant that is an exact power of two.
8937 if ((int)Value > 0 && isPowerOf2_32(Value))
8938 Result = DAG.getTargetConstant(Value, Op.getValueType());
8940 case 'O': // "O" is the constant zero.
8942 Result = DAG.getTargetConstant(Value, Op.getValueType());
8944 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8945 if ((short)-Value == (int)-Value)
8946 Result = DAG.getTargetConstant(Value, Op.getValueType());
8953 if (Result.getNode()) {
8954 Ops.push_back(Result);
8958 // Handle standard constraint letters.
8959 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8962 // isLegalAddressingMode - Return true if the addressing mode represented
8963 // by AM is legal for this target, for a load/store of the specified type.
8964 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8966 // FIXME: PPC does not allow r+i addressing modes for vectors!
8968 // PPC allows a sign-extended 16-bit immediate field.
8969 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8972 // No global is ever allowed as a base.
8976 // PPC only support r+r,
8978 case 0: // "r+i" or just "i", depending on HasBaseReg.
8981 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8983 // Otherwise we have r+r or r+i.
8986 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8988 // Allow 2*r as r+r.
8991 // No other scales are supported.
8998 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8999 SelectionDAG &DAG) const {
9000 MachineFunction &MF = DAG.getMachineFunction();
9001 MachineFrameInfo *MFI = MF.getFrameInfo();
9002 MFI->setReturnAddressIsTaken(true);
9004 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9008 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9010 // Make sure the function does not optimize away the store of the RA to
9012 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9013 FuncInfo->setLRStoreRequired();
9014 bool isPPC64 = Subtarget.isPPC64();
9015 bool isDarwinABI = Subtarget.isDarwinABI();
9018 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9021 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9022 isPPC64? MVT::i64 : MVT::i32);
9023 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9024 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9026 MachinePointerInfo(), false, false, false, 0);
9029 // Just load the return address off the stack.
9030 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9031 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9032 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9035 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9036 SelectionDAG &DAG) const {
9038 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9040 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9041 bool isPPC64 = PtrVT == MVT::i64;
9043 MachineFunction &MF = DAG.getMachineFunction();
9044 MachineFrameInfo *MFI = MF.getFrameInfo();
9045 MFI->setFrameAddressIsTaken(true);
9047 // Naked functions never have a frame pointer, and so we use r1. For all
9048 // other functions, this decision must be delayed until during PEI.
9050 if (MF.getFunction()->getAttributes().hasAttribute(
9051 AttributeSet::FunctionIndex, Attribute::Naked))
9052 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9054 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9056 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9059 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9060 FrameAddr, MachinePointerInfo(), false, false,
9065 // FIXME? Maybe this could be a TableGen attribute on some registers and
9066 // this table could be generated automatically from RegInfo.
9067 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9069 bool isPPC64 = Subtarget.isPPC64();
9070 bool isDarwinABI = Subtarget.isDarwinABI();
9072 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9073 (!isPPC64 && VT != MVT::i32))
9074 report_fatal_error("Invalid register global variable type");
9076 bool is64Bit = isPPC64 && VT == MVT::i64;
9077 unsigned Reg = StringSwitch<unsigned>(RegName)
9078 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9079 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9080 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9081 (is64Bit ? PPC::X13 : PPC::R13))
9086 report_fatal_error("Invalid register name global variable");
9090 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9091 // The PowerPC target isn't yet aware of offsets.
9095 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9097 unsigned Intrinsic) const {
9099 switch (Intrinsic) {
9100 case Intrinsic::ppc_altivec_lvx:
9101 case Intrinsic::ppc_altivec_lvxl:
9102 case Intrinsic::ppc_altivec_lvebx:
9103 case Intrinsic::ppc_altivec_lvehx:
9104 case Intrinsic::ppc_altivec_lvewx:
9105 case Intrinsic::ppc_vsx_lxvd2x:
9106 case Intrinsic::ppc_vsx_lxvw4x: {
9108 switch (Intrinsic) {
9109 case Intrinsic::ppc_altivec_lvebx:
9112 case Intrinsic::ppc_altivec_lvehx:
9115 case Intrinsic::ppc_altivec_lvewx:
9118 case Intrinsic::ppc_vsx_lxvd2x:
9126 Info.opc = ISD::INTRINSIC_W_CHAIN;
9128 Info.ptrVal = I.getArgOperand(0);
9129 Info.offset = -VT.getStoreSize()+1;
9130 Info.size = 2*VT.getStoreSize()-1;
9133 Info.readMem = true;
9134 Info.writeMem = false;
9137 case Intrinsic::ppc_altivec_stvx:
9138 case Intrinsic::ppc_altivec_stvxl:
9139 case Intrinsic::ppc_altivec_stvebx:
9140 case Intrinsic::ppc_altivec_stvehx:
9141 case Intrinsic::ppc_altivec_stvewx:
9142 case Intrinsic::ppc_vsx_stxvd2x:
9143 case Intrinsic::ppc_vsx_stxvw4x: {
9145 switch (Intrinsic) {
9146 case Intrinsic::ppc_altivec_stvebx:
9149 case Intrinsic::ppc_altivec_stvehx:
9152 case Intrinsic::ppc_altivec_stvewx:
9155 case Intrinsic::ppc_vsx_stxvd2x:
9163 Info.opc = ISD::INTRINSIC_VOID;
9165 Info.ptrVal = I.getArgOperand(1);
9166 Info.offset = -VT.getStoreSize()+1;
9167 Info.size = 2*VT.getStoreSize()-1;
9170 Info.readMem = false;
9171 Info.writeMem = true;
9181 /// getOptimalMemOpType - Returns the target specific optimal type for load
9182 /// and store operations as a result of memset, memcpy, and memmove
9183 /// lowering. If DstAlign is zero that means it's safe to destination
9184 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9185 /// means there isn't a need to check it against alignment requirement,
9186 /// probably because the source does not need to be loaded. If 'IsMemset' is
9187 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9188 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9189 /// source is constant so it does not need to be loaded.
9190 /// It returns EVT::Other if the type should be determined using generic
9191 /// target-independent logic.
9192 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9193 unsigned DstAlign, unsigned SrcAlign,
9194 bool IsMemset, bool ZeroMemset,
9196 MachineFunction &MF) const {
9197 if (Subtarget.isPPC64()) {
9204 /// \brief Returns true if it is beneficial to convert a load of a constant
9205 /// to just the constant itself.
9206 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9208 assert(Ty->isIntegerTy());
9210 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9211 if (BitSize == 0 || BitSize > 64)
9216 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9217 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9219 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9220 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9221 return NumBits1 == 64 && NumBits2 == 32;
9224 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9225 if (!VT1.isInteger() || !VT2.isInteger())
9227 unsigned NumBits1 = VT1.getSizeInBits();
9228 unsigned NumBits2 = VT2.getSizeInBits();
9229 return NumBits1 == 64 && NumBits2 == 32;
9232 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9233 return isInt<16>(Imm) || isUInt<16>(Imm);
9236 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9237 return isInt<16>(Imm) || isUInt<16>(Imm);
9240 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9244 if (DisablePPCUnaligned)
9247 // PowerPC supports unaligned memory access for simple non-vector types.
9248 // Although accessing unaligned addresses is not as efficient as accessing
9249 // aligned addresses, it is generally more efficient than manual expansion,
9250 // and generally only traps for software emulation when crossing page
9256 if (VT.getSimpleVT().isVector()) {
9257 if (Subtarget.hasVSX()) {
9258 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9259 VT != MVT::v4f32 && VT != MVT::v4i32)
9266 if (VT == MVT::ppcf128)
9275 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9276 VT = VT.getScalarType();
9281 switch (VT.getSimpleVT().SimpleTy) {
9293 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9294 EVT VT , unsigned DefinedValues) const {
9295 if (VT == MVT::v2i64)
9298 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9301 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9302 if (DisableILPPref || Subtarget.enableMachineScheduler())
9303 return TargetLowering::getSchedulingPreference(N);
9308 // Create a fast isel object.
9310 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9311 const TargetLibraryInfo *LibInfo) const {
9312 return PPC::createFastISel(FuncInfo, LibInfo);