1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
24 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
25 : TargetLowering(TM) {
27 // Fold away setcc operations if possible.
28 setSetCCIsExpensive();
30 // Set up the register classes.
31 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
32 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
33 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
35 // PowerPC has no intrinsics for these particular operations
36 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
37 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
38 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
40 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
41 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
42 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
44 // PowerPC has no SREM/UREM instructions
45 setOperationAction(ISD::SREM, MVT::i32, Expand);
46 setOperationAction(ISD::UREM, MVT::i32, Expand);
48 // We don't support sin/cos/sqrt/fmod
49 setOperationAction(ISD::FSIN , MVT::f64, Expand);
50 setOperationAction(ISD::FCOS , MVT::f64, Expand);
51 setOperationAction(ISD::SREM , MVT::f64, Expand);
52 setOperationAction(ISD::FSIN , MVT::f32, Expand);
53 setOperationAction(ISD::FCOS , MVT::f32, Expand);
54 setOperationAction(ISD::SREM , MVT::f32, Expand);
56 // If we're enabling GP optimizations, use hardware square root
57 if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
58 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
59 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
62 // PowerPC does not have CTPOP or CTTZ
63 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
64 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
66 // PowerPC does not have Select
67 setOperationAction(ISD::SELECT, MVT::i32, Expand);
68 setOperationAction(ISD::SELECT, MVT::f32, Expand);
69 setOperationAction(ISD::SELECT, MVT::f64, Expand);
71 // PowerPC wants to turn select_cc of FP into fsel when possible.
72 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
73 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
75 // PowerPC does not have BRCOND* which requires SetCC
76 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
77 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
79 // PowerPC does not have FP_TO_UINT
80 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
82 // PowerPC does not have [U|S]INT_TO_FP
83 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
84 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
86 setSetCCResultContents(ZeroOrOneSetCCResult);
88 computeRegisterProperties();
91 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
92 static bool isFloatingPointZero(SDOperand Op) {
93 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
94 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
95 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
96 // Maybe this has already been legalized into the constant pool?
97 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
98 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
99 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
104 /// LowerOperation - Provide custom lowering hooks for some operations.
106 SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
107 switch (Op.getOpcode()) {
108 default: assert(0 && "Wasn't expecting to be able to lower this!");
110 // Turn FP only select_cc's into fsel instructions.
111 if (MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
112 MVT::isFloatingPoint(Op.getOperand(2).getValueType())) {
113 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
114 MVT::ValueType ResVT = Op.getValueType();
115 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
116 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
117 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
119 // If the RHS of the comparison is a 0.0, we don't need to do the
120 // subtraction at all.
121 if (isFloatingPointZero(RHS))
123 default: assert(0 && "Invalid FSEL condition"); abort();
126 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
129 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
132 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
135 return DAG.getNode(PPCISD::FSEL, ResVT,
136 DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
140 default: assert(0 && "Invalid FSEL condition"); abort();
143 return DAG.getNode(PPCISD::FSEL, ResVT,
144 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
147 return DAG.getNode(PPCISD::FSEL, ResVT,
148 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
151 return DAG.getNode(PPCISD::FSEL, ResVT,
152 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
155 return DAG.getNode(PPCISD::FSEL, ResVT,
156 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
164 std::vector<SDOperand>
165 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
167 // add beautiful description of PPC stack frame format, or at least some docs
169 MachineFunction &MF = DAG.getMachineFunction();
170 MachineFrameInfo *MFI = MF.getFrameInfo();
171 MachineBasicBlock& BB = MF.front();
172 std::vector<SDOperand> ArgValues;
174 // Due to the rather complicated nature of the PowerPC ABI, rather than a
175 // fixed size array of physical args, for the sake of simplicity let the STL
176 // handle tracking them for us.
177 std::vector<unsigned> argVR, argPR, argOp;
178 unsigned ArgOffset = 24;
179 unsigned GPR_remaining = 8;
180 unsigned FPR_remaining = 13;
181 unsigned GPR_idx = 0, FPR_idx = 0;
182 static const unsigned GPR[] = {
183 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
184 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
186 static const unsigned FPR[] = {
187 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
188 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
191 // Add DAG nodes to load the arguments... On entry to a function on PPC,
192 // the arguments start at offset 24, although they are likely to be passed
194 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
195 SDOperand newroot, argt;
197 bool needsLoad = false;
198 bool ArgLive = !I->use_empty();
199 MVT::ValueType ObjectVT = getValueType(I->getType());
202 default: assert(0 && "Unhandled argument type!");
209 if (GPR_remaining > 0) {
210 MF.addLiveIn(GPR[GPR_idx]);
211 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
212 GPR[GPR_idx], MVT::i32);
213 if (ObjectVT != MVT::i32)
214 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
219 case MVT::i64: ObjSize = 8;
221 if (GPR_remaining > 0) {
222 SDOperand argHi, argLo;
223 MF.addLiveIn(GPR[GPR_idx]);
224 argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
225 // If we have two or more remaining argument registers, then both halves
226 // of the i64 can be sourced from there. Otherwise, the lower half will
227 // have to come off the stack. This can happen when an i64 is preceded
228 // by 28 bytes of arguments.
229 if (GPR_remaining > 1) {
230 MF.addLiveIn(GPR[GPR_idx+1]);
231 argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
233 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
234 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
235 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
236 DAG.getSrcValue(NULL));
238 // Build the outgoing arg thingy
239 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
247 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
249 if (FPR_remaining > 0) {
250 MF.addLiveIn(FPR[FPR_idx]);
251 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
252 FPR[FPR_idx], ObjectVT);
261 // We need to load the argument to a virtual register if we determined above
262 // that we ran out of physical registers of the appropriate type
264 unsigned SubregOffset = 0;
265 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
266 if (ObjectVT == MVT::i16) SubregOffset = 2;
267 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
268 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
269 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
270 DAG.getConstant(SubregOffset, MVT::i32));
271 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
272 DAG.getSrcValue(NULL));
275 // Every 4 bytes of argument space consumes one of the GPRs available for
277 if (GPR_remaining > 0) {
278 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
279 GPR_remaining -= delta;
282 ArgOffset += ObjSize;
284 DAG.setRoot(newroot.getValue(1));
286 ArgValues.push_back(argt);
289 // If the function takes variable number of arguments, make a frame index for
290 // the start of the first vararg value... for expansion of llvm.va_start.
292 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
293 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
294 // If this function is vararg, store any remaining integer argument regs
295 // to their spots on the stack so that they may be loaded by deferencing the
296 // result of va_next.
297 std::vector<SDOperand> MemOps;
298 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
299 MF.addLiveIn(GPR[GPR_idx]);
300 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
301 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
302 Val, FIN, DAG.getSrcValue(NULL));
303 MemOps.push_back(Store);
304 // Increment the address by four for the next argument to store
305 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
306 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
308 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
311 // Finally, inform the code generator which regs we return values in.
312 switch (getValueType(F.getReturnType())) {
313 default: assert(0 && "Unknown type!");
314 case MVT::isVoid: break;
319 MF.addLiveOut(PPC::R3);
322 MF.addLiveOut(PPC::R3);
323 MF.addLiveOut(PPC::R4);
327 MF.addLiveOut(PPC::F1);
334 std::pair<SDOperand, SDOperand>
335 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
336 const Type *RetTy, bool isVarArg,
337 unsigned CallingConv, bool isTailCall,
338 SDOperand Callee, ArgListTy &Args,
340 // args_to_use will accumulate outgoing args for the ISD::CALL case in
341 // SelectExpr to use to put the arguments in the appropriate registers.
342 std::vector<SDOperand> args_to_use;
344 // Count how many bytes are to be pushed on the stack, including the linkage
345 // area, and parameter passing area.
346 unsigned NumBytes = 24;
349 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
350 DAG.getConstant(NumBytes, getPointerTy()));
352 for (unsigned i = 0, e = Args.size(); i != e; ++i)
353 switch (getValueType(Args[i].second)) {
354 default: assert(0 && "Unknown value type!");
368 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
369 // plus 32 bytes of argument space in case any called code gets funky on us.
370 // (Required by ABI to support var arg)
371 if (NumBytes < 56) NumBytes = 56;
373 // Adjust the stack pointer for the new arguments...
374 // These operations are automatically eliminated by the prolog/epilog pass
375 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
376 DAG.getConstant(NumBytes, getPointerTy()));
378 // Set up a copy of the stack pointer for use loading and storing any
379 // arguments that may not fit in the registers available for argument
381 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
384 // Figure out which arguments are going to go in registers, and which in
385 // memory. Also, if this is a vararg function, floating point operations
386 // must be stored to our stack, and loaded into integer regs as well, if
387 // any integer regs are available for argument passing.
388 unsigned ArgOffset = 24;
389 unsigned GPR_remaining = 8;
390 unsigned FPR_remaining = 13;
392 std::vector<SDOperand> MemOps;
393 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
394 // PtrOff will be used to store the current argument to the stack if a
395 // register cannot be found for it.
396 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
397 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
398 MVT::ValueType ArgVT = getValueType(Args[i].second);
401 default: assert(0 && "Unexpected ValueType for argument!");
405 // Promote the integer to 32 bits. If the input type is signed use a
406 // sign extend, otherwise use a zero extend.
407 if (Args[i].second->isSigned())
408 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
410 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
413 if (GPR_remaining > 0) {
414 args_to_use.push_back(Args[i].first);
417 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
418 Args[i].first, PtrOff,
419 DAG.getSrcValue(NULL)));
424 // If we have one free GPR left, we can place the upper half of the i64
425 // in it, and store the other half to the stack. If we have two or more
426 // free GPRs, then we can pass both halves of the i64 in registers.
427 if (GPR_remaining > 0) {
428 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
429 Args[i].first, DAG.getConstant(1, MVT::i32));
430 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
431 Args[i].first, DAG.getConstant(0, MVT::i32));
432 args_to_use.push_back(Hi);
434 if (GPR_remaining > 0) {
435 args_to_use.push_back(Lo);
438 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
439 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
440 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
441 Lo, PtrOff, DAG.getSrcValue(NULL)));
444 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
445 Args[i].first, PtrOff,
446 DAG.getSrcValue(NULL)));
452 if (FPR_remaining > 0) {
453 args_to_use.push_back(Args[i].first);
456 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
457 Args[i].first, PtrOff,
458 DAG.getSrcValue(NULL));
459 MemOps.push_back(Store);
460 // Float varargs are always shadowed in available integer registers
461 if (GPR_remaining > 0) {
462 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
463 DAG.getSrcValue(NULL));
464 MemOps.push_back(Load);
465 args_to_use.push_back(Load);
468 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
469 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
470 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
471 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
472 DAG.getSrcValue(NULL));
473 MemOps.push_back(Load);
474 args_to_use.push_back(Load);
478 // If we have any FPRs remaining, we may also have GPRs remaining.
479 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
481 if (GPR_remaining > 0) {
482 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
485 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
486 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
491 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
492 Args[i].first, PtrOff,
493 DAG.getSrcValue(NULL)));
495 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
500 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
503 std::vector<MVT::ValueType> RetVals;
504 MVT::ValueType RetTyVT = getValueType(RetTy);
505 if (RetTyVT != MVT::isVoid)
506 RetVals.push_back(RetTyVT);
507 RetVals.push_back(MVT::Other);
509 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
510 Chain, Callee, args_to_use), 0);
511 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
512 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
513 DAG.getConstant(NumBytes, getPointerTy()));
514 return std::make_pair(TheCall, Chain);
517 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
518 Value *VAListV, SelectionDAG &DAG) {
519 // vastart just stores the address of the VarArgsFrameIndex slot into the
520 // memory location argument.
521 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
522 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
523 DAG.getSrcValue(VAListV));
526 std::pair<SDOperand,SDOperand>
527 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
528 SDOperand VAListP, Value *VAListV,
529 const Type *ArgTy, SelectionDAG &DAG) {
530 MVT::ValueType ArgVT = getValueType(ArgTy);
533 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
534 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
536 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
539 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
540 "Other types should have been promoted for varargs!");
543 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
544 DAG.getConstant(Amt, VAList.getValueType()));
545 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
546 VAList, VAListP, DAG.getSrcValue(VAListV));
547 return std::make_pair(Result, Chain);
551 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
552 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
554 assert(0 && "LowerFrameReturnAddress unimplemented");
559 PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
560 MachineBasicBlock *BB) {
561 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
562 MI->getOpcode() == PPC::SELECT_CC_FP) &&
563 "Unexpected instr type to insert");
565 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
566 // control-flow pattern. The incoming instruction knows the destination vreg
567 // to set, the condition code register to branch on, the true/false values to
568 // select between, and a branch opcode to use.
569 const BasicBlock *LLVM_BB = BB->getBasicBlock();
570 ilist<MachineBasicBlock>::iterator It = BB;
578 // fallthrough --> copy0MBB
579 MachineBasicBlock *thisMBB = BB;
580 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
581 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
582 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
583 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
584 MachineFunction *F = BB->getParent();
585 F->getBasicBlockList().insert(It, copy0MBB);
586 F->getBasicBlockList().insert(It, sinkMBB);
587 // Update machine-CFG edges
588 BB->addSuccessor(copy0MBB);
589 BB->addSuccessor(sinkMBB);
593 // # fallthrough to sinkMBB
596 // Update machine-CFG edges
597 BB->addSuccessor(sinkMBB);
600 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
603 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
604 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
605 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
607 delete MI; // The pseudo instruction is gone now.