1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CallingConv.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/Constants.h"
29 #include "llvm/DerivedTypes.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/MathExtras.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetOptions.h"
39 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
40 CCValAssign::LocInfo &LocInfo,
41 ISD::ArgFlagsTy &ArgFlags,
43 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
45 CCValAssign::LocInfo &LocInfo,
46 ISD::ArgFlagsTy &ArgFlags,
48 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
50 CCValAssign::LocInfo &LocInfo,
51 ISD::ArgFlagsTy &ArgFlags,
54 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
55 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
57 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
58 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
64 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
69 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
73 // Use _setjmp/_longjmp instead of setjmp/longjmp.
74 setUseUnderscoreSetJmp(true);
75 setUseUnderscoreLongJmp(true);
77 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
78 // arguments are at least 4/8 bytes aligned.
79 bool isPPC64 = Subtarget->isPPC64();
80 setMinStackArgumentAlignment(isPPC64 ? 8:4);
82 // Set up the register classes.
83 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
84 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
85 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
87 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
88 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
91 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
93 // PowerPC has pre-inc load and store's.
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
102 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
105 // This is used in the ppcf128->int sequence. Note it has different semantics
106 // from FP_ROUND: that rounds to nearest, this rounds to zero.
107 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
109 // We do not currently implement these libm ops for PowerPC.
110 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
111 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
112 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
113 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
114 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
116 // PowerPC has no SREM/UREM instructions
117 setOperationAction(ISD::SREM, MVT::i32, Expand);
118 setOperationAction(ISD::UREM, MVT::i32, Expand);
119 setOperationAction(ISD::SREM, MVT::i64, Expand);
120 setOperationAction(ISD::UREM, MVT::i64, Expand);
122 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
123 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
124 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
125 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
126 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
127 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
128 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
129 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
130 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
132 // We don't support sin/cos/sqrt/fmod/pow
133 setOperationAction(ISD::FSIN , MVT::f64, Expand);
134 setOperationAction(ISD::FCOS , MVT::f64, Expand);
135 setOperationAction(ISD::FREM , MVT::f64, Expand);
136 setOperationAction(ISD::FPOW , MVT::f64, Expand);
137 setOperationAction(ISD::FMA , MVT::f64, Legal);
138 setOperationAction(ISD::FSIN , MVT::f32, Expand);
139 setOperationAction(ISD::FCOS , MVT::f32, Expand);
140 setOperationAction(ISD::FREM , MVT::f32, Expand);
141 setOperationAction(ISD::FPOW , MVT::f32, Expand);
142 setOperationAction(ISD::FMA , MVT::f32, Legal);
144 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
146 // If we're enabling GP optimizations, use hardware square root
147 if (!Subtarget->hasFSQRT()) {
148 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
149 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
153 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
155 // PowerPC does not have BSWAP, CTPOP or CTTZ
156 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
157 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
158 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
159 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
160 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
161 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
162 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
163 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
164 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
165 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
167 // PowerPC does not have ROTR
168 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
169 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
171 // PowerPC does not have Select
172 setOperationAction(ISD::SELECT, MVT::i32, Expand);
173 setOperationAction(ISD::SELECT, MVT::i64, Expand);
174 setOperationAction(ISD::SELECT, MVT::f32, Expand);
175 setOperationAction(ISD::SELECT, MVT::f64, Expand);
177 // PowerPC wants to turn select_cc of FP into fsel when possible.
178 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
179 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
181 // PowerPC wants to optimize integer setcc a bit
182 setOperationAction(ISD::SETCC, MVT::i32, Custom);
184 // PowerPC does not have BRCOND which requires SetCC
185 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
187 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
189 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
190 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
192 // PowerPC does not have [U|S]INT_TO_FP
193 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
194 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
196 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
197 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
198 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
199 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
201 // We cannot sextinreg(i1). Expand to shifts.
202 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
204 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
205 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
206 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
207 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
210 // We want to legalize GlobalAddress and ConstantPool nodes into the
211 // appropriate instructions to materialize the address.
212 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
213 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
214 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
215 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
216 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
217 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
218 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
219 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
220 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
221 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
224 setOperationAction(ISD::TRAP, MVT::Other, Legal);
226 // TRAMPOLINE is custom lowered.
227 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
228 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
230 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
231 setOperationAction(ISD::VASTART , MVT::Other, Custom);
233 if (Subtarget->isSVR4ABI()) {
235 // VAARG always uses double-word chunks, so promote anything smaller.
236 setOperationAction(ISD::VAARG, MVT::i1, Promote);
237 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
238 setOperationAction(ISD::VAARG, MVT::i8, Promote);
239 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
240 setOperationAction(ISD::VAARG, MVT::i16, Promote);
241 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
242 setOperationAction(ISD::VAARG, MVT::i32, Promote);
243 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
244 setOperationAction(ISD::VAARG, MVT::Other, Expand);
246 // VAARG is custom lowered with the 32-bit SVR4 ABI.
247 setOperationAction(ISD::VAARG, MVT::Other, Custom);
248 setOperationAction(ISD::VAARG, MVT::i64, Custom);
251 setOperationAction(ISD::VAARG, MVT::Other, Expand);
253 // Use the default implementation.
254 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
255 setOperationAction(ISD::VAEND , MVT::Other, Expand);
256 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
257 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
258 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
259 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
261 // We want to custom lower some of our intrinsics.
262 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
264 // Comparisons that require checking two conditions.
265 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
266 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
267 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
268 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
269 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
270 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
271 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
272 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
273 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
274 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
275 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
276 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
278 if (Subtarget->has64BitSupport()) {
279 // They also have instructions for converting between i64 and fp.
280 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
281 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
282 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
283 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
284 // This is just the low 32 bits of a (signed) fp->i64 conversion.
285 // We cannot do this with Promote because i64 is not a legal type.
286 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
288 // FIXME: disable this lowered code. This generates 64-bit register values,
289 // and we don't model the fact that the top part is clobbered by calls. We
290 // need to flag these together so that the value isn't live across a call.
291 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
293 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
294 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
297 if (Subtarget->use64BitRegs()) {
298 // 64-bit PowerPC implementations can support i64 types directly
299 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
300 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
301 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
302 // 64-bit PowerPC wants to expand i128 shifts itself.
303 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
304 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
305 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
307 // 32-bit PowerPC wants to expand i64 shifts itself.
308 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
309 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
310 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
313 if (Subtarget->hasAltivec()) {
314 // First set operation action for all vector types to expand. Then we
315 // will selectively turn on ones that can be effectively codegen'd.
316 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
317 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
318 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
320 // add/sub are legal for all supported vector VT's.
321 setOperationAction(ISD::ADD , VT, Legal);
322 setOperationAction(ISD::SUB , VT, Legal);
324 // We promote all shuffles to v16i8.
325 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
326 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
328 // We promote all non-typed operations to v4i32.
329 setOperationAction(ISD::AND , VT, Promote);
330 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
331 setOperationAction(ISD::OR , VT, Promote);
332 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
333 setOperationAction(ISD::XOR , VT, Promote);
334 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
335 setOperationAction(ISD::LOAD , VT, Promote);
336 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
337 setOperationAction(ISD::SELECT, VT, Promote);
338 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
339 setOperationAction(ISD::STORE, VT, Promote);
340 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
342 // No other operations are legal.
343 setOperationAction(ISD::MUL , VT, Expand);
344 setOperationAction(ISD::SDIV, VT, Expand);
345 setOperationAction(ISD::SREM, VT, Expand);
346 setOperationAction(ISD::UDIV, VT, Expand);
347 setOperationAction(ISD::UREM, VT, Expand);
348 setOperationAction(ISD::FDIV, VT, Expand);
349 setOperationAction(ISD::FNEG, VT, Expand);
350 setOperationAction(ISD::FSQRT, VT, Expand);
351 setOperationAction(ISD::FLOG, VT, Expand);
352 setOperationAction(ISD::FLOG10, VT, Expand);
353 setOperationAction(ISD::FLOG2, VT, Expand);
354 setOperationAction(ISD::FEXP, VT, Expand);
355 setOperationAction(ISD::FEXP2, VT, Expand);
356 setOperationAction(ISD::FSIN, VT, Expand);
357 setOperationAction(ISD::FCOS, VT, Expand);
358 setOperationAction(ISD::FABS, VT, Expand);
359 setOperationAction(ISD::FPOWI, VT, Expand);
360 setOperationAction(ISD::FFLOOR, VT, Expand);
361 setOperationAction(ISD::FCEIL, VT, Expand);
362 setOperationAction(ISD::FTRUNC, VT, Expand);
363 setOperationAction(ISD::FRINT, VT, Expand);
364 setOperationAction(ISD::FNEARBYINT, VT, Expand);
365 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
366 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
367 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
368 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
369 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
370 setOperationAction(ISD::UDIVREM, VT, Expand);
371 setOperationAction(ISD::SDIVREM, VT, Expand);
372 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
373 setOperationAction(ISD::FPOW, VT, Expand);
374 setOperationAction(ISD::CTPOP, VT, Expand);
375 setOperationAction(ISD::CTLZ, VT, Expand);
376 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
377 setOperationAction(ISD::CTTZ, VT, Expand);
378 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
379 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
381 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
382 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
383 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
384 setTruncStoreAction(VT, InnerVT, Expand);
386 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
387 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
388 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
391 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
392 // with merges, splats, etc.
393 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
395 setOperationAction(ISD::AND , MVT::v4i32, Legal);
396 setOperationAction(ISD::OR , MVT::v4i32, Legal);
397 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
398 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
399 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
400 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
401 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
402 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
403 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
404 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
405 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
406 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
407 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
408 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
410 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
411 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
412 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
413 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
415 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
416 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
417 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
418 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
419 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
421 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
422 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
424 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
425 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
426 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
427 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
429 // Altivec does not contain unordered floating-point compare instructions
430 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
431 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
432 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
433 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
434 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
435 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
438 if (Subtarget->has64BitSupport()) {
439 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
440 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
443 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
444 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
446 setBooleanContents(ZeroOrOneBooleanContent);
447 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
450 setStackPointerRegisterToSaveRestore(PPC::X1);
451 setExceptionPointerRegister(PPC::X3);
452 setExceptionSelectorRegister(PPC::X4);
454 setStackPointerRegisterToSaveRestore(PPC::R1);
455 setExceptionPointerRegister(PPC::R3);
456 setExceptionSelectorRegister(PPC::R4);
459 // We have target-specific dag combine patterns for the following nodes:
460 setTargetDAGCombine(ISD::SINT_TO_FP);
461 setTargetDAGCombine(ISD::STORE);
462 setTargetDAGCombine(ISD::BR_CC);
463 setTargetDAGCombine(ISD::BSWAP);
465 // Darwin long double math library functions have $LDBL128 appended.
466 if (Subtarget->isDarwin()) {
467 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
468 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
469 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
470 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
471 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
472 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
473 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
474 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
475 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
476 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
479 setMinFunctionAlignment(2);
480 if (PPCSubTarget.isDarwin())
481 setPrefFunctionAlignment(4);
483 if (isPPC64 && Subtarget->isJITCodeModel())
484 // Temporary workaround for the inability of PPC64 JIT to handle jump
486 setSupportJumpTables(false);
488 setInsertFencesForAtomic(true);
490 setSchedulingPreference(Sched::Hybrid);
492 computeRegisterProperties();
494 // The Freescale cores does better with aggressive inlining of memcpy and
495 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
496 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
497 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
498 maxStoresPerMemset = 32;
499 maxStoresPerMemsetOptSize = 16;
500 maxStoresPerMemcpy = 32;
501 maxStoresPerMemcpyOptSize = 8;
502 maxStoresPerMemmove = 32;
503 maxStoresPerMemmoveOptSize = 8;
505 setPrefFunctionAlignment(4);
506 benefitFromCodePlacementOpt = true;
510 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
511 /// function arguments in the caller parameter area.
512 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
513 const TargetMachine &TM = getTargetMachine();
514 // Darwin passes everything on 4 byte boundary.
515 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
518 // 16byte and wider vectors are passed on 16byte boundary.
519 if (VectorType *VTy = dyn_cast<VectorType>(Ty))
520 if (VTy->getBitWidth() >= 128)
523 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
524 if (PPCSubTarget.isPPC64())
530 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
533 case PPCISD::FSEL: return "PPCISD::FSEL";
534 case PPCISD::FCFID: return "PPCISD::FCFID";
535 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
536 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
537 case PPCISD::STFIWX: return "PPCISD::STFIWX";
538 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
539 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
540 case PPCISD::VPERM: return "PPCISD::VPERM";
541 case PPCISD::Hi: return "PPCISD::Hi";
542 case PPCISD::Lo: return "PPCISD::Lo";
543 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
544 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
545 case PPCISD::LOAD: return "PPCISD::LOAD";
546 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
547 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
548 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
549 case PPCISD::SRL: return "PPCISD::SRL";
550 case PPCISD::SRA: return "PPCISD::SRA";
551 case PPCISD::SHL: return "PPCISD::SHL";
552 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
553 case PPCISD::STD_32: return "PPCISD::STD_32";
554 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
555 case PPCISD::CALL_NOP_SVR4: return "PPCISD::CALL_NOP_SVR4";
556 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
557 case PPCISD::NOP: return "PPCISD::NOP";
558 case PPCISD::MTCTR: return "PPCISD::MTCTR";
559 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
560 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
561 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
562 case PPCISD::MFCR: return "PPCISD::MFCR";
563 case PPCISD::VCMP: return "PPCISD::VCMP";
564 case PPCISD::VCMPo: return "PPCISD::VCMPo";
565 case PPCISD::LBRX: return "PPCISD::LBRX";
566 case PPCISD::STBRX: return "PPCISD::STBRX";
567 case PPCISD::LARX: return "PPCISD::LARX";
568 case PPCISD::STCX: return "PPCISD::STCX";
569 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
570 case PPCISD::MFFS: return "PPCISD::MFFS";
571 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
572 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
573 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
574 case PPCISD::MTFSF: return "PPCISD::MTFSF";
575 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
576 case PPCISD::CR6SET: return "PPCISD::CR6SET";
577 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
578 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
579 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
580 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
581 case PPCISD::LD_GOT_TPREL: return "PPCISD::LD_GOT_TPREL";
582 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
583 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
584 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
585 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
589 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
592 return VT.changeVectorElementTypeToInteger();
595 //===----------------------------------------------------------------------===//
596 // Node matching predicates, for use by the tblgen matching code.
597 //===----------------------------------------------------------------------===//
599 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
600 static bool isFloatingPointZero(SDValue Op) {
601 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
602 return CFP->getValueAPF().isZero();
603 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
604 // Maybe this has already been legalized into the constant pool?
605 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
606 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
607 return CFP->getValueAPF().isZero();
612 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
613 /// true if Op is undef or if it matches the specified value.
614 static bool isConstantOrUndef(int Op, int Val) {
615 return Op < 0 || Op == Val;
618 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
619 /// VPKUHUM instruction.
620 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
622 for (unsigned i = 0; i != 16; ++i)
623 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
626 for (unsigned i = 0; i != 8; ++i)
627 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
628 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
634 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
635 /// VPKUWUM instruction.
636 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
638 for (unsigned i = 0; i != 16; i += 2)
639 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
640 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
643 for (unsigned i = 0; i != 8; i += 2)
644 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
645 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
646 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
647 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
653 /// isVMerge - Common function, used to match vmrg* shuffles.
655 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
656 unsigned LHSStart, unsigned RHSStart) {
657 assert(N->getValueType(0) == MVT::v16i8 &&
658 "PPC only supports shuffles by bytes!");
659 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
660 "Unsupported merge size!");
662 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
663 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
664 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
665 LHSStart+j+i*UnitSize) ||
666 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
667 RHSStart+j+i*UnitSize))
673 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
674 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
675 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
678 return isVMerge(N, UnitSize, 8, 24);
679 return isVMerge(N, UnitSize, 8, 8);
682 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
683 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
684 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
687 return isVMerge(N, UnitSize, 0, 16);
688 return isVMerge(N, UnitSize, 0, 0);
692 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
693 /// amount, otherwise return -1.
694 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
695 assert(N->getValueType(0) == MVT::v16i8 &&
696 "PPC only supports shuffles by bytes!");
698 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
700 // Find the first non-undef value in the shuffle mask.
702 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
705 if (i == 16) return -1; // all undef.
707 // Otherwise, check to see if the rest of the elements are consecutively
708 // numbered from this value.
709 unsigned ShiftAmt = SVOp->getMaskElt(i);
710 if (ShiftAmt < i) return -1;
714 // Check the rest of the elements to see if they are consecutive.
715 for (++i; i != 16; ++i)
716 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
719 // Check the rest of the elements to see if they are consecutive.
720 for (++i; i != 16; ++i)
721 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
727 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
728 /// specifies a splat of a single element that is suitable for input to
729 /// VSPLTB/VSPLTH/VSPLTW.
730 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
731 assert(N->getValueType(0) == MVT::v16i8 &&
732 (EltSize == 1 || EltSize == 2 || EltSize == 4));
734 // This is a splat operation if each element of the permute is the same, and
735 // if the value doesn't reference the second vector.
736 unsigned ElementBase = N->getMaskElt(0);
738 // FIXME: Handle UNDEF elements too!
739 if (ElementBase >= 16)
742 // Check that the indices are consecutive, in the case of a multi-byte element
743 // splatted with a v16i8 mask.
744 for (unsigned i = 1; i != EltSize; ++i)
745 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
748 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
749 if (N->getMaskElt(i) < 0) continue;
750 for (unsigned j = 0; j != EltSize; ++j)
751 if (N->getMaskElt(i+j) != N->getMaskElt(j))
757 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
759 bool PPC::isAllNegativeZeroVector(SDNode *N) {
760 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
762 APInt APVal, APUndef;
766 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
767 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
768 return CFP->getValueAPF().isNegZero();
773 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
774 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
775 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
776 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
777 assert(isSplatShuffleMask(SVOp, EltSize));
778 return SVOp->getMaskElt(0) / EltSize;
781 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
782 /// by using a vspltis[bhw] instruction of the specified element size, return
783 /// the constant being splatted. The ByteSize field indicates the number of
784 /// bytes of each element [124] -> [bhw].
785 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
788 // If ByteSize of the splat is bigger than the element size of the
789 // build_vector, then we have a case where we are checking for a splat where
790 // multiple elements of the buildvector are folded together into a single
791 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
792 unsigned EltSize = 16/N->getNumOperands();
793 if (EltSize < ByteSize) {
794 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
795 SDValue UniquedVals[4];
796 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
798 // See if all of the elements in the buildvector agree across.
799 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
800 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
801 // If the element isn't a constant, bail fully out.
802 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
805 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
806 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
807 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
808 return SDValue(); // no match.
811 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
812 // either constant or undef values that are identical for each chunk. See
813 // if these chunks can form into a larger vspltis*.
815 // Check to see if all of the leading entries are either 0 or -1. If
816 // neither, then this won't fit into the immediate field.
817 bool LeadingZero = true;
818 bool LeadingOnes = true;
819 for (unsigned i = 0; i != Multiple-1; ++i) {
820 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
822 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
823 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
825 // Finally, check the least significant entry.
827 if (UniquedVals[Multiple-1].getNode() == 0)
828 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
829 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
831 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
834 if (UniquedVals[Multiple-1].getNode() == 0)
835 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
836 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
837 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
838 return DAG.getTargetConstant(Val, MVT::i32);
844 // Check to see if this buildvec has a single non-undef value in its elements.
845 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
846 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
847 if (OpVal.getNode() == 0)
848 OpVal = N->getOperand(i);
849 else if (OpVal != N->getOperand(i))
853 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
855 unsigned ValSizeInBytes = EltSize;
857 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
858 Value = CN->getZExtValue();
859 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
860 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
861 Value = FloatToBits(CN->getValueAPF().convertToFloat());
864 // If the splat value is larger than the element value, then we can never do
865 // this splat. The only case that we could fit the replicated bits into our
866 // immediate field for would be zero, and we prefer to use vxor for it.
867 if (ValSizeInBytes < ByteSize) return SDValue();
869 // If the element value is larger than the splat value, cut it in half and
870 // check to see if the two halves are equal. Continue doing this until we
871 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
872 while (ValSizeInBytes > ByteSize) {
873 ValSizeInBytes >>= 1;
875 // If the top half equals the bottom half, we're still ok.
876 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
877 (Value & ((1 << (8*ValSizeInBytes))-1)))
881 // Properly sign extend the value.
882 int MaskVal = SignExtend32(Value, ByteSize * 8);
884 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
885 if (MaskVal == 0) return SDValue();
887 // Finally, if this value fits in a 5 bit sext field, return it
888 if (SignExtend32<5>(MaskVal) == MaskVal)
889 return DAG.getTargetConstant(MaskVal, MVT::i32);
893 //===----------------------------------------------------------------------===//
894 // Addressing Mode Selection
895 //===----------------------------------------------------------------------===//
897 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
898 /// or 64-bit immediate, and if the value can be accurately represented as a
899 /// sign extension from a 16-bit value. If so, this returns true and the
901 static bool isIntS16Immediate(SDNode *N, short &Imm) {
902 if (N->getOpcode() != ISD::Constant)
905 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
906 if (N->getValueType(0) == MVT::i32)
907 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
909 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
911 static bool isIntS16Immediate(SDValue Op, short &Imm) {
912 return isIntS16Immediate(Op.getNode(), Imm);
916 /// SelectAddressRegReg - Given the specified addressed, check to see if it
917 /// can be represented as an indexed [r+r] operation. Returns false if it
918 /// can be more efficiently represented with [r+imm].
919 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
921 SelectionDAG &DAG) const {
923 if (N.getOpcode() == ISD::ADD) {
924 if (isIntS16Immediate(N.getOperand(1), imm))
926 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
929 Base = N.getOperand(0);
930 Index = N.getOperand(1);
932 } else if (N.getOpcode() == ISD::OR) {
933 if (isIntS16Immediate(N.getOperand(1), imm))
934 return false; // r+i can fold it if we can.
936 // If this is an or of disjoint bitfields, we can codegen this as an add
937 // (for better address arithmetic) if the LHS and RHS of the OR are provably
939 APInt LHSKnownZero, LHSKnownOne;
940 APInt RHSKnownZero, RHSKnownOne;
941 DAG.ComputeMaskedBits(N.getOperand(0),
942 LHSKnownZero, LHSKnownOne);
944 if (LHSKnownZero.getBoolValue()) {
945 DAG.ComputeMaskedBits(N.getOperand(1),
946 RHSKnownZero, RHSKnownOne);
947 // If all of the bits are known zero on the LHS or RHS, the add won't
949 if (~(LHSKnownZero | RHSKnownZero) == 0) {
950 Base = N.getOperand(0);
951 Index = N.getOperand(1);
960 /// Returns true if the address N can be represented by a base register plus
961 /// a signed 16-bit displacement [r+imm], and if it is not better
962 /// represented as reg+reg.
963 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
965 SelectionDAG &DAG) const {
966 // FIXME dl should come from parent load or store, not from address
967 DebugLoc dl = N.getDebugLoc();
968 // If this can be more profitably realized as r+r, fail.
969 if (SelectAddressRegReg(N, Disp, Base, DAG))
972 if (N.getOpcode() == ISD::ADD) {
974 if (isIntS16Immediate(N.getOperand(1), imm)) {
975 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
976 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
977 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
979 Base = N.getOperand(0);
981 return true; // [r+i]
982 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
983 // Match LOAD (ADD (X, Lo(G))).
984 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
985 && "Cannot handle constant offsets yet!");
986 Disp = N.getOperand(1).getOperand(0); // The global address.
987 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
988 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
989 Disp.getOpcode() == ISD::TargetConstantPool ||
990 Disp.getOpcode() == ISD::TargetJumpTable);
991 Base = N.getOperand(0);
992 return true; // [&g+r]
994 } else if (N.getOpcode() == ISD::OR) {
996 if (isIntS16Immediate(N.getOperand(1), imm)) {
997 // If this is an or of disjoint bitfields, we can codegen this as an add
998 // (for better address arithmetic) if the LHS and RHS of the OR are
999 // provably disjoint.
1000 APInt LHSKnownZero, LHSKnownOne;
1001 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1003 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1004 // If all of the bits are known zero on the LHS or RHS, the add won't
1006 Base = N.getOperand(0);
1007 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
1011 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1012 // Loading from a constant address.
1014 // If this address fits entirely in a 16-bit sext immediate field, codegen
1017 if (isIntS16Immediate(CN, Imm)) {
1018 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1019 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1020 CN->getValueType(0));
1024 // Handle 32-bit sext immediates with LIS + addr mode.
1025 if (CN->getValueType(0) == MVT::i32 ||
1026 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1027 int Addr = (int)CN->getZExtValue();
1029 // Otherwise, break this down into an LIS + disp.
1030 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1032 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1033 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1034 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1039 Disp = DAG.getTargetConstant(0, getPointerTy());
1040 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1041 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1044 return true; // [r+0]
1047 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1048 /// represented as an indexed [r+r] operation.
1049 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1051 SelectionDAG &DAG) const {
1052 // Check to see if we can easily represent this as an [r+r] address. This
1053 // will fail if it thinks that the address is more profitably represented as
1054 // reg+imm, e.g. where imm = 0.
1055 if (SelectAddressRegReg(N, Base, Index, DAG))
1058 // If the operand is an addition, always emit this as [r+r], since this is
1059 // better (for code size, and execution, as the memop does the add for free)
1060 // than emitting an explicit add.
1061 if (N.getOpcode() == ISD::ADD) {
1062 Base = N.getOperand(0);
1063 Index = N.getOperand(1);
1067 // Otherwise, do it the hard way, using R0 as the base register.
1068 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1074 /// SelectAddressRegImmShift - Returns true if the address N can be
1075 /// represented by a base register plus a signed 14-bit displacement
1076 /// [r+imm*4]. Suitable for use by STD and friends.
1077 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
1079 SelectionDAG &DAG) const {
1080 // FIXME dl should come from the parent load or store, not the address
1081 DebugLoc dl = N.getDebugLoc();
1082 // If this can be more profitably realized as r+r, fail.
1083 if (SelectAddressRegReg(N, Disp, Base, DAG))
1086 if (N.getOpcode() == ISD::ADD) {
1088 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1089 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1090 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1091 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1093 Base = N.getOperand(0);
1095 return true; // [r+i]
1096 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1097 // Match LOAD (ADD (X, Lo(G))).
1098 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1099 && "Cannot handle constant offsets yet!");
1100 Disp = N.getOperand(1).getOperand(0); // The global address.
1101 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1102 Disp.getOpcode() == ISD::TargetConstantPool ||
1103 Disp.getOpcode() == ISD::TargetJumpTable);
1104 Base = N.getOperand(0);
1105 return true; // [&g+r]
1107 } else if (N.getOpcode() == ISD::OR) {
1109 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1110 // If this is an or of disjoint bitfields, we can codegen this as an add
1111 // (for better address arithmetic) if the LHS and RHS of the OR are
1112 // provably disjoint.
1113 APInt LHSKnownZero, LHSKnownOne;
1114 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1115 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1116 // If all of the bits are known zero on the LHS or RHS, the add won't
1118 Base = N.getOperand(0);
1119 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1123 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1124 // Loading from a constant address. Verify low two bits are clear.
1125 if ((CN->getZExtValue() & 3) == 0) {
1126 // If this address fits entirely in a 14-bit sext immediate field, codegen
1129 if (isIntS16Immediate(CN, Imm)) {
1130 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1131 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1132 CN->getValueType(0));
1136 // Fold the low-part of 32-bit absolute addresses into addr mode.
1137 if (CN->getValueType(0) == MVT::i32 ||
1138 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1139 int Addr = (int)CN->getZExtValue();
1141 // Otherwise, break this down into an LIS + disp.
1142 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1143 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1144 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1145 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1151 Disp = DAG.getTargetConstant(0, getPointerTy());
1152 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1153 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1156 return true; // [r+0]
1160 /// getPreIndexedAddressParts - returns true by value, base pointer and
1161 /// offset pointer and addressing mode by reference if the node's address
1162 /// can be legally represented as pre-indexed load / store address.
1163 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1165 ISD::MemIndexedMode &AM,
1166 SelectionDAG &DAG) const {
1167 if (DisablePPCPreinc) return false;
1171 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1172 Ptr = LD->getBasePtr();
1173 VT = LD->getMemoryVT();
1175 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1176 Ptr = ST->getBasePtr();
1177 VT = ST->getMemoryVT();
1181 // PowerPC doesn't have preinc load/store instructions for vectors.
1185 if (SelectAddressRegReg(Ptr, Offset, Base, DAG)) {
1190 // LDU/STU use reg+imm*4, others use reg+imm.
1191 if (VT != MVT::i64) {
1193 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1197 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1201 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1202 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1203 // sext i32 to i64 when addr mode is r+i.
1204 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1205 LD->getExtensionType() == ISD::SEXTLOAD &&
1206 isa<ConstantSDNode>(Offset))
1214 //===----------------------------------------------------------------------===//
1215 // LowerOperation implementation
1216 //===----------------------------------------------------------------------===//
1218 /// GetLabelAccessInfo - Return true if we should reference labels using a
1219 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1220 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1221 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1222 HiOpFlags = PPCII::MO_HA16;
1223 LoOpFlags = PPCII::MO_LO16;
1225 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1226 // non-darwin platform. We don't support PIC on other platforms yet.
1227 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1228 TM.getSubtarget<PPCSubtarget>().isDarwin();
1230 HiOpFlags |= PPCII::MO_PIC_FLAG;
1231 LoOpFlags |= PPCII::MO_PIC_FLAG;
1234 // If this is a reference to a global value that requires a non-lazy-ptr, make
1235 // sure that instruction lowering adds it.
1236 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1237 HiOpFlags |= PPCII::MO_NLP_FLAG;
1238 LoOpFlags |= PPCII::MO_NLP_FLAG;
1240 if (GV->hasHiddenVisibility()) {
1241 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1242 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1249 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1250 SelectionDAG &DAG) {
1251 EVT PtrVT = HiPart.getValueType();
1252 SDValue Zero = DAG.getConstant(0, PtrVT);
1253 DebugLoc DL = HiPart.getDebugLoc();
1255 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1256 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1258 // With PIC, the first instruction is actually "GR+hi(&G)".
1260 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1261 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1263 // Generate non-pic code that has direct accesses to the constant pool.
1264 // The address of the global is just (hi(&g)+lo(&g)).
1265 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1268 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1269 SelectionDAG &DAG) const {
1270 EVT PtrVT = Op.getValueType();
1271 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1272 const Constant *C = CP->getConstVal();
1274 // 64-bit SVR4 ABI code is always position-independent.
1275 // The actual address of the GlobalValue is stored in the TOC.
1276 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1277 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1278 return DAG.getNode(PPCISD::TOC_ENTRY, CP->getDebugLoc(), MVT::i64, GA,
1279 DAG.getRegister(PPC::X2, MVT::i64));
1282 unsigned MOHiFlag, MOLoFlag;
1283 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1285 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1287 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1288 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1291 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1292 EVT PtrVT = Op.getValueType();
1293 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1295 // 64-bit SVR4 ABI code is always position-independent.
1296 // The actual address of the GlobalValue is stored in the TOC.
1297 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1298 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1299 return DAG.getNode(PPCISD::TOC_ENTRY, JT->getDebugLoc(), MVT::i64, GA,
1300 DAG.getRegister(PPC::X2, MVT::i64));
1303 unsigned MOHiFlag, MOLoFlag;
1304 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1305 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1306 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1307 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1310 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1311 SelectionDAG &DAG) const {
1312 EVT PtrVT = Op.getValueType();
1314 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1316 unsigned MOHiFlag, MOLoFlag;
1317 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1318 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1319 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1320 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1323 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1324 SelectionDAG &DAG) const {
1326 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1327 DebugLoc dl = GA->getDebugLoc();
1328 const GlobalValue *GV = GA->getGlobal();
1329 EVT PtrVT = getPointerTy();
1330 bool is64bit = PPCSubTarget.isPPC64();
1332 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1334 if (Model == TLSModel::LocalExec) {
1335 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1336 PPCII::MO_TPREL16_HA);
1337 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1338 PPCII::MO_TPREL16_LO);
1339 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1340 is64bit ? MVT::i64 : MVT::i32);
1341 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1342 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1346 llvm_unreachable("only local-exec is currently supported for ppc32");
1348 if (Model == TLSModel::InitialExec) {
1349 SDValue GOTOffset = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1350 PPCII::MO_GOT_TPREL16_DS);
1351 SDValue TPReg = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1353 SDValue GOTReg = DAG.getRegister(is64bit ? PPC::X2 : PPC::R2,
1354 is64bit ? MVT::i64 : MVT::i32);
1355 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL, dl, PtrVT,
1357 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TPReg);
1360 if (Model == TLSModel::GeneralDynamic) {
1361 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1362 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1363 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1365 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1368 // We need a chain node, and don't have one handy. The underlying
1369 // call has no side effects, so using the function entry node
1371 SDValue Chain = DAG.getEntryNode();
1372 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1373 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1374 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1375 PtrVT, ParmReg, TGA);
1376 // The call to GET_TLS_ADDR really is in X3 already, but
1377 // some hacks are needed here to tie everything together.
1378 // The extra copies dissolve during subsequent transforms.
1379 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1380 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1383 llvm_unreachable("local-dynamic TLS mode is not yet supported");
1386 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1387 SelectionDAG &DAG) const {
1388 EVT PtrVT = Op.getValueType();
1389 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1390 DebugLoc DL = GSDN->getDebugLoc();
1391 const GlobalValue *GV = GSDN->getGlobal();
1393 // 64-bit SVR4 ABI code is always position-independent.
1394 // The actual address of the GlobalValue is stored in the TOC.
1395 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1396 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1397 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1398 DAG.getRegister(PPC::X2, MVT::i64));
1401 unsigned MOHiFlag, MOLoFlag;
1402 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1405 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1407 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1409 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1411 // If the global reference is actually to a non-lazy-pointer, we have to do an
1412 // extra load to get the address of the global.
1413 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1414 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1415 false, false, false, 0);
1419 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1420 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1421 DebugLoc dl = Op.getDebugLoc();
1423 // If we're comparing for equality to zero, expose the fact that this is
1424 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1425 // fold the new nodes.
1426 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1427 if (C->isNullValue() && CC == ISD::SETEQ) {
1428 EVT VT = Op.getOperand(0).getValueType();
1429 SDValue Zext = Op.getOperand(0);
1430 if (VT.bitsLT(MVT::i32)) {
1432 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1434 unsigned Log2b = Log2_32(VT.getSizeInBits());
1435 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1436 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1437 DAG.getConstant(Log2b, MVT::i32));
1438 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1440 // Leave comparisons against 0 and -1 alone for now, since they're usually
1441 // optimized. FIXME: revisit this when we can custom lower all setcc
1443 if (C->isAllOnesValue() || C->isNullValue())
1447 // If we have an integer seteq/setne, turn it into a compare against zero
1448 // by xor'ing the rhs with the lhs, which is faster than setting a
1449 // condition register, reading it back out, and masking the correct bit. The
1450 // normal approach here uses sub to do this instead of xor. Using xor exposes
1451 // the result to other bit-twiddling opportunities.
1452 EVT LHSVT = Op.getOperand(0).getValueType();
1453 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1454 EVT VT = Op.getValueType();
1455 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1457 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1462 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1463 const PPCSubtarget &Subtarget) const {
1464 SDNode *Node = Op.getNode();
1465 EVT VT = Node->getValueType(0);
1466 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1467 SDValue InChain = Node->getOperand(0);
1468 SDValue VAListPtr = Node->getOperand(1);
1469 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1470 DebugLoc dl = Node->getDebugLoc();
1472 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1475 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1476 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1478 InChain = GprIndex.getValue(1);
1480 if (VT == MVT::i64) {
1481 // Check if GprIndex is even
1482 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1483 DAG.getConstant(1, MVT::i32));
1484 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1485 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1486 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1487 DAG.getConstant(1, MVT::i32));
1488 // Align GprIndex to be even if it isn't
1489 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1493 // fpr index is 1 byte after gpr
1494 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1495 DAG.getConstant(1, MVT::i32));
1498 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1499 FprPtr, MachinePointerInfo(SV), MVT::i8,
1501 InChain = FprIndex.getValue(1);
1503 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1504 DAG.getConstant(8, MVT::i32));
1506 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1507 DAG.getConstant(4, MVT::i32));
1510 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1511 MachinePointerInfo(), false, false,
1513 InChain = OverflowArea.getValue(1);
1515 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1516 MachinePointerInfo(), false, false,
1518 InChain = RegSaveArea.getValue(1);
1520 // select overflow_area if index > 8
1521 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1522 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1524 // adjustment constant gpr_index * 4/8
1525 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1526 VT.isInteger() ? GprIndex : FprIndex,
1527 DAG.getConstant(VT.isInteger() ? 4 : 8,
1530 // OurReg = RegSaveArea + RegConstant
1531 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1534 // Floating types are 32 bytes into RegSaveArea
1535 if (VT.isFloatingPoint())
1536 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1537 DAG.getConstant(32, MVT::i32));
1539 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1540 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1541 VT.isInteger() ? GprIndex : FprIndex,
1542 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1545 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1546 VT.isInteger() ? VAListPtr : FprPtr,
1547 MachinePointerInfo(SV),
1548 MVT::i8, false, false, 0);
1550 // determine if we should load from reg_save_area or overflow_area
1551 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1553 // increase overflow_area by 4/8 if gpr/fpr > 8
1554 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1555 DAG.getConstant(VT.isInteger() ? 4 : 8,
1558 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1561 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1563 MachinePointerInfo(),
1564 MVT::i32, false, false, 0);
1566 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1567 false, false, false, 0);
1570 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1571 SelectionDAG &DAG) const {
1572 return Op.getOperand(0);
1575 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1576 SelectionDAG &DAG) const {
1577 SDValue Chain = Op.getOperand(0);
1578 SDValue Trmp = Op.getOperand(1); // trampoline
1579 SDValue FPtr = Op.getOperand(2); // nested function
1580 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1581 DebugLoc dl = Op.getDebugLoc();
1583 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1584 bool isPPC64 = (PtrVT == MVT::i64);
1586 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1589 TargetLowering::ArgListTy Args;
1590 TargetLowering::ArgListEntry Entry;
1592 Entry.Ty = IntPtrTy;
1593 Entry.Node = Trmp; Args.push_back(Entry);
1595 // TrampSize == (isPPC64 ? 48 : 40);
1596 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1597 isPPC64 ? MVT::i64 : MVT::i32);
1598 Args.push_back(Entry);
1600 Entry.Node = FPtr; Args.push_back(Entry);
1601 Entry.Node = Nest; Args.push_back(Entry);
1603 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1604 TargetLowering::CallLoweringInfo CLI(Chain,
1605 Type::getVoidTy(*DAG.getContext()),
1606 false, false, false, false, 0,
1608 /*isTailCall=*/false,
1609 /*doesNotRet=*/false,
1610 /*isReturnValueUsed=*/true,
1611 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1613 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1615 return CallResult.second;
1618 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1619 const PPCSubtarget &Subtarget) const {
1620 MachineFunction &MF = DAG.getMachineFunction();
1621 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1623 DebugLoc dl = Op.getDebugLoc();
1625 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1626 // vastart just stores the address of the VarArgsFrameIndex slot into the
1627 // memory location argument.
1628 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1629 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1630 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1631 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1632 MachinePointerInfo(SV),
1636 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1637 // We suppose the given va_list is already allocated.
1640 // char gpr; /* index into the array of 8 GPRs
1641 // * stored in the register save area
1642 // * gpr=0 corresponds to r3,
1643 // * gpr=1 to r4, etc.
1645 // char fpr; /* index into the array of 8 FPRs
1646 // * stored in the register save area
1647 // * fpr=0 corresponds to f1,
1648 // * fpr=1 to f2, etc.
1650 // char *overflow_arg_area;
1651 // /* location on stack that holds
1652 // * the next overflow argument
1654 // char *reg_save_area;
1655 // /* where r3:r10 and f1:f8 (if saved)
1661 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1662 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1665 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1667 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1669 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1672 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1673 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1675 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1676 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1678 uint64_t FPROffset = 1;
1679 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1681 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1683 // Store first byte : number of int regs
1684 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1686 MachinePointerInfo(SV),
1687 MVT::i8, false, false, 0);
1688 uint64_t nextOffset = FPROffset;
1689 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1692 // Store second byte : number of float regs
1693 SDValue secondStore =
1694 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1695 MachinePointerInfo(SV, nextOffset), MVT::i8,
1697 nextOffset += StackOffset;
1698 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1700 // Store second word : arguments given on stack
1701 SDValue thirdStore =
1702 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1703 MachinePointerInfo(SV, nextOffset),
1705 nextOffset += FrameOffset;
1706 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1708 // Store third word : arguments given in registers
1709 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1710 MachinePointerInfo(SV, nextOffset),
1715 #include "PPCGenCallingConv.inc"
1717 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1718 CCValAssign::LocInfo &LocInfo,
1719 ISD::ArgFlagsTy &ArgFlags,
1724 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1726 CCValAssign::LocInfo &LocInfo,
1727 ISD::ArgFlagsTy &ArgFlags,
1729 static const uint16_t ArgRegs[] = {
1730 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1731 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1733 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1735 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1737 // Skip one register if the first unallocated register has an even register
1738 // number and there are still argument registers available which have not been
1739 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1740 // need to skip a register if RegNum is odd.
1741 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1742 State.AllocateReg(ArgRegs[RegNum]);
1745 // Always return false here, as this function only makes sure that the first
1746 // unallocated register has an odd register number and does not actually
1747 // allocate a register for the current argument.
1751 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1753 CCValAssign::LocInfo &LocInfo,
1754 ISD::ArgFlagsTy &ArgFlags,
1756 static const uint16_t ArgRegs[] = {
1757 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1761 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1763 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1765 // If there is only one Floating-point register left we need to put both f64
1766 // values of a split ppc_fp128 value on the stack.
1767 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1768 State.AllocateReg(ArgRegs[RegNum]);
1771 // Always return false here, as this function only makes sure that the two f64
1772 // values a ppc_fp128 value is split into are both passed in registers or both
1773 // passed on the stack and does not actually allocate a register for the
1774 // current argument.
1778 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1780 static const uint16_t *GetFPR() {
1781 static const uint16_t FPR[] = {
1782 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1783 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1789 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1791 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1792 unsigned PtrByteSize) {
1793 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1794 if (Flags.isByVal())
1795 ArgSize = Flags.getByValSize();
1796 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1802 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1803 CallingConv::ID CallConv, bool isVarArg,
1804 const SmallVectorImpl<ISD::InputArg>
1806 DebugLoc dl, SelectionDAG &DAG,
1807 SmallVectorImpl<SDValue> &InVals)
1809 if (PPCSubTarget.isSVR4ABI()) {
1810 if (PPCSubTarget.isPPC64())
1811 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1814 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1817 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1823 PPCTargetLowering::LowerFormalArguments_32SVR4(
1825 CallingConv::ID CallConv, bool isVarArg,
1826 const SmallVectorImpl<ISD::InputArg>
1828 DebugLoc dl, SelectionDAG &DAG,
1829 SmallVectorImpl<SDValue> &InVals) const {
1831 // 32-bit SVR4 ABI Stack Frame Layout:
1832 // +-----------------------------------+
1833 // +--> | Back chain |
1834 // | +-----------------------------------+
1835 // | | Floating-point register save area |
1836 // | +-----------------------------------+
1837 // | | General register save area |
1838 // | +-----------------------------------+
1839 // | | CR save word |
1840 // | +-----------------------------------+
1841 // | | VRSAVE save word |
1842 // | +-----------------------------------+
1843 // | | Alignment padding |
1844 // | +-----------------------------------+
1845 // | | Vector register save area |
1846 // | +-----------------------------------+
1847 // | | Local variable space |
1848 // | +-----------------------------------+
1849 // | | Parameter list area |
1850 // | +-----------------------------------+
1851 // | | LR save word |
1852 // | +-----------------------------------+
1853 // SP--> +--- | Back chain |
1854 // +-----------------------------------+
1857 // System V Application Binary Interface PowerPC Processor Supplement
1858 // AltiVec Technology Programming Interface Manual
1860 MachineFunction &MF = DAG.getMachineFunction();
1861 MachineFrameInfo *MFI = MF.getFrameInfo();
1862 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1864 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1865 // Potential tail calls could cause overwriting of argument stack slots.
1866 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1867 (CallConv == CallingConv::Fast));
1868 unsigned PtrByteSize = 4;
1870 // Assign locations to all of the incoming arguments.
1871 SmallVector<CCValAssign, 16> ArgLocs;
1872 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1873 getTargetMachine(), ArgLocs, *DAG.getContext());
1875 // Reserve space for the linkage area on the stack.
1876 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1878 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1880 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1881 CCValAssign &VA = ArgLocs[i];
1883 // Arguments stored in registers.
1884 if (VA.isRegLoc()) {
1885 const TargetRegisterClass *RC;
1886 EVT ValVT = VA.getValVT();
1888 switch (ValVT.getSimpleVT().SimpleTy) {
1890 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1892 RC = &PPC::GPRCRegClass;
1895 RC = &PPC::F4RCRegClass;
1898 RC = &PPC::F8RCRegClass;
1904 RC = &PPC::VRRCRegClass;
1908 // Transform the arguments stored in physical registers into virtual ones.
1909 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1910 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1912 InVals.push_back(ArgValue);
1914 // Argument stored in memory.
1915 assert(VA.isMemLoc());
1917 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1918 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1921 // Create load nodes to retrieve arguments from the stack.
1922 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1923 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1924 MachinePointerInfo(),
1925 false, false, false, 0));
1929 // Assign locations to all of the incoming aggregate by value arguments.
1930 // Aggregates passed by value are stored in the local variable space of the
1931 // caller's stack frame, right above the parameter list area.
1932 SmallVector<CCValAssign, 16> ByValArgLocs;
1933 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1934 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1936 // Reserve stack space for the allocations in CCInfo.
1937 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1939 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1941 // Area that is at least reserved in the caller of this function.
1942 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1944 // Set the size that is at least reserved in caller of this function. Tail
1945 // call optimized function's reserved stack space needs to be aligned so that
1946 // taking the difference between two stack areas will result in an aligned
1948 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1951 std::max(MinReservedArea,
1952 PPCFrameLowering::getMinCallFrameSize(false, false));
1954 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1955 getStackAlignment();
1956 unsigned AlignMask = TargetAlign-1;
1957 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1959 FI->setMinReservedArea(MinReservedArea);
1961 SmallVector<SDValue, 8> MemOps;
1963 // If the function takes variable number of arguments, make a frame index for
1964 // the start of the first vararg value... for expansion of llvm.va_start.
1966 static const uint16_t GPArgRegs[] = {
1967 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1968 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1970 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1972 static const uint16_t FPArgRegs[] = {
1973 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1976 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1978 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1980 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1983 // Make room for NumGPArgRegs and NumFPArgRegs.
1984 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1985 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1987 FuncInfo->setVarArgsStackOffset(
1988 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1989 CCInfo.getNextStackOffset(), true));
1991 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1992 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1994 // The fixed integer arguments of a variadic function are stored to the
1995 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1996 // the result of va_next.
1997 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1998 // Get an existing live-in vreg, or add a new one.
1999 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2001 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2003 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2004 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2005 MachinePointerInfo(), false, false, 0);
2006 MemOps.push_back(Store);
2007 // Increment the address by four for the next argument to store
2008 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2009 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2012 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2014 // The double arguments are stored to the VarArgsFrameIndex
2016 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2017 // Get an existing live-in vreg, or add a new one.
2018 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2020 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2022 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2023 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2024 MachinePointerInfo(), false, false, 0);
2025 MemOps.push_back(Store);
2026 // Increment the address by eight for the next argument to store
2027 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2029 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2033 if (!MemOps.empty())
2034 Chain = DAG.getNode(ISD::TokenFactor, dl,
2035 MVT::Other, &MemOps[0], MemOps.size());
2040 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2041 // value to MVT::i64 and then truncate to the correct register size.
2043 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2044 SelectionDAG &DAG, SDValue ArgVal,
2045 DebugLoc dl) const {
2047 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2048 DAG.getValueType(ObjectVT));
2049 else if (Flags.isZExt())
2050 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2051 DAG.getValueType(ObjectVT));
2053 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2056 // Set the size that is at least reserved in caller of this function. Tail
2057 // call optimized functions' reserved stack space needs to be aligned so that
2058 // taking the difference between two stack areas will result in an aligned
2061 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2062 unsigned nAltivecParamsAtEnd,
2063 unsigned MinReservedArea,
2064 bool isPPC64) const {
2065 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2066 // Add the Altivec parameters at the end, if needed.
2067 if (nAltivecParamsAtEnd) {
2068 MinReservedArea = ((MinReservedArea+15)/16)*16;
2069 MinReservedArea += 16*nAltivecParamsAtEnd;
2072 std::max(MinReservedArea,
2073 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2074 unsigned TargetAlign
2075 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2076 getStackAlignment();
2077 unsigned AlignMask = TargetAlign-1;
2078 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2079 FI->setMinReservedArea(MinReservedArea);
2083 PPCTargetLowering::LowerFormalArguments_64SVR4(
2085 CallingConv::ID CallConv, bool isVarArg,
2086 const SmallVectorImpl<ISD::InputArg>
2088 DebugLoc dl, SelectionDAG &DAG,
2089 SmallVectorImpl<SDValue> &InVals) const {
2090 // TODO: add description of PPC stack frame format, or at least some docs.
2092 MachineFunction &MF = DAG.getMachineFunction();
2093 MachineFrameInfo *MFI = MF.getFrameInfo();
2094 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2096 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2097 // Potential tail calls could cause overwriting of argument stack slots.
2098 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2099 (CallConv == CallingConv::Fast));
2100 unsigned PtrByteSize = 8;
2102 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2103 // Area that is at least reserved in caller of this function.
2104 unsigned MinReservedArea = ArgOffset;
2106 static const uint16_t GPR[] = {
2107 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2108 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2111 static const uint16_t *FPR = GetFPR();
2113 static const uint16_t VR[] = {
2114 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2115 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2118 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2119 const unsigned Num_FPR_Regs = 13;
2120 const unsigned Num_VR_Regs = array_lengthof(VR);
2122 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2124 // Add DAG nodes to load the arguments or copy them out of registers. On
2125 // entry to a function on PPC, the arguments start after the linkage area,
2126 // although the first ones are often in registers.
2128 SmallVector<SDValue, 8> MemOps;
2129 unsigned nAltivecParamsAtEnd = 0;
2130 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2131 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2133 bool needsLoad = false;
2134 EVT ObjectVT = Ins[ArgNo].VT;
2135 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2136 unsigned ArgSize = ObjSize;
2137 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2139 unsigned CurArgOffset = ArgOffset;
2141 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2142 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2143 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2145 MinReservedArea = ((MinReservedArea+15)/16)*16;
2146 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2150 nAltivecParamsAtEnd++;
2152 // Calculate min reserved area.
2153 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2157 // FIXME the codegen can be much improved in some cases.
2158 // We do not have to keep everything in memory.
2159 if (Flags.isByVal()) {
2160 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2161 ObjSize = Flags.getByValSize();
2162 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2163 // Empty aggregate parameters do not take up registers. Examples:
2167 // etc. However, we have to provide a place-holder in InVals, so
2168 // pretend we have an 8-byte item at the current address for that
2171 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2172 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2173 InVals.push_back(FIN);
2176 // All aggregates smaller than 8 bytes must be passed right-justified.
2177 if (ObjSize < PtrByteSize)
2178 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2179 // The value of the object is its address.
2180 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2181 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2182 InVals.push_back(FIN);
2185 if (GPR_idx != Num_GPR_Regs) {
2186 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2187 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2190 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2191 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2192 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2193 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2194 MachinePointerInfo(FuncArg, CurArgOffset),
2195 ObjType, false, false, 0);
2197 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2198 // store the whole register as-is to the parameter save area
2199 // slot. The address of the parameter was already calculated
2200 // above (InVals.push_back(FIN)) to be the right-justified
2201 // offset within the slot. For this store, we need a new
2202 // frame index that points at the beginning of the slot.
2203 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2204 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2205 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2206 MachinePointerInfo(FuncArg, ArgOffset),
2210 MemOps.push_back(Store);
2213 // Whether we copied from a register or not, advance the offset
2214 // into the parameter save area by a full doubleword.
2215 ArgOffset += PtrByteSize;
2219 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2220 // Store whatever pieces of the object are in registers
2221 // to memory. ArgOffset will be the address of the beginning
2223 if (GPR_idx != Num_GPR_Regs) {
2225 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2226 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2227 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2228 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2229 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2230 MachinePointerInfo(FuncArg, ArgOffset),
2232 MemOps.push_back(Store);
2234 ArgOffset += PtrByteSize;
2236 ArgOffset += ArgSize - j;
2243 switch (ObjectVT.getSimpleVT().SimpleTy) {
2244 default: llvm_unreachable("Unhandled argument type!");
2247 if (GPR_idx != Num_GPR_Regs) {
2248 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2249 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2251 if (ObjectVT == MVT::i32)
2252 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2253 // value to MVT::i64 and then truncate to the correct register size.
2254 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2259 ArgSize = PtrByteSize;
2266 // Every 8 bytes of argument space consumes one of the GPRs available for
2267 // argument passing.
2268 if (GPR_idx != Num_GPR_Regs) {
2271 if (FPR_idx != Num_FPR_Regs) {
2274 if (ObjectVT == MVT::f32)
2275 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2277 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2279 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2283 ArgSize = PtrByteSize;
2292 // Note that vector arguments in registers don't reserve stack space,
2293 // except in varargs functions.
2294 if (VR_idx != Num_VR_Regs) {
2295 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2296 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2298 while ((ArgOffset % 16) != 0) {
2299 ArgOffset += PtrByteSize;
2300 if (GPR_idx != Num_GPR_Regs)
2304 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2308 // Vectors are aligned.
2309 ArgOffset = ((ArgOffset+15)/16)*16;
2310 CurArgOffset = ArgOffset;
2317 // We need to load the argument to a virtual register if we determined
2318 // above that we ran out of physical registers of the appropriate type.
2320 int FI = MFI->CreateFixedObject(ObjSize,
2321 CurArgOffset + (ArgSize - ObjSize),
2323 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2324 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2325 false, false, false, 0);
2328 InVals.push_back(ArgVal);
2331 // Set the size that is at least reserved in caller of this function. Tail
2332 // call optimized functions' reserved stack space needs to be aligned so that
2333 // taking the difference between two stack areas will result in an aligned
2335 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2337 // If the function takes variable number of arguments, make a frame index for
2338 // the start of the first vararg value... for expansion of llvm.va_start.
2340 int Depth = ArgOffset;
2342 FuncInfo->setVarArgsFrameIndex(
2343 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2344 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2346 // If this function is vararg, store any remaining integer argument regs
2347 // to their spots on the stack so that they may be loaded by deferencing the
2348 // result of va_next.
2349 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2350 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2351 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2352 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2353 MachinePointerInfo(), false, false, 0);
2354 MemOps.push_back(Store);
2355 // Increment the address by four for the next argument to store
2356 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2357 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2361 if (!MemOps.empty())
2362 Chain = DAG.getNode(ISD::TokenFactor, dl,
2363 MVT::Other, &MemOps[0], MemOps.size());
2369 PPCTargetLowering::LowerFormalArguments_Darwin(
2371 CallingConv::ID CallConv, bool isVarArg,
2372 const SmallVectorImpl<ISD::InputArg>
2374 DebugLoc dl, SelectionDAG &DAG,
2375 SmallVectorImpl<SDValue> &InVals) const {
2376 // TODO: add description of PPC stack frame format, or at least some docs.
2378 MachineFunction &MF = DAG.getMachineFunction();
2379 MachineFrameInfo *MFI = MF.getFrameInfo();
2380 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2382 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2383 bool isPPC64 = PtrVT == MVT::i64;
2384 // Potential tail calls could cause overwriting of argument stack slots.
2385 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2386 (CallConv == CallingConv::Fast));
2387 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2389 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2390 // Area that is at least reserved in caller of this function.
2391 unsigned MinReservedArea = ArgOffset;
2393 static const uint16_t GPR_32[] = { // 32-bit registers.
2394 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2395 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2397 static const uint16_t GPR_64[] = { // 64-bit registers.
2398 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2399 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2402 static const uint16_t *FPR = GetFPR();
2404 static const uint16_t VR[] = {
2405 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2406 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2409 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2410 const unsigned Num_FPR_Regs = 13;
2411 const unsigned Num_VR_Regs = array_lengthof( VR);
2413 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2415 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2417 // In 32-bit non-varargs functions, the stack space for vectors is after the
2418 // stack space for non-vectors. We do not use this space unless we have
2419 // too many vectors to fit in registers, something that only occurs in
2420 // constructed examples:), but we have to walk the arglist to figure
2421 // that out...for the pathological case, compute VecArgOffset as the
2422 // start of the vector parameter area. Computing VecArgOffset is the
2423 // entire point of the following loop.
2424 unsigned VecArgOffset = ArgOffset;
2425 if (!isVarArg && !isPPC64) {
2426 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2428 EVT ObjectVT = Ins[ArgNo].VT;
2429 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2431 if (Flags.isByVal()) {
2432 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2433 unsigned ObjSize = Flags.getByValSize();
2435 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2436 VecArgOffset += ArgSize;
2440 switch(ObjectVT.getSimpleVT().SimpleTy) {
2441 default: llvm_unreachable("Unhandled argument type!");
2446 case MVT::i64: // PPC64
2448 // FIXME: We are guaranteed to be !isPPC64 at this point.
2449 // Does MVT::i64 apply?
2456 // Nothing to do, we're only looking at Nonvector args here.
2461 // We've found where the vector parameter area in memory is. Skip the
2462 // first 12 parameters; these don't use that memory.
2463 VecArgOffset = ((VecArgOffset+15)/16)*16;
2464 VecArgOffset += 12*16;
2466 // Add DAG nodes to load the arguments or copy them out of registers. On
2467 // entry to a function on PPC, the arguments start after the linkage area,
2468 // although the first ones are often in registers.
2470 SmallVector<SDValue, 8> MemOps;
2471 unsigned nAltivecParamsAtEnd = 0;
2472 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2473 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo, ++FuncArg) {
2475 bool needsLoad = false;
2476 EVT ObjectVT = Ins[ArgNo].VT;
2477 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2478 unsigned ArgSize = ObjSize;
2479 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2481 unsigned CurArgOffset = ArgOffset;
2483 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2484 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2485 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2486 if (isVarArg || isPPC64) {
2487 MinReservedArea = ((MinReservedArea+15)/16)*16;
2488 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2491 } else nAltivecParamsAtEnd++;
2493 // Calculate min reserved area.
2494 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2498 // FIXME the codegen can be much improved in some cases.
2499 // We do not have to keep everything in memory.
2500 if (Flags.isByVal()) {
2501 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2502 ObjSize = Flags.getByValSize();
2503 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2504 // Objects of size 1 and 2 are right justified, everything else is
2505 // left justified. This means the memory address is adjusted forwards.
2506 if (ObjSize==1 || ObjSize==2) {
2507 CurArgOffset = CurArgOffset + (4 - ObjSize);
2509 // The value of the object is its address.
2510 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2511 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2512 InVals.push_back(FIN);
2513 if (ObjSize==1 || ObjSize==2) {
2514 if (GPR_idx != Num_GPR_Regs) {
2517 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2519 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2520 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2521 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2522 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2523 MachinePointerInfo(FuncArg,
2525 ObjType, false, false, 0);
2526 MemOps.push_back(Store);
2530 ArgOffset += PtrByteSize;
2534 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2535 // Store whatever pieces of the object are in registers
2536 // to memory. ArgOffset will be the address of the beginning
2538 if (GPR_idx != Num_GPR_Regs) {
2541 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2543 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2544 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2545 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2546 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2547 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2548 MachinePointerInfo(FuncArg, ArgOffset),
2550 MemOps.push_back(Store);
2552 ArgOffset += PtrByteSize;
2554 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2561 switch (ObjectVT.getSimpleVT().SimpleTy) {
2562 default: llvm_unreachable("Unhandled argument type!");
2565 if (GPR_idx != Num_GPR_Regs) {
2566 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2567 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2571 ArgSize = PtrByteSize;
2573 // All int arguments reserve stack space in the Darwin ABI.
2574 ArgOffset += PtrByteSize;
2578 case MVT::i64: // PPC64
2579 if (GPR_idx != Num_GPR_Regs) {
2580 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2581 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2583 if (ObjectVT == MVT::i32)
2584 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2585 // value to MVT::i64 and then truncate to the correct register size.
2586 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2591 ArgSize = PtrByteSize;
2593 // All int arguments reserve stack space in the Darwin ABI.
2599 // Every 4 bytes of argument space consumes one of the GPRs available for
2600 // argument passing.
2601 if (GPR_idx != Num_GPR_Regs) {
2603 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2606 if (FPR_idx != Num_FPR_Regs) {
2609 if (ObjectVT == MVT::f32)
2610 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2612 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2614 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2620 // All FP arguments reserve stack space in the Darwin ABI.
2621 ArgOffset += isPPC64 ? 8 : ObjSize;
2627 // Note that vector arguments in registers don't reserve stack space,
2628 // except in varargs functions.
2629 if (VR_idx != Num_VR_Regs) {
2630 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2631 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2633 while ((ArgOffset % 16) != 0) {
2634 ArgOffset += PtrByteSize;
2635 if (GPR_idx != Num_GPR_Regs)
2639 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2643 if (!isVarArg && !isPPC64) {
2644 // Vectors go after all the nonvectors.
2645 CurArgOffset = VecArgOffset;
2648 // Vectors are aligned.
2649 ArgOffset = ((ArgOffset+15)/16)*16;
2650 CurArgOffset = ArgOffset;
2658 // We need to load the argument to a virtual register if we determined above
2659 // that we ran out of physical registers of the appropriate type.
2661 int FI = MFI->CreateFixedObject(ObjSize,
2662 CurArgOffset + (ArgSize - ObjSize),
2664 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2665 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2666 false, false, false, 0);
2669 InVals.push_back(ArgVal);
2672 // Set the size that is at least reserved in caller of this function. Tail
2673 // call optimized functions' reserved stack space needs to be aligned so that
2674 // taking the difference between two stack areas will result in an aligned
2676 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2678 // If the function takes variable number of arguments, make a frame index for
2679 // the start of the first vararg value... for expansion of llvm.va_start.
2681 int Depth = ArgOffset;
2683 FuncInfo->setVarArgsFrameIndex(
2684 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2686 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2688 // If this function is vararg, store any remaining integer argument regs
2689 // to their spots on the stack so that they may be loaded by deferencing the
2690 // result of va_next.
2691 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2695 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2697 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2699 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2700 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2701 MachinePointerInfo(), false, false, 0);
2702 MemOps.push_back(Store);
2703 // Increment the address by four for the next argument to store
2704 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2705 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2709 if (!MemOps.empty())
2710 Chain = DAG.getNode(ISD::TokenFactor, dl,
2711 MVT::Other, &MemOps[0], MemOps.size());
2716 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2717 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2719 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2723 const SmallVectorImpl<ISD::OutputArg>
2725 const SmallVectorImpl<SDValue> &OutVals,
2726 unsigned &nAltivecParamsAtEnd) {
2727 // Count how many bytes are to be pushed on the stack, including the linkage
2728 // area, and parameter passing area. We start with 24/48 bytes, which is
2729 // prereserved space for [SP][CR][LR][3 x unused].
2730 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2731 unsigned NumOps = Outs.size();
2732 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2734 // Add up all the space actually used.
2735 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2736 // they all go in registers, but we must reserve stack space for them for
2737 // possible use by the caller. In varargs or 64-bit calls, parameters are
2738 // assigned stack space in order, with padding so Altivec parameters are
2740 nAltivecParamsAtEnd = 0;
2741 for (unsigned i = 0; i != NumOps; ++i) {
2742 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2743 EVT ArgVT = Outs[i].VT;
2744 // Varargs Altivec parameters are padded to a 16 byte boundary.
2745 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2746 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2747 if (!isVarArg && !isPPC64) {
2748 // Non-varargs Altivec parameters go after all the non-Altivec
2749 // parameters; handle those later so we know how much padding we need.
2750 nAltivecParamsAtEnd++;
2753 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2754 NumBytes = ((NumBytes+15)/16)*16;
2756 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2759 // Allow for Altivec parameters at the end, if needed.
2760 if (nAltivecParamsAtEnd) {
2761 NumBytes = ((NumBytes+15)/16)*16;
2762 NumBytes += 16*nAltivecParamsAtEnd;
2765 // The prolog code of the callee may store up to 8 GPR argument registers to
2766 // the stack, allowing va_start to index over them in memory if its varargs.
2767 // Because we cannot tell if this is needed on the caller side, we have to
2768 // conservatively assume that it is needed. As such, make sure we have at
2769 // least enough stack space for the caller to store the 8 GPRs.
2770 NumBytes = std::max(NumBytes,
2771 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2773 // Tail call needs the stack to be aligned.
2774 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2775 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2776 getFrameLowering()->getStackAlignment();
2777 unsigned AlignMask = TargetAlign-1;
2778 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2784 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2785 /// adjusted to accommodate the arguments for the tailcall.
2786 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2787 unsigned ParamSize) {
2789 if (!isTailCall) return 0;
2791 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2792 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2793 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2794 // Remember only if the new adjustement is bigger.
2795 if (SPDiff < FI->getTailCallSPDelta())
2796 FI->setTailCallSPDelta(SPDiff);
2801 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2802 /// for tail call optimization. Targets which want to do tail call
2803 /// optimization should implement this function.
2805 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2806 CallingConv::ID CalleeCC,
2808 const SmallVectorImpl<ISD::InputArg> &Ins,
2809 SelectionDAG& DAG) const {
2810 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2813 // Variable argument functions are not supported.
2817 MachineFunction &MF = DAG.getMachineFunction();
2818 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2819 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2820 // Functions containing by val parameters are not supported.
2821 for (unsigned i = 0; i != Ins.size(); i++) {
2822 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2823 if (Flags.isByVal()) return false;
2826 // Non PIC/GOT tail calls are supported.
2827 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2830 // At the moment we can only do local tail calls (in same module, hidden
2831 // or protected) if we are generating PIC.
2832 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2833 return G->getGlobal()->hasHiddenVisibility()
2834 || G->getGlobal()->hasProtectedVisibility();
2840 /// isCallCompatibleAddress - Return the immediate to use if the specified
2841 /// 32-bit value is representable in the immediate field of a BxA instruction.
2842 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2843 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2846 int Addr = C->getZExtValue();
2847 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2848 SignExtend32<26>(Addr) != Addr)
2849 return 0; // Top 6 bits have to be sext of immediate.
2851 return DAG.getConstant((int)C->getZExtValue() >> 2,
2852 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2857 struct TailCallArgumentInfo {
2862 TailCallArgumentInfo() : FrameIdx(0) {}
2867 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2869 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2871 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2872 SmallVector<SDValue, 8> &MemOpChains,
2874 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2875 SDValue Arg = TailCallArgs[i].Arg;
2876 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2877 int FI = TailCallArgs[i].FrameIdx;
2878 // Store relative to framepointer.
2879 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2880 MachinePointerInfo::getFixedStack(FI),
2885 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2886 /// the appropriate stack slot for the tail call optimized function call.
2887 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2888 MachineFunction &MF,
2897 // Calculate the new stack slot for the return address.
2898 int SlotSize = isPPC64 ? 8 : 4;
2899 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2901 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2902 NewRetAddrLoc, true);
2903 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2904 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2905 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2906 MachinePointerInfo::getFixedStack(NewRetAddr),
2909 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2910 // slot as the FP is never overwritten.
2913 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2914 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2916 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2917 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2918 MachinePointerInfo::getFixedStack(NewFPIdx),
2925 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2926 /// the position of the argument.
2928 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2929 SDValue Arg, int SPDiff, unsigned ArgOffset,
2930 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2931 int Offset = ArgOffset + SPDiff;
2932 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2933 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2934 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2935 SDValue FIN = DAG.getFrameIndex(FI, VT);
2936 TailCallArgumentInfo Info;
2938 Info.FrameIdxOp = FIN;
2940 TailCallArguments.push_back(Info);
2943 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2944 /// stack slot. Returns the chain as result and the loaded frame pointers in
2945 /// LROpOut/FPOpout. Used when tail calling.
2946 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2952 DebugLoc dl) const {
2954 // Load the LR and FP stack slot for later adjusting.
2955 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2956 LROpOut = getReturnAddrFrameIndex(DAG);
2957 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2958 false, false, false, 0);
2959 Chain = SDValue(LROpOut.getNode(), 1);
2961 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2962 // slot as the FP is never overwritten.
2964 FPOpOut = getFramePointerFrameIndex(DAG);
2965 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2966 false, false, false, 0);
2967 Chain = SDValue(FPOpOut.getNode(), 1);
2973 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2974 /// by "Src" to address "Dst" of size "Size". Alignment information is
2975 /// specified by the specific parameter attribute. The copy will be passed as
2976 /// a byval function parameter.
2977 /// Sometimes what we are copying is the end of a larger object, the part that
2978 /// does not fit in registers.
2980 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2981 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2983 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2984 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2985 false, false, MachinePointerInfo(0),
2986 MachinePointerInfo(0));
2989 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2992 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2993 SDValue Arg, SDValue PtrOff, int SPDiff,
2994 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2995 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2996 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2998 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3003 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3005 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3006 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3007 DAG.getConstant(ArgOffset, PtrVT));
3009 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3010 MachinePointerInfo(), false, false, 0));
3011 // Calculate and remember argument location.
3012 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3017 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3018 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3019 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3020 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
3021 MachineFunction &MF = DAG.getMachineFunction();
3023 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3024 // might overwrite each other in case of tail call optimization.
3025 SmallVector<SDValue, 8> MemOpChains2;
3026 // Do not flag preceding copytoreg stuff together with the following stuff.
3028 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3030 if (!MemOpChains2.empty())
3031 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3032 &MemOpChains2[0], MemOpChains2.size());
3034 // Store the return address to the appropriate stack slot.
3035 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3036 isPPC64, isDarwinABI, dl);
3038 // Emit callseq_end just before tailcall node.
3039 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3040 DAG.getIntPtrConstant(0, true), InFlag);
3041 InFlag = Chain.getValue(1);
3045 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3046 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
3047 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
3048 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
3049 const PPCSubtarget &PPCSubTarget) {
3051 bool isPPC64 = PPCSubTarget.isPPC64();
3052 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3054 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3055 NodeTys.push_back(MVT::Other); // Returns a chain
3056 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3058 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
3060 bool needIndirectCall = true;
3061 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3062 // If this is an absolute destination address, use the munged value.
3063 Callee = SDValue(Dest, 0);
3064 needIndirectCall = false;
3067 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3068 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3069 // Use indirect calls for ALL functions calls in JIT mode, since the
3070 // far-call stubs may be outside relocation limits for a BL instruction.
3071 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3072 unsigned OpFlags = 0;
3073 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3074 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3075 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3076 (G->getGlobal()->isDeclaration() ||
3077 G->getGlobal()->isWeakForLinker())) {
3078 // PC-relative references to external symbols should go through $stub,
3079 // unless we're building with the leopard linker or later, which
3080 // automatically synthesizes these stubs.
3081 OpFlags = PPCII::MO_DARWIN_STUB;
3084 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3085 // every direct call is) turn it into a TargetGlobalAddress /
3086 // TargetExternalSymbol node so that legalize doesn't hack it.
3087 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3088 Callee.getValueType(),
3090 needIndirectCall = false;
3094 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3095 unsigned char OpFlags = 0;
3097 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3098 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3099 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3100 // PC-relative references to external symbols should go through $stub,
3101 // unless we're building with the leopard linker or later, which
3102 // automatically synthesizes these stubs.
3103 OpFlags = PPCII::MO_DARWIN_STUB;
3106 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3108 needIndirectCall = false;
3111 if (needIndirectCall) {
3112 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3113 // to do the call, we can't use PPCISD::CALL.
3114 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3116 if (isSVR4ABI && isPPC64) {
3117 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3118 // entry point, but to the function descriptor (the function entry point
3119 // address is part of the function descriptor though).
3120 // The function descriptor is a three doubleword structure with the
3121 // following fields: function entry point, TOC base address and
3122 // environment pointer.
3123 // Thus for a call through a function pointer, the following actions need
3125 // 1. Save the TOC of the caller in the TOC save area of its stack
3126 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3127 // 2. Load the address of the function entry point from the function
3129 // 3. Load the TOC of the callee from the function descriptor into r2.
3130 // 4. Load the environment pointer from the function descriptor into
3132 // 5. Branch to the function entry point address.
3133 // 6. On return of the callee, the TOC of the caller needs to be
3134 // restored (this is done in FinishCall()).
3136 // All those operations are flagged together to ensure that no other
3137 // operations can be scheduled in between. E.g. without flagging the
3138 // operations together, a TOC access in the caller could be scheduled
3139 // between the load of the callee TOC and the branch to the callee, which
3140 // results in the TOC access going through the TOC of the callee instead
3141 // of going through the TOC of the caller, which leads to incorrect code.
3143 // Load the address of the function entry point from the function
3145 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3146 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3147 InFlag.getNode() ? 3 : 2);
3148 Chain = LoadFuncPtr.getValue(1);
3149 InFlag = LoadFuncPtr.getValue(2);
3151 // Load environment pointer into r11.
3152 // Offset of the environment pointer within the function descriptor.
3153 SDValue PtrOff = DAG.getIntPtrConstant(16);
3155 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3156 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3158 Chain = LoadEnvPtr.getValue(1);
3159 InFlag = LoadEnvPtr.getValue(2);
3161 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3163 Chain = EnvVal.getValue(0);
3164 InFlag = EnvVal.getValue(1);
3166 // Load TOC of the callee into r2. We are using a target-specific load
3167 // with r2 hard coded, because the result of a target-independent load
3168 // would never go directly into r2, since r2 is a reserved register (which
3169 // prevents the register allocator from allocating it), resulting in an
3170 // additional register being allocated and an unnecessary move instruction
3172 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3173 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3175 Chain = LoadTOCPtr.getValue(0);
3176 InFlag = LoadTOCPtr.getValue(1);
3178 MTCTROps[0] = Chain;
3179 MTCTROps[1] = LoadFuncPtr;
3180 MTCTROps[2] = InFlag;
3183 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3184 2 + (InFlag.getNode() != 0));
3185 InFlag = Chain.getValue(1);
3188 NodeTys.push_back(MVT::Other);
3189 NodeTys.push_back(MVT::Glue);
3190 Ops.push_back(Chain);
3191 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
3193 // Add CTR register as callee so a bctr can be emitted later.
3195 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3198 // If this is a direct call, pass the chain and the callee.
3199 if (Callee.getNode()) {
3200 Ops.push_back(Chain);
3201 Ops.push_back(Callee);
3203 // If this is a tail call add stack pointer delta.
3205 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3207 // Add argument registers to the end of the list so that they are known live
3209 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3210 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3211 RegsToPass[i].second.getValueType()));
3217 bool isLocalCall(const SDValue &Callee)
3219 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3220 return !G->getGlobal()->isDeclaration() &&
3221 !G->getGlobal()->isWeakForLinker();
3226 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3227 CallingConv::ID CallConv, bool isVarArg,
3228 const SmallVectorImpl<ISD::InputArg> &Ins,
3229 DebugLoc dl, SelectionDAG &DAG,
3230 SmallVectorImpl<SDValue> &InVals) const {
3232 SmallVector<CCValAssign, 16> RVLocs;
3233 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3234 getTargetMachine(), RVLocs, *DAG.getContext());
3235 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3237 // Copy all of the result registers out of their specified physreg.
3238 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3239 CCValAssign &VA = RVLocs[i];
3240 assert(VA.isRegLoc() && "Can only return in registers!");
3242 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3243 VA.getLocReg(), VA.getLocVT(), InFlag);
3244 Chain = Val.getValue(1);
3245 InFlag = Val.getValue(2);
3247 switch (VA.getLocInfo()) {
3248 default: llvm_unreachable("Unknown loc info!");
3249 case CCValAssign::Full: break;
3250 case CCValAssign::AExt:
3251 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3253 case CCValAssign::ZExt:
3254 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3255 DAG.getValueType(VA.getValVT()));
3256 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3258 case CCValAssign::SExt:
3259 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3260 DAG.getValueType(VA.getValVT()));
3261 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3265 InVals.push_back(Val);
3272 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
3273 bool isTailCall, bool isVarArg,
3275 SmallVector<std::pair<unsigned, SDValue>, 8>
3277 SDValue InFlag, SDValue Chain,
3279 int SPDiff, unsigned NumBytes,
3280 const SmallVectorImpl<ISD::InputArg> &Ins,
3281 SmallVectorImpl<SDValue> &InVals) const {
3282 std::vector<EVT> NodeTys;
3283 SmallVector<SDValue, 8> Ops;
3284 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3285 isTailCall, RegsToPass, Ops, NodeTys,
3288 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3289 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3290 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3292 // When performing tail call optimization the callee pops its arguments off
3293 // the stack. Account for this here so these bytes can be pushed back on in
3294 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
3295 int BytesCalleePops =
3296 (CallConv == CallingConv::Fast &&
3297 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3299 // Add a register mask operand representing the call-preserved registers.
3300 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3301 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3302 assert(Mask && "Missing call preserved mask for calling convention");
3303 Ops.push_back(DAG.getRegisterMask(Mask));
3305 if (InFlag.getNode())
3306 Ops.push_back(InFlag);
3310 // If this is the first return lowered for this function, add the regs
3311 // to the liveout set for the function.
3312 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3313 SmallVector<CCValAssign, 16> RVLocs;
3314 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3315 getTargetMachine(), RVLocs, *DAG.getContext());
3316 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3317 for (unsigned i = 0; i != RVLocs.size(); ++i)
3318 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3321 assert(((Callee.getOpcode() == ISD::Register &&
3322 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3323 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3324 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3325 isa<ConstantSDNode>(Callee)) &&
3326 "Expecting an global address, external symbol, absolute value or register");
3328 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3331 // Add a NOP immediately after the branch instruction when using the 64-bit
3332 // SVR4 ABI. At link time, if caller and callee are in a different module and
3333 // thus have a different TOC, the call will be replaced with a call to a stub
3334 // function which saves the current TOC, loads the TOC of the callee and
3335 // branches to the callee. The NOP will be replaced with a load instruction
3336 // which restores the TOC of the caller from the TOC save slot of the current
3337 // stack frame. If caller and callee belong to the same module (and have the
3338 // same TOC), the NOP will remain unchanged.
3340 bool needsTOCRestore = false;
3341 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3342 if (CallOpc == PPCISD::BCTRL_SVR4) {
3343 // This is a call through a function pointer.
3344 // Restore the caller TOC from the save area into R2.
3345 // See PrepareCall() for more information about calls through function
3346 // pointers in the 64-bit SVR4 ABI.
3347 // We are using a target-specific load with r2 hard coded, because the
3348 // result of a target-independent load would never go directly into r2,
3349 // since r2 is a reserved register (which prevents the register allocator
3350 // from allocating it), resulting in an additional register being
3351 // allocated and an unnecessary move instruction being generated.
3352 needsTOCRestore = true;
3353 } else if ((CallOpc == PPCISD::CALL_SVR4) && !isLocalCall(Callee)) {
3354 // Otherwise insert NOP for non-local calls.
3355 CallOpc = PPCISD::CALL_NOP_SVR4;
3359 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3360 InFlag = Chain.getValue(1);
3362 if (needsTOCRestore) {
3363 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3364 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3365 InFlag = Chain.getValue(1);
3368 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3369 DAG.getIntPtrConstant(BytesCalleePops, true),
3372 InFlag = Chain.getValue(1);
3374 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3375 Ins, dl, DAG, InVals);
3379 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3380 SmallVectorImpl<SDValue> &InVals) const {
3381 SelectionDAG &DAG = CLI.DAG;
3382 DebugLoc &dl = CLI.DL;
3383 SmallVector<ISD::OutputArg, 32> &Outs = CLI.Outs;
3384 SmallVector<SDValue, 32> &OutVals = CLI.OutVals;
3385 SmallVector<ISD::InputArg, 32> &Ins = CLI.Ins;
3386 SDValue Chain = CLI.Chain;
3387 SDValue Callee = CLI.Callee;
3388 bool &isTailCall = CLI.IsTailCall;
3389 CallingConv::ID CallConv = CLI.CallConv;
3390 bool isVarArg = CLI.IsVarArg;
3393 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3396 if (PPCSubTarget.isSVR4ABI()) {
3397 if (PPCSubTarget.isPPC64())
3398 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3399 isTailCall, Outs, OutVals, Ins,
3402 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3403 isTailCall, Outs, OutVals, Ins,
3407 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3408 isTailCall, Outs, OutVals, Ins,
3413 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3414 CallingConv::ID CallConv, bool isVarArg,
3416 const SmallVectorImpl<ISD::OutputArg> &Outs,
3417 const SmallVectorImpl<SDValue> &OutVals,
3418 const SmallVectorImpl<ISD::InputArg> &Ins,
3419 DebugLoc dl, SelectionDAG &DAG,
3420 SmallVectorImpl<SDValue> &InVals) const {
3421 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3422 // of the 32-bit SVR4 ABI stack frame layout.
3424 assert((CallConv == CallingConv::C ||
3425 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3427 unsigned PtrByteSize = 4;
3429 MachineFunction &MF = DAG.getMachineFunction();
3431 // Mark this function as potentially containing a function that contains a
3432 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3433 // and restoring the callers stack pointer in this functions epilog. This is
3434 // done because by tail calling the called function might overwrite the value
3435 // in this function's (MF) stack pointer stack slot 0(SP).
3436 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3437 CallConv == CallingConv::Fast)
3438 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3440 // Count how many bytes are to be pushed on the stack, including the linkage
3441 // area, parameter list area and the part of the local variable space which
3442 // contains copies of aggregates which are passed by value.
3444 // Assign locations to all of the outgoing arguments.
3445 SmallVector<CCValAssign, 16> ArgLocs;
3446 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3447 getTargetMachine(), ArgLocs, *DAG.getContext());
3449 // Reserve space for the linkage area on the stack.
3450 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3453 // Handle fixed and variable vector arguments differently.
3454 // Fixed vector arguments go into registers as long as registers are
3455 // available. Variable vector arguments always go into memory.
3456 unsigned NumArgs = Outs.size();
3458 for (unsigned i = 0; i != NumArgs; ++i) {
3459 MVT ArgVT = Outs[i].VT;
3460 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3463 if (Outs[i].IsFixed) {
3464 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3467 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3473 errs() << "Call operand #" << i << " has unhandled type "
3474 << EVT(ArgVT).getEVTString() << "\n";
3476 llvm_unreachable(0);
3480 // All arguments are treated the same.
3481 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
3484 // Assign locations to all of the outgoing aggregate by value arguments.
3485 SmallVector<CCValAssign, 16> ByValArgLocs;
3486 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3487 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3489 // Reserve stack space for the allocations in CCInfo.
3490 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3492 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
3494 // Size of the linkage area, parameter list area and the part of the local
3495 // space variable where copies of aggregates which are passed by value are
3497 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3499 // Calculate by how many bytes the stack has to be adjusted in case of tail
3500 // call optimization.
3501 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3503 // Adjust the stack pointer for the new arguments...
3504 // These operations are automatically eliminated by the prolog/epilog pass
3505 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3506 SDValue CallSeqStart = Chain;
3508 // Load the return address and frame pointer so it can be moved somewhere else
3511 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3514 // Set up a copy of the stack pointer for use loading and storing any
3515 // arguments that may not fit in the registers available for argument
3517 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3519 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3520 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3521 SmallVector<SDValue, 8> MemOpChains;
3523 bool seenFloatArg = false;
3524 // Walk the register/memloc assignments, inserting copies/loads.
3525 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3528 CCValAssign &VA = ArgLocs[i];
3529 SDValue Arg = OutVals[i];
3530 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3532 if (Flags.isByVal()) {
3533 // Argument is an aggregate which is passed by value, thus we need to
3534 // create a copy of it in the local variable space of the current stack
3535 // frame (which is the stack frame of the caller) and pass the address of
3536 // this copy to the callee.
3537 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3538 CCValAssign &ByValVA = ByValArgLocs[j++];
3539 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3541 // Memory reserved in the local variable space of the callers stack frame.
3542 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3544 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3545 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3547 // Create a copy of the argument in the local area of the current
3549 SDValue MemcpyCall =
3550 CreateCopyOfByValArgument(Arg, PtrOff,
3551 CallSeqStart.getNode()->getOperand(0),
3554 // This must go outside the CALLSEQ_START..END.
3555 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3556 CallSeqStart.getNode()->getOperand(1));
3557 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3558 NewCallSeqStart.getNode());
3559 Chain = CallSeqStart = NewCallSeqStart;
3561 // Pass the address of the aggregate copy on the stack either in a
3562 // physical register or in the parameter list area of the current stack
3563 // frame to the callee.
3567 if (VA.isRegLoc()) {
3568 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3569 // Put argument in a physical register.
3570 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3572 // Put argument in the parameter list area of the current stack frame.
3573 assert(VA.isMemLoc());
3574 unsigned LocMemOffset = VA.getLocMemOffset();
3577 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3578 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3580 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3581 MachinePointerInfo(),
3584 // Calculate and remember argument location.
3585 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3591 if (!MemOpChains.empty())
3592 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3593 &MemOpChains[0], MemOpChains.size());
3595 // Build a sequence of copy-to-reg nodes chained together with token chain
3596 // and flag operands which copy the outgoing args into the appropriate regs.
3598 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3599 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3600 RegsToPass[i].second, InFlag);
3601 InFlag = Chain.getValue(1);
3604 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3607 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3608 SDValue Ops[] = { Chain, InFlag };
3610 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3611 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3613 InFlag = Chain.getValue(1);
3617 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3618 false, TailCallArguments);
3620 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3621 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3625 // Copy an argument into memory, being careful to do this outside the
3626 // call sequence for the call to which the argument belongs.
3628 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3629 SDValue CallSeqStart,
3630 ISD::ArgFlagsTy Flags,
3632 DebugLoc dl) const {
3633 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3634 CallSeqStart.getNode()->getOperand(0),
3636 // The MEMCPY must go outside the CALLSEQ_START..END.
3637 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3638 CallSeqStart.getNode()->getOperand(1));
3639 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3640 NewCallSeqStart.getNode());
3641 return NewCallSeqStart;
3645 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3646 CallingConv::ID CallConv, bool isVarArg,
3648 const SmallVectorImpl<ISD::OutputArg> &Outs,
3649 const SmallVectorImpl<SDValue> &OutVals,
3650 const SmallVectorImpl<ISD::InputArg> &Ins,
3651 DebugLoc dl, SelectionDAG &DAG,
3652 SmallVectorImpl<SDValue> &InVals) const {
3654 unsigned NumOps = Outs.size();
3656 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3657 unsigned PtrByteSize = 8;
3659 MachineFunction &MF = DAG.getMachineFunction();
3661 // Mark this function as potentially containing a function that contains a
3662 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3663 // and restoring the callers stack pointer in this functions epilog. This is
3664 // done because by tail calling the called function might overwrite the value
3665 // in this function's (MF) stack pointer stack slot 0(SP).
3666 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3667 CallConv == CallingConv::Fast)
3668 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3670 unsigned nAltivecParamsAtEnd = 0;
3672 // Count how many bytes are to be pushed on the stack, including the linkage
3673 // area, and parameter passing area. We start with at least 48 bytes, which
3674 // is reserved space for [SP][CR][LR][3 x unused].
3675 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3678 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3679 Outs, OutVals, nAltivecParamsAtEnd);
3681 // Calculate by how many bytes the stack has to be adjusted in case of tail
3682 // call optimization.
3683 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3685 // To protect arguments on the stack from being clobbered in a tail call,
3686 // force all the loads to happen before doing any other lowering.
3688 Chain = DAG.getStackArgumentTokenFactor(Chain);
3690 // Adjust the stack pointer for the new arguments...
3691 // These operations are automatically eliminated by the prolog/epilog pass
3692 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3693 SDValue CallSeqStart = Chain;
3695 // Load the return address and frame pointer so it can be move somewhere else
3698 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3701 // Set up a copy of the stack pointer for use loading and storing any
3702 // arguments that may not fit in the registers available for argument
3704 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3706 // Figure out which arguments are going to go in registers, and which in
3707 // memory. Also, if this is a vararg function, floating point operations
3708 // must be stored to our stack, and loaded into integer regs as well, if
3709 // any integer regs are available for argument passing.
3710 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3711 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3713 static const uint16_t GPR[] = {
3714 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3715 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3717 static const uint16_t *FPR = GetFPR();
3719 static const uint16_t VR[] = {
3720 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3721 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3723 const unsigned NumGPRs = array_lengthof(GPR);
3724 const unsigned NumFPRs = 13;
3725 const unsigned NumVRs = array_lengthof(VR);
3727 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3728 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3730 SmallVector<SDValue, 8> MemOpChains;
3731 for (unsigned i = 0; i != NumOps; ++i) {
3732 SDValue Arg = OutVals[i];
3733 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3735 // PtrOff will be used to store the current argument to the stack if a
3736 // register cannot be found for it.
3739 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3741 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3743 // Promote integers to 64-bit values.
3744 if (Arg.getValueType() == MVT::i32) {
3745 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3746 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3747 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3750 // FIXME memcpy is used way more than necessary. Correctness first.
3751 // Note: "by value" is code for passing a structure by value, not
3753 if (Flags.isByVal()) {
3754 // Note: Size includes alignment padding, so
3755 // struct x { short a; char b; }
3756 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3757 // These are the proper values we need for right-justifying the
3758 // aggregate in a parameter register.
3759 unsigned Size = Flags.getByValSize();
3761 // An empty aggregate parameter takes up no storage and no
3766 // All aggregates smaller than 8 bytes must be passed right-justified.
3767 if (Size==1 || Size==2 || Size==4) {
3768 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3769 if (GPR_idx != NumGPRs) {
3770 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3771 MachinePointerInfo(), VT,
3773 MemOpChains.push_back(Load.getValue(1));
3774 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3776 ArgOffset += PtrByteSize;
3781 if (GPR_idx == NumGPRs && Size < 8) {
3782 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3783 PtrOff.getValueType());
3784 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3785 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3788 ArgOffset += PtrByteSize;
3791 // Copy entire object into memory. There are cases where gcc-generated
3792 // code assumes it is there, even if it could be put entirely into
3793 // registers. (This is not what the doc says.)
3795 // FIXME: The above statement is likely due to a misunderstanding of the
3796 // documents. All arguments must be copied into the parameter area BY
3797 // THE CALLEE in the event that the callee takes the address of any
3798 // formal argument. That has not yet been implemented. However, it is
3799 // reasonable to use the stack area as a staging area for the register
3802 // Skip this for small aggregates, as we will use the same slot for a
3803 // right-justified copy, below.
3805 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3809 // When a register is available, pass a small aggregate right-justified.
3810 if (Size < 8 && GPR_idx != NumGPRs) {
3811 // The easiest way to get this right-justified in a register
3812 // is to copy the structure into the rightmost portion of a
3813 // local variable slot, then load the whole slot into the
3815 // FIXME: The memcpy seems to produce pretty awful code for
3816 // small aggregates, particularly for packed ones.
3817 // FIXME: It would be preferable to use the slot in the
3818 // parameter save area instead of a new local variable.
3819 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3820 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3821 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3825 // Load the slot into the register.
3826 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3827 MachinePointerInfo(),
3828 false, false, false, 0);
3829 MemOpChains.push_back(Load.getValue(1));
3830 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3832 // Done with this argument.
3833 ArgOffset += PtrByteSize;
3837 // For aggregates larger than PtrByteSize, copy the pieces of the
3838 // object that fit into registers from the parameter save area.
3839 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3840 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3841 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3842 if (GPR_idx != NumGPRs) {
3843 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3844 MachinePointerInfo(),
3845 false, false, false, 0);
3846 MemOpChains.push_back(Load.getValue(1));
3847 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3848 ArgOffset += PtrByteSize;
3850 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3857 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3858 default: llvm_unreachable("Unexpected ValueType for argument!");
3861 if (GPR_idx != NumGPRs) {
3862 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3864 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3865 true, isTailCall, false, MemOpChains,
3866 TailCallArguments, dl);
3868 ArgOffset += PtrByteSize;
3872 if (FPR_idx != NumFPRs) {
3873 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3876 // A single float or an aggregate containing only a single float
3877 // must be passed right-justified in the stack doubleword, and
3878 // in the GPR, if one is available.
3880 if (Arg.getValueType().getSimpleVT().SimpleTy == MVT::f32) {
3881 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3882 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3886 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
3887 MachinePointerInfo(), false, false, 0);
3888 MemOpChains.push_back(Store);
3890 // Float varargs are always shadowed in available integer registers
3891 if (GPR_idx != NumGPRs) {
3892 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3893 MachinePointerInfo(), false, false,
3895 MemOpChains.push_back(Load.getValue(1));
3896 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3898 } else if (GPR_idx != NumGPRs)
3899 // If we have any FPRs remaining, we may also have GPRs remaining.
3902 // Single-precision floating-point values are mapped to the
3903 // second (rightmost) word of the stack doubleword.
3904 if (Arg.getValueType() == MVT::f32) {
3905 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3906 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3909 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3910 true, isTailCall, false, MemOpChains,
3911 TailCallArguments, dl);
3920 // These go aligned on the stack, or in the corresponding R registers
3921 // when within range. The Darwin PPC ABI doc claims they also go in
3922 // V registers; in fact gcc does this only for arguments that are
3923 // prototyped, not for those that match the ... We do it for all
3924 // arguments, seems to work.
3925 while (ArgOffset % 16 !=0) {
3926 ArgOffset += PtrByteSize;
3927 if (GPR_idx != NumGPRs)
3930 // We could elide this store in the case where the object fits
3931 // entirely in R registers. Maybe later.
3932 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3933 DAG.getConstant(ArgOffset, PtrVT));
3934 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3935 MachinePointerInfo(), false, false, 0);
3936 MemOpChains.push_back(Store);
3937 if (VR_idx != NumVRs) {
3938 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3939 MachinePointerInfo(),
3940 false, false, false, 0);
3941 MemOpChains.push_back(Load.getValue(1));
3942 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3945 for (unsigned i=0; i<16; i+=PtrByteSize) {
3946 if (GPR_idx == NumGPRs)
3948 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3949 DAG.getConstant(i, PtrVT));
3950 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3951 false, false, false, 0);
3952 MemOpChains.push_back(Load.getValue(1));
3953 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3958 // Non-varargs Altivec params generally go in registers, but have
3959 // stack space allocated at the end.
3960 if (VR_idx != NumVRs) {
3961 // Doesn't have GPR space allocated.
3962 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3964 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3965 true, isTailCall, true, MemOpChains,
3966 TailCallArguments, dl);
3973 if (!MemOpChains.empty())
3974 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3975 &MemOpChains[0], MemOpChains.size());
3977 // Check if this is an indirect call (MTCTR/BCTRL).
3978 // See PrepareCall() for more information about calls through function
3979 // pointers in the 64-bit SVR4 ABI.
3981 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3982 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3983 !isBLACompatibleAddress(Callee, DAG)) {
3984 // Load r2 into a virtual register and store it to the TOC save area.
3985 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3986 // TOC save area offset.
3987 SDValue PtrOff = DAG.getIntPtrConstant(40);
3988 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3989 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3991 // R12 must contain the address of an indirect callee. This does not
3992 // mean the MTCTR instruction must use R12; it's easier to model this
3993 // as an extra parameter, so do that.
3994 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
3997 // Build a sequence of copy-to-reg nodes chained together with token chain
3998 // and flag operands which copy the outgoing args into the appropriate regs.
4000 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4001 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4002 RegsToPass[i].second, InFlag);
4003 InFlag = Chain.getValue(1);
4007 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4008 FPOp, true, TailCallArguments);
4010 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4011 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4016 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4017 CallingConv::ID CallConv, bool isVarArg,
4019 const SmallVectorImpl<ISD::OutputArg> &Outs,
4020 const SmallVectorImpl<SDValue> &OutVals,
4021 const SmallVectorImpl<ISD::InputArg> &Ins,
4022 DebugLoc dl, SelectionDAG &DAG,
4023 SmallVectorImpl<SDValue> &InVals) const {
4025 unsigned NumOps = Outs.size();
4027 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4028 bool isPPC64 = PtrVT == MVT::i64;
4029 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4031 MachineFunction &MF = DAG.getMachineFunction();
4033 // Mark this function as potentially containing a function that contains a
4034 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4035 // and restoring the callers stack pointer in this functions epilog. This is
4036 // done because by tail calling the called function might overwrite the value
4037 // in this function's (MF) stack pointer stack slot 0(SP).
4038 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4039 CallConv == CallingConv::Fast)
4040 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4042 unsigned nAltivecParamsAtEnd = 0;
4044 // Count how many bytes are to be pushed on the stack, including the linkage
4045 // area, and parameter passing area. We start with 24/48 bytes, which is
4046 // prereserved space for [SP][CR][LR][3 x unused].
4048 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4050 nAltivecParamsAtEnd);
4052 // Calculate by how many bytes the stack has to be adjusted in case of tail
4053 // call optimization.
4054 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4056 // To protect arguments on the stack from being clobbered in a tail call,
4057 // force all the loads to happen before doing any other lowering.
4059 Chain = DAG.getStackArgumentTokenFactor(Chain);
4061 // Adjust the stack pointer for the new arguments...
4062 // These operations are automatically eliminated by the prolog/epilog pass
4063 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
4064 SDValue CallSeqStart = Chain;
4066 // Load the return address and frame pointer so it can be move somewhere else
4069 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4072 // Set up a copy of the stack pointer for use loading and storing any
4073 // arguments that may not fit in the registers available for argument
4077 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4079 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4081 // Figure out which arguments are going to go in registers, and which in
4082 // memory. Also, if this is a vararg function, floating point operations
4083 // must be stored to our stack, and loaded into integer regs as well, if
4084 // any integer regs are available for argument passing.
4085 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4086 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4088 static const uint16_t GPR_32[] = { // 32-bit registers.
4089 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4090 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4092 static const uint16_t GPR_64[] = { // 64-bit registers.
4093 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4094 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4096 static const uint16_t *FPR = GetFPR();
4098 static const uint16_t VR[] = {
4099 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4100 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4102 const unsigned NumGPRs = array_lengthof(GPR_32);
4103 const unsigned NumFPRs = 13;
4104 const unsigned NumVRs = array_lengthof(VR);
4106 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4108 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4109 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4111 SmallVector<SDValue, 8> MemOpChains;
4112 for (unsigned i = 0; i != NumOps; ++i) {
4113 SDValue Arg = OutVals[i];
4114 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4116 // PtrOff will be used to store the current argument to the stack if a
4117 // register cannot be found for it.
4120 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4122 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4124 // On PPC64, promote integers to 64-bit values.
4125 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4126 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4127 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4128 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4131 // FIXME memcpy is used way more than necessary. Correctness first.
4132 // Note: "by value" is code for passing a structure by value, not
4134 if (Flags.isByVal()) {
4135 unsigned Size = Flags.getByValSize();
4136 // Very small objects are passed right-justified. Everything else is
4137 // passed left-justified.
4138 if (Size==1 || Size==2) {
4139 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4140 if (GPR_idx != NumGPRs) {
4141 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4142 MachinePointerInfo(), VT,
4144 MemOpChains.push_back(Load.getValue(1));
4145 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4147 ArgOffset += PtrByteSize;
4149 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4150 PtrOff.getValueType());
4151 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4152 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4155 ArgOffset += PtrByteSize;
4159 // Copy entire object into memory. There are cases where gcc-generated
4160 // code assumes it is there, even if it could be put entirely into
4161 // registers. (This is not what the doc says.)
4162 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4166 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4167 // copy the pieces of the object that fit into registers from the
4168 // parameter save area.
4169 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4170 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4171 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4172 if (GPR_idx != NumGPRs) {
4173 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4174 MachinePointerInfo(),
4175 false, false, false, 0);
4176 MemOpChains.push_back(Load.getValue(1));
4177 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4178 ArgOffset += PtrByteSize;
4180 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4187 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
4188 default: llvm_unreachable("Unexpected ValueType for argument!");
4191 if (GPR_idx != NumGPRs) {
4192 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4194 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4195 isPPC64, isTailCall, false, MemOpChains,
4196 TailCallArguments, dl);
4198 ArgOffset += PtrByteSize;
4202 if (FPR_idx != NumFPRs) {
4203 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4206 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4207 MachinePointerInfo(), false, false, 0);
4208 MemOpChains.push_back(Store);
4210 // Float varargs are always shadowed in available integer registers
4211 if (GPR_idx != NumGPRs) {
4212 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4213 MachinePointerInfo(), false, false,
4215 MemOpChains.push_back(Load.getValue(1));
4216 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4218 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4219 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4220 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4221 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4222 MachinePointerInfo(),
4223 false, false, false, 0);
4224 MemOpChains.push_back(Load.getValue(1));
4225 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4228 // If we have any FPRs remaining, we may also have GPRs remaining.
4229 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4231 if (GPR_idx != NumGPRs)
4233 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4234 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4238 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4239 isPPC64, isTailCall, false, MemOpChains,
4240 TailCallArguments, dl);
4244 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4251 // These go aligned on the stack, or in the corresponding R registers
4252 // when within range. The Darwin PPC ABI doc claims they also go in
4253 // V registers; in fact gcc does this only for arguments that are
4254 // prototyped, not for those that match the ... We do it for all
4255 // arguments, seems to work.
4256 while (ArgOffset % 16 !=0) {
4257 ArgOffset += PtrByteSize;
4258 if (GPR_idx != NumGPRs)
4261 // We could elide this store in the case where the object fits
4262 // entirely in R registers. Maybe later.
4263 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4264 DAG.getConstant(ArgOffset, PtrVT));
4265 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4266 MachinePointerInfo(), false, false, 0);
4267 MemOpChains.push_back(Store);
4268 if (VR_idx != NumVRs) {
4269 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4270 MachinePointerInfo(),
4271 false, false, false, 0);
4272 MemOpChains.push_back(Load.getValue(1));
4273 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4276 for (unsigned i=0; i<16; i+=PtrByteSize) {
4277 if (GPR_idx == NumGPRs)
4279 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4280 DAG.getConstant(i, PtrVT));
4281 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4282 false, false, false, 0);
4283 MemOpChains.push_back(Load.getValue(1));
4284 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4289 // Non-varargs Altivec params generally go in registers, but have
4290 // stack space allocated at the end.
4291 if (VR_idx != NumVRs) {
4292 // Doesn't have GPR space allocated.
4293 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4294 } else if (nAltivecParamsAtEnd==0) {
4295 // We are emitting Altivec params in order.
4296 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4297 isPPC64, isTailCall, true, MemOpChains,
4298 TailCallArguments, dl);
4304 // If all Altivec parameters fit in registers, as they usually do,
4305 // they get stack space following the non-Altivec parameters. We
4306 // don't track this here because nobody below needs it.
4307 // If there are more Altivec parameters than fit in registers emit
4309 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4311 // Offset is aligned; skip 1st 12 params which go in V registers.
4312 ArgOffset = ((ArgOffset+15)/16)*16;
4314 for (unsigned i = 0; i != NumOps; ++i) {
4315 SDValue Arg = OutVals[i];
4316 EVT ArgType = Outs[i].VT;
4317 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4318 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4321 // We are emitting Altivec params in order.
4322 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4323 isPPC64, isTailCall, true, MemOpChains,
4324 TailCallArguments, dl);
4331 if (!MemOpChains.empty())
4332 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4333 &MemOpChains[0], MemOpChains.size());
4335 // On Darwin, R12 must contain the address of an indirect callee. This does
4336 // not mean the MTCTR instruction must use R12; it's easier to model this as
4337 // an extra parameter, so do that.
4339 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4340 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4341 !isBLACompatibleAddress(Callee, DAG))
4342 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4343 PPC::R12), Callee));
4345 // Build a sequence of copy-to-reg nodes chained together with token chain
4346 // and flag operands which copy the outgoing args into the appropriate regs.
4348 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4349 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4350 RegsToPass[i].second, InFlag);
4351 InFlag = Chain.getValue(1);
4355 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4356 FPOp, true, TailCallArguments);
4358 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4359 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4364 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4365 MachineFunction &MF, bool isVarArg,
4366 const SmallVectorImpl<ISD::OutputArg> &Outs,
4367 LLVMContext &Context) const {
4368 SmallVector<CCValAssign, 16> RVLocs;
4369 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4371 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4375 PPCTargetLowering::LowerReturn(SDValue Chain,
4376 CallingConv::ID CallConv, bool isVarArg,
4377 const SmallVectorImpl<ISD::OutputArg> &Outs,
4378 const SmallVectorImpl<SDValue> &OutVals,
4379 DebugLoc dl, SelectionDAG &DAG) const {
4381 SmallVector<CCValAssign, 16> RVLocs;
4382 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4383 getTargetMachine(), RVLocs, *DAG.getContext());
4384 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4386 // If this is the first return lowered for this function, add the regs to the
4387 // liveout set for the function.
4388 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
4389 for (unsigned i = 0; i != RVLocs.size(); ++i)
4390 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
4395 // Copy the result values into the output registers.
4396 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4397 CCValAssign &VA = RVLocs[i];
4398 assert(VA.isRegLoc() && "Can only return in registers!");
4400 SDValue Arg = OutVals[i];
4402 switch (VA.getLocInfo()) {
4403 default: llvm_unreachable("Unknown loc info!");
4404 case CCValAssign::Full: break;
4405 case CCValAssign::AExt:
4406 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4408 case CCValAssign::ZExt:
4409 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4411 case CCValAssign::SExt:
4412 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4416 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4417 Flag = Chain.getValue(1);
4421 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
4423 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
4426 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4427 const PPCSubtarget &Subtarget) const {
4428 // When we pop the dynamic allocation we need to restore the SP link.
4429 DebugLoc dl = Op.getDebugLoc();
4431 // Get the corect type for pointers.
4432 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4434 // Construct the stack pointer operand.
4435 bool isPPC64 = Subtarget.isPPC64();
4436 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4437 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4439 // Get the operands for the STACKRESTORE.
4440 SDValue Chain = Op.getOperand(0);
4441 SDValue SaveSP = Op.getOperand(1);
4443 // Load the old link SP.
4444 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4445 MachinePointerInfo(),
4446 false, false, false, 0);
4448 // Restore the stack pointer.
4449 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4451 // Store the old link SP.
4452 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4459 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4460 MachineFunction &MF = DAG.getMachineFunction();
4461 bool isPPC64 = PPCSubTarget.isPPC64();
4462 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4463 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4465 // Get current frame pointer save index. The users of this index will be
4466 // primarily DYNALLOC instructions.
4467 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4468 int RASI = FI->getReturnAddrSaveIndex();
4470 // If the frame pointer save index hasn't been defined yet.
4472 // Find out what the fix offset of the frame pointer save area.
4473 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4474 // Allocate the frame index for frame pointer save area.
4475 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4477 FI->setReturnAddrSaveIndex(RASI);
4479 return DAG.getFrameIndex(RASI, PtrVT);
4483 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4484 MachineFunction &MF = DAG.getMachineFunction();
4485 bool isPPC64 = PPCSubTarget.isPPC64();
4486 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4487 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4489 // Get current frame pointer save index. The users of this index will be
4490 // primarily DYNALLOC instructions.
4491 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4492 int FPSI = FI->getFramePointerSaveIndex();
4494 // If the frame pointer save index hasn't been defined yet.
4496 // Find out what the fix offset of the frame pointer save area.
4497 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4500 // Allocate the frame index for frame pointer save area.
4501 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4503 FI->setFramePointerSaveIndex(FPSI);
4505 return DAG.getFrameIndex(FPSI, PtrVT);
4508 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4510 const PPCSubtarget &Subtarget) const {
4512 SDValue Chain = Op.getOperand(0);
4513 SDValue Size = Op.getOperand(1);
4514 DebugLoc dl = Op.getDebugLoc();
4516 // Get the corect type for pointers.
4517 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4519 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4520 DAG.getConstant(0, PtrVT), Size);
4521 // Construct a node for the frame pointer save index.
4522 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4523 // Build a DYNALLOC node.
4524 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4525 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4526 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4529 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4531 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4532 // Not FP? Not a fsel.
4533 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4534 !Op.getOperand(2).getValueType().isFloatingPoint())
4537 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4539 // Cannot handle SETEQ/SETNE.
4540 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
4542 EVT ResVT = Op.getValueType();
4543 EVT CmpVT = Op.getOperand(0).getValueType();
4544 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4545 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4546 DebugLoc dl = Op.getDebugLoc();
4548 // If the RHS of the comparison is a 0.0, we don't need to do the
4549 // subtraction at all.
4550 if (isFloatingPointZero(RHS))
4552 default: break; // SETUO etc aren't handled by fsel.
4555 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4558 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4559 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4560 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4563 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4566 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4567 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4568 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4569 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4574 default: break; // SETUO etc aren't handled by fsel.
4577 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4578 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4579 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4580 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4583 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4584 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4585 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4586 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4589 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4590 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4591 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4592 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4595 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4596 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4597 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4598 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4603 // FIXME: Split this code up when LegalizeDAGTypes lands.
4604 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4605 DebugLoc dl) const {
4606 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4607 SDValue Src = Op.getOperand(0);
4608 if (Src.getValueType() == MVT::f32)
4609 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4612 switch (Op.getValueType().getSimpleVT().SimpleTy) {
4613 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4615 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4620 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
4624 // Convert the FP value to an int value through memory.
4625 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
4627 // Emit a store to the stack slot.
4628 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4629 MachinePointerInfo(), false, false, 0);
4631 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4633 if (Op.getValueType() == MVT::i32)
4634 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4635 DAG.getConstant(4, FIPtr.getValueType()));
4636 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
4637 false, false, false, 0);
4640 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
4641 SelectionDAG &DAG) const {
4642 DebugLoc dl = Op.getDebugLoc();
4643 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4644 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4647 if (Op.getOperand(0).getValueType() == MVT::i64) {
4648 SDValue SINT = Op.getOperand(0);
4649 // When converting to single-precision, we actually need to convert
4650 // to double-precision first and then round to single-precision.
4651 // To avoid double-rounding effects during that operation, we have
4652 // to prepare the input operand. Bits that might be truncated when
4653 // converting to double-precision are replaced by a bit that won't
4654 // be lost at this stage, but is below the single-precision rounding
4657 // However, if -enable-unsafe-fp-math is in effect, accept double
4658 // rounding to avoid the extra overhead.
4659 if (Op.getValueType() == MVT::f32 &&
4660 !DAG.getTarget().Options.UnsafeFPMath) {
4662 // Twiddle input to make sure the low 11 bits are zero. (If this
4663 // is the case, we are guaranteed the value will fit into the 53 bit
4664 // mantissa of an IEEE double-precision value without rounding.)
4665 // If any of those low 11 bits were not zero originally, make sure
4666 // bit 12 (value 2048) is set instead, so that the final rounding
4667 // to single-precision gets the correct result.
4668 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4669 SINT, DAG.getConstant(2047, MVT::i64));
4670 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4671 Round, DAG.getConstant(2047, MVT::i64));
4672 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4673 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4674 Round, DAG.getConstant(-2048, MVT::i64));
4676 // However, we cannot use that value unconditionally: if the magnitude
4677 // of the input value is small, the bit-twiddling we did above might
4678 // end up visibly changing the output. Fortunately, in that case, we
4679 // don't need to twiddle bits since the original input will convert
4680 // exactly to double-precision floating-point already. Therefore,
4681 // construct a conditional to use the original value if the top 11
4682 // bits are all sign-bit copies, and use the rounded value computed
4684 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4685 SINT, DAG.getConstant(53, MVT::i32));
4686 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4687 Cond, DAG.getConstant(1, MVT::i64));
4688 Cond = DAG.getSetCC(dl, MVT::i32,
4689 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4691 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4693 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4694 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
4695 if (Op.getValueType() == MVT::f32)
4696 FP = DAG.getNode(ISD::FP_ROUND, dl,
4697 MVT::f32, FP, DAG.getIntPtrConstant(0));
4701 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4702 "Unhandled SINT_TO_FP type in custom expander!");
4703 // Since we only generate this in 64-bit mode, we can take advantage of
4704 // 64-bit registers. In particular, sign extend the input value into the
4705 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4706 // then lfd it and fcfid it.
4707 MachineFunction &MF = DAG.getMachineFunction();
4708 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4709 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4710 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4711 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4713 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
4716 // STD the extended value into the stack slot.
4717 MachineMemOperand *MMO =
4718 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4719 MachineMemOperand::MOStore, 8, 8);
4720 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
4722 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
4723 Ops, 4, MVT::i64, MMO);
4724 // Load the value as a double.
4725 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
4726 false, false, false, 0);
4728 // FCFID it and return it.
4729 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
4730 if (Op.getValueType() == MVT::f32)
4731 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4735 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4736 SelectionDAG &DAG) const {
4737 DebugLoc dl = Op.getDebugLoc();
4739 The rounding mode is in bits 30:31 of FPSR, and has the following
4746 FLT_ROUNDS, on the other hand, expects the following:
4753 To perform the conversion, we do:
4754 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
4757 MachineFunction &MF = DAG.getMachineFunction();
4758 EVT VT = Op.getValueType();
4759 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4760 std::vector<EVT> NodeTys;
4761 SDValue MFFSreg, InFlag;
4763 // Save FP Control Word to register
4764 NodeTys.push_back(MVT::f64); // return register
4765 NodeTys.push_back(MVT::Glue); // unused in this context
4766 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4768 // Save FP register to stack slot
4769 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
4770 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
4771 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
4772 StackSlot, MachinePointerInfo(), false, false,0);
4774 // Load FP Control Word from low 32 bits of stack slot.
4775 SDValue Four = DAG.getConstant(4, PtrVT);
4776 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
4777 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
4778 false, false, false, 0);
4780 // Transform as necessary
4782 DAG.getNode(ISD::AND, dl, MVT::i32,
4783 CWD, DAG.getConstant(3, MVT::i32));
4785 DAG.getNode(ISD::SRL, dl, MVT::i32,
4786 DAG.getNode(ISD::AND, dl, MVT::i32,
4787 DAG.getNode(ISD::XOR, dl, MVT::i32,
4788 CWD, DAG.getConstant(3, MVT::i32)),
4789 DAG.getConstant(3, MVT::i32)),
4790 DAG.getConstant(1, MVT::i32));
4793 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
4795 return DAG.getNode((VT.getSizeInBits() < 16 ?
4796 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
4799 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4800 EVT VT = Op.getValueType();
4801 unsigned BitWidth = VT.getSizeInBits();
4802 DebugLoc dl = Op.getDebugLoc();
4803 assert(Op.getNumOperands() == 3 &&
4804 VT == Op.getOperand(1).getValueType() &&
4807 // Expand into a bunch of logical ops. Note that these ops
4808 // depend on the PPC behavior for oversized shift amounts.
4809 SDValue Lo = Op.getOperand(0);
4810 SDValue Hi = Op.getOperand(1);
4811 SDValue Amt = Op.getOperand(2);
4812 EVT AmtVT = Amt.getValueType();
4814 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4815 DAG.getConstant(BitWidth, AmtVT), Amt);
4816 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
4817 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
4818 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
4819 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4820 DAG.getConstant(-BitWidth, AmtVT));
4821 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
4822 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4823 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
4824 SDValue OutOps[] = { OutLo, OutHi };
4825 return DAG.getMergeValues(OutOps, 2, dl);
4828 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
4829 EVT VT = Op.getValueType();
4830 DebugLoc dl = Op.getDebugLoc();
4831 unsigned BitWidth = VT.getSizeInBits();
4832 assert(Op.getNumOperands() == 3 &&
4833 VT == Op.getOperand(1).getValueType() &&
4836 // Expand into a bunch of logical ops. Note that these ops
4837 // depend on the PPC behavior for oversized shift amounts.
4838 SDValue Lo = Op.getOperand(0);
4839 SDValue Hi = Op.getOperand(1);
4840 SDValue Amt = Op.getOperand(2);
4841 EVT AmtVT = Amt.getValueType();
4843 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4844 DAG.getConstant(BitWidth, AmtVT), Amt);
4845 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4846 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4847 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4848 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4849 DAG.getConstant(-BitWidth, AmtVT));
4850 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
4851 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
4852 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
4853 SDValue OutOps[] = { OutLo, OutHi };
4854 return DAG.getMergeValues(OutOps, 2, dl);
4857 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
4858 DebugLoc dl = Op.getDebugLoc();
4859 EVT VT = Op.getValueType();
4860 unsigned BitWidth = VT.getSizeInBits();
4861 assert(Op.getNumOperands() == 3 &&
4862 VT == Op.getOperand(1).getValueType() &&
4865 // Expand into a bunch of logical ops, followed by a select_cc.
4866 SDValue Lo = Op.getOperand(0);
4867 SDValue Hi = Op.getOperand(1);
4868 SDValue Amt = Op.getOperand(2);
4869 EVT AmtVT = Amt.getValueType();
4871 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
4872 DAG.getConstant(BitWidth, AmtVT), Amt);
4873 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
4874 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
4875 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
4876 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
4877 DAG.getConstant(-BitWidth, AmtVT));
4878 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
4879 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
4880 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
4881 Tmp4, Tmp6, ISD::SETLE);
4882 SDValue OutOps[] = { OutLo, OutHi };
4883 return DAG.getMergeValues(OutOps, 2, dl);
4886 //===----------------------------------------------------------------------===//
4887 // Vector related lowering.
4890 /// BuildSplatI - Build a canonical splati of Val with an element size of
4891 /// SplatSize. Cast the result to VT.
4892 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
4893 SelectionDAG &DAG, DebugLoc dl) {
4894 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
4896 static const EVT VTys[] = { // canonical VT to use for each size.
4897 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
4900 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
4902 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
4906 EVT CanonicalVT = VTys[SplatSize-1];
4908 // Build a canonical splat for this value.
4909 SDValue Elt = DAG.getConstant(Val, MVT::i32);
4910 SmallVector<SDValue, 8> Ops;
4911 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
4912 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
4913 &Ops[0], Ops.size());
4914 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
4917 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
4918 /// specified intrinsic ID.
4919 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
4920 SelectionDAG &DAG, DebugLoc dl,
4921 EVT DestVT = MVT::Other) {
4922 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
4923 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4924 DAG.getConstant(IID, MVT::i32), LHS, RHS);
4927 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
4928 /// specified intrinsic ID.
4929 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
4930 SDValue Op2, SelectionDAG &DAG,
4931 DebugLoc dl, EVT DestVT = MVT::Other) {
4932 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
4933 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
4934 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
4938 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
4939 /// amount. The result has the specified value type.
4940 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
4941 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
4942 // Force LHS/RHS to be the right type.
4943 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
4944 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
4947 for (unsigned i = 0; i != 16; ++i)
4949 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
4950 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4953 // If this is a case we can't handle, return null and let the default
4954 // expansion code take care of it. If we CAN select this case, and if it
4955 // selects to a single instruction, return Op. Otherwise, if we can codegen
4956 // this case more efficiently than a constant pool load, lower it to the
4957 // sequence of ops that should be used.
4958 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
4959 SelectionDAG &DAG) const {
4960 DebugLoc dl = Op.getDebugLoc();
4961 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
4962 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
4964 // Check if this is a splat of a constant value.
4965 APInt APSplatBits, APSplatUndef;
4966 unsigned SplatBitSize;
4968 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
4969 HasAnyUndefs, 0, true) || SplatBitSize > 32)
4972 unsigned SplatBits = APSplatBits.getZExtValue();
4973 unsigned SplatUndef = APSplatUndef.getZExtValue();
4974 unsigned SplatSize = SplatBitSize / 8;
4976 // First, handle single instruction cases.
4979 if (SplatBits == 0) {
4980 // Canonicalize all zero vectors to be v4i32.
4981 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
4982 SDValue Z = DAG.getConstant(0, MVT::i32);
4983 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
4984 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
4989 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
4990 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
4992 if (SextVal >= -16 && SextVal <= 15)
4993 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
4996 // Two instruction sequences.
4998 // If this value is in the range [-32,30] and is even, use:
4999 // tmp = VSPLTI[bhw], result = add tmp, tmp
5000 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
5001 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
5002 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
5003 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5006 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5007 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5009 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5010 // Make -1 and vspltisw -1:
5011 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5013 // Make the VSLW intrinsic, computing 0x8000_0000.
5014 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5017 // xor by OnesV to invert it.
5018 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5019 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5022 // Check to see if this is a wide variety of vsplti*, binop self cases.
5023 static const signed char SplatCsts[] = {
5024 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5025 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5028 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5029 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5030 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5031 int i = SplatCsts[idx];
5033 // Figure out what shift amount will be used by altivec if shifted by i in
5035 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5037 // vsplti + shl self.
5038 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5039 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5040 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5041 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5042 Intrinsic::ppc_altivec_vslw
5044 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5045 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5048 // vsplti + srl self.
5049 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5050 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5051 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5052 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5053 Intrinsic::ppc_altivec_vsrw
5055 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5056 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5059 // vsplti + sra self.
5060 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5061 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5062 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5063 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5064 Intrinsic::ppc_altivec_vsraw
5066 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5067 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5070 // vsplti + rol self.
5071 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5072 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5073 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5074 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5075 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5076 Intrinsic::ppc_altivec_vrlw
5078 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5079 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5082 // t = vsplti c, result = vsldoi t, t, 1
5083 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5084 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5085 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5087 // t = vsplti c, result = vsldoi t, t, 2
5088 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5089 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5090 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5092 // t = vsplti c, result = vsldoi t, t, 3
5093 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5094 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5095 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5099 // Three instruction sequences.
5101 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
5102 if (SextVal >= 0 && SextVal <= 31) {
5103 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
5104 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
5105 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
5106 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
5108 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
5109 if (SextVal >= -31 && SextVal <= 0) {
5110 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
5111 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
5112 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
5113 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
5119 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5120 /// the specified operations to build the shuffle.
5121 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5122 SDValue RHS, SelectionDAG &DAG,
5124 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5125 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5126 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5129 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5141 if (OpNum == OP_COPY) {
5142 if (LHSID == (1*9+2)*9+3) return LHS;
5143 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5147 SDValue OpLHS, OpRHS;
5148 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5149 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5153 default: llvm_unreachable("Unknown i32 permute!");
5155 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5156 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5157 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5158 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5161 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5162 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5163 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5164 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5167 for (unsigned i = 0; i != 16; ++i)
5168 ShufIdxs[i] = (i&3)+0;
5171 for (unsigned i = 0; i != 16; ++i)
5172 ShufIdxs[i] = (i&3)+4;
5175 for (unsigned i = 0; i != 16; ++i)
5176 ShufIdxs[i] = (i&3)+8;
5179 for (unsigned i = 0; i != 16; ++i)
5180 ShufIdxs[i] = (i&3)+12;
5183 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5185 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5187 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5189 EVT VT = OpLHS.getValueType();
5190 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5191 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5192 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5193 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5196 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5197 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5198 /// return the code it can be lowered into. Worst case, it can always be
5199 /// lowered into a vperm.
5200 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5201 SelectionDAG &DAG) const {
5202 DebugLoc dl = Op.getDebugLoc();
5203 SDValue V1 = Op.getOperand(0);
5204 SDValue V2 = Op.getOperand(1);
5205 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5206 EVT VT = Op.getValueType();
5208 // Cases that are handled by instructions that take permute immediates
5209 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5210 // selected by the instruction selector.
5211 if (V2.getOpcode() == ISD::UNDEF) {
5212 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5213 PPC::isSplatShuffleMask(SVOp, 2) ||
5214 PPC::isSplatShuffleMask(SVOp, 4) ||
5215 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5216 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5217 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5218 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5219 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5220 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5221 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5222 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5223 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5228 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5229 // and produce a fixed permutation. If any of these match, do not lower to
5231 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5232 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5233 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5234 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5235 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5236 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5237 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5238 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5239 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5242 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5243 // perfect shuffle table to emit an optimal matching sequence.
5244 ArrayRef<int> PermMask = SVOp->getMask();
5246 unsigned PFIndexes[4];
5247 bool isFourElementShuffle = true;
5248 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5249 unsigned EltNo = 8; // Start out undef.
5250 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5251 if (PermMask[i*4+j] < 0)
5252 continue; // Undef, ignore it.
5254 unsigned ByteSource = PermMask[i*4+j];
5255 if ((ByteSource & 3) != j) {
5256 isFourElementShuffle = false;
5261 EltNo = ByteSource/4;
5262 } else if (EltNo != ByteSource/4) {
5263 isFourElementShuffle = false;
5267 PFIndexes[i] = EltNo;
5270 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5271 // perfect shuffle vector to determine if it is cost effective to do this as
5272 // discrete instructions, or whether we should use a vperm.
5273 if (isFourElementShuffle) {
5274 // Compute the index in the perfect shuffle table.
5275 unsigned PFTableIndex =
5276 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5278 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5279 unsigned Cost = (PFEntry >> 30);
5281 // Determining when to avoid vperm is tricky. Many things affect the cost
5282 // of vperm, particularly how many times the perm mask needs to be computed.
5283 // For example, if the perm mask can be hoisted out of a loop or is already
5284 // used (perhaps because there are multiple permutes with the same shuffle
5285 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5286 // the loop requires an extra register.
5288 // As a compromise, we only emit discrete instructions if the shuffle can be
5289 // generated in 3 or fewer operations. When we have loop information
5290 // available, if this block is within a loop, we should avoid using vperm
5291 // for 3-operation perms and use a constant pool load instead.
5293 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5296 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5297 // vector that will get spilled to the constant pool.
5298 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5300 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5301 // that it is in input element units, not in bytes. Convert now.
5302 EVT EltVT = V1.getValueType().getVectorElementType();
5303 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5305 SmallVector<SDValue, 16> ResultMask;
5306 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5307 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5309 for (unsigned j = 0; j != BytesPerElement; ++j)
5310 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5314 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5315 &ResultMask[0], ResultMask.size());
5316 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5319 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5320 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5321 /// information about the intrinsic.
5322 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5324 unsigned IntrinsicID =
5325 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5328 switch (IntrinsicID) {
5329 default: return false;
5330 // Comparison predicates.
5331 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5332 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5333 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5334 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5335 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5336 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5337 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5338 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5339 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5340 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5341 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5342 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5343 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5345 // Normal Comparisons.
5346 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5347 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5348 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5349 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5350 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5351 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5352 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5353 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5354 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5355 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5356 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5357 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5358 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5363 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5364 /// lower, do it, otherwise return null.
5365 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5366 SelectionDAG &DAG) const {
5367 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5368 // opcode number of the comparison.
5369 DebugLoc dl = Op.getDebugLoc();
5372 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5373 return SDValue(); // Don't custom lower most intrinsics.
5375 // If this is a non-dot comparison, make the VCMP node and we are done.
5377 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5378 Op.getOperand(1), Op.getOperand(2),
5379 DAG.getConstant(CompareOpc, MVT::i32));
5380 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5383 // Create the PPCISD altivec 'dot' comparison node.
5385 Op.getOperand(2), // LHS
5386 Op.getOperand(3), // RHS
5387 DAG.getConstant(CompareOpc, MVT::i32)
5389 std::vector<EVT> VTs;
5390 VTs.push_back(Op.getOperand(2).getValueType());
5391 VTs.push_back(MVT::Glue);
5392 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5394 // Now that we have the comparison, emit a copy from the CR to a GPR.
5395 // This is flagged to the above dot comparison.
5396 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
5397 DAG.getRegister(PPC::CR6, MVT::i32),
5398 CompNode.getValue(1));
5400 // Unpack the result based on how the target uses it.
5401 unsigned BitNo; // Bit # of CR6.
5402 bool InvertBit; // Invert result?
5403 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5404 default: // Can't happen, don't crash on invalid number though.
5405 case 0: // Return the value of the EQ bit of CR6.
5406 BitNo = 0; InvertBit = false;
5408 case 1: // Return the inverted value of the EQ bit of CR6.
5409 BitNo = 0; InvertBit = true;
5411 case 2: // Return the value of the LT bit of CR6.
5412 BitNo = 2; InvertBit = false;
5414 case 3: // Return the inverted value of the LT bit of CR6.
5415 BitNo = 2; InvertBit = true;
5419 // Shift the bit into the low position.
5420 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5421 DAG.getConstant(8-(3-BitNo), MVT::i32));
5423 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5424 DAG.getConstant(1, MVT::i32));
5426 // If we are supposed to, toggle the bit.
5428 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5429 DAG.getConstant(1, MVT::i32));
5433 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5434 SelectionDAG &DAG) const {
5435 DebugLoc dl = Op.getDebugLoc();
5436 // Create a stack slot that is 16-byte aligned.
5437 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5438 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5439 EVT PtrVT = getPointerTy();
5440 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5442 // Store the input value into Value#0 of the stack slot.
5443 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5444 Op.getOperand(0), FIdx, MachinePointerInfo(),
5447 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5448 false, false, false, 0);
5451 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5452 DebugLoc dl = Op.getDebugLoc();
5453 if (Op.getValueType() == MVT::v4i32) {
5454 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5456 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5457 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5459 SDValue RHSSwap = // = vrlw RHS, 16
5460 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5462 // Shrinkify inputs to v8i16.
5463 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5464 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5465 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5467 // Low parts multiplied together, generating 32-bit results (we ignore the
5469 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5470 LHS, RHS, DAG, dl, MVT::v4i32);
5472 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5473 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5474 // Shift the high parts up 16 bits.
5475 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5477 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5478 } else if (Op.getValueType() == MVT::v8i16) {
5479 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5481 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5483 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5484 LHS, RHS, Zero, DAG, dl);
5485 } else if (Op.getValueType() == MVT::v16i8) {
5486 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5488 // Multiply the even 8-bit parts, producing 16-bit sums.
5489 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5490 LHS, RHS, DAG, dl, MVT::v8i16);
5491 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5493 // Multiply the odd 8-bit parts, producing 16-bit sums.
5494 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5495 LHS, RHS, DAG, dl, MVT::v8i16);
5496 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5498 // Merge the results together.
5500 for (unsigned i = 0; i != 8; ++i) {
5502 Ops[i*2+1] = 2*i+1+16;
5504 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5506 llvm_unreachable("Unknown mul to lower!");
5510 /// LowerOperation - Provide custom lowering hooks for some operations.
5512 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5513 switch (Op.getOpcode()) {
5514 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5515 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5516 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5517 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5518 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5519 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5520 case ISD::SETCC: return LowerSETCC(Op, DAG);
5521 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5522 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5524 return LowerVASTART(Op, DAG, PPCSubTarget);
5527 return LowerVAARG(Op, DAG, PPCSubTarget);
5529 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5530 case ISD::DYNAMIC_STACKALLOC:
5531 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5533 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5534 case ISD::FP_TO_UINT:
5535 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5537 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
5538 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5540 // Lower 64-bit shifts.
5541 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5542 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5543 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5545 // Vector-related lowering.
5546 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5547 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5548 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5549 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5550 case ISD::MUL: return LowerMUL(Op, DAG);
5552 // Frame & Return address.
5553 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5554 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5558 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5559 SmallVectorImpl<SDValue>&Results,
5560 SelectionDAG &DAG) const {
5561 const TargetMachine &TM = getTargetMachine();
5562 DebugLoc dl = N->getDebugLoc();
5563 switch (N->getOpcode()) {
5565 llvm_unreachable("Do not know how to custom type legalize this operation!");
5567 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5568 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5571 EVT VT = N->getValueType(0);
5573 if (VT == MVT::i64) {
5574 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5576 Results.push_back(NewNode);
5577 Results.push_back(NewNode.getValue(1));
5581 case ISD::FP_ROUND_INREG: {
5582 assert(N->getValueType(0) == MVT::ppcf128);
5583 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5584 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5585 MVT::f64, N->getOperand(0),
5586 DAG.getIntPtrConstant(0));
5587 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5588 MVT::f64, N->getOperand(0),
5589 DAG.getIntPtrConstant(1));
5591 // This sequence changes FPSCR to do round-to-zero, adds the two halves
5592 // of the long double, and puts FPSCR back the way it was. We do not
5593 // actually model FPSCR.
5594 std::vector<EVT> NodeTys;
5595 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
5597 NodeTys.push_back(MVT::f64); // Return register
5598 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
5599 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5600 MFFSreg = Result.getValue(0);
5601 InFlag = Result.getValue(1);
5604 NodeTys.push_back(MVT::Glue); // Returns a flag
5605 Ops[0] = DAG.getConstant(31, MVT::i32);
5607 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
5608 InFlag = Result.getValue(0);
5611 NodeTys.push_back(MVT::Glue); // Returns a flag
5612 Ops[0] = DAG.getConstant(30, MVT::i32);
5614 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
5615 InFlag = Result.getValue(0);
5618 NodeTys.push_back(MVT::f64); // result of add
5619 NodeTys.push_back(MVT::Glue); // Returns a flag
5623 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
5624 FPreg = Result.getValue(0);
5625 InFlag = Result.getValue(1);
5628 NodeTys.push_back(MVT::f64);
5629 Ops[0] = DAG.getConstant(1, MVT::i32);
5633 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
5634 FPreg = Result.getValue(0);
5636 // We know the low half is about to be thrown away, so just use something
5638 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5642 case ISD::FP_TO_SINT:
5643 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5649 //===----------------------------------------------------------------------===//
5650 // Other Lowering Code
5651 //===----------------------------------------------------------------------===//
5654 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5655 bool is64bit, unsigned BinOpcode) const {
5656 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5657 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5659 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5660 MachineFunction *F = BB->getParent();
5661 MachineFunction::iterator It = BB;
5664 unsigned dest = MI->getOperand(0).getReg();
5665 unsigned ptrA = MI->getOperand(1).getReg();
5666 unsigned ptrB = MI->getOperand(2).getReg();
5667 unsigned incr = MI->getOperand(3).getReg();
5668 DebugLoc dl = MI->getDebugLoc();
5670 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5671 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5672 F->insert(It, loopMBB);
5673 F->insert(It, exitMBB);
5674 exitMBB->splice(exitMBB->begin(), BB,
5675 llvm::next(MachineBasicBlock::iterator(MI)),
5677 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5679 MachineRegisterInfo &RegInfo = F->getRegInfo();
5680 unsigned TmpReg = (!BinOpcode) ? incr :
5681 RegInfo.createVirtualRegister(
5682 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5683 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5687 // fallthrough --> loopMBB
5688 BB->addSuccessor(loopMBB);
5691 // l[wd]arx dest, ptr
5692 // add r0, dest, incr
5693 // st[wd]cx. r0, ptr
5695 // fallthrough --> exitMBB
5697 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5698 .addReg(ptrA).addReg(ptrB);
5700 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5701 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5702 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5703 BuildMI(BB, dl, TII->get(PPC::BCC))
5704 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5705 BB->addSuccessor(loopMBB);
5706 BB->addSuccessor(exitMBB);
5715 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5716 MachineBasicBlock *BB,
5717 bool is8bit, // operation
5718 unsigned BinOpcode) const {
5719 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5720 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5721 // In 64 bit mode we have to use 64 bits for addresses, even though the
5722 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5723 // registers without caring whether they're 32 or 64, but here we're
5724 // doing actual arithmetic on the addresses.
5725 bool is64bit = PPCSubTarget.isPPC64();
5726 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5728 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5729 MachineFunction *F = BB->getParent();
5730 MachineFunction::iterator It = BB;
5733 unsigned dest = MI->getOperand(0).getReg();
5734 unsigned ptrA = MI->getOperand(1).getReg();
5735 unsigned ptrB = MI->getOperand(2).getReg();
5736 unsigned incr = MI->getOperand(3).getReg();
5737 DebugLoc dl = MI->getDebugLoc();
5739 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5740 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5741 F->insert(It, loopMBB);
5742 F->insert(It, exitMBB);
5743 exitMBB->splice(exitMBB->begin(), BB,
5744 llvm::next(MachineBasicBlock::iterator(MI)),
5746 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5748 MachineRegisterInfo &RegInfo = F->getRegInfo();
5749 const TargetRegisterClass *RC =
5750 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5751 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5752 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5753 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5754 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5755 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5756 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5757 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5758 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5759 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5760 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5761 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5762 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5764 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
5768 // fallthrough --> loopMBB
5769 BB->addSuccessor(loopMBB);
5771 // The 4-byte load must be aligned, while a char or short may be
5772 // anywhere in the word. Hence all this nasty bookkeeping code.
5773 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5774 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5775 // xori shift, shift1, 24 [16]
5776 // rlwinm ptr, ptr1, 0, 0, 29
5777 // slw incr2, incr, shift
5778 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5779 // slw mask, mask2, shift
5781 // lwarx tmpDest, ptr
5782 // add tmp, tmpDest, incr2
5783 // andc tmp2, tmpDest, mask
5784 // and tmp3, tmp, mask
5785 // or tmp4, tmp3, tmp2
5788 // fallthrough --> exitMBB
5789 // srw dest, tmpDest, shift
5790 if (ptrA != ZeroReg) {
5791 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5792 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5793 .addReg(ptrA).addReg(ptrB);
5797 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5798 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5799 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5800 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5802 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5803 .addReg(Ptr1Reg).addImm(0).addImm(61);
5805 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5806 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5807 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
5808 .addReg(incr).addReg(ShiftReg);
5810 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5812 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5813 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
5815 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5816 .addReg(Mask2Reg).addReg(ShiftReg);
5819 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5820 .addReg(ZeroReg).addReg(PtrReg);
5822 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
5823 .addReg(Incr2Reg).addReg(TmpDestReg);
5824 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
5825 .addReg(TmpDestReg).addReg(MaskReg);
5826 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
5827 .addReg(TmpReg).addReg(MaskReg);
5828 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
5829 .addReg(Tmp3Reg).addReg(Tmp2Reg);
5830 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5831 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
5832 BuildMI(BB, dl, TII->get(PPC::BCC))
5833 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5834 BB->addSuccessor(loopMBB);
5835 BB->addSuccessor(exitMBB);
5840 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
5846 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
5847 MachineBasicBlock *BB) const {
5848 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5850 // To "insert" these instructions we actually have to insert their
5851 // control-flow patterns.
5852 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5853 MachineFunction::iterator It = BB;
5856 MachineFunction *F = BB->getParent();
5858 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
5859 MI->getOpcode() == PPC::SELECT_CC_I8)) {
5860 unsigned OpCode = MI->getOpcode() == PPC::SELECT_CC_I8 ?
5861 PPC::ISEL8 : PPC::ISEL;
5862 unsigned SelectPred = MI->getOperand(4).getImm();
5863 DebugLoc dl = MI->getDebugLoc();
5865 // The SelectPred is ((BI << 5) | BO) for a BCC
5866 unsigned BO = SelectPred & 0xF;
5867 assert((BO == 12 || BO == 4) && "invalid predicate BO field for isel");
5869 unsigned TrueOpNo, FalseOpNo;
5876 SelectPred = PPC::InvertPredicate((PPC::Predicate)SelectPred);
5879 BuildMI(*BB, MI, dl, TII->get(OpCode), MI->getOperand(0).getReg())
5880 .addReg(MI->getOperand(TrueOpNo).getReg())
5881 .addReg(MI->getOperand(FalseOpNo).getReg())
5882 .addImm(SelectPred).addReg(MI->getOperand(1).getReg());
5883 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
5884 MI->getOpcode() == PPC::SELECT_CC_I8 ||
5885 MI->getOpcode() == PPC::SELECT_CC_F4 ||
5886 MI->getOpcode() == PPC::SELECT_CC_F8 ||
5887 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
5890 // The incoming instruction knows the destination vreg to set, the
5891 // condition code register to branch on, the true/false values to
5892 // select between, and a branch opcode to use.
5897 // cmpTY ccX, r1, r2
5899 // fallthrough --> copy0MBB
5900 MachineBasicBlock *thisMBB = BB;
5901 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
5902 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
5903 unsigned SelectPred = MI->getOperand(4).getImm();
5904 DebugLoc dl = MI->getDebugLoc();
5905 F->insert(It, copy0MBB);
5906 F->insert(It, sinkMBB);
5908 // Transfer the remainder of BB and its successor edges to sinkMBB.
5909 sinkMBB->splice(sinkMBB->begin(), BB,
5910 llvm::next(MachineBasicBlock::iterator(MI)),
5912 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
5914 // Next, add the true and fallthrough blocks as its successors.
5915 BB->addSuccessor(copy0MBB);
5916 BB->addSuccessor(sinkMBB);
5918 BuildMI(BB, dl, TII->get(PPC::BCC))
5919 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
5922 // %FalseValue = ...
5923 // # fallthrough to sinkMBB
5926 // Update machine-CFG edges
5927 BB->addSuccessor(sinkMBB);
5930 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
5933 BuildMI(*BB, BB->begin(), dl,
5934 TII->get(PPC::PHI), MI->getOperand(0).getReg())
5935 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
5936 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
5938 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
5939 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
5940 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
5941 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
5942 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
5943 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
5944 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
5945 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
5947 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
5948 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
5949 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
5950 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
5951 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
5952 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
5953 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
5954 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
5956 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
5957 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
5958 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
5959 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
5960 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
5961 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
5962 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
5963 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
5965 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
5966 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
5967 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
5968 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
5969 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
5970 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
5971 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
5972 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
5974 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
5975 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
5976 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
5977 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
5978 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
5979 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
5980 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
5981 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
5983 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
5984 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
5985 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
5986 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
5987 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
5988 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
5989 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
5990 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
5992 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
5993 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
5994 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
5995 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
5996 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
5997 BB = EmitAtomicBinary(MI, BB, false, 0);
5998 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
5999 BB = EmitAtomicBinary(MI, BB, true, 0);
6001 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6002 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6003 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6005 unsigned dest = MI->getOperand(0).getReg();
6006 unsigned ptrA = MI->getOperand(1).getReg();
6007 unsigned ptrB = MI->getOperand(2).getReg();
6008 unsigned oldval = MI->getOperand(3).getReg();
6009 unsigned newval = MI->getOperand(4).getReg();
6010 DebugLoc dl = MI->getDebugLoc();
6012 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6013 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6014 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6015 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6016 F->insert(It, loop1MBB);
6017 F->insert(It, loop2MBB);
6018 F->insert(It, midMBB);
6019 F->insert(It, exitMBB);
6020 exitMBB->splice(exitMBB->begin(), BB,
6021 llvm::next(MachineBasicBlock::iterator(MI)),
6023 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6027 // fallthrough --> loopMBB
6028 BB->addSuccessor(loop1MBB);
6031 // l[wd]arx dest, ptr
6032 // cmp[wd] dest, oldval
6035 // st[wd]cx. newval, ptr
6039 // st[wd]cx. dest, ptr
6042 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6043 .addReg(ptrA).addReg(ptrB);
6044 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6045 .addReg(oldval).addReg(dest);
6046 BuildMI(BB, dl, TII->get(PPC::BCC))
6047 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6048 BB->addSuccessor(loop2MBB);
6049 BB->addSuccessor(midMBB);
6052 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6053 .addReg(newval).addReg(ptrA).addReg(ptrB);
6054 BuildMI(BB, dl, TII->get(PPC::BCC))
6055 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6056 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6057 BB->addSuccessor(loop1MBB);
6058 BB->addSuccessor(exitMBB);
6061 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6062 .addReg(dest).addReg(ptrA).addReg(ptrB);
6063 BB->addSuccessor(exitMBB);
6068 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6069 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6070 // We must use 64-bit registers for addresses when targeting 64-bit,
6071 // since we're actually doing arithmetic on them. Other registers
6073 bool is64bit = PPCSubTarget.isPPC64();
6074 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6076 unsigned dest = MI->getOperand(0).getReg();
6077 unsigned ptrA = MI->getOperand(1).getReg();
6078 unsigned ptrB = MI->getOperand(2).getReg();
6079 unsigned oldval = MI->getOperand(3).getReg();
6080 unsigned newval = MI->getOperand(4).getReg();
6081 DebugLoc dl = MI->getDebugLoc();
6083 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6084 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6085 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6086 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6087 F->insert(It, loop1MBB);
6088 F->insert(It, loop2MBB);
6089 F->insert(It, midMBB);
6090 F->insert(It, exitMBB);
6091 exitMBB->splice(exitMBB->begin(), BB,
6092 llvm::next(MachineBasicBlock::iterator(MI)),
6094 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6096 MachineRegisterInfo &RegInfo = F->getRegInfo();
6097 const TargetRegisterClass *RC =
6098 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6099 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6100 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6101 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6102 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6103 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6104 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6105 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6106 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6107 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6108 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6109 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6110 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6111 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6112 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6114 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6115 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
6118 // fallthrough --> loopMBB
6119 BB->addSuccessor(loop1MBB);
6121 // The 4-byte load must be aligned, while a char or short may be
6122 // anywhere in the word. Hence all this nasty bookkeeping code.
6123 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6124 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6125 // xori shift, shift1, 24 [16]
6126 // rlwinm ptr, ptr1, 0, 0, 29
6127 // slw newval2, newval, shift
6128 // slw oldval2, oldval,shift
6129 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6130 // slw mask, mask2, shift
6131 // and newval3, newval2, mask
6132 // and oldval3, oldval2, mask
6134 // lwarx tmpDest, ptr
6135 // and tmp, tmpDest, mask
6136 // cmpw tmp, oldval3
6139 // andc tmp2, tmpDest, mask
6140 // or tmp4, tmp2, newval3
6145 // stwcx. tmpDest, ptr
6147 // srw dest, tmpDest, shift
6148 if (ptrA != ZeroReg) {
6149 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6150 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6151 .addReg(ptrA).addReg(ptrB);
6155 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6156 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6157 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6158 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6160 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6161 .addReg(Ptr1Reg).addImm(0).addImm(61);
6163 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6164 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6165 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6166 .addReg(newval).addReg(ShiftReg);
6167 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6168 .addReg(oldval).addReg(ShiftReg);
6170 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6172 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6173 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6174 .addReg(Mask3Reg).addImm(65535);
6176 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6177 .addReg(Mask2Reg).addReg(ShiftReg);
6178 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6179 .addReg(NewVal2Reg).addReg(MaskReg);
6180 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6181 .addReg(OldVal2Reg).addReg(MaskReg);
6184 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6185 .addReg(ZeroReg).addReg(PtrReg);
6186 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6187 .addReg(TmpDestReg).addReg(MaskReg);
6188 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6189 .addReg(TmpReg).addReg(OldVal3Reg);
6190 BuildMI(BB, dl, TII->get(PPC::BCC))
6191 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6192 BB->addSuccessor(loop2MBB);
6193 BB->addSuccessor(midMBB);
6196 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6197 .addReg(TmpDestReg).addReg(MaskReg);
6198 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6199 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6200 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6201 .addReg(ZeroReg).addReg(PtrReg);
6202 BuildMI(BB, dl, TII->get(PPC::BCC))
6203 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6204 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6205 BB->addSuccessor(loop1MBB);
6206 BB->addSuccessor(exitMBB);
6209 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6210 .addReg(ZeroReg).addReg(PtrReg);
6211 BB->addSuccessor(exitMBB);
6216 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6219 llvm_unreachable("Unexpected instr type to insert");
6222 MI->eraseFromParent(); // The pseudo instruction is gone now.
6226 //===----------------------------------------------------------------------===//
6227 // Target Optimization Hooks
6228 //===----------------------------------------------------------------------===//
6230 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6231 DAGCombinerInfo &DCI) const {
6232 const TargetMachine &TM = getTargetMachine();
6233 SelectionDAG &DAG = DCI.DAG;
6234 DebugLoc dl = N->getDebugLoc();
6235 switch (N->getOpcode()) {
6238 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6239 if (C->isNullValue()) // 0 << V -> 0.
6240 return N->getOperand(0);
6244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6245 if (C->isNullValue()) // 0 >>u V -> 0.
6246 return N->getOperand(0);
6250 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6251 if (C->isNullValue() || // 0 >>s V -> 0.
6252 C->isAllOnesValue()) // -1 >>s V -> -1.
6253 return N->getOperand(0);
6257 case ISD::SINT_TO_FP:
6258 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
6259 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
6260 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
6261 // We allow the src/dst to be either f32/f64, but the intermediate
6262 // type must be i64.
6263 if (N->getOperand(0).getValueType() == MVT::i64 &&
6264 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
6265 SDValue Val = N->getOperand(0).getOperand(0);
6266 if (Val.getValueType() == MVT::f32) {
6267 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6268 DCI.AddToWorklist(Val.getNode());
6271 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
6272 DCI.AddToWorklist(Val.getNode());
6273 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
6274 DCI.AddToWorklist(Val.getNode());
6275 if (N->getValueType(0) == MVT::f32) {
6276 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
6277 DAG.getIntPtrConstant(0));
6278 DCI.AddToWorklist(Val.getNode());
6281 } else if (N->getOperand(0).getValueType() == MVT::i32) {
6282 // If the intermediate type is i32, we can avoid the load/store here
6289 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
6290 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
6291 !cast<StoreSDNode>(N)->isTruncatingStore() &&
6292 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
6293 N->getOperand(1).getValueType() == MVT::i32 &&
6294 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
6295 SDValue Val = N->getOperand(1).getOperand(0);
6296 if (Val.getValueType() == MVT::f32) {
6297 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
6298 DCI.AddToWorklist(Val.getNode());
6300 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
6301 DCI.AddToWorklist(Val.getNode());
6303 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
6304 N->getOperand(2), N->getOperand(3));
6305 DCI.AddToWorklist(Val.getNode());
6309 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
6310 if (cast<StoreSDNode>(N)->isUnindexed() &&
6311 N->getOperand(1).getOpcode() == ISD::BSWAP &&
6312 N->getOperand(1).getNode()->hasOneUse() &&
6313 (N->getOperand(1).getValueType() == MVT::i32 ||
6314 N->getOperand(1).getValueType() == MVT::i16)) {
6315 SDValue BSwapOp = N->getOperand(1).getOperand(0);
6316 // Do an any-extend to 32-bits if this is a half-word input.
6317 if (BSwapOp.getValueType() == MVT::i16)
6318 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
6321 N->getOperand(0), BSwapOp, N->getOperand(2),
6322 DAG.getValueType(N->getOperand(1).getValueType())
6325 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
6326 Ops, array_lengthof(Ops),
6327 cast<StoreSDNode>(N)->getMemoryVT(),
6328 cast<StoreSDNode>(N)->getMemOperand());
6332 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
6333 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
6334 N->getOperand(0).hasOneUse() &&
6335 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
6336 SDValue Load = N->getOperand(0);
6337 LoadSDNode *LD = cast<LoadSDNode>(Load);
6338 // Create the byte-swapping load.
6340 LD->getChain(), // Chain
6341 LD->getBasePtr(), // Ptr
6342 DAG.getValueType(N->getValueType(0)) // VT
6345 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
6346 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
6347 LD->getMemoryVT(), LD->getMemOperand());
6349 // If this is an i16 load, insert the truncate.
6350 SDValue ResVal = BSLoad;
6351 if (N->getValueType(0) == MVT::i16)
6352 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
6354 // First, combine the bswap away. This makes the value produced by the
6356 DCI.CombineTo(N, ResVal);
6358 // Next, combine the load away, we give it a bogus result value but a real
6359 // chain result. The result value is dead because the bswap is dead.
6360 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
6362 // Return N so it doesn't get rechecked!
6363 return SDValue(N, 0);
6367 case PPCISD::VCMP: {
6368 // If a VCMPo node already exists with exactly the same operands as this
6369 // node, use its result instead of this node (VCMPo computes both a CR6 and
6370 // a normal output).
6372 if (!N->getOperand(0).hasOneUse() &&
6373 !N->getOperand(1).hasOneUse() &&
6374 !N->getOperand(2).hasOneUse()) {
6376 // Scan all of the users of the LHS, looking for VCMPo's that match.
6377 SDNode *VCMPoNode = 0;
6379 SDNode *LHSN = N->getOperand(0).getNode();
6380 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
6382 if (UI->getOpcode() == PPCISD::VCMPo &&
6383 UI->getOperand(1) == N->getOperand(1) &&
6384 UI->getOperand(2) == N->getOperand(2) &&
6385 UI->getOperand(0) == N->getOperand(0)) {
6390 // If there is no VCMPo node, or if the flag value has a single use, don't
6392 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
6395 // Look at the (necessarily single) use of the flag value. If it has a
6396 // chain, this transformation is more complex. Note that multiple things
6397 // could use the value result, which we should ignore.
6398 SDNode *FlagUser = 0;
6399 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
6400 FlagUser == 0; ++UI) {
6401 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
6403 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
6404 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
6411 // If the user is a MFCR instruction, we know this is safe. Otherwise we
6412 // give up for right now.
6413 if (FlagUser->getOpcode() == PPCISD::MFCR)
6414 return SDValue(VCMPoNode, 0);
6419 // If this is a branch on an altivec predicate comparison, lower this so
6420 // that we don't have to do a MFCR: instead, branch directly on CR6. This
6421 // lowering is done pre-legalize, because the legalizer lowers the predicate
6422 // compare down to code that is difficult to reassemble.
6423 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
6424 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
6428 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
6429 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
6430 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
6431 assert(isDot && "Can't compare against a vector result!");
6433 // If this is a comparison against something other than 0/1, then we know
6434 // that the condition is never/always true.
6435 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
6436 if (Val != 0 && Val != 1) {
6437 if (CC == ISD::SETEQ) // Cond never true, remove branch.
6438 return N->getOperand(0);
6439 // Always !=, turn it into an unconditional branch.
6440 return DAG.getNode(ISD::BR, dl, MVT::Other,
6441 N->getOperand(0), N->getOperand(4));
6444 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
6446 // Create the PPCISD altivec 'dot' comparison node.
6447 std::vector<EVT> VTs;
6449 LHS.getOperand(2), // LHS of compare
6450 LHS.getOperand(3), // RHS of compare
6451 DAG.getConstant(CompareOpc, MVT::i32)
6453 VTs.push_back(LHS.getOperand(2).getValueType());
6454 VTs.push_back(MVT::Glue);
6455 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
6457 // Unpack the result based on how the target uses it.
6458 PPC::Predicate CompOpc;
6459 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
6460 default: // Can't happen, don't crash on invalid number though.
6461 case 0: // Branch on the value of the EQ bit of CR6.
6462 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
6464 case 1: // Branch on the inverted value of the EQ bit of CR6.
6465 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
6467 case 2: // Branch on the value of the LT bit of CR6.
6468 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
6470 case 3: // Branch on the inverted value of the LT bit of CR6.
6471 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
6475 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
6476 DAG.getConstant(CompOpc, MVT::i32),
6477 DAG.getRegister(PPC::CR6, MVT::i32),
6478 N->getOperand(4), CompNode.getValue(1));
6487 //===----------------------------------------------------------------------===//
6488 // Inline Assembly Support
6489 //===----------------------------------------------------------------------===//
6491 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
6494 const SelectionDAG &DAG,
6495 unsigned Depth) const {
6496 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
6497 switch (Op.getOpcode()) {
6499 case PPCISD::LBRX: {
6500 // lhbrx is known to have the top bits cleared out.
6501 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
6502 KnownZero = 0xFFFF0000;
6505 case ISD::INTRINSIC_WO_CHAIN: {
6506 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
6508 case Intrinsic::ppc_altivec_vcmpbfp_p:
6509 case Intrinsic::ppc_altivec_vcmpeqfp_p:
6510 case Intrinsic::ppc_altivec_vcmpequb_p:
6511 case Intrinsic::ppc_altivec_vcmpequh_p:
6512 case Intrinsic::ppc_altivec_vcmpequw_p:
6513 case Intrinsic::ppc_altivec_vcmpgefp_p:
6514 case Intrinsic::ppc_altivec_vcmpgtfp_p:
6515 case Intrinsic::ppc_altivec_vcmpgtsb_p:
6516 case Intrinsic::ppc_altivec_vcmpgtsh_p:
6517 case Intrinsic::ppc_altivec_vcmpgtsw_p:
6518 case Intrinsic::ppc_altivec_vcmpgtub_p:
6519 case Intrinsic::ppc_altivec_vcmpgtuh_p:
6520 case Intrinsic::ppc_altivec_vcmpgtuw_p:
6521 KnownZero = ~1U; // All bits but the low one are known to be zero.
6529 /// getConstraintType - Given a constraint, return the type of
6530 /// constraint it is for this target.
6531 PPCTargetLowering::ConstraintType
6532 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
6533 if (Constraint.size() == 1) {
6534 switch (Constraint[0]) {
6541 return C_RegisterClass;
6543 // FIXME: While Z does indicate a memory constraint, it specifically
6544 // indicates an r+r address (used in conjunction with the 'y' modifier
6545 // in the replacement string). Currently, we're forcing the base
6546 // register to be r0 in the asm printer (which is interpreted as zero)
6547 // and forming the complete address in the second register. This is
6552 return TargetLowering::getConstraintType(Constraint);
6555 /// Examine constraint type and operand type and determine a weight value.
6556 /// This object must already have been set up with the operand type
6557 /// and the current alternative constraint selected.
6558 TargetLowering::ConstraintWeight
6559 PPCTargetLowering::getSingleConstraintMatchWeight(
6560 AsmOperandInfo &info, const char *constraint) const {
6561 ConstraintWeight weight = CW_Invalid;
6562 Value *CallOperandVal = info.CallOperandVal;
6563 // If we don't have a value, we can't do a match,
6564 // but allow it at the lowest weight.
6565 if (CallOperandVal == NULL)
6567 Type *type = CallOperandVal->getType();
6568 // Look at the constraint type.
6569 switch (*constraint) {
6571 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
6574 if (type->isIntegerTy())
6575 weight = CW_Register;
6578 if (type->isFloatTy())
6579 weight = CW_Register;
6582 if (type->isDoubleTy())
6583 weight = CW_Register;
6586 if (type->isVectorTy())
6587 weight = CW_Register;
6590 weight = CW_Register;
6599 std::pair<unsigned, const TargetRegisterClass*>
6600 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
6602 if (Constraint.size() == 1) {
6603 // GCC RS6000 Constraint Letters
6604 switch (Constraint[0]) {
6607 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
6608 return std::make_pair(0U, &PPC::G8RCRegClass);
6609 return std::make_pair(0U, &PPC::GPRCRegClass);
6611 if (VT == MVT::f32 || VT == MVT::i32)
6612 return std::make_pair(0U, &PPC::F4RCRegClass);
6613 if (VT == MVT::f64 || VT == MVT::i64)
6614 return std::make_pair(0U, &PPC::F8RCRegClass);
6617 return std::make_pair(0U, &PPC::VRRCRegClass);
6619 return std::make_pair(0U, &PPC::CRRCRegClass);
6623 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
6627 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
6628 /// vector. If it is invalid, don't add anything to Ops.
6629 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
6630 std::string &Constraint,
6631 std::vector<SDValue>&Ops,
6632 SelectionDAG &DAG) const {
6633 SDValue Result(0,0);
6635 // Only support length 1 constraints.
6636 if (Constraint.length() > 1) return;
6638 char Letter = Constraint[0];
6649 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
6650 if (!CST) return; // Must be an immediate to match.
6651 unsigned Value = CST->getZExtValue();
6653 default: llvm_unreachable("Unknown constraint letter!");
6654 case 'I': // "I" is a signed 16-bit constant.
6655 if ((short)Value == (int)Value)
6656 Result = DAG.getTargetConstant(Value, Op.getValueType());
6658 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
6659 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
6660 if ((short)Value == 0)
6661 Result = DAG.getTargetConstant(Value, Op.getValueType());
6663 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
6664 if ((Value >> 16) == 0)
6665 Result = DAG.getTargetConstant(Value, Op.getValueType());
6667 case 'M': // "M" is a constant that is greater than 31.
6669 Result = DAG.getTargetConstant(Value, Op.getValueType());
6671 case 'N': // "N" is a positive constant that is an exact power of two.
6672 if ((int)Value > 0 && isPowerOf2_32(Value))
6673 Result = DAG.getTargetConstant(Value, Op.getValueType());
6675 case 'O': // "O" is the constant zero.
6677 Result = DAG.getTargetConstant(Value, Op.getValueType());
6679 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
6680 if ((short)-Value == (int)-Value)
6681 Result = DAG.getTargetConstant(Value, Op.getValueType());
6688 if (Result.getNode()) {
6689 Ops.push_back(Result);
6693 // Handle standard constraint letters.
6694 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
6697 // isLegalAddressingMode - Return true if the addressing mode represented
6698 // by AM is legal for this target, for a load/store of the specified type.
6699 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
6701 // FIXME: PPC does not allow r+i addressing modes for vectors!
6703 // PPC allows a sign-extended 16-bit immediate field.
6704 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
6707 // No global is ever allowed as a base.
6711 // PPC only support r+r,
6713 case 0: // "r+i" or just "i", depending on HasBaseReg.
6716 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
6718 // Otherwise we have r+r or r+i.
6721 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
6723 // Allow 2*r as r+r.
6726 // No other scales are supported.
6733 /// isLegalAddressImmediate - Return true if the integer value can be used
6734 /// as the offset of the target addressing mode for load / store of the
6736 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
6737 // PPC allows a sign-extended 16-bit immediate field.
6738 return (V > -(1 << 16) && V < (1 << 16)-1);
6741 bool PPCTargetLowering::isLegalAddressImmediate(GlobalValue* GV) const {
6745 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
6746 SelectionDAG &DAG) const {
6747 MachineFunction &MF = DAG.getMachineFunction();
6748 MachineFrameInfo *MFI = MF.getFrameInfo();
6749 MFI->setReturnAddressIsTaken(true);
6751 DebugLoc dl = Op.getDebugLoc();
6752 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6754 // Make sure the function does not optimize away the store of the RA to
6756 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
6757 FuncInfo->setLRStoreRequired();
6758 bool isPPC64 = PPCSubTarget.isPPC64();
6759 bool isDarwinABI = PPCSubTarget.isDarwinABI();
6762 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
6765 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
6766 isPPC64? MVT::i64 : MVT::i32);
6767 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6768 DAG.getNode(ISD::ADD, dl, getPointerTy(),
6770 MachinePointerInfo(), false, false, false, 0);
6773 // Just load the return address off the stack.
6774 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
6775 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
6776 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
6779 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
6780 SelectionDAG &DAG) const {
6781 DebugLoc dl = Op.getDebugLoc();
6782 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
6784 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
6785 bool isPPC64 = PtrVT == MVT::i64;
6787 MachineFunction &MF = DAG.getMachineFunction();
6788 MachineFrameInfo *MFI = MF.getFrameInfo();
6789 MFI->setFrameAddressIsTaken(true);
6790 bool is31 = (getTargetMachine().Options.DisableFramePointerElim(MF) ||
6791 MFI->hasVarSizedObjects()) &&
6792 MFI->getStackSize() &&
6793 !MF.getFunction()->getFnAttributes().
6794 hasAttribute(Attributes::Naked);
6795 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
6796 (is31 ? PPC::R31 : PPC::R1);
6797 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
6800 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
6801 FrameAddr, MachinePointerInfo(), false, false,
6807 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
6808 // The PowerPC target isn't yet aware of offsets.
6812 /// getOptimalMemOpType - Returns the target specific optimal type for load
6813 /// and store operations as a result of memset, memcpy, and memmove
6814 /// lowering. If DstAlign is zero that means it's safe to destination
6815 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
6816 /// means there isn't a need to check it against alignment requirement,
6817 /// probably because the source does not need to be loaded. If 'IsMemset' is
6818 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
6819 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
6820 /// source is constant so it does not need to be loaded.
6821 /// It returns EVT::Other if the type should be determined using generic
6822 /// target-independent logic.
6823 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
6824 unsigned DstAlign, unsigned SrcAlign,
6825 bool IsMemset, bool ZeroMemset,
6827 MachineFunction &MF) const {
6828 if (this->PPCSubTarget.isPPC64()) {
6835 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
6836 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
6837 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
6838 /// is expanded to mul + add.
6839 bool PPCTargetLowering::isFMAFasterThanMulAndAdd(EVT VT) const {
6843 switch (VT.getSimpleVT().SimpleTy) {
6855 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
6857 return TargetLowering::getSchedulingPreference(N);