1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAG.h"
27 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/Intrinsics.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/MathExtras.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetOptions.h"
40 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
41 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
43 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
44 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
46 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
47 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
49 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
50 if (TM.getSubtargetImpl()->isDarwin())
51 return new TargetLoweringObjectFileMachO();
53 if (TM.getSubtargetImpl()->isSVR4ABI())
54 return new PPC64LinuxTargetObjectFile();
56 return new TargetLoweringObjectFileELF();
59 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
60 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
61 const PPCSubtarget *Subtarget = &TM.getSubtarget<PPCSubtarget>();
65 // Use _setjmp/_longjmp instead of setjmp/longjmp.
66 setUseUnderscoreSetJmp(true);
67 setUseUnderscoreLongJmp(true);
69 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
70 // arguments are at least 4/8 bytes aligned.
71 bool isPPC64 = Subtarget->isPPC64();
72 setMinStackArgumentAlignment(isPPC64 ? 8:4);
74 // Set up the register classes.
75 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
76 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
77 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
79 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
80 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
83 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
85 // PowerPC has pre-inc load and store's.
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
97 // This is used in the ppcf128->int sequence. Note it has different semantics
98 // from FP_ROUND: that rounds to nearest, this rounds to zero.
99 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
101 // We do not currently implement these libm ops for PowerPC.
102 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
103 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
104 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
105 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
106 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
107 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
109 // PowerPC has no SREM/UREM instructions
110 setOperationAction(ISD::SREM, MVT::i32, Expand);
111 setOperationAction(ISD::UREM, MVT::i32, Expand);
112 setOperationAction(ISD::SREM, MVT::i64, Expand);
113 setOperationAction(ISD::UREM, MVT::i64, Expand);
115 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
118 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
119 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
122 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
123 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
125 // We don't support sin/cos/sqrt/fmod/pow
126 setOperationAction(ISD::FSIN , MVT::f64, Expand);
127 setOperationAction(ISD::FCOS , MVT::f64, Expand);
128 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
129 setOperationAction(ISD::FREM , MVT::f64, Expand);
130 setOperationAction(ISD::FPOW , MVT::f64, Expand);
131 setOperationAction(ISD::FMA , MVT::f64, Legal);
132 setOperationAction(ISD::FSIN , MVT::f32, Expand);
133 setOperationAction(ISD::FCOS , MVT::f32, Expand);
134 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
135 setOperationAction(ISD::FREM , MVT::f32, Expand);
136 setOperationAction(ISD::FPOW , MVT::f32, Expand);
137 setOperationAction(ISD::FMA , MVT::f32, Legal);
139 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
141 // If we're enabling GP optimizations, use hardware square root
142 if (!Subtarget->hasFSQRT() &&
143 !(TM.Options.UnsafeFPMath &&
144 Subtarget->hasFRSQRTE() && Subtarget->hasFRE()))
145 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
147 if (!Subtarget->hasFSQRT() &&
148 !(TM.Options.UnsafeFPMath &&
149 Subtarget->hasFRSQRTES() && Subtarget->hasFRES()))
150 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
152 if (Subtarget->hasFCPSGN()) {
153 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
154 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
156 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
157 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
160 if (Subtarget->hasFPRND()) {
161 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
162 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
163 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
164 setOperationAction(ISD::FROUND, MVT::f64, Legal);
166 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
167 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
168 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
169 setOperationAction(ISD::FROUND, MVT::f32, Legal);
172 // PowerPC does not have BSWAP, CTPOP or CTTZ
173 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
174 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
175 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
176 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
177 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
178 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
179 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
180 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
182 if (Subtarget->hasPOPCNTD()) {
183 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
184 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
186 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
187 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
190 // PowerPC does not have ROTR
191 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
192 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
194 // PowerPC does not have Select
195 setOperationAction(ISD::SELECT, MVT::i32, Expand);
196 setOperationAction(ISD::SELECT, MVT::i64, Expand);
197 setOperationAction(ISD::SELECT, MVT::f32, Expand);
198 setOperationAction(ISD::SELECT, MVT::f64, Expand);
200 // PowerPC wants to turn select_cc of FP into fsel when possible.
201 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
202 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
204 // PowerPC wants to optimize integer setcc a bit
205 setOperationAction(ISD::SETCC, MVT::i32, Custom);
207 // PowerPC does not have BRCOND which requires SetCC
208 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
210 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
212 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
213 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
215 // PowerPC does not have [U|S]INT_TO_FP
216 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
217 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
219 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
220 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
221 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
222 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
224 // We cannot sextinreg(i1). Expand to shifts.
225 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
227 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
228 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
229 // support continuation, user-level threading, and etc.. As a result, no
230 // other SjLj exception interfaces are implemented and please don't build
231 // your own exception handling based on them.
232 // LLVM/Clang supports zero-cost DWARF exception handling.
233 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
234 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
236 // We want to legalize GlobalAddress and ConstantPool nodes into the
237 // appropriate instructions to materialize the address.
238 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
239 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
240 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
241 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
242 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
243 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
244 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
245 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
246 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
247 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
250 setOperationAction(ISD::TRAP, MVT::Other, Legal);
252 // TRAMPOLINE is custom lowered.
253 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
254 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
256 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
257 setOperationAction(ISD::VASTART , MVT::Other, Custom);
259 if (Subtarget->isSVR4ABI()) {
261 // VAARG always uses double-word chunks, so promote anything smaller.
262 setOperationAction(ISD::VAARG, MVT::i1, Promote);
263 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
264 setOperationAction(ISD::VAARG, MVT::i8, Promote);
265 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
266 setOperationAction(ISD::VAARG, MVT::i16, Promote);
267 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
268 setOperationAction(ISD::VAARG, MVT::i32, Promote);
269 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
270 setOperationAction(ISD::VAARG, MVT::Other, Expand);
272 // VAARG is custom lowered with the 32-bit SVR4 ABI.
273 setOperationAction(ISD::VAARG, MVT::Other, Custom);
274 setOperationAction(ISD::VAARG, MVT::i64, Custom);
277 setOperationAction(ISD::VAARG, MVT::Other, Expand);
279 if (Subtarget->isSVR4ABI() && !isPPC64)
280 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
281 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
283 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
285 // Use the default implementation.
286 setOperationAction(ISD::VAEND , MVT::Other, Expand);
287 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
288 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
289 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
290 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
292 // We want to custom lower some of our intrinsics.
293 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
295 // To handle counter-based loop conditions.
296 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
298 // Comparisons that require checking two conditions.
299 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
300 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
301 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
302 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
303 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
304 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
305 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
306 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
307 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
308 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
309 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
310 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
312 if (Subtarget->has64BitSupport()) {
313 // They also have instructions for converting between i64 and fp.
314 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
315 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
316 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
317 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
318 // This is just the low 32 bits of a (signed) fp->i64 conversion.
319 // We cannot do this with Promote because i64 is not a legal type.
320 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
322 if (PPCSubTarget.hasLFIWAX() || Subtarget->isPPC64())
323 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
325 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
326 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
329 // With the instructions enabled under FPCVT, we can do everything.
330 if (PPCSubTarget.hasFPCVT()) {
331 if (Subtarget->has64BitSupport()) {
332 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
333 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
334 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
335 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
338 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
339 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
340 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
341 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
344 if (Subtarget->use64BitRegs()) {
345 // 64-bit PowerPC implementations can support i64 types directly
346 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
347 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
348 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
349 // 64-bit PowerPC wants to expand i128 shifts itself.
350 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
351 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
352 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
354 // 32-bit PowerPC wants to expand i64 shifts itself.
355 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
356 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
357 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
360 if (Subtarget->hasAltivec()) {
361 // First set operation action for all vector types to expand. Then we
362 // will selectively turn on ones that can be effectively codegen'd.
363 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
364 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
365 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
367 // add/sub are legal for all supported vector VT's.
368 setOperationAction(ISD::ADD , VT, Legal);
369 setOperationAction(ISD::SUB , VT, Legal);
371 // We promote all shuffles to v16i8.
372 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
373 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
375 // We promote all non-typed operations to v4i32.
376 setOperationAction(ISD::AND , VT, Promote);
377 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
378 setOperationAction(ISD::OR , VT, Promote);
379 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
380 setOperationAction(ISD::XOR , VT, Promote);
381 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
382 setOperationAction(ISD::LOAD , VT, Promote);
383 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
384 setOperationAction(ISD::SELECT, VT, Promote);
385 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
386 setOperationAction(ISD::STORE, VT, Promote);
387 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
389 // No other operations are legal.
390 setOperationAction(ISD::MUL , VT, Expand);
391 setOperationAction(ISD::SDIV, VT, Expand);
392 setOperationAction(ISD::SREM, VT, Expand);
393 setOperationAction(ISD::UDIV, VT, Expand);
394 setOperationAction(ISD::UREM, VT, Expand);
395 setOperationAction(ISD::FDIV, VT, Expand);
396 setOperationAction(ISD::FREM, VT, Expand);
397 setOperationAction(ISD::FNEG, VT, Expand);
398 setOperationAction(ISD::FSQRT, VT, Expand);
399 setOperationAction(ISD::FLOG, VT, Expand);
400 setOperationAction(ISD::FLOG10, VT, Expand);
401 setOperationAction(ISD::FLOG2, VT, Expand);
402 setOperationAction(ISD::FEXP, VT, Expand);
403 setOperationAction(ISD::FEXP2, VT, Expand);
404 setOperationAction(ISD::FSIN, VT, Expand);
405 setOperationAction(ISD::FCOS, VT, Expand);
406 setOperationAction(ISD::FABS, VT, Expand);
407 setOperationAction(ISD::FPOWI, VT, Expand);
408 setOperationAction(ISD::FFLOOR, VT, Expand);
409 setOperationAction(ISD::FCEIL, VT, Expand);
410 setOperationAction(ISD::FTRUNC, VT, Expand);
411 setOperationAction(ISD::FRINT, VT, Expand);
412 setOperationAction(ISD::FNEARBYINT, VT, Expand);
413 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
414 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
415 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
416 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
417 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
418 setOperationAction(ISD::UDIVREM, VT, Expand);
419 setOperationAction(ISD::SDIVREM, VT, Expand);
420 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
421 setOperationAction(ISD::FPOW, VT, Expand);
422 setOperationAction(ISD::CTPOP, VT, Expand);
423 setOperationAction(ISD::CTLZ, VT, Expand);
424 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
425 setOperationAction(ISD::CTTZ, VT, Expand);
426 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
427 setOperationAction(ISD::VSELECT, VT, Expand);
428 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
430 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
431 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
432 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
433 setTruncStoreAction(VT, InnerVT, Expand);
435 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
436 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
437 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
440 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
441 // with merges, splats, etc.
442 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
444 setOperationAction(ISD::AND , MVT::v4i32, Legal);
445 setOperationAction(ISD::OR , MVT::v4i32, Legal);
446 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
447 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
448 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
449 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
450 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
451 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
452 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
453 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
454 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
455 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
456 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
457 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
459 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
460 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
461 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
462 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
464 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
465 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
467 if (TM.Options.UnsafeFPMath) {
468 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
469 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
472 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
473 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
474 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
476 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
477 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
479 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
480 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
481 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
482 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
484 // Altivec does not contain unordered floating-point compare instructions
485 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
486 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
487 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
488 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
489 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
490 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
492 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
493 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
496 if (Subtarget->has64BitSupport()) {
497 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
498 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
501 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
502 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
503 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
504 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
506 setBooleanContents(ZeroOrOneBooleanContent);
507 // Altivec instructions set fields to all zeros or all ones.
508 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
511 setStackPointerRegisterToSaveRestore(PPC::X1);
512 setExceptionPointerRegister(PPC::X3);
513 setExceptionSelectorRegister(PPC::X4);
515 setStackPointerRegisterToSaveRestore(PPC::R1);
516 setExceptionPointerRegister(PPC::R3);
517 setExceptionSelectorRegister(PPC::R4);
520 // We have target-specific dag combine patterns for the following nodes:
521 setTargetDAGCombine(ISD::SINT_TO_FP);
522 setTargetDAGCombine(ISD::LOAD);
523 setTargetDAGCombine(ISD::STORE);
524 setTargetDAGCombine(ISD::BR_CC);
525 setTargetDAGCombine(ISD::BSWAP);
526 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
528 // Use reciprocal estimates.
529 if (TM.Options.UnsafeFPMath) {
530 setTargetDAGCombine(ISD::FDIV);
531 setTargetDAGCombine(ISD::FSQRT);
534 // Darwin long double math library functions have $LDBL128 appended.
535 if (Subtarget->isDarwin()) {
536 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
537 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
538 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
539 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
540 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
541 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
542 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
543 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
544 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
545 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
548 setMinFunctionAlignment(2);
549 if (PPCSubTarget.isDarwin())
550 setPrefFunctionAlignment(4);
552 if (isPPC64 && Subtarget->isJITCodeModel())
553 // Temporary workaround for the inability of PPC64 JIT to handle jump
555 setSupportJumpTables(false);
557 setInsertFencesForAtomic(true);
559 if (Subtarget->enableMachineScheduler())
560 setSchedulingPreference(Sched::Source);
562 setSchedulingPreference(Sched::Hybrid);
564 computeRegisterProperties();
566 // The Freescale cores does better with aggressive inlining of memcpy and
567 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
568 if (Subtarget->getDarwinDirective() == PPC::DIR_E500mc ||
569 Subtarget->getDarwinDirective() == PPC::DIR_E5500) {
570 MaxStoresPerMemset = 32;
571 MaxStoresPerMemsetOptSize = 16;
572 MaxStoresPerMemcpy = 32;
573 MaxStoresPerMemcpyOptSize = 8;
574 MaxStoresPerMemmove = 32;
575 MaxStoresPerMemmoveOptSize = 8;
577 setPrefFunctionAlignment(4);
581 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
582 /// the desired ByVal argument alignment.
583 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
584 unsigned MaxMaxAlign) {
585 if (MaxAlign == MaxMaxAlign)
587 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
588 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
590 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
592 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
593 unsigned EltAlign = 0;
594 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
595 if (EltAlign > MaxAlign)
597 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
598 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
599 unsigned EltAlign = 0;
600 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
601 if (EltAlign > MaxAlign)
603 if (MaxAlign == MaxMaxAlign)
609 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
610 /// function arguments in the caller parameter area.
611 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
612 // Darwin passes everything on 4 byte boundary.
613 if (PPCSubTarget.isDarwin())
616 // 16byte and wider vectors are passed on 16byte boundary.
617 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
618 unsigned Align = PPCSubTarget.isPPC64() ? 8 : 4;
619 if (PPCSubTarget.hasAltivec() || PPCSubTarget.hasQPX())
620 getMaxByValAlign(Ty, Align, PPCSubTarget.hasQPX() ? 32 : 16);
624 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
627 case PPCISD::FSEL: return "PPCISD::FSEL";
628 case PPCISD::FCFID: return "PPCISD::FCFID";
629 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
630 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
631 case PPCISD::FRE: return "PPCISD::FRE";
632 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
633 case PPCISD::STFIWX: return "PPCISD::STFIWX";
634 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
635 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
636 case PPCISD::VPERM: return "PPCISD::VPERM";
637 case PPCISD::Hi: return "PPCISD::Hi";
638 case PPCISD::Lo: return "PPCISD::Lo";
639 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
640 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
641 case PPCISD::LOAD: return "PPCISD::LOAD";
642 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
643 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
644 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
645 case PPCISD::SRL: return "PPCISD::SRL";
646 case PPCISD::SRA: return "PPCISD::SRA";
647 case PPCISD::SHL: return "PPCISD::SHL";
648 case PPCISD::CALL: return "PPCISD::CALL";
649 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
650 case PPCISD::MTCTR: return "PPCISD::MTCTR";
651 case PPCISD::BCTRL: return "PPCISD::BCTRL";
652 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
653 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
654 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
655 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
656 case PPCISD::VCMP: return "PPCISD::VCMP";
657 case PPCISD::VCMPo: return "PPCISD::VCMPo";
658 case PPCISD::LBRX: return "PPCISD::LBRX";
659 case PPCISD::STBRX: return "PPCISD::STBRX";
660 case PPCISD::LARX: return "PPCISD::LARX";
661 case PPCISD::STCX: return "PPCISD::STCX";
662 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
663 case PPCISD::BDNZ: return "PPCISD::BDNZ";
664 case PPCISD::BDZ: return "PPCISD::BDZ";
665 case PPCISD::MFFS: return "PPCISD::MFFS";
666 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
667 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
668 case PPCISD::CR6SET: return "PPCISD::CR6SET";
669 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
670 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
671 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
672 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
673 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
674 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
675 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
676 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
677 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
678 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
679 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
680 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
681 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
682 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
683 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
684 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
685 case PPCISD::SC: return "PPCISD::SC";
689 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
692 return VT.changeVectorElementTypeToInteger();
695 //===----------------------------------------------------------------------===//
696 // Node matching predicates, for use by the tblgen matching code.
697 //===----------------------------------------------------------------------===//
699 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
700 static bool isFloatingPointZero(SDValue Op) {
701 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
702 return CFP->getValueAPF().isZero();
703 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
704 // Maybe this has already been legalized into the constant pool?
705 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
706 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
707 return CFP->getValueAPF().isZero();
712 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
713 /// true if Op is undef or if it matches the specified value.
714 static bool isConstantOrUndef(int Op, int Val) {
715 return Op < 0 || Op == Val;
718 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
719 /// VPKUHUM instruction.
720 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
722 for (unsigned i = 0; i != 16; ++i)
723 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
726 for (unsigned i = 0; i != 8; ++i)
727 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
728 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
734 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
735 /// VPKUWUM instruction.
736 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
738 for (unsigned i = 0; i != 16; i += 2)
739 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
740 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
743 for (unsigned i = 0; i != 8; i += 2)
744 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
745 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
746 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
747 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
753 /// isVMerge - Common function, used to match vmrg* shuffles.
755 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
756 unsigned LHSStart, unsigned RHSStart) {
757 assert(N->getValueType(0) == MVT::v16i8 &&
758 "PPC only supports shuffles by bytes!");
759 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
760 "Unsupported merge size!");
762 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
763 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
764 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
765 LHSStart+j+i*UnitSize) ||
766 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
767 RHSStart+j+i*UnitSize))
773 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
774 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
775 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
778 return isVMerge(N, UnitSize, 8, 24);
779 return isVMerge(N, UnitSize, 8, 8);
782 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
783 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
784 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
787 return isVMerge(N, UnitSize, 0, 16);
788 return isVMerge(N, UnitSize, 0, 0);
792 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
793 /// amount, otherwise return -1.
794 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
795 assert(N->getValueType(0) == MVT::v16i8 &&
796 "PPC only supports shuffles by bytes!");
798 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
800 // Find the first non-undef value in the shuffle mask.
802 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
805 if (i == 16) return -1; // all undef.
807 // Otherwise, check to see if the rest of the elements are consecutively
808 // numbered from this value.
809 unsigned ShiftAmt = SVOp->getMaskElt(i);
810 if (ShiftAmt < i) return -1;
814 // Check the rest of the elements to see if they are consecutive.
815 for (++i; i != 16; ++i)
816 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
819 // Check the rest of the elements to see if they are consecutive.
820 for (++i; i != 16; ++i)
821 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
827 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
828 /// specifies a splat of a single element that is suitable for input to
829 /// VSPLTB/VSPLTH/VSPLTW.
830 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
831 assert(N->getValueType(0) == MVT::v16i8 &&
832 (EltSize == 1 || EltSize == 2 || EltSize == 4));
834 // This is a splat operation if each element of the permute is the same, and
835 // if the value doesn't reference the second vector.
836 unsigned ElementBase = N->getMaskElt(0);
838 // FIXME: Handle UNDEF elements too!
839 if (ElementBase >= 16)
842 // Check that the indices are consecutive, in the case of a multi-byte element
843 // splatted with a v16i8 mask.
844 for (unsigned i = 1; i != EltSize; ++i)
845 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
848 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
849 if (N->getMaskElt(i) < 0) continue;
850 for (unsigned j = 0; j != EltSize; ++j)
851 if (N->getMaskElt(i+j) != N->getMaskElt(j))
857 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
859 bool PPC::isAllNegativeZeroVector(SDNode *N) {
860 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
862 APInt APVal, APUndef;
866 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
867 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
868 return CFP->getValueAPF().isNegZero();
873 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
874 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
875 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
876 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
877 assert(isSplatShuffleMask(SVOp, EltSize));
878 return SVOp->getMaskElt(0) / EltSize;
881 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
882 /// by using a vspltis[bhw] instruction of the specified element size, return
883 /// the constant being splatted. The ByteSize field indicates the number of
884 /// bytes of each element [124] -> [bhw].
885 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
888 // If ByteSize of the splat is bigger than the element size of the
889 // build_vector, then we have a case where we are checking for a splat where
890 // multiple elements of the buildvector are folded together into a single
891 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
892 unsigned EltSize = 16/N->getNumOperands();
893 if (EltSize < ByteSize) {
894 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
895 SDValue UniquedVals[4];
896 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
898 // See if all of the elements in the buildvector agree across.
899 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
900 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
901 // If the element isn't a constant, bail fully out.
902 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
905 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
906 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
907 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
908 return SDValue(); // no match.
911 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
912 // either constant or undef values that are identical for each chunk. See
913 // if these chunks can form into a larger vspltis*.
915 // Check to see if all of the leading entries are either 0 or -1. If
916 // neither, then this won't fit into the immediate field.
917 bool LeadingZero = true;
918 bool LeadingOnes = true;
919 for (unsigned i = 0; i != Multiple-1; ++i) {
920 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
922 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
923 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
925 // Finally, check the least significant entry.
927 if (UniquedVals[Multiple-1].getNode() == 0)
928 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
929 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
931 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
934 if (UniquedVals[Multiple-1].getNode() == 0)
935 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
936 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
937 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
938 return DAG.getTargetConstant(Val, MVT::i32);
944 // Check to see if this buildvec has a single non-undef value in its elements.
945 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
946 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
947 if (OpVal.getNode() == 0)
948 OpVal = N->getOperand(i);
949 else if (OpVal != N->getOperand(i))
953 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
955 unsigned ValSizeInBytes = EltSize;
957 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
958 Value = CN->getZExtValue();
959 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
960 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
961 Value = FloatToBits(CN->getValueAPF().convertToFloat());
964 // If the splat value is larger than the element value, then we can never do
965 // this splat. The only case that we could fit the replicated bits into our
966 // immediate field for would be zero, and we prefer to use vxor for it.
967 if (ValSizeInBytes < ByteSize) return SDValue();
969 // If the element value is larger than the splat value, cut it in half and
970 // check to see if the two halves are equal. Continue doing this until we
971 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
972 while (ValSizeInBytes > ByteSize) {
973 ValSizeInBytes >>= 1;
975 // If the top half equals the bottom half, we're still ok.
976 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
977 (Value & ((1 << (8*ValSizeInBytes))-1)))
981 // Properly sign extend the value.
982 int MaskVal = SignExtend32(Value, ByteSize * 8);
984 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
985 if (MaskVal == 0) return SDValue();
987 // Finally, if this value fits in a 5 bit sext field, return it
988 if (SignExtend32<5>(MaskVal) == MaskVal)
989 return DAG.getTargetConstant(MaskVal, MVT::i32);
993 //===----------------------------------------------------------------------===//
994 // Addressing Mode Selection
995 //===----------------------------------------------------------------------===//
997 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
998 /// or 64-bit immediate, and if the value can be accurately represented as a
999 /// sign extension from a 16-bit value. If so, this returns true and the
1001 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1002 if (N->getOpcode() != ISD::Constant)
1005 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1006 if (N->getValueType(0) == MVT::i32)
1007 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1009 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1011 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1012 return isIntS16Immediate(Op.getNode(), Imm);
1016 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1017 /// can be represented as an indexed [r+r] operation. Returns false if it
1018 /// can be more efficiently represented with [r+imm].
1019 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1021 SelectionDAG &DAG) const {
1023 if (N.getOpcode() == ISD::ADD) {
1024 if (isIntS16Immediate(N.getOperand(1), imm))
1025 return false; // r+i
1026 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1027 return false; // r+i
1029 Base = N.getOperand(0);
1030 Index = N.getOperand(1);
1032 } else if (N.getOpcode() == ISD::OR) {
1033 if (isIntS16Immediate(N.getOperand(1), imm))
1034 return false; // r+i can fold it if we can.
1036 // If this is an or of disjoint bitfields, we can codegen this as an add
1037 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1039 APInt LHSKnownZero, LHSKnownOne;
1040 APInt RHSKnownZero, RHSKnownOne;
1041 DAG.ComputeMaskedBits(N.getOperand(0),
1042 LHSKnownZero, LHSKnownOne);
1044 if (LHSKnownZero.getBoolValue()) {
1045 DAG.ComputeMaskedBits(N.getOperand(1),
1046 RHSKnownZero, RHSKnownOne);
1047 // If all of the bits are known zero on the LHS or RHS, the add won't
1049 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1050 Base = N.getOperand(0);
1051 Index = N.getOperand(1);
1060 // If we happen to be doing an i64 load or store into a stack slot that has
1061 // less than a 4-byte alignment, then the frame-index elimination may need to
1062 // use an indexed load or store instruction (because the offset may not be a
1063 // multiple of 4). The extra register needed to hold the offset comes from the
1064 // register scavenger, and it is possible that the scavenger will need to use
1065 // an emergency spill slot. As a result, we need to make sure that a spill slot
1066 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1068 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1069 // FIXME: This does not handle the LWA case.
1073 // NOTE: We'll exclude negative FIs here, which come from argument
1074 // lowering, because there are no known test cases triggering this problem
1075 // using packed structures (or similar). We can remove this exclusion if
1076 // we find such a test case. The reason why this is so test-case driven is
1077 // because this entire 'fixup' is only to prevent crashes (from the
1078 // register scavenger) on not-really-valid inputs. For example, if we have:
1080 // %b = bitcast i1* %a to i64*
1081 // store i64* a, i64 b
1082 // then the store should really be marked as 'align 1', but is not. If it
1083 // were marked as 'align 1' then the indexed form would have been
1084 // instruction-selected initially, and the problem this 'fixup' is preventing
1085 // won't happen regardless.
1089 MachineFunction &MF = DAG.getMachineFunction();
1090 MachineFrameInfo *MFI = MF.getFrameInfo();
1092 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1096 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1097 FuncInfo->setHasNonRISpills();
1100 /// Returns true if the address N can be represented by a base register plus
1101 /// a signed 16-bit displacement [r+imm], and if it is not better
1102 /// represented as reg+reg. If Aligned is true, only accept displacements
1103 /// suitable for STD and friends, i.e. multiples of 4.
1104 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1107 bool Aligned) const {
1108 // FIXME dl should come from parent load or store, not from address
1110 // If this can be more profitably realized as r+r, fail.
1111 if (SelectAddressRegReg(N, Disp, Base, DAG))
1114 if (N.getOpcode() == ISD::ADD) {
1116 if (isIntS16Immediate(N.getOperand(1), imm) &&
1117 (!Aligned || (imm & 3) == 0)) {
1118 Disp = DAG.getTargetConstant(imm, N.getValueType());
1119 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1120 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1121 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1123 Base = N.getOperand(0);
1125 return true; // [r+i]
1126 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1127 // Match LOAD (ADD (X, Lo(G))).
1128 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1129 && "Cannot handle constant offsets yet!");
1130 Disp = N.getOperand(1).getOperand(0); // The global address.
1131 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1132 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1133 Disp.getOpcode() == ISD::TargetConstantPool ||
1134 Disp.getOpcode() == ISD::TargetJumpTable);
1135 Base = N.getOperand(0);
1136 return true; // [&g+r]
1138 } else if (N.getOpcode() == ISD::OR) {
1140 if (isIntS16Immediate(N.getOperand(1), imm) &&
1141 (!Aligned || (imm & 3) == 0)) {
1142 // If this is an or of disjoint bitfields, we can codegen this as an add
1143 // (for better address arithmetic) if the LHS and RHS of the OR are
1144 // provably disjoint.
1145 APInt LHSKnownZero, LHSKnownOne;
1146 DAG.ComputeMaskedBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1148 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1149 // If all of the bits are known zero on the LHS or RHS, the add won't
1151 Base = N.getOperand(0);
1152 Disp = DAG.getTargetConstant(imm, N.getValueType());
1156 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1157 // Loading from a constant address.
1159 // If this address fits entirely in a 16-bit sext immediate field, codegen
1162 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1163 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1164 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1165 CN->getValueType(0));
1169 // Handle 32-bit sext immediates with LIS + addr mode.
1170 if ((CN->getValueType(0) == MVT::i32 ||
1171 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1172 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1173 int Addr = (int)CN->getZExtValue();
1175 // Otherwise, break this down into an LIS + disp.
1176 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1178 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1179 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1180 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1185 Disp = DAG.getTargetConstant(0, getPointerTy());
1186 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1187 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1188 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1191 return true; // [r+0]
1194 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1195 /// represented as an indexed [r+r] operation.
1196 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1198 SelectionDAG &DAG) const {
1199 // Check to see if we can easily represent this as an [r+r] address. This
1200 // will fail if it thinks that the address is more profitably represented as
1201 // reg+imm, e.g. where imm = 0.
1202 if (SelectAddressRegReg(N, Base, Index, DAG))
1205 // If the operand is an addition, always emit this as [r+r], since this is
1206 // better (for code size, and execution, as the memop does the add for free)
1207 // than emitting an explicit add.
1208 if (N.getOpcode() == ISD::ADD) {
1209 Base = N.getOperand(0);
1210 Index = N.getOperand(1);
1214 // Otherwise, do it the hard way, using R0 as the base register.
1215 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1221 /// getPreIndexedAddressParts - returns true by value, base pointer and
1222 /// offset pointer and addressing mode by reference if the node's address
1223 /// can be legally represented as pre-indexed load / store address.
1224 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1226 ISD::MemIndexedMode &AM,
1227 SelectionDAG &DAG) const {
1228 if (DisablePPCPreinc) return false;
1234 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1235 Ptr = LD->getBasePtr();
1236 VT = LD->getMemoryVT();
1237 Alignment = LD->getAlignment();
1238 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1239 Ptr = ST->getBasePtr();
1240 VT = ST->getMemoryVT();
1241 Alignment = ST->getAlignment();
1246 // PowerPC doesn't have preinc load/store instructions for vectors.
1250 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1252 // Common code will reject creating a pre-inc form if the base pointer
1253 // is a frame index, or if N is a store and the base pointer is either
1254 // the same as or a predecessor of the value being stored. Check for
1255 // those situations here, and try with swapped Base/Offset instead.
1258 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1261 SDValue Val = cast<StoreSDNode>(N)->getValue();
1262 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1267 std::swap(Base, Offset);
1273 // LDU/STU can only handle immediates that are a multiple of 4.
1274 if (VT != MVT::i64) {
1275 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1278 // LDU/STU need an address with at least 4-byte alignment.
1282 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1286 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1287 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1288 // sext i32 to i64 when addr mode is r+i.
1289 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1290 LD->getExtensionType() == ISD::SEXTLOAD &&
1291 isa<ConstantSDNode>(Offset))
1299 //===----------------------------------------------------------------------===//
1300 // LowerOperation implementation
1301 //===----------------------------------------------------------------------===//
1303 /// GetLabelAccessInfo - Return true if we should reference labels using a
1304 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1305 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1306 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1307 HiOpFlags = PPCII::MO_HA;
1308 LoOpFlags = PPCII::MO_LO;
1310 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1311 // non-darwin platform. We don't support PIC on other platforms yet.
1312 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1313 TM.getSubtarget<PPCSubtarget>().isDarwin();
1315 HiOpFlags |= PPCII::MO_PIC_FLAG;
1316 LoOpFlags |= PPCII::MO_PIC_FLAG;
1319 // If this is a reference to a global value that requires a non-lazy-ptr, make
1320 // sure that instruction lowering adds it.
1321 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1322 HiOpFlags |= PPCII::MO_NLP_FLAG;
1323 LoOpFlags |= PPCII::MO_NLP_FLAG;
1325 if (GV->hasHiddenVisibility()) {
1326 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1327 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1334 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1335 SelectionDAG &DAG) {
1336 EVT PtrVT = HiPart.getValueType();
1337 SDValue Zero = DAG.getConstant(0, PtrVT);
1340 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1341 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1343 // With PIC, the first instruction is actually "GR+hi(&G)".
1345 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1346 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1348 // Generate non-pic code that has direct accesses to the constant pool.
1349 // The address of the global is just (hi(&g)+lo(&g)).
1350 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1353 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1354 SelectionDAG &DAG) const {
1355 EVT PtrVT = Op.getValueType();
1356 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1357 const Constant *C = CP->getConstVal();
1359 // 64-bit SVR4 ABI code is always position-independent.
1360 // The actual address of the GlobalValue is stored in the TOC.
1361 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1362 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1363 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1364 DAG.getRegister(PPC::X2, MVT::i64));
1367 unsigned MOHiFlag, MOLoFlag;
1368 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1370 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1372 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1373 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1376 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1377 EVT PtrVT = Op.getValueType();
1378 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1380 // 64-bit SVR4 ABI code is always position-independent.
1381 // The actual address of the GlobalValue is stored in the TOC.
1382 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1383 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1384 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1385 DAG.getRegister(PPC::X2, MVT::i64));
1388 unsigned MOHiFlag, MOLoFlag;
1389 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1390 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1391 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1392 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1395 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1396 SelectionDAG &DAG) const {
1397 EVT PtrVT = Op.getValueType();
1399 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1401 unsigned MOHiFlag, MOLoFlag;
1402 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1403 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1404 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1405 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1408 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1409 SelectionDAG &DAG) const {
1411 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1413 const GlobalValue *GV = GA->getGlobal();
1414 EVT PtrVT = getPointerTy();
1415 bool is64bit = PPCSubTarget.isPPC64();
1417 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1419 if (Model == TLSModel::LocalExec) {
1420 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1421 PPCII::MO_TPREL_HA);
1422 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1423 PPCII::MO_TPREL_LO);
1424 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1425 is64bit ? MVT::i64 : MVT::i32);
1426 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1427 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1431 llvm_unreachable("only local-exec is currently supported for ppc32");
1433 if (Model == TLSModel::InitialExec) {
1434 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1435 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1437 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1438 SDValue TPOffsetHi = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1439 PtrVT, GOTReg, TGA);
1440 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1441 PtrVT, TGA, TPOffsetHi);
1442 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1445 if (Model == TLSModel::GeneralDynamic) {
1446 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1447 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1448 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1450 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1453 // We need a chain node, and don't have one handy. The underlying
1454 // call has no side effects, so using the function entry node
1456 SDValue Chain = DAG.getEntryNode();
1457 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1458 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1459 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1460 PtrVT, ParmReg, TGA);
1461 // The return value from GET_TLS_ADDR really is in X3 already, but
1462 // some hacks are needed here to tie everything together. The extra
1463 // copies dissolve during subsequent transforms.
1464 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1465 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1468 if (Model == TLSModel::LocalDynamic) {
1469 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1470 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1471 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1473 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1476 // We need a chain node, and don't have one handy. The underlying
1477 // call has no side effects, so using the function entry node
1479 SDValue Chain = DAG.getEntryNode();
1480 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1481 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1482 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1483 PtrVT, ParmReg, TGA);
1484 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1485 // some hacks are needed here to tie everything together. The extra
1486 // copies dissolve during subsequent transforms.
1487 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1488 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1489 Chain, ParmReg, TGA);
1490 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1493 llvm_unreachable("Unknown TLS model!");
1496 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1497 SelectionDAG &DAG) const {
1498 EVT PtrVT = Op.getValueType();
1499 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1501 const GlobalValue *GV = GSDN->getGlobal();
1503 // 64-bit SVR4 ABI code is always position-independent.
1504 // The actual address of the GlobalValue is stored in the TOC.
1505 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1506 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1507 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1508 DAG.getRegister(PPC::X2, MVT::i64));
1511 unsigned MOHiFlag, MOLoFlag;
1512 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1515 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1517 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1519 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1521 // If the global reference is actually to a non-lazy-pointer, we have to do an
1522 // extra load to get the address of the global.
1523 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1524 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1525 false, false, false, 0);
1529 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1530 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1533 // If we're comparing for equality to zero, expose the fact that this is
1534 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1535 // fold the new nodes.
1536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1537 if (C->isNullValue() && CC == ISD::SETEQ) {
1538 EVT VT = Op.getOperand(0).getValueType();
1539 SDValue Zext = Op.getOperand(0);
1540 if (VT.bitsLT(MVT::i32)) {
1542 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1544 unsigned Log2b = Log2_32(VT.getSizeInBits());
1545 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1546 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1547 DAG.getConstant(Log2b, MVT::i32));
1548 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1550 // Leave comparisons against 0 and -1 alone for now, since they're usually
1551 // optimized. FIXME: revisit this when we can custom lower all setcc
1553 if (C->isAllOnesValue() || C->isNullValue())
1557 // If we have an integer seteq/setne, turn it into a compare against zero
1558 // by xor'ing the rhs with the lhs, which is faster than setting a
1559 // condition register, reading it back out, and masking the correct bit. The
1560 // normal approach here uses sub to do this instead of xor. Using xor exposes
1561 // the result to other bit-twiddling opportunities.
1562 EVT LHSVT = Op.getOperand(0).getValueType();
1563 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1564 EVT VT = Op.getValueType();
1565 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1567 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1572 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1573 const PPCSubtarget &Subtarget) const {
1574 SDNode *Node = Op.getNode();
1575 EVT VT = Node->getValueType(0);
1576 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1577 SDValue InChain = Node->getOperand(0);
1578 SDValue VAListPtr = Node->getOperand(1);
1579 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1582 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1585 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1586 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1588 InChain = GprIndex.getValue(1);
1590 if (VT == MVT::i64) {
1591 // Check if GprIndex is even
1592 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1593 DAG.getConstant(1, MVT::i32));
1594 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1595 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1596 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1597 DAG.getConstant(1, MVT::i32));
1598 // Align GprIndex to be even if it isn't
1599 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1603 // fpr index is 1 byte after gpr
1604 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1605 DAG.getConstant(1, MVT::i32));
1608 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1609 FprPtr, MachinePointerInfo(SV), MVT::i8,
1611 InChain = FprIndex.getValue(1);
1613 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1614 DAG.getConstant(8, MVT::i32));
1616 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1617 DAG.getConstant(4, MVT::i32));
1620 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1621 MachinePointerInfo(), false, false,
1623 InChain = OverflowArea.getValue(1);
1625 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1626 MachinePointerInfo(), false, false,
1628 InChain = RegSaveArea.getValue(1);
1630 // select overflow_area if index > 8
1631 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1632 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1634 // adjustment constant gpr_index * 4/8
1635 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1636 VT.isInteger() ? GprIndex : FprIndex,
1637 DAG.getConstant(VT.isInteger() ? 4 : 8,
1640 // OurReg = RegSaveArea + RegConstant
1641 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1644 // Floating types are 32 bytes into RegSaveArea
1645 if (VT.isFloatingPoint())
1646 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1647 DAG.getConstant(32, MVT::i32));
1649 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1650 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1651 VT.isInteger() ? GprIndex : FprIndex,
1652 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1655 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1656 VT.isInteger() ? VAListPtr : FprPtr,
1657 MachinePointerInfo(SV),
1658 MVT::i8, false, false, 0);
1660 // determine if we should load from reg_save_area or overflow_area
1661 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1663 // increase overflow_area by 4/8 if gpr/fpr > 8
1664 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1665 DAG.getConstant(VT.isInteger() ? 4 : 8,
1668 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1671 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1673 MachinePointerInfo(),
1674 MVT::i32, false, false, 0);
1676 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1677 false, false, false, 0);
1680 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1681 const PPCSubtarget &Subtarget) const {
1682 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1684 // We have to copy the entire va_list struct:
1685 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1686 return DAG.getMemcpy(Op.getOperand(0), Op,
1687 Op.getOperand(1), Op.getOperand(2),
1688 DAG.getConstant(12, MVT::i32), 8, false, true,
1689 MachinePointerInfo(), MachinePointerInfo());
1692 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1693 SelectionDAG &DAG) const {
1694 return Op.getOperand(0);
1697 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1698 SelectionDAG &DAG) const {
1699 SDValue Chain = Op.getOperand(0);
1700 SDValue Trmp = Op.getOperand(1); // trampoline
1701 SDValue FPtr = Op.getOperand(2); // nested function
1702 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1705 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1706 bool isPPC64 = (PtrVT == MVT::i64);
1708 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1711 TargetLowering::ArgListTy Args;
1712 TargetLowering::ArgListEntry Entry;
1714 Entry.Ty = IntPtrTy;
1715 Entry.Node = Trmp; Args.push_back(Entry);
1717 // TrampSize == (isPPC64 ? 48 : 40);
1718 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1719 isPPC64 ? MVT::i64 : MVT::i32);
1720 Args.push_back(Entry);
1722 Entry.Node = FPtr; Args.push_back(Entry);
1723 Entry.Node = Nest; Args.push_back(Entry);
1725 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1726 TargetLowering::CallLoweringInfo CLI(Chain,
1727 Type::getVoidTy(*DAG.getContext()),
1728 false, false, false, false, 0,
1730 /*isTailCall=*/false,
1731 /*doesNotRet=*/false,
1732 /*isReturnValueUsed=*/true,
1733 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1735 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1737 return CallResult.second;
1740 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1741 const PPCSubtarget &Subtarget) const {
1742 MachineFunction &MF = DAG.getMachineFunction();
1743 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1747 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1748 // vastart just stores the address of the VarArgsFrameIndex slot into the
1749 // memory location argument.
1750 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1751 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1752 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1753 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1754 MachinePointerInfo(SV),
1758 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1759 // We suppose the given va_list is already allocated.
1762 // char gpr; /* index into the array of 8 GPRs
1763 // * stored in the register save area
1764 // * gpr=0 corresponds to r3,
1765 // * gpr=1 to r4, etc.
1767 // char fpr; /* index into the array of 8 FPRs
1768 // * stored in the register save area
1769 // * fpr=0 corresponds to f1,
1770 // * fpr=1 to f2, etc.
1772 // char *overflow_arg_area;
1773 // /* location on stack that holds
1774 // * the next overflow argument
1776 // char *reg_save_area;
1777 // /* where r3:r10 and f1:f8 (if saved)
1783 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1784 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1787 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1789 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1791 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1794 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1795 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1797 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1798 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1800 uint64_t FPROffset = 1;
1801 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1803 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1805 // Store first byte : number of int regs
1806 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1808 MachinePointerInfo(SV),
1809 MVT::i8, false, false, 0);
1810 uint64_t nextOffset = FPROffset;
1811 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1814 // Store second byte : number of float regs
1815 SDValue secondStore =
1816 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1817 MachinePointerInfo(SV, nextOffset), MVT::i8,
1819 nextOffset += StackOffset;
1820 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1822 // Store second word : arguments given on stack
1823 SDValue thirdStore =
1824 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1825 MachinePointerInfo(SV, nextOffset),
1827 nextOffset += FrameOffset;
1828 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1830 // Store third word : arguments given in registers
1831 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1832 MachinePointerInfo(SV, nextOffset),
1837 #include "PPCGenCallingConv.inc"
1839 // Function whose sole purpose is to kill compiler warnings
1840 // stemming from unused functions included from PPCGenCallingConv.inc.
1841 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
1842 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
1845 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1846 CCValAssign::LocInfo &LocInfo,
1847 ISD::ArgFlagsTy &ArgFlags,
1852 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1854 CCValAssign::LocInfo &LocInfo,
1855 ISD::ArgFlagsTy &ArgFlags,
1857 static const uint16_t ArgRegs[] = {
1858 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1859 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1861 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1863 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1865 // Skip one register if the first unallocated register has an even register
1866 // number and there are still argument registers available which have not been
1867 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1868 // need to skip a register if RegNum is odd.
1869 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1870 State.AllocateReg(ArgRegs[RegNum]);
1873 // Always return false here, as this function only makes sure that the first
1874 // unallocated register has an odd register number and does not actually
1875 // allocate a register for the current argument.
1879 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1881 CCValAssign::LocInfo &LocInfo,
1882 ISD::ArgFlagsTy &ArgFlags,
1884 static const uint16_t ArgRegs[] = {
1885 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1889 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1891 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1893 // If there is only one Floating-point register left we need to put both f64
1894 // values of a split ppc_fp128 value on the stack.
1895 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1896 State.AllocateReg(ArgRegs[RegNum]);
1899 // Always return false here, as this function only makes sure that the two f64
1900 // values a ppc_fp128 value is split into are both passed in registers or both
1901 // passed on the stack and does not actually allocate a register for the
1902 // current argument.
1906 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1908 static const uint16_t *GetFPR() {
1909 static const uint16_t FPR[] = {
1910 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1911 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1917 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1919 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1920 unsigned PtrByteSize) {
1921 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1922 if (Flags.isByVal())
1923 ArgSize = Flags.getByValSize();
1924 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1930 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1931 CallingConv::ID CallConv, bool isVarArg,
1932 const SmallVectorImpl<ISD::InputArg>
1934 SDLoc dl, SelectionDAG &DAG,
1935 SmallVectorImpl<SDValue> &InVals)
1937 if (PPCSubTarget.isSVR4ABI()) {
1938 if (PPCSubTarget.isPPC64())
1939 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
1942 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
1945 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1951 PPCTargetLowering::LowerFormalArguments_32SVR4(
1953 CallingConv::ID CallConv, bool isVarArg,
1954 const SmallVectorImpl<ISD::InputArg>
1956 SDLoc dl, SelectionDAG &DAG,
1957 SmallVectorImpl<SDValue> &InVals) const {
1959 // 32-bit SVR4 ABI Stack Frame Layout:
1960 // +-----------------------------------+
1961 // +--> | Back chain |
1962 // | +-----------------------------------+
1963 // | | Floating-point register save area |
1964 // | +-----------------------------------+
1965 // | | General register save area |
1966 // | +-----------------------------------+
1967 // | | CR save word |
1968 // | +-----------------------------------+
1969 // | | VRSAVE save word |
1970 // | +-----------------------------------+
1971 // | | Alignment padding |
1972 // | +-----------------------------------+
1973 // | | Vector register save area |
1974 // | +-----------------------------------+
1975 // | | Local variable space |
1976 // | +-----------------------------------+
1977 // | | Parameter list area |
1978 // | +-----------------------------------+
1979 // | | LR save word |
1980 // | +-----------------------------------+
1981 // SP--> +--- | Back chain |
1982 // +-----------------------------------+
1985 // System V Application Binary Interface PowerPC Processor Supplement
1986 // AltiVec Technology Programming Interface Manual
1988 MachineFunction &MF = DAG.getMachineFunction();
1989 MachineFrameInfo *MFI = MF.getFrameInfo();
1990 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1992 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1993 // Potential tail calls could cause overwriting of argument stack slots.
1994 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
1995 (CallConv == CallingConv::Fast));
1996 unsigned PtrByteSize = 4;
1998 // Assign locations to all of the incoming arguments.
1999 SmallVector<CCValAssign, 16> ArgLocs;
2000 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2001 getTargetMachine(), ArgLocs, *DAG.getContext());
2003 // Reserve space for the linkage area on the stack.
2004 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2006 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2008 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2009 CCValAssign &VA = ArgLocs[i];
2011 // Arguments stored in registers.
2012 if (VA.isRegLoc()) {
2013 const TargetRegisterClass *RC;
2014 EVT ValVT = VA.getValVT();
2016 switch (ValVT.getSimpleVT().SimpleTy) {
2018 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2020 RC = &PPC::GPRCRegClass;
2023 RC = &PPC::F4RCRegClass;
2026 RC = &PPC::F8RCRegClass;
2032 RC = &PPC::VRRCRegClass;
2036 // Transform the arguments stored in physical registers into virtual ones.
2037 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2038 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
2040 InVals.push_back(ArgValue);
2042 // Argument stored in memory.
2043 assert(VA.isMemLoc());
2045 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
2046 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2049 // Create load nodes to retrieve arguments from the stack.
2050 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2051 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2052 MachinePointerInfo(),
2053 false, false, false, 0));
2057 // Assign locations to all of the incoming aggregate by value arguments.
2058 // Aggregates passed by value are stored in the local variable space of the
2059 // caller's stack frame, right above the parameter list area.
2060 SmallVector<CCValAssign, 16> ByValArgLocs;
2061 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2062 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2064 // Reserve stack space for the allocations in CCInfo.
2065 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2067 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2069 // Area that is at least reserved in the caller of this function.
2070 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2072 // Set the size that is at least reserved in caller of this function. Tail
2073 // call optimized function's reserved stack space needs to be aligned so that
2074 // taking the difference between two stack areas will result in an aligned
2076 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2079 std::max(MinReservedArea,
2080 PPCFrameLowering::getMinCallFrameSize(false, false));
2082 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2083 getStackAlignment();
2084 unsigned AlignMask = TargetAlign-1;
2085 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2087 FI->setMinReservedArea(MinReservedArea);
2089 SmallVector<SDValue, 8> MemOps;
2091 // If the function takes variable number of arguments, make a frame index for
2092 // the start of the first vararg value... for expansion of llvm.va_start.
2094 static const uint16_t GPArgRegs[] = {
2095 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2096 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2098 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2100 static const uint16_t FPArgRegs[] = {
2101 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2104 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2106 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2108 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2111 // Make room for NumGPArgRegs and NumFPArgRegs.
2112 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2113 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2115 FuncInfo->setVarArgsStackOffset(
2116 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2117 CCInfo.getNextStackOffset(), true));
2119 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2120 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2122 // The fixed integer arguments of a variadic function are stored to the
2123 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2124 // the result of va_next.
2125 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2126 // Get an existing live-in vreg, or add a new one.
2127 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2129 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2131 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2132 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2133 MachinePointerInfo(), false, false, 0);
2134 MemOps.push_back(Store);
2135 // Increment the address by four for the next argument to store
2136 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2137 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2140 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2142 // The double arguments are stored to the VarArgsFrameIndex
2144 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2145 // Get an existing live-in vreg, or add a new one.
2146 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2148 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2150 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2151 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2152 MachinePointerInfo(), false, false, 0);
2153 MemOps.push_back(Store);
2154 // Increment the address by eight for the next argument to store
2155 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2157 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2161 if (!MemOps.empty())
2162 Chain = DAG.getNode(ISD::TokenFactor, dl,
2163 MVT::Other, &MemOps[0], MemOps.size());
2168 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2169 // value to MVT::i64 and then truncate to the correct register size.
2171 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2172 SelectionDAG &DAG, SDValue ArgVal,
2175 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2176 DAG.getValueType(ObjectVT));
2177 else if (Flags.isZExt())
2178 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2179 DAG.getValueType(ObjectVT));
2181 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2184 // Set the size that is at least reserved in caller of this function. Tail
2185 // call optimized functions' reserved stack space needs to be aligned so that
2186 // taking the difference between two stack areas will result in an aligned
2189 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2190 unsigned nAltivecParamsAtEnd,
2191 unsigned MinReservedArea,
2192 bool isPPC64) const {
2193 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2194 // Add the Altivec parameters at the end, if needed.
2195 if (nAltivecParamsAtEnd) {
2196 MinReservedArea = ((MinReservedArea+15)/16)*16;
2197 MinReservedArea += 16*nAltivecParamsAtEnd;
2200 std::max(MinReservedArea,
2201 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2202 unsigned TargetAlign
2203 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2204 getStackAlignment();
2205 unsigned AlignMask = TargetAlign-1;
2206 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2207 FI->setMinReservedArea(MinReservedArea);
2211 PPCTargetLowering::LowerFormalArguments_64SVR4(
2213 CallingConv::ID CallConv, bool isVarArg,
2214 const SmallVectorImpl<ISD::InputArg>
2216 SDLoc dl, SelectionDAG &DAG,
2217 SmallVectorImpl<SDValue> &InVals) const {
2218 // TODO: add description of PPC stack frame format, or at least some docs.
2220 MachineFunction &MF = DAG.getMachineFunction();
2221 MachineFrameInfo *MFI = MF.getFrameInfo();
2222 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2224 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2225 // Potential tail calls could cause overwriting of argument stack slots.
2226 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2227 (CallConv == CallingConv::Fast));
2228 unsigned PtrByteSize = 8;
2230 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2231 // Area that is at least reserved in caller of this function.
2232 unsigned MinReservedArea = ArgOffset;
2234 static const uint16_t GPR[] = {
2235 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2236 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2239 static const uint16_t *FPR = GetFPR();
2241 static const uint16_t VR[] = {
2242 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2243 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2246 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2247 const unsigned Num_FPR_Regs = 13;
2248 const unsigned Num_VR_Regs = array_lengthof(VR);
2250 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2252 // Add DAG nodes to load the arguments or copy them out of registers. On
2253 // entry to a function on PPC, the arguments start after the linkage area,
2254 // although the first ones are often in registers.
2256 SmallVector<SDValue, 8> MemOps;
2257 unsigned nAltivecParamsAtEnd = 0;
2258 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2259 unsigned CurArgIdx = 0;
2260 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2262 bool needsLoad = false;
2263 EVT ObjectVT = Ins[ArgNo].VT;
2264 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2265 unsigned ArgSize = ObjSize;
2266 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2267 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2268 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2270 unsigned CurArgOffset = ArgOffset;
2272 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2273 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2274 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2276 MinReservedArea = ((MinReservedArea+15)/16)*16;
2277 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2281 nAltivecParamsAtEnd++;
2283 // Calculate min reserved area.
2284 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2288 // FIXME the codegen can be much improved in some cases.
2289 // We do not have to keep everything in memory.
2290 if (Flags.isByVal()) {
2291 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2292 ObjSize = Flags.getByValSize();
2293 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2294 // Empty aggregate parameters do not take up registers. Examples:
2298 // etc. However, we have to provide a place-holder in InVals, so
2299 // pretend we have an 8-byte item at the current address for that
2302 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2303 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2304 InVals.push_back(FIN);
2308 unsigned BVAlign = Flags.getByValAlign();
2310 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2311 CurArgOffset = ArgOffset;
2314 // All aggregates smaller than 8 bytes must be passed right-justified.
2315 if (ObjSize < PtrByteSize)
2316 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2317 // The value of the object is its address.
2318 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2319 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2320 InVals.push_back(FIN);
2323 if (GPR_idx != Num_GPR_Regs) {
2324 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2325 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2328 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2329 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2330 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2331 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2332 MachinePointerInfo(FuncArg, CurArgOffset),
2333 ObjType, false, false, 0);
2335 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2336 // store the whole register as-is to the parameter save area
2337 // slot. The address of the parameter was already calculated
2338 // above (InVals.push_back(FIN)) to be the right-justified
2339 // offset within the slot. For this store, we need a new
2340 // frame index that points at the beginning of the slot.
2341 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2342 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2343 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2344 MachinePointerInfo(FuncArg, ArgOffset),
2348 MemOps.push_back(Store);
2351 // Whether we copied from a register or not, advance the offset
2352 // into the parameter save area by a full doubleword.
2353 ArgOffset += PtrByteSize;
2357 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2358 // Store whatever pieces of the object are in registers
2359 // to memory. ArgOffset will be the address of the beginning
2361 if (GPR_idx != Num_GPR_Regs) {
2363 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2364 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2365 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2366 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2367 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2368 MachinePointerInfo(FuncArg, ArgOffset),
2370 MemOps.push_back(Store);
2372 ArgOffset += PtrByteSize;
2374 ArgOffset += ArgSize - j;
2381 switch (ObjectVT.getSimpleVT().SimpleTy) {
2382 default: llvm_unreachable("Unhandled argument type!");
2385 if (GPR_idx != Num_GPR_Regs) {
2386 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2387 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2389 if (ObjectVT == MVT::i32)
2390 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2391 // value to MVT::i64 and then truncate to the correct register size.
2392 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2397 ArgSize = PtrByteSize;
2404 // Every 8 bytes of argument space consumes one of the GPRs available for
2405 // argument passing.
2406 if (GPR_idx != Num_GPR_Regs) {
2409 if (FPR_idx != Num_FPR_Regs) {
2412 if (ObjectVT == MVT::f32)
2413 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2415 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2417 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2421 ArgSize = PtrByteSize;
2430 // Note that vector arguments in registers don't reserve stack space,
2431 // except in varargs functions.
2432 if (VR_idx != Num_VR_Regs) {
2433 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2434 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2436 while ((ArgOffset % 16) != 0) {
2437 ArgOffset += PtrByteSize;
2438 if (GPR_idx != Num_GPR_Regs)
2442 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2446 // Vectors are aligned.
2447 ArgOffset = ((ArgOffset+15)/16)*16;
2448 CurArgOffset = ArgOffset;
2455 // We need to load the argument to a virtual register if we determined
2456 // above that we ran out of physical registers of the appropriate type.
2458 int FI = MFI->CreateFixedObject(ObjSize,
2459 CurArgOffset + (ArgSize - ObjSize),
2461 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2462 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2463 false, false, false, 0);
2466 InVals.push_back(ArgVal);
2469 // Set the size that is at least reserved in caller of this function. Tail
2470 // call optimized functions' reserved stack space needs to be aligned so that
2471 // taking the difference between two stack areas will result in an aligned
2473 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2475 // If the function takes variable number of arguments, make a frame index for
2476 // the start of the first vararg value... for expansion of llvm.va_start.
2478 int Depth = ArgOffset;
2480 FuncInfo->setVarArgsFrameIndex(
2481 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2482 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2484 // If this function is vararg, store any remaining integer argument regs
2485 // to their spots on the stack so that they may be loaded by deferencing the
2486 // result of va_next.
2487 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2488 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2489 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2490 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2491 MachinePointerInfo(), false, false, 0);
2492 MemOps.push_back(Store);
2493 // Increment the address by four for the next argument to store
2494 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2495 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2499 if (!MemOps.empty())
2500 Chain = DAG.getNode(ISD::TokenFactor, dl,
2501 MVT::Other, &MemOps[0], MemOps.size());
2507 PPCTargetLowering::LowerFormalArguments_Darwin(
2509 CallingConv::ID CallConv, bool isVarArg,
2510 const SmallVectorImpl<ISD::InputArg>
2512 SDLoc dl, SelectionDAG &DAG,
2513 SmallVectorImpl<SDValue> &InVals) const {
2514 // TODO: add description of PPC stack frame format, or at least some docs.
2516 MachineFunction &MF = DAG.getMachineFunction();
2517 MachineFrameInfo *MFI = MF.getFrameInfo();
2518 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2520 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2521 bool isPPC64 = PtrVT == MVT::i64;
2522 // Potential tail calls could cause overwriting of argument stack slots.
2523 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2524 (CallConv == CallingConv::Fast));
2525 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2527 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2528 // Area that is at least reserved in caller of this function.
2529 unsigned MinReservedArea = ArgOffset;
2531 static const uint16_t GPR_32[] = { // 32-bit registers.
2532 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2533 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2535 static const uint16_t GPR_64[] = { // 64-bit registers.
2536 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2537 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2540 static const uint16_t *FPR = GetFPR();
2542 static const uint16_t VR[] = {
2543 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2544 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2547 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2548 const unsigned Num_FPR_Regs = 13;
2549 const unsigned Num_VR_Regs = array_lengthof( VR);
2551 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2553 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
2555 // In 32-bit non-varargs functions, the stack space for vectors is after the
2556 // stack space for non-vectors. We do not use this space unless we have
2557 // too many vectors to fit in registers, something that only occurs in
2558 // constructed examples:), but we have to walk the arglist to figure
2559 // that out...for the pathological case, compute VecArgOffset as the
2560 // start of the vector parameter area. Computing VecArgOffset is the
2561 // entire point of the following loop.
2562 unsigned VecArgOffset = ArgOffset;
2563 if (!isVarArg && !isPPC64) {
2564 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2566 EVT ObjectVT = Ins[ArgNo].VT;
2567 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2569 if (Flags.isByVal()) {
2570 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2571 unsigned ObjSize = Flags.getByValSize();
2573 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2574 VecArgOffset += ArgSize;
2578 switch(ObjectVT.getSimpleVT().SimpleTy) {
2579 default: llvm_unreachable("Unhandled argument type!");
2584 case MVT::i64: // PPC64
2586 // FIXME: We are guaranteed to be !isPPC64 at this point.
2587 // Does MVT::i64 apply?
2594 // Nothing to do, we're only looking at Nonvector args here.
2599 // We've found where the vector parameter area in memory is. Skip the
2600 // first 12 parameters; these don't use that memory.
2601 VecArgOffset = ((VecArgOffset+15)/16)*16;
2602 VecArgOffset += 12*16;
2604 // Add DAG nodes to load the arguments or copy them out of registers. On
2605 // entry to a function on PPC, the arguments start after the linkage area,
2606 // although the first ones are often in registers.
2608 SmallVector<SDValue, 8> MemOps;
2609 unsigned nAltivecParamsAtEnd = 0;
2610 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2611 unsigned CurArgIdx = 0;
2612 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2614 bool needsLoad = false;
2615 EVT ObjectVT = Ins[ArgNo].VT;
2616 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2617 unsigned ArgSize = ObjSize;
2618 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2619 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2620 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2622 unsigned CurArgOffset = ArgOffset;
2624 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2625 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2626 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2627 if (isVarArg || isPPC64) {
2628 MinReservedArea = ((MinReservedArea+15)/16)*16;
2629 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2632 } else nAltivecParamsAtEnd++;
2634 // Calculate min reserved area.
2635 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2639 // FIXME the codegen can be much improved in some cases.
2640 // We do not have to keep everything in memory.
2641 if (Flags.isByVal()) {
2642 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2643 ObjSize = Flags.getByValSize();
2644 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2645 // Objects of size 1 and 2 are right justified, everything else is
2646 // left justified. This means the memory address is adjusted forwards.
2647 if (ObjSize==1 || ObjSize==2) {
2648 CurArgOffset = CurArgOffset + (4 - ObjSize);
2650 // The value of the object is its address.
2651 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2652 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2653 InVals.push_back(FIN);
2654 if (ObjSize==1 || ObjSize==2) {
2655 if (GPR_idx != Num_GPR_Regs) {
2658 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2660 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2661 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2662 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2663 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2664 MachinePointerInfo(FuncArg,
2666 ObjType, false, false, 0);
2667 MemOps.push_back(Store);
2671 ArgOffset += PtrByteSize;
2675 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2676 // Store whatever pieces of the object are in registers
2677 // to memory. ArgOffset will be the address of the beginning
2679 if (GPR_idx != Num_GPR_Regs) {
2682 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2684 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2685 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2686 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2687 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2688 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2689 MachinePointerInfo(FuncArg, ArgOffset),
2691 MemOps.push_back(Store);
2693 ArgOffset += PtrByteSize;
2695 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2702 switch (ObjectVT.getSimpleVT().SimpleTy) {
2703 default: llvm_unreachable("Unhandled argument type!");
2706 if (GPR_idx != Num_GPR_Regs) {
2707 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2708 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2712 ArgSize = PtrByteSize;
2714 // All int arguments reserve stack space in the Darwin ABI.
2715 ArgOffset += PtrByteSize;
2719 case MVT::i64: // PPC64
2720 if (GPR_idx != Num_GPR_Regs) {
2721 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2722 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2724 if (ObjectVT == MVT::i32)
2725 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2726 // value to MVT::i64 and then truncate to the correct register size.
2727 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2732 ArgSize = PtrByteSize;
2734 // All int arguments reserve stack space in the Darwin ABI.
2740 // Every 4 bytes of argument space consumes one of the GPRs available for
2741 // argument passing.
2742 if (GPR_idx != Num_GPR_Regs) {
2744 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2747 if (FPR_idx != Num_FPR_Regs) {
2750 if (ObjectVT == MVT::f32)
2751 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2753 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2755 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2761 // All FP arguments reserve stack space in the Darwin ABI.
2762 ArgOffset += isPPC64 ? 8 : ObjSize;
2768 // Note that vector arguments in registers don't reserve stack space,
2769 // except in varargs functions.
2770 if (VR_idx != Num_VR_Regs) {
2771 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2772 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2774 while ((ArgOffset % 16) != 0) {
2775 ArgOffset += PtrByteSize;
2776 if (GPR_idx != Num_GPR_Regs)
2780 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2784 if (!isVarArg && !isPPC64) {
2785 // Vectors go after all the nonvectors.
2786 CurArgOffset = VecArgOffset;
2789 // Vectors are aligned.
2790 ArgOffset = ((ArgOffset+15)/16)*16;
2791 CurArgOffset = ArgOffset;
2799 // We need to load the argument to a virtual register if we determined above
2800 // that we ran out of physical registers of the appropriate type.
2802 int FI = MFI->CreateFixedObject(ObjSize,
2803 CurArgOffset + (ArgSize - ObjSize),
2805 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2806 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2807 false, false, false, 0);
2810 InVals.push_back(ArgVal);
2813 // Set the size that is at least reserved in caller of this function. Tail
2814 // call optimized functions' reserved stack space needs to be aligned so that
2815 // taking the difference between two stack areas will result in an aligned
2817 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
2819 // If the function takes variable number of arguments, make a frame index for
2820 // the start of the first vararg value... for expansion of llvm.va_start.
2822 int Depth = ArgOffset;
2824 FuncInfo->setVarArgsFrameIndex(
2825 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2827 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2829 // If this function is vararg, store any remaining integer argument regs
2830 // to their spots on the stack so that they may be loaded by deferencing the
2831 // result of va_next.
2832 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2836 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2838 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2840 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2841 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2842 MachinePointerInfo(), false, false, 0);
2843 MemOps.push_back(Store);
2844 // Increment the address by four for the next argument to store
2845 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2846 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2850 if (!MemOps.empty())
2851 Chain = DAG.getNode(ISD::TokenFactor, dl,
2852 MVT::Other, &MemOps[0], MemOps.size());
2857 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
2858 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
2860 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2864 const SmallVectorImpl<ISD::OutputArg>
2866 const SmallVectorImpl<SDValue> &OutVals,
2867 unsigned &nAltivecParamsAtEnd) {
2868 // Count how many bytes are to be pushed on the stack, including the linkage
2869 // area, and parameter passing area. We start with 24/48 bytes, which is
2870 // prereserved space for [SP][CR][LR][3 x unused].
2871 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2872 unsigned NumOps = Outs.size();
2873 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2875 // Add up all the space actually used.
2876 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2877 // they all go in registers, but we must reserve stack space for them for
2878 // possible use by the caller. In varargs or 64-bit calls, parameters are
2879 // assigned stack space in order, with padding so Altivec parameters are
2881 nAltivecParamsAtEnd = 0;
2882 for (unsigned i = 0; i != NumOps; ++i) {
2883 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2884 EVT ArgVT = Outs[i].VT;
2885 // Varargs Altivec parameters are padded to a 16 byte boundary.
2886 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2887 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2888 if (!isVarArg && !isPPC64) {
2889 // Non-varargs Altivec parameters go after all the non-Altivec
2890 // parameters; handle those later so we know how much padding we need.
2891 nAltivecParamsAtEnd++;
2894 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2895 NumBytes = ((NumBytes+15)/16)*16;
2897 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2900 // Allow for Altivec parameters at the end, if needed.
2901 if (nAltivecParamsAtEnd) {
2902 NumBytes = ((NumBytes+15)/16)*16;
2903 NumBytes += 16*nAltivecParamsAtEnd;
2906 // The prolog code of the callee may store up to 8 GPR argument registers to
2907 // the stack, allowing va_start to index over them in memory if its varargs.
2908 // Because we cannot tell if this is needed on the caller side, we have to
2909 // conservatively assume that it is needed. As such, make sure we have at
2910 // least enough stack space for the caller to store the 8 GPRs.
2911 NumBytes = std::max(NumBytes,
2912 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2914 // Tail call needs the stack to be aligned.
2915 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
2916 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
2917 getFrameLowering()->getStackAlignment();
2918 unsigned AlignMask = TargetAlign-1;
2919 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2925 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2926 /// adjusted to accommodate the arguments for the tailcall.
2927 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2928 unsigned ParamSize) {
2930 if (!isTailCall) return 0;
2932 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2933 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2934 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2935 // Remember only if the new adjustement is bigger.
2936 if (SPDiff < FI->getTailCallSPDelta())
2937 FI->setTailCallSPDelta(SPDiff);
2942 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2943 /// for tail call optimization. Targets which want to do tail call
2944 /// optimization should implement this function.
2946 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2947 CallingConv::ID CalleeCC,
2949 const SmallVectorImpl<ISD::InputArg> &Ins,
2950 SelectionDAG& DAG) const {
2951 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
2954 // Variable argument functions are not supported.
2958 MachineFunction &MF = DAG.getMachineFunction();
2959 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2960 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2961 // Functions containing by val parameters are not supported.
2962 for (unsigned i = 0; i != Ins.size(); i++) {
2963 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2964 if (Flags.isByVal()) return false;
2967 // Non PIC/GOT tail calls are supported.
2968 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2971 // At the moment we can only do local tail calls (in same module, hidden
2972 // or protected) if we are generating PIC.
2973 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2974 return G->getGlobal()->hasHiddenVisibility()
2975 || G->getGlobal()->hasProtectedVisibility();
2981 /// isCallCompatibleAddress - Return the immediate to use if the specified
2982 /// 32-bit value is representable in the immediate field of a BxA instruction.
2983 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2984 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2987 int Addr = C->getZExtValue();
2988 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2989 SignExtend32<26>(Addr) != Addr)
2990 return 0; // Top 6 bits have to be sext of immediate.
2992 return DAG.getConstant((int)C->getZExtValue() >> 2,
2993 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2998 struct TailCallArgumentInfo {
3003 TailCallArgumentInfo() : FrameIdx(0) {}
3008 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3010 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3012 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3013 SmallVectorImpl<SDValue> &MemOpChains,
3015 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3016 SDValue Arg = TailCallArgs[i].Arg;
3017 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3018 int FI = TailCallArgs[i].FrameIdx;
3019 // Store relative to framepointer.
3020 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3021 MachinePointerInfo::getFixedStack(FI),
3026 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3027 /// the appropriate stack slot for the tail call optimized function call.
3028 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3029 MachineFunction &MF,
3038 // Calculate the new stack slot for the return address.
3039 int SlotSize = isPPC64 ? 8 : 4;
3040 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3042 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3043 NewRetAddrLoc, true);
3044 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3045 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3046 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3047 MachinePointerInfo::getFixedStack(NewRetAddr),
3050 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3051 // slot as the FP is never overwritten.
3054 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3055 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3057 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3058 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3059 MachinePointerInfo::getFixedStack(NewFPIdx),
3066 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3067 /// the position of the argument.
3069 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3070 SDValue Arg, int SPDiff, unsigned ArgOffset,
3071 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3072 int Offset = ArgOffset + SPDiff;
3073 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3074 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3075 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3076 SDValue FIN = DAG.getFrameIndex(FI, VT);
3077 TailCallArgumentInfo Info;
3079 Info.FrameIdxOp = FIN;
3081 TailCallArguments.push_back(Info);
3084 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3085 /// stack slot. Returns the chain as result and the loaded frame pointers in
3086 /// LROpOut/FPOpout. Used when tail calling.
3087 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3095 // Load the LR and FP stack slot for later adjusting.
3096 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
3097 LROpOut = getReturnAddrFrameIndex(DAG);
3098 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3099 false, false, false, 0);
3100 Chain = SDValue(LROpOut.getNode(), 1);
3102 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3103 // slot as the FP is never overwritten.
3105 FPOpOut = getFramePointerFrameIndex(DAG);
3106 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3107 false, false, false, 0);
3108 Chain = SDValue(FPOpOut.getNode(), 1);
3114 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3115 /// by "Src" to address "Dst" of size "Size". Alignment information is
3116 /// specified by the specific parameter attribute. The copy will be passed as
3117 /// a byval function parameter.
3118 /// Sometimes what we are copying is the end of a larger object, the part that
3119 /// does not fit in registers.
3121 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3122 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3124 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3125 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3126 false, false, MachinePointerInfo(0),
3127 MachinePointerInfo(0));
3130 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3133 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3134 SDValue Arg, SDValue PtrOff, int SPDiff,
3135 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3136 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3137 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3139 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3144 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3146 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3147 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3148 DAG.getConstant(ArgOffset, PtrVT));
3150 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3151 MachinePointerInfo(), false, false, 0));
3152 // Calculate and remember argument location.
3153 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3158 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3159 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3160 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3161 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3162 MachineFunction &MF = DAG.getMachineFunction();
3164 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3165 // might overwrite each other in case of tail call optimization.
3166 SmallVector<SDValue, 8> MemOpChains2;
3167 // Do not flag preceding copytoreg stuff together with the following stuff.
3169 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3171 if (!MemOpChains2.empty())
3172 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3173 &MemOpChains2[0], MemOpChains2.size());
3175 // Store the return address to the appropriate stack slot.
3176 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3177 isPPC64, isDarwinABI, dl);
3179 // Emit callseq_end just before tailcall node.
3180 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3181 DAG.getIntPtrConstant(0, true), InFlag, dl);
3182 InFlag = Chain.getValue(1);
3186 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3187 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3188 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3189 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3190 const PPCSubtarget &PPCSubTarget) {
3192 bool isPPC64 = PPCSubTarget.isPPC64();
3193 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
3195 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3196 NodeTys.push_back(MVT::Other); // Returns a chain
3197 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3199 unsigned CallOpc = PPCISD::CALL;
3201 bool needIndirectCall = true;
3202 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3203 // If this is an absolute destination address, use the munged value.
3204 Callee = SDValue(Dest, 0);
3205 needIndirectCall = false;
3208 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3209 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3210 // Use indirect calls for ALL functions calls in JIT mode, since the
3211 // far-call stubs may be outside relocation limits for a BL instruction.
3212 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3213 unsigned OpFlags = 0;
3214 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3215 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3216 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3217 (G->getGlobal()->isDeclaration() ||
3218 G->getGlobal()->isWeakForLinker())) {
3219 // PC-relative references to external symbols should go through $stub,
3220 // unless we're building with the leopard linker or later, which
3221 // automatically synthesizes these stubs.
3222 OpFlags = PPCII::MO_DARWIN_STUB;
3225 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3226 // every direct call is) turn it into a TargetGlobalAddress /
3227 // TargetExternalSymbol node so that legalize doesn't hack it.
3228 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3229 Callee.getValueType(),
3231 needIndirectCall = false;
3235 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3236 unsigned char OpFlags = 0;
3238 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3239 (PPCSubTarget.getTargetTriple().isMacOSX() &&
3240 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3241 // PC-relative references to external symbols should go through $stub,
3242 // unless we're building with the leopard linker or later, which
3243 // automatically synthesizes these stubs.
3244 OpFlags = PPCII::MO_DARWIN_STUB;
3247 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3249 needIndirectCall = false;
3252 if (needIndirectCall) {
3253 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3254 // to do the call, we can't use PPCISD::CALL.
3255 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3257 if (isSVR4ABI && isPPC64) {
3258 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3259 // entry point, but to the function descriptor (the function entry point
3260 // address is part of the function descriptor though).
3261 // The function descriptor is a three doubleword structure with the
3262 // following fields: function entry point, TOC base address and
3263 // environment pointer.
3264 // Thus for a call through a function pointer, the following actions need
3266 // 1. Save the TOC of the caller in the TOC save area of its stack
3267 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3268 // 2. Load the address of the function entry point from the function
3270 // 3. Load the TOC of the callee from the function descriptor into r2.
3271 // 4. Load the environment pointer from the function descriptor into
3273 // 5. Branch to the function entry point address.
3274 // 6. On return of the callee, the TOC of the caller needs to be
3275 // restored (this is done in FinishCall()).
3277 // All those operations are flagged together to ensure that no other
3278 // operations can be scheduled in between. E.g. without flagging the
3279 // operations together, a TOC access in the caller could be scheduled
3280 // between the load of the callee TOC and the branch to the callee, which
3281 // results in the TOC access going through the TOC of the callee instead
3282 // of going through the TOC of the caller, which leads to incorrect code.
3284 // Load the address of the function entry point from the function
3286 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3287 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
3288 InFlag.getNode() ? 3 : 2);
3289 Chain = LoadFuncPtr.getValue(1);
3290 InFlag = LoadFuncPtr.getValue(2);
3292 // Load environment pointer into r11.
3293 // Offset of the environment pointer within the function descriptor.
3294 SDValue PtrOff = DAG.getIntPtrConstant(16);
3296 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3297 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3299 Chain = LoadEnvPtr.getValue(1);
3300 InFlag = LoadEnvPtr.getValue(2);
3302 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3304 Chain = EnvVal.getValue(0);
3305 InFlag = EnvVal.getValue(1);
3307 // Load TOC of the callee into r2. We are using a target-specific load
3308 // with r2 hard coded, because the result of a target-independent load
3309 // would never go directly into r2, since r2 is a reserved register (which
3310 // prevents the register allocator from allocating it), resulting in an
3311 // additional register being allocated and an unnecessary move instruction
3313 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3314 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3316 Chain = LoadTOCPtr.getValue(0);
3317 InFlag = LoadTOCPtr.getValue(1);
3319 MTCTROps[0] = Chain;
3320 MTCTROps[1] = LoadFuncPtr;
3321 MTCTROps[2] = InFlag;
3324 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
3325 2 + (InFlag.getNode() != 0));
3326 InFlag = Chain.getValue(1);
3329 NodeTys.push_back(MVT::Other);
3330 NodeTys.push_back(MVT::Glue);
3331 Ops.push_back(Chain);
3332 CallOpc = PPCISD::BCTRL;
3334 // Add use of X11 (holding environment pointer)
3335 if (isSVR4ABI && isPPC64)
3336 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3337 // Add CTR register as callee so a bctr can be emitted later.
3339 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3342 // If this is a direct call, pass the chain and the callee.
3343 if (Callee.getNode()) {
3344 Ops.push_back(Chain);
3345 Ops.push_back(Callee);
3347 // If this is a tail call add stack pointer delta.
3349 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3351 // Add argument registers to the end of the list so that they are known live
3353 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3354 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3355 RegsToPass[i].second.getValueType()));
3361 bool isLocalCall(const SDValue &Callee)
3363 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3364 return !G->getGlobal()->isDeclaration() &&
3365 !G->getGlobal()->isWeakForLinker();
3370 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3371 CallingConv::ID CallConv, bool isVarArg,
3372 const SmallVectorImpl<ISD::InputArg> &Ins,
3373 SDLoc dl, SelectionDAG &DAG,
3374 SmallVectorImpl<SDValue> &InVals) const {
3376 SmallVector<CCValAssign, 16> RVLocs;
3377 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3378 getTargetMachine(), RVLocs, *DAG.getContext());
3379 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3381 // Copy all of the result registers out of their specified physreg.
3382 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3383 CCValAssign &VA = RVLocs[i];
3384 assert(VA.isRegLoc() && "Can only return in registers!");
3386 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3387 VA.getLocReg(), VA.getLocVT(), InFlag);
3388 Chain = Val.getValue(1);
3389 InFlag = Val.getValue(2);
3391 switch (VA.getLocInfo()) {
3392 default: llvm_unreachable("Unknown loc info!");
3393 case CCValAssign::Full: break;
3394 case CCValAssign::AExt:
3395 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3397 case CCValAssign::ZExt:
3398 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3399 DAG.getValueType(VA.getValVT()));
3400 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3402 case CCValAssign::SExt:
3403 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3404 DAG.getValueType(VA.getValVT()));
3405 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3409 InVals.push_back(Val);
3416 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3417 bool isTailCall, bool isVarArg,
3419 SmallVector<std::pair<unsigned, SDValue>, 8>
3421 SDValue InFlag, SDValue Chain,
3423 int SPDiff, unsigned NumBytes,
3424 const SmallVectorImpl<ISD::InputArg> &Ins,
3425 SmallVectorImpl<SDValue> &InVals) const {
3426 std::vector<EVT> NodeTys;
3427 SmallVector<SDValue, 8> Ops;
3428 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3429 isTailCall, RegsToPass, Ops, NodeTys,
3432 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3433 if (isVarArg && PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
3434 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3436 // When performing tail call optimization the callee pops its arguments off
3437 // the stack. Account for this here so these bytes can be pushed back on in
3438 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3439 int BytesCalleePops =
3440 (CallConv == CallingConv::Fast &&
3441 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3443 // Add a register mask operand representing the call-preserved registers.
3444 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3445 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3446 assert(Mask && "Missing call preserved mask for calling convention");
3447 Ops.push_back(DAG.getRegisterMask(Mask));
3449 if (InFlag.getNode())
3450 Ops.push_back(InFlag);
3454 assert(((Callee.getOpcode() == ISD::Register &&
3455 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3456 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3457 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3458 isa<ConstantSDNode>(Callee)) &&
3459 "Expecting an global address, external symbol, absolute value or register");
3461 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
3464 // Add a NOP immediately after the branch instruction when using the 64-bit
3465 // SVR4 ABI. At link time, if caller and callee are in a different module and
3466 // thus have a different TOC, the call will be replaced with a call to a stub
3467 // function which saves the current TOC, loads the TOC of the callee and
3468 // branches to the callee. The NOP will be replaced with a load instruction
3469 // which restores the TOC of the caller from the TOC save slot of the current
3470 // stack frame. If caller and callee belong to the same module (and have the
3471 // same TOC), the NOP will remain unchanged.
3473 bool needsTOCRestore = false;
3474 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
3475 if (CallOpc == PPCISD::BCTRL) {
3476 // This is a call through a function pointer.
3477 // Restore the caller TOC from the save area into R2.
3478 // See PrepareCall() for more information about calls through function
3479 // pointers in the 64-bit SVR4 ABI.
3480 // We are using a target-specific load with r2 hard coded, because the
3481 // result of a target-independent load would never go directly into r2,
3482 // since r2 is a reserved register (which prevents the register allocator
3483 // from allocating it), resulting in an additional register being
3484 // allocated and an unnecessary move instruction being generated.
3485 needsTOCRestore = true;
3486 } else if ((CallOpc == PPCISD::CALL) && !isLocalCall(Callee)) {
3487 // Otherwise insert NOP for non-local calls.
3488 CallOpc = PPCISD::CALL_NOP;
3492 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
3493 InFlag = Chain.getValue(1);
3495 if (needsTOCRestore) {
3496 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3497 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3498 InFlag = Chain.getValue(1);
3501 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3502 DAG.getIntPtrConstant(BytesCalleePops, true),
3505 InFlag = Chain.getValue(1);
3507 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3508 Ins, dl, DAG, InVals);
3512 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3513 SmallVectorImpl<SDValue> &InVals) const {
3514 SelectionDAG &DAG = CLI.DAG;
3516 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3517 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3518 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3519 SDValue Chain = CLI.Chain;
3520 SDValue Callee = CLI.Callee;
3521 bool &isTailCall = CLI.IsTailCall;
3522 CallingConv::ID CallConv = CLI.CallConv;
3523 bool isVarArg = CLI.IsVarArg;
3526 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3529 if (PPCSubTarget.isSVR4ABI()) {
3530 if (PPCSubTarget.isPPC64())
3531 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3532 isTailCall, Outs, OutVals, Ins,
3535 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3536 isTailCall, Outs, OutVals, Ins,
3540 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3541 isTailCall, Outs, OutVals, Ins,
3546 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3547 CallingConv::ID CallConv, bool isVarArg,
3549 const SmallVectorImpl<ISD::OutputArg> &Outs,
3550 const SmallVectorImpl<SDValue> &OutVals,
3551 const SmallVectorImpl<ISD::InputArg> &Ins,
3552 SDLoc dl, SelectionDAG &DAG,
3553 SmallVectorImpl<SDValue> &InVals) const {
3554 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3555 // of the 32-bit SVR4 ABI stack frame layout.
3557 assert((CallConv == CallingConv::C ||
3558 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3560 unsigned PtrByteSize = 4;
3562 MachineFunction &MF = DAG.getMachineFunction();
3564 // Mark this function as potentially containing a function that contains a
3565 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3566 // and restoring the callers stack pointer in this functions epilog. This is
3567 // done because by tail calling the called function might overwrite the value
3568 // in this function's (MF) stack pointer stack slot 0(SP).
3569 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3570 CallConv == CallingConv::Fast)
3571 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3573 // Count how many bytes are to be pushed on the stack, including the linkage
3574 // area, parameter list area and the part of the local variable space which
3575 // contains copies of aggregates which are passed by value.
3577 // Assign locations to all of the outgoing arguments.
3578 SmallVector<CCValAssign, 16> ArgLocs;
3579 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3580 getTargetMachine(), ArgLocs, *DAG.getContext());
3582 // Reserve space for the linkage area on the stack.
3583 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3586 // Handle fixed and variable vector arguments differently.
3587 // Fixed vector arguments go into registers as long as registers are
3588 // available. Variable vector arguments always go into memory.
3589 unsigned NumArgs = Outs.size();
3591 for (unsigned i = 0; i != NumArgs; ++i) {
3592 MVT ArgVT = Outs[i].VT;
3593 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3596 if (Outs[i].IsFixed) {
3597 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3600 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3606 errs() << "Call operand #" << i << " has unhandled type "
3607 << EVT(ArgVT).getEVTString() << "\n";
3609 llvm_unreachable(0);
3613 // All arguments are treated the same.
3614 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3617 // Assign locations to all of the outgoing aggregate by value arguments.
3618 SmallVector<CCValAssign, 16> ByValArgLocs;
3619 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3620 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3622 // Reserve stack space for the allocations in CCInfo.
3623 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3625 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3627 // Size of the linkage area, parameter list area and the part of the local
3628 // space variable where copies of aggregates which are passed by value are
3630 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3632 // Calculate by how many bytes the stack has to be adjusted in case of tail
3633 // call optimization.
3634 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3636 // Adjust the stack pointer for the new arguments...
3637 // These operations are automatically eliminated by the prolog/epilog pass
3638 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3640 SDValue CallSeqStart = Chain;
3642 // Load the return address and frame pointer so it can be moved somewhere else
3645 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3648 // Set up a copy of the stack pointer for use loading and storing any
3649 // arguments that may not fit in the registers available for argument
3651 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3653 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3654 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3655 SmallVector<SDValue, 8> MemOpChains;
3657 bool seenFloatArg = false;
3658 // Walk the register/memloc assignments, inserting copies/loads.
3659 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3662 CCValAssign &VA = ArgLocs[i];
3663 SDValue Arg = OutVals[i];
3664 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3666 if (Flags.isByVal()) {
3667 // Argument is an aggregate which is passed by value, thus we need to
3668 // create a copy of it in the local variable space of the current stack
3669 // frame (which is the stack frame of the caller) and pass the address of
3670 // this copy to the callee.
3671 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3672 CCValAssign &ByValVA = ByValArgLocs[j++];
3673 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3675 // Memory reserved in the local variable space of the callers stack frame.
3676 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3678 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3679 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3681 // Create a copy of the argument in the local area of the current
3683 SDValue MemcpyCall =
3684 CreateCopyOfByValArgument(Arg, PtrOff,
3685 CallSeqStart.getNode()->getOperand(0),
3688 // This must go outside the CALLSEQ_START..END.
3689 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3690 CallSeqStart.getNode()->getOperand(1),
3692 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3693 NewCallSeqStart.getNode());
3694 Chain = CallSeqStart = NewCallSeqStart;
3696 // Pass the address of the aggregate copy on the stack either in a
3697 // physical register or in the parameter list area of the current stack
3698 // frame to the callee.
3702 if (VA.isRegLoc()) {
3703 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3704 // Put argument in a physical register.
3705 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3707 // Put argument in the parameter list area of the current stack frame.
3708 assert(VA.isMemLoc());
3709 unsigned LocMemOffset = VA.getLocMemOffset();
3712 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3713 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3715 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3716 MachinePointerInfo(),
3719 // Calculate and remember argument location.
3720 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3726 if (!MemOpChains.empty())
3727 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3728 &MemOpChains[0], MemOpChains.size());
3730 // Build a sequence of copy-to-reg nodes chained together with token chain
3731 // and flag operands which copy the outgoing args into the appropriate regs.
3733 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3734 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3735 RegsToPass[i].second, InFlag);
3736 InFlag = Chain.getValue(1);
3739 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3742 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3743 SDValue Ops[] = { Chain, InFlag };
3745 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3746 dl, VTs, Ops, InFlag.getNode() ? 2 : 1);
3748 InFlag = Chain.getValue(1);
3752 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3753 false, TailCallArguments);
3755 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3756 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3760 // Copy an argument into memory, being careful to do this outside the
3761 // call sequence for the call to which the argument belongs.
3763 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3764 SDValue CallSeqStart,
3765 ISD::ArgFlagsTy Flags,
3768 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3769 CallSeqStart.getNode()->getOperand(0),
3771 // The MEMCPY must go outside the CALLSEQ_START..END.
3772 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3773 CallSeqStart.getNode()->getOperand(1),
3775 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3776 NewCallSeqStart.getNode());
3777 return NewCallSeqStart;
3781 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
3782 CallingConv::ID CallConv, bool isVarArg,
3784 const SmallVectorImpl<ISD::OutputArg> &Outs,
3785 const SmallVectorImpl<SDValue> &OutVals,
3786 const SmallVectorImpl<ISD::InputArg> &Ins,
3787 SDLoc dl, SelectionDAG &DAG,
3788 SmallVectorImpl<SDValue> &InVals) const {
3790 unsigned NumOps = Outs.size();
3792 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3793 unsigned PtrByteSize = 8;
3795 MachineFunction &MF = DAG.getMachineFunction();
3797 // Mark this function as potentially containing a function that contains a
3798 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3799 // and restoring the callers stack pointer in this functions epilog. This is
3800 // done because by tail calling the called function might overwrite the value
3801 // in this function's (MF) stack pointer stack slot 0(SP).
3802 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3803 CallConv == CallingConv::Fast)
3804 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3806 unsigned nAltivecParamsAtEnd = 0;
3808 // Count how many bytes are to be pushed on the stack, including the linkage
3809 // area, and parameter passing area. We start with at least 48 bytes, which
3810 // is reserved space for [SP][CR][LR][3 x unused].
3811 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
3814 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
3815 Outs, OutVals, nAltivecParamsAtEnd);
3817 // Calculate by how many bytes the stack has to be adjusted in case of tail
3818 // call optimization.
3819 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3821 // To protect arguments on the stack from being clobbered in a tail call,
3822 // force all the loads to happen before doing any other lowering.
3824 Chain = DAG.getStackArgumentTokenFactor(Chain);
3826 // Adjust the stack pointer for the new arguments...
3827 // These operations are automatically eliminated by the prolog/epilog pass
3828 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3830 SDValue CallSeqStart = Chain;
3832 // Load the return address and frame pointer so it can be move somewhere else
3835 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3838 // Set up a copy of the stack pointer for use loading and storing any
3839 // arguments that may not fit in the registers available for argument
3841 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3843 // Figure out which arguments are going to go in registers, and which in
3844 // memory. Also, if this is a vararg function, floating point operations
3845 // must be stored to our stack, and loaded into integer regs as well, if
3846 // any integer regs are available for argument passing.
3847 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
3848 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3850 static const uint16_t GPR[] = {
3851 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3852 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3854 static const uint16_t *FPR = GetFPR();
3856 static const uint16_t VR[] = {
3857 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3858 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3860 const unsigned NumGPRs = array_lengthof(GPR);
3861 const unsigned NumFPRs = 13;
3862 const unsigned NumVRs = array_lengthof(VR);
3864 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3865 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3867 SmallVector<SDValue, 8> MemOpChains;
3868 for (unsigned i = 0; i != NumOps; ++i) {
3869 SDValue Arg = OutVals[i];
3870 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3872 // PtrOff will be used to store the current argument to the stack if a
3873 // register cannot be found for it.
3876 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3878 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3880 // Promote integers to 64-bit values.
3881 if (Arg.getValueType() == MVT::i32) {
3882 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3883 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3884 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3887 // FIXME memcpy is used way more than necessary. Correctness first.
3888 // Note: "by value" is code for passing a structure by value, not
3890 if (Flags.isByVal()) {
3891 // Note: Size includes alignment padding, so
3892 // struct x { short a; char b; }
3893 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
3894 // These are the proper values we need for right-justifying the
3895 // aggregate in a parameter register.
3896 unsigned Size = Flags.getByValSize();
3898 // An empty aggregate parameter takes up no storage and no
3903 unsigned BVAlign = Flags.getByValAlign();
3905 if (BVAlign % PtrByteSize != 0)
3907 "ByVal alignment is not a multiple of the pointer size");
3909 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
3912 // All aggregates smaller than 8 bytes must be passed right-justified.
3913 if (Size==1 || Size==2 || Size==4) {
3914 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
3915 if (GPR_idx != NumGPRs) {
3916 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3917 MachinePointerInfo(), VT,
3919 MemOpChains.push_back(Load.getValue(1));
3920 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3922 ArgOffset += PtrByteSize;
3927 if (GPR_idx == NumGPRs && Size < 8) {
3928 SDValue Const = DAG.getConstant(PtrByteSize - Size,
3929 PtrOff.getValueType());
3930 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3931 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3934 ArgOffset += PtrByteSize;
3937 // Copy entire object into memory. There are cases where gcc-generated
3938 // code assumes it is there, even if it could be put entirely into
3939 // registers. (This is not what the doc says.)
3941 // FIXME: The above statement is likely due to a misunderstanding of the
3942 // documents. All arguments must be copied into the parameter area BY
3943 // THE CALLEE in the event that the callee takes the address of any
3944 // formal argument. That has not yet been implemented. However, it is
3945 // reasonable to use the stack area as a staging area for the register
3948 // Skip this for small aggregates, as we will use the same slot for a
3949 // right-justified copy, below.
3951 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
3955 // When a register is available, pass a small aggregate right-justified.
3956 if (Size < 8 && GPR_idx != NumGPRs) {
3957 // The easiest way to get this right-justified in a register
3958 // is to copy the structure into the rightmost portion of a
3959 // local variable slot, then load the whole slot into the
3961 // FIXME: The memcpy seems to produce pretty awful code for
3962 // small aggregates, particularly for packed ones.
3963 // FIXME: It would be preferable to use the slot in the
3964 // parameter save area instead of a new local variable.
3965 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
3966 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3967 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
3971 // Load the slot into the register.
3972 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
3973 MachinePointerInfo(),
3974 false, false, false, 0);
3975 MemOpChains.push_back(Load.getValue(1));
3976 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3978 // Done with this argument.
3979 ArgOffset += PtrByteSize;
3983 // For aggregates larger than PtrByteSize, copy the pieces of the
3984 // object that fit into registers from the parameter save area.
3985 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3986 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3987 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3988 if (GPR_idx != NumGPRs) {
3989 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3990 MachinePointerInfo(),
3991 false, false, false, 0);
3992 MemOpChains.push_back(Load.getValue(1));
3993 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3994 ArgOffset += PtrByteSize;
3996 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4003 switch (Arg.getSimpleValueType().SimpleTy) {
4004 default: llvm_unreachable("Unexpected ValueType for argument!");
4007 if (GPR_idx != NumGPRs) {
4008 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4010 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4011 true, isTailCall, false, MemOpChains,
4012 TailCallArguments, dl);
4014 ArgOffset += PtrByteSize;
4018 if (FPR_idx != NumFPRs) {
4019 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4022 // A single float or an aggregate containing only a single float
4023 // must be passed right-justified in the stack doubleword, and
4024 // in the GPR, if one is available.
4026 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4027 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4028 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4032 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4033 MachinePointerInfo(), false, false, 0);
4034 MemOpChains.push_back(Store);
4036 // Float varargs are always shadowed in available integer registers
4037 if (GPR_idx != NumGPRs) {
4038 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4039 MachinePointerInfo(), false, false,
4041 MemOpChains.push_back(Load.getValue(1));
4042 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4044 } else if (GPR_idx != NumGPRs)
4045 // If we have any FPRs remaining, we may also have GPRs remaining.
4048 // Single-precision floating-point values are mapped to the
4049 // second (rightmost) word of the stack doubleword.
4050 if (Arg.getValueType() == MVT::f32) {
4051 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4052 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4055 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4056 true, isTailCall, false, MemOpChains,
4057 TailCallArguments, dl);
4066 // These go aligned on the stack, or in the corresponding R registers
4067 // when within range. The Darwin PPC ABI doc claims they also go in
4068 // V registers; in fact gcc does this only for arguments that are
4069 // prototyped, not for those that match the ... We do it for all
4070 // arguments, seems to work.
4071 while (ArgOffset % 16 !=0) {
4072 ArgOffset += PtrByteSize;
4073 if (GPR_idx != NumGPRs)
4076 // We could elide this store in the case where the object fits
4077 // entirely in R registers. Maybe later.
4078 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4079 DAG.getConstant(ArgOffset, PtrVT));
4080 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4081 MachinePointerInfo(), false, false, 0);
4082 MemOpChains.push_back(Store);
4083 if (VR_idx != NumVRs) {
4084 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4085 MachinePointerInfo(),
4086 false, false, false, 0);
4087 MemOpChains.push_back(Load.getValue(1));
4088 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4091 for (unsigned i=0; i<16; i+=PtrByteSize) {
4092 if (GPR_idx == NumGPRs)
4094 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4095 DAG.getConstant(i, PtrVT));
4096 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4097 false, false, false, 0);
4098 MemOpChains.push_back(Load.getValue(1));
4099 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4104 // Non-varargs Altivec params generally go in registers, but have
4105 // stack space allocated at the end.
4106 if (VR_idx != NumVRs) {
4107 // Doesn't have GPR space allocated.
4108 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4110 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4111 true, isTailCall, true, MemOpChains,
4112 TailCallArguments, dl);
4119 if (!MemOpChains.empty())
4120 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4121 &MemOpChains[0], MemOpChains.size());
4123 // Check if this is an indirect call (MTCTR/BCTRL).
4124 // See PrepareCall() for more information about calls through function
4125 // pointers in the 64-bit SVR4 ABI.
4127 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4128 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4129 !isBLACompatibleAddress(Callee, DAG)) {
4130 // Load r2 into a virtual register and store it to the TOC save area.
4131 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4132 // TOC save area offset.
4133 SDValue PtrOff = DAG.getIntPtrConstant(40);
4134 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4135 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4137 // R12 must contain the address of an indirect callee. This does not
4138 // mean the MTCTR instruction must use R12; it's easier to model this
4139 // as an extra parameter, so do that.
4140 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4143 // Build a sequence of copy-to-reg nodes chained together with token chain
4144 // and flag operands which copy the outgoing args into the appropriate regs.
4146 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4147 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4148 RegsToPass[i].second, InFlag);
4149 InFlag = Chain.getValue(1);
4153 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4154 FPOp, true, TailCallArguments);
4156 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4157 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4162 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4163 CallingConv::ID CallConv, bool isVarArg,
4165 const SmallVectorImpl<ISD::OutputArg> &Outs,
4166 const SmallVectorImpl<SDValue> &OutVals,
4167 const SmallVectorImpl<ISD::InputArg> &Ins,
4168 SDLoc dl, SelectionDAG &DAG,
4169 SmallVectorImpl<SDValue> &InVals) const {
4171 unsigned NumOps = Outs.size();
4173 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4174 bool isPPC64 = PtrVT == MVT::i64;
4175 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4177 MachineFunction &MF = DAG.getMachineFunction();
4179 // Mark this function as potentially containing a function that contains a
4180 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4181 // and restoring the callers stack pointer in this functions epilog. This is
4182 // done because by tail calling the called function might overwrite the value
4183 // in this function's (MF) stack pointer stack slot 0(SP).
4184 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4185 CallConv == CallingConv::Fast)
4186 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4188 unsigned nAltivecParamsAtEnd = 0;
4190 // Count how many bytes are to be pushed on the stack, including the linkage
4191 // area, and parameter passing area. We start with 24/48 bytes, which is
4192 // prereserved space for [SP][CR][LR][3 x unused].
4194 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4196 nAltivecParamsAtEnd);
4198 // Calculate by how many bytes the stack has to be adjusted in case of tail
4199 // call optimization.
4200 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4202 // To protect arguments on the stack from being clobbered in a tail call,
4203 // force all the loads to happen before doing any other lowering.
4205 Chain = DAG.getStackArgumentTokenFactor(Chain);
4207 // Adjust the stack pointer for the new arguments...
4208 // These operations are automatically eliminated by the prolog/epilog pass
4209 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4211 SDValue CallSeqStart = Chain;
4213 // Load the return address and frame pointer so it can be move somewhere else
4216 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4219 // Set up a copy of the stack pointer for use loading and storing any
4220 // arguments that may not fit in the registers available for argument
4224 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4226 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4228 // Figure out which arguments are going to go in registers, and which in
4229 // memory. Also, if this is a vararg function, floating point operations
4230 // must be stored to our stack, and loaded into integer regs as well, if
4231 // any integer regs are available for argument passing.
4232 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4233 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4235 static const uint16_t GPR_32[] = { // 32-bit registers.
4236 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4237 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4239 static const uint16_t GPR_64[] = { // 64-bit registers.
4240 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4241 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4243 static const uint16_t *FPR = GetFPR();
4245 static const uint16_t VR[] = {
4246 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4247 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4249 const unsigned NumGPRs = array_lengthof(GPR_32);
4250 const unsigned NumFPRs = 13;
4251 const unsigned NumVRs = array_lengthof(VR);
4253 const uint16_t *GPR = isPPC64 ? GPR_64 : GPR_32;
4255 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4256 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4258 SmallVector<SDValue, 8> MemOpChains;
4259 for (unsigned i = 0; i != NumOps; ++i) {
4260 SDValue Arg = OutVals[i];
4261 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4263 // PtrOff will be used to store the current argument to the stack if a
4264 // register cannot be found for it.
4267 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4269 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4271 // On PPC64, promote integers to 64-bit values.
4272 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4273 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4274 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4275 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4278 // FIXME memcpy is used way more than necessary. Correctness first.
4279 // Note: "by value" is code for passing a structure by value, not
4281 if (Flags.isByVal()) {
4282 unsigned Size = Flags.getByValSize();
4283 // Very small objects are passed right-justified. Everything else is
4284 // passed left-justified.
4285 if (Size==1 || Size==2) {
4286 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4287 if (GPR_idx != NumGPRs) {
4288 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4289 MachinePointerInfo(), VT,
4291 MemOpChains.push_back(Load.getValue(1));
4292 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4294 ArgOffset += PtrByteSize;
4296 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4297 PtrOff.getValueType());
4298 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4299 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4302 ArgOffset += PtrByteSize;
4306 // Copy entire object into memory. There are cases where gcc-generated
4307 // code assumes it is there, even if it could be put entirely into
4308 // registers. (This is not what the doc says.)
4309 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4313 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4314 // copy the pieces of the object that fit into registers from the
4315 // parameter save area.
4316 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4317 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4318 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4319 if (GPR_idx != NumGPRs) {
4320 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4321 MachinePointerInfo(),
4322 false, false, false, 0);
4323 MemOpChains.push_back(Load.getValue(1));
4324 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4325 ArgOffset += PtrByteSize;
4327 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4334 switch (Arg.getSimpleValueType().SimpleTy) {
4335 default: llvm_unreachable("Unexpected ValueType for argument!");
4338 if (GPR_idx != NumGPRs) {
4339 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4341 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4342 isPPC64, isTailCall, false, MemOpChains,
4343 TailCallArguments, dl);
4345 ArgOffset += PtrByteSize;
4349 if (FPR_idx != NumFPRs) {
4350 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4353 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4354 MachinePointerInfo(), false, false, 0);
4355 MemOpChains.push_back(Store);
4357 // Float varargs are always shadowed in available integer registers
4358 if (GPR_idx != NumGPRs) {
4359 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4360 MachinePointerInfo(), false, false,
4362 MemOpChains.push_back(Load.getValue(1));
4363 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4365 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4366 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4367 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4368 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4369 MachinePointerInfo(),
4370 false, false, false, 0);
4371 MemOpChains.push_back(Load.getValue(1));
4372 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4375 // If we have any FPRs remaining, we may also have GPRs remaining.
4376 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4378 if (GPR_idx != NumGPRs)
4380 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4381 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4385 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4386 isPPC64, isTailCall, false, MemOpChains,
4387 TailCallArguments, dl);
4391 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4398 // These go aligned on the stack, or in the corresponding R registers
4399 // when within range. The Darwin PPC ABI doc claims they also go in
4400 // V registers; in fact gcc does this only for arguments that are
4401 // prototyped, not for those that match the ... We do it for all
4402 // arguments, seems to work.
4403 while (ArgOffset % 16 !=0) {
4404 ArgOffset += PtrByteSize;
4405 if (GPR_idx != NumGPRs)
4408 // We could elide this store in the case where the object fits
4409 // entirely in R registers. Maybe later.
4410 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4411 DAG.getConstant(ArgOffset, PtrVT));
4412 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4413 MachinePointerInfo(), false, false, 0);
4414 MemOpChains.push_back(Store);
4415 if (VR_idx != NumVRs) {
4416 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4417 MachinePointerInfo(),
4418 false, false, false, 0);
4419 MemOpChains.push_back(Load.getValue(1));
4420 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4423 for (unsigned i=0; i<16; i+=PtrByteSize) {
4424 if (GPR_idx == NumGPRs)
4426 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4427 DAG.getConstant(i, PtrVT));
4428 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4429 false, false, false, 0);
4430 MemOpChains.push_back(Load.getValue(1));
4431 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4436 // Non-varargs Altivec params generally go in registers, but have
4437 // stack space allocated at the end.
4438 if (VR_idx != NumVRs) {
4439 // Doesn't have GPR space allocated.
4440 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4441 } else if (nAltivecParamsAtEnd==0) {
4442 // We are emitting Altivec params in order.
4443 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4444 isPPC64, isTailCall, true, MemOpChains,
4445 TailCallArguments, dl);
4451 // If all Altivec parameters fit in registers, as they usually do,
4452 // they get stack space following the non-Altivec parameters. We
4453 // don't track this here because nobody below needs it.
4454 // If there are more Altivec parameters than fit in registers emit
4456 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4458 // Offset is aligned; skip 1st 12 params which go in V registers.
4459 ArgOffset = ((ArgOffset+15)/16)*16;
4461 for (unsigned i = 0; i != NumOps; ++i) {
4462 SDValue Arg = OutVals[i];
4463 EVT ArgType = Outs[i].VT;
4464 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4465 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4468 // We are emitting Altivec params in order.
4469 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4470 isPPC64, isTailCall, true, MemOpChains,
4471 TailCallArguments, dl);
4478 if (!MemOpChains.empty())
4479 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
4480 &MemOpChains[0], MemOpChains.size());
4482 // On Darwin, R12 must contain the address of an indirect callee. This does
4483 // not mean the MTCTR instruction must use R12; it's easier to model this as
4484 // an extra parameter, so do that.
4486 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4487 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4488 !isBLACompatibleAddress(Callee, DAG))
4489 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4490 PPC::R12), Callee));
4492 // Build a sequence of copy-to-reg nodes chained together with token chain
4493 // and flag operands which copy the outgoing args into the appropriate regs.
4495 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4496 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4497 RegsToPass[i].second, InFlag);
4498 InFlag = Chain.getValue(1);
4502 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4503 FPOp, true, TailCallArguments);
4505 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4506 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4511 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4512 MachineFunction &MF, bool isVarArg,
4513 const SmallVectorImpl<ISD::OutputArg> &Outs,
4514 LLVMContext &Context) const {
4515 SmallVector<CCValAssign, 16> RVLocs;
4516 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4518 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4522 PPCTargetLowering::LowerReturn(SDValue Chain,
4523 CallingConv::ID CallConv, bool isVarArg,
4524 const SmallVectorImpl<ISD::OutputArg> &Outs,
4525 const SmallVectorImpl<SDValue> &OutVals,
4526 SDLoc dl, SelectionDAG &DAG) const {
4528 SmallVector<CCValAssign, 16> RVLocs;
4529 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4530 getTargetMachine(), RVLocs, *DAG.getContext());
4531 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4534 SmallVector<SDValue, 4> RetOps(1, Chain);
4536 // Copy the result values into the output registers.
4537 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4538 CCValAssign &VA = RVLocs[i];
4539 assert(VA.isRegLoc() && "Can only return in registers!");
4541 SDValue Arg = OutVals[i];
4543 switch (VA.getLocInfo()) {
4544 default: llvm_unreachable("Unknown loc info!");
4545 case CCValAssign::Full: break;
4546 case CCValAssign::AExt:
4547 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4549 case CCValAssign::ZExt:
4550 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4552 case CCValAssign::SExt:
4553 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4557 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4558 Flag = Chain.getValue(1);
4559 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4562 RetOps[0] = Chain; // Update chain.
4564 // Add the flag if we have it.
4566 RetOps.push_back(Flag);
4568 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other,
4569 &RetOps[0], RetOps.size());
4572 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4573 const PPCSubtarget &Subtarget) const {
4574 // When we pop the dynamic allocation we need to restore the SP link.
4577 // Get the corect type for pointers.
4578 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4580 // Construct the stack pointer operand.
4581 bool isPPC64 = Subtarget.isPPC64();
4582 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4583 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4585 // Get the operands for the STACKRESTORE.
4586 SDValue Chain = Op.getOperand(0);
4587 SDValue SaveSP = Op.getOperand(1);
4589 // Load the old link SP.
4590 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4591 MachinePointerInfo(),
4592 false, false, false, 0);
4594 // Restore the stack pointer.
4595 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4597 // Store the old link SP.
4598 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4605 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4606 MachineFunction &MF = DAG.getMachineFunction();
4607 bool isPPC64 = PPCSubTarget.isPPC64();
4608 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4609 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4611 // Get current frame pointer save index. The users of this index will be
4612 // primarily DYNALLOC instructions.
4613 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4614 int RASI = FI->getReturnAddrSaveIndex();
4616 // If the frame pointer save index hasn't been defined yet.
4618 // Find out what the fix offset of the frame pointer save area.
4619 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4620 // Allocate the frame index for frame pointer save area.
4621 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4623 FI->setReturnAddrSaveIndex(RASI);
4625 return DAG.getFrameIndex(RASI, PtrVT);
4629 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4630 MachineFunction &MF = DAG.getMachineFunction();
4631 bool isPPC64 = PPCSubTarget.isPPC64();
4632 bool isDarwinABI = PPCSubTarget.isDarwinABI();
4633 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4635 // Get current frame pointer save index. The users of this index will be
4636 // primarily DYNALLOC instructions.
4637 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4638 int FPSI = FI->getFramePointerSaveIndex();
4640 // If the frame pointer save index hasn't been defined yet.
4642 // Find out what the fix offset of the frame pointer save area.
4643 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4646 // Allocate the frame index for frame pointer save area.
4647 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4649 FI->setFramePointerSaveIndex(FPSI);
4651 return DAG.getFrameIndex(FPSI, PtrVT);
4654 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4656 const PPCSubtarget &Subtarget) const {
4658 SDValue Chain = Op.getOperand(0);
4659 SDValue Size = Op.getOperand(1);
4662 // Get the corect type for pointers.
4663 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4665 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4666 DAG.getConstant(0, PtrVT), Size);
4667 // Construct a node for the frame pointer save index.
4668 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4669 // Build a DYNALLOC node.
4670 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4671 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4672 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
4675 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4676 SelectionDAG &DAG) const {
4678 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4679 DAG.getVTList(MVT::i32, MVT::Other),
4680 Op.getOperand(0), Op.getOperand(1));
4683 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4684 SelectionDAG &DAG) const {
4686 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4687 Op.getOperand(0), Op.getOperand(1));
4690 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4692 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4693 // Not FP? Not a fsel.
4694 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
4695 !Op.getOperand(2).getValueType().isFloatingPoint())
4698 // We might be able to do better than this under some circumstances, but in
4699 // general, fsel-based lowering of select is a finite-math-only optimization.
4700 // For more information, see section F.3 of the 2.06 ISA specification.
4701 if (!DAG.getTarget().Options.NoInfsFPMath ||
4702 !DAG.getTarget().Options.NoNaNsFPMath)
4705 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
4707 EVT ResVT = Op.getValueType();
4708 EVT CmpVT = Op.getOperand(0).getValueType();
4709 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4710 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
4713 // If the RHS of the comparison is a 0.0, we don't need to do the
4714 // subtraction at all.
4716 if (isFloatingPointZero(RHS))
4718 default: break; // SETUO etc aren't handled by fsel.
4722 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4723 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4724 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4725 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4726 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4727 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4728 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
4731 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4734 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4735 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4736 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
4739 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
4742 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
4743 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
4744 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4745 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
4750 default: break; // SETUO etc aren't handled by fsel.
4754 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4755 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4756 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4757 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4758 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
4759 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
4760 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
4761 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
4764 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4765 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4766 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4767 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4770 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
4771 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4772 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4773 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4776 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4777 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4778 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4779 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
4782 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
4783 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
4784 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
4785 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
4790 // FIXME: Split this code up when LegalizeDAGTypes lands.
4791 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
4793 assert(Op.getOperand(0).getValueType().isFloatingPoint());
4794 SDValue Src = Op.getOperand(0);
4795 if (Src.getValueType() == MVT::f32)
4796 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
4799 switch (Op.getSimpleValueType().SimpleTy) {
4800 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
4802 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
4803 (PPCSubTarget.hasFPCVT() ? PPCISD::FCTIWUZ :
4808 assert((Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT()) &&
4809 "i64 FP_TO_UINT is supported only with FPCVT");
4810 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
4816 // Convert the FP value to an int value through memory.
4817 bool i32Stack = Op.getValueType() == MVT::i32 && PPCSubTarget.hasSTFIWX() &&
4818 (Op.getOpcode() == ISD::FP_TO_SINT || PPCSubTarget.hasFPCVT());
4819 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
4820 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
4821 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
4823 // Emit a store to the stack slot.
4826 MachineFunction &MF = DAG.getMachineFunction();
4827 MachineMemOperand *MMO =
4828 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
4829 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
4830 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
4831 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
4834 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
4835 MPI, false, false, 0);
4837 // Result is a load from the stack slot. If loading 4 bytes, make sure to
4839 if (Op.getValueType() == MVT::i32 && !i32Stack) {
4840 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
4841 DAG.getConstant(4, FIPtr.getValueType()));
4842 MPI = MachinePointerInfo();
4845 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
4846 false, false, false, 0);
4849 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
4850 SelectionDAG &DAG) const {
4852 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
4853 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
4856 assert((Op.getOpcode() == ISD::SINT_TO_FP || PPCSubTarget.hasFPCVT()) &&
4857 "UINT_TO_FP is supported only with FPCVT");
4859 // If we have FCFIDS, then use it when converting to single-precision.
4860 // Otherwise, convert to double-precision and then round.
4861 unsigned FCFOp = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4862 (Op.getOpcode() == ISD::UINT_TO_FP ?
4863 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
4864 (Op.getOpcode() == ISD::UINT_TO_FP ?
4865 PPCISD::FCFIDU : PPCISD::FCFID);
4866 MVT FCFTy = (PPCSubTarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
4867 MVT::f32 : MVT::f64;
4869 if (Op.getOperand(0).getValueType() == MVT::i64) {
4870 SDValue SINT = Op.getOperand(0);
4871 // When converting to single-precision, we actually need to convert
4872 // to double-precision first and then round to single-precision.
4873 // To avoid double-rounding effects during that operation, we have
4874 // to prepare the input operand. Bits that might be truncated when
4875 // converting to double-precision are replaced by a bit that won't
4876 // be lost at this stage, but is below the single-precision rounding
4879 // However, if -enable-unsafe-fp-math is in effect, accept double
4880 // rounding to avoid the extra overhead.
4881 if (Op.getValueType() == MVT::f32 &&
4882 !PPCSubTarget.hasFPCVT() &&
4883 !DAG.getTarget().Options.UnsafeFPMath) {
4885 // Twiddle input to make sure the low 11 bits are zero. (If this
4886 // is the case, we are guaranteed the value will fit into the 53 bit
4887 // mantissa of an IEEE double-precision value without rounding.)
4888 // If any of those low 11 bits were not zero originally, make sure
4889 // bit 12 (value 2048) is set instead, so that the final rounding
4890 // to single-precision gets the correct result.
4891 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4892 SINT, DAG.getConstant(2047, MVT::i64));
4893 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
4894 Round, DAG.getConstant(2047, MVT::i64));
4895 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
4896 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
4897 Round, DAG.getConstant(-2048, MVT::i64));
4899 // However, we cannot use that value unconditionally: if the magnitude
4900 // of the input value is small, the bit-twiddling we did above might
4901 // end up visibly changing the output. Fortunately, in that case, we
4902 // don't need to twiddle bits since the original input will convert
4903 // exactly to double-precision floating-point already. Therefore,
4904 // construct a conditional to use the original value if the top 11
4905 // bits are all sign-bit copies, and use the rounded value computed
4907 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
4908 SINT, DAG.getConstant(53, MVT::i32));
4909 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
4910 Cond, DAG.getConstant(1, MVT::i64));
4911 Cond = DAG.getSetCC(dl, MVT::i32,
4912 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
4914 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
4917 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
4918 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
4920 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4921 FP = DAG.getNode(ISD::FP_ROUND, dl,
4922 MVT::f32, FP, DAG.getIntPtrConstant(0));
4926 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
4927 "Unhandled INT_TO_FP type in custom expander!");
4928 // Since we only generate this in 64-bit mode, we can take advantage of
4929 // 64-bit registers. In particular, sign extend the input value into the
4930 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
4931 // then lfd it and fcfid it.
4932 MachineFunction &MF = DAG.getMachineFunction();
4933 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
4934 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4937 if (PPCSubTarget.hasLFIWAX() || PPCSubTarget.hasFPCVT()) {
4938 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
4939 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4941 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
4942 MachinePointerInfo::getFixedStack(FrameIdx),
4945 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
4946 "Expected an i32 store");
4947 MachineMemOperand *MMO =
4948 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
4949 MachineMemOperand::MOLoad, 4, 4);
4950 SDValue Ops[] = { Store, FIdx };
4951 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
4952 PPCISD::LFIWZX : PPCISD::LFIWAX,
4953 dl, DAG.getVTList(MVT::f64, MVT::Other),
4954 Ops, 2, MVT::i32, MMO);
4956 assert(PPCSubTarget.isPPC64() &&
4957 "i32->FP without LFIWAX supported only on PPC64");
4959 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
4960 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4962 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
4965 // STD the extended value into the stack slot.
4966 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
4967 MachinePointerInfo::getFixedStack(FrameIdx),
4970 // Load the value as a double.
4971 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
4972 MachinePointerInfo::getFixedStack(FrameIdx),
4973 false, false, false, 0);
4976 // FCFID it and return it.
4977 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
4978 if (Op.getValueType() == MVT::f32 && !PPCSubTarget.hasFPCVT())
4979 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
4983 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
4984 SelectionDAG &DAG) const {
4987 The rounding mode is in bits 30:31 of FPSR, and has the following
4994 FLT_ROUNDS, on the other hand, expects the following:
5001 To perform the conversion, we do:
5002 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5005 MachineFunction &MF = DAG.getMachineFunction();
5006 EVT VT = Op.getValueType();
5007 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5008 SDValue MFFSreg, InFlag;
5010 // Save FP Control Word to register
5012 MVT::f64, // return register
5013 MVT::Glue // unused in this context
5015 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
5017 // Save FP register to stack slot
5018 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5019 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5020 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5021 StackSlot, MachinePointerInfo(), false, false,0);
5023 // Load FP Control Word from low 32 bits of stack slot.
5024 SDValue Four = DAG.getConstant(4, PtrVT);
5025 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5026 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5027 false, false, false, 0);
5029 // Transform as necessary
5031 DAG.getNode(ISD::AND, dl, MVT::i32,
5032 CWD, DAG.getConstant(3, MVT::i32));
5034 DAG.getNode(ISD::SRL, dl, MVT::i32,
5035 DAG.getNode(ISD::AND, dl, MVT::i32,
5036 DAG.getNode(ISD::XOR, dl, MVT::i32,
5037 CWD, DAG.getConstant(3, MVT::i32)),
5038 DAG.getConstant(3, MVT::i32)),
5039 DAG.getConstant(1, MVT::i32));
5042 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5044 return DAG.getNode((VT.getSizeInBits() < 16 ?
5045 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5048 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5049 EVT VT = Op.getValueType();
5050 unsigned BitWidth = VT.getSizeInBits();
5052 assert(Op.getNumOperands() == 3 &&
5053 VT == Op.getOperand(1).getValueType() &&
5056 // Expand into a bunch of logical ops. Note that these ops
5057 // depend on the PPC behavior for oversized shift amounts.
5058 SDValue Lo = Op.getOperand(0);
5059 SDValue Hi = Op.getOperand(1);
5060 SDValue Amt = Op.getOperand(2);
5061 EVT AmtVT = Amt.getValueType();
5063 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5064 DAG.getConstant(BitWidth, AmtVT), Amt);
5065 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5066 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5067 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5068 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5069 DAG.getConstant(-BitWidth, AmtVT));
5070 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5071 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5072 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5073 SDValue OutOps[] = { OutLo, OutHi };
5074 return DAG.getMergeValues(OutOps, 2, dl);
5077 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5078 EVT VT = Op.getValueType();
5080 unsigned BitWidth = VT.getSizeInBits();
5081 assert(Op.getNumOperands() == 3 &&
5082 VT == Op.getOperand(1).getValueType() &&
5085 // Expand into a bunch of logical ops. Note that these ops
5086 // depend on the PPC behavior for oversized shift amounts.
5087 SDValue Lo = Op.getOperand(0);
5088 SDValue Hi = Op.getOperand(1);
5089 SDValue Amt = Op.getOperand(2);
5090 EVT AmtVT = Amt.getValueType();
5092 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5093 DAG.getConstant(BitWidth, AmtVT), Amt);
5094 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5095 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5096 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5097 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5098 DAG.getConstant(-BitWidth, AmtVT));
5099 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5100 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5101 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5102 SDValue OutOps[] = { OutLo, OutHi };
5103 return DAG.getMergeValues(OutOps, 2, dl);
5106 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5108 EVT VT = Op.getValueType();
5109 unsigned BitWidth = VT.getSizeInBits();
5110 assert(Op.getNumOperands() == 3 &&
5111 VT == Op.getOperand(1).getValueType() &&
5114 // Expand into a bunch of logical ops, followed by a select_cc.
5115 SDValue Lo = Op.getOperand(0);
5116 SDValue Hi = Op.getOperand(1);
5117 SDValue Amt = Op.getOperand(2);
5118 EVT AmtVT = Amt.getValueType();
5120 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5121 DAG.getConstant(BitWidth, AmtVT), Amt);
5122 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5123 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5124 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5125 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5126 DAG.getConstant(-BitWidth, AmtVT));
5127 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5128 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5129 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5130 Tmp4, Tmp6, ISD::SETLE);
5131 SDValue OutOps[] = { OutLo, OutHi };
5132 return DAG.getMergeValues(OutOps, 2, dl);
5135 //===----------------------------------------------------------------------===//
5136 // Vector related lowering.
5139 /// BuildSplatI - Build a canonical splati of Val with an element size of
5140 /// SplatSize. Cast the result to VT.
5141 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5142 SelectionDAG &DAG, SDLoc dl) {
5143 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5145 static const EVT VTys[] = { // canonical VT to use for each size.
5146 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5149 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5151 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5155 EVT CanonicalVT = VTys[SplatSize-1];
5157 // Build a canonical splat for this value.
5158 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5159 SmallVector<SDValue, 8> Ops;
5160 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5161 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
5162 &Ops[0], Ops.size());
5163 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5166 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5167 /// specified intrinsic ID.
5168 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5169 SelectionDAG &DAG, SDLoc dl,
5170 EVT DestVT = MVT::Other) {
5171 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5172 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5173 DAG.getConstant(IID, MVT::i32), Op);
5176 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5177 /// specified intrinsic ID.
5178 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5179 SelectionDAG &DAG, SDLoc dl,
5180 EVT DestVT = MVT::Other) {
5181 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5182 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5183 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5186 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5187 /// specified intrinsic ID.
5188 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5189 SDValue Op2, SelectionDAG &DAG,
5190 SDLoc dl, EVT DestVT = MVT::Other) {
5191 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5192 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5193 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5197 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5198 /// amount. The result has the specified value type.
5199 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5200 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5201 // Force LHS/RHS to be the right type.
5202 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5203 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5206 for (unsigned i = 0; i != 16; ++i)
5208 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5209 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5212 // If this is a case we can't handle, return null and let the default
5213 // expansion code take care of it. If we CAN select this case, and if it
5214 // selects to a single instruction, return Op. Otherwise, if we can codegen
5215 // this case more efficiently than a constant pool load, lower it to the
5216 // sequence of ops that should be used.
5217 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5218 SelectionDAG &DAG) const {
5220 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5221 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5223 // Check if this is a splat of a constant value.
5224 APInt APSplatBits, APSplatUndef;
5225 unsigned SplatBitSize;
5227 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5228 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5231 unsigned SplatBits = APSplatBits.getZExtValue();
5232 unsigned SplatUndef = APSplatUndef.getZExtValue();
5233 unsigned SplatSize = SplatBitSize / 8;
5235 // First, handle single instruction cases.
5238 if (SplatBits == 0) {
5239 // Canonicalize all zero vectors to be v4i32.
5240 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5241 SDValue Z = DAG.getConstant(0, MVT::i32);
5242 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5243 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5248 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5249 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5251 if (SextVal >= -16 && SextVal <= 15)
5252 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5255 // Two instruction sequences.
5257 // If this value is in the range [-32,30] and is even, use:
5258 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5259 // If this value is in the range [17,31] and is odd, use:
5260 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5261 // If this value is in the range [-31,-17] and is odd, use:
5262 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5263 // Note the last two are three-instruction sequences.
5264 if (SextVal >= -32 && SextVal <= 31) {
5265 // To avoid having these optimizations undone by constant folding,
5266 // we convert to a pseudo that will be expanded later into one of
5268 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5269 EVT VT = Op.getValueType();
5270 int Size = VT == MVT::v16i8 ? 1 : (VT == MVT::v8i16 ? 2 : 4);
5271 SDValue EltSize = DAG.getConstant(Size, MVT::i32);
5272 return DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5275 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5276 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5278 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5279 // Make -1 and vspltisw -1:
5280 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5282 // Make the VSLW intrinsic, computing 0x8000_0000.
5283 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5286 // xor by OnesV to invert it.
5287 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5288 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5291 // Check to see if this is a wide variety of vsplti*, binop self cases.
5292 static const signed char SplatCsts[] = {
5293 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5294 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5297 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5298 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5299 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5300 int i = SplatCsts[idx];
5302 // Figure out what shift amount will be used by altivec if shifted by i in
5304 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5306 // vsplti + shl self.
5307 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5308 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5309 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5310 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5311 Intrinsic::ppc_altivec_vslw
5313 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5314 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5317 // vsplti + srl self.
5318 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5319 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5320 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5321 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5322 Intrinsic::ppc_altivec_vsrw
5324 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5325 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5328 // vsplti + sra self.
5329 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5330 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5331 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5332 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5333 Intrinsic::ppc_altivec_vsraw
5335 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5336 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5339 // vsplti + rol self.
5340 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5341 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5342 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5343 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5344 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5345 Intrinsic::ppc_altivec_vrlw
5347 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5348 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5351 // t = vsplti c, result = vsldoi t, t, 1
5352 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5353 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5354 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5356 // t = vsplti c, result = vsldoi t, t, 2
5357 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5358 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5359 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5361 // t = vsplti c, result = vsldoi t, t, 3
5362 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5363 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5364 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5371 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5372 /// the specified operations to build the shuffle.
5373 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5374 SDValue RHS, SelectionDAG &DAG,
5376 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5377 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5378 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5381 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5393 if (OpNum == OP_COPY) {
5394 if (LHSID == (1*9+2)*9+3) return LHS;
5395 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5399 SDValue OpLHS, OpRHS;
5400 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5401 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5405 default: llvm_unreachable("Unknown i32 permute!");
5407 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5408 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5409 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5410 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5413 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5414 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5415 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5416 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5419 for (unsigned i = 0; i != 16; ++i)
5420 ShufIdxs[i] = (i&3)+0;
5423 for (unsigned i = 0; i != 16; ++i)
5424 ShufIdxs[i] = (i&3)+4;
5427 for (unsigned i = 0; i != 16; ++i)
5428 ShufIdxs[i] = (i&3)+8;
5431 for (unsigned i = 0; i != 16; ++i)
5432 ShufIdxs[i] = (i&3)+12;
5435 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5437 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5439 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5441 EVT VT = OpLHS.getValueType();
5442 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5443 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5444 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5445 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5448 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5449 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5450 /// return the code it can be lowered into. Worst case, it can always be
5451 /// lowered into a vperm.
5452 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5453 SelectionDAG &DAG) const {
5455 SDValue V1 = Op.getOperand(0);
5456 SDValue V2 = Op.getOperand(1);
5457 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5458 EVT VT = Op.getValueType();
5460 // Cases that are handled by instructions that take permute immediates
5461 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5462 // selected by the instruction selector.
5463 if (V2.getOpcode() == ISD::UNDEF) {
5464 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5465 PPC::isSplatShuffleMask(SVOp, 2) ||
5466 PPC::isSplatShuffleMask(SVOp, 4) ||
5467 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
5468 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
5469 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
5470 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
5471 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
5472 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
5473 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
5474 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
5475 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
5480 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5481 // and produce a fixed permutation. If any of these match, do not lower to
5483 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
5484 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
5485 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
5486 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
5487 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
5488 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
5489 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
5490 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
5491 PPC::isVMRGHShuffleMask(SVOp, 4, false))
5494 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5495 // perfect shuffle table to emit an optimal matching sequence.
5496 ArrayRef<int> PermMask = SVOp->getMask();
5498 unsigned PFIndexes[4];
5499 bool isFourElementShuffle = true;
5500 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5501 unsigned EltNo = 8; // Start out undef.
5502 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5503 if (PermMask[i*4+j] < 0)
5504 continue; // Undef, ignore it.
5506 unsigned ByteSource = PermMask[i*4+j];
5507 if ((ByteSource & 3) != j) {
5508 isFourElementShuffle = false;
5513 EltNo = ByteSource/4;
5514 } else if (EltNo != ByteSource/4) {
5515 isFourElementShuffle = false;
5519 PFIndexes[i] = EltNo;
5522 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5523 // perfect shuffle vector to determine if it is cost effective to do this as
5524 // discrete instructions, or whether we should use a vperm.
5525 if (isFourElementShuffle) {
5526 // Compute the index in the perfect shuffle table.
5527 unsigned PFTableIndex =
5528 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5530 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5531 unsigned Cost = (PFEntry >> 30);
5533 // Determining when to avoid vperm is tricky. Many things affect the cost
5534 // of vperm, particularly how many times the perm mask needs to be computed.
5535 // For example, if the perm mask can be hoisted out of a loop or is already
5536 // used (perhaps because there are multiple permutes with the same shuffle
5537 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5538 // the loop requires an extra register.
5540 // As a compromise, we only emit discrete instructions if the shuffle can be
5541 // generated in 3 or fewer operations. When we have loop information
5542 // available, if this block is within a loop, we should avoid using vperm
5543 // for 3-operation perms and use a constant pool load instead.
5545 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5548 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5549 // vector that will get spilled to the constant pool.
5550 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5552 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5553 // that it is in input element units, not in bytes. Convert now.
5554 EVT EltVT = V1.getValueType().getVectorElementType();
5555 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5557 SmallVector<SDValue, 16> ResultMask;
5558 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5559 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5561 for (unsigned j = 0; j != BytesPerElement; ++j)
5562 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5566 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5567 &ResultMask[0], ResultMask.size());
5568 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
5571 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5572 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5573 /// information about the intrinsic.
5574 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5576 unsigned IntrinsicID =
5577 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5580 switch (IntrinsicID) {
5581 default: return false;
5582 // Comparison predicates.
5583 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5584 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5585 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5586 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5587 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5588 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5589 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5590 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5591 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5592 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5593 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5594 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5595 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5597 // Normal Comparisons.
5598 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5599 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5600 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5601 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5602 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5603 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5604 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5605 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5606 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5607 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5608 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5609 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5610 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5615 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5616 /// lower, do it, otherwise return null.
5617 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5618 SelectionDAG &DAG) const {
5619 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5620 // opcode number of the comparison.
5624 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5625 return SDValue(); // Don't custom lower most intrinsics.
5627 // If this is a non-dot comparison, make the VCMP node and we are done.
5629 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5630 Op.getOperand(1), Op.getOperand(2),
5631 DAG.getConstant(CompareOpc, MVT::i32));
5632 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5635 // Create the PPCISD altivec 'dot' comparison node.
5637 Op.getOperand(2), // LHS
5638 Op.getOperand(3), // RHS
5639 DAG.getConstant(CompareOpc, MVT::i32)
5641 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5642 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5644 // Now that we have the comparison, emit a copy from the CR to a GPR.
5645 // This is flagged to the above dot comparison.
5646 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5647 DAG.getRegister(PPC::CR6, MVT::i32),
5648 CompNode.getValue(1));
5650 // Unpack the result based on how the target uses it.
5651 unsigned BitNo; // Bit # of CR6.
5652 bool InvertBit; // Invert result?
5653 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5654 default: // Can't happen, don't crash on invalid number though.
5655 case 0: // Return the value of the EQ bit of CR6.
5656 BitNo = 0; InvertBit = false;
5658 case 1: // Return the inverted value of the EQ bit of CR6.
5659 BitNo = 0; InvertBit = true;
5661 case 2: // Return the value of the LT bit of CR6.
5662 BitNo = 2; InvertBit = false;
5664 case 3: // Return the inverted value of the LT bit of CR6.
5665 BitNo = 2; InvertBit = true;
5669 // Shift the bit into the low position.
5670 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
5671 DAG.getConstant(8-(3-BitNo), MVT::i32));
5673 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
5674 DAG.getConstant(1, MVT::i32));
5676 // If we are supposed to, toggle the bit.
5678 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
5679 DAG.getConstant(1, MVT::i32));
5683 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
5684 SelectionDAG &DAG) const {
5686 // Create a stack slot that is 16-byte aligned.
5687 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
5688 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
5689 EVT PtrVT = getPointerTy();
5690 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5692 // Store the input value into Value#0 of the stack slot.
5693 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
5694 Op.getOperand(0), FIdx, MachinePointerInfo(),
5697 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
5698 false, false, false, 0);
5701 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
5703 if (Op.getValueType() == MVT::v4i32) {
5704 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5706 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
5707 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
5709 SDValue RHSSwap = // = vrlw RHS, 16
5710 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
5712 // Shrinkify inputs to v8i16.
5713 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
5714 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
5715 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
5717 // Low parts multiplied together, generating 32-bit results (we ignore the
5719 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
5720 LHS, RHS, DAG, dl, MVT::v4i32);
5722 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
5723 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
5724 // Shift the high parts up 16 bits.
5725 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
5727 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
5728 } else if (Op.getValueType() == MVT::v8i16) {
5729 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5731 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
5733 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
5734 LHS, RHS, Zero, DAG, dl);
5735 } else if (Op.getValueType() == MVT::v16i8) {
5736 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5738 // Multiply the even 8-bit parts, producing 16-bit sums.
5739 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
5740 LHS, RHS, DAG, dl, MVT::v8i16);
5741 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
5743 // Multiply the odd 8-bit parts, producing 16-bit sums.
5744 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
5745 LHS, RHS, DAG, dl, MVT::v8i16);
5746 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
5748 // Merge the results together.
5750 for (unsigned i = 0; i != 8; ++i) {
5752 Ops[i*2+1] = 2*i+1+16;
5754 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
5756 llvm_unreachable("Unknown mul to lower!");
5760 /// LowerOperation - Provide custom lowering hooks for some operations.
5762 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
5763 switch (Op.getOpcode()) {
5764 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
5765 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
5766 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
5767 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
5768 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
5769 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
5770 case ISD::SETCC: return LowerSETCC(Op, DAG);
5771 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
5772 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
5774 return LowerVASTART(Op, DAG, PPCSubTarget);
5777 return LowerVAARG(Op, DAG, PPCSubTarget);
5780 return LowerVACOPY(Op, DAG, PPCSubTarget);
5782 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
5783 case ISD::DYNAMIC_STACKALLOC:
5784 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
5786 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
5787 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
5789 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
5790 case ISD::FP_TO_UINT:
5791 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
5793 case ISD::UINT_TO_FP:
5794 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
5795 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
5797 // Lower 64-bit shifts.
5798 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
5799 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
5800 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
5802 // Vector-related lowering.
5803 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
5804 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
5805 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
5806 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
5807 case ISD::MUL: return LowerMUL(Op, DAG);
5809 // For counter-based loop handling.
5810 case ISD::INTRINSIC_W_CHAIN: return SDValue();
5812 // Frame & Return address.
5813 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
5814 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
5818 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
5819 SmallVectorImpl<SDValue>&Results,
5820 SelectionDAG &DAG) const {
5821 const TargetMachine &TM = getTargetMachine();
5823 switch (N->getOpcode()) {
5825 llvm_unreachable("Do not know how to custom type legalize this operation!");
5826 case ISD::INTRINSIC_W_CHAIN: {
5827 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
5828 Intrinsic::ppc_is_decremented_ctr_nonzero)
5831 assert(N->getValueType(0) == MVT::i1 &&
5832 "Unexpected result type for CTR decrement intrinsic");
5833 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
5834 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
5835 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
5838 Results.push_back(NewInt);
5839 Results.push_back(NewInt.getValue(1));
5843 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
5844 || TM.getSubtarget<PPCSubtarget>().isPPC64())
5847 EVT VT = N->getValueType(0);
5849 if (VT == MVT::i64) {
5850 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
5852 Results.push_back(NewNode);
5853 Results.push_back(NewNode.getValue(1));
5857 case ISD::FP_ROUND_INREG: {
5858 assert(N->getValueType(0) == MVT::ppcf128);
5859 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
5860 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5861 MVT::f64, N->getOperand(0),
5862 DAG.getIntPtrConstant(0));
5863 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
5864 MVT::f64, N->getOperand(0),
5865 DAG.getIntPtrConstant(1));
5867 // Add the two halves of the long double in round-to-zero mode.
5868 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
5870 // We know the low half is about to be thrown away, so just use something
5872 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
5876 case ISD::FP_TO_SINT:
5877 // LowerFP_TO_INT() can only handle f32 and f64.
5878 if (N->getOperand(0).getValueType() == MVT::ppcf128)
5880 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
5886 //===----------------------------------------------------------------------===//
5887 // Other Lowering Code
5888 //===----------------------------------------------------------------------===//
5891 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
5892 bool is64bit, unsigned BinOpcode) const {
5893 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5894 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5896 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5897 MachineFunction *F = BB->getParent();
5898 MachineFunction::iterator It = BB;
5901 unsigned dest = MI->getOperand(0).getReg();
5902 unsigned ptrA = MI->getOperand(1).getReg();
5903 unsigned ptrB = MI->getOperand(2).getReg();
5904 unsigned incr = MI->getOperand(3).getReg();
5905 DebugLoc dl = MI->getDebugLoc();
5907 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5908 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5909 F->insert(It, loopMBB);
5910 F->insert(It, exitMBB);
5911 exitMBB->splice(exitMBB->begin(), BB,
5912 llvm::next(MachineBasicBlock::iterator(MI)),
5914 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5916 MachineRegisterInfo &RegInfo = F->getRegInfo();
5917 unsigned TmpReg = (!BinOpcode) ? incr :
5918 RegInfo.createVirtualRegister(
5919 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5920 (const TargetRegisterClass *) &PPC::GPRCRegClass);
5924 // fallthrough --> loopMBB
5925 BB->addSuccessor(loopMBB);
5928 // l[wd]arx dest, ptr
5929 // add r0, dest, incr
5930 // st[wd]cx. r0, ptr
5932 // fallthrough --> exitMBB
5934 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5935 .addReg(ptrA).addReg(ptrB);
5937 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
5938 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5939 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
5940 BuildMI(BB, dl, TII->get(PPC::BCC))
5941 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
5942 BB->addSuccessor(loopMBB);
5943 BB->addSuccessor(exitMBB);
5952 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
5953 MachineBasicBlock *BB,
5954 bool is8bit, // operation
5955 unsigned BinOpcode) const {
5956 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
5957 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
5958 // In 64 bit mode we have to use 64 bits for addresses, even though the
5959 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
5960 // registers without caring whether they're 32 or 64, but here we're
5961 // doing actual arithmetic on the addresses.
5962 bool is64bit = PPCSubTarget.isPPC64();
5963 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
5965 const BasicBlock *LLVM_BB = BB->getBasicBlock();
5966 MachineFunction *F = BB->getParent();
5967 MachineFunction::iterator It = BB;
5970 unsigned dest = MI->getOperand(0).getReg();
5971 unsigned ptrA = MI->getOperand(1).getReg();
5972 unsigned ptrB = MI->getOperand(2).getReg();
5973 unsigned incr = MI->getOperand(3).getReg();
5974 DebugLoc dl = MI->getDebugLoc();
5976 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
5977 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5978 F->insert(It, loopMBB);
5979 F->insert(It, exitMBB);
5980 exitMBB->splice(exitMBB->begin(), BB,
5981 llvm::next(MachineBasicBlock::iterator(MI)),
5983 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5985 MachineRegisterInfo &RegInfo = F->getRegInfo();
5986 const TargetRegisterClass *RC =
5987 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5988 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5989 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5990 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5991 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5992 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
5993 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5994 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5995 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5996 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5997 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
5998 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5999 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6001 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6005 // fallthrough --> loopMBB
6006 BB->addSuccessor(loopMBB);
6008 // The 4-byte load must be aligned, while a char or short may be
6009 // anywhere in the word. Hence all this nasty bookkeeping code.
6010 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6011 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6012 // xori shift, shift1, 24 [16]
6013 // rlwinm ptr, ptr1, 0, 0, 29
6014 // slw incr2, incr, shift
6015 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6016 // slw mask, mask2, shift
6018 // lwarx tmpDest, ptr
6019 // add tmp, tmpDest, incr2
6020 // andc tmp2, tmpDest, mask
6021 // and tmp3, tmp, mask
6022 // or tmp4, tmp3, tmp2
6025 // fallthrough --> exitMBB
6026 // srw dest, tmpDest, shift
6027 if (ptrA != ZeroReg) {
6028 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6029 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6030 .addReg(ptrA).addReg(ptrB);
6034 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6035 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6036 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6037 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6039 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6040 .addReg(Ptr1Reg).addImm(0).addImm(61);
6042 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6043 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6044 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6045 .addReg(incr).addReg(ShiftReg);
6047 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6049 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6050 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6052 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6053 .addReg(Mask2Reg).addReg(ShiftReg);
6056 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6057 .addReg(ZeroReg).addReg(PtrReg);
6059 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6060 .addReg(Incr2Reg).addReg(TmpDestReg);
6061 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6062 .addReg(TmpDestReg).addReg(MaskReg);
6063 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6064 .addReg(TmpReg).addReg(MaskReg);
6065 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6066 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6067 BuildMI(BB, dl, TII->get(PPC::STWCX))
6068 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6069 BuildMI(BB, dl, TII->get(PPC::BCC))
6070 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6071 BB->addSuccessor(loopMBB);
6072 BB->addSuccessor(exitMBB);
6077 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6082 llvm::MachineBasicBlock*
6083 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6084 MachineBasicBlock *MBB) const {
6085 DebugLoc DL = MI->getDebugLoc();
6086 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6088 MachineFunction *MF = MBB->getParent();
6089 MachineRegisterInfo &MRI = MF->getRegInfo();
6091 const BasicBlock *BB = MBB->getBasicBlock();
6092 MachineFunction::iterator I = MBB;
6096 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6097 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6099 unsigned DstReg = MI->getOperand(0).getReg();
6100 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6101 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6102 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6103 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6105 MVT PVT = getPointerTy();
6106 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6107 "Invalid Pointer Size!");
6108 // For v = setjmp(buf), we generate
6111 // SjLjSetup mainMBB
6117 // buf[LabelOffset] = LR
6121 // v = phi(main, restore)
6124 MachineBasicBlock *thisMBB = MBB;
6125 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6126 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6127 MF->insert(I, mainMBB);
6128 MF->insert(I, sinkMBB);
6130 MachineInstrBuilder MIB;
6132 // Transfer the remainder of BB and its successor edges to sinkMBB.
6133 sinkMBB->splice(sinkMBB->begin(), MBB,
6134 llvm::next(MachineBasicBlock::iterator(MI)), MBB->end());
6135 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6137 // Note that the structure of the jmp_buf used here is not compatible
6138 // with that used by libc, and is not designed to be. Specifically, it
6139 // stores only those 'reserved' registers that LLVM does not otherwise
6140 // understand how to spill. Also, by convention, by the time this
6141 // intrinsic is called, Clang has already stored the frame address in the
6142 // first slot of the buffer and stack address in the third. Following the
6143 // X86 target code, we'll store the jump address in the second slot. We also
6144 // need to save the TOC pointer (R2) to handle jumps between shared
6145 // libraries, and that will be stored in the fourth slot. The thread
6146 // identifier (R13) is not affected.
6149 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6150 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6151 const int64_t BPOffset = 4 * PVT.getStoreSize();
6153 // Prepare IP either in reg.
6154 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6155 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6156 unsigned BufReg = MI->getOperand(1).getReg();
6158 if (PPCSubTarget.isPPC64() && PPCSubTarget.isSVR4ABI()) {
6159 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6163 MIB.setMemRefs(MMOBegin, MMOEnd);
6166 // Naked functions never have a base pointer, and so we use r1. For all
6167 // other functions, this decision must be delayed until during PEI.
6169 if (MF->getFunction()->getAttributes().hasAttribute(
6170 AttributeSet::FunctionIndex, Attribute::Naked))
6171 BaseReg = PPCSubTarget.isPPC64() ? PPC::X1 : PPC::R1;
6173 BaseReg = PPCSubTarget.isPPC64() ? PPC::BP8 : PPC::BP;
6175 MIB = BuildMI(*thisMBB, MI, DL,
6176 TII->get(PPCSubTarget.isPPC64() ? PPC::STD : PPC::STW))
6180 MIB.setMemRefs(MMOBegin, MMOEnd);
6183 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6184 const PPCRegisterInfo *TRI =
6185 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6186 MIB.addRegMask(TRI->getNoPreservedMask());
6188 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6190 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6192 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6194 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6195 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6199 MIB = BuildMI(mainMBB, DL,
6200 TII->get(PPCSubTarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6203 if (PPCSubTarget.isPPC64()) {
6204 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6206 .addImm(LabelOffset)
6209 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6211 .addImm(LabelOffset)
6215 MIB.setMemRefs(MMOBegin, MMOEnd);
6217 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6218 mainMBB->addSuccessor(sinkMBB);
6221 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6222 TII->get(PPC::PHI), DstReg)
6223 .addReg(mainDstReg).addMBB(mainMBB)
6224 .addReg(restoreDstReg).addMBB(thisMBB);
6226 MI->eraseFromParent();
6231 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6232 MachineBasicBlock *MBB) const {
6233 DebugLoc DL = MI->getDebugLoc();
6234 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6236 MachineFunction *MF = MBB->getParent();
6237 MachineRegisterInfo &MRI = MF->getRegInfo();
6240 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6241 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6243 MVT PVT = getPointerTy();
6244 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6245 "Invalid Pointer Size!");
6247 const TargetRegisterClass *RC =
6248 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6249 unsigned Tmp = MRI.createVirtualRegister(RC);
6250 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6251 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6252 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6253 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6255 MachineInstrBuilder MIB;
6257 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6258 const int64_t SPOffset = 2 * PVT.getStoreSize();
6259 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6260 const int64_t BPOffset = 4 * PVT.getStoreSize();
6262 unsigned BufReg = MI->getOperand(0).getReg();
6264 // Reload FP (the jumped-to function may not have had a
6265 // frame pointer, and if so, then its r31 will be restored
6267 if (PVT == MVT::i64) {
6268 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6272 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6276 MIB.setMemRefs(MMOBegin, MMOEnd);
6279 if (PVT == MVT::i64) {
6280 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6281 .addImm(LabelOffset)
6284 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6285 .addImm(LabelOffset)
6288 MIB.setMemRefs(MMOBegin, MMOEnd);
6291 if (PVT == MVT::i64) {
6292 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6296 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6300 MIB.setMemRefs(MMOBegin, MMOEnd);
6303 if (PVT == MVT::i64) {
6304 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6308 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6312 MIB.setMemRefs(MMOBegin, MMOEnd);
6315 if (PVT == MVT::i64 && PPCSubTarget.isSVR4ABI()) {
6316 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6320 MIB.setMemRefs(MMOBegin, MMOEnd);
6324 BuildMI(*MBB, MI, DL,
6325 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6326 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6328 MI->eraseFromParent();
6333 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6334 MachineBasicBlock *BB) const {
6335 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6336 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6337 return emitEHSjLjSetJmp(MI, BB);
6338 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6339 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6340 return emitEHSjLjLongJmp(MI, BB);
6343 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6345 // To "insert" these instructions we actually have to insert their
6346 // control-flow patterns.
6347 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6348 MachineFunction::iterator It = BB;
6351 MachineFunction *F = BB->getParent();
6353 if (PPCSubTarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6354 MI->getOpcode() == PPC::SELECT_CC_I8)) {
6355 SmallVector<MachineOperand, 2> Cond;
6356 Cond.push_back(MI->getOperand(4));
6357 Cond.push_back(MI->getOperand(1));
6359 DebugLoc dl = MI->getDebugLoc();
6360 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6361 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6362 Cond, MI->getOperand(2).getReg(),
6363 MI->getOperand(3).getReg());
6364 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6365 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6366 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6367 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6368 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
6371 // The incoming instruction knows the destination vreg to set, the
6372 // condition code register to branch on, the true/false values to
6373 // select between, and a branch opcode to use.
6378 // cmpTY ccX, r1, r2
6380 // fallthrough --> copy0MBB
6381 MachineBasicBlock *thisMBB = BB;
6382 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6383 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6384 unsigned SelectPred = MI->getOperand(4).getImm();
6385 DebugLoc dl = MI->getDebugLoc();
6386 F->insert(It, copy0MBB);
6387 F->insert(It, sinkMBB);
6389 // Transfer the remainder of BB and its successor edges to sinkMBB.
6390 sinkMBB->splice(sinkMBB->begin(), BB,
6391 llvm::next(MachineBasicBlock::iterator(MI)),
6393 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6395 // Next, add the true and fallthrough blocks as its successors.
6396 BB->addSuccessor(copy0MBB);
6397 BB->addSuccessor(sinkMBB);
6399 BuildMI(BB, dl, TII->get(PPC::BCC))
6400 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6403 // %FalseValue = ...
6404 // # fallthrough to sinkMBB
6407 // Update machine-CFG edges
6408 BB->addSuccessor(sinkMBB);
6411 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6414 BuildMI(*BB, BB->begin(), dl,
6415 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6416 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6417 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6419 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6420 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6421 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6422 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6423 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6424 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6425 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6426 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6428 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6429 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6430 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6431 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6432 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6433 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6434 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6435 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6437 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6438 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6439 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6440 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6441 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6442 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6443 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6444 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6446 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6447 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6448 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6449 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6450 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6451 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6452 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6453 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6455 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6456 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6457 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6458 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6459 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6460 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6461 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6462 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6464 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6465 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6466 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6467 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6468 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6469 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6470 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6471 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6473 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6474 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6475 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6476 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6477 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6478 BB = EmitAtomicBinary(MI, BB, false, 0);
6479 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6480 BB = EmitAtomicBinary(MI, BB, true, 0);
6482 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6483 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6484 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6486 unsigned dest = MI->getOperand(0).getReg();
6487 unsigned ptrA = MI->getOperand(1).getReg();
6488 unsigned ptrB = MI->getOperand(2).getReg();
6489 unsigned oldval = MI->getOperand(3).getReg();
6490 unsigned newval = MI->getOperand(4).getReg();
6491 DebugLoc dl = MI->getDebugLoc();
6493 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6494 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6495 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6496 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6497 F->insert(It, loop1MBB);
6498 F->insert(It, loop2MBB);
6499 F->insert(It, midMBB);
6500 F->insert(It, exitMBB);
6501 exitMBB->splice(exitMBB->begin(), BB,
6502 llvm::next(MachineBasicBlock::iterator(MI)),
6504 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6508 // fallthrough --> loopMBB
6509 BB->addSuccessor(loop1MBB);
6512 // l[wd]arx dest, ptr
6513 // cmp[wd] dest, oldval
6516 // st[wd]cx. newval, ptr
6520 // st[wd]cx. dest, ptr
6523 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6524 .addReg(ptrA).addReg(ptrB);
6525 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6526 .addReg(oldval).addReg(dest);
6527 BuildMI(BB, dl, TII->get(PPC::BCC))
6528 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6529 BB->addSuccessor(loop2MBB);
6530 BB->addSuccessor(midMBB);
6533 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6534 .addReg(newval).addReg(ptrA).addReg(ptrB);
6535 BuildMI(BB, dl, TII->get(PPC::BCC))
6536 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6537 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6538 BB->addSuccessor(loop1MBB);
6539 BB->addSuccessor(exitMBB);
6542 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6543 .addReg(dest).addReg(ptrA).addReg(ptrB);
6544 BB->addSuccessor(exitMBB);
6549 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6550 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6551 // We must use 64-bit registers for addresses when targeting 64-bit,
6552 // since we're actually doing arithmetic on them. Other registers
6554 bool is64bit = PPCSubTarget.isPPC64();
6555 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6557 unsigned dest = MI->getOperand(0).getReg();
6558 unsigned ptrA = MI->getOperand(1).getReg();
6559 unsigned ptrB = MI->getOperand(2).getReg();
6560 unsigned oldval = MI->getOperand(3).getReg();
6561 unsigned newval = MI->getOperand(4).getReg();
6562 DebugLoc dl = MI->getDebugLoc();
6564 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6565 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6566 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6567 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6568 F->insert(It, loop1MBB);
6569 F->insert(It, loop2MBB);
6570 F->insert(It, midMBB);
6571 F->insert(It, exitMBB);
6572 exitMBB->splice(exitMBB->begin(), BB,
6573 llvm::next(MachineBasicBlock::iterator(MI)),
6575 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6577 MachineRegisterInfo &RegInfo = F->getRegInfo();
6578 const TargetRegisterClass *RC =
6579 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6580 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6581 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6582 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6583 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6584 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6585 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6586 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6587 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6588 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6589 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6590 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6591 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6592 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6593 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6595 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6596 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6599 // fallthrough --> loopMBB
6600 BB->addSuccessor(loop1MBB);
6602 // The 4-byte load must be aligned, while a char or short may be
6603 // anywhere in the word. Hence all this nasty bookkeeping code.
6604 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6605 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6606 // xori shift, shift1, 24 [16]
6607 // rlwinm ptr, ptr1, 0, 0, 29
6608 // slw newval2, newval, shift
6609 // slw oldval2, oldval,shift
6610 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6611 // slw mask, mask2, shift
6612 // and newval3, newval2, mask
6613 // and oldval3, oldval2, mask
6615 // lwarx tmpDest, ptr
6616 // and tmp, tmpDest, mask
6617 // cmpw tmp, oldval3
6620 // andc tmp2, tmpDest, mask
6621 // or tmp4, tmp2, newval3
6626 // stwcx. tmpDest, ptr
6628 // srw dest, tmpDest, shift
6629 if (ptrA != ZeroReg) {
6630 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6631 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6632 .addReg(ptrA).addReg(ptrB);
6636 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6637 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6638 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6639 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6641 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6642 .addReg(Ptr1Reg).addImm(0).addImm(61);
6644 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6645 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6646 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
6647 .addReg(newval).addReg(ShiftReg);
6648 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
6649 .addReg(oldval).addReg(ShiftReg);
6651 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6653 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6654 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
6655 .addReg(Mask3Reg).addImm(65535);
6657 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6658 .addReg(Mask2Reg).addReg(ShiftReg);
6659 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
6660 .addReg(NewVal2Reg).addReg(MaskReg);
6661 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
6662 .addReg(OldVal2Reg).addReg(MaskReg);
6665 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6666 .addReg(ZeroReg).addReg(PtrReg);
6667 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
6668 .addReg(TmpDestReg).addReg(MaskReg);
6669 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
6670 .addReg(TmpReg).addReg(OldVal3Reg);
6671 BuildMI(BB, dl, TII->get(PPC::BCC))
6672 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6673 BB->addSuccessor(loop2MBB);
6674 BB->addSuccessor(midMBB);
6677 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
6678 .addReg(TmpDestReg).addReg(MaskReg);
6679 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
6680 .addReg(Tmp2Reg).addReg(NewVal3Reg);
6681 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
6682 .addReg(ZeroReg).addReg(PtrReg);
6683 BuildMI(BB, dl, TII->get(PPC::BCC))
6684 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6685 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6686 BB->addSuccessor(loop1MBB);
6687 BB->addSuccessor(exitMBB);
6690 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
6691 .addReg(ZeroReg).addReg(PtrReg);
6692 BB->addSuccessor(exitMBB);
6697 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
6699 } else if (MI->getOpcode() == PPC::FADDrtz) {
6700 // This pseudo performs an FADD with rounding mode temporarily forced
6701 // to round-to-zero. We emit this via custom inserter since the FPSCR
6702 // is not modeled at the SelectionDAG level.
6703 unsigned Dest = MI->getOperand(0).getReg();
6704 unsigned Src1 = MI->getOperand(1).getReg();
6705 unsigned Src2 = MI->getOperand(2).getReg();
6706 DebugLoc dl = MI->getDebugLoc();
6708 MachineRegisterInfo &RegInfo = F->getRegInfo();
6709 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
6711 // Save FPSCR value.
6712 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
6714 // Set rounding mode to round-to-zero.
6715 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
6716 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
6718 // Perform addition.
6719 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
6721 // Restore FPSCR value.
6722 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
6724 llvm_unreachable("Unexpected instr type to insert");
6727 MI->eraseFromParent(); // The pseudo instruction is gone now.
6731 //===----------------------------------------------------------------------===//
6732 // Target Optimization Hooks
6733 //===----------------------------------------------------------------------===//
6735 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
6736 DAGCombinerInfo &DCI) const {
6737 if (DCI.isAfterLegalizeVectorOps())
6740 EVT VT = Op.getValueType();
6742 if ((VT == MVT::f32 && PPCSubTarget.hasFRES()) ||
6743 (VT == MVT::f64 && PPCSubTarget.hasFRE()) ||
6744 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6746 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6747 // For the reciprocal, we need to find the zero of the function:
6748 // F(X) = A X - 1 [which has a zero at X = 1/A]
6750 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
6751 // does not require additional intermediate precision]
6753 // Convergence is quadratic, so we essentially double the number of digits
6754 // correct after every iteration. The minimum architected relative
6755 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6756 // 23 digits and double has 52 digits.
6757 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6758 if (VT.getScalarType() == MVT::f64)
6761 SelectionDAG &DAG = DCI.DAG;
6765 DAG.getConstantFP(1.0, VT.getScalarType());
6766 if (VT.isVector()) {
6767 assert(VT.getVectorNumElements() == 4 &&
6768 "Unknown vector type");
6769 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6770 FPOne, FPOne, FPOne, FPOne);
6773 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
6774 DCI.AddToWorklist(Est.getNode());
6776 // Newton iterations: Est = Est + Est (1 - Arg * Est)
6777 for (int i = 0; i < Iterations; ++i) {
6778 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
6779 DCI.AddToWorklist(NewEst.getNode());
6781 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
6782 DCI.AddToWorklist(NewEst.getNode());
6784 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6785 DCI.AddToWorklist(NewEst.getNode());
6787 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
6788 DCI.AddToWorklist(Est.getNode());
6797 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
6798 DAGCombinerInfo &DCI) const {
6799 if (DCI.isAfterLegalizeVectorOps())
6802 EVT VT = Op.getValueType();
6804 if ((VT == MVT::f32 && PPCSubTarget.hasFRSQRTES()) ||
6805 (VT == MVT::f64 && PPCSubTarget.hasFRSQRTE()) ||
6806 (VT == MVT::v4f32 && PPCSubTarget.hasAltivec())) {
6808 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
6809 // For the reciprocal sqrt, we need to find the zero of the function:
6810 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
6812 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
6813 // As a result, we precompute A/2 prior to the iteration loop.
6815 // Convergence is quadratic, so we essentially double the number of digits
6816 // correct after every iteration. The minimum architected relative
6817 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
6818 // 23 digits and double has 52 digits.
6819 int Iterations = PPCSubTarget.hasRecipPrec() ? 1 : 3;
6820 if (VT.getScalarType() == MVT::f64)
6823 SelectionDAG &DAG = DCI.DAG;
6826 SDValue FPThreeHalves =
6827 DAG.getConstantFP(1.5, VT.getScalarType());
6828 if (VT.isVector()) {
6829 assert(VT.getVectorNumElements() == 4 &&
6830 "Unknown vector type");
6831 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
6832 FPThreeHalves, FPThreeHalves,
6833 FPThreeHalves, FPThreeHalves);
6836 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
6837 DCI.AddToWorklist(Est.getNode());
6839 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
6840 // this entire sequence requires only one FP constant.
6841 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
6842 DCI.AddToWorklist(HalfArg.getNode());
6844 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
6845 DCI.AddToWorklist(HalfArg.getNode());
6847 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
6848 for (int i = 0; i < Iterations; ++i) {
6849 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
6850 DCI.AddToWorklist(NewEst.getNode());
6852 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
6853 DCI.AddToWorklist(NewEst.getNode());
6855 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
6856 DCI.AddToWorklist(NewEst.getNode());
6858 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
6859 DCI.AddToWorklist(Est.getNode());
6868 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
6869 // not enforce equality of the chain operands.
6870 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
6871 unsigned Bytes, int Dist,
6872 SelectionDAG &DAG) {
6873 EVT VT = LS->getMemoryVT();
6874 if (VT.getSizeInBits() / 8 != Bytes)
6877 SDValue Loc = LS->getBasePtr();
6878 SDValue BaseLoc = Base->getBasePtr();
6879 if (Loc.getOpcode() == ISD::FrameIndex) {
6880 if (BaseLoc.getOpcode() != ISD::FrameIndex)
6882 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
6883 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
6884 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
6885 int FS = MFI->getObjectSize(FI);
6886 int BFS = MFI->getObjectSize(BFI);
6887 if (FS != BFS || FS != (int)Bytes) return false;
6888 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
6892 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
6893 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
6896 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
6897 const GlobalValue *GV1 = NULL;
6898 const GlobalValue *GV2 = NULL;
6899 int64_t Offset1 = 0;
6900 int64_t Offset2 = 0;
6901 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
6902 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
6903 if (isGA1 && isGA2 && GV1 == GV2)
6904 return Offset1 == (Offset2 + Dist*Bytes);
6908 // Return true is there is a nearyby consecutive load to the one provided
6909 // (regardless of alignment). We search up and down the chain, looking though
6910 // token factors and other loads (but nothing else). As a result, a true
6911 // results indicates that it is safe to create a new consecutive load adjacent
6912 // to the load provided.
6913 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
6914 SDValue Chain = LD->getChain();
6915 EVT VT = LD->getMemoryVT();
6917 SmallSet<SDNode *, 16> LoadRoots;
6918 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
6919 SmallSet<SDNode *, 16> Visited;
6921 // First, search up the chain, branching to follow all token-factor operands.
6922 // If we find a consecutive load, then we're done, otherwise, record all
6923 // nodes just above the top-level loads and token factors.
6924 while (!Queue.empty()) {
6925 SDNode *ChainNext = Queue.pop_back_val();
6926 if (!Visited.insert(ChainNext))
6929 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
6930 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6933 if (!Visited.count(ChainLD->getChain().getNode()))
6934 Queue.push_back(ChainLD->getChain().getNode());
6935 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
6936 for (SDNode::op_iterator O = ChainNext->op_begin(),
6937 OE = ChainNext->op_end(); O != OE; ++O)
6938 if (!Visited.count(O->getNode()))
6939 Queue.push_back(O->getNode());
6941 LoadRoots.insert(ChainNext);
6944 // Second, search down the chain, starting from the top-level nodes recorded
6945 // in the first phase. These top-level nodes are the nodes just above all
6946 // loads and token factors. Starting with their uses, recursively look though
6947 // all loads (just the chain uses) and token factors to find a consecutive
6952 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
6953 IE = LoadRoots.end(); I != IE; ++I) {
6954 Queue.push_back(*I);
6956 while (!Queue.empty()) {
6957 SDNode *LoadRoot = Queue.pop_back_val();
6958 if (!Visited.insert(LoadRoot))
6961 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
6962 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
6965 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
6966 UE = LoadRoot->use_end(); UI != UE; ++UI)
6967 if (((isa<LoadSDNode>(*UI) &&
6968 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
6969 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
6970 Queue.push_back(*UI);
6977 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
6978 DAGCombinerInfo &DCI) const {
6979 const TargetMachine &TM = getTargetMachine();
6980 SelectionDAG &DAG = DCI.DAG;
6982 switch (N->getOpcode()) {
6985 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6986 if (C->isNullValue()) // 0 << V -> 0.
6987 return N->getOperand(0);
6991 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6992 if (C->isNullValue()) // 0 >>u V -> 0.
6993 return N->getOperand(0);
6997 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
6998 if (C->isNullValue() || // 0 >>s V -> 0.
6999 C->isAllOnesValue()) // -1 >>s V -> -1.
7000 return N->getOperand(0);
7004 assert(TM.Options.UnsafeFPMath &&
7005 "Reciprocal estimates require UnsafeFPMath");
7007 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7009 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7010 if (RV.getNode() != 0) {
7011 DCI.AddToWorklist(RV.getNode());
7012 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7013 N->getOperand(0), RV);
7015 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7016 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7018 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7020 if (RV.getNode() != 0) {
7021 DCI.AddToWorklist(RV.getNode());
7022 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7023 N->getValueType(0), RV);
7024 DCI.AddToWorklist(RV.getNode());
7025 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7026 N->getOperand(0), RV);
7028 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7029 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7031 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7033 if (RV.getNode() != 0) {
7034 DCI.AddToWorklist(RV.getNode());
7035 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7036 N->getValueType(0), RV,
7037 N->getOperand(1).getOperand(1));
7038 DCI.AddToWorklist(RV.getNode());
7039 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7040 N->getOperand(0), RV);
7044 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
7045 if (RV.getNode() != 0) {
7046 DCI.AddToWorklist(RV.getNode());
7047 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7048 N->getOperand(0), RV);
7054 assert(TM.Options.UnsafeFPMath &&
7055 "Reciprocal estimates require UnsafeFPMath");
7057 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
7059 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
7060 if (RV.getNode() != 0) {
7061 DCI.AddToWorklist(RV.getNode());
7062 RV = DAGCombineFastRecip(RV, DCI);
7063 if (RV.getNode() != 0) {
7064 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
7065 // this case and force the answer to 0.
7067 EVT VT = RV.getValueType();
7069 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
7070 if (VT.isVector()) {
7071 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
7072 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
7076 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
7077 N->getOperand(0), Zero, ISD::SETEQ);
7078 DCI.AddToWorklist(ZeroCmp.getNode());
7079 DCI.AddToWorklist(RV.getNode());
7081 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
7089 case ISD::SINT_TO_FP:
7090 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
7091 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
7092 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
7093 // We allow the src/dst to be either f32/f64, but the intermediate
7094 // type must be i64.
7095 if (N->getOperand(0).getValueType() == MVT::i64 &&
7096 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
7097 SDValue Val = N->getOperand(0).getOperand(0);
7098 if (Val.getValueType() == MVT::f32) {
7099 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7100 DCI.AddToWorklist(Val.getNode());
7103 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
7104 DCI.AddToWorklist(Val.getNode());
7105 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
7106 DCI.AddToWorklist(Val.getNode());
7107 if (N->getValueType(0) == MVT::f32) {
7108 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
7109 DAG.getIntPtrConstant(0));
7110 DCI.AddToWorklist(Val.getNode());
7113 } else if (N->getOperand(0).getValueType() == MVT::i32) {
7114 // If the intermediate type is i32, we can avoid the load/store here
7121 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
7122 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
7123 !cast<StoreSDNode>(N)->isTruncatingStore() &&
7124 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
7125 N->getOperand(1).getValueType() == MVT::i32 &&
7126 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
7127 SDValue Val = N->getOperand(1).getOperand(0);
7128 if (Val.getValueType() == MVT::f32) {
7129 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
7130 DCI.AddToWorklist(Val.getNode());
7132 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
7133 DCI.AddToWorklist(Val.getNode());
7136 N->getOperand(0), Val, N->getOperand(2),
7137 DAG.getValueType(N->getOperand(1).getValueType())
7140 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
7141 DAG.getVTList(MVT::Other), Ops, array_lengthof(Ops),
7142 cast<StoreSDNode>(N)->getMemoryVT(),
7143 cast<StoreSDNode>(N)->getMemOperand());
7144 DCI.AddToWorklist(Val.getNode());
7148 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
7149 if (cast<StoreSDNode>(N)->isUnindexed() &&
7150 N->getOperand(1).getOpcode() == ISD::BSWAP &&
7151 N->getOperand(1).getNode()->hasOneUse() &&
7152 (N->getOperand(1).getValueType() == MVT::i32 ||
7153 N->getOperand(1).getValueType() == MVT::i16 ||
7154 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7155 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7156 N->getOperand(1).getValueType() == MVT::i64))) {
7157 SDValue BSwapOp = N->getOperand(1).getOperand(0);
7158 // Do an any-extend to 32-bits if this is a half-word input.
7159 if (BSwapOp.getValueType() == MVT::i16)
7160 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
7163 N->getOperand(0), BSwapOp, N->getOperand(2),
7164 DAG.getValueType(N->getOperand(1).getValueType())
7167 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
7168 Ops, array_lengthof(Ops),
7169 cast<StoreSDNode>(N)->getMemoryVT(),
7170 cast<StoreSDNode>(N)->getMemOperand());
7174 LoadSDNode *LD = cast<LoadSDNode>(N);
7175 EVT VT = LD->getValueType(0);
7176 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
7177 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
7178 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
7179 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
7180 DCI.getDAGCombineLevel() == AfterLegalizeTypes &&
7181 LD->getAlignment() < ABIAlignment) {
7182 // This is a type-legal unaligned Altivec load.
7183 SDValue Chain = LD->getChain();
7184 SDValue Ptr = LD->getBasePtr();
7186 // This implements the loading of unaligned vectors as described in
7187 // the venerable Apple Velocity Engine overview. Specifically:
7188 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
7189 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
7191 // The general idea is to expand a sequence of one or more unaligned
7192 // loads into a alignment-based permutation-control instruction (lvsl),
7193 // a series of regular vector loads (which always truncate their
7194 // input address to an aligned address), and a series of permutations.
7195 // The results of these permutations are the requested loaded values.
7196 // The trick is that the last "extra" load is not taken from the address
7197 // you might suspect (sizeof(vector) bytes after the last requested
7198 // load), but rather sizeof(vector) - 1 bytes after the last
7199 // requested vector. The point of this is to avoid a page fault if the
7200 // base address happend to be aligned. This works because if the base
7201 // address is aligned, then adding less than a full vector length will
7202 // cause the last vector in the sequence to be (re)loaded. Otherwise,
7203 // the next vector will be fetched as you might suspect was necessary.
7205 // We might be able to reuse the permutation generation from
7206 // a different base address offset from this one by an aligned amount.
7207 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
7208 // optimization later.
7209 SDValue PermCntl = BuildIntrinsicOp(Intrinsic::ppc_altivec_lvsl, Ptr,
7210 DAG, dl, MVT::v16i8);
7212 // Refine the alignment of the original load (a "new" load created here
7213 // which was identical to the first except for the alignment would be
7214 // merged with the existing node regardless).
7215 MachineFunction &MF = DAG.getMachineFunction();
7216 MachineMemOperand *MMO =
7217 MF.getMachineMemOperand(LD->getPointerInfo(),
7218 LD->getMemOperand()->getFlags(),
7219 LD->getMemoryVT().getStoreSize(),
7221 LD->refineAlignment(MMO);
7222 SDValue BaseLoad = SDValue(LD, 0);
7224 // Note that the value of IncOffset (which is provided to the next
7225 // load's pointer info offset value, and thus used to calculate the
7226 // alignment), and the value of IncValue (which is actually used to
7227 // increment the pointer value) are different! This is because we
7228 // require the next load to appear to be aligned, even though it
7229 // is actually offset from the base pointer by a lesser amount.
7230 int IncOffset = VT.getSizeInBits() / 8;
7231 int IncValue = IncOffset;
7233 // Walk (both up and down) the chain looking for another load at the real
7234 // (aligned) offset (the alignment of the other load does not matter in
7235 // this case). If found, then do not use the offset reduction trick, as
7236 // that will prevent the loads from being later combined (as they would
7237 // otherwise be duplicates).
7238 if (!findConsecutiveLoad(LD, DAG))
7241 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
7242 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
7245 DAG.getLoad(VT, dl, Chain, Ptr,
7246 LD->getPointerInfo().getWithOffset(IncOffset),
7247 LD->isVolatile(), LD->isNonTemporal(),
7248 LD->isInvariant(), ABIAlignment);
7250 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
7251 BaseLoad.getValue(1), ExtraLoad.getValue(1));
7253 if (BaseLoad.getValueType() != MVT::v4i32)
7254 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
7256 if (ExtraLoad.getValueType() != MVT::v4i32)
7257 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
7259 SDValue Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
7260 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
7262 if (VT != MVT::v4i32)
7263 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
7265 // Now we need to be really careful about how we update the users of the
7266 // original load. We cannot just call DCI.CombineTo (or
7267 // DAG.ReplaceAllUsesWith for that matter), because the load still has
7268 // uses created here (the permutation for example) that need to stay.
7269 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
7271 SDUse &Use = UI.getUse();
7273 // Note: BaseLoad is checked here because it might not be N, but a
7275 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
7276 User == TF.getNode() || Use.getResNo() > 1) {
7281 SDValue To = Use.getResNo() ? TF : Perm;
7284 SmallVector<SDValue, 8> Ops;
7285 for (SDNode::op_iterator O = User->op_begin(),
7286 OE = User->op_end(); O != OE; ++O) {
7293 DAG.UpdateNodeOperands(User, Ops.data(), Ops.size());
7296 return SDValue(N, 0);
7300 case ISD::INTRINSIC_WO_CHAIN:
7301 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() ==
7302 Intrinsic::ppc_altivec_lvsl &&
7303 N->getOperand(1)->getOpcode() == ISD::ADD) {
7304 SDValue Add = N->getOperand(1);
7306 if (DAG.MaskedValueIsZero(Add->getOperand(1),
7307 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
7308 Add.getValueType().getScalarType().getSizeInBits()))) {
7309 SDNode *BasePtr = Add->getOperand(0).getNode();
7310 for (SDNode::use_iterator UI = BasePtr->use_begin(),
7311 UE = BasePtr->use_end(); UI != UE; ++UI) {
7312 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7313 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
7314 Intrinsic::ppc_altivec_lvsl) {
7315 // We've found another LVSL, and this address if an aligned
7316 // multiple of that one. The results will be the same, so use the
7317 // one we've just found instead.
7319 return SDValue(*UI, 0);
7327 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
7328 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
7329 N->getOperand(0).hasOneUse() &&
7330 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
7331 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
7332 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
7333 N->getValueType(0) == MVT::i64))) {
7334 SDValue Load = N->getOperand(0);
7335 LoadSDNode *LD = cast<LoadSDNode>(Load);
7336 // Create the byte-swapping load.
7338 LD->getChain(), // Chain
7339 LD->getBasePtr(), // Ptr
7340 DAG.getValueType(N->getValueType(0)) // VT
7343 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
7344 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
7345 MVT::i64 : MVT::i32, MVT::Other),
7346 Ops, 3, LD->getMemoryVT(), LD->getMemOperand());
7348 // If this is an i16 load, insert the truncate.
7349 SDValue ResVal = BSLoad;
7350 if (N->getValueType(0) == MVT::i16)
7351 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
7353 // First, combine the bswap away. This makes the value produced by the
7355 DCI.CombineTo(N, ResVal);
7357 // Next, combine the load away, we give it a bogus result value but a real
7358 // chain result. The result value is dead because the bswap is dead.
7359 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
7361 // Return N so it doesn't get rechecked!
7362 return SDValue(N, 0);
7366 case PPCISD::VCMP: {
7367 // If a VCMPo node already exists with exactly the same operands as this
7368 // node, use its result instead of this node (VCMPo computes both a CR6 and
7369 // a normal output).
7371 if (!N->getOperand(0).hasOneUse() &&
7372 !N->getOperand(1).hasOneUse() &&
7373 !N->getOperand(2).hasOneUse()) {
7375 // Scan all of the users of the LHS, looking for VCMPo's that match.
7376 SDNode *VCMPoNode = 0;
7378 SDNode *LHSN = N->getOperand(0).getNode();
7379 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
7381 if (UI->getOpcode() == PPCISD::VCMPo &&
7382 UI->getOperand(1) == N->getOperand(1) &&
7383 UI->getOperand(2) == N->getOperand(2) &&
7384 UI->getOperand(0) == N->getOperand(0)) {
7389 // If there is no VCMPo node, or if the flag value has a single use, don't
7391 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
7394 // Look at the (necessarily single) use of the flag value. If it has a
7395 // chain, this transformation is more complex. Note that multiple things
7396 // could use the value result, which we should ignore.
7397 SDNode *FlagUser = 0;
7398 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
7399 FlagUser == 0; ++UI) {
7400 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
7402 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
7403 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
7410 // If the user is a MFOCRF instruction, we know this is safe.
7411 // Otherwise we give up for right now.
7412 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
7413 return SDValue(VCMPoNode, 0);
7418 // If this is a branch on an altivec predicate comparison, lower this so
7419 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
7420 // lowering is done pre-legalize, because the legalizer lowers the predicate
7421 // compare down to code that is difficult to reassemble.
7422 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
7423 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
7425 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
7426 // value. If so, pass-through the AND to get to the intrinsic.
7427 if (LHS.getOpcode() == ISD::AND &&
7428 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7429 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
7430 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7431 isa<ConstantSDNode>(LHS.getOperand(1)) &&
7432 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
7434 LHS = LHS.getOperand(0);
7436 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
7437 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
7438 Intrinsic::ppc_is_decremented_ctr_nonzero &&
7439 isa<ConstantSDNode>(RHS)) {
7440 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
7441 "Counter decrement comparison is not EQ or NE");
7443 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7444 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
7445 (CC == ISD::SETNE && !Val);
7447 // We now need to make the intrinsic dead (it cannot be instruction
7449 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
7450 assert(LHS.getNode()->hasOneUse() &&
7451 "Counter decrement has more than one use");
7453 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
7454 N->getOperand(0), N->getOperand(4));
7460 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
7461 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
7462 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
7463 assert(isDot && "Can't compare against a vector result!");
7465 // If this is a comparison against something other than 0/1, then we know
7466 // that the condition is never/always true.
7467 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
7468 if (Val != 0 && Val != 1) {
7469 if (CC == ISD::SETEQ) // Cond never true, remove branch.
7470 return N->getOperand(0);
7471 // Always !=, turn it into an unconditional branch.
7472 return DAG.getNode(ISD::BR, dl, MVT::Other,
7473 N->getOperand(0), N->getOperand(4));
7476 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
7478 // Create the PPCISD altivec 'dot' comparison node.
7480 LHS.getOperand(2), // LHS of compare
7481 LHS.getOperand(3), // RHS of compare
7482 DAG.getConstant(CompareOpc, MVT::i32)
7484 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
7485 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
7487 // Unpack the result based on how the target uses it.
7488 PPC::Predicate CompOpc;
7489 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
7490 default: // Can't happen, don't crash on invalid number though.
7491 case 0: // Branch on the value of the EQ bit of CR6.
7492 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
7494 case 1: // Branch on the inverted value of the EQ bit of CR6.
7495 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
7497 case 2: // Branch on the value of the LT bit of CR6.
7498 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
7500 case 3: // Branch on the inverted value of the LT bit of CR6.
7501 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
7505 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
7506 DAG.getConstant(CompOpc, MVT::i32),
7507 DAG.getRegister(PPC::CR6, MVT::i32),
7508 N->getOperand(4), CompNode.getValue(1));
7517 //===----------------------------------------------------------------------===//
7518 // Inline Assembly Support
7519 //===----------------------------------------------------------------------===//
7521 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
7524 const SelectionDAG &DAG,
7525 unsigned Depth) const {
7526 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
7527 switch (Op.getOpcode()) {
7529 case PPCISD::LBRX: {
7530 // lhbrx is known to have the top bits cleared out.
7531 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
7532 KnownZero = 0xFFFF0000;
7535 case ISD::INTRINSIC_WO_CHAIN: {
7536 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
7538 case Intrinsic::ppc_altivec_vcmpbfp_p:
7539 case Intrinsic::ppc_altivec_vcmpeqfp_p:
7540 case Intrinsic::ppc_altivec_vcmpequb_p:
7541 case Intrinsic::ppc_altivec_vcmpequh_p:
7542 case Intrinsic::ppc_altivec_vcmpequw_p:
7543 case Intrinsic::ppc_altivec_vcmpgefp_p:
7544 case Intrinsic::ppc_altivec_vcmpgtfp_p:
7545 case Intrinsic::ppc_altivec_vcmpgtsb_p:
7546 case Intrinsic::ppc_altivec_vcmpgtsh_p:
7547 case Intrinsic::ppc_altivec_vcmpgtsw_p:
7548 case Intrinsic::ppc_altivec_vcmpgtub_p:
7549 case Intrinsic::ppc_altivec_vcmpgtuh_p:
7550 case Intrinsic::ppc_altivec_vcmpgtuw_p:
7551 KnownZero = ~1U; // All bits but the low one are known to be zero.
7559 /// getConstraintType - Given a constraint, return the type of
7560 /// constraint it is for this target.
7561 PPCTargetLowering::ConstraintType
7562 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
7563 if (Constraint.size() == 1) {
7564 switch (Constraint[0]) {
7571 return C_RegisterClass;
7573 // FIXME: While Z does indicate a memory constraint, it specifically
7574 // indicates an r+r address (used in conjunction with the 'y' modifier
7575 // in the replacement string). Currently, we're forcing the base
7576 // register to be r0 in the asm printer (which is interpreted as zero)
7577 // and forming the complete address in the second register. This is
7582 return TargetLowering::getConstraintType(Constraint);
7585 /// Examine constraint type and operand type and determine a weight value.
7586 /// This object must already have been set up with the operand type
7587 /// and the current alternative constraint selected.
7588 TargetLowering::ConstraintWeight
7589 PPCTargetLowering::getSingleConstraintMatchWeight(
7590 AsmOperandInfo &info, const char *constraint) const {
7591 ConstraintWeight weight = CW_Invalid;
7592 Value *CallOperandVal = info.CallOperandVal;
7593 // If we don't have a value, we can't do a match,
7594 // but allow it at the lowest weight.
7595 if (CallOperandVal == NULL)
7597 Type *type = CallOperandVal->getType();
7598 // Look at the constraint type.
7599 switch (*constraint) {
7601 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
7604 if (type->isIntegerTy())
7605 weight = CW_Register;
7608 if (type->isFloatTy())
7609 weight = CW_Register;
7612 if (type->isDoubleTy())
7613 weight = CW_Register;
7616 if (type->isVectorTy())
7617 weight = CW_Register;
7620 weight = CW_Register;
7629 std::pair<unsigned, const TargetRegisterClass*>
7630 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
7632 if (Constraint.size() == 1) {
7633 // GCC RS6000 Constraint Letters
7634 switch (Constraint[0]) {
7636 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7637 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
7638 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
7640 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
7641 return std::make_pair(0U, &PPC::G8RCRegClass);
7642 return std::make_pair(0U, &PPC::GPRCRegClass);
7644 if (VT == MVT::f32 || VT == MVT::i32)
7645 return std::make_pair(0U, &PPC::F4RCRegClass);
7646 if (VT == MVT::f64 || VT == MVT::i64)
7647 return std::make_pair(0U, &PPC::F8RCRegClass);
7650 return std::make_pair(0U, &PPC::VRRCRegClass);
7652 return std::make_pair(0U, &PPC::CRRCRegClass);
7656 std::pair<unsigned, const TargetRegisterClass*> R =
7657 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
7659 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
7660 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
7661 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
7663 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
7664 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
7665 if (R.first && VT == MVT::i64 && PPCSubTarget.isPPC64() &&
7666 PPC::GPRCRegClass.contains(R.first)) {
7667 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
7668 return std::make_pair(TRI->getMatchingSuperReg(R.first,
7669 PPC::sub_32, &PPC::G8RCRegClass),
7670 &PPC::G8RCRegClass);
7677 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
7678 /// vector. If it is invalid, don't add anything to Ops.
7679 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
7680 std::string &Constraint,
7681 std::vector<SDValue>&Ops,
7682 SelectionDAG &DAG) const {
7683 SDValue Result(0,0);
7685 // Only support length 1 constraints.
7686 if (Constraint.length() > 1) return;
7688 char Letter = Constraint[0];
7699 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
7700 if (!CST) return; // Must be an immediate to match.
7701 unsigned Value = CST->getZExtValue();
7703 default: llvm_unreachable("Unknown constraint letter!");
7704 case 'I': // "I" is a signed 16-bit constant.
7705 if ((short)Value == (int)Value)
7706 Result = DAG.getTargetConstant(Value, Op.getValueType());
7708 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
7709 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
7710 if ((short)Value == 0)
7711 Result = DAG.getTargetConstant(Value, Op.getValueType());
7713 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
7714 if ((Value >> 16) == 0)
7715 Result = DAG.getTargetConstant(Value, Op.getValueType());
7717 case 'M': // "M" is a constant that is greater than 31.
7719 Result = DAG.getTargetConstant(Value, Op.getValueType());
7721 case 'N': // "N" is a positive constant that is an exact power of two.
7722 if ((int)Value > 0 && isPowerOf2_32(Value))
7723 Result = DAG.getTargetConstant(Value, Op.getValueType());
7725 case 'O': // "O" is the constant zero.
7727 Result = DAG.getTargetConstant(Value, Op.getValueType());
7729 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
7730 if ((short)-Value == (int)-Value)
7731 Result = DAG.getTargetConstant(Value, Op.getValueType());
7738 if (Result.getNode()) {
7739 Ops.push_back(Result);
7743 // Handle standard constraint letters.
7744 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
7747 // isLegalAddressingMode - Return true if the addressing mode represented
7748 // by AM is legal for this target, for a load/store of the specified type.
7749 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
7751 // FIXME: PPC does not allow r+i addressing modes for vectors!
7753 // PPC allows a sign-extended 16-bit immediate field.
7754 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
7757 // No global is ever allowed as a base.
7761 // PPC only support r+r,
7763 case 0: // "r+i" or just "i", depending on HasBaseReg.
7766 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
7768 // Otherwise we have r+r or r+i.
7771 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
7773 // Allow 2*r as r+r.
7776 // No other scales are supported.
7783 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
7784 SelectionDAG &DAG) const {
7785 MachineFunction &MF = DAG.getMachineFunction();
7786 MachineFrameInfo *MFI = MF.getFrameInfo();
7787 MFI->setReturnAddressIsTaken(true);
7790 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7792 // Make sure the function does not optimize away the store of the RA to
7794 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
7795 FuncInfo->setLRStoreRequired();
7796 bool isPPC64 = PPCSubTarget.isPPC64();
7797 bool isDarwinABI = PPCSubTarget.isDarwinABI();
7800 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
7803 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
7804 isPPC64? MVT::i64 : MVT::i32);
7805 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7806 DAG.getNode(ISD::ADD, dl, getPointerTy(),
7808 MachinePointerInfo(), false, false, false, 0);
7811 // Just load the return address off the stack.
7812 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
7813 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
7814 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
7817 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
7818 SelectionDAG &DAG) const {
7820 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
7822 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
7823 bool isPPC64 = PtrVT == MVT::i64;
7825 MachineFunction &MF = DAG.getMachineFunction();
7826 MachineFrameInfo *MFI = MF.getFrameInfo();
7827 MFI->setFrameAddressIsTaken(true);
7829 // Naked functions never have a frame pointer, and so we use r1. For all
7830 // other functions, this decision must be delayed until during PEI.
7832 if (MF.getFunction()->getAttributes().hasAttribute(
7833 AttributeSet::FunctionIndex, Attribute::Naked))
7834 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
7836 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
7838 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
7841 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
7842 FrameAddr, MachinePointerInfo(), false, false,
7848 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
7849 // The PowerPC target isn't yet aware of offsets.
7853 /// getOptimalMemOpType - Returns the target specific optimal type for load
7854 /// and store operations as a result of memset, memcpy, and memmove
7855 /// lowering. If DstAlign is zero that means it's safe to destination
7856 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
7857 /// means there isn't a need to check it against alignment requirement,
7858 /// probably because the source does not need to be loaded. If 'IsMemset' is
7859 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
7860 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
7861 /// source is constant so it does not need to be loaded.
7862 /// It returns EVT::Other if the type should be determined using generic
7863 /// target-independent logic.
7864 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
7865 unsigned DstAlign, unsigned SrcAlign,
7866 bool IsMemset, bool ZeroMemset,
7868 MachineFunction &MF) const {
7869 if (this->PPCSubTarget.isPPC64()) {
7876 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
7878 if (DisablePPCUnaligned)
7881 // PowerPC supports unaligned memory access for simple non-vector types.
7882 // Although accessing unaligned addresses is not as efficient as accessing
7883 // aligned addresses, it is generally more efficient than manual expansion,
7884 // and generally only traps for software emulation when crossing page
7890 if (VT.getSimpleVT().isVector())
7893 if (VT == MVT::ppcf128)
7902 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
7903 VT = VT.getScalarType();
7908 switch (VT.getSimpleVT().SimpleTy) {
7919 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
7920 if (DisableILPPref || PPCSubTarget.enableMachineScheduler())
7921 return TargetLowering::getSchedulingPreference(N);
7926 // Create a fast isel object.
7928 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
7929 const TargetLibraryInfo *LibInfo) const {
7930 return PPC::createFastISel(FuncInfo, LibInfo);