1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCTargetMachine.h"
18 #include "MCTargetDesc/PPCPredicates.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/CallingConv.h"
30 #include "llvm/Constants.h"
31 #include "llvm/Function.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
64 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
77 // arguments are at least 4/8 bytes aligned.
78 setMinStackArgumentAlignment(TM.getSubtarget<PPCSubtarget>().isPPC64() ? 8:4);
80 // Set up the register classes.
81 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
82 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
83 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
85 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
86 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
89 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
91 // PowerPC has pre-inc load and store's.
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
94 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
103 // This is used in the ppcf128->int sequence. Note it has different semantics
104 // from FP_ROUND: that rounds to nearest, this rounds to zero.
105 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
107 // PowerPC has no SREM/UREM instructions
108 setOperationAction(ISD::SREM, MVT::i32, Expand);
109 setOperationAction(ISD::UREM, MVT::i32, Expand);
110 setOperationAction(ISD::SREM, MVT::i64, Expand);
111 setOperationAction(ISD::UREM, MVT::i64, Expand);
113 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
114 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
116 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
117 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
118 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
119 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
120 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
121 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
123 // We don't support sin/cos/sqrt/fmod/pow
124 setOperationAction(ISD::FSIN , MVT::f64, Expand);
125 setOperationAction(ISD::FCOS , MVT::f64, Expand);
126 setOperationAction(ISD::FREM , MVT::f64, Expand);
127 setOperationAction(ISD::FPOW , MVT::f64, Expand);
128 setOperationAction(ISD::FMA , MVT::f64, Expand);
129 setOperationAction(ISD::FSIN , MVT::f32, Expand);
130 setOperationAction(ISD::FCOS , MVT::f32, Expand);
131 setOperationAction(ISD::FREM , MVT::f32, Expand);
132 setOperationAction(ISD::FPOW , MVT::f32, Expand);
133 setOperationAction(ISD::FMA , MVT::f32, Expand);
135 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
137 // If we're enabling GP optimizations, use hardware square root
138 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
139 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
140 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
143 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
144 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
146 // PowerPC does not have BSWAP, CTPOP or CTTZ
147 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
148 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
149 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
150 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
151 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
152 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
154 // PowerPC does not have ROTR
155 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
156 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
158 // PowerPC does not have Select
159 setOperationAction(ISD::SELECT, MVT::i32, Expand);
160 setOperationAction(ISD::SELECT, MVT::i64, Expand);
161 setOperationAction(ISD::SELECT, MVT::f32, Expand);
162 setOperationAction(ISD::SELECT, MVT::f64, Expand);
164 // PowerPC wants to turn select_cc of FP into fsel when possible.
165 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
166 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
168 // PowerPC wants to optimize integer setcc a bit
169 setOperationAction(ISD::SETCC, MVT::i32, Custom);
171 // PowerPC does not have BRCOND which requires SetCC
172 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
174 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
176 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
177 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
179 // PowerPC does not have [U|S]INT_TO_FP
180 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
181 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
183 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
184 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
185 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
186 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
188 // We cannot sextinreg(i1). Expand to shifts.
189 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
191 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
192 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
193 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
194 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
197 // We want to legalize GlobalAddress and ConstantPool nodes into the
198 // appropriate instructions to materialize the address.
199 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
200 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
201 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
202 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
203 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
204 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
205 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
206 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
207 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
208 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
211 setOperationAction(ISD::TRAP, MVT::Other, Legal);
213 // TRAMPOLINE is custom lowered.
214 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
215 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
217 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
218 setOperationAction(ISD::VASTART , MVT::Other, Custom);
220 // VAARG is custom lowered with the 32-bit SVR4 ABI.
221 if (TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
222 && !TM.getSubtarget<PPCSubtarget>().isPPC64()) {
223 setOperationAction(ISD::VAARG, MVT::Other, Custom);
224 setOperationAction(ISD::VAARG, MVT::i64, Custom);
226 setOperationAction(ISD::VAARG, MVT::Other, Expand);
228 // Use the default implementation.
229 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
230 setOperationAction(ISD::VAEND , MVT::Other, Expand);
231 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
232 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
233 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
234 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
236 // We want to custom lower some of our intrinsics.
237 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
239 // Comparisons that require checking two conditions.
240 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
244 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
245 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
246 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
247 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
248 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
249 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
250 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
251 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
253 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
254 // They also have instructions for converting between i64 and fp.
255 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
256 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
257 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
259 // This is just the low 32 bits of a (signed) fp->i64 conversion.
260 // We cannot do this with Promote because i64 is not a legal type.
261 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
263 // FIXME: disable this lowered code. This generates 64-bit register values,
264 // and we don't model the fact that the top part is clobbered by calls. We
265 // need to flag these together so that the value isn't live across a call.
266 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
268 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
269 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
272 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
273 // 64-bit PowerPC implementations can support i64 types directly
274 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
275 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
276 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
277 // 64-bit PowerPC wants to expand i128 shifts itself.
278 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
279 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
280 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
282 // 32-bit PowerPC wants to expand i64 shifts itself.
283 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
284 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
285 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
288 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
289 // First set operation action for all vector types to expand. Then we
290 // will selectively turn on ones that can be effectively codegen'd.
291 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
292 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
293 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
295 // add/sub are legal for all supported vector VT's.
296 setOperationAction(ISD::ADD , VT, Legal);
297 setOperationAction(ISD::SUB , VT, Legal);
299 // We promote all shuffles to v16i8.
300 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
301 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
303 // We promote all non-typed operations to v4i32.
304 setOperationAction(ISD::AND , VT, Promote);
305 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
306 setOperationAction(ISD::OR , VT, Promote);
307 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
308 setOperationAction(ISD::XOR , VT, Promote);
309 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
310 setOperationAction(ISD::LOAD , VT, Promote);
311 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
312 setOperationAction(ISD::SELECT, VT, Promote);
313 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
314 setOperationAction(ISD::STORE, VT, Promote);
315 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
317 // No other operations are legal.
318 setOperationAction(ISD::MUL , VT, Expand);
319 setOperationAction(ISD::SDIV, VT, Expand);
320 setOperationAction(ISD::SREM, VT, Expand);
321 setOperationAction(ISD::UDIV, VT, Expand);
322 setOperationAction(ISD::UREM, VT, Expand);
323 setOperationAction(ISD::FDIV, VT, Expand);
324 setOperationAction(ISD::FNEG, VT, Expand);
325 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
326 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
327 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
328 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
329 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
330 setOperationAction(ISD::UDIVREM, VT, Expand);
331 setOperationAction(ISD::SDIVREM, VT, Expand);
332 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
333 setOperationAction(ISD::FPOW, VT, Expand);
334 setOperationAction(ISD::CTPOP, VT, Expand);
335 setOperationAction(ISD::CTLZ, VT, Expand);
336 setOperationAction(ISD::CTTZ, VT, Expand);
339 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
340 // with merges, splats, etc.
341 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
343 setOperationAction(ISD::AND , MVT::v4i32, Legal);
344 setOperationAction(ISD::OR , MVT::v4i32, Legal);
345 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
346 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
347 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
348 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
350 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
351 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
352 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
353 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
355 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
356 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
357 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
358 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
360 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
361 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
363 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
364 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
365 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
366 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
369 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
370 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
372 setBooleanContents(ZeroOrOneBooleanContent);
373 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
375 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
376 setStackPointerRegisterToSaveRestore(PPC::X1);
377 setExceptionPointerRegister(PPC::X3);
378 setExceptionSelectorRegister(PPC::X4);
380 setStackPointerRegisterToSaveRestore(PPC::R1);
381 setExceptionPointerRegister(PPC::R3);
382 setExceptionSelectorRegister(PPC::R4);
385 // We have target-specific dag combine patterns for the following nodes:
386 setTargetDAGCombine(ISD::SINT_TO_FP);
387 setTargetDAGCombine(ISD::STORE);
388 setTargetDAGCombine(ISD::BR_CC);
389 setTargetDAGCombine(ISD::BSWAP);
391 // Darwin long double math library functions have $LDBL128 appended.
392 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
393 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
394 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
395 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
396 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
397 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
398 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
399 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
400 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
401 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
402 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
405 if (PPCSubTarget.isBookE()) {
406 // Book E: Instructions are always four bytes long and word-aligned.
407 setMinFunctionAlignment(4);
408 setPrefFunctionAlignment(8);
411 setMinFunctionAlignment(2);
412 if (PPCSubTarget.isDarwin())
413 setPrefFunctionAlignment(4);
416 setInsertFencesForAtomic(true);
418 computeRegisterProperties();
421 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
422 /// function arguments in the caller parameter area.
423 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
424 const TargetMachine &TM = getTargetMachine();
425 // Darwin passes everything on 4 byte boundary.
426 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
432 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
435 case PPCISD::FSEL: return "PPCISD::FSEL";
436 case PPCISD::FCFID: return "PPCISD::FCFID";
437 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
438 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
439 case PPCISD::STFIWX: return "PPCISD::STFIWX";
440 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
441 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
442 case PPCISD::VPERM: return "PPCISD::VPERM";
443 case PPCISD::Hi: return "PPCISD::Hi";
444 case PPCISD::Lo: return "PPCISD::Lo";
445 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
446 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
447 case PPCISD::LOAD: return "PPCISD::LOAD";
448 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
449 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
450 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
451 case PPCISD::SRL: return "PPCISD::SRL";
452 case PPCISD::SRA: return "PPCISD::SRA";
453 case PPCISD::SHL: return "PPCISD::SHL";
454 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
455 case PPCISD::STD_32: return "PPCISD::STD_32";
456 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
457 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
458 case PPCISD::NOP: return "PPCISD::NOP";
459 case PPCISD::MTCTR: return "PPCISD::MTCTR";
460 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
461 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
462 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
463 case PPCISD::MFCR: return "PPCISD::MFCR";
464 case PPCISD::VCMP: return "PPCISD::VCMP";
465 case PPCISD::VCMPo: return "PPCISD::VCMPo";
466 case PPCISD::LBRX: return "PPCISD::LBRX";
467 case PPCISD::STBRX: return "PPCISD::STBRX";
468 case PPCISD::LARX: return "PPCISD::LARX";
469 case PPCISD::STCX: return "PPCISD::STCX";
470 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
471 case PPCISD::MFFS: return "PPCISD::MFFS";
472 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
473 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
474 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
475 case PPCISD::MTFSF: return "PPCISD::MTFSF";
476 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
480 EVT PPCTargetLowering::getSetCCResultType(EVT VT) const {
484 //===----------------------------------------------------------------------===//
485 // Node matching predicates, for use by the tblgen matching code.
486 //===----------------------------------------------------------------------===//
488 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
489 static bool isFloatingPointZero(SDValue Op) {
490 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
491 return CFP->getValueAPF().isZero();
492 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
493 // Maybe this has already been legalized into the constant pool?
494 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
495 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
496 return CFP->getValueAPF().isZero();
501 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
502 /// true if Op is undef or if it matches the specified value.
503 static bool isConstantOrUndef(int Op, int Val) {
504 return Op < 0 || Op == Val;
507 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
508 /// VPKUHUM instruction.
509 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
511 for (unsigned i = 0; i != 16; ++i)
512 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
515 for (unsigned i = 0; i != 8; ++i)
516 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
517 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
523 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
524 /// VPKUWUM instruction.
525 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
527 for (unsigned i = 0; i != 16; i += 2)
528 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
529 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
532 for (unsigned i = 0; i != 8; i += 2)
533 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
534 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
535 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
536 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
542 /// isVMerge - Common function, used to match vmrg* shuffles.
544 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
545 unsigned LHSStart, unsigned RHSStart) {
546 assert(N->getValueType(0) == MVT::v16i8 &&
547 "PPC only supports shuffles by bytes!");
548 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
549 "Unsupported merge size!");
551 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
552 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
553 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
554 LHSStart+j+i*UnitSize) ||
555 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
556 RHSStart+j+i*UnitSize))
562 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
563 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
564 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
567 return isVMerge(N, UnitSize, 8, 24);
568 return isVMerge(N, UnitSize, 8, 8);
571 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
572 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
573 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
576 return isVMerge(N, UnitSize, 0, 16);
577 return isVMerge(N, UnitSize, 0, 0);
581 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
582 /// amount, otherwise return -1.
583 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
584 assert(N->getValueType(0) == MVT::v16i8 &&
585 "PPC only supports shuffles by bytes!");
587 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
589 // Find the first non-undef value in the shuffle mask.
591 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
594 if (i == 16) return -1; // all undef.
596 // Otherwise, check to see if the rest of the elements are consecutively
597 // numbered from this value.
598 unsigned ShiftAmt = SVOp->getMaskElt(i);
599 if (ShiftAmt < i) return -1;
603 // Check the rest of the elements to see if they are consecutive.
604 for (++i; i != 16; ++i)
605 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
608 // Check the rest of the elements to see if they are consecutive.
609 for (++i; i != 16; ++i)
610 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
616 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
617 /// specifies a splat of a single element that is suitable for input to
618 /// VSPLTB/VSPLTH/VSPLTW.
619 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
620 assert(N->getValueType(0) == MVT::v16i8 &&
621 (EltSize == 1 || EltSize == 2 || EltSize == 4));
623 // This is a splat operation if each element of the permute is the same, and
624 // if the value doesn't reference the second vector.
625 unsigned ElementBase = N->getMaskElt(0);
627 // FIXME: Handle UNDEF elements too!
628 if (ElementBase >= 16)
631 // Check that the indices are consecutive, in the case of a multi-byte element
632 // splatted with a v16i8 mask.
633 for (unsigned i = 1; i != EltSize; ++i)
634 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
637 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
638 if (N->getMaskElt(i) < 0) continue;
639 for (unsigned j = 0; j != EltSize; ++j)
640 if (N->getMaskElt(i+j) != N->getMaskElt(j))
646 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
648 bool PPC::isAllNegativeZeroVector(SDNode *N) {
649 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
651 APInt APVal, APUndef;
655 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
656 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
657 return CFP->getValueAPF().isNegZero();
662 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
663 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
664 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
665 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
666 assert(isSplatShuffleMask(SVOp, EltSize));
667 return SVOp->getMaskElt(0) / EltSize;
670 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
671 /// by using a vspltis[bhw] instruction of the specified element size, return
672 /// the constant being splatted. The ByteSize field indicates the number of
673 /// bytes of each element [124] -> [bhw].
674 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
677 // If ByteSize of the splat is bigger than the element size of the
678 // build_vector, then we have a case where we are checking for a splat where
679 // multiple elements of the buildvector are folded together into a single
680 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
681 unsigned EltSize = 16/N->getNumOperands();
682 if (EltSize < ByteSize) {
683 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
684 SDValue UniquedVals[4];
685 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
687 // See if all of the elements in the buildvector agree across.
688 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
689 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
690 // If the element isn't a constant, bail fully out.
691 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
694 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
695 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
696 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
697 return SDValue(); // no match.
700 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
701 // either constant or undef values that are identical for each chunk. See
702 // if these chunks can form into a larger vspltis*.
704 // Check to see if all of the leading entries are either 0 or -1. If
705 // neither, then this won't fit into the immediate field.
706 bool LeadingZero = true;
707 bool LeadingOnes = true;
708 for (unsigned i = 0; i != Multiple-1; ++i) {
709 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
711 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
712 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
714 // Finally, check the least significant entry.
716 if (UniquedVals[Multiple-1].getNode() == 0)
717 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
718 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
720 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
723 if (UniquedVals[Multiple-1].getNode() == 0)
724 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
725 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
726 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
727 return DAG.getTargetConstant(Val, MVT::i32);
733 // Check to see if this buildvec has a single non-undef value in its elements.
734 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
735 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
736 if (OpVal.getNode() == 0)
737 OpVal = N->getOperand(i);
738 else if (OpVal != N->getOperand(i))
742 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
744 unsigned ValSizeInBytes = EltSize;
746 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
747 Value = CN->getZExtValue();
748 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
749 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
750 Value = FloatToBits(CN->getValueAPF().convertToFloat());
753 // If the splat value is larger than the element value, then we can never do
754 // this splat. The only case that we could fit the replicated bits into our
755 // immediate field for would be zero, and we prefer to use vxor for it.
756 if (ValSizeInBytes < ByteSize) return SDValue();
758 // If the element value is larger than the splat value, cut it in half and
759 // check to see if the two halves are equal. Continue doing this until we
760 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
761 while (ValSizeInBytes > ByteSize) {
762 ValSizeInBytes >>= 1;
764 // If the top half equals the bottom half, we're still ok.
765 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
766 (Value & ((1 << (8*ValSizeInBytes))-1)))
770 // Properly sign extend the value.
771 int ShAmt = (4-ByteSize)*8;
772 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
774 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
775 if (MaskVal == 0) return SDValue();
777 // Finally, if this value fits in a 5 bit sext field, return it
778 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
779 return DAG.getTargetConstant(MaskVal, MVT::i32);
783 //===----------------------------------------------------------------------===//
784 // Addressing Mode Selection
785 //===----------------------------------------------------------------------===//
787 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
788 /// or 64-bit immediate, and if the value can be accurately represented as a
789 /// sign extension from a 16-bit value. If so, this returns true and the
791 static bool isIntS16Immediate(SDNode *N, short &Imm) {
792 if (N->getOpcode() != ISD::Constant)
795 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
796 if (N->getValueType(0) == MVT::i32)
797 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
799 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
801 static bool isIntS16Immediate(SDValue Op, short &Imm) {
802 return isIntS16Immediate(Op.getNode(), Imm);
806 /// SelectAddressRegReg - Given the specified addressed, check to see if it
807 /// can be represented as an indexed [r+r] operation. Returns false if it
808 /// can be more efficiently represented with [r+imm].
809 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
811 SelectionDAG &DAG) const {
813 if (N.getOpcode() == ISD::ADD) {
814 if (isIntS16Immediate(N.getOperand(1), imm))
816 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
819 Base = N.getOperand(0);
820 Index = N.getOperand(1);
822 } else if (N.getOpcode() == ISD::OR) {
823 if (isIntS16Immediate(N.getOperand(1), imm))
824 return false; // r+i can fold it if we can.
826 // If this is an or of disjoint bitfields, we can codegen this as an add
827 // (for better address arithmetic) if the LHS and RHS of the OR are provably
829 APInt LHSKnownZero, LHSKnownOne;
830 APInt RHSKnownZero, RHSKnownOne;
831 DAG.ComputeMaskedBits(N.getOperand(0),
832 APInt::getAllOnesValue(N.getOperand(0)
833 .getValueSizeInBits()),
834 LHSKnownZero, LHSKnownOne);
836 if (LHSKnownZero.getBoolValue()) {
837 DAG.ComputeMaskedBits(N.getOperand(1),
838 APInt::getAllOnesValue(N.getOperand(1)
839 .getValueSizeInBits()),
840 RHSKnownZero, RHSKnownOne);
841 // If all of the bits are known zero on the LHS or RHS, the add won't
843 if (~(LHSKnownZero | RHSKnownZero) == 0) {
844 Base = N.getOperand(0);
845 Index = N.getOperand(1);
854 /// Returns true if the address N can be represented by a base register plus
855 /// a signed 16-bit displacement [r+imm], and if it is not better
856 /// represented as reg+reg.
857 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
859 SelectionDAG &DAG) const {
860 // FIXME dl should come from parent load or store, not from address
861 DebugLoc dl = N.getDebugLoc();
862 // If this can be more profitably realized as r+r, fail.
863 if (SelectAddressRegReg(N, Disp, Base, DAG))
866 if (N.getOpcode() == ISD::ADD) {
868 if (isIntS16Immediate(N.getOperand(1), imm)) {
869 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
870 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
871 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
873 Base = N.getOperand(0);
875 return true; // [r+i]
876 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
877 // Match LOAD (ADD (X, Lo(G))).
878 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
879 && "Cannot handle constant offsets yet!");
880 Disp = N.getOperand(1).getOperand(0); // The global address.
881 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
882 Disp.getOpcode() == ISD::TargetConstantPool ||
883 Disp.getOpcode() == ISD::TargetJumpTable);
884 Base = N.getOperand(0);
885 return true; // [&g+r]
887 } else if (N.getOpcode() == ISD::OR) {
889 if (isIntS16Immediate(N.getOperand(1), imm)) {
890 // If this is an or of disjoint bitfields, we can codegen this as an add
891 // (for better address arithmetic) if the LHS and RHS of the OR are
892 // provably disjoint.
893 APInt LHSKnownZero, LHSKnownOne;
894 DAG.ComputeMaskedBits(N.getOperand(0),
895 APInt::getAllOnesValue(N.getOperand(0)
896 .getValueSizeInBits()),
897 LHSKnownZero, LHSKnownOne);
899 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
900 // If all of the bits are known zero on the LHS or RHS, the add won't
902 Base = N.getOperand(0);
903 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
907 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
908 // Loading from a constant address.
910 // If this address fits entirely in a 16-bit sext immediate field, codegen
913 if (isIntS16Immediate(CN, Imm)) {
914 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
915 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
916 CN->getValueType(0));
920 // Handle 32-bit sext immediates with LIS + addr mode.
921 if (CN->getValueType(0) == MVT::i32 ||
922 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
923 int Addr = (int)CN->getZExtValue();
925 // Otherwise, break this down into an LIS + disp.
926 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
928 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
929 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
930 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
935 Disp = DAG.getTargetConstant(0, getPointerTy());
936 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
937 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
940 return true; // [r+0]
943 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
944 /// represented as an indexed [r+r] operation.
945 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
947 SelectionDAG &DAG) const {
948 // Check to see if we can easily represent this as an [r+r] address. This
949 // will fail if it thinks that the address is more profitably represented as
950 // reg+imm, e.g. where imm = 0.
951 if (SelectAddressRegReg(N, Base, Index, DAG))
954 // If the operand is an addition, always emit this as [r+r], since this is
955 // better (for code size, and execution, as the memop does the add for free)
956 // than emitting an explicit add.
957 if (N.getOpcode() == ISD::ADD) {
958 Base = N.getOperand(0);
959 Index = N.getOperand(1);
963 // Otherwise, do it the hard way, using R0 as the base register.
964 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
970 /// SelectAddressRegImmShift - Returns true if the address N can be
971 /// represented by a base register plus a signed 14-bit displacement
972 /// [r+imm*4]. Suitable for use by STD and friends.
973 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
975 SelectionDAG &DAG) const {
976 // FIXME dl should come from the parent load or store, not the address
977 DebugLoc dl = N.getDebugLoc();
978 // If this can be more profitably realized as r+r, fail.
979 if (SelectAddressRegReg(N, Disp, Base, DAG))
982 if (N.getOpcode() == ISD::ADD) {
984 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
985 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
986 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
987 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
989 Base = N.getOperand(0);
991 return true; // [r+i]
992 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
993 // Match LOAD (ADD (X, Lo(G))).
994 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
995 && "Cannot handle constant offsets yet!");
996 Disp = N.getOperand(1).getOperand(0); // The global address.
997 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
998 Disp.getOpcode() == ISD::TargetConstantPool ||
999 Disp.getOpcode() == ISD::TargetJumpTable);
1000 Base = N.getOperand(0);
1001 return true; // [&g+r]
1003 } else if (N.getOpcode() == ISD::OR) {
1005 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
1006 // If this is an or of disjoint bitfields, we can codegen this as an add
1007 // (for better address arithmetic) if the LHS and RHS of the OR are
1008 // provably disjoint.
1009 APInt LHSKnownZero, LHSKnownOne;
1010 DAG.ComputeMaskedBits(N.getOperand(0),
1011 APInt::getAllOnesValue(N.getOperand(0)
1012 .getValueSizeInBits()),
1013 LHSKnownZero, LHSKnownOne);
1014 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1015 // If all of the bits are known zero on the LHS or RHS, the add won't
1017 Base = N.getOperand(0);
1018 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1022 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1023 // Loading from a constant address. Verify low two bits are clear.
1024 if ((CN->getZExtValue() & 3) == 0) {
1025 // If this address fits entirely in a 14-bit sext immediate field, codegen
1028 if (isIntS16Immediate(CN, Imm)) {
1029 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1030 Base = DAG.getRegister(PPCSubTarget.isPPC64() ? PPC::X0 : PPC::R0,
1031 CN->getValueType(0));
1035 // Fold the low-part of 32-bit absolute addresses into addr mode.
1036 if (CN->getValueType(0) == MVT::i32 ||
1037 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1038 int Addr = (int)CN->getZExtValue();
1040 // Otherwise, break this down into an LIS + disp.
1041 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1042 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1043 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1044 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1050 Disp = DAG.getTargetConstant(0, getPointerTy());
1051 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1052 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1055 return true; // [r+0]
1059 /// getPreIndexedAddressParts - returns true by value, base pointer and
1060 /// offset pointer and addressing mode by reference if the node's address
1061 /// can be legally represented as pre-indexed load / store address.
1062 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1064 ISD::MemIndexedMode &AM,
1065 SelectionDAG &DAG) const {
1066 // Disabled by default for now.
1067 if (!EnablePPCPreinc) return false;
1071 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1072 Ptr = LD->getBasePtr();
1073 VT = LD->getMemoryVT();
1075 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1076 Ptr = ST->getBasePtr();
1077 VT = ST->getMemoryVT();
1081 // PowerPC doesn't have preinc load/store instructions for vectors.
1085 // TODO: Check reg+reg first.
1087 // LDU/STU use reg+imm*4, others use reg+imm.
1088 if (VT != MVT::i64) {
1090 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1094 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1098 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1099 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1100 // sext i32 to i64 when addr mode is r+i.
1101 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1102 LD->getExtensionType() == ISD::SEXTLOAD &&
1103 isa<ConstantSDNode>(Offset))
1111 //===----------------------------------------------------------------------===//
1112 // LowerOperation implementation
1113 //===----------------------------------------------------------------------===//
1115 /// GetLabelAccessInfo - Return true if we should reference labels using a
1116 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1117 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1118 unsigned &LoOpFlags, const GlobalValue *GV = 0) {
1119 HiOpFlags = PPCII::MO_HA16;
1120 LoOpFlags = PPCII::MO_LO16;
1122 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1123 // non-darwin platform. We don't support PIC on other platforms yet.
1124 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1125 TM.getSubtarget<PPCSubtarget>().isDarwin();
1127 HiOpFlags |= PPCII::MO_PIC_FLAG;
1128 LoOpFlags |= PPCII::MO_PIC_FLAG;
1131 // If this is a reference to a global value that requires a non-lazy-ptr, make
1132 // sure that instruction lowering adds it.
1133 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1134 HiOpFlags |= PPCII::MO_NLP_FLAG;
1135 LoOpFlags |= PPCII::MO_NLP_FLAG;
1137 if (GV->hasHiddenVisibility()) {
1138 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1139 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1146 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1147 SelectionDAG &DAG) {
1148 EVT PtrVT = HiPart.getValueType();
1149 SDValue Zero = DAG.getConstant(0, PtrVT);
1150 DebugLoc DL = HiPart.getDebugLoc();
1152 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1153 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1155 // With PIC, the first instruction is actually "GR+hi(&G)".
1157 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1158 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1160 // Generate non-pic code that has direct accesses to the constant pool.
1161 // The address of the global is just (hi(&g)+lo(&g)).
1162 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1165 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1166 SelectionDAG &DAG) const {
1167 EVT PtrVT = Op.getValueType();
1168 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1169 const Constant *C = CP->getConstVal();
1171 unsigned MOHiFlag, MOLoFlag;
1172 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1174 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1176 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1177 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1180 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1181 EVT PtrVT = Op.getValueType();
1182 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1184 unsigned MOHiFlag, MOLoFlag;
1185 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1186 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1187 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1188 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1191 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1192 SelectionDAG &DAG) const {
1193 EVT PtrVT = Op.getValueType();
1195 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1197 unsigned MOHiFlag, MOLoFlag;
1198 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1199 SDValue TgtBAHi = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOHiFlag);
1200 SDValue TgtBALo = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true, MOLoFlag);
1201 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1204 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1205 SelectionDAG &DAG) const {
1206 EVT PtrVT = Op.getValueType();
1207 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1208 DebugLoc DL = GSDN->getDebugLoc();
1209 const GlobalValue *GV = GSDN->getGlobal();
1211 // 64-bit SVR4 ABI code is always position-independent.
1212 // The actual address of the GlobalValue is stored in the TOC.
1213 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1214 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1215 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1216 DAG.getRegister(PPC::X2, MVT::i64));
1219 unsigned MOHiFlag, MOLoFlag;
1220 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1223 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1225 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1227 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1229 // If the global reference is actually to a non-lazy-pointer, we have to do an
1230 // extra load to get the address of the global.
1231 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1232 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1237 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1238 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1239 DebugLoc dl = Op.getDebugLoc();
1241 // If we're comparing for equality to zero, expose the fact that this is
1242 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1243 // fold the new nodes.
1244 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1245 if (C->isNullValue() && CC == ISD::SETEQ) {
1246 EVT VT = Op.getOperand(0).getValueType();
1247 SDValue Zext = Op.getOperand(0);
1248 if (VT.bitsLT(MVT::i32)) {
1250 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1252 unsigned Log2b = Log2_32(VT.getSizeInBits());
1253 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1254 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1255 DAG.getConstant(Log2b, MVT::i32));
1256 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1258 // Leave comparisons against 0 and -1 alone for now, since they're usually
1259 // optimized. FIXME: revisit this when we can custom lower all setcc
1261 if (C->isAllOnesValue() || C->isNullValue())
1265 // If we have an integer seteq/setne, turn it into a compare against zero
1266 // by xor'ing the rhs with the lhs, which is faster than setting a
1267 // condition register, reading it back out, and masking the correct bit. The
1268 // normal approach here uses sub to do this instead of xor. Using xor exposes
1269 // the result to other bit-twiddling opportunities.
1270 EVT LHSVT = Op.getOperand(0).getValueType();
1271 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1272 EVT VT = Op.getValueType();
1273 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1275 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1280 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1281 const PPCSubtarget &Subtarget) const {
1282 SDNode *Node = Op.getNode();
1283 EVT VT = Node->getValueType(0);
1284 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1285 SDValue InChain = Node->getOperand(0);
1286 SDValue VAListPtr = Node->getOperand(1);
1287 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1288 DebugLoc dl = Node->getDebugLoc();
1290 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1293 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1294 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1296 InChain = GprIndex.getValue(1);
1298 if (VT == MVT::i64) {
1299 // Check if GprIndex is even
1300 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1301 DAG.getConstant(1, MVT::i32));
1302 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1303 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1304 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1305 DAG.getConstant(1, MVT::i32));
1306 // Align GprIndex to be even if it isn't
1307 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1311 // fpr index is 1 byte after gpr
1312 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1313 DAG.getConstant(1, MVT::i32));
1316 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1317 FprPtr, MachinePointerInfo(SV), MVT::i8,
1319 InChain = FprIndex.getValue(1);
1321 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1322 DAG.getConstant(8, MVT::i32));
1324 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1325 DAG.getConstant(4, MVT::i32));
1328 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1329 MachinePointerInfo(), false, false, 0);
1330 InChain = OverflowArea.getValue(1);
1332 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1333 MachinePointerInfo(), false, false, 0);
1334 InChain = RegSaveArea.getValue(1);
1336 // select overflow_area if index > 8
1337 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1338 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1340 // adjustment constant gpr_index * 4/8
1341 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1342 VT.isInteger() ? GprIndex : FprIndex,
1343 DAG.getConstant(VT.isInteger() ? 4 : 8,
1346 // OurReg = RegSaveArea + RegConstant
1347 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1350 // Floating types are 32 bytes into RegSaveArea
1351 if (VT.isFloatingPoint())
1352 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1353 DAG.getConstant(32, MVT::i32));
1355 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1356 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1357 VT.isInteger() ? GprIndex : FprIndex,
1358 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1361 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1362 VT.isInteger() ? VAListPtr : FprPtr,
1363 MachinePointerInfo(SV),
1364 MVT::i8, false, false, 0);
1366 // determine if we should load from reg_save_area or overflow_area
1367 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1369 // increase overflow_area by 4/8 if gpr/fpr > 8
1370 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1371 DAG.getConstant(VT.isInteger() ? 4 : 8,
1374 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1377 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1379 MachinePointerInfo(),
1380 MVT::i32, false, false, 0);
1382 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(), false, false, 0);
1385 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1386 SelectionDAG &DAG) const {
1387 return Op.getOperand(0);
1390 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1391 SelectionDAG &DAG) const {
1392 SDValue Chain = Op.getOperand(0);
1393 SDValue Trmp = Op.getOperand(1); // trampoline
1394 SDValue FPtr = Op.getOperand(2); // nested function
1395 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1396 DebugLoc dl = Op.getDebugLoc();
1398 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1399 bool isPPC64 = (PtrVT == MVT::i64);
1401 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1404 TargetLowering::ArgListTy Args;
1405 TargetLowering::ArgListEntry Entry;
1407 Entry.Ty = IntPtrTy;
1408 Entry.Node = Trmp; Args.push_back(Entry);
1410 // TrampSize == (isPPC64 ? 48 : 40);
1411 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1412 isPPC64 ? MVT::i64 : MVT::i32);
1413 Args.push_back(Entry);
1415 Entry.Node = FPtr; Args.push_back(Entry);
1416 Entry.Node = Nest; Args.push_back(Entry);
1418 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1419 std::pair<SDValue, SDValue> CallResult =
1420 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
1421 false, false, false, false, 0, CallingConv::C, false,
1422 /*isReturnValueUsed=*/true,
1423 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1426 return CallResult.second;
1429 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1430 const PPCSubtarget &Subtarget) const {
1431 MachineFunction &MF = DAG.getMachineFunction();
1432 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1434 DebugLoc dl = Op.getDebugLoc();
1436 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1437 // vastart just stores the address of the VarArgsFrameIndex slot into the
1438 // memory location argument.
1439 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1440 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1441 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1442 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1443 MachinePointerInfo(SV),
1447 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1448 // We suppose the given va_list is already allocated.
1451 // char gpr; /* index into the array of 8 GPRs
1452 // * stored in the register save area
1453 // * gpr=0 corresponds to r3,
1454 // * gpr=1 to r4, etc.
1456 // char fpr; /* index into the array of 8 FPRs
1457 // * stored in the register save area
1458 // * fpr=0 corresponds to f1,
1459 // * fpr=1 to f2, etc.
1461 // char *overflow_arg_area;
1462 // /* location on stack that holds
1463 // * the next overflow argument
1465 // char *reg_save_area;
1466 // /* where r3:r10 and f1:f8 (if saved)
1472 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1473 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1476 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1478 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1480 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1483 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1484 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1486 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1487 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1489 uint64_t FPROffset = 1;
1490 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1492 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1494 // Store first byte : number of int regs
1495 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1497 MachinePointerInfo(SV),
1498 MVT::i8, false, false, 0);
1499 uint64_t nextOffset = FPROffset;
1500 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1503 // Store second byte : number of float regs
1504 SDValue secondStore =
1505 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
1506 MachinePointerInfo(SV, nextOffset), MVT::i8,
1508 nextOffset += StackOffset;
1509 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1511 // Store second word : arguments given on stack
1512 SDValue thirdStore =
1513 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
1514 MachinePointerInfo(SV, nextOffset),
1516 nextOffset += FrameOffset;
1517 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1519 // Store third word : arguments given in registers
1520 return DAG.getStore(thirdStore, dl, FR, nextPtr,
1521 MachinePointerInfo(SV, nextOffset),
1526 #include "PPCGenCallingConv.inc"
1528 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
1529 CCValAssign::LocInfo &LocInfo,
1530 ISD::ArgFlagsTy &ArgFlags,
1535 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
1537 CCValAssign::LocInfo &LocInfo,
1538 ISD::ArgFlagsTy &ArgFlags,
1540 static const unsigned ArgRegs[] = {
1541 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1542 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1544 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1546 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1548 // Skip one register if the first unallocated register has an even register
1549 // number and there are still argument registers available which have not been
1550 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1551 // need to skip a register if RegNum is odd.
1552 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1553 State.AllocateReg(ArgRegs[RegNum]);
1556 // Always return false here, as this function only makes sure that the first
1557 // unallocated register has an odd register number and does not actually
1558 // allocate a register for the current argument.
1562 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
1564 CCValAssign::LocInfo &LocInfo,
1565 ISD::ArgFlagsTy &ArgFlags,
1567 static const unsigned ArgRegs[] = {
1568 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1572 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1574 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1576 // If there is only one Floating-point register left we need to put both f64
1577 // values of a split ppc_fp128 value on the stack.
1578 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1579 State.AllocateReg(ArgRegs[RegNum]);
1582 // Always return false here, as this function only makes sure that the two f64
1583 // values a ppc_fp128 value is split into are both passed in registers or both
1584 // passed on the stack and does not actually allocate a register for the
1585 // current argument.
1589 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1591 static const unsigned *GetFPR() {
1592 static const unsigned FPR[] = {
1593 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1594 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1600 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1602 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1603 unsigned PtrByteSize) {
1604 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1605 if (Flags.isByVal())
1606 ArgSize = Flags.getByValSize();
1607 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1613 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1614 CallingConv::ID CallConv, bool isVarArg,
1615 const SmallVectorImpl<ISD::InputArg>
1617 DebugLoc dl, SelectionDAG &DAG,
1618 SmallVectorImpl<SDValue> &InVals)
1620 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1621 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1624 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1630 PPCTargetLowering::LowerFormalArguments_SVR4(
1632 CallingConv::ID CallConv, bool isVarArg,
1633 const SmallVectorImpl<ISD::InputArg>
1635 DebugLoc dl, SelectionDAG &DAG,
1636 SmallVectorImpl<SDValue> &InVals) const {
1638 // 32-bit SVR4 ABI Stack Frame Layout:
1639 // +-----------------------------------+
1640 // +--> | Back chain |
1641 // | +-----------------------------------+
1642 // | | Floating-point register save area |
1643 // | +-----------------------------------+
1644 // | | General register save area |
1645 // | +-----------------------------------+
1646 // | | CR save word |
1647 // | +-----------------------------------+
1648 // | | VRSAVE save word |
1649 // | +-----------------------------------+
1650 // | | Alignment padding |
1651 // | +-----------------------------------+
1652 // | | Vector register save area |
1653 // | +-----------------------------------+
1654 // | | Local variable space |
1655 // | +-----------------------------------+
1656 // | | Parameter list area |
1657 // | +-----------------------------------+
1658 // | | LR save word |
1659 // | +-----------------------------------+
1660 // SP--> +--- | Back chain |
1661 // +-----------------------------------+
1664 // System V Application Binary Interface PowerPC Processor Supplement
1665 // AltiVec Technology Programming Interface Manual
1667 MachineFunction &MF = DAG.getMachineFunction();
1668 MachineFrameInfo *MFI = MF.getFrameInfo();
1669 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1671 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1672 // Potential tail calls could cause overwriting of argument stack slots.
1673 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1674 unsigned PtrByteSize = 4;
1676 // Assign locations to all of the incoming arguments.
1677 SmallVector<CCValAssign, 16> ArgLocs;
1678 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1679 getTargetMachine(), ArgLocs, *DAG.getContext());
1681 // Reserve space for the linkage area on the stack.
1682 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
1684 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1686 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1687 CCValAssign &VA = ArgLocs[i];
1689 // Arguments stored in registers.
1690 if (VA.isRegLoc()) {
1691 TargetRegisterClass *RC;
1692 EVT ValVT = VA.getValVT();
1694 switch (ValVT.getSimpleVT().SimpleTy) {
1696 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1698 RC = PPC::GPRCRegisterClass;
1701 RC = PPC::F4RCRegisterClass;
1704 RC = PPC::F8RCRegisterClass;
1710 RC = PPC::VRRCRegisterClass;
1714 // Transform the arguments stored in physical registers into virtual ones.
1715 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1716 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1718 InVals.push_back(ArgValue);
1720 // Argument stored in memory.
1721 assert(VA.isMemLoc());
1723 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1724 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1727 // Create load nodes to retrieve arguments from the stack.
1728 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1729 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
1730 MachinePointerInfo(),
1735 // Assign locations to all of the incoming aggregate by value arguments.
1736 // Aggregates passed by value are stored in the local variable space of the
1737 // caller's stack frame, right above the parameter list area.
1738 SmallVector<CCValAssign, 16> ByValArgLocs;
1739 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
1740 getTargetMachine(), ByValArgLocs, *DAG.getContext());
1742 // Reserve stack space for the allocations in CCInfo.
1743 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1745 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1747 // Area that is at least reserved in the caller of this function.
1748 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1750 // Set the size that is at least reserved in caller of this function. Tail
1751 // call optimized function's reserved stack space needs to be aligned so that
1752 // taking the difference between two stack areas will result in an aligned
1754 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1757 std::max(MinReservedArea,
1758 PPCFrameLowering::getMinCallFrameSize(false, false));
1760 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
1761 getStackAlignment();
1762 unsigned AlignMask = TargetAlign-1;
1763 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1765 FI->setMinReservedArea(MinReservedArea);
1767 SmallVector<SDValue, 8> MemOps;
1769 // If the function takes variable number of arguments, make a frame index for
1770 // the start of the first vararg value... for expansion of llvm.va_start.
1772 static const unsigned GPArgRegs[] = {
1773 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1774 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1776 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1778 static const unsigned FPArgRegs[] = {
1779 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1782 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1784 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1786 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1789 // Make room for NumGPArgRegs and NumFPArgRegs.
1790 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1791 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1793 FuncInfo->setVarArgsStackOffset(
1794 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1795 CCInfo.getNextStackOffset(), true));
1797 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1798 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1800 // The fixed integer arguments of a variadic function are stored to the
1801 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
1802 // the result of va_next.
1803 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1804 // Get an existing live-in vreg, or add a new one.
1805 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
1807 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1809 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1810 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1811 MachinePointerInfo(), false, false, 0);
1812 MemOps.push_back(Store);
1813 // Increment the address by four for the next argument to store
1814 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1815 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1818 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1820 // The double arguments are stored to the VarArgsFrameIndex
1822 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1823 // Get an existing live-in vreg, or add a new one.
1824 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
1826 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1828 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1829 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1830 MachinePointerInfo(), false, false, 0);
1831 MemOps.push_back(Store);
1832 // Increment the address by eight for the next argument to store
1833 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1835 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1839 if (!MemOps.empty())
1840 Chain = DAG.getNode(ISD::TokenFactor, dl,
1841 MVT::Other, &MemOps[0], MemOps.size());
1847 PPCTargetLowering::LowerFormalArguments_Darwin(
1849 CallingConv::ID CallConv, bool isVarArg,
1850 const SmallVectorImpl<ISD::InputArg>
1852 DebugLoc dl, SelectionDAG &DAG,
1853 SmallVectorImpl<SDValue> &InVals) const {
1854 // TODO: add description of PPC stack frame format, or at least some docs.
1856 MachineFunction &MF = DAG.getMachineFunction();
1857 MachineFrameInfo *MFI = MF.getFrameInfo();
1858 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1860 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1861 bool isPPC64 = PtrVT == MVT::i64;
1862 // Potential tail calls could cause overwriting of argument stack slots.
1863 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1864 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1866 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
1867 // Area that is at least reserved in caller of this function.
1868 unsigned MinReservedArea = ArgOffset;
1870 static const unsigned GPR_32[] = { // 32-bit registers.
1871 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1872 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1874 static const unsigned GPR_64[] = { // 64-bit registers.
1875 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1876 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1879 static const unsigned *FPR = GetFPR();
1881 static const unsigned VR[] = {
1882 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1883 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1886 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1887 const unsigned Num_FPR_Regs = 13;
1888 const unsigned Num_VR_Regs = array_lengthof( VR);
1890 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1892 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1894 // In 32-bit non-varargs functions, the stack space for vectors is after the
1895 // stack space for non-vectors. We do not use this space unless we have
1896 // too many vectors to fit in registers, something that only occurs in
1897 // constructed examples:), but we have to walk the arglist to figure
1898 // that out...for the pathological case, compute VecArgOffset as the
1899 // start of the vector parameter area. Computing VecArgOffset is the
1900 // entire point of the following loop.
1901 unsigned VecArgOffset = ArgOffset;
1902 if (!isVarArg && !isPPC64) {
1903 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1905 EVT ObjectVT = Ins[ArgNo].VT;
1906 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1907 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1909 if (Flags.isByVal()) {
1910 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1911 ObjSize = Flags.getByValSize();
1913 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1914 VecArgOffset += ArgSize;
1918 switch(ObjectVT.getSimpleVT().SimpleTy) {
1919 default: llvm_unreachable("Unhandled argument type!");
1922 VecArgOffset += isPPC64 ? 8 : 4;
1924 case MVT::i64: // PPC64
1932 // Nothing to do, we're only looking at Nonvector args here.
1937 // We've found where the vector parameter area in memory is. Skip the
1938 // first 12 parameters; these don't use that memory.
1939 VecArgOffset = ((VecArgOffset+15)/16)*16;
1940 VecArgOffset += 12*16;
1942 // Add DAG nodes to load the arguments or copy them out of registers. On
1943 // entry to a function on PPC, the arguments start after the linkage area,
1944 // although the first ones are often in registers.
1946 SmallVector<SDValue, 8> MemOps;
1947 unsigned nAltivecParamsAtEnd = 0;
1948 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1950 bool needsLoad = false;
1951 EVT ObjectVT = Ins[ArgNo].VT;
1952 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1953 unsigned ArgSize = ObjSize;
1954 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1956 unsigned CurArgOffset = ArgOffset;
1958 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1959 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1960 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1961 if (isVarArg || isPPC64) {
1962 MinReservedArea = ((MinReservedArea+15)/16)*16;
1963 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1966 } else nAltivecParamsAtEnd++;
1968 // Calculate min reserved area.
1969 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1973 // FIXME the codegen can be much improved in some cases.
1974 // We do not have to keep everything in memory.
1975 if (Flags.isByVal()) {
1976 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1977 ObjSize = Flags.getByValSize();
1978 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1979 // Objects of size 1 and 2 are right justified, everything else is
1980 // left justified. This means the memory address is adjusted forwards.
1981 if (ObjSize==1 || ObjSize==2) {
1982 CurArgOffset = CurArgOffset + (4 - ObjSize);
1984 // The value of the object is its address.
1985 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
1986 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1987 InVals.push_back(FIN);
1988 if (ObjSize==1 || ObjSize==2) {
1989 if (GPR_idx != Num_GPR_Regs) {
1992 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1994 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1995 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1996 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1997 MachinePointerInfo(),
1998 ObjSize==1 ? MVT::i8 : MVT::i16,
2000 MemOps.push_back(Store);
2004 ArgOffset += PtrByteSize;
2008 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2009 // Store whatever pieces of the object are in registers
2010 // to memory. ArgVal will be address of the beginning of
2012 if (GPR_idx != Num_GPR_Regs) {
2015 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2017 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2018 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2019 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2020 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2021 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2022 MachinePointerInfo(),
2024 MemOps.push_back(Store);
2026 ArgOffset += PtrByteSize;
2028 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2035 switch (ObjectVT.getSimpleVT().SimpleTy) {
2036 default: llvm_unreachable("Unhandled argument type!");
2039 if (GPR_idx != Num_GPR_Regs) {
2040 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2041 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2045 ArgSize = PtrByteSize;
2047 // All int arguments reserve stack space in the Darwin ABI.
2048 ArgOffset += PtrByteSize;
2052 case MVT::i64: // PPC64
2053 if (GPR_idx != Num_GPR_Regs) {
2054 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2055 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2057 if (ObjectVT == MVT::i32) {
2058 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2059 // value to MVT::i64 and then truncate to the correct register size.
2061 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2062 DAG.getValueType(ObjectVT));
2063 else if (Flags.isZExt())
2064 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2065 DAG.getValueType(ObjectVT));
2067 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2073 ArgSize = PtrByteSize;
2075 // All int arguments reserve stack space in the Darwin ABI.
2081 // Every 4 bytes of argument space consumes one of the GPRs available for
2082 // argument passing.
2083 if (GPR_idx != Num_GPR_Regs) {
2085 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2088 if (FPR_idx != Num_FPR_Regs) {
2091 if (ObjectVT == MVT::f32)
2092 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2094 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2096 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2102 // All FP arguments reserve stack space in the Darwin ABI.
2103 ArgOffset += isPPC64 ? 8 : ObjSize;
2109 // Note that vector arguments in registers don't reserve stack space,
2110 // except in varargs functions.
2111 if (VR_idx != Num_VR_Regs) {
2112 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2113 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2115 while ((ArgOffset % 16) != 0) {
2116 ArgOffset += PtrByteSize;
2117 if (GPR_idx != Num_GPR_Regs)
2121 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2125 if (!isVarArg && !isPPC64) {
2126 // Vectors go after all the nonvectors.
2127 CurArgOffset = VecArgOffset;
2130 // Vectors are aligned.
2131 ArgOffset = ((ArgOffset+15)/16)*16;
2132 CurArgOffset = ArgOffset;
2140 // We need to load the argument to a virtual register if we determined above
2141 // that we ran out of physical registers of the appropriate type.
2143 int FI = MFI->CreateFixedObject(ObjSize,
2144 CurArgOffset + (ArgSize - ObjSize),
2146 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2147 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2151 InVals.push_back(ArgVal);
2154 // Set the size that is at least reserved in caller of this function. Tail
2155 // call optimized function's reserved stack space needs to be aligned so that
2156 // taking the difference between two stack areas will result in an aligned
2158 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2159 // Add the Altivec parameters at the end, if needed.
2160 if (nAltivecParamsAtEnd) {
2161 MinReservedArea = ((MinReservedArea+15)/16)*16;
2162 MinReservedArea += 16*nAltivecParamsAtEnd;
2165 std::max(MinReservedArea,
2166 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2167 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2168 getStackAlignment();
2169 unsigned AlignMask = TargetAlign-1;
2170 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2171 FI->setMinReservedArea(MinReservedArea);
2173 // If the function takes variable number of arguments, make a frame index for
2174 // the start of the first vararg value... for expansion of llvm.va_start.
2176 int Depth = ArgOffset;
2178 FuncInfo->setVarArgsFrameIndex(
2179 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2181 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2183 // If this function is vararg, store any remaining integer argument regs
2184 // to their spots on the stack so that they may be loaded by deferencing the
2185 // result of va_next.
2186 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2190 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2192 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2194 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2195 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2196 MachinePointerInfo(), false, false, 0);
2197 MemOps.push_back(Store);
2198 // Increment the address by four for the next argument to store
2199 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2200 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2204 if (!MemOps.empty())
2205 Chain = DAG.getNode(ISD::TokenFactor, dl,
2206 MVT::Other, &MemOps[0], MemOps.size());
2211 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2212 /// linkage area for the Darwin ABI.
2214 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2218 const SmallVectorImpl<ISD::OutputArg>
2220 const SmallVectorImpl<SDValue> &OutVals,
2221 unsigned &nAltivecParamsAtEnd) {
2222 // Count how many bytes are to be pushed on the stack, including the linkage
2223 // area, and parameter passing area. We start with 24/48 bytes, which is
2224 // prereserved space for [SP][CR][LR][3 x unused].
2225 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
2226 unsigned NumOps = Outs.size();
2227 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2229 // Add up all the space actually used.
2230 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2231 // they all go in registers, but we must reserve stack space for them for
2232 // possible use by the caller. In varargs or 64-bit calls, parameters are
2233 // assigned stack space in order, with padding so Altivec parameters are
2235 nAltivecParamsAtEnd = 0;
2236 for (unsigned i = 0; i != NumOps; ++i) {
2237 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2238 EVT ArgVT = Outs[i].VT;
2239 // Varargs Altivec parameters are padded to a 16 byte boundary.
2240 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2241 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2242 if (!isVarArg && !isPPC64) {
2243 // Non-varargs Altivec parameters go after all the non-Altivec
2244 // parameters; handle those later so we know how much padding we need.
2245 nAltivecParamsAtEnd++;
2248 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2249 NumBytes = ((NumBytes+15)/16)*16;
2251 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2254 // Allow for Altivec parameters at the end, if needed.
2255 if (nAltivecParamsAtEnd) {
2256 NumBytes = ((NumBytes+15)/16)*16;
2257 NumBytes += 16*nAltivecParamsAtEnd;
2260 // The prolog code of the callee may store up to 8 GPR argument registers to
2261 // the stack, allowing va_start to index over them in memory if its varargs.
2262 // Because we cannot tell if this is needed on the caller side, we have to
2263 // conservatively assume that it is needed. As such, make sure we have at
2264 // least enough stack space for the caller to store the 8 GPRs.
2265 NumBytes = std::max(NumBytes,
2266 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2268 // Tail call needs the stack to be aligned.
2269 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2270 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2271 getStackAlignment();
2272 unsigned AlignMask = TargetAlign-1;
2273 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2279 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2280 /// adjusted to accommodate the arguments for the tailcall.
2281 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2282 unsigned ParamSize) {
2284 if (!isTailCall) return 0;
2286 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2287 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2288 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2289 // Remember only if the new adjustement is bigger.
2290 if (SPDiff < FI->getTailCallSPDelta())
2291 FI->setTailCallSPDelta(SPDiff);
2296 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2297 /// for tail call optimization. Targets which want to do tail call
2298 /// optimization should implement this function.
2300 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2301 CallingConv::ID CalleeCC,
2303 const SmallVectorImpl<ISD::InputArg> &Ins,
2304 SelectionDAG& DAG) const {
2305 if (!GuaranteedTailCallOpt)
2308 // Variable argument functions are not supported.
2312 MachineFunction &MF = DAG.getMachineFunction();
2313 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2314 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2315 // Functions containing by val parameters are not supported.
2316 for (unsigned i = 0; i != Ins.size(); i++) {
2317 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2318 if (Flags.isByVal()) return false;
2321 // Non PIC/GOT tail calls are supported.
2322 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2325 // At the moment we can only do local tail calls (in same module, hidden
2326 // or protected) if we are generating PIC.
2327 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2328 return G->getGlobal()->hasHiddenVisibility()
2329 || G->getGlobal()->hasProtectedVisibility();
2335 /// isCallCompatibleAddress - Return the immediate to use if the specified
2336 /// 32-bit value is representable in the immediate field of a BxA instruction.
2337 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2338 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2341 int Addr = C->getZExtValue();
2342 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2343 (Addr << 6 >> 6) != Addr)
2344 return 0; // Top 6 bits have to be sext of immediate.
2346 return DAG.getConstant((int)C->getZExtValue() >> 2,
2347 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2352 struct TailCallArgumentInfo {
2357 TailCallArgumentInfo() : FrameIdx(0) {}
2362 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2364 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2366 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2367 SmallVector<SDValue, 8> &MemOpChains,
2369 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2370 SDValue Arg = TailCallArgs[i].Arg;
2371 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2372 int FI = TailCallArgs[i].FrameIdx;
2373 // Store relative to framepointer.
2374 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2375 MachinePointerInfo::getFixedStack(FI),
2380 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2381 /// the appropriate stack slot for the tail call optimized function call.
2382 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2383 MachineFunction &MF,
2392 // Calculate the new stack slot for the return address.
2393 int SlotSize = isPPC64 ? 8 : 4;
2394 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
2396 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2397 NewRetAddrLoc, true);
2398 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2399 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2400 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2401 MachinePointerInfo::getFixedStack(NewRetAddr),
2404 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2405 // slot as the FP is never overwritten.
2408 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2409 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2411 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2412 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2413 MachinePointerInfo::getFixedStack(NewFPIdx),
2420 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2421 /// the position of the argument.
2423 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2424 SDValue Arg, int SPDiff, unsigned ArgOffset,
2425 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2426 int Offset = ArgOffset + SPDiff;
2427 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2428 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2429 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2430 SDValue FIN = DAG.getFrameIndex(FI, VT);
2431 TailCallArgumentInfo Info;
2433 Info.FrameIdxOp = FIN;
2435 TailCallArguments.push_back(Info);
2438 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2439 /// stack slot. Returns the chain as result and the loaded frame pointers in
2440 /// LROpOut/FPOpout. Used when tail calling.
2441 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2447 DebugLoc dl) const {
2449 // Load the LR and FP stack slot for later adjusting.
2450 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2451 LROpOut = getReturnAddrFrameIndex(DAG);
2452 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
2454 Chain = SDValue(LROpOut.getNode(), 1);
2456 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2457 // slot as the FP is never overwritten.
2459 FPOpOut = getFramePointerFrameIndex(DAG);
2460 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
2462 Chain = SDValue(FPOpOut.getNode(), 1);
2468 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2469 /// by "Src" to address "Dst" of size "Size". Alignment information is
2470 /// specified by the specific parameter attribute. The copy will be passed as
2471 /// a byval function parameter.
2472 /// Sometimes what we are copying is the end of a larger object, the part that
2473 /// does not fit in registers.
2475 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2476 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2478 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2479 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2480 false, false, MachinePointerInfo(0),
2481 MachinePointerInfo(0));
2484 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2487 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2488 SDValue Arg, SDValue PtrOff, int SPDiff,
2489 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2490 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2491 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments,
2493 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2498 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2500 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2501 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2502 DAG.getConstant(ArgOffset, PtrVT));
2504 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2505 MachinePointerInfo(), false, false, 0));
2506 // Calculate and remember argument location.
2507 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2512 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2513 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2514 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2515 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2516 MachineFunction &MF = DAG.getMachineFunction();
2518 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2519 // might overwrite each other in case of tail call optimization.
2520 SmallVector<SDValue, 8> MemOpChains2;
2521 // Do not flag preceding copytoreg stuff together with the following stuff.
2523 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2525 if (!MemOpChains2.empty())
2526 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2527 &MemOpChains2[0], MemOpChains2.size());
2529 // Store the return address to the appropriate stack slot.
2530 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2531 isPPC64, isDarwinABI, dl);
2533 // Emit callseq_end just before tailcall node.
2534 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2535 DAG.getIntPtrConstant(0, true), InFlag);
2536 InFlag = Chain.getValue(1);
2540 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2541 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2542 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2543 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2544 const PPCSubtarget &PPCSubTarget) {
2546 bool isPPC64 = PPCSubTarget.isPPC64();
2547 bool isSVR4ABI = PPCSubTarget.isSVR4ABI();
2549 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2550 NodeTys.push_back(MVT::Other); // Returns a chain
2551 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
2553 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2555 bool needIndirectCall = true;
2556 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
2557 // If this is an absolute destination address, use the munged value.
2558 Callee = SDValue(Dest, 0);
2559 needIndirectCall = false;
2562 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
2563 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
2564 // Use indirect calls for ALL functions calls in JIT mode, since the
2565 // far-call stubs may be outside relocation limits for a BL instruction.
2566 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
2567 unsigned OpFlags = 0;
2568 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2569 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2570 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
2571 (G->getGlobal()->isDeclaration() ||
2572 G->getGlobal()->isWeakForLinker())) {
2573 // PC-relative references to external symbols should go through $stub,
2574 // unless we're building with the leopard linker or later, which
2575 // automatically synthesizes these stubs.
2576 OpFlags = PPCII::MO_DARWIN_STUB;
2579 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
2580 // every direct call is) turn it into a TargetGlobalAddress /
2581 // TargetExternalSymbol node so that legalize doesn't hack it.
2582 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2583 Callee.getValueType(),
2585 needIndirectCall = false;
2589 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
2590 unsigned char OpFlags = 0;
2592 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
2593 (PPCSubTarget.getTargetTriple().isMacOSX() &&
2594 PPCSubTarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
2595 // PC-relative references to external symbols should go through $stub,
2596 // unless we're building with the leopard linker or later, which
2597 // automatically synthesizes these stubs.
2598 OpFlags = PPCII::MO_DARWIN_STUB;
2601 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
2603 needIndirectCall = false;
2606 if (needIndirectCall) {
2607 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2608 // to do the call, we can't use PPCISD::CALL.
2609 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2611 if (isSVR4ABI && isPPC64) {
2612 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2613 // entry point, but to the function descriptor (the function entry point
2614 // address is part of the function descriptor though).
2615 // The function descriptor is a three doubleword structure with the
2616 // following fields: function entry point, TOC base address and
2617 // environment pointer.
2618 // Thus for a call through a function pointer, the following actions need
2620 // 1. Save the TOC of the caller in the TOC save area of its stack
2621 // frame (this is done in LowerCall_Darwin()).
2622 // 2. Load the address of the function entry point from the function
2624 // 3. Load the TOC of the callee from the function descriptor into r2.
2625 // 4. Load the environment pointer from the function descriptor into
2627 // 5. Branch to the function entry point address.
2628 // 6. On return of the callee, the TOC of the caller needs to be
2629 // restored (this is done in FinishCall()).
2631 // All those operations are flagged together to ensure that no other
2632 // operations can be scheduled in between. E.g. without flagging the
2633 // operations together, a TOC access in the caller could be scheduled
2634 // between the load of the callee TOC and the branch to the callee, which
2635 // results in the TOC access going through the TOC of the callee instead
2636 // of going through the TOC of the caller, which leads to incorrect code.
2638 // Load the address of the function entry point from the function
2640 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
2641 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2642 InFlag.getNode() ? 3 : 2);
2643 Chain = LoadFuncPtr.getValue(1);
2644 InFlag = LoadFuncPtr.getValue(2);
2646 // Load environment pointer into r11.
2647 // Offset of the environment pointer within the function descriptor.
2648 SDValue PtrOff = DAG.getIntPtrConstant(16);
2650 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2651 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2653 Chain = LoadEnvPtr.getValue(1);
2654 InFlag = LoadEnvPtr.getValue(2);
2656 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2658 Chain = EnvVal.getValue(0);
2659 InFlag = EnvVal.getValue(1);
2661 // Load TOC of the callee into r2. We are using a target-specific load
2662 // with r2 hard coded, because the result of a target-independent load
2663 // would never go directly into r2, since r2 is a reserved register (which
2664 // prevents the register allocator from allocating it), resulting in an
2665 // additional register being allocated and an unnecessary move instruction
2667 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2668 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2670 Chain = LoadTOCPtr.getValue(0);
2671 InFlag = LoadTOCPtr.getValue(1);
2673 MTCTROps[0] = Chain;
2674 MTCTROps[1] = LoadFuncPtr;
2675 MTCTROps[2] = InFlag;
2678 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2679 2 + (InFlag.getNode() != 0));
2680 InFlag = Chain.getValue(1);
2683 NodeTys.push_back(MVT::Other);
2684 NodeTys.push_back(MVT::Glue);
2685 Ops.push_back(Chain);
2686 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2688 // Add CTR register as callee so a bctr can be emitted later.
2690 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
2693 // If this is a direct call, pass the chain and the callee.
2694 if (Callee.getNode()) {
2695 Ops.push_back(Chain);
2696 Ops.push_back(Callee);
2698 // If this is a tail call add stack pointer delta.
2700 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2702 // Add argument registers to the end of the list so that they are known live
2704 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2705 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2706 RegsToPass[i].second.getValueType()));
2712 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2713 CallingConv::ID CallConv, bool isVarArg,
2714 const SmallVectorImpl<ISD::InputArg> &Ins,
2715 DebugLoc dl, SelectionDAG &DAG,
2716 SmallVectorImpl<SDValue> &InVals) const {
2718 SmallVector<CCValAssign, 16> RVLocs;
2719 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2720 getTargetMachine(), RVLocs, *DAG.getContext());
2721 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2723 // Copy all of the result registers out of their specified physreg.
2724 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2725 CCValAssign &VA = RVLocs[i];
2726 EVT VT = VA.getValVT();
2727 assert(VA.isRegLoc() && "Can only return in registers!");
2728 Chain = DAG.getCopyFromReg(Chain, dl,
2729 VA.getLocReg(), VT, InFlag).getValue(1);
2730 InVals.push_back(Chain.getValue(0));
2731 InFlag = Chain.getValue(2);
2738 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2739 bool isTailCall, bool isVarArg,
2741 SmallVector<std::pair<unsigned, SDValue>, 8>
2743 SDValue InFlag, SDValue Chain,
2745 int SPDiff, unsigned NumBytes,
2746 const SmallVectorImpl<ISD::InputArg> &Ins,
2747 SmallVectorImpl<SDValue> &InVals) const {
2748 std::vector<EVT> NodeTys;
2749 SmallVector<SDValue, 8> Ops;
2750 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2751 isTailCall, RegsToPass, Ops, NodeTys,
2754 // When performing tail call optimization the callee pops its arguments off
2755 // the stack. Account for this here so these bytes can be pushed back on in
2756 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2757 int BytesCalleePops =
2758 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2760 if (InFlag.getNode())
2761 Ops.push_back(InFlag);
2765 // If this is the first return lowered for this function, add the regs
2766 // to the liveout set for the function.
2767 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2768 SmallVector<CCValAssign, 16> RVLocs;
2769 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2770 getTargetMachine(), RVLocs, *DAG.getContext());
2771 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2772 for (unsigned i = 0; i != RVLocs.size(); ++i)
2773 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2776 assert(((Callee.getOpcode() == ISD::Register &&
2777 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2778 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2779 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2780 isa<ConstantSDNode>(Callee)) &&
2781 "Expecting an global address, external symbol, absolute value or register");
2783 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2786 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2787 InFlag = Chain.getValue(1);
2789 // Add a NOP immediately after the branch instruction when using the 64-bit
2790 // SVR4 ABI. At link time, if caller and callee are in a different module and
2791 // thus have a different TOC, the call will be replaced with a call to a stub
2792 // function which saves the current TOC, loads the TOC of the callee and
2793 // branches to the callee. The NOP will be replaced with a load instruction
2794 // which restores the TOC of the caller from the TOC save slot of the current
2795 // stack frame. If caller and callee belong to the same module (and have the
2796 // same TOC), the NOP will remain unchanged.
2797 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2798 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
2799 if (CallOpc == PPCISD::BCTRL_SVR4) {
2800 // This is a call through a function pointer.
2801 // Restore the caller TOC from the save area into R2.
2802 // See PrepareCall() for more information about calls through function
2803 // pointers in the 64-bit SVR4 ABI.
2804 // We are using a target-specific load with r2 hard coded, because the
2805 // result of a target-independent load would never go directly into r2,
2806 // since r2 is a reserved register (which prevents the register allocator
2807 // from allocating it), resulting in an additional register being
2808 // allocated and an unnecessary move instruction being generated.
2809 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2810 InFlag = Chain.getValue(1);
2812 // Otherwise insert NOP.
2813 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Glue, InFlag);
2817 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2818 DAG.getIntPtrConstant(BytesCalleePops, true),
2821 InFlag = Chain.getValue(1);
2823 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2824 Ins, dl, DAG, InVals);
2828 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2829 CallingConv::ID CallConv, bool isVarArg,
2831 const SmallVectorImpl<ISD::OutputArg> &Outs,
2832 const SmallVectorImpl<SDValue> &OutVals,
2833 const SmallVectorImpl<ISD::InputArg> &Ins,
2834 DebugLoc dl, SelectionDAG &DAG,
2835 SmallVectorImpl<SDValue> &InVals) const {
2837 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2840 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64())
2841 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2842 isTailCall, Outs, OutVals, Ins,
2845 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2846 isTailCall, Outs, OutVals, Ins,
2851 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2852 CallingConv::ID CallConv, bool isVarArg,
2854 const SmallVectorImpl<ISD::OutputArg> &Outs,
2855 const SmallVectorImpl<SDValue> &OutVals,
2856 const SmallVectorImpl<ISD::InputArg> &Ins,
2857 DebugLoc dl, SelectionDAG &DAG,
2858 SmallVectorImpl<SDValue> &InVals) const {
2859 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2860 // of the 32-bit SVR4 ABI stack frame layout.
2862 assert((CallConv == CallingConv::C ||
2863 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2865 unsigned PtrByteSize = 4;
2867 MachineFunction &MF = DAG.getMachineFunction();
2869 // Mark this function as potentially containing a function that contains a
2870 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2871 // and restoring the callers stack pointer in this functions epilog. This is
2872 // done because by tail calling the called function might overwrite the value
2873 // in this function's (MF) stack pointer stack slot 0(SP).
2874 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2875 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2877 // Count how many bytes are to be pushed on the stack, including the linkage
2878 // area, parameter list area and the part of the local variable space which
2879 // contains copies of aggregates which are passed by value.
2881 // Assign locations to all of the outgoing arguments.
2882 SmallVector<CCValAssign, 16> ArgLocs;
2883 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2884 getTargetMachine(), ArgLocs, *DAG.getContext());
2886 // Reserve space for the linkage area on the stack.
2887 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2890 // Handle fixed and variable vector arguments differently.
2891 // Fixed vector arguments go into registers as long as registers are
2892 // available. Variable vector arguments always go into memory.
2893 unsigned NumArgs = Outs.size();
2895 for (unsigned i = 0; i != NumArgs; ++i) {
2896 MVT ArgVT = Outs[i].VT;
2897 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2900 if (Outs[i].IsFixed) {
2901 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2904 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2910 errs() << "Call operand #" << i << " has unhandled type "
2911 << EVT(ArgVT).getEVTString() << "\n";
2913 llvm_unreachable(0);
2917 // All arguments are treated the same.
2918 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2921 // Assign locations to all of the outgoing aggregate by value arguments.
2922 SmallVector<CCValAssign, 16> ByValArgLocs;
2923 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2924 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2926 // Reserve stack space for the allocations in CCInfo.
2927 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2929 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2931 // Size of the linkage area, parameter list area and the part of the local
2932 // space variable where copies of aggregates which are passed by value are
2934 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2936 // Calculate by how many bytes the stack has to be adjusted in case of tail
2937 // call optimization.
2938 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2940 // Adjust the stack pointer for the new arguments...
2941 // These operations are automatically eliminated by the prolog/epilog pass
2942 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2943 SDValue CallSeqStart = Chain;
2945 // Load the return address and frame pointer so it can be moved somewhere else
2948 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2951 // Set up a copy of the stack pointer for use loading and storing any
2952 // arguments that may not fit in the registers available for argument
2954 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2956 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2957 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2958 SmallVector<SDValue, 8> MemOpChains;
2960 bool seenFloatArg = false;
2961 // Walk the register/memloc assignments, inserting copies/loads.
2962 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2965 CCValAssign &VA = ArgLocs[i];
2966 SDValue Arg = OutVals[i];
2967 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2969 if (Flags.isByVal()) {
2970 // Argument is an aggregate which is passed by value, thus we need to
2971 // create a copy of it in the local variable space of the current stack
2972 // frame (which is the stack frame of the caller) and pass the address of
2973 // this copy to the callee.
2974 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2975 CCValAssign &ByValVA = ByValArgLocs[j++];
2976 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2978 // Memory reserved in the local variable space of the callers stack frame.
2979 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2981 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2982 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2984 // Create a copy of the argument in the local area of the current
2986 SDValue MemcpyCall =
2987 CreateCopyOfByValArgument(Arg, PtrOff,
2988 CallSeqStart.getNode()->getOperand(0),
2991 // This must go outside the CALLSEQ_START..END.
2992 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2993 CallSeqStart.getNode()->getOperand(1));
2994 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2995 NewCallSeqStart.getNode());
2996 Chain = CallSeqStart = NewCallSeqStart;
2998 // Pass the address of the aggregate copy on the stack either in a
2999 // physical register or in the parameter list area of the current stack
3000 // frame to the callee.
3004 if (VA.isRegLoc()) {
3005 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3006 // Put argument in a physical register.
3007 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3009 // Put argument in the parameter list area of the current stack frame.
3010 assert(VA.isMemLoc());
3011 unsigned LocMemOffset = VA.getLocMemOffset();
3014 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3015 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3017 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3018 MachinePointerInfo(),
3021 // Calculate and remember argument location.
3022 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3028 if (!MemOpChains.empty())
3029 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3030 &MemOpChains[0], MemOpChains.size());
3032 // Set CR6 to true if this is a vararg call with floating args passed in
3035 SDValue SetCR(DAG.getMachineNode(seenFloatArg ? PPC::CRSET : PPC::CRUNSET,
3037 RegsToPass.push_back(std::make_pair(unsigned(PPC::CR1EQ), SetCR));
3040 // Build a sequence of copy-to-reg nodes chained together with token chain
3041 // and flag operands which copy the outgoing args into the appropriate regs.
3043 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3044 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3045 RegsToPass[i].second, InFlag);
3046 InFlag = Chain.getValue(1);
3050 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3051 false, TailCallArguments);
3053 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3054 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3059 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
3060 CallingConv::ID CallConv, bool isVarArg,
3062 const SmallVectorImpl<ISD::OutputArg> &Outs,
3063 const SmallVectorImpl<SDValue> &OutVals,
3064 const SmallVectorImpl<ISD::InputArg> &Ins,
3065 DebugLoc dl, SelectionDAG &DAG,
3066 SmallVectorImpl<SDValue> &InVals) const {
3068 unsigned NumOps = Outs.size();
3070 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3071 bool isPPC64 = PtrVT == MVT::i64;
3072 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3074 MachineFunction &MF = DAG.getMachineFunction();
3076 // Mark this function as potentially containing a function that contains a
3077 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3078 // and restoring the callers stack pointer in this functions epilog. This is
3079 // done because by tail calling the called function might overwrite the value
3080 // in this function's (MF) stack pointer stack slot 0(SP).
3081 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
3082 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3084 unsigned nAltivecParamsAtEnd = 0;
3086 // Count how many bytes are to be pushed on the stack, including the linkage
3087 // area, and parameter passing area. We start with 24/48 bytes, which is
3088 // prereserved space for [SP][CR][LR][3 x unused].
3090 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
3092 nAltivecParamsAtEnd);
3094 // Calculate by how many bytes the stack has to be adjusted in case of tail
3095 // call optimization.
3096 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3098 // To protect arguments on the stack from being clobbered in a tail call,
3099 // force all the loads to happen before doing any other lowering.
3101 Chain = DAG.getStackArgumentTokenFactor(Chain);
3103 // Adjust the stack pointer for the new arguments...
3104 // These operations are automatically eliminated by the prolog/epilog pass
3105 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
3106 SDValue CallSeqStart = Chain;
3108 // Load the return address and frame pointer so it can be move somewhere else
3111 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
3114 // Set up a copy of the stack pointer for use loading and storing any
3115 // arguments that may not fit in the registers available for argument
3119 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3121 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3123 // Figure out which arguments are going to go in registers, and which in
3124 // memory. Also, if this is a vararg function, floating point operations
3125 // must be stored to our stack, and loaded into integer regs as well, if
3126 // any integer regs are available for argument passing.
3127 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
3128 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3130 static const unsigned GPR_32[] = { // 32-bit registers.
3131 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3132 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3134 static const unsigned GPR_64[] = { // 64-bit registers.
3135 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3136 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3138 static const unsigned *FPR = GetFPR();
3140 static const unsigned VR[] = {
3141 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3142 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3144 const unsigned NumGPRs = array_lengthof(GPR_32);
3145 const unsigned NumFPRs = 13;
3146 const unsigned NumVRs = array_lengthof(VR);
3148 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3150 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3151 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3153 SmallVector<SDValue, 8> MemOpChains;
3154 for (unsigned i = 0; i != NumOps; ++i) {
3155 SDValue Arg = OutVals[i];
3156 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3158 // PtrOff will be used to store the current argument to the stack if a
3159 // register cannot be found for it.
3162 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3164 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3166 // On PPC64, promote integers to 64-bit values.
3167 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3168 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3169 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3170 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3173 // FIXME memcpy is used way more than necessary. Correctness first.
3174 if (Flags.isByVal()) {
3175 unsigned Size = Flags.getByValSize();
3176 if (Size==1 || Size==2) {
3177 // Very small objects are passed right-justified.
3178 // Everything else is passed left-justified.
3179 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3180 if (GPR_idx != NumGPRs) {
3181 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
3182 MachinePointerInfo(), VT,
3184 MemOpChains.push_back(Load.getValue(1));
3185 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3187 ArgOffset += PtrByteSize;
3189 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3190 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3191 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3192 CallSeqStart.getNode()->getOperand(0),
3194 // This must go outside the CALLSEQ_START..END.
3195 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3196 CallSeqStart.getNode()->getOperand(1));
3197 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3198 NewCallSeqStart.getNode());
3199 Chain = CallSeqStart = NewCallSeqStart;
3200 ArgOffset += PtrByteSize;
3204 // Copy entire object into memory. There are cases where gcc-generated
3205 // code assumes it is there, even if it could be put entirely into
3206 // registers. (This is not what the doc says.)
3207 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3208 CallSeqStart.getNode()->getOperand(0),
3210 // This must go outside the CALLSEQ_START..END.
3211 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3212 CallSeqStart.getNode()->getOperand(1));
3213 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3214 Chain = CallSeqStart = NewCallSeqStart;
3215 // And copy the pieces of it that fit into registers.
3216 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3217 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3218 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3219 if (GPR_idx != NumGPRs) {
3220 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
3221 MachinePointerInfo(),
3223 MemOpChains.push_back(Load.getValue(1));
3224 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3225 ArgOffset += PtrByteSize;
3227 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3234 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3235 default: llvm_unreachable("Unexpected ValueType for argument!");
3238 if (GPR_idx != NumGPRs) {
3239 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3241 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3242 isPPC64, isTailCall, false, MemOpChains,
3243 TailCallArguments, dl);
3245 ArgOffset += PtrByteSize;
3249 if (FPR_idx != NumFPRs) {
3250 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3253 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3254 MachinePointerInfo(), false, false, 0);
3255 MemOpChains.push_back(Store);
3257 // Float varargs are always shadowed in available integer registers
3258 if (GPR_idx != NumGPRs) {
3259 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3260 MachinePointerInfo(), false, false, 0);
3261 MemOpChains.push_back(Load.getValue(1));
3262 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3264 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3265 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3266 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3267 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
3268 MachinePointerInfo(),
3270 MemOpChains.push_back(Load.getValue(1));
3271 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3274 // If we have any FPRs remaining, we may also have GPRs remaining.
3275 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3277 if (GPR_idx != NumGPRs)
3279 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3280 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3284 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3285 isPPC64, isTailCall, false, MemOpChains,
3286 TailCallArguments, dl);
3291 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3298 // These go aligned on the stack, or in the corresponding R registers
3299 // when within range. The Darwin PPC ABI doc claims they also go in
3300 // V registers; in fact gcc does this only for arguments that are
3301 // prototyped, not for those that match the ... We do it for all
3302 // arguments, seems to work.
3303 while (ArgOffset % 16 !=0) {
3304 ArgOffset += PtrByteSize;
3305 if (GPR_idx != NumGPRs)
3308 // We could elide this store in the case where the object fits
3309 // entirely in R registers. Maybe later.
3310 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3311 DAG.getConstant(ArgOffset, PtrVT));
3312 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
3313 MachinePointerInfo(), false, false, 0);
3314 MemOpChains.push_back(Store);
3315 if (VR_idx != NumVRs) {
3316 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
3317 MachinePointerInfo(),
3319 MemOpChains.push_back(Load.getValue(1));
3320 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3323 for (unsigned i=0; i<16; i+=PtrByteSize) {
3324 if (GPR_idx == NumGPRs)
3326 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3327 DAG.getConstant(i, PtrVT));
3328 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
3330 MemOpChains.push_back(Load.getValue(1));
3331 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3336 // Non-varargs Altivec params generally go in registers, but have
3337 // stack space allocated at the end.
3338 if (VR_idx != NumVRs) {
3339 // Doesn't have GPR space allocated.
3340 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3341 } else if (nAltivecParamsAtEnd==0) {
3342 // We are emitting Altivec params in order.
3343 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3344 isPPC64, isTailCall, true, MemOpChains,
3345 TailCallArguments, dl);
3351 // If all Altivec parameters fit in registers, as they usually do,
3352 // they get stack space following the non-Altivec parameters. We
3353 // don't track this here because nobody below needs it.
3354 // If there are more Altivec parameters than fit in registers emit
3356 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3358 // Offset is aligned; skip 1st 12 params which go in V registers.
3359 ArgOffset = ((ArgOffset+15)/16)*16;
3361 for (unsigned i = 0; i != NumOps; ++i) {
3362 SDValue Arg = OutVals[i];
3363 EVT ArgType = Outs[i].VT;
3364 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3365 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3368 // We are emitting Altivec params in order.
3369 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3370 isPPC64, isTailCall, true, MemOpChains,
3371 TailCallArguments, dl);
3378 if (!MemOpChains.empty())
3379 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3380 &MemOpChains[0], MemOpChains.size());
3382 // Check if this is an indirect call (MTCTR/BCTRL).
3383 // See PrepareCall() for more information about calls through function
3384 // pointers in the 64-bit SVR4 ABI.
3385 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3386 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3387 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3388 !isBLACompatibleAddress(Callee, DAG)) {
3389 // Load r2 into a virtual register and store it to the TOC save area.
3390 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3391 // TOC save area offset.
3392 SDValue PtrOff = DAG.getIntPtrConstant(40);
3393 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3394 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
3398 // On Darwin, R12 must contain the address of an indirect callee. This does
3399 // not mean the MTCTR instruction must use R12; it's easier to model this as
3400 // an extra parameter, so do that.
3402 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3403 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3404 !isBLACompatibleAddress(Callee, DAG))
3405 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3406 PPC::R12), Callee));
3408 // Build a sequence of copy-to-reg nodes chained together with token chain
3409 // and flag operands which copy the outgoing args into the appropriate regs.
3411 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3412 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3413 RegsToPass[i].second, InFlag);
3414 InFlag = Chain.getValue(1);
3418 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3419 FPOp, true, TailCallArguments);
3421 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3422 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3427 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
3428 MachineFunction &MF, bool isVarArg,
3429 const SmallVectorImpl<ISD::OutputArg> &Outs,
3430 LLVMContext &Context) const {
3431 SmallVector<CCValAssign, 16> RVLocs;
3432 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
3434 return CCInfo.CheckReturn(Outs, RetCC_PPC);
3438 PPCTargetLowering::LowerReturn(SDValue Chain,
3439 CallingConv::ID CallConv, bool isVarArg,
3440 const SmallVectorImpl<ISD::OutputArg> &Outs,
3441 const SmallVectorImpl<SDValue> &OutVals,
3442 DebugLoc dl, SelectionDAG &DAG) const {
3444 SmallVector<CCValAssign, 16> RVLocs;
3445 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3446 getTargetMachine(), RVLocs, *DAG.getContext());
3447 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3449 // If this is the first return lowered for this function, add the regs to the
3450 // liveout set for the function.
3451 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3452 for (unsigned i = 0; i != RVLocs.size(); ++i)
3453 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3458 // Copy the result values into the output registers.
3459 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3460 CCValAssign &VA = RVLocs[i];
3461 assert(VA.isRegLoc() && "Can only return in registers!");
3462 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3464 Flag = Chain.getValue(1);
3468 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3470 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3473 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3474 const PPCSubtarget &Subtarget) const {
3475 // When we pop the dynamic allocation we need to restore the SP link.
3476 DebugLoc dl = Op.getDebugLoc();
3478 // Get the corect type for pointers.
3479 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3481 // Construct the stack pointer operand.
3482 bool isPPC64 = Subtarget.isPPC64();
3483 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3484 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3486 // Get the operands for the STACKRESTORE.
3487 SDValue Chain = Op.getOperand(0);
3488 SDValue SaveSP = Op.getOperand(1);
3490 // Load the old link SP.
3491 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
3492 MachinePointerInfo(),
3495 // Restore the stack pointer.
3496 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3498 // Store the old link SP.
3499 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
3506 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3507 MachineFunction &MF = DAG.getMachineFunction();
3508 bool isPPC64 = PPCSubTarget.isPPC64();
3509 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3510 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3512 // Get current frame pointer save index. The users of this index will be
3513 // primarily DYNALLOC instructions.
3514 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3515 int RASI = FI->getReturnAddrSaveIndex();
3517 // If the frame pointer save index hasn't been defined yet.
3519 // Find out what the fix offset of the frame pointer save area.
3520 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
3521 // Allocate the frame index for frame pointer save area.
3522 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3524 FI->setReturnAddrSaveIndex(RASI);
3526 return DAG.getFrameIndex(RASI, PtrVT);
3530 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3531 MachineFunction &MF = DAG.getMachineFunction();
3532 bool isPPC64 = PPCSubTarget.isPPC64();
3533 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3534 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3536 // Get current frame pointer save index. The users of this index will be
3537 // primarily DYNALLOC instructions.
3538 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3539 int FPSI = FI->getFramePointerSaveIndex();
3541 // If the frame pointer save index hasn't been defined yet.
3543 // Find out what the fix offset of the frame pointer save area.
3544 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
3547 // Allocate the frame index for frame pointer save area.
3548 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3550 FI->setFramePointerSaveIndex(FPSI);
3552 return DAG.getFrameIndex(FPSI, PtrVT);
3555 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3557 const PPCSubtarget &Subtarget) const {
3559 SDValue Chain = Op.getOperand(0);
3560 SDValue Size = Op.getOperand(1);
3561 DebugLoc dl = Op.getDebugLoc();
3563 // Get the corect type for pointers.
3564 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3566 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3567 DAG.getConstant(0, PtrVT), Size);
3568 // Construct a node for the frame pointer save index.
3569 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3570 // Build a DYNALLOC node.
3571 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3572 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3573 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3576 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3578 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3579 // Not FP? Not a fsel.
3580 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3581 !Op.getOperand(2).getValueType().isFloatingPoint())
3584 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3586 // Cannot handle SETEQ/SETNE.
3587 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3589 EVT ResVT = Op.getValueType();
3590 EVT CmpVT = Op.getOperand(0).getValueType();
3591 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3592 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3593 DebugLoc dl = Op.getDebugLoc();
3595 // If the RHS of the comparison is a 0.0, we don't need to do the
3596 // subtraction at all.
3597 if (isFloatingPointZero(RHS))
3599 default: break; // SETUO etc aren't handled by fsel.
3602 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3605 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3606 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3607 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3610 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3613 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3614 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3615 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3616 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3621 default: break; // SETUO etc aren't handled by fsel.
3624 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3625 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3626 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3627 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3630 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3631 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3632 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3633 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3636 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3637 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3638 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3639 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3642 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3643 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3644 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3645 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3650 // FIXME: Split this code up when LegalizeDAGTypes lands.
3651 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3652 DebugLoc dl) const {
3653 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3654 SDValue Src = Op.getOperand(0);
3655 if (Src.getValueType() == MVT::f32)
3656 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3659 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3660 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3662 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3667 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3671 // Convert the FP value to an int value through memory.
3672 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3674 // Emit a store to the stack slot.
3675 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
3676 MachinePointerInfo(), false, false, 0);
3678 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3680 if (Op.getValueType() == MVT::i32)
3681 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3682 DAG.getConstant(4, FIPtr.getValueType()));
3683 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MachinePointerInfo(),
3687 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3688 SelectionDAG &DAG) const {
3689 DebugLoc dl = Op.getDebugLoc();
3690 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3691 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3694 if (Op.getOperand(0).getValueType() == MVT::i64) {
3695 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Op.getOperand(0));
3696 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3697 if (Op.getValueType() == MVT::f32)
3698 FP = DAG.getNode(ISD::FP_ROUND, dl,
3699 MVT::f32, FP, DAG.getIntPtrConstant(0));
3703 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3704 "Unhandled SINT_TO_FP type in custom expander!");
3705 // Since we only generate this in 64-bit mode, we can take advantage of
3706 // 64-bit registers. In particular, sign extend the input value into the
3707 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3708 // then lfd it and fcfid it.
3709 MachineFunction &MF = DAG.getMachineFunction();
3710 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3711 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3712 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3713 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3715 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3718 // STD the extended value into the stack slot.
3719 MachineMemOperand *MMO =
3720 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
3721 MachineMemOperand::MOStore, 8, 8);
3722 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3724 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3725 Ops, 4, MVT::i64, MMO);
3726 // Load the value as a double.
3727 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, MachinePointerInfo(),
3730 // FCFID it and return it.
3731 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3732 if (Op.getValueType() == MVT::f32)
3733 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3737 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3738 SelectionDAG &DAG) const {
3739 DebugLoc dl = Op.getDebugLoc();
3741 The rounding mode is in bits 30:31 of FPSR, and has the following
3748 FLT_ROUNDS, on the other hand, expects the following:
3755 To perform the conversion, we do:
3756 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3759 MachineFunction &MF = DAG.getMachineFunction();
3760 EVT VT = Op.getValueType();
3761 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3762 std::vector<EVT> NodeTys;
3763 SDValue MFFSreg, InFlag;
3765 // Save FP Control Word to register
3766 NodeTys.push_back(MVT::f64); // return register
3767 NodeTys.push_back(MVT::Glue); // unused in this context
3768 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3770 // Save FP register to stack slot
3771 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3772 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3773 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3774 StackSlot, MachinePointerInfo(), false, false,0);
3776 // Load FP Control Word from low 32 bits of stack slot.
3777 SDValue Four = DAG.getConstant(4, PtrVT);
3778 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3779 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
3782 // Transform as necessary
3784 DAG.getNode(ISD::AND, dl, MVT::i32,
3785 CWD, DAG.getConstant(3, MVT::i32));
3787 DAG.getNode(ISD::SRL, dl, MVT::i32,
3788 DAG.getNode(ISD::AND, dl, MVT::i32,
3789 DAG.getNode(ISD::XOR, dl, MVT::i32,
3790 CWD, DAG.getConstant(3, MVT::i32)),
3791 DAG.getConstant(3, MVT::i32)),
3792 DAG.getConstant(1, MVT::i32));
3795 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3797 return DAG.getNode((VT.getSizeInBits() < 16 ?
3798 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3801 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3802 EVT VT = Op.getValueType();
3803 unsigned BitWidth = VT.getSizeInBits();
3804 DebugLoc dl = Op.getDebugLoc();
3805 assert(Op.getNumOperands() == 3 &&
3806 VT == Op.getOperand(1).getValueType() &&
3809 // Expand into a bunch of logical ops. Note that these ops
3810 // depend on the PPC behavior for oversized shift amounts.
3811 SDValue Lo = Op.getOperand(0);
3812 SDValue Hi = Op.getOperand(1);
3813 SDValue Amt = Op.getOperand(2);
3814 EVT AmtVT = Amt.getValueType();
3816 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3817 DAG.getConstant(BitWidth, AmtVT), Amt);
3818 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3819 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3820 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3821 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3822 DAG.getConstant(-BitWidth, AmtVT));
3823 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3824 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3825 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3826 SDValue OutOps[] = { OutLo, OutHi };
3827 return DAG.getMergeValues(OutOps, 2, dl);
3830 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3831 EVT VT = Op.getValueType();
3832 DebugLoc dl = Op.getDebugLoc();
3833 unsigned BitWidth = VT.getSizeInBits();
3834 assert(Op.getNumOperands() == 3 &&
3835 VT == Op.getOperand(1).getValueType() &&
3838 // Expand into a bunch of logical ops. Note that these ops
3839 // depend on the PPC behavior for oversized shift amounts.
3840 SDValue Lo = Op.getOperand(0);
3841 SDValue Hi = Op.getOperand(1);
3842 SDValue Amt = Op.getOperand(2);
3843 EVT AmtVT = Amt.getValueType();
3845 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3846 DAG.getConstant(BitWidth, AmtVT), Amt);
3847 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3848 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3849 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3850 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3851 DAG.getConstant(-BitWidth, AmtVT));
3852 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3853 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3854 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3855 SDValue OutOps[] = { OutLo, OutHi };
3856 return DAG.getMergeValues(OutOps, 2, dl);
3859 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3860 DebugLoc dl = Op.getDebugLoc();
3861 EVT VT = Op.getValueType();
3862 unsigned BitWidth = VT.getSizeInBits();
3863 assert(Op.getNumOperands() == 3 &&
3864 VT == Op.getOperand(1).getValueType() &&
3867 // Expand into a bunch of logical ops, followed by a select_cc.
3868 SDValue Lo = Op.getOperand(0);
3869 SDValue Hi = Op.getOperand(1);
3870 SDValue Amt = Op.getOperand(2);
3871 EVT AmtVT = Amt.getValueType();
3873 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3874 DAG.getConstant(BitWidth, AmtVT), Amt);
3875 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3876 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3877 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3878 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3879 DAG.getConstant(-BitWidth, AmtVT));
3880 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3881 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3882 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3883 Tmp4, Tmp6, ISD::SETLE);
3884 SDValue OutOps[] = { OutLo, OutHi };
3885 return DAG.getMergeValues(OutOps, 2, dl);
3888 //===----------------------------------------------------------------------===//
3889 // Vector related lowering.
3892 /// BuildSplatI - Build a canonical splati of Val with an element size of
3893 /// SplatSize. Cast the result to VT.
3894 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3895 SelectionDAG &DAG, DebugLoc dl) {
3896 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3898 static const EVT VTys[] = { // canonical VT to use for each size.
3899 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3902 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3904 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3908 EVT CanonicalVT = VTys[SplatSize-1];
3910 // Build a canonical splat for this value.
3911 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3912 SmallVector<SDValue, 8> Ops;
3913 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3914 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3915 &Ops[0], Ops.size());
3916 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
3919 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3920 /// specified intrinsic ID.
3921 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3922 SelectionDAG &DAG, DebugLoc dl,
3923 EVT DestVT = MVT::Other) {
3924 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3925 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3926 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3929 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3930 /// specified intrinsic ID.
3931 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3932 SDValue Op2, SelectionDAG &DAG,
3933 DebugLoc dl, EVT DestVT = MVT::Other) {
3934 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3935 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3936 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3940 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3941 /// amount. The result has the specified value type.
3942 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3943 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3944 // Force LHS/RHS to be the right type.
3945 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
3946 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
3949 for (unsigned i = 0; i != 16; ++i)
3951 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3952 return DAG.getNode(ISD::BITCAST, dl, VT, T);
3955 // If this is a case we can't handle, return null and let the default
3956 // expansion code take care of it. If we CAN select this case, and if it
3957 // selects to a single instruction, return Op. Otherwise, if we can codegen
3958 // this case more efficiently than a constant pool load, lower it to the
3959 // sequence of ops that should be used.
3960 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3961 SelectionDAG &DAG) const {
3962 DebugLoc dl = Op.getDebugLoc();
3963 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3964 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3966 // Check if this is a splat of a constant value.
3967 APInt APSplatBits, APSplatUndef;
3968 unsigned SplatBitSize;
3970 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3971 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3974 unsigned SplatBits = APSplatBits.getZExtValue();
3975 unsigned SplatUndef = APSplatUndef.getZExtValue();
3976 unsigned SplatSize = SplatBitSize / 8;
3978 // First, handle single instruction cases.
3981 if (SplatBits == 0) {
3982 // Canonicalize all zero vectors to be v4i32.
3983 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3984 SDValue Z = DAG.getConstant(0, MVT::i32);
3985 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3986 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
3991 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3992 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3994 if (SextVal >= -16 && SextVal <= 15)
3995 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3998 // Two instruction sequences.
4000 // If this value is in the range [-32,30] and is even, use:
4001 // tmp = VSPLTI[bhw], result = add tmp, tmp
4002 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
4003 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
4004 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
4005 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4008 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
4009 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
4011 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
4012 // Make -1 and vspltisw -1:
4013 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
4015 // Make the VSLW intrinsic, computing 0x8000_0000.
4016 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
4019 // xor by OnesV to invert it.
4020 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
4021 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4024 // Check to see if this is a wide variety of vsplti*, binop self cases.
4025 static const signed char SplatCsts[] = {
4026 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
4027 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
4030 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
4031 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
4032 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
4033 int i = SplatCsts[idx];
4035 // Figure out what shift amount will be used by altivec if shifted by i in
4037 unsigned TypeShiftAmt = i & (SplatBitSize-1);
4039 // vsplti + shl self.
4040 if (SextVal == (i << (int)TypeShiftAmt)) {
4041 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4042 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4043 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
4044 Intrinsic::ppc_altivec_vslw
4046 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4047 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4050 // vsplti + srl self.
4051 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4052 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4053 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4054 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
4055 Intrinsic::ppc_altivec_vsrw
4057 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4058 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4061 // vsplti + sra self.
4062 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
4063 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4064 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4065 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
4066 Intrinsic::ppc_altivec_vsraw
4068 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4069 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4072 // vsplti + rol self.
4073 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
4074 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
4075 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
4076 static const unsigned IIDs[] = { // Intrinsic to use for each size.
4077 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
4078 Intrinsic::ppc_altivec_vrlw
4080 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
4081 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
4084 // t = vsplti c, result = vsldoi t, t, 1
4085 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
4086 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4087 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
4089 // t = vsplti c, result = vsldoi t, t, 2
4090 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
4091 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4092 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
4094 // t = vsplti c, result = vsldoi t, t, 3
4095 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
4096 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
4097 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
4101 // Three instruction sequences.
4103 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
4104 if (SextVal >= 0 && SextVal <= 31) {
4105 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
4106 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4107 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
4108 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4110 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
4111 if (SextVal >= -31 && SextVal <= 0) {
4112 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
4113 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
4114 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
4115 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), LHS);
4121 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
4122 /// the specified operations to build the shuffle.
4123 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
4124 SDValue RHS, SelectionDAG &DAG,
4126 unsigned OpNum = (PFEntry >> 26) & 0x0F;
4127 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
4128 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
4131 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4143 if (OpNum == OP_COPY) {
4144 if (LHSID == (1*9+2)*9+3) return LHS;
4145 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4149 SDValue OpLHS, OpRHS;
4150 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4151 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4155 default: llvm_unreachable("Unknown i32 permute!");
4157 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4158 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4159 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4160 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4163 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4164 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4165 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4166 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4169 for (unsigned i = 0; i != 16; ++i)
4170 ShufIdxs[i] = (i&3)+0;
4173 for (unsigned i = 0; i != 16; ++i)
4174 ShufIdxs[i] = (i&3)+4;
4177 for (unsigned i = 0; i != 16; ++i)
4178 ShufIdxs[i] = (i&3)+8;
4181 for (unsigned i = 0; i != 16; ++i)
4182 ShufIdxs[i] = (i&3)+12;
4185 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4187 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4189 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4191 EVT VT = OpLHS.getValueType();
4192 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
4193 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
4194 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4195 return DAG.getNode(ISD::BITCAST, dl, VT, T);
4198 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4199 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4200 /// return the code it can be lowered into. Worst case, it can always be
4201 /// lowered into a vperm.
4202 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4203 SelectionDAG &DAG) const {
4204 DebugLoc dl = Op.getDebugLoc();
4205 SDValue V1 = Op.getOperand(0);
4206 SDValue V2 = Op.getOperand(1);
4207 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4208 EVT VT = Op.getValueType();
4210 // Cases that are handled by instructions that take permute immediates
4211 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4212 // selected by the instruction selector.
4213 if (V2.getOpcode() == ISD::UNDEF) {
4214 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4215 PPC::isSplatShuffleMask(SVOp, 2) ||
4216 PPC::isSplatShuffleMask(SVOp, 4) ||
4217 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4218 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4219 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4220 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4221 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4222 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4223 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4224 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4225 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4230 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4231 // and produce a fixed permutation. If any of these match, do not lower to
4233 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4234 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4235 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4236 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4237 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4238 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4239 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4240 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4241 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4244 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4245 // perfect shuffle table to emit an optimal matching sequence.
4246 SmallVector<int, 16> PermMask;
4247 SVOp->getMask(PermMask);
4249 unsigned PFIndexes[4];
4250 bool isFourElementShuffle = true;
4251 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4252 unsigned EltNo = 8; // Start out undef.
4253 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4254 if (PermMask[i*4+j] < 0)
4255 continue; // Undef, ignore it.
4257 unsigned ByteSource = PermMask[i*4+j];
4258 if ((ByteSource & 3) != j) {
4259 isFourElementShuffle = false;
4264 EltNo = ByteSource/4;
4265 } else if (EltNo != ByteSource/4) {
4266 isFourElementShuffle = false;
4270 PFIndexes[i] = EltNo;
4273 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4274 // perfect shuffle vector to determine if it is cost effective to do this as
4275 // discrete instructions, or whether we should use a vperm.
4276 if (isFourElementShuffle) {
4277 // Compute the index in the perfect shuffle table.
4278 unsigned PFTableIndex =
4279 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4281 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4282 unsigned Cost = (PFEntry >> 30);
4284 // Determining when to avoid vperm is tricky. Many things affect the cost
4285 // of vperm, particularly how many times the perm mask needs to be computed.
4286 // For example, if the perm mask can be hoisted out of a loop or is already
4287 // used (perhaps because there are multiple permutes with the same shuffle
4288 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4289 // the loop requires an extra register.
4291 // As a compromise, we only emit discrete instructions if the shuffle can be
4292 // generated in 3 or fewer operations. When we have loop information
4293 // available, if this block is within a loop, we should avoid using vperm
4294 // for 3-operation perms and use a constant pool load instead.
4296 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4299 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4300 // vector that will get spilled to the constant pool.
4301 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4303 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4304 // that it is in input element units, not in bytes. Convert now.
4305 EVT EltVT = V1.getValueType().getVectorElementType();
4306 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4308 SmallVector<SDValue, 16> ResultMask;
4309 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4310 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4312 for (unsigned j = 0; j != BytesPerElement; ++j)
4313 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4317 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4318 &ResultMask[0], ResultMask.size());
4319 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4322 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4323 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4324 /// information about the intrinsic.
4325 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4327 unsigned IntrinsicID =
4328 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4331 switch (IntrinsicID) {
4332 default: return false;
4333 // Comparison predicates.
4334 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4335 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4336 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4337 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4338 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4339 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4340 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4341 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4342 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4343 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4344 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4345 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4346 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4348 // Normal Comparisons.
4349 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4350 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4351 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4352 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4353 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4354 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4355 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4356 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4357 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4358 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4359 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4360 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4361 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4366 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4367 /// lower, do it, otherwise return null.
4368 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4369 SelectionDAG &DAG) const {
4370 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4371 // opcode number of the comparison.
4372 DebugLoc dl = Op.getDebugLoc();
4375 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4376 return SDValue(); // Don't custom lower most intrinsics.
4378 // If this is a non-dot comparison, make the VCMP node and we are done.
4380 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4381 Op.getOperand(1), Op.getOperand(2),
4382 DAG.getConstant(CompareOpc, MVT::i32));
4383 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
4386 // Create the PPCISD altivec 'dot' comparison node.
4388 Op.getOperand(2), // LHS
4389 Op.getOperand(3), // RHS
4390 DAG.getConstant(CompareOpc, MVT::i32)
4392 std::vector<EVT> VTs;
4393 VTs.push_back(Op.getOperand(2).getValueType());
4394 VTs.push_back(MVT::Glue);
4395 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4397 // Now that we have the comparison, emit a copy from the CR to a GPR.
4398 // This is flagged to the above dot comparison.
4399 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4400 DAG.getRegister(PPC::CR6, MVT::i32),
4401 CompNode.getValue(1));
4403 // Unpack the result based on how the target uses it.
4404 unsigned BitNo; // Bit # of CR6.
4405 bool InvertBit; // Invert result?
4406 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4407 default: // Can't happen, don't crash on invalid number though.
4408 case 0: // Return the value of the EQ bit of CR6.
4409 BitNo = 0; InvertBit = false;
4411 case 1: // Return the inverted value of the EQ bit of CR6.
4412 BitNo = 0; InvertBit = true;
4414 case 2: // Return the value of the LT bit of CR6.
4415 BitNo = 2; InvertBit = false;
4417 case 3: // Return the inverted value of the LT bit of CR6.
4418 BitNo = 2; InvertBit = true;
4422 // Shift the bit into the low position.
4423 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4424 DAG.getConstant(8-(3-BitNo), MVT::i32));
4426 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4427 DAG.getConstant(1, MVT::i32));
4429 // If we are supposed to, toggle the bit.
4431 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4432 DAG.getConstant(1, MVT::i32));
4436 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4437 SelectionDAG &DAG) const {
4438 DebugLoc dl = Op.getDebugLoc();
4439 // Create a stack slot that is 16-byte aligned.
4440 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4441 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4442 EVT PtrVT = getPointerTy();
4443 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4445 // Store the input value into Value#0 of the stack slot.
4446 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4447 Op.getOperand(0), FIdx, MachinePointerInfo(),
4450 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
4454 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4455 DebugLoc dl = Op.getDebugLoc();
4456 if (Op.getValueType() == MVT::v4i32) {
4457 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4459 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4460 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4462 SDValue RHSSwap = // = vrlw RHS, 16
4463 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4465 // Shrinkify inputs to v8i16.
4466 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
4467 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
4468 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
4470 // Low parts multiplied together, generating 32-bit results (we ignore the
4472 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4473 LHS, RHS, DAG, dl, MVT::v4i32);
4475 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4476 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4477 // Shift the high parts up 16 bits.
4478 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4480 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4481 } else if (Op.getValueType() == MVT::v8i16) {
4482 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4484 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4486 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4487 LHS, RHS, Zero, DAG, dl);
4488 } else if (Op.getValueType() == MVT::v16i8) {
4489 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4491 // Multiply the even 8-bit parts, producing 16-bit sums.
4492 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4493 LHS, RHS, DAG, dl, MVT::v8i16);
4494 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
4496 // Multiply the odd 8-bit parts, producing 16-bit sums.
4497 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4498 LHS, RHS, DAG, dl, MVT::v8i16);
4499 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
4501 // Merge the results together.
4503 for (unsigned i = 0; i != 8; ++i) {
4505 Ops[i*2+1] = 2*i+1+16;
4507 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4509 llvm_unreachable("Unknown mul to lower!");
4513 /// LowerOperation - Provide custom lowering hooks for some operations.
4515 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4516 switch (Op.getOpcode()) {
4517 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4518 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4519 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4520 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4521 case ISD::GlobalTLSAddress: llvm_unreachable("TLS not implemented for PPC");
4522 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4523 case ISD::SETCC: return LowerSETCC(Op, DAG);
4524 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
4525 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
4527 return LowerVASTART(Op, DAG, PPCSubTarget);
4530 return LowerVAARG(Op, DAG, PPCSubTarget);
4532 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4533 case ISD::DYNAMIC_STACKALLOC:
4534 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4536 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4537 case ISD::FP_TO_UINT:
4538 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4540 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4541 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4543 // Lower 64-bit shifts.
4544 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4545 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4546 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4548 // Vector-related lowering.
4549 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4550 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4551 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4552 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4553 case ISD::MUL: return LowerMUL(Op, DAG);
4555 // Frame & Return address.
4556 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4557 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4562 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4563 SmallVectorImpl<SDValue>&Results,
4564 SelectionDAG &DAG) const {
4565 const TargetMachine &TM = getTargetMachine();
4566 DebugLoc dl = N->getDebugLoc();
4567 switch (N->getOpcode()) {
4569 assert(false && "Do not know how to custom type legalize this operation!");
4572 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
4573 || TM.getSubtarget<PPCSubtarget>().isPPC64())
4576 EVT VT = N->getValueType(0);
4578 if (VT == MVT::i64) {
4579 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, PPCSubTarget);
4581 Results.push_back(NewNode);
4582 Results.push_back(NewNode.getValue(1));
4586 case ISD::FP_ROUND_INREG: {
4587 assert(N->getValueType(0) == MVT::ppcf128);
4588 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4589 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4590 MVT::f64, N->getOperand(0),
4591 DAG.getIntPtrConstant(0));
4592 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4593 MVT::f64, N->getOperand(0),
4594 DAG.getIntPtrConstant(1));
4596 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4597 // of the long double, and puts FPSCR back the way it was. We do not
4598 // actually model FPSCR.
4599 std::vector<EVT> NodeTys;
4600 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4602 NodeTys.push_back(MVT::f64); // Return register
4603 NodeTys.push_back(MVT::Glue); // Returns a flag for later insns
4604 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4605 MFFSreg = Result.getValue(0);
4606 InFlag = Result.getValue(1);
4609 NodeTys.push_back(MVT::Glue); // Returns a flag
4610 Ops[0] = DAG.getConstant(31, MVT::i32);
4612 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4613 InFlag = Result.getValue(0);
4616 NodeTys.push_back(MVT::Glue); // Returns a flag
4617 Ops[0] = DAG.getConstant(30, MVT::i32);
4619 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4620 InFlag = Result.getValue(0);
4623 NodeTys.push_back(MVT::f64); // result of add
4624 NodeTys.push_back(MVT::Glue); // Returns a flag
4628 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4629 FPreg = Result.getValue(0);
4630 InFlag = Result.getValue(1);
4633 NodeTys.push_back(MVT::f64);
4634 Ops[0] = DAG.getConstant(1, MVT::i32);
4638 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4639 FPreg = Result.getValue(0);
4641 // We know the low half is about to be thrown away, so just use something
4643 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4647 case ISD::FP_TO_SINT:
4648 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4654 //===----------------------------------------------------------------------===//
4655 // Other Lowering Code
4656 //===----------------------------------------------------------------------===//
4659 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4660 bool is64bit, unsigned BinOpcode) const {
4661 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4662 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4664 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4665 MachineFunction *F = BB->getParent();
4666 MachineFunction::iterator It = BB;
4669 unsigned dest = MI->getOperand(0).getReg();
4670 unsigned ptrA = MI->getOperand(1).getReg();
4671 unsigned ptrB = MI->getOperand(2).getReg();
4672 unsigned incr = MI->getOperand(3).getReg();
4673 DebugLoc dl = MI->getDebugLoc();
4675 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4676 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4677 F->insert(It, loopMBB);
4678 F->insert(It, exitMBB);
4679 exitMBB->splice(exitMBB->begin(), BB,
4680 llvm::next(MachineBasicBlock::iterator(MI)),
4682 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4684 MachineRegisterInfo &RegInfo = F->getRegInfo();
4685 unsigned TmpReg = (!BinOpcode) ? incr :
4686 RegInfo.createVirtualRegister(
4687 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4688 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4692 // fallthrough --> loopMBB
4693 BB->addSuccessor(loopMBB);
4696 // l[wd]arx dest, ptr
4697 // add r0, dest, incr
4698 // st[wd]cx. r0, ptr
4700 // fallthrough --> exitMBB
4702 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4703 .addReg(ptrA).addReg(ptrB);
4705 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4706 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4707 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4708 BuildMI(BB, dl, TII->get(PPC::BCC))
4709 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4710 BB->addSuccessor(loopMBB);
4711 BB->addSuccessor(exitMBB);
4720 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4721 MachineBasicBlock *BB,
4722 bool is8bit, // operation
4723 unsigned BinOpcode) const {
4724 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4725 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4726 // In 64 bit mode we have to use 64 bits for addresses, even though the
4727 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4728 // registers without caring whether they're 32 or 64, but here we're
4729 // doing actual arithmetic on the addresses.
4730 bool is64bit = PPCSubTarget.isPPC64();
4731 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
4733 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4734 MachineFunction *F = BB->getParent();
4735 MachineFunction::iterator It = BB;
4738 unsigned dest = MI->getOperand(0).getReg();
4739 unsigned ptrA = MI->getOperand(1).getReg();
4740 unsigned ptrB = MI->getOperand(2).getReg();
4741 unsigned incr = MI->getOperand(3).getReg();
4742 DebugLoc dl = MI->getDebugLoc();
4744 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4745 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4746 F->insert(It, loopMBB);
4747 F->insert(It, exitMBB);
4748 exitMBB->splice(exitMBB->begin(), BB,
4749 llvm::next(MachineBasicBlock::iterator(MI)),
4751 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4753 MachineRegisterInfo &RegInfo = F->getRegInfo();
4754 const TargetRegisterClass *RC =
4755 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4756 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4757 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4758 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4759 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4760 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4761 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4762 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4763 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4764 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4765 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4766 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4767 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4769 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4773 // fallthrough --> loopMBB
4774 BB->addSuccessor(loopMBB);
4776 // The 4-byte load must be aligned, while a char or short may be
4777 // anywhere in the word. Hence all this nasty bookkeeping code.
4778 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4779 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4780 // xori shift, shift1, 24 [16]
4781 // rlwinm ptr, ptr1, 0, 0, 29
4782 // slw incr2, incr, shift
4783 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4784 // slw mask, mask2, shift
4786 // lwarx tmpDest, ptr
4787 // add tmp, tmpDest, incr2
4788 // andc tmp2, tmpDest, mask
4789 // and tmp3, tmp, mask
4790 // or tmp4, tmp3, tmp2
4793 // fallthrough --> exitMBB
4794 // srw dest, tmpDest, shift
4795 if (ptrA != ZeroReg) {
4796 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4797 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4798 .addReg(ptrA).addReg(ptrB);
4802 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4803 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4804 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4805 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4807 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4808 .addReg(Ptr1Reg).addImm(0).addImm(61);
4810 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4811 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4812 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4813 .addReg(incr).addReg(ShiftReg);
4815 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4817 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4818 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4820 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4821 .addReg(Mask2Reg).addReg(ShiftReg);
4824 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4825 .addReg(ZeroReg).addReg(PtrReg);
4827 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4828 .addReg(Incr2Reg).addReg(TmpDestReg);
4829 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4830 .addReg(TmpDestReg).addReg(MaskReg);
4831 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4832 .addReg(TmpReg).addReg(MaskReg);
4833 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4834 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4835 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4836 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
4837 BuildMI(BB, dl, TII->get(PPC::BCC))
4838 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4839 BB->addSuccessor(loopMBB);
4840 BB->addSuccessor(exitMBB);
4845 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
4851 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4852 MachineBasicBlock *BB) const {
4853 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4855 // To "insert" these instructions we actually have to insert their
4856 // control-flow patterns.
4857 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4858 MachineFunction::iterator It = BB;
4861 MachineFunction *F = BB->getParent();
4863 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4864 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4865 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4866 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4867 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4869 // The incoming instruction knows the destination vreg to set, the
4870 // condition code register to branch on, the true/false values to
4871 // select between, and a branch opcode to use.
4876 // cmpTY ccX, r1, r2
4878 // fallthrough --> copy0MBB
4879 MachineBasicBlock *thisMBB = BB;
4880 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4881 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4882 unsigned SelectPred = MI->getOperand(4).getImm();
4883 DebugLoc dl = MI->getDebugLoc();
4884 F->insert(It, copy0MBB);
4885 F->insert(It, sinkMBB);
4887 // Transfer the remainder of BB and its successor edges to sinkMBB.
4888 sinkMBB->splice(sinkMBB->begin(), BB,
4889 llvm::next(MachineBasicBlock::iterator(MI)),
4891 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4893 // Next, add the true and fallthrough blocks as its successors.
4894 BB->addSuccessor(copy0MBB);
4895 BB->addSuccessor(sinkMBB);
4897 BuildMI(BB, dl, TII->get(PPC::BCC))
4898 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4901 // %FalseValue = ...
4902 // # fallthrough to sinkMBB
4905 // Update machine-CFG edges
4906 BB->addSuccessor(sinkMBB);
4909 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4912 BuildMI(*BB, BB->begin(), dl,
4913 TII->get(PPC::PHI), MI->getOperand(0).getReg())
4914 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4915 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4917 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4918 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4919 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4920 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4921 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4922 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4923 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4924 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4926 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4927 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4928 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4929 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4930 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4931 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4932 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4933 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4935 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4936 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4937 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4938 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4939 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4940 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4941 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4942 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4944 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4945 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4946 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4947 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4948 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4949 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4950 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4951 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4953 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4954 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4955 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4956 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4957 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4958 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4959 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4960 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4962 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4963 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4964 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4965 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4966 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4967 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4968 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4969 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4971 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4972 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4973 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4974 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4975 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4976 BB = EmitAtomicBinary(MI, BB, false, 0);
4977 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4978 BB = EmitAtomicBinary(MI, BB, true, 0);
4980 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4981 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4982 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4984 unsigned dest = MI->getOperand(0).getReg();
4985 unsigned ptrA = MI->getOperand(1).getReg();
4986 unsigned ptrB = MI->getOperand(2).getReg();
4987 unsigned oldval = MI->getOperand(3).getReg();
4988 unsigned newval = MI->getOperand(4).getReg();
4989 DebugLoc dl = MI->getDebugLoc();
4991 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4992 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4993 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4994 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4995 F->insert(It, loop1MBB);
4996 F->insert(It, loop2MBB);
4997 F->insert(It, midMBB);
4998 F->insert(It, exitMBB);
4999 exitMBB->splice(exitMBB->begin(), BB,
5000 llvm::next(MachineBasicBlock::iterator(MI)),
5002 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5006 // fallthrough --> loopMBB
5007 BB->addSuccessor(loop1MBB);
5010 // l[wd]arx dest, ptr
5011 // cmp[wd] dest, oldval
5014 // st[wd]cx. newval, ptr
5018 // st[wd]cx. dest, ptr
5021 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
5022 .addReg(ptrA).addReg(ptrB);
5023 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
5024 .addReg(oldval).addReg(dest);
5025 BuildMI(BB, dl, TII->get(PPC::BCC))
5026 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5027 BB->addSuccessor(loop2MBB);
5028 BB->addSuccessor(midMBB);
5031 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5032 .addReg(newval).addReg(ptrA).addReg(ptrB);
5033 BuildMI(BB, dl, TII->get(PPC::BCC))
5034 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5035 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5036 BB->addSuccessor(loop1MBB);
5037 BB->addSuccessor(exitMBB);
5040 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
5041 .addReg(dest).addReg(ptrA).addReg(ptrB);
5042 BB->addSuccessor(exitMBB);
5047 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
5048 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
5049 // We must use 64-bit registers for addresses when targeting 64-bit,
5050 // since we're actually doing arithmetic on them. Other registers
5052 bool is64bit = PPCSubTarget.isPPC64();
5053 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
5055 unsigned dest = MI->getOperand(0).getReg();
5056 unsigned ptrA = MI->getOperand(1).getReg();
5057 unsigned ptrB = MI->getOperand(2).getReg();
5058 unsigned oldval = MI->getOperand(3).getReg();
5059 unsigned newval = MI->getOperand(4).getReg();
5060 DebugLoc dl = MI->getDebugLoc();
5062 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
5063 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
5064 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
5065 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
5066 F->insert(It, loop1MBB);
5067 F->insert(It, loop2MBB);
5068 F->insert(It, midMBB);
5069 F->insert(It, exitMBB);
5070 exitMBB->splice(exitMBB->begin(), BB,
5071 llvm::next(MachineBasicBlock::iterator(MI)),
5073 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
5075 MachineRegisterInfo &RegInfo = F->getRegInfo();
5076 const TargetRegisterClass *RC =
5077 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
5078 (const TargetRegisterClass *) &PPC::GPRCRegClass;
5079 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
5080 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
5081 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
5082 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
5083 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
5084 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
5085 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
5086 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
5087 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
5088 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
5089 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
5090 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
5091 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
5093 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
5094 unsigned ZeroReg = is64bit ? PPC::X0 : PPC::R0;
5097 // fallthrough --> loopMBB
5098 BB->addSuccessor(loop1MBB);
5100 // The 4-byte load must be aligned, while a char or short may be
5101 // anywhere in the word. Hence all this nasty bookkeeping code.
5102 // add ptr1, ptrA, ptrB [copy if ptrA==0]
5103 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
5104 // xori shift, shift1, 24 [16]
5105 // rlwinm ptr, ptr1, 0, 0, 29
5106 // slw newval2, newval, shift
5107 // slw oldval2, oldval,shift
5108 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
5109 // slw mask, mask2, shift
5110 // and newval3, newval2, mask
5111 // and oldval3, oldval2, mask
5113 // lwarx tmpDest, ptr
5114 // and tmp, tmpDest, mask
5115 // cmpw tmp, oldval3
5118 // andc tmp2, tmpDest, mask
5119 // or tmp4, tmp2, newval3
5124 // stwcx. tmpDest, ptr
5126 // srw dest, tmpDest, shift
5127 if (ptrA != ZeroReg) {
5128 Ptr1Reg = RegInfo.createVirtualRegister(RC);
5129 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
5130 .addReg(ptrA).addReg(ptrB);
5134 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
5135 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
5136 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
5137 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
5139 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
5140 .addReg(Ptr1Reg).addImm(0).addImm(61);
5142 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
5143 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
5144 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
5145 .addReg(newval).addReg(ShiftReg);
5146 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
5147 .addReg(oldval).addReg(ShiftReg);
5149 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
5151 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
5152 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
5153 .addReg(Mask3Reg).addImm(65535);
5155 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
5156 .addReg(Mask2Reg).addReg(ShiftReg);
5157 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
5158 .addReg(NewVal2Reg).addReg(MaskReg);
5159 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5160 .addReg(OldVal2Reg).addReg(MaskReg);
5163 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5164 .addReg(ZeroReg).addReg(PtrReg);
5165 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5166 .addReg(TmpDestReg).addReg(MaskReg);
5167 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5168 .addReg(TmpReg).addReg(OldVal3Reg);
5169 BuildMI(BB, dl, TII->get(PPC::BCC))
5170 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5171 BB->addSuccessor(loop2MBB);
5172 BB->addSuccessor(midMBB);
5175 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5176 .addReg(TmpDestReg).addReg(MaskReg);
5177 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5178 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5179 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5180 .addReg(ZeroReg).addReg(PtrReg);
5181 BuildMI(BB, dl, TII->get(PPC::BCC))
5182 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5183 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5184 BB->addSuccessor(loop1MBB);
5185 BB->addSuccessor(exitMBB);
5188 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5189 .addReg(ZeroReg).addReg(PtrReg);
5190 BB->addSuccessor(exitMBB);
5195 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
5198 llvm_unreachable("Unexpected instr type to insert");
5201 MI->eraseFromParent(); // The pseudo instruction is gone now.
5205 //===----------------------------------------------------------------------===//
5206 // Target Optimization Hooks
5207 //===----------------------------------------------------------------------===//
5209 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5210 DAGCombinerInfo &DCI) const {
5211 const TargetMachine &TM = getTargetMachine();
5212 SelectionDAG &DAG = DCI.DAG;
5213 DebugLoc dl = N->getDebugLoc();
5214 switch (N->getOpcode()) {
5217 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5218 if (C->isNullValue()) // 0 << V -> 0.
5219 return N->getOperand(0);
5223 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5224 if (C->isNullValue()) // 0 >>u V -> 0.
5225 return N->getOperand(0);
5229 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5230 if (C->isNullValue() || // 0 >>s V -> 0.
5231 C->isAllOnesValue()) // -1 >>s V -> -1.
5232 return N->getOperand(0);
5236 case ISD::SINT_TO_FP:
5237 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5238 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5239 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5240 // We allow the src/dst to be either f32/f64, but the intermediate
5241 // type must be i64.
5242 if (N->getOperand(0).getValueType() == MVT::i64 &&
5243 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5244 SDValue Val = N->getOperand(0).getOperand(0);
5245 if (Val.getValueType() == MVT::f32) {
5246 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5247 DCI.AddToWorklist(Val.getNode());
5250 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5251 DCI.AddToWorklist(Val.getNode());
5252 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5253 DCI.AddToWorklist(Val.getNode());
5254 if (N->getValueType(0) == MVT::f32) {
5255 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5256 DAG.getIntPtrConstant(0));
5257 DCI.AddToWorklist(Val.getNode());
5260 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5261 // If the intermediate type is i32, we can avoid the load/store here
5268 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5269 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5270 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5271 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5272 N->getOperand(1).getValueType() == MVT::i32 &&
5273 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5274 SDValue Val = N->getOperand(1).getOperand(0);
5275 if (Val.getValueType() == MVT::f32) {
5276 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5277 DCI.AddToWorklist(Val.getNode());
5279 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5280 DCI.AddToWorklist(Val.getNode());
5282 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5283 N->getOperand(2), N->getOperand(3));
5284 DCI.AddToWorklist(Val.getNode());
5288 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5289 if (cast<StoreSDNode>(N)->isUnindexed() &&
5290 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5291 N->getOperand(1).getNode()->hasOneUse() &&
5292 (N->getOperand(1).getValueType() == MVT::i32 ||
5293 N->getOperand(1).getValueType() == MVT::i16)) {
5294 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5295 // Do an any-extend to 32-bits if this is a half-word input.
5296 if (BSwapOp.getValueType() == MVT::i16)
5297 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5300 N->getOperand(0), BSwapOp, N->getOperand(2),
5301 DAG.getValueType(N->getOperand(1).getValueType())
5304 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5305 Ops, array_lengthof(Ops),
5306 cast<StoreSDNode>(N)->getMemoryVT(),
5307 cast<StoreSDNode>(N)->getMemOperand());
5311 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5312 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5313 N->getOperand(0).hasOneUse() &&
5314 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5315 SDValue Load = N->getOperand(0);
5316 LoadSDNode *LD = cast<LoadSDNode>(Load);
5317 // Create the byte-swapping load.
5319 LD->getChain(), // Chain
5320 LD->getBasePtr(), // Ptr
5321 DAG.getValueType(N->getValueType(0)) // VT
5324 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5325 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5326 LD->getMemoryVT(), LD->getMemOperand());
5328 // If this is an i16 load, insert the truncate.
5329 SDValue ResVal = BSLoad;
5330 if (N->getValueType(0) == MVT::i16)
5331 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5333 // First, combine the bswap away. This makes the value produced by the
5335 DCI.CombineTo(N, ResVal);
5337 // Next, combine the load away, we give it a bogus result value but a real
5338 // chain result. The result value is dead because the bswap is dead.
5339 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5341 // Return N so it doesn't get rechecked!
5342 return SDValue(N, 0);
5346 case PPCISD::VCMP: {
5347 // If a VCMPo node already exists with exactly the same operands as this
5348 // node, use its result instead of this node (VCMPo computes both a CR6 and
5349 // a normal output).
5351 if (!N->getOperand(0).hasOneUse() &&
5352 !N->getOperand(1).hasOneUse() &&
5353 !N->getOperand(2).hasOneUse()) {
5355 // Scan all of the users of the LHS, looking for VCMPo's that match.
5356 SDNode *VCMPoNode = 0;
5358 SDNode *LHSN = N->getOperand(0).getNode();
5359 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5361 if (UI->getOpcode() == PPCISD::VCMPo &&
5362 UI->getOperand(1) == N->getOperand(1) &&
5363 UI->getOperand(2) == N->getOperand(2) &&
5364 UI->getOperand(0) == N->getOperand(0)) {
5369 // If there is no VCMPo node, or if the flag value has a single use, don't
5371 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5374 // Look at the (necessarily single) use of the flag value. If it has a
5375 // chain, this transformation is more complex. Note that multiple things
5376 // could use the value result, which we should ignore.
5377 SDNode *FlagUser = 0;
5378 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5379 FlagUser == 0; ++UI) {
5380 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5382 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5383 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5390 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5391 // give up for right now.
5392 if (FlagUser->getOpcode() == PPCISD::MFCR)
5393 return SDValue(VCMPoNode, 0);
5398 // If this is a branch on an altivec predicate comparison, lower this so
5399 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5400 // lowering is done pre-legalize, because the legalizer lowers the predicate
5401 // compare down to code that is difficult to reassemble.
5402 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5403 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5407 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5408 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5409 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5410 assert(isDot && "Can't compare against a vector result!");
5412 // If this is a comparison against something other than 0/1, then we know
5413 // that the condition is never/always true.
5414 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5415 if (Val != 0 && Val != 1) {
5416 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5417 return N->getOperand(0);
5418 // Always !=, turn it into an unconditional branch.
5419 return DAG.getNode(ISD::BR, dl, MVT::Other,
5420 N->getOperand(0), N->getOperand(4));
5423 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5425 // Create the PPCISD altivec 'dot' comparison node.
5426 std::vector<EVT> VTs;
5428 LHS.getOperand(2), // LHS of compare
5429 LHS.getOperand(3), // RHS of compare
5430 DAG.getConstant(CompareOpc, MVT::i32)
5432 VTs.push_back(LHS.getOperand(2).getValueType());
5433 VTs.push_back(MVT::Glue);
5434 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5436 // Unpack the result based on how the target uses it.
5437 PPC::Predicate CompOpc;
5438 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5439 default: // Can't happen, don't crash on invalid number though.
5440 case 0: // Branch on the value of the EQ bit of CR6.
5441 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5443 case 1: // Branch on the inverted value of the EQ bit of CR6.
5444 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5446 case 2: // Branch on the value of the LT bit of CR6.
5447 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5449 case 3: // Branch on the inverted value of the LT bit of CR6.
5450 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5454 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5455 DAG.getConstant(CompOpc, MVT::i32),
5456 DAG.getRegister(PPC::CR6, MVT::i32),
5457 N->getOperand(4), CompNode.getValue(1));
5466 //===----------------------------------------------------------------------===//
5467 // Inline Assembly Support
5468 //===----------------------------------------------------------------------===//
5470 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5474 const SelectionDAG &DAG,
5475 unsigned Depth) const {
5476 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5477 switch (Op.getOpcode()) {
5479 case PPCISD::LBRX: {
5480 // lhbrx is known to have the top bits cleared out.
5481 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5482 KnownZero = 0xFFFF0000;
5485 case ISD::INTRINSIC_WO_CHAIN: {
5486 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5488 case Intrinsic::ppc_altivec_vcmpbfp_p:
5489 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5490 case Intrinsic::ppc_altivec_vcmpequb_p:
5491 case Intrinsic::ppc_altivec_vcmpequh_p:
5492 case Intrinsic::ppc_altivec_vcmpequw_p:
5493 case Intrinsic::ppc_altivec_vcmpgefp_p:
5494 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5495 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5496 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5497 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5498 case Intrinsic::ppc_altivec_vcmpgtub_p:
5499 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5500 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5501 KnownZero = ~1U; // All bits but the low one are known to be zero.
5509 /// getConstraintType - Given a constraint, return the type of
5510 /// constraint it is for this target.
5511 PPCTargetLowering::ConstraintType
5512 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5513 if (Constraint.size() == 1) {
5514 switch (Constraint[0]) {
5521 return C_RegisterClass;
5524 return TargetLowering::getConstraintType(Constraint);
5527 /// Examine constraint type and operand type and determine a weight value.
5528 /// This object must already have been set up with the operand type
5529 /// and the current alternative constraint selected.
5530 TargetLowering::ConstraintWeight
5531 PPCTargetLowering::getSingleConstraintMatchWeight(
5532 AsmOperandInfo &info, const char *constraint) const {
5533 ConstraintWeight weight = CW_Invalid;
5534 Value *CallOperandVal = info.CallOperandVal;
5535 // If we don't have a value, we can't do a match,
5536 // but allow it at the lowest weight.
5537 if (CallOperandVal == NULL)
5539 Type *type = CallOperandVal->getType();
5540 // Look at the constraint type.
5541 switch (*constraint) {
5543 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
5546 if (type->isIntegerTy())
5547 weight = CW_Register;
5550 if (type->isFloatTy())
5551 weight = CW_Register;
5554 if (type->isDoubleTy())
5555 weight = CW_Register;
5558 if (type->isVectorTy())
5559 weight = CW_Register;
5562 weight = CW_Register;
5568 std::pair<unsigned, const TargetRegisterClass*>
5569 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5571 if (Constraint.size() == 1) {
5572 // GCC RS6000 Constraint Letters
5573 switch (Constraint[0]) {
5576 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5577 return std::make_pair(0U, PPC::G8RCRegisterClass);
5578 return std::make_pair(0U, PPC::GPRCRegisterClass);
5581 return std::make_pair(0U, PPC::F4RCRegisterClass);
5582 else if (VT == MVT::f64)
5583 return std::make_pair(0U, PPC::F8RCRegisterClass);
5586 return std::make_pair(0U, PPC::VRRCRegisterClass);
5588 return std::make_pair(0U, PPC::CRRCRegisterClass);
5592 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5596 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5597 /// vector. If it is invalid, don't add anything to Ops.
5598 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
5599 std::string &Constraint,
5600 std::vector<SDValue>&Ops,
5601 SelectionDAG &DAG) const {
5602 SDValue Result(0,0);
5604 // Only support length 1 constraints.
5605 if (Constraint.length() > 1) return;
5607 char Letter = Constraint[0];
5618 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5619 if (!CST) return; // Must be an immediate to match.
5620 unsigned Value = CST->getZExtValue();
5622 default: llvm_unreachable("Unknown constraint letter!");
5623 case 'I': // "I" is a signed 16-bit constant.
5624 if ((short)Value == (int)Value)
5625 Result = DAG.getTargetConstant(Value, Op.getValueType());
5627 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5628 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5629 if ((short)Value == 0)
5630 Result = DAG.getTargetConstant(Value, Op.getValueType());
5632 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5633 if ((Value >> 16) == 0)
5634 Result = DAG.getTargetConstant(Value, Op.getValueType());
5636 case 'M': // "M" is a constant that is greater than 31.
5638 Result = DAG.getTargetConstant(Value, Op.getValueType());
5640 case 'N': // "N" is a positive constant that is an exact power of two.
5641 if ((int)Value > 0 && isPowerOf2_32(Value))
5642 Result = DAG.getTargetConstant(Value, Op.getValueType());
5644 case 'O': // "O" is the constant zero.
5646 Result = DAG.getTargetConstant(Value, Op.getValueType());
5648 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5649 if ((short)-Value == (int)-Value)
5650 Result = DAG.getTargetConstant(Value, Op.getValueType());
5657 if (Result.getNode()) {
5658 Ops.push_back(Result);
5662 // Handle standard constraint letters.
5663 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
5666 // isLegalAddressingMode - Return true if the addressing mode represented
5667 // by AM is legal for this target, for a load/store of the specified type.
5668 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5670 // FIXME: PPC does not allow r+i addressing modes for vectors!
5672 // PPC allows a sign-extended 16-bit immediate field.
5673 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5676 // No global is ever allowed as a base.
5680 // PPC only support r+r,
5682 case 0: // "r+i" or just "i", depending on HasBaseReg.
5685 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5687 // Otherwise we have r+r or r+i.
5690 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5692 // Allow 2*r as r+r.
5695 // No other scales are supported.
5702 /// isLegalAddressImmediate - Return true if the integer value can be used
5703 /// as the offset of the target addressing mode for load / store of the
5705 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,Type *Ty) const{
5706 // PPC allows a sign-extended 16-bit immediate field.
5707 return (V > -(1 << 16) && V < (1 << 16)-1);
5710 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5714 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5715 SelectionDAG &DAG) const {
5716 MachineFunction &MF = DAG.getMachineFunction();
5717 MachineFrameInfo *MFI = MF.getFrameInfo();
5718 MFI->setReturnAddressIsTaken(true);
5720 DebugLoc dl = Op.getDebugLoc();
5721 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5723 // Make sure the function does not optimize away the store of the RA to
5725 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5726 FuncInfo->setLRStoreRequired();
5727 bool isPPC64 = PPCSubTarget.isPPC64();
5728 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5731 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5734 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
5735 isPPC64? MVT::i64 : MVT::i32);
5736 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5737 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5739 MachinePointerInfo(), false, false, 0);
5742 // Just load the return address off the stack.
5743 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5744 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5745 RetAddrFI, MachinePointerInfo(), false, false, 0);
5748 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5749 SelectionDAG &DAG) const {
5750 DebugLoc dl = Op.getDebugLoc();
5751 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5753 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5754 bool isPPC64 = PtrVT == MVT::i64;
5756 MachineFunction &MF = DAG.getMachineFunction();
5757 MachineFrameInfo *MFI = MF.getFrameInfo();
5758 MFI->setFrameAddressIsTaken(true);
5759 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) &&
5760 MFI->getStackSize() &&
5761 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5762 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5763 (is31 ? PPC::R31 : PPC::R1);
5764 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5767 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5768 FrameAddr, MachinePointerInfo(), false, false, 0);
5773 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5774 // The PowerPC target isn't yet aware of offsets.
5778 /// getOptimalMemOpType - Returns the target specific optimal type for load
5779 /// and store operations as a result of memset, memcpy, and memmove
5780 /// lowering. If DstAlign is zero that means it's safe to destination
5781 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5782 /// means there isn't a need to check it against alignment requirement,
5783 /// probably because the source does not need to be loaded. If
5784 /// 'NonScalarIntSafe' is true, that means it's safe to return a
5785 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5786 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5787 /// constant so it does not need to be loaded.
5788 /// It returns EVT::Other if the type should be determined using generic
5789 /// target-independent logic.
5790 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5791 unsigned DstAlign, unsigned SrcAlign,
5792 bool NonScalarIntSafe,
5794 MachineFunction &MF) const {
5795 if (this->PPCSubTarget.isPPC64()) {