1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCTargetMachine.h"
16 #include "llvm/ADT/VectorExtras.h"
17 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
18 #include "llvm/CodeGen/MachineFrameInfo.h"
19 #include "llvm/CodeGen/MachineFunction.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
22 #include "llvm/CodeGen/SSARegMap.h"
23 #include "llvm/Constants.h"
24 #include "llvm/Function.h"
25 #include "llvm/Intrinsics.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Target/TargetOptions.h"
30 PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
31 : TargetLowering(TM) {
33 // Fold away setcc operations if possible.
34 setSetCCIsExpensive();
37 // Use _setjmp/_longjmp instead of setjmp/longjmp.
38 setUseUnderscoreSetJmpLongJmp(true);
40 // Set up the register classes.
41 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
42 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
43 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
45 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
46 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
48 // PowerPC has no intrinsics for these particular operations
49 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
50 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
51 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
53 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
54 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
55 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
57 // PowerPC has no SREM/UREM instructions
58 setOperationAction(ISD::SREM, MVT::i32, Expand);
59 setOperationAction(ISD::UREM, MVT::i32, Expand);
61 // We don't support sin/cos/sqrt/fmod
62 setOperationAction(ISD::FSIN , MVT::f64, Expand);
63 setOperationAction(ISD::FCOS , MVT::f64, Expand);
64 setOperationAction(ISD::FREM , MVT::f64, Expand);
65 setOperationAction(ISD::FSIN , MVT::f32, Expand);
66 setOperationAction(ISD::FCOS , MVT::f32, Expand);
67 setOperationAction(ISD::FREM , MVT::f32, Expand);
69 // If we're enabling GP optimizations, use hardware square root
70 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
71 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
72 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
75 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
76 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
78 // PowerPC does not have BSWAP, CTPOP or CTTZ
79 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
80 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
81 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
83 // PowerPC does not have ROTR
84 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
86 // PowerPC does not have Select
87 setOperationAction(ISD::SELECT, MVT::i32, Expand);
88 setOperationAction(ISD::SELECT, MVT::f32, Expand);
89 setOperationAction(ISD::SELECT, MVT::f64, Expand);
90 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
91 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
92 setOperationAction(ISD::SELECT, MVT::v8i16, Expand);
93 setOperationAction(ISD::SELECT, MVT::v16i8, Expand);
95 // PowerPC wants to turn select_cc of FP into fsel when possible.
96 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
97 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
99 // PowerPC wants to optimize integer setcc a bit
100 setOperationAction(ISD::SETCC, MVT::i32, Custom);
102 // PowerPC does not have BRCOND which requires SetCC
103 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
105 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
106 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
108 // PowerPC does not have [U|S]INT_TO_FP
109 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
110 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
112 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
113 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
115 // PowerPC does not have truncstore for i1.
116 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
118 // Support label based line numbers.
119 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
120 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
121 // FIXME - use subtarget debug flags
122 if (!TM.getSubtarget<PPCSubtarget>().isDarwin())
123 setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
125 // We want to legalize GlobalAddress and ConstantPool nodes into the
126 // appropriate instructions to materialize the address.
127 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
128 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
130 // RET must be custom lowered, to meet ABI requirements
131 setOperationAction(ISD::RET , MVT::Other, Custom);
133 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
134 setOperationAction(ISD::VASTART , MVT::Other, Custom);
136 // Use the default implementation.
137 setOperationAction(ISD::VAARG , MVT::Other, Expand);
138 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
139 setOperationAction(ISD::VAEND , MVT::Other, Expand);
140 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
141 setOperationAction(ISD::STACKRESTORE , MVT::Other, Expand);
142 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Expand);
144 // We want to custom lower some of our intrinsics.
145 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
147 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
148 // They also have instructions for converting between i64 and fp.
149 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
150 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
152 // FIXME: disable this lowered code. This generates 64-bit register values,
153 // and we don't model the fact that the top part is clobbered by calls. We
154 // need to flag these together so that the value isn't live across a call.
155 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
157 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
158 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
160 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
161 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
164 if (TM.getSubtarget<PPCSubtarget>().has64BitRegs()) {
165 // 64 bit PowerPC implementations can support i64 types directly
166 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
167 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
168 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
170 // 32 bit PowerPC wants to expand i64 shifts itself.
171 setOperationAction(ISD::SHL, MVT::i64, Custom);
172 setOperationAction(ISD::SRL, MVT::i64, Custom);
173 setOperationAction(ISD::SRA, MVT::i64, Custom);
176 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
177 // First set operation action for all vector types to expand. Then we
178 // will selectively turn on ones that can be effectively codegen'd.
179 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
180 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
181 // add/sub/and/or/xor are legal for all supported vector VT's.
182 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
183 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
184 setOperationAction(ISD::AND , (MVT::ValueType)VT, Legal);
185 setOperationAction(ISD::OR , (MVT::ValueType)VT, Legal);
186 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Legal);
188 // We promote all shuffles to v16i8.
189 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
190 AddPromotedToType(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
192 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
193 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
194 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
195 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
196 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
197 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
198 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
199 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
201 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
204 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
205 // with merges, splats, etc.
206 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
208 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
209 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
210 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
211 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
213 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
215 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
216 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
218 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
219 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
220 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
221 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
224 setSetCCResultContents(ZeroOrOneSetCCResult);
225 setStackPointerRegisterToSaveRestore(PPC::R1);
227 // We have target-specific dag combine patterns for the following nodes:
228 setTargetDAGCombine(ISD::SINT_TO_FP);
229 setTargetDAGCombine(ISD::STORE);
231 computeRegisterProperties();
234 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
237 case PPCISD::FSEL: return "PPCISD::FSEL";
238 case PPCISD::FCFID: return "PPCISD::FCFID";
239 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
240 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
241 case PPCISD::STFIWX: return "PPCISD::STFIWX";
242 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
243 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
244 case PPCISD::VPERM: return "PPCISD::VPERM";
245 case PPCISD::Hi: return "PPCISD::Hi";
246 case PPCISD::Lo: return "PPCISD::Lo";
247 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
248 case PPCISD::SRL: return "PPCISD::SRL";
249 case PPCISD::SRA: return "PPCISD::SRA";
250 case PPCISD::SHL: return "PPCISD::SHL";
251 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
252 case PPCISD::STD_32: return "PPCISD::STD_32";
253 case PPCISD::CALL: return "PPCISD::CALL";
254 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
255 case PPCISD::MFCR: return "PPCISD::MFCR";
256 case PPCISD::VCMP: return "PPCISD::VCMP";
257 case PPCISD::VCMPo: return "PPCISD::VCMPo";
261 //===----------------------------------------------------------------------===//
262 // Node matching predicates, for use by the tblgen matching code.
263 //===----------------------------------------------------------------------===//
265 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
266 static bool isFloatingPointZero(SDOperand Op) {
267 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
268 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
269 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
270 // Maybe this has already been legalized into the constant pool?
271 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
272 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
273 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
278 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
279 /// true if Op is undef or if it matches the specified value.
280 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
281 return Op.getOpcode() == ISD::UNDEF ||
282 cast<ConstantSDNode>(Op)->getValue() == Val;
285 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
286 /// VPKUHUM instruction.
287 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
289 for (unsigned i = 0; i != 16; ++i)
290 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
293 for (unsigned i = 0; i != 8; ++i)
294 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
295 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
301 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
302 /// VPKUWUM instruction.
303 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
305 for (unsigned i = 0; i != 16; i += 2)
306 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
307 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
310 for (unsigned i = 0; i != 8; i += 2)
311 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
312 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
313 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
314 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
320 /// isVMerge - Common function, used to match vmrg* shuffles.
322 static bool isVMerge(SDNode *N, unsigned UnitSize,
323 unsigned LHSStart, unsigned RHSStart) {
324 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
325 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
326 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
327 "Unsupported merge size!");
329 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
330 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
331 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
332 LHSStart+j+i*UnitSize) ||
333 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
334 RHSStart+j+i*UnitSize))
340 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
341 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
342 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
344 return isVMerge(N, UnitSize, 8, 24);
345 return isVMerge(N, UnitSize, 8, 8);
348 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
349 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
350 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
352 return isVMerge(N, UnitSize, 0, 16);
353 return isVMerge(N, UnitSize, 0, 0);
357 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
358 /// amount, otherwise return -1.
359 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
360 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
361 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
362 // Find the first non-undef value in the shuffle mask.
364 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
367 if (i == 16) return -1; // all undef.
369 // Otherwise, check to see if the rest of the elements are consequtively
370 // numbered from this value.
371 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
372 if (ShiftAmt < i) return -1;
376 // Check the rest of the elements to see if they are consequtive.
377 for (++i; i != 16; ++i)
378 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
381 // Check the rest of the elements to see if they are consequtive.
382 for (++i; i != 16; ++i)
383 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
390 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
391 /// specifies a splat of a single element that is suitable for input to
392 /// VSPLTB/VSPLTH/VSPLTW.
393 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
394 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
395 N->getNumOperands() == 16 &&
396 (EltSize == 1 || EltSize == 2 || EltSize == 4));
398 // This is a splat operation if each element of the permute is the same, and
399 // if the value doesn't reference the second vector.
400 unsigned ElementBase = 0;
401 SDOperand Elt = N->getOperand(0);
402 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
403 ElementBase = EltV->getValue();
405 return false; // FIXME: Handle UNDEF elements too!
407 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
410 // Check that they are consequtive.
411 for (unsigned i = 1; i != EltSize; ++i) {
412 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
413 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
417 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
418 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
419 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
420 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
421 "Invalid VECTOR_SHUFFLE mask!");
422 for (unsigned j = 0; j != EltSize; ++j)
423 if (N->getOperand(i+j) != N->getOperand(j))
430 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
431 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
432 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
433 assert(isSplatShuffleMask(N, EltSize));
434 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
437 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
438 /// by using a vspltis[bhw] instruction of the specified element size, return
439 /// the constant being splatted. The ByteSize field indicates the number of
440 /// bytes of each element [124] -> [bhw].
441 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
442 SDOperand OpVal(0, 0);
444 // If ByteSize of the splat is bigger than the element size of the
445 // build_vector, then we have a case where we are checking for a splat where
446 // multiple elements of the buildvector are folded together into a single
447 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
448 unsigned EltSize = 16/N->getNumOperands();
449 if (EltSize < ByteSize) {
450 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
451 SDOperand UniquedVals[4];
452 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
454 // See if all of the elements in the buildvector agree across.
455 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
456 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
457 // If the element isn't a constant, bail fully out.
458 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
461 if (UniquedVals[i&(Multiple-1)].Val == 0)
462 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
463 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
464 return SDOperand(); // no match.
467 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
468 // either constant or undef values that are identical for each chunk. See
469 // if these chunks can form into a larger vspltis*.
471 // Check to see if all of the leading entries are either 0 or -1. If
472 // neither, then this won't fit into the immediate field.
473 bool LeadingZero = true;
474 bool LeadingOnes = true;
475 for (unsigned i = 0; i != Multiple-1; ++i) {
476 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
478 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
479 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
481 // Finally, check the least significant entry.
483 if (UniquedVals[Multiple-1].Val == 0)
484 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
485 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
487 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
490 if (UniquedVals[Multiple-1].Val == 0)
491 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
492 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
493 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
494 return DAG.getTargetConstant(Val, MVT::i32);
500 // Check to see if this buildvec has a single non-undef value in its elements.
501 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
502 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
504 OpVal = N->getOperand(i);
505 else if (OpVal != N->getOperand(i))
509 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
511 unsigned ValSizeInBytes = 0;
513 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
514 Value = CN->getValue();
515 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
516 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
517 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
518 Value = FloatToBits(CN->getValue());
522 // If the splat value is larger than the element value, then we can never do
523 // this splat. The only case that we could fit the replicated bits into our
524 // immediate field for would be zero, and we prefer to use vxor for it.
525 if (ValSizeInBytes < ByteSize) return SDOperand();
527 // If the element value is larger than the splat value, cut it in half and
528 // check to see if the two halves are equal. Continue doing this until we
529 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
530 while (ValSizeInBytes > ByteSize) {
531 ValSizeInBytes >>= 1;
533 // If the top half equals the bottom half, we're still ok.
534 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
535 (Value & ((1 << (8*ValSizeInBytes))-1)))
539 // Properly sign extend the value.
540 int ShAmt = (4-ByteSize)*8;
541 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
543 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
544 if (MaskVal == 0) return SDOperand();
546 // Finally, if this value fits in a 5 bit sext field, return it
547 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
548 return DAG.getTargetConstant(MaskVal, MVT::i32);
552 //===----------------------------------------------------------------------===//
553 // LowerOperation implementation
554 //===----------------------------------------------------------------------===//
556 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
557 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
558 Constant *C = CP->get();
559 SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i32, CP->getAlignment());
560 SDOperand Zero = DAG.getConstant(0, MVT::i32);
562 const TargetMachine &TM = DAG.getTarget();
564 // If this is a non-darwin platform, we don't support non-static relo models
566 if (TM.getRelocationModel() == Reloc::Static ||
567 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
568 // Generate non-pic code that has direct accesses to the constant pool.
569 // The address of the global is just (hi(&g)+lo(&g)).
570 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
571 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
572 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
575 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, CPI, Zero);
576 if (TM.getRelocationModel() == Reloc::PIC) {
577 // With PIC, the first instruction is actually "GR+hi(&G)".
578 Hi = DAG.getNode(ISD::ADD, MVT::i32,
579 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
582 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, CPI, Zero);
583 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
587 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
588 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
589 GlobalValue *GV = GSDN->getGlobal();
590 SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i32, GSDN->getOffset());
591 SDOperand Zero = DAG.getConstant(0, MVT::i32);
593 const TargetMachine &TM = DAG.getTarget();
595 // If this is a non-darwin platform, we don't support non-static relo models
597 if (TM.getRelocationModel() == Reloc::Static ||
598 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
599 // Generate non-pic code that has direct accesses to globals.
600 // The address of the global is just (hi(&g)+lo(&g)).
601 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
602 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
603 return DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
606 SDOperand Hi = DAG.getNode(PPCISD::Hi, MVT::i32, GA, Zero);
607 if (TM.getRelocationModel() == Reloc::PIC) {
608 // With PIC, the first instruction is actually "GR+hi(&G)".
609 Hi = DAG.getNode(ISD::ADD, MVT::i32,
610 DAG.getNode(PPCISD::GlobalBaseReg, MVT::i32), Hi);
613 SDOperand Lo = DAG.getNode(PPCISD::Lo, MVT::i32, GA, Zero);
614 Lo = DAG.getNode(ISD::ADD, MVT::i32, Hi, Lo);
616 if (!GV->hasWeakLinkage() && !GV->hasLinkOnceLinkage() &&
617 (!GV->isExternal() || GV->hasNotBeenReadFromBytecode()))
620 // If the global is weak or external, we have to go through the lazy
622 return DAG.getLoad(MVT::i32, DAG.getEntryNode(), Lo, DAG.getSrcValue(0));
625 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
626 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
628 // If we're comparing for equality to zero, expose the fact that this is
629 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
630 // fold the new nodes.
631 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
632 if (C->isNullValue() && CC == ISD::SETEQ) {
633 MVT::ValueType VT = Op.getOperand(0).getValueType();
634 SDOperand Zext = Op.getOperand(0);
637 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
639 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
640 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
641 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
642 DAG.getConstant(Log2b, MVT::i32));
643 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
645 // Leave comparisons against 0 and -1 alone for now, since they're usually
646 // optimized. FIXME: revisit this when we can custom lower all setcc
648 if (C->isAllOnesValue() || C->isNullValue())
652 // If we have an integer seteq/setne, turn it into a compare against zero
653 // by subtracting the rhs from the lhs, which is faster than setting a
654 // condition register, reading it back out, and masking the correct bit.
655 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
656 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
657 MVT::ValueType VT = Op.getValueType();
658 SDOperand Sub = DAG.getNode(ISD::SUB, LHSVT, Op.getOperand(0),
660 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
665 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
666 unsigned VarArgsFrameIndex) {
667 // vastart just stores the address of the VarArgsFrameIndex slot into the
668 // memory location argument.
669 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
670 return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), FR,
671 Op.getOperand(1), Op.getOperand(2));
674 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG) {
676 switch(Op.getNumOperands()) {
678 assert(0 && "Do not know how to return this many arguments!");
681 return SDOperand(); // ret void is legal
683 MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
685 if (MVT::isVector(ArgVT))
687 else if (MVT::isInteger(ArgVT))
690 assert(MVT::isFloatingPoint(ArgVT));
694 Copy = DAG.getCopyToReg(Op.getOperand(0), ArgReg, Op.getOperand(1),
697 // If we haven't noted the R3/F1 are live out, do so now.
698 if (DAG.getMachineFunction().liveout_empty())
699 DAG.getMachineFunction().addLiveOut(ArgReg);
703 Copy = DAG.getCopyToReg(Op.getOperand(0), PPC::R3, Op.getOperand(2),
705 Copy = DAG.getCopyToReg(Copy, PPC::R4, Op.getOperand(1),Copy.getValue(1));
706 // If we haven't noted the R3+R4 are live out, do so now.
707 if (DAG.getMachineFunction().liveout_empty()) {
708 DAG.getMachineFunction().addLiveOut(PPC::R3);
709 DAG.getMachineFunction().addLiveOut(PPC::R4);
713 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
716 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
718 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
719 // Not FP? Not a fsel.
720 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
721 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
724 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
726 // Cannot handle SETEQ/SETNE.
727 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
729 MVT::ValueType ResVT = Op.getValueType();
730 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
731 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
732 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
734 // If the RHS of the comparison is a 0.0, we don't need to do the
735 // subtraction at all.
736 if (isFloatingPointZero(RHS))
738 default: break; // SETUO etc aren't handled by fsel.
741 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
744 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
745 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
746 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
749 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
752 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
753 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
754 return DAG.getNode(PPCISD::FSEL, ResVT,
755 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
760 default: break; // SETUO etc aren't handled by fsel.
763 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
764 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
765 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
766 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
769 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
770 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
771 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
772 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
775 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
776 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
777 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
778 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
781 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
782 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
783 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
784 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
789 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
790 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
791 SDOperand Src = Op.getOperand(0);
792 if (Src.getValueType() == MVT::f32)
793 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
796 switch (Op.getValueType()) {
797 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
799 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
802 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
806 // Convert the FP value to an int value through memory.
807 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::i64, Tmp);
808 if (Op.getValueType() == MVT::i32)
809 Bits = DAG.getNode(ISD::TRUNCATE, MVT::i32, Bits);
813 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
814 if (Op.getOperand(0).getValueType() == MVT::i64) {
815 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
816 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
817 if (Op.getValueType() == MVT::f32)
818 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
822 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
823 "Unhandled SINT_TO_FP type in custom expander!");
824 // Since we only generate this in 64-bit mode, we can take advantage of
825 // 64-bit registers. In particular, sign extend the input value into the
826 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
827 // then lfd it and fcfid it.
828 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
829 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
830 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
832 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
835 // STD the extended value into the stack slot.
836 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
837 DAG.getEntryNode(), Ext64, FIdx,
838 DAG.getSrcValue(NULL));
839 // Load the value as a double.
840 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, DAG.getSrcValue(NULL));
842 // FCFID it and return it.
843 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
844 if (Op.getValueType() == MVT::f32)
845 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
849 static SDOperand LowerSHL(SDOperand Op, SelectionDAG &DAG) {
850 assert(Op.getValueType() == MVT::i64 &&
851 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
852 // The generic code does a fine job expanding shift by a constant.
853 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
855 // Otherwise, expand into a bunch of logical ops. Note that these ops
856 // depend on the PPC behavior for oversized shift amounts.
857 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
858 DAG.getConstant(0, MVT::i32));
859 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
860 DAG.getConstant(1, MVT::i32));
861 SDOperand Amt = Op.getOperand(1);
863 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
864 DAG.getConstant(32, MVT::i32), Amt);
865 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
866 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
867 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
868 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
869 DAG.getConstant(-32U, MVT::i32));
870 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
871 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
872 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
873 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
876 static SDOperand LowerSRL(SDOperand Op, SelectionDAG &DAG) {
877 assert(Op.getValueType() == MVT::i64 &&
878 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
879 // The generic code does a fine job expanding shift by a constant.
880 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
882 // Otherwise, expand into a bunch of logical ops. Note that these ops
883 // depend on the PPC behavior for oversized shift amounts.
884 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
885 DAG.getConstant(0, MVT::i32));
886 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
887 DAG.getConstant(1, MVT::i32));
888 SDOperand Amt = Op.getOperand(1);
890 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
891 DAG.getConstant(32, MVT::i32), Amt);
892 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
893 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
894 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
895 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
896 DAG.getConstant(-32U, MVT::i32));
897 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
898 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
899 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
900 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
903 static SDOperand LowerSRA(SDOperand Op, SelectionDAG &DAG) {
904 assert(Op.getValueType() == MVT::i64 &&
905 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
906 // The generic code does a fine job expanding shift by a constant.
907 if (isa<ConstantSDNode>(Op.getOperand(1))) return SDOperand();
909 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
910 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
911 DAG.getConstant(0, MVT::i32));
912 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
913 DAG.getConstant(1, MVT::i32));
914 SDOperand Amt = Op.getOperand(1);
916 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
917 DAG.getConstant(32, MVT::i32), Amt);
918 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
919 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
920 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
921 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
922 DAG.getConstant(-32U, MVT::i32));
923 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
924 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
925 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
926 Tmp4, Tmp6, ISD::SETLE);
927 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
930 //===----------------------------------------------------------------------===//
931 // Vector related lowering.
934 // If this is a vector of constants or undefs, get the bits. A bit in
935 // UndefBits is set if the corresponding element of the vector is an
936 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
937 // zero. Return true if this is not an array of constants, false if it is.
939 // Note that VectorBits/UndefBits are returned in 'little endian' form, so
940 // elements 0,1 go in VectorBits[0] and 2,3 go in VectorBits[1] for a v4i32.
941 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
942 uint64_t UndefBits[2]) {
943 // Start with zero'd results.
944 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
946 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
947 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
948 SDOperand OpVal = BV->getOperand(i);
950 unsigned PartNo = i >= e/2; // In the upper 128 bits?
951 unsigned SlotNo = i & (e/2-1); // Which subpiece of the uint64_t it is.
953 uint64_t EltBits = 0;
954 if (OpVal.getOpcode() == ISD::UNDEF) {
955 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
956 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
958 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
959 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
960 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
961 assert(CN->getValueType(0) == MVT::f32 &&
962 "Only one legal FP vector type!");
963 EltBits = FloatToBits(CN->getValue());
965 // Nonconstant element.
969 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
972 //printf("%llx %llx %llx %llx\n",
973 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
977 // If this is a case we can't handle, return null and let the default
978 // expansion code take care of it. If we CAN select this case, and if it
979 // selects to a single instruction, return Op. Otherwise, if we can codegen
980 // this case more efficiently than a constant pool load, lower it to the
981 // sequence of ops that should be used.
982 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
983 // If this is a vector of constants or undefs, get the bits. A bit in
984 // UndefBits is set if the corresponding element of the vector is an
985 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
987 uint64_t VectorBits[2];
988 uint64_t UndefBits[2];
989 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
990 return SDOperand(); // Not a constant vector.
992 // See if this is all zeros.
993 if ((VectorBits[0] | VectorBits[1]) == 0) {
994 // Canonicalize all zero vectors to be v4i32.
995 if (Op.getValueType() != MVT::v4i32) {
996 SDOperand Z = DAG.getConstant(0, MVT::i32);
997 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
998 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
1003 // Check to see if this is something we can use VSPLTI* to form.
1004 MVT::ValueType CanonicalVT = MVT::Other;
1007 if ((CST = PPC::get_VSPLTI_elt(Op.Val, 4, DAG).Val)) // vspltisw
1008 CanonicalVT = MVT::v4i32;
1009 else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 2, DAG).Val)) // vspltish
1010 CanonicalVT = MVT::v8i16;
1011 else if ((CST = PPC::get_VSPLTI_elt(Op.Val, 1, DAG).Val)) // vspltisb
1012 CanonicalVT = MVT::v16i8;
1014 // If this matches one of the vsplti* patterns, force it to the canonical
1015 // type for the pattern.
1017 if (Op.getValueType() != CanonicalVT) {
1018 // Convert the splatted element to the right element type.
1019 SDOperand Elt = DAG.getNode(ISD::TRUNCATE,
1020 MVT::getVectorBaseType(CanonicalVT),
1022 std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
1023 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
1024 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1029 // If this is some other splat of 4-byte elements, see if we can handle it
1031 // FIXME: Make this more undef happy and work with other widths (1,2 bytes).
1032 if (VectorBits[0] == VectorBits[1] &&
1033 unsigned(VectorBits[0]) == unsigned(VectorBits[0] >> 32)) {
1034 unsigned Bits = unsigned(VectorBits[0]);
1036 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
1037 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). These are important
1039 if (Bits == 0x80000000 || Bits == 0x7FFFFFFF) {
1040 // Make -1 and vspltisw -1:
1041 SDOperand OnesI = DAG.getConstant(~0U, MVT::i32);
1042 SDOperand OnesV = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32,
1043 OnesI, OnesI, OnesI, OnesI);
1045 // Make the VSLW intrinsic, computing 0x8000_0000.
1047 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, MVT::v4i32,
1048 DAG.getConstant(Intrinsic::ppc_altivec_vslw, MVT::i32),
1051 // If this is 0x7FFF_FFFF, xor by OnesV to invert it.
1052 if (Bits == 0x7FFFFFFF)
1053 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
1055 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
1062 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
1063 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
1064 /// return the code it can be lowered into. Worst case, it can always be
1065 /// lowered into a vperm.
1066 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
1067 SDOperand V1 = Op.getOperand(0);
1068 SDOperand V2 = Op.getOperand(1);
1069 SDOperand PermMask = Op.getOperand(2);
1071 // Cases that are handled by instructions that take permute immediates
1072 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
1073 // selected by the instruction selector.
1074 if (V2.getOpcode() == ISD::UNDEF) {
1075 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
1076 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
1077 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
1078 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
1079 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
1080 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
1081 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
1082 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
1083 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
1084 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
1085 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
1086 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
1091 // Altivec has a variety of "shuffle immediates" that take two vector inputs
1092 // and produce a fixed permutation. If any of these match, do not lower to
1094 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
1095 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
1096 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
1097 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
1098 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
1099 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
1100 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
1101 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
1102 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
1105 // TODO: Handle more cases, and also handle cases that are cheaper to do as
1106 // multiple such instructions than as a constant pool load/vperm pair.
1108 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
1109 // vector that will get spilled to the constant pool.
1110 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
1112 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
1113 // that it is in input element units, not in bytes. Convert now.
1114 MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
1115 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
1117 std::vector<SDOperand> ResultMask;
1118 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
1119 unsigned SrcElt =cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
1121 for (unsigned j = 0; j != BytesPerElement; ++j)
1122 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
1126 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
1127 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
1130 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
1131 /// lower, do it, otherwise return null.
1132 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
1133 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getValue();
1135 // If this is a lowered altivec predicate compare, CompareOpc is set to the
1136 // opcode number of the comparison.
1137 int CompareOpc = -1;
1140 default: return SDOperand(); // Don't custom lower most intrinsics.
1141 // Comparison predicates.
1142 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
1143 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
1144 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
1145 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
1146 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
1147 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
1148 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
1149 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
1150 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
1151 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
1152 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
1153 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
1154 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
1156 // Normal Comparisons.
1157 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
1158 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
1159 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
1160 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
1161 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
1162 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
1163 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
1164 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
1165 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
1166 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
1167 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
1168 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
1169 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
1172 assert(CompareOpc>0 && "We only lower altivec predicate compares so far!");
1174 // If this is a non-dot comparison, make the VCMP node.
1176 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
1177 Op.getOperand(1), Op.getOperand(2),
1178 DAG.getConstant(CompareOpc, MVT::i32));
1179 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
1182 // Create the PPCISD altivec 'dot' comparison node.
1183 std::vector<SDOperand> Ops;
1184 std::vector<MVT::ValueType> VTs;
1185 Ops.push_back(Op.getOperand(2)); // LHS
1186 Ops.push_back(Op.getOperand(3)); // RHS
1187 Ops.push_back(DAG.getConstant(CompareOpc, MVT::i32));
1188 VTs.push_back(Op.getOperand(2).getValueType());
1189 VTs.push_back(MVT::Flag);
1190 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops);
1192 // Now that we have the comparison, emit a copy from the CR to a GPR.
1193 // This is flagged to the above dot comparison.
1194 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
1195 DAG.getRegister(PPC::CR6, MVT::i32),
1196 CompNode.getValue(1));
1198 // Unpack the result based on how the target uses it.
1199 unsigned BitNo; // Bit # of CR6.
1200 bool InvertBit; // Invert result?
1201 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
1202 default: // Can't happen, don't crash on invalid number though.
1203 case 0: // Return the value of the EQ bit of CR6.
1204 BitNo = 0; InvertBit = false;
1206 case 1: // Return the inverted value of the EQ bit of CR6.
1207 BitNo = 0; InvertBit = true;
1209 case 2: // Return the value of the LT bit of CR6.
1210 BitNo = 2; InvertBit = false;
1212 case 3: // Return the inverted value of the LT bit of CR6.
1213 BitNo = 2; InvertBit = true;
1217 // Shift the bit into the low position.
1218 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
1219 DAG.getConstant(8-(3-BitNo), MVT::i32));
1221 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
1222 DAG.getConstant(1, MVT::i32));
1224 // If we are supposed to, toggle the bit.
1226 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
1227 DAG.getConstant(1, MVT::i32));
1231 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
1232 // Create a stack slot that is 16-byte aligned.
1233 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
1234 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
1235 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, MVT::i32);
1237 // Store the input value into Value#0 of the stack slot.
1238 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
1239 Op.getOperand(0), FIdx,DAG.getSrcValue(NULL));
1241 return DAG.getLoad(Op.getValueType(), Store, FIdx, DAG.getSrcValue(NULL));
1244 /// LowerOperation - Provide custom lowering hooks for some operations.
1246 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
1247 switch (Op.getOpcode()) {
1248 default: assert(0 && "Wasn't expecting to be able to lower this!");
1249 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
1250 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
1251 case ISD::SETCC: return LowerSETCC(Op, DAG);
1252 case ISD::VASTART: return LowerVASTART(Op, DAG, VarArgsFrameIndex);
1253 case ISD::RET: return LowerRET(Op, DAG);
1255 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
1256 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
1257 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
1259 // Lower 64-bit shifts.
1260 case ISD::SHL: return LowerSHL(Op, DAG);
1261 case ISD::SRL: return LowerSRL(Op, DAG);
1262 case ISD::SRA: return LowerSRA(Op, DAG);
1264 // Vector-related lowering.
1265 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
1266 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
1267 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1268 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
1273 //===----------------------------------------------------------------------===//
1274 // Other Lowering Code
1275 //===----------------------------------------------------------------------===//
1277 std::vector<SDOperand>
1278 PPCTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
1280 // add beautiful description of PPC stack frame format, or at least some docs
1282 MachineFunction &MF = DAG.getMachineFunction();
1283 MachineFrameInfo *MFI = MF.getFrameInfo();
1284 MachineBasicBlock& BB = MF.front();
1285 SSARegMap *RegMap = MF.getSSARegMap();
1286 std::vector<SDOperand> ArgValues;
1288 unsigned ArgOffset = 24;
1289 unsigned GPR_remaining = 8;
1290 unsigned FPR_remaining = 13;
1291 unsigned GPR_idx = 0, FPR_idx = 0;
1292 static const unsigned GPR[] = {
1293 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1294 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1296 static const unsigned FPR[] = {
1297 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1298 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1301 // Add DAG nodes to load the arguments... On entry to a function on PPC,
1302 // the arguments start at offset 24, although they are likely to be passed
1304 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
1305 SDOperand newroot, argt;
1307 bool needsLoad = false;
1308 bool ArgLive = !I->use_empty();
1309 MVT::ValueType ObjectVT = getValueType(I->getType());
1312 default: assert(0 && "Unhandled argument type!");
1318 if (!ArgLive) break;
1319 if (GPR_remaining > 0) {
1320 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1321 MF.addLiveIn(GPR[GPR_idx], VReg);
1322 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1323 if (ObjectVT != MVT::i32) {
1324 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
1326 argt = DAG.getNode(AssertOp, MVT::i32, argt,
1327 DAG.getValueType(ObjectVT));
1328 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
1336 if (!ArgLive) break;
1337 if (GPR_remaining > 0) {
1338 SDOperand argHi, argLo;
1339 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1340 MF.addLiveIn(GPR[GPR_idx], VReg);
1341 argHi = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1342 // If we have two or more remaining argument registers, then both halves
1343 // of the i64 can be sourced from there. Otherwise, the lower half will
1344 // have to come off the stack. This can happen when an i64 is preceded
1345 // by 28 bytes of arguments.
1346 if (GPR_remaining > 1) {
1347 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1348 MF.addLiveIn(GPR[GPR_idx+1], VReg);
1349 argLo = DAG.getCopyFromReg(argHi, VReg, MVT::i32);
1351 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
1352 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
1353 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
1354 DAG.getSrcValue(NULL));
1356 // Build the outgoing arg thingy
1357 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
1365 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
1367 if (FPR_remaining > 0) {
1373 if (FPR_remaining > 0) {
1375 if (ObjectVT == MVT::f32)
1376 VReg = RegMap->createVirtualRegister(&PPC::F4RCRegClass);
1378 VReg = RegMap->createVirtualRegister(&PPC::F8RCRegClass);
1379 MF.addLiveIn(FPR[FPR_idx], VReg);
1380 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(), VReg, ObjectVT);
1389 // We need to load the argument to a virtual register if we determined above
1390 // that we ran out of physical registers of the appropriate type
1392 unsigned SubregOffset = 0;
1393 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
1394 if (ObjectVT == MVT::i16) SubregOffset = 2;
1395 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
1396 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
1397 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
1398 DAG.getConstant(SubregOffset, MVT::i32));
1399 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
1400 DAG.getSrcValue(NULL));
1403 // Every 4 bytes of argument space consumes one of the GPRs available for
1404 // argument passing.
1405 if (GPR_remaining > 0) {
1406 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
1407 GPR_remaining -= delta;
1410 ArgOffset += ObjSize;
1412 DAG.setRoot(newroot.getValue(1));
1414 ArgValues.push_back(argt);
1417 // If the function takes variable number of arguments, make a frame index for
1418 // the start of the first vararg value... for expansion of llvm.va_start.
1420 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
1421 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
1422 // If this function is vararg, store any remaining integer argument regs
1423 // to their spots on the stack so that they may be loaded by deferencing the
1424 // result of va_next.
1425 std::vector<SDOperand> MemOps;
1426 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
1427 unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
1428 MF.addLiveIn(GPR[GPR_idx], VReg);
1429 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), VReg, MVT::i32);
1430 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
1431 Val, FIN, DAG.getSrcValue(NULL));
1432 MemOps.push_back(Store);
1433 // Increment the address by four for the next argument to store
1434 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
1435 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
1437 if (!MemOps.empty()) {
1438 MemOps.push_back(DAG.getRoot());
1439 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
1446 std::pair<SDOperand, SDOperand>
1447 PPCTargetLowering::LowerCallTo(SDOperand Chain,
1448 const Type *RetTy, bool isVarArg,
1449 unsigned CallingConv, bool isTailCall,
1450 SDOperand Callee, ArgListTy &Args,
1451 SelectionDAG &DAG) {
1452 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1453 // SelectExpr to use to put the arguments in the appropriate registers.
1454 std::vector<SDOperand> args_to_use;
1456 // Count how many bytes are to be pushed on the stack, including the linkage
1457 // area, and parameter passing area.
1458 unsigned NumBytes = 24;
1461 Chain = DAG.getCALLSEQ_START(Chain,
1462 DAG.getConstant(NumBytes, getPointerTy()));
1464 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1465 switch (getValueType(Args[i].second)) {
1466 default: assert(0 && "Unknown value type!");
1481 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
1482 // plus 32 bytes of argument space in case any called code gets funky on us.
1483 // (Required by ABI to support var arg)
1484 if (NumBytes < 56) NumBytes = 56;
1486 // Adjust the stack pointer for the new arguments...
1487 // These operations are automatically eliminated by the prolog/epilog pass
1488 Chain = DAG.getCALLSEQ_START(Chain,
1489 DAG.getConstant(NumBytes, getPointerTy()));
1491 // Set up a copy of the stack pointer for use loading and storing any
1492 // arguments that may not fit in the registers available for argument
1494 SDOperand StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1496 // Figure out which arguments are going to go in registers, and which in
1497 // memory. Also, if this is a vararg function, floating point operations
1498 // must be stored to our stack, and loaded into integer regs as well, if
1499 // any integer regs are available for argument passing.
1500 unsigned ArgOffset = 24;
1501 unsigned GPR_remaining = 8;
1502 unsigned FPR_remaining = 13;
1504 std::vector<SDOperand> MemOps;
1505 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
1506 // PtrOff will be used to store the current argument to the stack if a
1507 // register cannot be found for it.
1508 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
1509 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
1510 MVT::ValueType ArgVT = getValueType(Args[i].second);
1513 default: assert(0 && "Unexpected ValueType for argument!");
1517 // Promote the integer to 32 bits. If the input type is signed use a
1518 // sign extend, otherwise use a zero extend.
1519 if (Args[i].second->isSigned())
1520 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
1522 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
1525 if (GPR_remaining > 0) {
1526 args_to_use.push_back(Args[i].first);
1529 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1530 Args[i].first, PtrOff,
1531 DAG.getSrcValue(NULL)));
1536 // If we have one free GPR left, we can place the upper half of the i64
1537 // in it, and store the other half to the stack. If we have two or more
1538 // free GPRs, then we can pass both halves of the i64 in registers.
1539 if (GPR_remaining > 0) {
1540 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1541 Args[i].first, DAG.getConstant(1, MVT::i32));
1542 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
1543 Args[i].first, DAG.getConstant(0, MVT::i32));
1544 args_to_use.push_back(Hi);
1546 if (GPR_remaining > 0) {
1547 args_to_use.push_back(Lo);
1550 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
1551 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
1552 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1553 Lo, PtrOff, DAG.getSrcValue(NULL)));
1556 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1557 Args[i].first, PtrOff,
1558 DAG.getSrcValue(NULL)));
1564 if (FPR_remaining > 0) {
1565 args_to_use.push_back(Args[i].first);
1568 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
1569 Args[i].first, PtrOff,
1570 DAG.getSrcValue(NULL));
1571 MemOps.push_back(Store);
1572 // Float varargs are always shadowed in available integer registers
1573 if (GPR_remaining > 0) {
1574 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
1575 DAG.getSrcValue(NULL));
1576 MemOps.push_back(Load.getValue(1));
1577 args_to_use.push_back(Load);
1580 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
1581 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
1582 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
1583 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
1584 DAG.getSrcValue(NULL));
1585 MemOps.push_back(Load.getValue(1));
1586 args_to_use.push_back(Load);
1590 // If we have any FPRs remaining, we may also have GPRs remaining.
1591 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1593 if (GPR_remaining > 0) {
1594 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
1597 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
1598 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
1603 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
1604 Args[i].first, PtrOff,
1605 DAG.getSrcValue(NULL)));
1607 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
1611 if (!MemOps.empty())
1612 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
1615 std::vector<MVT::ValueType> RetVals;
1616 MVT::ValueType RetTyVT = getValueType(RetTy);
1617 MVT::ValueType ActualRetTyVT = RetTyVT;
1618 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
1619 ActualRetTyVT = MVT::i32; // Promote result to i32.
1621 if (RetTyVT == MVT::i64) {
1622 RetVals.push_back(MVT::i32);
1623 RetVals.push_back(MVT::i32);
1624 } else if (RetTyVT != MVT::isVoid) {
1625 RetVals.push_back(ActualRetTyVT);
1627 RetVals.push_back(MVT::Other);
1629 // If the callee is a GlobalAddress node (quite common, every direct call is)
1630 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1631 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1632 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
1634 std::vector<SDOperand> Ops;
1635 Ops.push_back(Chain);
1636 Ops.push_back(Callee);
1637 Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
1638 SDOperand TheCall = DAG.getNode(PPCISD::CALL, RetVals, Ops);
1639 Chain = TheCall.getValue(TheCall.Val->getNumValues()-1);
1640 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
1641 DAG.getConstant(NumBytes, getPointerTy()));
1642 SDOperand RetVal = TheCall;
1644 // If the result is a small value, add a note so that we keep track of the
1645 // information about whether it is sign or zero extended.
1646 if (RetTyVT != ActualRetTyVT) {
1647 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
1648 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
1649 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
1650 } else if (RetTyVT == MVT::i64) {
1651 RetVal = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, RetVal, RetVal.getValue(1));
1654 return std::make_pair(RetVal, Chain);
1658 PPCTargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
1659 MachineBasicBlock *BB) {
1660 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
1661 MI->getOpcode() == PPC::SELECT_CC_F4 ||
1662 MI->getOpcode() == PPC::SELECT_CC_F8 ||
1663 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
1664 "Unexpected instr type to insert");
1666 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1667 // control-flow pattern. The incoming instruction knows the destination vreg
1668 // to set, the condition code register to branch on, the true/false values to
1669 // select between, and a branch opcode to use.
1670 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1671 ilist<MachineBasicBlock>::iterator It = BB;
1677 // cmpTY ccX, r1, r2
1679 // fallthrough --> copy0MBB
1680 MachineBasicBlock *thisMBB = BB;
1681 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1682 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1683 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
1684 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1685 MachineFunction *F = BB->getParent();
1686 F->getBasicBlockList().insert(It, copy0MBB);
1687 F->getBasicBlockList().insert(It, sinkMBB);
1688 // Update machine-CFG edges by first adding all successors of the current
1689 // block to the new block which will contain the Phi node for the select.
1690 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
1691 e = BB->succ_end(); i != e; ++i)
1692 sinkMBB->addSuccessor(*i);
1693 // Next, remove all successors of the current block, and add the true
1694 // and fallthrough blocks as its successors.
1695 while(!BB->succ_empty())
1696 BB->removeSuccessor(BB->succ_begin());
1697 BB->addSuccessor(copy0MBB);
1698 BB->addSuccessor(sinkMBB);
1701 // %FalseValue = ...
1702 // # fallthrough to sinkMBB
1705 // Update machine-CFG edges
1706 BB->addSuccessor(sinkMBB);
1709 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1712 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
1713 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1714 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1716 delete MI; // The pseudo instruction is gone now.
1720 //===----------------------------------------------------------------------===//
1721 // Target Optimization Hooks
1722 //===----------------------------------------------------------------------===//
1724 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
1725 DAGCombinerInfo &DCI) const {
1726 TargetMachine &TM = getTargetMachine();
1727 SelectionDAG &DAG = DCI.DAG;
1728 switch (N->getOpcode()) {
1730 case ISD::SINT_TO_FP:
1731 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
1732 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
1733 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
1734 // We allow the src/dst to be either f32/f64, but the intermediate
1735 // type must be i64.
1736 if (N->getOperand(0).getValueType() == MVT::i64) {
1737 SDOperand Val = N->getOperand(0).getOperand(0);
1738 if (Val.getValueType() == MVT::f32) {
1739 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
1740 DCI.AddToWorklist(Val.Val);
1743 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
1744 DCI.AddToWorklist(Val.Val);
1745 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
1746 DCI.AddToWorklist(Val.Val);
1747 if (N->getValueType(0) == MVT::f32) {
1748 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val);
1749 DCI.AddToWorklist(Val.Val);
1752 } else if (N->getOperand(0).getValueType() == MVT::i32) {
1753 // If the intermediate type is i32, we can avoid the load/store here
1760 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
1761 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
1762 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
1763 N->getOperand(1).getValueType() == MVT::i32) {
1764 SDOperand Val = N->getOperand(1).getOperand(0);
1765 if (Val.getValueType() == MVT::f32) {
1766 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
1767 DCI.AddToWorklist(Val.Val);
1769 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
1770 DCI.AddToWorklist(Val.Val);
1772 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
1773 N->getOperand(2), N->getOperand(3));
1774 DCI.AddToWorklist(Val.Val);
1778 case PPCISD::VCMP: {
1779 // If a VCMPo node already exists with exactly the same operands as this
1780 // node, use its result instead of this node (VCMPo computes both a CR6 and
1781 // a normal output).
1783 if (!N->getOperand(0).hasOneUse() &&
1784 !N->getOperand(1).hasOneUse() &&
1785 !N->getOperand(2).hasOneUse()) {
1787 // Scan all of the users of the LHS, looking for VCMPo's that match.
1788 SDNode *VCMPoNode = 0;
1790 SDNode *LHSN = N->getOperand(0).Val;
1791 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
1793 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
1794 (*UI)->getOperand(1) == N->getOperand(1) &&
1795 (*UI)->getOperand(2) == N->getOperand(2) &&
1796 (*UI)->getOperand(0) == N->getOperand(0)) {
1801 // If there are non-zero uses of the flag value, use the VCMPo node!
1802 if (VCMPoNode && !VCMPoNode->hasNUsesOfValue(0, 1))
1803 return SDOperand(VCMPoNode, 0);
1812 //===----------------------------------------------------------------------===//
1813 // Inline Assembly Support
1814 //===----------------------------------------------------------------------===//
1816 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
1818 uint64_t &KnownZero,
1820 unsigned Depth) const {
1823 switch (Op.getOpcode()) {
1825 case ISD::INTRINSIC_WO_CHAIN: {
1826 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
1828 case Intrinsic::ppc_altivec_vcmpbfp_p:
1829 case Intrinsic::ppc_altivec_vcmpeqfp_p:
1830 case Intrinsic::ppc_altivec_vcmpequb_p:
1831 case Intrinsic::ppc_altivec_vcmpequh_p:
1832 case Intrinsic::ppc_altivec_vcmpequw_p:
1833 case Intrinsic::ppc_altivec_vcmpgefp_p:
1834 case Intrinsic::ppc_altivec_vcmpgtfp_p:
1835 case Intrinsic::ppc_altivec_vcmpgtsb_p:
1836 case Intrinsic::ppc_altivec_vcmpgtsh_p:
1837 case Intrinsic::ppc_altivec_vcmpgtsw_p:
1838 case Intrinsic::ppc_altivec_vcmpgtub_p:
1839 case Intrinsic::ppc_altivec_vcmpgtuh_p:
1840 case Intrinsic::ppc_altivec_vcmpgtuw_p:
1841 KnownZero = ~1U; // All bits but the low one are known to be zero.
1849 /// getConstraintType - Given a constraint letter, return the type of
1850 /// constraint it is for this target.
1851 PPCTargetLowering::ConstraintType
1852 PPCTargetLowering::getConstraintType(char ConstraintLetter) const {
1853 switch (ConstraintLetter) {
1860 return C_RegisterClass;
1862 return TargetLowering::getConstraintType(ConstraintLetter);
1866 std::vector<unsigned> PPCTargetLowering::
1867 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1868 MVT::ValueType VT) const {
1869 if (Constraint.size() == 1) {
1870 switch (Constraint[0]) { // GCC RS6000 Constraint Letters
1871 default: break; // Unknown constriant letter
1873 return make_vector<unsigned>(/*no R0*/ PPC::R1 , PPC::R2 , PPC::R3 ,
1874 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
1875 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
1876 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
1877 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
1878 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
1879 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
1880 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
1883 return make_vector<unsigned>(PPC::R0 , PPC::R1 , PPC::R2 , PPC::R3 ,
1884 PPC::R4 , PPC::R5 , PPC::R6 , PPC::R7 ,
1885 PPC::R8 , PPC::R9 , PPC::R10, PPC::R11,
1886 PPC::R12, PPC::R13, PPC::R14, PPC::R15,
1887 PPC::R16, PPC::R17, PPC::R18, PPC::R19,
1888 PPC::R20, PPC::R21, PPC::R22, PPC::R23,
1889 PPC::R24, PPC::R25, PPC::R26, PPC::R27,
1890 PPC::R28, PPC::R29, PPC::R30, PPC::R31,
1893 return make_vector<unsigned>(PPC::F0 , PPC::F1 , PPC::F2 , PPC::F3 ,
1894 PPC::F4 , PPC::F5 , PPC::F6 , PPC::F7 ,
1895 PPC::F8 , PPC::F9 , PPC::F10, PPC::F11,
1896 PPC::F12, PPC::F13, PPC::F14, PPC::F15,
1897 PPC::F16, PPC::F17, PPC::F18, PPC::F19,
1898 PPC::F20, PPC::F21, PPC::F22, PPC::F23,
1899 PPC::F24, PPC::F25, PPC::F26, PPC::F27,
1900 PPC::F28, PPC::F29, PPC::F30, PPC::F31,
1903 return make_vector<unsigned>(PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 ,
1904 PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
1905 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11,
1906 PPC::V12, PPC::V13, PPC::V14, PPC::V15,
1907 PPC::V16, PPC::V17, PPC::V18, PPC::V19,
1908 PPC::V20, PPC::V21, PPC::V22, PPC::V23,
1909 PPC::V24, PPC::V25, PPC::V26, PPC::V27,
1910 PPC::V28, PPC::V29, PPC::V30, PPC::V31,
1913 return make_vector<unsigned>(PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
1914 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7,
1919 return std::vector<unsigned>();
1922 // isOperandValidForConstraint
1923 bool PPCTargetLowering::
1924 isOperandValidForConstraint(SDOperand Op, char Letter) {
1935 if (!isa<ConstantSDNode>(Op)) return false; // Must be an immediate.
1936 unsigned Value = cast<ConstantSDNode>(Op)->getValue();
1938 default: assert(0 && "Unknown constraint letter!");
1939 case 'I': // "I" is a signed 16-bit constant.
1940 return (short)Value == (int)Value;
1941 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
1942 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
1943 return (short)Value == 0;
1944 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
1945 return (Value >> 16) == 0;
1946 case 'M': // "M" is a constant that is greater than 31.
1948 case 'N': // "N" is a positive constant that is an exact power of two.
1949 return (int)Value > 0 && isPowerOf2_32(Value);
1950 case 'O': // "O" is the constant zero.
1952 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
1953 return (short)-Value == (int)-Value;
1959 // Handle standard constraint letters.
1960 return TargetLowering::isOperandValidForConstraint(Op, Letter);
1963 /// isLegalAddressImmediate - Return true if the integer value can be used
1964 /// as the offset of the target addressing mode.
1965 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V) const {
1966 // PPC allows a sign-extended 16-bit immediate field.
1967 return (V > -(1 << 16) && V < (1 << 16)-1);