1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineLoopInfo.h"
28 #include "llvm/CodeGen/MachineRegisterInfo.h"
29 #include "llvm/CodeGen/SelectionDAG.h"
30 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 #include "llvm/IR/CallingConv.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/DerivedTypes.h"
34 #include "llvm/IR/Function.h"
35 #include "llvm/IR/Intrinsics.h"
36 #include "llvm/Support/CommandLine.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/MathExtras.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetOptions.h"
43 // FIXME: Remove this once soft-float is supported.
44 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
45 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
47 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
48 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
50 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
51 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
53 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
54 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
56 // FIXME: Remove this once the bug has been fixed!
57 extern cl::opt<bool> ANDIGlueBug;
59 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM)
61 Subtarget(*TM.getSubtargetImpl()) {
62 // Use _setjmp/_longjmp instead of setjmp/longjmp.
63 setUseUnderscoreSetJmp(true);
64 setUseUnderscoreLongJmp(true);
66 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
67 // arguments are at least 4/8 bytes aligned.
68 bool isPPC64 = Subtarget.isPPC64();
69 setMinStackArgumentAlignment(isPPC64 ? 8:4);
71 // Set up the register classes.
72 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
73 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
74 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
76 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
77 for (MVT VT : MVT::integer_valuetypes()) {
78 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
79 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
82 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
84 // PowerPC has pre-inc load and store's.
85 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
86 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
90 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
91 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
92 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
96 if (Subtarget.useCRBits()) {
97 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
99 if (isPPC64 || Subtarget.hasFPCVT()) {
100 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
101 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
102 isPPC64 ? MVT::i64 : MVT::i32);
103 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
104 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
105 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
108 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
111 // PowerPC does not support direct load / store of condition registers
112 setOperationAction(ISD::LOAD, MVT::i1, Custom);
113 setOperationAction(ISD::STORE, MVT::i1, Custom);
115 // FIXME: Remove this once the ANDI glue bug is fixed:
117 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
119 for (MVT VT : MVT::integer_valuetypes()) {
120 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
121 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
122 setTruncStoreAction(VT, MVT::i1, Expand);
125 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
128 // This is used in the ppcf128->int sequence. Note it has different semantics
129 // from FP_ROUND: that rounds to nearest, this rounds to zero.
130 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
132 // We do not currently implement these libm ops for PowerPC.
133 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
134 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
135 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
136 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
137 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
138 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
140 // PowerPC has no SREM/UREM instructions
141 setOperationAction(ISD::SREM, MVT::i32, Expand);
142 setOperationAction(ISD::UREM, MVT::i32, Expand);
143 setOperationAction(ISD::SREM, MVT::i64, Expand);
144 setOperationAction(ISD::UREM, MVT::i64, Expand);
146 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
147 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
148 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
149 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
150 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
151 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
152 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
153 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
154 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
156 // We don't support sin/cos/sqrt/fmod/pow
157 setOperationAction(ISD::FSIN , MVT::f64, Expand);
158 setOperationAction(ISD::FCOS , MVT::f64, Expand);
159 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
160 setOperationAction(ISD::FREM , MVT::f64, Expand);
161 setOperationAction(ISD::FPOW , MVT::f64, Expand);
162 setOperationAction(ISD::FMA , MVT::f64, Legal);
163 setOperationAction(ISD::FSIN , MVT::f32, Expand);
164 setOperationAction(ISD::FCOS , MVT::f32, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
166 setOperationAction(ISD::FREM , MVT::f32, Expand);
167 setOperationAction(ISD::FPOW , MVT::f32, Expand);
168 setOperationAction(ISD::FMA , MVT::f32, Legal);
170 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
172 // If we're enabling GP optimizations, use hardware square root
173 if (!Subtarget.hasFSQRT() &&
174 !(TM.Options.UnsafeFPMath &&
175 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
176 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
181 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
183 if (Subtarget.hasFCPSGN()) {
184 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
185 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
187 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
188 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
191 if (Subtarget.hasFPRND()) {
192 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
193 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
194 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
195 setOperationAction(ISD::FROUND, MVT::f64, Legal);
197 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
200 setOperationAction(ISD::FROUND, MVT::f32, Legal);
203 // PowerPC does not have BSWAP, CTPOP or CTTZ
204 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
205 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
206 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
207 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
208 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
209 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
210 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
211 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
213 if (Subtarget.hasPOPCNTD()) {
214 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
215 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
217 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
218 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
221 // PowerPC does not have ROTR
222 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
223 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
225 if (!Subtarget.useCRBits()) {
226 // PowerPC does not have Select
227 setOperationAction(ISD::SELECT, MVT::i32, Expand);
228 setOperationAction(ISD::SELECT, MVT::i64, Expand);
229 setOperationAction(ISD::SELECT, MVT::f32, Expand);
230 setOperationAction(ISD::SELECT, MVT::f64, Expand);
233 // PowerPC wants to turn select_cc of FP into fsel when possible.
234 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
235 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
237 // PowerPC wants to optimize integer setcc a bit
238 if (!Subtarget.useCRBits())
239 setOperationAction(ISD::SETCC, MVT::i32, Custom);
241 // PowerPC does not have BRCOND which requires SetCC
242 if (!Subtarget.useCRBits())
243 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
245 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
247 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
248 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
250 // PowerPC does not have [U|S]INT_TO_FP
251 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
252 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
254 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
255 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
256 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
257 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
259 // We cannot sextinreg(i1). Expand to shifts.
260 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
262 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
263 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
264 // support continuation, user-level threading, and etc.. As a result, no
265 // other SjLj exception interfaces are implemented and please don't build
266 // your own exception handling based on them.
267 // LLVM/Clang supports zero-cost DWARF exception handling.
268 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
269 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
271 // We want to legalize GlobalAddress and ConstantPool nodes into the
272 // appropriate instructions to materialize the address.
273 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
274 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
275 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
276 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
277 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
278 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
285 setOperationAction(ISD::TRAP, MVT::Other, Legal);
287 // TRAMPOLINE is custom lowered.
288 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
289 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
291 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
292 setOperationAction(ISD::VASTART , MVT::Other, Custom);
294 if (Subtarget.isSVR4ABI()) {
296 // VAARG always uses double-word chunks, so promote anything smaller.
297 setOperationAction(ISD::VAARG, MVT::i1, Promote);
298 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
299 setOperationAction(ISD::VAARG, MVT::i8, Promote);
300 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
301 setOperationAction(ISD::VAARG, MVT::i16, Promote);
302 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
303 setOperationAction(ISD::VAARG, MVT::i32, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::Other, Expand);
307 // VAARG is custom lowered with the 32-bit SVR4 ABI.
308 setOperationAction(ISD::VAARG, MVT::Other, Custom);
309 setOperationAction(ISD::VAARG, MVT::i64, Custom);
312 setOperationAction(ISD::VAARG, MVT::Other, Expand);
314 if (Subtarget.isSVR4ABI() && !isPPC64)
315 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
316 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
318 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
320 // Use the default implementation.
321 setOperationAction(ISD::VAEND , MVT::Other, Expand);
322 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
323 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
324 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
325 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
327 // We want to custom lower some of our intrinsics.
328 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
330 // To handle counter-based loop conditions.
331 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
333 // Comparisons that require checking two conditions.
334 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
335 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
336 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
337 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
338 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
339 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
340 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
347 if (Subtarget.has64BitSupport()) {
348 // They also have instructions for converting between i64 and fp.
349 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
350 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
351 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
352 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
353 // This is just the low 32 bits of a (signed) fp->i64 conversion.
354 // We cannot do this with Promote because i64 is not a legal type.
355 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
357 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
358 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
360 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
364 // With the instructions enabled under FPCVT, we can do everything.
365 if (Subtarget.hasFPCVT()) {
366 if (Subtarget.has64BitSupport()) {
367 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
368 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
369 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
370 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
379 if (Subtarget.use64BitRegs()) {
380 // 64-bit PowerPC implementations can support i64 types directly
381 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
382 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
383 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
384 // 64-bit PowerPC wants to expand i128 shifts itself.
385 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
386 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
387 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
389 // 32-bit PowerPC wants to expand i64 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
395 if (Subtarget.hasAltivec()) {
396 // First set operation action for all vector types to expand. Then we
397 // will selectively turn on ones that can be effectively codegen'd.
398 for (MVT VT : MVT::vector_valuetypes()) {
399 // add/sub are legal for all supported vector VT's.
400 setOperationAction(ISD::ADD , VT, Legal);
401 setOperationAction(ISD::SUB , VT, Legal);
403 // We promote all shuffles to v16i8.
404 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
405 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
407 // We promote all non-typed operations to v4i32.
408 setOperationAction(ISD::AND , VT, Promote);
409 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
410 setOperationAction(ISD::OR , VT, Promote);
411 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
412 setOperationAction(ISD::XOR , VT, Promote);
413 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
414 setOperationAction(ISD::LOAD , VT, Promote);
415 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
416 setOperationAction(ISD::SELECT, VT, Promote);
417 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
418 setOperationAction(ISD::STORE, VT, Promote);
419 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
421 // No other operations are legal.
422 setOperationAction(ISD::MUL , VT, Expand);
423 setOperationAction(ISD::SDIV, VT, Expand);
424 setOperationAction(ISD::SREM, VT, Expand);
425 setOperationAction(ISD::UDIV, VT, Expand);
426 setOperationAction(ISD::UREM, VT, Expand);
427 setOperationAction(ISD::FDIV, VT, Expand);
428 setOperationAction(ISD::FREM, VT, Expand);
429 setOperationAction(ISD::FNEG, VT, Expand);
430 setOperationAction(ISD::FSQRT, VT, Expand);
431 setOperationAction(ISD::FLOG, VT, Expand);
432 setOperationAction(ISD::FLOG10, VT, Expand);
433 setOperationAction(ISD::FLOG2, VT, Expand);
434 setOperationAction(ISD::FEXP, VT, Expand);
435 setOperationAction(ISD::FEXP2, VT, Expand);
436 setOperationAction(ISD::FSIN, VT, Expand);
437 setOperationAction(ISD::FCOS, VT, Expand);
438 setOperationAction(ISD::FABS, VT, Expand);
439 setOperationAction(ISD::FPOWI, VT, Expand);
440 setOperationAction(ISD::FFLOOR, VT, Expand);
441 setOperationAction(ISD::FCEIL, VT, Expand);
442 setOperationAction(ISD::FTRUNC, VT, Expand);
443 setOperationAction(ISD::FRINT, VT, Expand);
444 setOperationAction(ISD::FNEARBYINT, VT, Expand);
445 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
446 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
447 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
448 setOperationAction(ISD::MULHU, VT, Expand);
449 setOperationAction(ISD::MULHS, VT, Expand);
450 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
451 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
452 setOperationAction(ISD::UDIVREM, VT, Expand);
453 setOperationAction(ISD::SDIVREM, VT, Expand);
454 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
455 setOperationAction(ISD::FPOW, VT, Expand);
456 setOperationAction(ISD::BSWAP, VT, Expand);
457 setOperationAction(ISD::CTPOP, VT, Expand);
458 setOperationAction(ISD::CTLZ, VT, Expand);
459 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
460 setOperationAction(ISD::CTTZ, VT, Expand);
461 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
462 setOperationAction(ISD::VSELECT, VT, Expand);
463 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
465 for (MVT InnerVT : MVT::vector_valuetypes()) {
466 setTruncStoreAction(VT, InnerVT, Expand);
467 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
468 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
469 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
473 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
474 // with merges, splats, etc.
475 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
477 setOperationAction(ISD::AND , MVT::v4i32, Legal);
478 setOperationAction(ISD::OR , MVT::v4i32, Legal);
479 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
480 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
481 setOperationAction(ISD::SELECT, MVT::v4i32,
482 Subtarget.useCRBits() ? Legal : Expand);
483 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
484 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
485 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
486 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
487 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
488 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
489 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
490 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
491 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
493 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
494 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
495 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
496 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
498 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
499 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
501 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
502 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
503 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
506 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
507 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
508 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
510 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
511 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
513 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
514 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
515 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
516 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
518 // Altivec does not contain unordered floating-point compare instructions
519 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
520 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
521 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
522 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
524 if (Subtarget.hasVSX()) {
525 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
526 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
528 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
529 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
530 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
531 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
532 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
534 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
536 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
537 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
539 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
540 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
542 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
543 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
544 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
545 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
546 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
548 // Share the Altivec comparison restrictions.
549 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
550 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
551 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
552 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
554 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
555 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
557 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
559 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
561 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
562 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
564 // VSX v2i64 only supports non-arithmetic operations.
565 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
566 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
568 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
569 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
570 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
572 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
574 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
575 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
576 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
577 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
579 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
581 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
582 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
583 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
584 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
586 // Vector operation legalization checks the result type of
587 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
588 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
589 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
590 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
591 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
593 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
597 if (Subtarget.has64BitSupport())
598 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
600 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
603 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
604 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
607 setBooleanContents(ZeroOrOneBooleanContent);
608 // Altivec instructions set fields to all zeros or all ones.
609 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
612 // These libcalls are not available in 32-bit.
613 setLibcallName(RTLIB::SHL_I128, nullptr);
614 setLibcallName(RTLIB::SRL_I128, nullptr);
615 setLibcallName(RTLIB::SRA_I128, nullptr);
619 setStackPointerRegisterToSaveRestore(PPC::X1);
620 setExceptionPointerRegister(PPC::X3);
621 setExceptionSelectorRegister(PPC::X4);
623 setStackPointerRegisterToSaveRestore(PPC::R1);
624 setExceptionPointerRegister(PPC::R3);
625 setExceptionSelectorRegister(PPC::R4);
628 // We have target-specific dag combine patterns for the following nodes:
629 setTargetDAGCombine(ISD::SINT_TO_FP);
630 if (Subtarget.hasFPCVT())
631 setTargetDAGCombine(ISD::UINT_TO_FP);
632 setTargetDAGCombine(ISD::LOAD);
633 setTargetDAGCombine(ISD::STORE);
634 setTargetDAGCombine(ISD::BR_CC);
635 if (Subtarget.useCRBits())
636 setTargetDAGCombine(ISD::BRCOND);
637 setTargetDAGCombine(ISD::BSWAP);
638 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
639 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
640 setTargetDAGCombine(ISD::INTRINSIC_VOID);
642 setTargetDAGCombine(ISD::SIGN_EXTEND);
643 setTargetDAGCombine(ISD::ZERO_EXTEND);
644 setTargetDAGCombine(ISD::ANY_EXTEND);
646 if (Subtarget.useCRBits()) {
647 setTargetDAGCombine(ISD::TRUNCATE);
648 setTargetDAGCombine(ISD::SETCC);
649 setTargetDAGCombine(ISD::SELECT_CC);
652 // Use reciprocal estimates.
653 if (TM.Options.UnsafeFPMath) {
654 setTargetDAGCombine(ISD::FDIV);
655 setTargetDAGCombine(ISD::FSQRT);
658 // Darwin long double math library functions have $LDBL128 appended.
659 if (Subtarget.isDarwin()) {
660 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
661 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
662 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
663 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
664 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
665 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
666 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
667 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
668 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
669 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
672 // With 32 condition bits, we don't need to sink (and duplicate) compares
673 // aggressively in CodeGenPrep.
674 if (Subtarget.useCRBits())
675 setHasMultipleConditionRegisters();
677 setMinFunctionAlignment(2);
678 if (Subtarget.isDarwin())
679 setPrefFunctionAlignment(4);
681 switch (Subtarget.getDarwinDirective()) {
685 case PPC::DIR_E500mc:
694 setPrefFunctionAlignment(4);
695 setPrefLoopAlignment(4);
699 setInsertFencesForAtomic(true);
701 if (Subtarget.enableMachineScheduler())
702 setSchedulingPreference(Sched::Source);
704 setSchedulingPreference(Sched::Hybrid);
706 computeRegisterProperties();
708 // The Freescale cores do better with aggressive inlining of memcpy and
709 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
710 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
711 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
712 MaxStoresPerMemset = 32;
713 MaxStoresPerMemsetOptSize = 16;
714 MaxStoresPerMemcpy = 32;
715 MaxStoresPerMemcpyOptSize = 8;
716 MaxStoresPerMemmove = 32;
717 MaxStoresPerMemmoveOptSize = 8;
721 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
722 /// the desired ByVal argument alignment.
723 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
724 unsigned MaxMaxAlign) {
725 if (MaxAlign == MaxMaxAlign)
727 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
728 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
730 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
732 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
733 unsigned EltAlign = 0;
734 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
735 if (EltAlign > MaxAlign)
737 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
738 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
739 unsigned EltAlign = 0;
740 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
741 if (EltAlign > MaxAlign)
743 if (MaxAlign == MaxMaxAlign)
749 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
750 /// function arguments in the caller parameter area.
751 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
752 // Darwin passes everything on 4 byte boundary.
753 if (Subtarget.isDarwin())
756 // 16byte and wider vectors are passed on 16byte boundary.
757 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
758 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
759 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
760 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
764 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
766 default: return nullptr;
767 case PPCISD::FSEL: return "PPCISD::FSEL";
768 case PPCISD::FCFID: return "PPCISD::FCFID";
769 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
770 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
771 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
772 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
773 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
774 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
775 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
776 case PPCISD::FRE: return "PPCISD::FRE";
777 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
778 case PPCISD::STFIWX: return "PPCISD::STFIWX";
779 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
780 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
781 case PPCISD::VPERM: return "PPCISD::VPERM";
782 case PPCISD::CMPB: return "PPCISD::CMPB";
783 case PPCISD::Hi: return "PPCISD::Hi";
784 case PPCISD::Lo: return "PPCISD::Lo";
785 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
786 case PPCISD::LOAD: return "PPCISD::LOAD";
787 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
788 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
789 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
790 case PPCISD::SRL: return "PPCISD::SRL";
791 case PPCISD::SRA: return "PPCISD::SRA";
792 case PPCISD::SHL: return "PPCISD::SHL";
793 case PPCISD::CALL: return "PPCISD::CALL";
794 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
795 case PPCISD::CALL_TLS: return "PPCISD::CALL_TLS";
796 case PPCISD::CALL_NOP_TLS: return "PPCISD::CALL_NOP_TLS";
797 case PPCISD::MTCTR: return "PPCISD::MTCTR";
798 case PPCISD::BCTRL: return "PPCISD::BCTRL";
799 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
800 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
801 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
802 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
803 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
804 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
805 case PPCISD::VCMP: return "PPCISD::VCMP";
806 case PPCISD::VCMPo: return "PPCISD::VCMPo";
807 case PPCISD::LBRX: return "PPCISD::LBRX";
808 case PPCISD::STBRX: return "PPCISD::STBRX";
809 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
810 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
811 case PPCISD::LARX: return "PPCISD::LARX";
812 case PPCISD::STCX: return "PPCISD::STCX";
813 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
814 case PPCISD::BDNZ: return "PPCISD::BDNZ";
815 case PPCISD::BDZ: return "PPCISD::BDZ";
816 case PPCISD::MFFS: return "PPCISD::MFFS";
817 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
818 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
819 case PPCISD::CR6SET: return "PPCISD::CR6SET";
820 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
821 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
822 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
823 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
824 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
825 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
826 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
827 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
828 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
829 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
830 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
831 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
832 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
833 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
834 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
835 case PPCISD::SC: return "PPCISD::SC";
839 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
841 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
842 return VT.changeVectorElementTypeToInteger();
845 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
846 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
850 //===----------------------------------------------------------------------===//
851 // Node matching predicates, for use by the tblgen matching code.
852 //===----------------------------------------------------------------------===//
854 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
855 static bool isFloatingPointZero(SDValue Op) {
856 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
857 return CFP->getValueAPF().isZero();
858 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
859 // Maybe this has already been legalized into the constant pool?
860 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
861 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
862 return CFP->getValueAPF().isZero();
867 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
868 /// true if Op is undef or if it matches the specified value.
869 static bool isConstantOrUndef(int Op, int Val) {
870 return Op < 0 || Op == Val;
873 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
874 /// VPKUHUM instruction.
875 /// The ShuffleKind distinguishes between big-endian operations with
876 /// two different inputs (0), either-endian operations with two identical
877 /// inputs (1), and little-endian operantion with two different inputs (2).
878 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
879 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
881 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
882 if (ShuffleKind == 0) {
885 for (unsigned i = 0; i != 16; ++i)
886 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
888 } else if (ShuffleKind == 2) {
891 for (unsigned i = 0; i != 16; ++i)
892 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
894 } else if (ShuffleKind == 1) {
895 unsigned j = IsLE ? 0 : 1;
896 for (unsigned i = 0; i != 8; ++i)
897 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
898 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
904 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
905 /// VPKUWUM instruction.
906 /// The ShuffleKind distinguishes between big-endian operations with
907 /// two different inputs (0), either-endian operations with two identical
908 /// inputs (1), and little-endian operantion with two different inputs (2).
909 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
910 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
912 bool IsLE = DAG.getSubtarget().getDataLayout()->isLittleEndian();
913 if (ShuffleKind == 0) {
916 for (unsigned i = 0; i != 16; i += 2)
917 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
918 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
920 } else if (ShuffleKind == 2) {
923 for (unsigned i = 0; i != 16; i += 2)
924 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
925 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
927 } else if (ShuffleKind == 1) {
928 unsigned j = IsLE ? 0 : 2;
929 for (unsigned i = 0; i != 8; i += 2)
930 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
931 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
932 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
933 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
939 /// isVMerge - Common function, used to match vmrg* shuffles.
941 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
942 unsigned LHSStart, unsigned RHSStart) {
943 if (N->getValueType(0) != MVT::v16i8)
945 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
946 "Unsupported merge size!");
948 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
949 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
950 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
951 LHSStart+j+i*UnitSize) ||
952 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
953 RHSStart+j+i*UnitSize))
959 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
960 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
961 /// The ShuffleKind distinguishes between big-endian merges with two
962 /// different inputs (0), either-endian merges with two identical inputs (1),
963 /// and little-endian merges with two different inputs (2). For the latter,
964 /// the input operands are swapped (see PPCInstrAltivec.td).
965 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
966 unsigned ShuffleKind, SelectionDAG &DAG) {
967 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
968 if (ShuffleKind == 1) // unary
969 return isVMerge(N, UnitSize, 0, 0);
970 else if (ShuffleKind == 2) // swapped
971 return isVMerge(N, UnitSize, 0, 16);
975 if (ShuffleKind == 1) // unary
976 return isVMerge(N, UnitSize, 8, 8);
977 else if (ShuffleKind == 0) // normal
978 return isVMerge(N, UnitSize, 8, 24);
984 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
985 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
986 /// The ShuffleKind distinguishes between big-endian merges with two
987 /// different inputs (0), either-endian merges with two identical inputs (1),
988 /// and little-endian merges with two different inputs (2). For the latter,
989 /// the input operands are swapped (see PPCInstrAltivec.td).
990 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
991 unsigned ShuffleKind, SelectionDAG &DAG) {
992 if (DAG.getSubtarget().getDataLayout()->isLittleEndian()) {
993 if (ShuffleKind == 1) // unary
994 return isVMerge(N, UnitSize, 8, 8);
995 else if (ShuffleKind == 2) // swapped
996 return isVMerge(N, UnitSize, 8, 24);
1000 if (ShuffleKind == 1) // unary
1001 return isVMerge(N, UnitSize, 0, 0);
1002 else if (ShuffleKind == 0) // normal
1003 return isVMerge(N, UnitSize, 0, 16);
1010 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1011 /// amount, otherwise return -1.
1012 /// The ShuffleKind distinguishes between big-endian operations with two
1013 /// different inputs (0), either-endian operations with two identical inputs
1014 /// (1), and little-endian operations with two different inputs (2). For the
1015 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1016 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1017 SelectionDAG &DAG) {
1018 if (N->getValueType(0) != MVT::v16i8)
1021 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1023 // Find the first non-undef value in the shuffle mask.
1025 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1028 if (i == 16) return -1; // all undef.
1030 // Otherwise, check to see if the rest of the elements are consecutively
1031 // numbered from this value.
1032 unsigned ShiftAmt = SVOp->getMaskElt(i);
1033 if (ShiftAmt < i) return -1;
1036 bool isLE = DAG.getTarget().getSubtargetImpl()->getDataLayout()->
1039 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1040 // Check the rest of the elements to see if they are consecutive.
1041 for (++i; i != 16; ++i)
1042 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1044 } else if (ShuffleKind == 1) {
1045 // Check the rest of the elements to see if they are consecutive.
1046 for (++i; i != 16; ++i)
1047 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1052 if (ShuffleKind == 2 && isLE)
1053 ShiftAmt = 16 - ShiftAmt;
1058 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1059 /// specifies a splat of a single element that is suitable for input to
1060 /// VSPLTB/VSPLTH/VSPLTW.
1061 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1062 assert(N->getValueType(0) == MVT::v16i8 &&
1063 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1065 // This is a splat operation if each element of the permute is the same, and
1066 // if the value doesn't reference the second vector.
1067 unsigned ElementBase = N->getMaskElt(0);
1069 // FIXME: Handle UNDEF elements too!
1070 if (ElementBase >= 16)
1073 // Check that the indices are consecutive, in the case of a multi-byte element
1074 // splatted with a v16i8 mask.
1075 for (unsigned i = 1; i != EltSize; ++i)
1076 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1079 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1080 if (N->getMaskElt(i) < 0) continue;
1081 for (unsigned j = 0; j != EltSize; ++j)
1082 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1088 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1090 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1091 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1093 APInt APVal, APUndef;
1097 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1098 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1099 return CFP->getValueAPF().isNegZero();
1104 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1105 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1106 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1107 SelectionDAG &DAG) {
1108 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1109 assert(isSplatShuffleMask(SVOp, EltSize));
1110 if (DAG.getSubtarget().getDataLayout()->isLittleEndian())
1111 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1113 return SVOp->getMaskElt(0) / EltSize;
1116 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1117 /// by using a vspltis[bhw] instruction of the specified element size, return
1118 /// the constant being splatted. The ByteSize field indicates the number of
1119 /// bytes of each element [124] -> [bhw].
1120 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1121 SDValue OpVal(nullptr, 0);
1123 // If ByteSize of the splat is bigger than the element size of the
1124 // build_vector, then we have a case where we are checking for a splat where
1125 // multiple elements of the buildvector are folded together into a single
1126 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1127 unsigned EltSize = 16/N->getNumOperands();
1128 if (EltSize < ByteSize) {
1129 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1130 SDValue UniquedVals[4];
1131 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1133 // See if all of the elements in the buildvector agree across.
1134 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1135 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1136 // If the element isn't a constant, bail fully out.
1137 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1140 if (!UniquedVals[i&(Multiple-1)].getNode())
1141 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1142 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1143 return SDValue(); // no match.
1146 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1147 // either constant or undef values that are identical for each chunk. See
1148 // if these chunks can form into a larger vspltis*.
1150 // Check to see if all of the leading entries are either 0 or -1. If
1151 // neither, then this won't fit into the immediate field.
1152 bool LeadingZero = true;
1153 bool LeadingOnes = true;
1154 for (unsigned i = 0; i != Multiple-1; ++i) {
1155 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1157 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1158 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1160 // Finally, check the least significant entry.
1162 if (!UniquedVals[Multiple-1].getNode())
1163 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1164 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1166 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1169 if (!UniquedVals[Multiple-1].getNode())
1170 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1171 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1172 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1173 return DAG.getTargetConstant(Val, MVT::i32);
1179 // Check to see if this buildvec has a single non-undef value in its elements.
1180 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1181 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1182 if (!OpVal.getNode())
1183 OpVal = N->getOperand(i);
1184 else if (OpVal != N->getOperand(i))
1188 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1190 unsigned ValSizeInBytes = EltSize;
1192 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1193 Value = CN->getZExtValue();
1194 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1195 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1196 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1199 // If the splat value is larger than the element value, then we can never do
1200 // this splat. The only case that we could fit the replicated bits into our
1201 // immediate field for would be zero, and we prefer to use vxor for it.
1202 if (ValSizeInBytes < ByteSize) return SDValue();
1204 // If the element value is larger than the splat value, cut it in half and
1205 // check to see if the two halves are equal. Continue doing this until we
1206 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1207 while (ValSizeInBytes > ByteSize) {
1208 ValSizeInBytes >>= 1;
1210 // If the top half equals the bottom half, we're still ok.
1211 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1212 (Value & ((1 << (8*ValSizeInBytes))-1)))
1216 // Properly sign extend the value.
1217 int MaskVal = SignExtend32(Value, ByteSize * 8);
1219 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1220 if (MaskVal == 0) return SDValue();
1222 // Finally, if this value fits in a 5 bit sext field, return it
1223 if (SignExtend32<5>(MaskVal) == MaskVal)
1224 return DAG.getTargetConstant(MaskVal, MVT::i32);
1228 //===----------------------------------------------------------------------===//
1229 // Addressing Mode Selection
1230 //===----------------------------------------------------------------------===//
1232 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1233 /// or 64-bit immediate, and if the value can be accurately represented as a
1234 /// sign extension from a 16-bit value. If so, this returns true and the
1236 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1237 if (!isa<ConstantSDNode>(N))
1240 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1241 if (N->getValueType(0) == MVT::i32)
1242 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1244 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1246 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1247 return isIntS16Immediate(Op.getNode(), Imm);
1251 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1252 /// can be represented as an indexed [r+r] operation. Returns false if it
1253 /// can be more efficiently represented with [r+imm].
1254 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1256 SelectionDAG &DAG) const {
1258 if (N.getOpcode() == ISD::ADD) {
1259 if (isIntS16Immediate(N.getOperand(1), imm))
1260 return false; // r+i
1261 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1262 return false; // r+i
1264 Base = N.getOperand(0);
1265 Index = N.getOperand(1);
1267 } else if (N.getOpcode() == ISD::OR) {
1268 if (isIntS16Immediate(N.getOperand(1), imm))
1269 return false; // r+i can fold it if we can.
1271 // If this is an or of disjoint bitfields, we can codegen this as an add
1272 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1274 APInt LHSKnownZero, LHSKnownOne;
1275 APInt RHSKnownZero, RHSKnownOne;
1276 DAG.computeKnownBits(N.getOperand(0),
1277 LHSKnownZero, LHSKnownOne);
1279 if (LHSKnownZero.getBoolValue()) {
1280 DAG.computeKnownBits(N.getOperand(1),
1281 RHSKnownZero, RHSKnownOne);
1282 // If all of the bits are known zero on the LHS or RHS, the add won't
1284 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1285 Base = N.getOperand(0);
1286 Index = N.getOperand(1);
1295 // If we happen to be doing an i64 load or store into a stack slot that has
1296 // less than a 4-byte alignment, then the frame-index elimination may need to
1297 // use an indexed load or store instruction (because the offset may not be a
1298 // multiple of 4). The extra register needed to hold the offset comes from the
1299 // register scavenger, and it is possible that the scavenger will need to use
1300 // an emergency spill slot. As a result, we need to make sure that a spill slot
1301 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1303 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1304 // FIXME: This does not handle the LWA case.
1308 // NOTE: We'll exclude negative FIs here, which come from argument
1309 // lowering, because there are no known test cases triggering this problem
1310 // using packed structures (or similar). We can remove this exclusion if
1311 // we find such a test case. The reason why this is so test-case driven is
1312 // because this entire 'fixup' is only to prevent crashes (from the
1313 // register scavenger) on not-really-valid inputs. For example, if we have:
1315 // %b = bitcast i1* %a to i64*
1316 // store i64* a, i64 b
1317 // then the store should really be marked as 'align 1', but is not. If it
1318 // were marked as 'align 1' then the indexed form would have been
1319 // instruction-selected initially, and the problem this 'fixup' is preventing
1320 // won't happen regardless.
1324 MachineFunction &MF = DAG.getMachineFunction();
1325 MachineFrameInfo *MFI = MF.getFrameInfo();
1327 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1331 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1332 FuncInfo->setHasNonRISpills();
1335 /// Returns true if the address N can be represented by a base register plus
1336 /// a signed 16-bit displacement [r+imm], and if it is not better
1337 /// represented as reg+reg. If Aligned is true, only accept displacements
1338 /// suitable for STD and friends, i.e. multiples of 4.
1339 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1342 bool Aligned) const {
1343 // FIXME dl should come from parent load or store, not from address
1345 // If this can be more profitably realized as r+r, fail.
1346 if (SelectAddressRegReg(N, Disp, Base, DAG))
1349 if (N.getOpcode() == ISD::ADD) {
1351 if (isIntS16Immediate(N.getOperand(1), imm) &&
1352 (!Aligned || (imm & 3) == 0)) {
1353 Disp = DAG.getTargetConstant(imm, N.getValueType());
1354 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1355 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1356 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1358 Base = N.getOperand(0);
1360 return true; // [r+i]
1361 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1362 // Match LOAD (ADD (X, Lo(G))).
1363 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1364 && "Cannot handle constant offsets yet!");
1365 Disp = N.getOperand(1).getOperand(0); // The global address.
1366 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1367 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1368 Disp.getOpcode() == ISD::TargetConstantPool ||
1369 Disp.getOpcode() == ISD::TargetJumpTable);
1370 Base = N.getOperand(0);
1371 return true; // [&g+r]
1373 } else if (N.getOpcode() == ISD::OR) {
1375 if (isIntS16Immediate(N.getOperand(1), imm) &&
1376 (!Aligned || (imm & 3) == 0)) {
1377 // If this is an or of disjoint bitfields, we can codegen this as an add
1378 // (for better address arithmetic) if the LHS and RHS of the OR are
1379 // provably disjoint.
1380 APInt LHSKnownZero, LHSKnownOne;
1381 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1383 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1384 // If all of the bits are known zero on the LHS or RHS, the add won't
1386 if (FrameIndexSDNode *FI =
1387 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1388 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1389 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1391 Base = N.getOperand(0);
1393 Disp = DAG.getTargetConstant(imm, N.getValueType());
1397 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1398 // Loading from a constant address.
1400 // If this address fits entirely in a 16-bit sext immediate field, codegen
1403 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1404 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1405 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1406 CN->getValueType(0));
1410 // Handle 32-bit sext immediates with LIS + addr mode.
1411 if ((CN->getValueType(0) == MVT::i32 ||
1412 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1413 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1414 int Addr = (int)CN->getZExtValue();
1416 // Otherwise, break this down into an LIS + disp.
1417 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1419 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1420 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1421 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1426 Disp = DAG.getTargetConstant(0, getPointerTy());
1427 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1428 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1429 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1432 return true; // [r+0]
1435 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1436 /// represented as an indexed [r+r] operation.
1437 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1439 SelectionDAG &DAG) const {
1440 // Check to see if we can easily represent this as an [r+r] address. This
1441 // will fail if it thinks that the address is more profitably represented as
1442 // reg+imm, e.g. where imm = 0.
1443 if (SelectAddressRegReg(N, Base, Index, DAG))
1446 // If the operand is an addition, always emit this as [r+r], since this is
1447 // better (for code size, and execution, as the memop does the add for free)
1448 // than emitting an explicit add.
1449 if (N.getOpcode() == ISD::ADD) {
1450 Base = N.getOperand(0);
1451 Index = N.getOperand(1);
1455 // Otherwise, do it the hard way, using R0 as the base register.
1456 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1462 /// getPreIndexedAddressParts - returns true by value, base pointer and
1463 /// offset pointer and addressing mode by reference if the node's address
1464 /// can be legally represented as pre-indexed load / store address.
1465 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1467 ISD::MemIndexedMode &AM,
1468 SelectionDAG &DAG) const {
1469 if (DisablePPCPreinc) return false;
1475 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1476 Ptr = LD->getBasePtr();
1477 VT = LD->getMemoryVT();
1478 Alignment = LD->getAlignment();
1479 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1480 Ptr = ST->getBasePtr();
1481 VT = ST->getMemoryVT();
1482 Alignment = ST->getAlignment();
1487 // PowerPC doesn't have preinc load/store instructions for vectors.
1491 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1493 // Common code will reject creating a pre-inc form if the base pointer
1494 // is a frame index, or if N is a store and the base pointer is either
1495 // the same as or a predecessor of the value being stored. Check for
1496 // those situations here, and try with swapped Base/Offset instead.
1499 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1502 SDValue Val = cast<StoreSDNode>(N)->getValue();
1503 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1508 std::swap(Base, Offset);
1514 // LDU/STU can only handle immediates that are a multiple of 4.
1515 if (VT != MVT::i64) {
1516 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1519 // LDU/STU need an address with at least 4-byte alignment.
1523 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1527 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1528 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1529 // sext i32 to i64 when addr mode is r+i.
1530 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1531 LD->getExtensionType() == ISD::SEXTLOAD &&
1532 isa<ConstantSDNode>(Offset))
1540 //===----------------------------------------------------------------------===//
1541 // LowerOperation implementation
1542 //===----------------------------------------------------------------------===//
1544 /// GetLabelAccessInfo - Return true if we should reference labels using a
1545 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1546 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1547 unsigned &LoOpFlags,
1548 const GlobalValue *GV = nullptr) {
1549 HiOpFlags = PPCII::MO_HA;
1550 LoOpFlags = PPCII::MO_LO;
1552 // Don't use the pic base if not in PIC relocation model.
1553 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1556 HiOpFlags |= PPCII::MO_PIC_FLAG;
1557 LoOpFlags |= PPCII::MO_PIC_FLAG;
1560 // If this is a reference to a global value that requires a non-lazy-ptr, make
1561 // sure that instruction lowering adds it.
1562 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1563 HiOpFlags |= PPCII::MO_NLP_FLAG;
1564 LoOpFlags |= PPCII::MO_NLP_FLAG;
1566 if (GV->hasHiddenVisibility()) {
1567 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1568 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1575 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1576 SelectionDAG &DAG) {
1577 EVT PtrVT = HiPart.getValueType();
1578 SDValue Zero = DAG.getConstant(0, PtrVT);
1581 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1582 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1584 // With PIC, the first instruction is actually "GR+hi(&G)".
1586 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1587 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1589 // Generate non-pic code that has direct accesses to the constant pool.
1590 // The address of the global is just (hi(&g)+lo(&g)).
1591 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1594 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1595 SelectionDAG &DAG) const {
1596 EVT PtrVT = Op.getValueType();
1597 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1598 const Constant *C = CP->getConstVal();
1600 // 64-bit SVR4 ABI code is always position-independent.
1601 // The actual address of the GlobalValue is stored in the TOC.
1602 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1603 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1604 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1605 DAG.getRegister(PPC::X2, MVT::i64));
1608 unsigned MOHiFlag, MOLoFlag;
1609 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1611 if (isPIC && Subtarget.isSVR4ABI()) {
1612 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
1613 PPCII::MO_PIC_FLAG);
1615 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1616 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1620 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1622 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1623 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1626 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1627 EVT PtrVT = Op.getValueType();
1628 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1630 // 64-bit SVR4 ABI code is always position-independent.
1631 // The actual address of the GlobalValue is stored in the TOC.
1632 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1633 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1634 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1635 DAG.getRegister(PPC::X2, MVT::i64));
1638 unsigned MOHiFlag, MOLoFlag;
1639 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1641 if (isPIC && Subtarget.isSVR4ABI()) {
1642 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
1643 PPCII::MO_PIC_FLAG);
1645 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), PtrVT, GA,
1646 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT));
1649 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1650 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1651 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1654 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1655 SelectionDAG &DAG) const {
1656 EVT PtrVT = Op.getValueType();
1657 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
1658 const BlockAddress *BA = BASDN->getBlockAddress();
1660 // 64-bit SVR4 ABI code is always position-independent.
1661 // The actual BlockAddress is stored in the TOC.
1662 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1663 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
1664 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(BASDN), MVT::i64, GA,
1665 DAG.getRegister(PPC::X2, MVT::i64));
1668 unsigned MOHiFlag, MOLoFlag;
1669 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1670 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1671 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1672 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1675 // Generate a call to __tls_get_addr for the given GOT entry Op.
1676 std::pair<SDValue,SDValue>
1677 PPCTargetLowering::lowerTLSCall(SDValue Op, SDLoc dl,
1678 SelectionDAG &DAG) const {
1680 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
1681 TargetLowering::ArgListTy Args;
1682 TargetLowering::ArgListEntry Entry;
1684 Entry.Ty = IntPtrTy;
1685 Args.push_back(Entry);
1687 TargetLowering::CallLoweringInfo CLI(DAG);
1688 CLI.setDebugLoc(dl).setChain(DAG.getEntryNode())
1689 .setCallee(CallingConv::C, IntPtrTy,
1690 DAG.getTargetExternalSymbol("__tls_get_addr", getPointerTy()),
1691 std::move(Args), 0);
1693 return LowerCallTo(CLI);
1696 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1697 SelectionDAG &DAG) const {
1699 // FIXME: TLS addresses currently use medium model code sequences,
1700 // which is the most useful form. Eventually support for small and
1701 // large models could be added if users need it, at the cost of
1702 // additional complexity.
1703 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1705 const GlobalValue *GV = GA->getGlobal();
1706 EVT PtrVT = getPointerTy();
1707 bool is64bit = Subtarget.isPPC64();
1708 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
1709 PICLevel::Level picLevel = M->getPICLevel();
1711 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1713 if (Model == TLSModel::LocalExec) {
1714 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1715 PPCII::MO_TPREL_HA);
1716 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1717 PPCII::MO_TPREL_LO);
1718 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1719 is64bit ? MVT::i64 : MVT::i32);
1720 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1721 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1724 if (Model == TLSModel::InitialExec) {
1725 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1726 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1730 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1731 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1732 PtrVT, GOTReg, TGA);
1734 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1735 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1736 PtrVT, TGA, GOTPtr);
1737 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1740 if (Model == TLSModel::GeneralDynamic) {
1741 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1745 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1746 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1749 if (picLevel == PICLevel::Small)
1750 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1752 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1754 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1756 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1757 return CallResult.first;
1760 if (Model == TLSModel::LocalDynamic) {
1761 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1765 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1766 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1769 if (picLevel == PICLevel::Small)
1770 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
1772 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
1774 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1776 std::pair<SDValue, SDValue> CallResult = lowerTLSCall(GOTEntry, dl, DAG);
1777 SDValue TLSAddr = CallResult.first;
1778 SDValue Chain = CallResult.second;
1779 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1780 Chain, TLSAddr, TGA);
1781 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1784 llvm_unreachable("Unknown TLS model!");
1787 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1788 SelectionDAG &DAG) const {
1789 EVT PtrVT = Op.getValueType();
1790 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1792 const GlobalValue *GV = GSDN->getGlobal();
1794 // 64-bit SVR4 ABI code is always position-independent.
1795 // The actual address of the GlobalValue is stored in the TOC.
1796 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1797 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1798 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1799 DAG.getRegister(PPC::X2, MVT::i64));
1802 unsigned MOHiFlag, MOLoFlag;
1803 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1805 if (isPIC && Subtarget.isSVR4ABI()) {
1806 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
1808 PPCII::MO_PIC_FLAG);
1809 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i32, GA,
1810 DAG.getNode(PPCISD::GlobalBaseReg, DL, MVT::i32));
1814 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1816 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1818 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1820 // If the global reference is actually to a non-lazy-pointer, we have to do an
1821 // extra load to get the address of the global.
1822 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1823 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1824 false, false, false, 0);
1828 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1829 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1832 if (Op.getValueType() == MVT::v2i64) {
1833 // When the operands themselves are v2i64 values, we need to do something
1834 // special because VSX has no underlying comparison operations for these.
1835 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1836 // Equality can be handled by casting to the legal type for Altivec
1837 // comparisons, everything else needs to be expanded.
1838 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1839 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1840 DAG.getSetCC(dl, MVT::v4i32,
1841 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1842 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1849 // We handle most of these in the usual way.
1853 // If we're comparing for equality to zero, expose the fact that this is
1854 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1855 // fold the new nodes.
1856 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1857 if (C->isNullValue() && CC == ISD::SETEQ) {
1858 EVT VT = Op.getOperand(0).getValueType();
1859 SDValue Zext = Op.getOperand(0);
1860 if (VT.bitsLT(MVT::i32)) {
1862 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1864 unsigned Log2b = Log2_32(VT.getSizeInBits());
1865 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1866 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1867 DAG.getConstant(Log2b, MVT::i32));
1868 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1870 // Leave comparisons against 0 and -1 alone for now, since they're usually
1871 // optimized. FIXME: revisit this when we can custom lower all setcc
1873 if (C->isAllOnesValue() || C->isNullValue())
1877 // If we have an integer seteq/setne, turn it into a compare against zero
1878 // by xor'ing the rhs with the lhs, which is faster than setting a
1879 // condition register, reading it back out, and masking the correct bit. The
1880 // normal approach here uses sub to do this instead of xor. Using xor exposes
1881 // the result to other bit-twiddling opportunities.
1882 EVT LHSVT = Op.getOperand(0).getValueType();
1883 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1884 EVT VT = Op.getValueType();
1885 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1887 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1892 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1893 const PPCSubtarget &Subtarget) const {
1894 SDNode *Node = Op.getNode();
1895 EVT VT = Node->getValueType(0);
1896 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1897 SDValue InChain = Node->getOperand(0);
1898 SDValue VAListPtr = Node->getOperand(1);
1899 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1902 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1905 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1906 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1907 false, false, false, 0);
1908 InChain = GprIndex.getValue(1);
1910 if (VT == MVT::i64) {
1911 // Check if GprIndex is even
1912 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1913 DAG.getConstant(1, MVT::i32));
1914 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1915 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1916 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1917 DAG.getConstant(1, MVT::i32));
1918 // Align GprIndex to be even if it isn't
1919 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1923 // fpr index is 1 byte after gpr
1924 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1925 DAG.getConstant(1, MVT::i32));
1928 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1929 FprPtr, MachinePointerInfo(SV), MVT::i8,
1930 false, false, false, 0);
1931 InChain = FprIndex.getValue(1);
1933 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1934 DAG.getConstant(8, MVT::i32));
1936 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1937 DAG.getConstant(4, MVT::i32));
1940 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1941 MachinePointerInfo(), false, false,
1943 InChain = OverflowArea.getValue(1);
1945 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1946 MachinePointerInfo(), false, false,
1948 InChain = RegSaveArea.getValue(1);
1950 // select overflow_area if index > 8
1951 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1952 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1954 // adjustment constant gpr_index * 4/8
1955 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1956 VT.isInteger() ? GprIndex : FprIndex,
1957 DAG.getConstant(VT.isInteger() ? 4 : 8,
1960 // OurReg = RegSaveArea + RegConstant
1961 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1964 // Floating types are 32 bytes into RegSaveArea
1965 if (VT.isFloatingPoint())
1966 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1967 DAG.getConstant(32, MVT::i32));
1969 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1970 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1971 VT.isInteger() ? GprIndex : FprIndex,
1972 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1975 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1976 VT.isInteger() ? VAListPtr : FprPtr,
1977 MachinePointerInfo(SV),
1978 MVT::i8, false, false, 0);
1980 // determine if we should load from reg_save_area or overflow_area
1981 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1983 // increase overflow_area by 4/8 if gpr/fpr > 8
1984 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1985 DAG.getConstant(VT.isInteger() ? 4 : 8,
1988 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1991 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1993 MachinePointerInfo(),
1994 MVT::i32, false, false, 0);
1996 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1997 false, false, false, 0);
2000 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2001 const PPCSubtarget &Subtarget) const {
2002 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2004 // We have to copy the entire va_list struct:
2005 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2006 return DAG.getMemcpy(Op.getOperand(0), Op,
2007 Op.getOperand(1), Op.getOperand(2),
2008 DAG.getConstant(12, MVT::i32), 8, false, true,
2009 MachinePointerInfo(), MachinePointerInfo());
2012 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2013 SelectionDAG &DAG) const {
2014 return Op.getOperand(0);
2017 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2018 SelectionDAG &DAG) const {
2019 SDValue Chain = Op.getOperand(0);
2020 SDValue Trmp = Op.getOperand(1); // trampoline
2021 SDValue FPtr = Op.getOperand(2); // nested function
2022 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2025 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2026 bool isPPC64 = (PtrVT == MVT::i64);
2028 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
2031 TargetLowering::ArgListTy Args;
2032 TargetLowering::ArgListEntry Entry;
2034 Entry.Ty = IntPtrTy;
2035 Entry.Node = Trmp; Args.push_back(Entry);
2037 // TrampSize == (isPPC64 ? 48 : 40);
2038 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
2039 isPPC64 ? MVT::i64 : MVT::i32);
2040 Args.push_back(Entry);
2042 Entry.Node = FPtr; Args.push_back(Entry);
2043 Entry.Node = Nest; Args.push_back(Entry);
2045 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2046 TargetLowering::CallLoweringInfo CLI(DAG);
2047 CLI.setDebugLoc(dl).setChain(Chain)
2048 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2049 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2050 std::move(Args), 0);
2052 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2053 return CallResult.second;
2056 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2057 const PPCSubtarget &Subtarget) const {
2058 MachineFunction &MF = DAG.getMachineFunction();
2059 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2063 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2064 // vastart just stores the address of the VarArgsFrameIndex slot into the
2065 // memory location argument.
2066 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2067 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2068 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2069 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2070 MachinePointerInfo(SV),
2074 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2075 // We suppose the given va_list is already allocated.
2078 // char gpr; /* index into the array of 8 GPRs
2079 // * stored in the register save area
2080 // * gpr=0 corresponds to r3,
2081 // * gpr=1 to r4, etc.
2083 // char fpr; /* index into the array of 8 FPRs
2084 // * stored in the register save area
2085 // * fpr=0 corresponds to f1,
2086 // * fpr=1 to f2, etc.
2088 // char *overflow_arg_area;
2089 // /* location on stack that holds
2090 // * the next overflow argument
2092 // char *reg_save_area;
2093 // /* where r3:r10 and f1:f8 (if saved)
2099 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
2100 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
2103 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2105 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2107 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2110 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2111 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2113 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2114 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2116 uint64_t FPROffset = 1;
2117 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2119 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2121 // Store first byte : number of int regs
2122 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2124 MachinePointerInfo(SV),
2125 MVT::i8, false, false, 0);
2126 uint64_t nextOffset = FPROffset;
2127 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2130 // Store second byte : number of float regs
2131 SDValue secondStore =
2132 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2133 MachinePointerInfo(SV, nextOffset), MVT::i8,
2135 nextOffset += StackOffset;
2136 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2138 // Store second word : arguments given on stack
2139 SDValue thirdStore =
2140 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2141 MachinePointerInfo(SV, nextOffset),
2143 nextOffset += FrameOffset;
2144 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2146 // Store third word : arguments given in registers
2147 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2148 MachinePointerInfo(SV, nextOffset),
2153 #include "PPCGenCallingConv.inc"
2155 // Function whose sole purpose is to kill compiler warnings
2156 // stemming from unused functions included from PPCGenCallingConv.inc.
2157 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2158 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2161 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2162 CCValAssign::LocInfo &LocInfo,
2163 ISD::ArgFlagsTy &ArgFlags,
2168 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2170 CCValAssign::LocInfo &LocInfo,
2171 ISD::ArgFlagsTy &ArgFlags,
2173 static const MCPhysReg ArgRegs[] = {
2174 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2175 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2177 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2179 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2181 // Skip one register if the first unallocated register has an even register
2182 // number and there are still argument registers available which have not been
2183 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2184 // need to skip a register if RegNum is odd.
2185 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2186 State.AllocateReg(ArgRegs[RegNum]);
2189 // Always return false here, as this function only makes sure that the first
2190 // unallocated register has an odd register number and does not actually
2191 // allocate a register for the current argument.
2195 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2197 CCValAssign::LocInfo &LocInfo,
2198 ISD::ArgFlagsTy &ArgFlags,
2200 static const MCPhysReg ArgRegs[] = {
2201 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2205 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2207 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2209 // If there is only one Floating-point register left we need to put both f64
2210 // values of a split ppc_fp128 value on the stack.
2211 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2212 State.AllocateReg(ArgRegs[RegNum]);
2215 // Always return false here, as this function only makes sure that the two f64
2216 // values a ppc_fp128 value is split into are both passed in registers or both
2217 // passed on the stack and does not actually allocate a register for the
2218 // current argument.
2222 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2224 static const MCPhysReg *GetFPR() {
2225 static const MCPhysReg FPR[] = {
2226 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2227 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2233 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2235 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2236 unsigned PtrByteSize) {
2237 unsigned ArgSize = ArgVT.getStoreSize();
2238 if (Flags.isByVal())
2239 ArgSize = Flags.getByValSize();
2241 // Round up to multiples of the pointer size, except for array members,
2242 // which are always packed.
2243 if (!Flags.isInConsecutiveRegs())
2244 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2249 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2251 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2252 ISD::ArgFlagsTy Flags,
2253 unsigned PtrByteSize) {
2254 unsigned Align = PtrByteSize;
2256 // Altivec parameters are padded to a 16 byte boundary.
2257 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2258 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2259 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2262 // ByVal parameters are aligned as requested.
2263 if (Flags.isByVal()) {
2264 unsigned BVAlign = Flags.getByValAlign();
2265 if (BVAlign > PtrByteSize) {
2266 if (BVAlign % PtrByteSize != 0)
2268 "ByVal alignment is not a multiple of the pointer size");
2274 // Array members are always packed to their original alignment.
2275 if (Flags.isInConsecutiveRegs()) {
2276 // If the array member was split into multiple registers, the first
2277 // needs to be aligned to the size of the full type. (Except for
2278 // ppcf128, which is only aligned as its f64 components.)
2279 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2280 Align = OrigVT.getStoreSize();
2282 Align = ArgVT.getStoreSize();
2288 /// CalculateStackSlotUsed - Return whether this argument will use its
2289 /// stack slot (instead of being passed in registers). ArgOffset,
2290 /// AvailableFPRs, and AvailableVRs must hold the current argument
2291 /// position, and will be updated to account for this argument.
2292 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2293 ISD::ArgFlagsTy Flags,
2294 unsigned PtrByteSize,
2295 unsigned LinkageSize,
2296 unsigned ParamAreaSize,
2297 unsigned &ArgOffset,
2298 unsigned &AvailableFPRs,
2299 unsigned &AvailableVRs) {
2300 bool UseMemory = false;
2302 // Respect alignment of argument on the stack.
2304 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2305 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2306 // If there's no space left in the argument save area, we must
2307 // use memory (this check also catches zero-sized arguments).
2308 if (ArgOffset >= LinkageSize + ParamAreaSize)
2311 // Allocate argument on the stack.
2312 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2313 if (Flags.isInConsecutiveRegsLast())
2314 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2315 // If we overran the argument save area, we must use memory
2316 // (this check catches arguments passed partially in memory)
2317 if (ArgOffset > LinkageSize + ParamAreaSize)
2320 // However, if the argument is actually passed in an FPR or a VR,
2321 // we don't use memory after all.
2322 if (!Flags.isByVal()) {
2323 if (ArgVT == MVT::f32 || ArgVT == MVT::f64)
2324 if (AvailableFPRs > 0) {
2328 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2329 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2330 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64)
2331 if (AvailableVRs > 0) {
2340 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2341 /// ensure minimum alignment required for target.
2342 static unsigned EnsureStackAlignment(const TargetMachine &Target,
2343 unsigned NumBytes) {
2344 unsigned TargetAlign =
2345 Target.getSubtargetImpl()->getFrameLowering()->getStackAlignment();
2346 unsigned AlignMask = TargetAlign - 1;
2347 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2352 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2353 CallingConv::ID CallConv, bool isVarArg,
2354 const SmallVectorImpl<ISD::InputArg>
2356 SDLoc dl, SelectionDAG &DAG,
2357 SmallVectorImpl<SDValue> &InVals)
2359 if (Subtarget.isSVR4ABI()) {
2360 if (Subtarget.isPPC64())
2361 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2364 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2367 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2373 PPCTargetLowering::LowerFormalArguments_32SVR4(
2375 CallingConv::ID CallConv, bool isVarArg,
2376 const SmallVectorImpl<ISD::InputArg>
2378 SDLoc dl, SelectionDAG &DAG,
2379 SmallVectorImpl<SDValue> &InVals) const {
2381 // 32-bit SVR4 ABI Stack Frame Layout:
2382 // +-----------------------------------+
2383 // +--> | Back chain |
2384 // | +-----------------------------------+
2385 // | | Floating-point register save area |
2386 // | +-----------------------------------+
2387 // | | General register save area |
2388 // | +-----------------------------------+
2389 // | | CR save word |
2390 // | +-----------------------------------+
2391 // | | VRSAVE save word |
2392 // | +-----------------------------------+
2393 // | | Alignment padding |
2394 // | +-----------------------------------+
2395 // | | Vector register save area |
2396 // | +-----------------------------------+
2397 // | | Local variable space |
2398 // | +-----------------------------------+
2399 // | | Parameter list area |
2400 // | +-----------------------------------+
2401 // | | LR save word |
2402 // | +-----------------------------------+
2403 // SP--> +--- | Back chain |
2404 // +-----------------------------------+
2407 // System V Application Binary Interface PowerPC Processor Supplement
2408 // AltiVec Technology Programming Interface Manual
2410 MachineFunction &MF = DAG.getMachineFunction();
2411 MachineFrameInfo *MFI = MF.getFrameInfo();
2412 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2414 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2415 // Potential tail calls could cause overwriting of argument stack slots.
2416 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2417 (CallConv == CallingConv::Fast));
2418 unsigned PtrByteSize = 4;
2420 // Assign locations to all of the incoming arguments.
2421 SmallVector<CCValAssign, 16> ArgLocs;
2422 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2425 // Reserve space for the linkage area on the stack.
2426 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(false, false, false);
2427 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2429 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2431 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2432 CCValAssign &VA = ArgLocs[i];
2434 // Arguments stored in registers.
2435 if (VA.isRegLoc()) {
2436 const TargetRegisterClass *RC;
2437 EVT ValVT = VA.getValVT();
2439 switch (ValVT.getSimpleVT().SimpleTy) {
2441 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2444 RC = &PPC::GPRCRegClass;
2447 RC = &PPC::F4RCRegClass;
2450 if (Subtarget.hasVSX())
2451 RC = &PPC::VSFRCRegClass;
2453 RC = &PPC::F8RCRegClass;
2459 RC = &PPC::VRRCRegClass;
2463 RC = &PPC::VSHRCRegClass;
2467 // Transform the arguments stored in physical registers into virtual ones.
2468 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2469 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2470 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2472 if (ValVT == MVT::i1)
2473 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2475 InVals.push_back(ArgValue);
2477 // Argument stored in memory.
2478 assert(VA.isMemLoc());
2480 unsigned ArgSize = VA.getLocVT().getStoreSize();
2481 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2484 // Create load nodes to retrieve arguments from the stack.
2485 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2486 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2487 MachinePointerInfo(),
2488 false, false, false, 0));
2492 // Assign locations to all of the incoming aggregate by value arguments.
2493 // Aggregates passed by value are stored in the local variable space of the
2494 // caller's stack frame, right above the parameter list area.
2495 SmallVector<CCValAssign, 16> ByValArgLocs;
2496 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2497 ByValArgLocs, *DAG.getContext());
2499 // Reserve stack space for the allocations in CCInfo.
2500 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2502 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2504 // Area that is at least reserved in the caller of this function.
2505 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2506 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2508 // Set the size that is at least reserved in caller of this function. Tail
2509 // call optimized function's reserved stack space needs to be aligned so that
2510 // taking the difference between two stack areas will result in an aligned
2512 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2513 FuncInfo->setMinReservedArea(MinReservedArea);
2515 SmallVector<SDValue, 8> MemOps;
2517 // If the function takes variable number of arguments, make a frame index for
2518 // the start of the first vararg value... for expansion of llvm.va_start.
2520 static const MCPhysReg GPArgRegs[] = {
2521 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2522 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2524 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2526 static const MCPhysReg FPArgRegs[] = {
2527 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2530 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2531 if (DisablePPCFloatInVariadic)
2534 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2536 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2539 // Make room for NumGPArgRegs and NumFPArgRegs.
2540 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2541 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2543 FuncInfo->setVarArgsStackOffset(
2544 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2545 CCInfo.getNextStackOffset(), true));
2547 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2548 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2550 // The fixed integer arguments of a variadic function are stored to the
2551 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2552 // the result of va_next.
2553 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2554 // Get an existing live-in vreg, or add a new one.
2555 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2557 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2559 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2560 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2561 MachinePointerInfo(), false, false, 0);
2562 MemOps.push_back(Store);
2563 // Increment the address by four for the next argument to store
2564 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2565 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2568 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2570 // The double arguments are stored to the VarArgsFrameIndex
2572 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2573 // Get an existing live-in vreg, or add a new one.
2574 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2576 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2578 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2579 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2580 MachinePointerInfo(), false, false, 0);
2581 MemOps.push_back(Store);
2582 // Increment the address by eight for the next argument to store
2583 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8,
2585 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2589 if (!MemOps.empty())
2590 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2595 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2596 // value to MVT::i64 and then truncate to the correct register size.
2598 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2599 SelectionDAG &DAG, SDValue ArgVal,
2602 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2603 DAG.getValueType(ObjectVT));
2604 else if (Flags.isZExt())
2605 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2606 DAG.getValueType(ObjectVT));
2608 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2612 PPCTargetLowering::LowerFormalArguments_64SVR4(
2614 CallingConv::ID CallConv, bool isVarArg,
2615 const SmallVectorImpl<ISD::InputArg>
2617 SDLoc dl, SelectionDAG &DAG,
2618 SmallVectorImpl<SDValue> &InVals) const {
2619 // TODO: add description of PPC stack frame format, or at least some docs.
2621 bool isELFv2ABI = Subtarget.isELFv2ABI();
2622 bool isLittleEndian = Subtarget.isLittleEndian();
2623 MachineFunction &MF = DAG.getMachineFunction();
2624 MachineFrameInfo *MFI = MF.getFrameInfo();
2625 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2627 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2628 // Potential tail calls could cause overwriting of argument stack slots.
2629 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2630 (CallConv == CallingConv::Fast));
2631 unsigned PtrByteSize = 8;
2633 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
2636 static const MCPhysReg GPR[] = {
2637 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2638 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2641 static const MCPhysReg *FPR = GetFPR();
2643 static const MCPhysReg VR[] = {
2644 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2645 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2647 static const MCPhysReg VSRH[] = {
2648 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2649 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2652 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2653 const unsigned Num_FPR_Regs = 13;
2654 const unsigned Num_VR_Regs = array_lengthof(VR);
2656 // Do a first pass over the arguments to determine whether the ABI
2657 // guarantees that our caller has allocated the parameter save area
2658 // on its stack frame. In the ELFv1 ABI, this is always the case;
2659 // in the ELFv2 ABI, it is true if this is a vararg function or if
2660 // any parameter is located in a stack slot.
2662 bool HasParameterArea = !isELFv2ABI || isVarArg;
2663 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
2664 unsigned NumBytes = LinkageSize;
2665 unsigned AvailableFPRs = Num_FPR_Regs;
2666 unsigned AvailableVRs = Num_VR_Regs;
2667 for (unsigned i = 0, e = Ins.size(); i != e; ++i)
2668 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
2669 PtrByteSize, LinkageSize, ParamAreaSize,
2670 NumBytes, AvailableFPRs, AvailableVRs))
2671 HasParameterArea = true;
2673 // Add DAG nodes to load the arguments or copy them out of registers. On
2674 // entry to a function on PPC, the arguments start after the linkage area,
2675 // although the first ones are often in registers.
2677 unsigned ArgOffset = LinkageSize;
2678 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
2679 SmallVector<SDValue, 8> MemOps;
2680 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2681 unsigned CurArgIdx = 0;
2682 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2684 bool needsLoad = false;
2685 EVT ObjectVT = Ins[ArgNo].VT;
2686 EVT OrigVT = Ins[ArgNo].ArgVT;
2687 unsigned ObjSize = ObjectVT.getStoreSize();
2688 unsigned ArgSize = ObjSize;
2689 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2690 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2691 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2693 /* Respect alignment of argument on the stack. */
2695 CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
2696 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2697 unsigned CurArgOffset = ArgOffset;
2699 /* Compute GPR index associated with argument offset. */
2700 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2701 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
2703 // FIXME the codegen can be much improved in some cases.
2704 // We do not have to keep everything in memory.
2705 if (Flags.isByVal()) {
2706 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2707 ObjSize = Flags.getByValSize();
2708 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2709 // Empty aggregate parameters do not take up registers. Examples:
2713 // etc. However, we have to provide a place-holder in InVals, so
2714 // pretend we have an 8-byte item at the current address for that
2717 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2718 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2719 InVals.push_back(FIN);
2723 // Create a stack object covering all stack doublewords occupied
2724 // by the argument. If the argument is (fully or partially) on
2725 // the stack, or if the argument is fully in registers but the
2726 // caller has allocated the parameter save anyway, we can refer
2727 // directly to the caller's stack frame. Otherwise, create a
2728 // local copy in our own frame.
2730 if (HasParameterArea ||
2731 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
2732 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
2734 FI = MFI->CreateStackObject(ArgSize, Align, false);
2735 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2737 // Handle aggregates smaller than 8 bytes.
2738 if (ObjSize < PtrByteSize) {
2739 // The value of the object is its address, which differs from the
2740 // address of the enclosing doubleword on big-endian systems.
2742 if (!isLittleEndian) {
2743 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, PtrVT);
2744 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
2746 InVals.push_back(Arg);
2748 if (GPR_idx != Num_GPR_Regs) {
2749 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2750 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2753 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2754 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2755 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2756 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
2757 MachinePointerInfo(FuncArg),
2758 ObjType, false, false, 0);
2760 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2761 // store the whole register as-is to the parameter save area
2763 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2764 MachinePointerInfo(FuncArg),
2768 MemOps.push_back(Store);
2770 // Whether we copied from a register or not, advance the offset
2771 // into the parameter save area by a full doubleword.
2772 ArgOffset += PtrByteSize;
2776 // The value of the object is its address, which is the address of
2777 // its first stack doubleword.
2778 InVals.push_back(FIN);
2780 // Store whatever pieces of the object are in registers to memory.
2781 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2782 if (GPR_idx == Num_GPR_Regs)
2785 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2786 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2789 SDValue Off = DAG.getConstant(j, PtrVT);
2790 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
2792 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
2793 MachinePointerInfo(FuncArg, j),
2795 MemOps.push_back(Store);
2798 ArgOffset += ArgSize;
2802 switch (ObjectVT.getSimpleVT().SimpleTy) {
2803 default: llvm_unreachable("Unhandled argument type!");
2807 // These can be scalar arguments or elements of an integer array type
2808 // passed directly. Clang may use those instead of "byval" aggregate
2809 // types to avoid forcing arguments to memory unnecessarily.
2810 if (GPR_idx != Num_GPR_Regs) {
2811 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2812 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2814 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2815 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2816 // value to MVT::i64 and then truncate to the correct register size.
2817 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2820 ArgSize = PtrByteSize;
2827 // These can be scalar arguments or elements of a float array type
2828 // passed directly. The latter are used to implement ELFv2 homogenous
2829 // float aggregates.
2830 if (FPR_idx != Num_FPR_Regs) {
2833 if (ObjectVT == MVT::f32)
2834 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2836 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2837 &PPC::VSFRCRegClass :
2838 &PPC::F8RCRegClass);
2840 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2842 } else if (GPR_idx != Num_GPR_Regs) {
2843 // This can only ever happen in the presence of f32 array types,
2844 // since otherwise we never run out of FPRs before running out
2846 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2847 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2849 if (ObjectVT == MVT::f32) {
2850 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
2851 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
2852 DAG.getConstant(32, MVT::i32));
2853 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
2856 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
2861 // When passing an array of floats, the array occupies consecutive
2862 // space in the argument area; only round up to the next doubleword
2863 // at the end of the array. Otherwise, each float takes 8 bytes.
2864 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
2865 ArgOffset += ArgSize;
2866 if (Flags.isInConsecutiveRegsLast())
2867 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2875 // These can be scalar arguments or elements of a vector array type
2876 // passed directly. The latter are used to implement ELFv2 homogenous
2877 // vector aggregates.
2878 if (VR_idx != Num_VR_Regs) {
2879 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2880 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2881 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2882 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2891 // We need to load the argument to a virtual register if we determined
2892 // above that we ran out of physical registers of the appropriate type.
2894 if (ObjSize < ArgSize && !isLittleEndian)
2895 CurArgOffset += ArgSize - ObjSize;
2896 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2897 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2898 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2899 false, false, false, 0);
2902 InVals.push_back(ArgVal);
2905 // Area that is at least reserved in the caller of this function.
2906 unsigned MinReservedArea;
2907 if (HasParameterArea)
2908 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
2910 MinReservedArea = LinkageSize;
2912 // Set the size that is at least reserved in caller of this function. Tail
2913 // call optimized functions' reserved stack space needs to be aligned so that
2914 // taking the difference between two stack areas will result in an aligned
2916 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
2917 FuncInfo->setMinReservedArea(MinReservedArea);
2919 // If the function takes variable number of arguments, make a frame index for
2920 // the start of the first vararg value... for expansion of llvm.va_start.
2922 int Depth = ArgOffset;
2924 FuncInfo->setVarArgsFrameIndex(
2925 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2926 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2928 // If this function is vararg, store any remaining integer argument regs
2929 // to their spots on the stack so that they may be loaded by deferencing the
2930 // result of va_next.
2931 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
2932 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
2933 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2934 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2935 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2936 MachinePointerInfo(), false, false, 0);
2937 MemOps.push_back(Store);
2938 // Increment the address by four for the next argument to store
2939 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2940 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2944 if (!MemOps.empty())
2945 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2951 PPCTargetLowering::LowerFormalArguments_Darwin(
2953 CallingConv::ID CallConv, bool isVarArg,
2954 const SmallVectorImpl<ISD::InputArg>
2956 SDLoc dl, SelectionDAG &DAG,
2957 SmallVectorImpl<SDValue> &InVals) const {
2958 // TODO: add description of PPC stack frame format, or at least some docs.
2960 MachineFunction &MF = DAG.getMachineFunction();
2961 MachineFrameInfo *MFI = MF.getFrameInfo();
2962 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2964 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2965 bool isPPC64 = PtrVT == MVT::i64;
2966 // Potential tail calls could cause overwriting of argument stack slots.
2967 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2968 (CallConv == CallingConv::Fast));
2969 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2971 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
2973 unsigned ArgOffset = LinkageSize;
2974 // Area that is at least reserved in caller of this function.
2975 unsigned MinReservedArea = ArgOffset;
2977 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2978 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2979 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2981 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2982 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2983 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2986 static const MCPhysReg *FPR = GetFPR();
2988 static const MCPhysReg VR[] = {
2989 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2990 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2993 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2994 const unsigned Num_FPR_Regs = 13;
2995 const unsigned Num_VR_Regs = array_lengthof( VR);
2997 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2999 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3001 // In 32-bit non-varargs functions, the stack space for vectors is after the
3002 // stack space for non-vectors. We do not use this space unless we have
3003 // too many vectors to fit in registers, something that only occurs in
3004 // constructed examples:), but we have to walk the arglist to figure
3005 // that out...for the pathological case, compute VecArgOffset as the
3006 // start of the vector parameter area. Computing VecArgOffset is the
3007 // entire point of the following loop.
3008 unsigned VecArgOffset = ArgOffset;
3009 if (!isVarArg && !isPPC64) {
3010 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3012 EVT ObjectVT = Ins[ArgNo].VT;
3013 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3015 if (Flags.isByVal()) {
3016 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3017 unsigned ObjSize = Flags.getByValSize();
3019 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3020 VecArgOffset += ArgSize;
3024 switch(ObjectVT.getSimpleVT().SimpleTy) {
3025 default: llvm_unreachable("Unhandled argument type!");
3031 case MVT::i64: // PPC64
3033 // FIXME: We are guaranteed to be !isPPC64 at this point.
3034 // Does MVT::i64 apply?
3041 // Nothing to do, we're only looking at Nonvector args here.
3046 // We've found where the vector parameter area in memory is. Skip the
3047 // first 12 parameters; these don't use that memory.
3048 VecArgOffset = ((VecArgOffset+15)/16)*16;
3049 VecArgOffset += 12*16;
3051 // Add DAG nodes to load the arguments or copy them out of registers. On
3052 // entry to a function on PPC, the arguments start after the linkage area,
3053 // although the first ones are often in registers.
3055 SmallVector<SDValue, 8> MemOps;
3056 unsigned nAltivecParamsAtEnd = 0;
3057 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3058 unsigned CurArgIdx = 0;
3059 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3061 bool needsLoad = false;
3062 EVT ObjectVT = Ins[ArgNo].VT;
3063 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3064 unsigned ArgSize = ObjSize;
3065 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3066 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
3067 CurArgIdx = Ins[ArgNo].OrigArgIndex;
3069 unsigned CurArgOffset = ArgOffset;
3071 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3072 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3073 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3074 if (isVarArg || isPPC64) {
3075 MinReservedArea = ((MinReservedArea+15)/16)*16;
3076 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3079 } else nAltivecParamsAtEnd++;
3081 // Calculate min reserved area.
3082 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3086 // FIXME the codegen can be much improved in some cases.
3087 // We do not have to keep everything in memory.
3088 if (Flags.isByVal()) {
3089 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3090 ObjSize = Flags.getByValSize();
3091 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3092 // Objects of size 1 and 2 are right justified, everything else is
3093 // left justified. This means the memory address is adjusted forwards.
3094 if (ObjSize==1 || ObjSize==2) {
3095 CurArgOffset = CurArgOffset + (4 - ObjSize);
3097 // The value of the object is its address.
3098 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3099 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3100 InVals.push_back(FIN);
3101 if (ObjSize==1 || ObjSize==2) {
3102 if (GPR_idx != Num_GPR_Regs) {
3105 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3107 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3108 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3109 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3110 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3111 MachinePointerInfo(FuncArg),
3112 ObjType, false, false, 0);
3113 MemOps.push_back(Store);
3117 ArgOffset += PtrByteSize;
3121 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3122 // Store whatever pieces of the object are in registers
3123 // to memory. ArgOffset will be the address of the beginning
3125 if (GPR_idx != Num_GPR_Regs) {
3128 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3130 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3131 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3132 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3133 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3134 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3135 MachinePointerInfo(FuncArg, j),
3137 MemOps.push_back(Store);
3139 ArgOffset += PtrByteSize;
3141 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3148 switch (ObjectVT.getSimpleVT().SimpleTy) {
3149 default: llvm_unreachable("Unhandled argument type!");
3153 if (GPR_idx != Num_GPR_Regs) {
3154 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3155 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3157 if (ObjectVT == MVT::i1)
3158 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3163 ArgSize = PtrByteSize;
3165 // All int arguments reserve stack space in the Darwin ABI.
3166 ArgOffset += PtrByteSize;
3170 case MVT::i64: // PPC64
3171 if (GPR_idx != Num_GPR_Regs) {
3172 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3173 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3175 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3176 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3177 // value to MVT::i64 and then truncate to the correct register size.
3178 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3183 ArgSize = PtrByteSize;
3185 // All int arguments reserve stack space in the Darwin ABI.
3191 // Every 4 bytes of argument space consumes one of the GPRs available for
3192 // argument passing.
3193 if (GPR_idx != Num_GPR_Regs) {
3195 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3198 if (FPR_idx != Num_FPR_Regs) {
3201 if (ObjectVT == MVT::f32)
3202 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3204 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3206 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3212 // All FP arguments reserve stack space in the Darwin ABI.
3213 ArgOffset += isPPC64 ? 8 : ObjSize;
3219 // Note that vector arguments in registers don't reserve stack space,
3220 // except in varargs functions.
3221 if (VR_idx != Num_VR_Regs) {
3222 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3223 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3225 while ((ArgOffset % 16) != 0) {
3226 ArgOffset += PtrByteSize;
3227 if (GPR_idx != Num_GPR_Regs)
3231 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3235 if (!isVarArg && !isPPC64) {
3236 // Vectors go after all the nonvectors.
3237 CurArgOffset = VecArgOffset;
3240 // Vectors are aligned.
3241 ArgOffset = ((ArgOffset+15)/16)*16;
3242 CurArgOffset = ArgOffset;
3250 // We need to load the argument to a virtual register if we determined above
3251 // that we ran out of physical registers of the appropriate type.
3253 int FI = MFI->CreateFixedObject(ObjSize,
3254 CurArgOffset + (ArgSize - ObjSize),
3256 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3257 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3258 false, false, false, 0);
3261 InVals.push_back(ArgVal);
3264 // Allow for Altivec parameters at the end, if needed.
3265 if (nAltivecParamsAtEnd) {
3266 MinReservedArea = ((MinReservedArea+15)/16)*16;
3267 MinReservedArea += 16*nAltivecParamsAtEnd;
3270 // Area that is at least reserved in the caller of this function.
3271 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3273 // Set the size that is at least reserved in caller of this function. Tail
3274 // call optimized functions' reserved stack space needs to be aligned so that
3275 // taking the difference between two stack areas will result in an aligned
3277 MinReservedArea = EnsureStackAlignment(MF.getTarget(), MinReservedArea);
3278 FuncInfo->setMinReservedArea(MinReservedArea);
3280 // If the function takes variable number of arguments, make a frame index for
3281 // the start of the first vararg value... for expansion of llvm.va_start.
3283 int Depth = ArgOffset;
3285 FuncInfo->setVarArgsFrameIndex(
3286 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3288 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3290 // If this function is vararg, store any remaining integer argument regs
3291 // to their spots on the stack so that they may be loaded by deferencing the
3292 // result of va_next.
3293 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3297 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3299 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3301 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3302 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3303 MachinePointerInfo(), false, false, 0);
3304 MemOps.push_back(Store);
3305 // Increment the address by four for the next argument to store
3306 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3307 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3311 if (!MemOps.empty())
3312 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3317 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3318 /// adjusted to accommodate the arguments for the tailcall.
3319 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3320 unsigned ParamSize) {
3322 if (!isTailCall) return 0;
3324 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3325 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3326 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3327 // Remember only if the new adjustement is bigger.
3328 if (SPDiff < FI->getTailCallSPDelta())
3329 FI->setTailCallSPDelta(SPDiff);
3334 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3335 /// for tail call optimization. Targets which want to do tail call
3336 /// optimization should implement this function.
3338 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3339 CallingConv::ID CalleeCC,
3341 const SmallVectorImpl<ISD::InputArg> &Ins,
3342 SelectionDAG& DAG) const {
3343 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3346 // Variable argument functions are not supported.
3350 MachineFunction &MF = DAG.getMachineFunction();
3351 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3352 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3353 // Functions containing by val parameters are not supported.
3354 for (unsigned i = 0; i != Ins.size(); i++) {
3355 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3356 if (Flags.isByVal()) return false;
3359 // Non-PIC/GOT tail calls are supported.
3360 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3363 // At the moment we can only do local tail calls (in same module, hidden
3364 // or protected) if we are generating PIC.
3365 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3366 return G->getGlobal()->hasHiddenVisibility()
3367 || G->getGlobal()->hasProtectedVisibility();
3373 /// isCallCompatibleAddress - Return the immediate to use if the specified
3374 /// 32-bit value is representable in the immediate field of a BxA instruction.
3375 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3376 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3377 if (!C) return nullptr;
3379 int Addr = C->getZExtValue();
3380 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3381 SignExtend32<26>(Addr) != Addr)
3382 return nullptr; // Top 6 bits have to be sext of immediate.
3384 return DAG.getConstant((int)C->getZExtValue() >> 2,
3385 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3390 struct TailCallArgumentInfo {
3395 TailCallArgumentInfo() : FrameIdx(0) {}
3400 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3402 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3404 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3405 SmallVectorImpl<SDValue> &MemOpChains,
3407 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3408 SDValue Arg = TailCallArgs[i].Arg;
3409 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3410 int FI = TailCallArgs[i].FrameIdx;
3411 // Store relative to framepointer.
3412 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3413 MachinePointerInfo::getFixedStack(FI),
3418 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3419 /// the appropriate stack slot for the tail call optimized function call.
3420 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3421 MachineFunction &MF,
3430 // Calculate the new stack slot for the return address.
3431 int SlotSize = isPPC64 ? 8 : 4;
3432 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3434 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3435 NewRetAddrLoc, true);
3436 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3437 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3438 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3439 MachinePointerInfo::getFixedStack(NewRetAddr),
3442 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3443 // slot as the FP is never overwritten.
3446 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3447 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3449 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3450 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3451 MachinePointerInfo::getFixedStack(NewFPIdx),
3458 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3459 /// the position of the argument.
3461 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3462 SDValue Arg, int SPDiff, unsigned ArgOffset,
3463 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3464 int Offset = ArgOffset + SPDiff;
3465 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3466 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3467 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3468 SDValue FIN = DAG.getFrameIndex(FI, VT);
3469 TailCallArgumentInfo Info;
3471 Info.FrameIdxOp = FIN;
3473 TailCallArguments.push_back(Info);
3476 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3477 /// stack slot. Returns the chain as result and the loaded frame pointers in
3478 /// LROpOut/FPOpout. Used when tail calling.
3479 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3487 // Load the LR and FP stack slot for later adjusting.
3488 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3489 LROpOut = getReturnAddrFrameIndex(DAG);
3490 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3491 false, false, false, 0);
3492 Chain = SDValue(LROpOut.getNode(), 1);
3494 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3495 // slot as the FP is never overwritten.
3497 FPOpOut = getFramePointerFrameIndex(DAG);
3498 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3499 false, false, false, 0);
3500 Chain = SDValue(FPOpOut.getNode(), 1);
3506 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3507 /// by "Src" to address "Dst" of size "Size". Alignment information is
3508 /// specified by the specific parameter attribute. The copy will be passed as
3509 /// a byval function parameter.
3510 /// Sometimes what we are copying is the end of a larger object, the part that
3511 /// does not fit in registers.
3513 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3514 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3516 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3517 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3518 false, false, MachinePointerInfo(),
3519 MachinePointerInfo());
3522 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3525 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3526 SDValue Arg, SDValue PtrOff, int SPDiff,
3527 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3528 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3529 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3531 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3536 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3538 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3539 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3540 DAG.getConstant(ArgOffset, PtrVT));
3542 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3543 MachinePointerInfo(), false, false, 0));
3544 // Calculate and remember argument location.
3545 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3550 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3551 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3552 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3553 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3554 MachineFunction &MF = DAG.getMachineFunction();
3556 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3557 // might overwrite each other in case of tail call optimization.
3558 SmallVector<SDValue, 8> MemOpChains2;
3559 // Do not flag preceding copytoreg stuff together with the following stuff.
3561 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3563 if (!MemOpChains2.empty())
3564 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3566 // Store the return address to the appropriate stack slot.
3567 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3568 isPPC64, isDarwinABI, dl);
3570 // Emit callseq_end just before tailcall node.
3571 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3572 DAG.getIntPtrConstant(0, true), InFlag, dl);
3573 InFlag = Chain.getValue(1);
3576 // Is this global address that of a function that can be called by name? (as
3577 // opposed to something that must hold a descriptor for an indirect call).
3578 static bool isFunctionGlobalAddress(SDValue Callee) {
3579 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3580 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
3581 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
3584 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
3591 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3592 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3593 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3594 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3595 const PPCSubtarget &Subtarget) {
3597 bool isPPC64 = Subtarget.isPPC64();
3598 bool isSVR4ABI = Subtarget.isSVR4ABI();
3599 bool isELFv2ABI = Subtarget.isELFv2ABI();
3601 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3602 NodeTys.push_back(MVT::Other); // Returns a chain
3603 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3605 unsigned CallOpc = PPCISD::CALL;
3607 bool needIndirectCall = true;
3608 if (!isSVR4ABI || !isPPC64)
3609 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3610 // If this is an absolute destination address, use the munged value.
3611 Callee = SDValue(Dest, 0);
3612 needIndirectCall = false;
3615 if (isFunctionGlobalAddress(Callee)) {
3616 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
3617 // A call to a TLS address is actually an indirect call to a
3618 // thread-specific pointer.
3619 unsigned OpFlags = 0;
3620 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3621 (Subtarget.getTargetTriple().isMacOSX() &&
3622 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3623 (G->getGlobal()->isDeclaration() ||
3624 G->getGlobal()->isWeakForLinker())) ||
3625 (Subtarget.isTargetELF() && !isPPC64 &&
3626 !G->getGlobal()->hasLocalLinkage() &&
3627 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3628 // PC-relative references to external symbols should go through $stub,
3629 // unless we're building with the leopard linker or later, which
3630 // automatically synthesizes these stubs.
3631 OpFlags = PPCII::MO_PLT_OR_STUB;
3634 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3635 // every direct call is) turn it into a TargetGlobalAddress /
3636 // TargetExternalSymbol node so that legalize doesn't hack it.
3637 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3638 Callee.getValueType(), 0, OpFlags);
3639 needIndirectCall = false;
3642 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3643 unsigned char OpFlags = 0;
3645 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
3646 (Subtarget.getTargetTriple().isMacOSX() &&
3647 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
3648 (Subtarget.isTargetELF() && !isPPC64 &&
3649 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3650 // PC-relative references to external symbols should go through $stub,
3651 // unless we're building with the leopard linker or later, which
3652 // automatically synthesizes these stubs.
3653 OpFlags = PPCII::MO_PLT_OR_STUB;
3656 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3658 needIndirectCall = false;
3661 if (needIndirectCall) {
3662 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3663 // to do the call, we can't use PPCISD::CALL.
3664 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3666 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
3667 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3668 // entry point, but to the function descriptor (the function entry point
3669 // address is part of the function descriptor though).
3670 // The function descriptor is a three doubleword structure with the
3671 // following fields: function entry point, TOC base address and
3672 // environment pointer.
3673 // Thus for a call through a function pointer, the following actions need
3675 // 1. Save the TOC of the caller in the TOC save area of its stack
3676 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3677 // 2. Load the address of the function entry point from the function
3679 // 3. Load the TOC of the callee from the function descriptor into r2.
3680 // 4. Load the environment pointer from the function descriptor into
3682 // 5. Branch to the function entry point address.
3683 // 6. On return of the callee, the TOC of the caller needs to be
3684 // restored (this is done in FinishCall()).
3686 // All those operations are flagged together to ensure that no other
3687 // operations can be scheduled in between. E.g. without flagging the
3688 // operations together, a TOC access in the caller could be scheduled
3689 // between the load of the callee TOC and the branch to the callee, which
3690 // results in the TOC access going through the TOC of the callee instead
3691 // of going through the TOC of the caller, which leads to incorrect code.
3693 // Load the address of the function entry point from the function
3695 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3696 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3697 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3698 Chain = LoadFuncPtr.getValue(1);
3699 InFlag = LoadFuncPtr.getValue(2);
3701 // Load environment pointer into r11.
3702 // Offset of the environment pointer within the function descriptor.
3703 SDValue PtrOff = DAG.getIntPtrConstant(16);
3705 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3706 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3708 Chain = LoadEnvPtr.getValue(1);
3709 InFlag = LoadEnvPtr.getValue(2);
3711 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3713 Chain = EnvVal.getValue(0);
3714 InFlag = EnvVal.getValue(1);
3716 // Load TOC of the callee into r2. We are using a target-specific load
3717 // with r2 hard coded, because the result of a target-independent load
3718 // would never go directly into r2, since r2 is a reserved register (which
3719 // prevents the register allocator from allocating it), resulting in an
3720 // additional register being allocated and an unnecessary move instruction
3722 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3723 SDValue TOCOff = DAG.getIntPtrConstant(8);
3724 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3725 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3727 Chain = LoadTOCPtr.getValue(0);
3728 InFlag = LoadTOCPtr.getValue(1);
3730 MTCTROps[0] = Chain;
3731 MTCTROps[1] = LoadFuncPtr;
3732 MTCTROps[2] = InFlag;
3735 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3736 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3737 InFlag = Chain.getValue(1);
3740 NodeTys.push_back(MVT::Other);
3741 NodeTys.push_back(MVT::Glue);
3742 Ops.push_back(Chain);
3743 CallOpc = PPCISD::BCTRL;
3744 Callee.setNode(nullptr);
3745 // Add use of X11 (holding environment pointer)
3746 if (isSVR4ABI && isPPC64 && !isELFv2ABI)
3747 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3748 // Add CTR register as callee so a bctr can be emitted later.
3750 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3753 // If this is a direct call, pass the chain and the callee.
3754 if (Callee.getNode()) {
3755 Ops.push_back(Chain);
3756 Ops.push_back(Callee);
3758 // If this is a call to __tls_get_addr, find the symbol whose address
3759 // is to be taken and add it to the list. This will be used to
3760 // generate __tls_get_addr(<sym>@tlsgd) or __tls_get_addr(<sym>@tlsld).
3761 // We find the symbol by walking the chain to the CopyFromReg, walking
3762 // back from the CopyFromReg to the ADDI_TLSGD_L or ADDI_TLSLD_L, and
3763 // pulling the symbol from that node.
3764 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
3765 if (!strcmp(S->getSymbol(), "__tls_get_addr")) {
3766 assert(!needIndirectCall && "Indirect call to __tls_get_addr???");
3767 SDNode *AddI = Chain.getNode()->getOperand(2).getNode();
3768 SDValue TGTAddr = AddI->getOperand(1);
3769 assert(TGTAddr.getNode()->getOpcode() == ISD::TargetGlobalTLSAddress &&
3770 "Didn't find target global TLS address where we expected one");
3771 Ops.push_back(TGTAddr);
3772 CallOpc = PPCISD::CALL_TLS;
3775 // If this is a tail call add stack pointer delta.
3777 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3779 // Add argument registers to the end of the list so that they are known live
3781 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3782 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3783 RegsToPass[i].second.getValueType()));
3785 // Direct calls in the ELFv2 ABI need the TOC register live into the call.
3786 if (Callee.getNode() && isELFv2ABI)
3787 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
3793 bool isLocalCall(const SDValue &Callee)
3795 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3796 return !G->getGlobal()->isDeclaration() &&
3797 !G->getGlobal()->isWeakForLinker();
3802 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3803 CallingConv::ID CallConv, bool isVarArg,
3804 const SmallVectorImpl<ISD::InputArg> &Ins,
3805 SDLoc dl, SelectionDAG &DAG,
3806 SmallVectorImpl<SDValue> &InVals) const {
3808 SmallVector<CCValAssign, 16> RVLocs;
3809 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
3811 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3813 // Copy all of the result registers out of their specified physreg.
3814 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3815 CCValAssign &VA = RVLocs[i];
3816 assert(VA.isRegLoc() && "Can only return in registers!");
3818 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3819 VA.getLocReg(), VA.getLocVT(), InFlag);
3820 Chain = Val.getValue(1);
3821 InFlag = Val.getValue(2);
3823 switch (VA.getLocInfo()) {
3824 default: llvm_unreachable("Unknown loc info!");
3825 case CCValAssign::Full: break;
3826 case CCValAssign::AExt:
3827 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3829 case CCValAssign::ZExt:
3830 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3831 DAG.getValueType(VA.getValVT()));
3832 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3834 case CCValAssign::SExt:
3835 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3836 DAG.getValueType(VA.getValVT()));
3837 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3841 InVals.push_back(Val);
3848 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3849 bool isTailCall, bool isVarArg,
3851 SmallVector<std::pair<unsigned, SDValue>, 8>
3853 SDValue InFlag, SDValue Chain,
3855 int SPDiff, unsigned NumBytes,
3856 const SmallVectorImpl<ISD::InputArg> &Ins,
3857 SmallVectorImpl<SDValue> &InVals) const {
3859 bool isELFv2ABI = Subtarget.isELFv2ABI();
3860 std::vector<EVT> NodeTys;
3861 SmallVector<SDValue, 8> Ops;
3862 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3863 isTailCall, RegsToPass, Ops, NodeTys,
3866 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3867 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3868 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3870 // When performing tail call optimization the callee pops its arguments off
3871 // the stack. Account for this here so these bytes can be pushed back on in
3872 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3873 int BytesCalleePops =
3874 (CallConv == CallingConv::Fast &&
3875 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3877 // Add a register mask operand representing the call-preserved registers.
3878 const TargetRegisterInfo *TRI =
3879 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
3880 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3881 assert(Mask && "Missing call preserved mask for calling convention");
3882 Ops.push_back(DAG.getRegisterMask(Mask));
3884 if (InFlag.getNode())
3885 Ops.push_back(InFlag);
3889 assert(((Callee.getOpcode() == ISD::Register &&
3890 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3891 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3892 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3893 isa<ConstantSDNode>(Callee)) &&
3894 "Expecting an global address, external symbol, absolute value or register");
3896 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3899 // Add a NOP immediately after the branch instruction when using the 64-bit
3900 // SVR4 ABI. At link time, if caller and callee are in a different module and
3901 // thus have a different TOC, the call will be replaced with a call to a stub
3902 // function which saves the current TOC, loads the TOC of the callee and
3903 // branches to the callee. The NOP will be replaced with a load instruction
3904 // which restores the TOC of the caller from the TOC save slot of the current
3905 // stack frame. If caller and callee belong to the same module (and have the
3906 // same TOC), the NOP will remain unchanged.
3908 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3909 if (CallOpc == PPCISD::BCTRL) {
3910 // This is a call through a function pointer.
3911 // Restore the caller TOC from the save area into R2.
3912 // See PrepareCall() for more information about calls through function
3913 // pointers in the 64-bit SVR4 ABI.
3914 // We are using a target-specific load with r2 hard coded, because the
3915 // result of a target-independent load would never go directly into r2,
3916 // since r2 is a reserved register (which prevents the register allocator
3917 // from allocating it), resulting in an additional register being
3918 // allocated and an unnecessary move instruction being generated.
3919 CallOpc = PPCISD::BCTRL_LOAD_TOC;
3921 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3922 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3923 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
3924 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3925 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3927 // The address needs to go after the chain input but before the flag (or
3928 // any other variadic arguments).
3929 Ops.insert(std::next(Ops.begin()), AddTOC);
3930 } else if ((CallOpc == PPCISD::CALL) &&
3931 (!isLocalCall(Callee) ||
3932 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3933 // Otherwise insert NOP for non-local calls.
3934 CallOpc = PPCISD::CALL_NOP;
3935 } else if (CallOpc == PPCISD::CALL_TLS)
3936 // For 64-bit SVR4, TLS calls are always non-local.
3937 CallOpc = PPCISD::CALL_NOP_TLS;
3940 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3941 InFlag = Chain.getValue(1);
3943 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3944 DAG.getIntPtrConstant(BytesCalleePops, true),
3947 InFlag = Chain.getValue(1);
3949 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3950 Ins, dl, DAG, InVals);
3954 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3955 SmallVectorImpl<SDValue> &InVals) const {
3956 SelectionDAG &DAG = CLI.DAG;
3958 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3959 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3960 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3961 SDValue Chain = CLI.Chain;
3962 SDValue Callee = CLI.Callee;
3963 bool &isTailCall = CLI.IsTailCall;
3964 CallingConv::ID CallConv = CLI.CallConv;
3965 bool isVarArg = CLI.IsVarArg;
3968 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3971 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3972 report_fatal_error("failed to perform tail call elimination on a call "
3973 "site marked musttail");
3975 if (Subtarget.isSVR4ABI()) {
3976 if (Subtarget.isPPC64())
3977 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3978 isTailCall, Outs, OutVals, Ins,
3981 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3982 isTailCall, Outs, OutVals, Ins,
3986 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3987 isTailCall, Outs, OutVals, Ins,
3992 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3993 CallingConv::ID CallConv, bool isVarArg,
3995 const SmallVectorImpl<ISD::OutputArg> &Outs,
3996 const SmallVectorImpl<SDValue> &OutVals,
3997 const SmallVectorImpl<ISD::InputArg> &Ins,
3998 SDLoc dl, SelectionDAG &DAG,
3999 SmallVectorImpl<SDValue> &InVals) const {
4000 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4001 // of the 32-bit SVR4 ABI stack frame layout.
4003 assert((CallConv == CallingConv::C ||
4004 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4006 unsigned PtrByteSize = 4;
4008 MachineFunction &MF = DAG.getMachineFunction();
4010 // Mark this function as potentially containing a function that contains a
4011 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4012 // and restoring the callers stack pointer in this functions epilog. This is
4013 // done because by tail calling the called function might overwrite the value
4014 // in this function's (MF) stack pointer stack slot 0(SP).
4015 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4016 CallConv == CallingConv::Fast)
4017 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4019 // Count how many bytes are to be pushed on the stack, including the linkage
4020 // area, parameter list area and the part of the local variable space which
4021 // contains copies of aggregates which are passed by value.
4023 // Assign locations to all of the outgoing arguments.
4024 SmallVector<CCValAssign, 16> ArgLocs;
4025 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4028 // Reserve space for the linkage area on the stack.
4029 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false, false),
4033 // Handle fixed and variable vector arguments differently.
4034 // Fixed vector arguments go into registers as long as registers are
4035 // available. Variable vector arguments always go into memory.
4036 unsigned NumArgs = Outs.size();
4038 for (unsigned i = 0; i != NumArgs; ++i) {
4039 MVT ArgVT = Outs[i].VT;
4040 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4043 if (Outs[i].IsFixed) {
4044 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4047 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4053 errs() << "Call operand #" << i << " has unhandled type "
4054 << EVT(ArgVT).getEVTString() << "\n";
4056 llvm_unreachable(nullptr);
4060 // All arguments are treated the same.
4061 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4064 // Assign locations to all of the outgoing aggregate by value arguments.
4065 SmallVector<CCValAssign, 16> ByValArgLocs;
4066 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4067 ByValArgLocs, *DAG.getContext());
4069 // Reserve stack space for the allocations in CCInfo.
4070 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4072 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4074 // Size of the linkage area, parameter list area and the part of the local
4075 // space variable where copies of aggregates which are passed by value are
4077 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4079 // Calculate by how many bytes the stack has to be adjusted in case of tail
4080 // call optimization.
4081 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4083 // Adjust the stack pointer for the new arguments...
4084 // These operations are automatically eliminated by the prolog/epilog pass
4085 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4087 SDValue CallSeqStart = Chain;
4089 // Load the return address and frame pointer so it can be moved somewhere else
4092 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4095 // Set up a copy of the stack pointer for use loading and storing any
4096 // arguments that may not fit in the registers available for argument
4098 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4100 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4101 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4102 SmallVector<SDValue, 8> MemOpChains;
4104 bool seenFloatArg = false;
4105 // Walk the register/memloc assignments, inserting copies/loads.
4106 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4109 CCValAssign &VA = ArgLocs[i];
4110 SDValue Arg = OutVals[i];
4111 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4113 if (Flags.isByVal()) {
4114 // Argument is an aggregate which is passed by value, thus we need to
4115 // create a copy of it in the local variable space of the current stack
4116 // frame (which is the stack frame of the caller) and pass the address of
4117 // this copy to the callee.
4118 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4119 CCValAssign &ByValVA = ByValArgLocs[j++];
4120 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4122 // Memory reserved in the local variable space of the callers stack frame.
4123 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4125 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4126 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4128 // Create a copy of the argument in the local area of the current
4130 SDValue MemcpyCall =
4131 CreateCopyOfByValArgument(Arg, PtrOff,
4132 CallSeqStart.getNode()->getOperand(0),
4135 // This must go outside the CALLSEQ_START..END.
4136 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4137 CallSeqStart.getNode()->getOperand(1),
4139 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4140 NewCallSeqStart.getNode());
4141 Chain = CallSeqStart = NewCallSeqStart;
4143 // Pass the address of the aggregate copy on the stack either in a
4144 // physical register or in the parameter list area of the current stack
4145 // frame to the callee.
4149 if (VA.isRegLoc()) {
4150 if (Arg.getValueType() == MVT::i1)
4151 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4153 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4154 // Put argument in a physical register.
4155 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4157 // Put argument in the parameter list area of the current stack frame.
4158 assert(VA.isMemLoc());
4159 unsigned LocMemOffset = VA.getLocMemOffset();
4162 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
4163 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
4165 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4166 MachinePointerInfo(),
4169 // Calculate and remember argument location.
4170 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4176 if (!MemOpChains.empty())
4177 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4179 // Build a sequence of copy-to-reg nodes chained together with token chain
4180 // and flag operands which copy the outgoing args into the appropriate regs.
4182 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4183 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4184 RegsToPass[i].second, InFlag);
4185 InFlag = Chain.getValue(1);
4188 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4191 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4192 SDValue Ops[] = { Chain, InFlag };
4194 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4195 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4197 InFlag = Chain.getValue(1);
4201 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4202 false, TailCallArguments);
4204 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4205 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4209 // Copy an argument into memory, being careful to do this outside the
4210 // call sequence for the call to which the argument belongs.
4212 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4213 SDValue CallSeqStart,
4214 ISD::ArgFlagsTy Flags,
4217 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4218 CallSeqStart.getNode()->getOperand(0),
4220 // The MEMCPY must go outside the CALLSEQ_START..END.
4221 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4222 CallSeqStart.getNode()->getOperand(1),
4224 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4225 NewCallSeqStart.getNode());
4226 return NewCallSeqStart;
4230 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4231 CallingConv::ID CallConv, bool isVarArg,
4233 const SmallVectorImpl<ISD::OutputArg> &Outs,
4234 const SmallVectorImpl<SDValue> &OutVals,
4235 const SmallVectorImpl<ISD::InputArg> &Ins,
4236 SDLoc dl, SelectionDAG &DAG,
4237 SmallVectorImpl<SDValue> &InVals) const {
4239 bool isELFv2ABI = Subtarget.isELFv2ABI();
4240 bool isLittleEndian = Subtarget.isLittleEndian();
4241 unsigned NumOps = Outs.size();
4243 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4244 unsigned PtrByteSize = 8;
4246 MachineFunction &MF = DAG.getMachineFunction();
4248 // Mark this function as potentially containing a function that contains a
4249 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4250 // and restoring the callers stack pointer in this functions epilog. This is
4251 // done because by tail calling the called function might overwrite the value
4252 // in this function's (MF) stack pointer stack slot 0(SP).
4253 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4254 CallConv == CallingConv::Fast)
4255 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4257 // Count how many bytes are to be pushed on the stack, including the linkage
4258 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4259 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4260 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4261 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(true, false,
4263 unsigned NumBytes = LinkageSize;
4265 // Add up all the space actually used.
4266 for (unsigned i = 0; i != NumOps; ++i) {
4267 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4268 EVT ArgVT = Outs[i].VT;
4269 EVT OrigVT = Outs[i].ArgVT;
4271 /* Respect alignment of argument on the stack. */
4273 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4274 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4276 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4277 if (Flags.isInConsecutiveRegsLast())
4278 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4281 unsigned NumBytesActuallyUsed = NumBytes;
4283 // The prolog code of the callee may store up to 8 GPR argument registers to
4284 // the stack, allowing va_start to index over them in memory if its varargs.
4285 // Because we cannot tell if this is needed on the caller side, we have to
4286 // conservatively assume that it is needed. As such, make sure we have at
4287 // least enough stack space for the caller to store the 8 GPRs.
4288 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4289 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4291 // Tail call needs the stack to be aligned.
4292 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4293 CallConv == CallingConv::Fast)
4294 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4296 // Calculate by how many bytes the stack has to be adjusted in case of tail
4297 // call optimization.
4298 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4300 // To protect arguments on the stack from being clobbered in a tail call,
4301 // force all the loads to happen before doing any other lowering.
4303 Chain = DAG.getStackArgumentTokenFactor(Chain);
4305 // Adjust the stack pointer for the new arguments...
4306 // These operations are automatically eliminated by the prolog/epilog pass
4307 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4309 SDValue CallSeqStart = Chain;
4311 // Load the return address and frame pointer so it can be move somewhere else
4314 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4317 // Set up a copy of the stack pointer for use loading and storing any
4318 // arguments that may not fit in the registers available for argument
4320 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4322 // Figure out which arguments are going to go in registers, and which in
4323 // memory. Also, if this is a vararg function, floating point operations
4324 // must be stored to our stack, and loaded into integer regs as well, if
4325 // any integer regs are available for argument passing.
4326 unsigned ArgOffset = LinkageSize;
4327 unsigned GPR_idx, FPR_idx = 0, VR_idx = 0;
4329 static const MCPhysReg GPR[] = {
4330 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4331 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4333 static const MCPhysReg *FPR = GetFPR();
4335 static const MCPhysReg VR[] = {
4336 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4337 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4339 static const MCPhysReg VSRH[] = {
4340 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4341 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4344 const unsigned NumGPRs = array_lengthof(GPR);
4345 const unsigned NumFPRs = 13;
4346 const unsigned NumVRs = array_lengthof(VR);
4348 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4349 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4351 SmallVector<SDValue, 8> MemOpChains;
4352 for (unsigned i = 0; i != NumOps; ++i) {
4353 SDValue Arg = OutVals[i];
4354 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4355 EVT ArgVT = Outs[i].VT;
4356 EVT OrigVT = Outs[i].ArgVT;
4358 /* Respect alignment of argument on the stack. */
4360 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4361 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4363 /* Compute GPR index associated with argument offset. */
4364 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4365 GPR_idx = std::min(GPR_idx, NumGPRs);
4367 // PtrOff will be used to store the current argument to the stack if a
4368 // register cannot be found for it.
4371 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4373 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4375 // Promote integers to 64-bit values.
4376 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4377 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4378 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4379 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4382 // FIXME memcpy is used way more than necessary. Correctness first.
4383 // Note: "by value" is code for passing a structure by value, not
4385 if (Flags.isByVal()) {
4386 // Note: Size includes alignment padding, so
4387 // struct x { short a; char b; }
4388 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4389 // These are the proper values we need for right-justifying the
4390 // aggregate in a parameter register.
4391 unsigned Size = Flags.getByValSize();
4393 // An empty aggregate parameter takes up no storage and no
4398 // All aggregates smaller than 8 bytes must be passed right-justified.
4399 if (Size==1 || Size==2 || Size==4) {
4400 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4401 if (GPR_idx != NumGPRs) {
4402 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4403 MachinePointerInfo(), VT,
4404 false, false, false, 0);
4405 MemOpChains.push_back(Load.getValue(1));
4406 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4408 ArgOffset += PtrByteSize;
4413 if (GPR_idx == NumGPRs && Size < 8) {
4414 SDValue AddPtr = PtrOff;
4415 if (!isLittleEndian) {
4416 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4417 PtrOff.getValueType());
4418 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4420 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4423 ArgOffset += PtrByteSize;
4426 // Copy entire object into memory. There are cases where gcc-generated
4427 // code assumes it is there, even if it could be put entirely into
4428 // registers. (This is not what the doc says.)
4430 // FIXME: The above statement is likely due to a misunderstanding of the
4431 // documents. All arguments must be copied into the parameter area BY
4432 // THE CALLEE in the event that the callee takes the address of any
4433 // formal argument. That has not yet been implemented. However, it is
4434 // reasonable to use the stack area as a staging area for the register
4437 // Skip this for small aggregates, as we will use the same slot for a
4438 // right-justified copy, below.
4440 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4444 // When a register is available, pass a small aggregate right-justified.
4445 if (Size < 8 && GPR_idx != NumGPRs) {
4446 // The easiest way to get this right-justified in a register
4447 // is to copy the structure into the rightmost portion of a
4448 // local variable slot, then load the whole slot into the
4450 // FIXME: The memcpy seems to produce pretty awful code for
4451 // small aggregates, particularly for packed ones.
4452 // FIXME: It would be preferable to use the slot in the
4453 // parameter save area instead of a new local variable.
4454 SDValue AddPtr = PtrOff;
4455 if (!isLittleEndian) {
4456 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4457 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4459 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4463 // Load the slot into the register.
4464 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4465 MachinePointerInfo(),
4466 false, false, false, 0);
4467 MemOpChains.push_back(Load.getValue(1));
4468 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Load));
4470 // Done with this argument.
4471 ArgOffset += PtrByteSize;
4475 // For aggregates larger than PtrByteSize, copy the pieces of the
4476 // object that fit into registers from the parameter save area.
4477 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4478 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4479 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4480 if (GPR_idx != NumGPRs) {
4481 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4482 MachinePointerInfo(),
4483 false, false, false, 0);
4484 MemOpChains.push_back(Load.getValue(1));
4485 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4486 ArgOffset += PtrByteSize;
4488 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4495 switch (Arg.getSimpleValueType().SimpleTy) {
4496 default: llvm_unreachable("Unexpected ValueType for argument!");
4500 // These can be scalar arguments or elements of an integer array type
4501 // passed directly. Clang may use those instead of "byval" aggregate
4502 // types to avoid forcing arguments to memory unnecessarily.
4503 if (GPR_idx != NumGPRs) {
4504 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], Arg));
4506 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4507 true, isTailCall, false, MemOpChains,
4508 TailCallArguments, dl);
4510 ArgOffset += PtrByteSize;
4514 // These can be scalar arguments or elements of a float array type
4515 // passed directly. The latter are used to implement ELFv2 homogenous
4516 // float aggregates.
4518 // Named arguments go into FPRs first, and once they overflow, the
4519 // remaining arguments go into GPRs and then the parameter save area.
4520 // Unnamed arguments for vararg functions always go to GPRs and
4521 // then the parameter save area. For now, put all arguments to vararg
4522 // routines always in both locations (FPR *and* GPR or stack slot).
4523 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
4525 // First load the argument into the next available FPR.
4526 if (FPR_idx != NumFPRs)
4527 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4529 // Next, load the argument into GPR or stack slot if needed.
4530 if (!NeedGPROrStack)
4532 else if (GPR_idx != NumGPRs) {
4533 // In the non-vararg case, this can only ever happen in the
4534 // presence of f32 array types, since otherwise we never run
4535 // out of FPRs before running out of GPRs.
4538 // Double values are always passed in a single GPR.
4539 if (Arg.getValueType() != MVT::f32) {
4540 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
4542 // Non-array float values are extended and passed in a GPR.
4543 } else if (!Flags.isInConsecutiveRegs()) {
4544 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4545 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4547 // If we have an array of floats, we collect every odd element
4548 // together with its predecessor into one GPR.
4549 } else if (ArgOffset % PtrByteSize != 0) {
4551 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
4552 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4553 if (!isLittleEndian)
4555 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
4557 // The final element, if even, goes into the first half of a GPR.
4558 } else if (Flags.isInConsecutiveRegsLast()) {
4559 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
4560 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
4561 if (!isLittleEndian)
4562 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
4563 DAG.getConstant(32, MVT::i32));
4565 // Non-final even elements are skipped; they will be handled
4566 // together the with subsequent argument on the next go-around.
4570 if (ArgVal.getNode())
4571 RegsToPass.push_back(std::make_pair(GPR[GPR_idx], ArgVal));
4573 // Single-precision floating-point values are mapped to the
4574 // second (rightmost) word of the stack doubleword.
4575 if (Arg.getValueType() == MVT::f32 &&
4576 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
4577 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4578 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4581 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4582 true, isTailCall, false, MemOpChains,
4583 TailCallArguments, dl);
4585 // When passing an array of floats, the array occupies consecutive
4586 // space in the argument area; only round up to the next doubleword
4587 // at the end of the array. Otherwise, each float takes 8 bytes.
4588 ArgOffset += (Arg.getValueType() == MVT::f32 &&
4589 Flags.isInConsecutiveRegs()) ? 4 : 8;
4590 if (Flags.isInConsecutiveRegsLast())
4591 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4600 // These can be scalar arguments or elements of a vector array type
4601 // passed directly. The latter are used to implement ELFv2 homogenous
4602 // vector aggregates.
4604 // For a varargs call, named arguments go into VRs or on the stack as
4605 // usual; unnamed arguments always go to the stack or the corresponding
4606 // GPRs when within range. For now, we always put the value in both
4607 // locations (or even all three).
4609 // We could elide this store in the case where the object fits
4610 // entirely in R registers. Maybe later.
4611 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4612 MachinePointerInfo(), false, false, 0);
4613 MemOpChains.push_back(Store);
4614 if (VR_idx != NumVRs) {
4615 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4616 MachinePointerInfo(),
4617 false, false, false, 0);
4618 MemOpChains.push_back(Load.getValue(1));
4620 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4621 Arg.getSimpleValueType() == MVT::v2i64) ?
4622 VSRH[VR_idx] : VR[VR_idx];
4625 RegsToPass.push_back(std::make_pair(VReg, Load));
4628 for (unsigned i=0; i<16; i+=PtrByteSize) {
4629 if (GPR_idx == NumGPRs)
4631 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4632 DAG.getConstant(i, PtrVT));
4633 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4634 false, false, false, 0);
4635 MemOpChains.push_back(Load.getValue(1));
4636 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4641 // Non-varargs Altivec params go into VRs or on the stack.
4642 if (VR_idx != NumVRs) {
4643 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4644 Arg.getSimpleValueType() == MVT::v2i64) ?
4645 VSRH[VR_idx] : VR[VR_idx];
4648 RegsToPass.push_back(std::make_pair(VReg, Arg));
4650 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4651 true, isTailCall, true, MemOpChains,
4652 TailCallArguments, dl);
4659 assert(NumBytesActuallyUsed == ArgOffset);
4660 (void)NumBytesActuallyUsed;
4662 if (!MemOpChains.empty())
4663 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4665 // Check if this is an indirect call (MTCTR/BCTRL).
4666 // See PrepareCall() for more information about calls through function
4667 // pointers in the 64-bit SVR4 ABI.
4669 !isFunctionGlobalAddress(Callee) &&
4670 !isa<ExternalSymbolSDNode>(Callee)) {
4671 // Load r2 into a virtual register and store it to the TOC save area.
4672 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4673 // TOC save area offset.
4674 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset(isELFv2ABI);
4675 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4676 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4677 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4679 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
4680 // This does not mean the MTCTR instruction must use R12; it's easier
4681 // to model this as an extra parameter, so do that.
4683 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4686 // Build a sequence of copy-to-reg nodes chained together with token chain
4687 // and flag operands which copy the outgoing args into the appropriate regs.
4689 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4690 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4691 RegsToPass[i].second, InFlag);
4692 InFlag = Chain.getValue(1);
4696 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4697 FPOp, true, TailCallArguments);
4699 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4700 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4705 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4706 CallingConv::ID CallConv, bool isVarArg,
4708 const SmallVectorImpl<ISD::OutputArg> &Outs,
4709 const SmallVectorImpl<SDValue> &OutVals,
4710 const SmallVectorImpl<ISD::InputArg> &Ins,
4711 SDLoc dl, SelectionDAG &DAG,
4712 SmallVectorImpl<SDValue> &InVals) const {
4714 unsigned NumOps = Outs.size();
4716 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4717 bool isPPC64 = PtrVT == MVT::i64;
4718 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4720 MachineFunction &MF = DAG.getMachineFunction();
4722 // Mark this function as potentially containing a function that contains a
4723 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4724 // and restoring the callers stack pointer in this functions epilog. This is
4725 // done because by tail calling the called function might overwrite the value
4726 // in this function's (MF) stack pointer stack slot 0(SP).
4727 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4728 CallConv == CallingConv::Fast)
4729 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4731 // Count how many bytes are to be pushed on the stack, including the linkage
4732 // area, and parameter passing area. We start with 24/48 bytes, which is
4733 // prereserved space for [SP][CR][LR][3 x unused].
4734 unsigned LinkageSize = PPCFrameLowering::getLinkageSize(isPPC64, true,
4736 unsigned NumBytes = LinkageSize;
4738 // Add up all the space actually used.
4739 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
4740 // they all go in registers, but we must reserve stack space for them for
4741 // possible use by the caller. In varargs or 64-bit calls, parameters are
4742 // assigned stack space in order, with padding so Altivec parameters are
4744 unsigned nAltivecParamsAtEnd = 0;
4745 for (unsigned i = 0; i != NumOps; ++i) {
4746 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4747 EVT ArgVT = Outs[i].VT;
4748 // Varargs Altivec parameters are padded to a 16 byte boundary.
4749 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
4750 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
4751 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
4752 if (!isVarArg && !isPPC64) {
4753 // Non-varargs Altivec parameters go after all the non-Altivec
4754 // parameters; handle those later so we know how much padding we need.
4755 nAltivecParamsAtEnd++;
4758 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
4759 NumBytes = ((NumBytes+15)/16)*16;
4761 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4764 // Allow for Altivec parameters at the end, if needed.
4765 if (nAltivecParamsAtEnd) {
4766 NumBytes = ((NumBytes+15)/16)*16;
4767 NumBytes += 16*nAltivecParamsAtEnd;
4770 // The prolog code of the callee may store up to 8 GPR argument registers to
4771 // the stack, allowing va_start to index over them in memory if its varargs.
4772 // Because we cannot tell if this is needed on the caller side, we have to
4773 // conservatively assume that it is needed. As such, make sure we have at
4774 // least enough stack space for the caller to store the 8 GPRs.
4775 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4777 // Tail call needs the stack to be aligned.
4778 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4779 CallConv == CallingConv::Fast)
4780 NumBytes = EnsureStackAlignment(MF.getTarget(), NumBytes);
4782 // Calculate by how many bytes the stack has to be adjusted in case of tail
4783 // call optimization.
4784 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4786 // To protect arguments on the stack from being clobbered in a tail call,
4787 // force all the loads to happen before doing any other lowering.
4789 Chain = DAG.getStackArgumentTokenFactor(Chain);
4791 // Adjust the stack pointer for the new arguments...
4792 // These operations are automatically eliminated by the prolog/epilog pass
4793 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4795 SDValue CallSeqStart = Chain;
4797 // Load the return address and frame pointer so it can be move somewhere else
4800 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4803 // Set up a copy of the stack pointer for use loading and storing any
4804 // arguments that may not fit in the registers available for argument
4808 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4810 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4812 // Figure out which arguments are going to go in registers, and which in
4813 // memory. Also, if this is a vararg function, floating point operations
4814 // must be stored to our stack, and loaded into integer regs as well, if
4815 // any integer regs are available for argument passing.
4816 unsigned ArgOffset = LinkageSize;
4817 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4819 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4820 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4821 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4823 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4824 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4825 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4827 static const MCPhysReg *FPR = GetFPR();
4829 static const MCPhysReg VR[] = {
4830 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4831 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4833 const unsigned NumGPRs = array_lengthof(GPR_32);
4834 const unsigned NumFPRs = 13;
4835 const unsigned NumVRs = array_lengthof(VR);
4837 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4839 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4840 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4842 SmallVector<SDValue, 8> MemOpChains;
4843 for (unsigned i = 0; i != NumOps; ++i) {
4844 SDValue Arg = OutVals[i];
4845 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4847 // PtrOff will be used to store the current argument to the stack if a
4848 // register cannot be found for it.
4851 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4853 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4855 // On PPC64, promote integers to 64-bit values.
4856 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4857 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4858 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4859 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4862 // FIXME memcpy is used way more than necessary. Correctness first.
4863 // Note: "by value" is code for passing a structure by value, not
4865 if (Flags.isByVal()) {
4866 unsigned Size = Flags.getByValSize();
4867 // Very small objects are passed right-justified. Everything else is
4868 // passed left-justified.
4869 if (Size==1 || Size==2) {
4870 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4871 if (GPR_idx != NumGPRs) {
4872 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4873 MachinePointerInfo(), VT,
4874 false, false, false, 0);
4875 MemOpChains.push_back(Load.getValue(1));
4876 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4878 ArgOffset += PtrByteSize;
4880 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4881 PtrOff.getValueType());
4882 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4883 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4886 ArgOffset += PtrByteSize;
4890 // Copy entire object into memory. There are cases where gcc-generated
4891 // code assumes it is there, even if it could be put entirely into
4892 // registers. (This is not what the doc says.)
4893 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4897 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4898 // copy the pieces of the object that fit into registers from the
4899 // parameter save area.
4900 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4901 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4902 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4903 if (GPR_idx != NumGPRs) {
4904 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4905 MachinePointerInfo(),
4906 false, false, false, 0);
4907 MemOpChains.push_back(Load.getValue(1));
4908 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4909 ArgOffset += PtrByteSize;
4911 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4918 switch (Arg.getSimpleValueType().SimpleTy) {
4919 default: llvm_unreachable("Unexpected ValueType for argument!");
4923 if (GPR_idx != NumGPRs) {
4924 if (Arg.getValueType() == MVT::i1)
4925 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4927 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4929 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4930 isPPC64, isTailCall, false, MemOpChains,
4931 TailCallArguments, dl);
4933 ArgOffset += PtrByteSize;
4937 if (FPR_idx != NumFPRs) {
4938 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4941 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4942 MachinePointerInfo(), false, false, 0);
4943 MemOpChains.push_back(Store);
4945 // Float varargs are always shadowed in available integer registers
4946 if (GPR_idx != NumGPRs) {
4947 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4948 MachinePointerInfo(), false, false,
4950 MemOpChains.push_back(Load.getValue(1));
4951 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4953 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4954 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4955 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4956 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4957 MachinePointerInfo(),
4958 false, false, false, 0);
4959 MemOpChains.push_back(Load.getValue(1));
4960 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4963 // If we have any FPRs remaining, we may also have GPRs remaining.
4964 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4966 if (GPR_idx != NumGPRs)
4968 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4969 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4973 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4974 isPPC64, isTailCall, false, MemOpChains,
4975 TailCallArguments, dl);
4979 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4986 // These go aligned on the stack, or in the corresponding R registers
4987 // when within range. The Darwin PPC ABI doc claims they also go in
4988 // V registers; in fact gcc does this only for arguments that are
4989 // prototyped, not for those that match the ... We do it for all
4990 // arguments, seems to work.
4991 while (ArgOffset % 16 !=0) {
4992 ArgOffset += PtrByteSize;
4993 if (GPR_idx != NumGPRs)
4996 // We could elide this store in the case where the object fits
4997 // entirely in R registers. Maybe later.
4998 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4999 DAG.getConstant(ArgOffset, PtrVT));
5000 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5001 MachinePointerInfo(), false, false, 0);
5002 MemOpChains.push_back(Store);
5003 if (VR_idx != NumVRs) {
5004 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5005 MachinePointerInfo(),
5006 false, false, false, 0);
5007 MemOpChains.push_back(Load.getValue(1));
5008 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5011 for (unsigned i=0; i<16; i+=PtrByteSize) {
5012 if (GPR_idx == NumGPRs)
5014 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5015 DAG.getConstant(i, PtrVT));
5016 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5017 false, false, false, 0);
5018 MemOpChains.push_back(Load.getValue(1));
5019 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5024 // Non-varargs Altivec params generally go in registers, but have
5025 // stack space allocated at the end.
5026 if (VR_idx != NumVRs) {
5027 // Doesn't have GPR space allocated.
5028 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5029 } else if (nAltivecParamsAtEnd==0) {
5030 // We are emitting Altivec params in order.
5031 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5032 isPPC64, isTailCall, true, MemOpChains,
5033 TailCallArguments, dl);
5039 // If all Altivec parameters fit in registers, as they usually do,
5040 // they get stack space following the non-Altivec parameters. We
5041 // don't track this here because nobody below needs it.
5042 // If there are more Altivec parameters than fit in registers emit
5044 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5046 // Offset is aligned; skip 1st 12 params which go in V registers.
5047 ArgOffset = ((ArgOffset+15)/16)*16;
5049 for (unsigned i = 0; i != NumOps; ++i) {
5050 SDValue Arg = OutVals[i];
5051 EVT ArgType = Outs[i].VT;
5052 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5053 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5056 // We are emitting Altivec params in order.
5057 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5058 isPPC64, isTailCall, true, MemOpChains,
5059 TailCallArguments, dl);
5066 if (!MemOpChains.empty())
5067 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5069 // On Darwin, R12 must contain the address of an indirect callee. This does
5070 // not mean the MTCTR instruction must use R12; it's easier to model this as
5071 // an extra parameter, so do that.
5073 !isFunctionGlobalAddress(Callee) &&
5074 !isa<ExternalSymbolSDNode>(Callee) &&
5075 !isBLACompatibleAddress(Callee, DAG))
5076 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5077 PPC::R12), Callee));
5079 // Build a sequence of copy-to-reg nodes chained together with token chain
5080 // and flag operands which copy the outgoing args into the appropriate regs.
5082 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5083 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5084 RegsToPass[i].second, InFlag);
5085 InFlag = Chain.getValue(1);
5089 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5090 FPOp, true, TailCallArguments);
5092 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
5093 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
5098 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5099 MachineFunction &MF, bool isVarArg,
5100 const SmallVectorImpl<ISD::OutputArg> &Outs,
5101 LLVMContext &Context) const {
5102 SmallVector<CCValAssign, 16> RVLocs;
5103 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5104 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5108 PPCTargetLowering::LowerReturn(SDValue Chain,
5109 CallingConv::ID CallConv, bool isVarArg,
5110 const SmallVectorImpl<ISD::OutputArg> &Outs,
5111 const SmallVectorImpl<SDValue> &OutVals,
5112 SDLoc dl, SelectionDAG &DAG) const {
5114 SmallVector<CCValAssign, 16> RVLocs;
5115 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5117 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5120 SmallVector<SDValue, 4> RetOps(1, Chain);
5122 // Copy the result values into the output registers.
5123 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5124 CCValAssign &VA = RVLocs[i];
5125 assert(VA.isRegLoc() && "Can only return in registers!");
5127 SDValue Arg = OutVals[i];
5129 switch (VA.getLocInfo()) {
5130 default: llvm_unreachable("Unknown loc info!");
5131 case CCValAssign::Full: break;
5132 case CCValAssign::AExt:
5133 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5135 case CCValAssign::ZExt:
5136 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5138 case CCValAssign::SExt:
5139 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5143 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5144 Flag = Chain.getValue(1);
5145 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5148 RetOps[0] = Chain; // Update chain.
5150 // Add the flag if we have it.
5152 RetOps.push_back(Flag);
5154 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5157 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5158 const PPCSubtarget &Subtarget) const {
5159 // When we pop the dynamic allocation we need to restore the SP link.
5162 // Get the corect type for pointers.
5163 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5165 // Construct the stack pointer operand.
5166 bool isPPC64 = Subtarget.isPPC64();
5167 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5168 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5170 // Get the operands for the STACKRESTORE.
5171 SDValue Chain = Op.getOperand(0);
5172 SDValue SaveSP = Op.getOperand(1);
5174 // Load the old link SP.
5175 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5176 MachinePointerInfo(),
5177 false, false, false, 0);
5179 // Restore the stack pointer.
5180 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5182 // Store the old link SP.
5183 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5190 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5191 MachineFunction &MF = DAG.getMachineFunction();
5192 bool isPPC64 = Subtarget.isPPC64();
5193 bool isDarwinABI = Subtarget.isDarwinABI();
5194 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5196 // Get current frame pointer save index. The users of this index will be
5197 // primarily DYNALLOC instructions.
5198 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5199 int RASI = FI->getReturnAddrSaveIndex();
5201 // If the frame pointer save index hasn't been defined yet.
5203 // Find out what the fix offset of the frame pointer save area.
5204 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
5205 // Allocate the frame index for frame pointer save area.
5206 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5208 FI->setReturnAddrSaveIndex(RASI);
5210 return DAG.getFrameIndex(RASI, PtrVT);
5214 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5215 MachineFunction &MF = DAG.getMachineFunction();
5216 bool isPPC64 = Subtarget.isPPC64();
5217 bool isDarwinABI = Subtarget.isDarwinABI();
5218 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5220 // Get current frame pointer save index. The users of this index will be
5221 // primarily DYNALLOC instructions.
5222 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5223 int FPSI = FI->getFramePointerSaveIndex();
5225 // If the frame pointer save index hasn't been defined yet.
5227 // Find out what the fix offset of the frame pointer save area.
5228 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
5231 // Allocate the frame index for frame pointer save area.
5232 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5234 FI->setFramePointerSaveIndex(FPSI);
5236 return DAG.getFrameIndex(FPSI, PtrVT);
5239 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5241 const PPCSubtarget &Subtarget) const {
5243 SDValue Chain = Op.getOperand(0);
5244 SDValue Size = Op.getOperand(1);
5247 // Get the corect type for pointers.
5248 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5250 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5251 DAG.getConstant(0, PtrVT), Size);
5252 // Construct a node for the frame pointer save index.
5253 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5254 // Build a DYNALLOC node.
5255 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5256 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5257 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5260 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5261 SelectionDAG &DAG) const {
5263 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5264 DAG.getVTList(MVT::i32, MVT::Other),
5265 Op.getOperand(0), Op.getOperand(1));
5268 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5269 SelectionDAG &DAG) const {
5271 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5272 Op.getOperand(0), Op.getOperand(1));
5275 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5276 assert(Op.getValueType() == MVT::i1 &&
5277 "Custom lowering only for i1 loads");
5279 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5282 LoadSDNode *LD = cast<LoadSDNode>(Op);
5284 SDValue Chain = LD->getChain();
5285 SDValue BasePtr = LD->getBasePtr();
5286 MachineMemOperand *MMO = LD->getMemOperand();
5288 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
5289 BasePtr, MVT::i8, MMO);
5290 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5292 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5293 return DAG.getMergeValues(Ops, dl);
5296 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5297 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5298 "Custom lowering only for i1 stores");
5300 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5303 StoreSDNode *ST = cast<StoreSDNode>(Op);
5305 SDValue Chain = ST->getChain();
5306 SDValue BasePtr = ST->getBasePtr();
5307 SDValue Value = ST->getValue();
5308 MachineMemOperand *MMO = ST->getMemOperand();
5310 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
5311 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5314 // FIXME: Remove this once the ANDI glue bug is fixed:
5315 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5316 assert(Op.getValueType() == MVT::i1 &&
5317 "Custom lowering only for i1 results");
5320 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5324 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5326 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5327 // Not FP? Not a fsel.
5328 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5329 !Op.getOperand(2).getValueType().isFloatingPoint())
5332 // We might be able to do better than this under some circumstances, but in
5333 // general, fsel-based lowering of select is a finite-math-only optimization.
5334 // For more information, see section F.3 of the 2.06 ISA specification.
5335 if (!DAG.getTarget().Options.NoInfsFPMath ||
5336 !DAG.getTarget().Options.NoNaNsFPMath)
5339 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5341 EVT ResVT = Op.getValueType();
5342 EVT CmpVT = Op.getOperand(0).getValueType();
5343 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5344 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5347 // If the RHS of the comparison is a 0.0, we don't need to do the
5348 // subtraction at all.
5350 if (isFloatingPointZero(RHS))
5352 default: break; // SETUO etc aren't handled by fsel.
5356 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5357 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5358 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5359 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5360 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5361 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5362 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5365 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5368 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5369 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5370 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5373 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5376 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5377 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5378 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5379 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5384 default: break; // SETUO etc aren't handled by fsel.
5388 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5389 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5390 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5391 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5392 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5393 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5394 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5395 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5398 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5399 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5400 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5401 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5404 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5405 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5406 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5407 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5410 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5411 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5412 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5413 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5416 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5417 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5418 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5419 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5424 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
5427 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5428 SDValue Src = Op.getOperand(0);
5429 if (Src.getValueType() == MVT::f32)
5430 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5433 switch (Op.getSimpleValueType().SimpleTy) {
5434 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5436 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5437 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5442 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5443 "i64 FP_TO_UINT is supported only with FPCVT");
5444 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5450 // Convert the FP value to an int value through memory.
5451 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5452 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5453 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5454 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5455 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5457 // Emit a store to the stack slot.
5460 MachineFunction &MF = DAG.getMachineFunction();
5461 MachineMemOperand *MMO =
5462 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5463 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5464 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5465 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5467 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5468 MPI, false, false, 0);
5470 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5472 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5473 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5474 DAG.getConstant(4, FIPtr.getValueType()));
5475 MPI = MPI.getWithOffset(4);
5483 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5486 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5488 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5489 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5493 // We're trying to insert a regular store, S, and then a load, L. If the
5494 // incoming value, O, is a load, we might just be able to have our load use the
5495 // address used by O. However, we don't know if anything else will store to
5496 // that address before we can load from it. To prevent this situation, we need
5497 // to insert our load, L, into the chain as a peer of O. To do this, we give L
5498 // the same chain operand as O, we create a token factor from the chain results
5499 // of O and L, and we replace all uses of O's chain result with that token
5500 // factor (see spliceIntoChain below for this last part).
5501 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
5504 ISD::LoadExtType ET) const {
5506 if (ET == ISD::NON_EXTLOAD &&
5507 (Op.getOpcode() == ISD::FP_TO_UINT ||
5508 Op.getOpcode() == ISD::FP_TO_SINT) &&
5509 isOperationLegalOrCustom(Op.getOpcode(),
5510 Op.getOperand(0).getValueType())) {
5512 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
5516 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
5517 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
5518 LD->isNonTemporal())
5520 if (LD->getMemoryVT() != MemVT)
5523 RLI.Ptr = LD->getBasePtr();
5524 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
5525 assert(LD->getAddressingMode() == ISD::PRE_INC &&
5526 "Non-pre-inc AM on PPC?");
5527 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
5531 RLI.Chain = LD->getChain();
5532 RLI.MPI = LD->getPointerInfo();
5533 RLI.IsInvariant = LD->isInvariant();
5534 RLI.Alignment = LD->getAlignment();
5535 RLI.AAInfo = LD->getAAInfo();
5536 RLI.Ranges = LD->getRanges();
5538 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
5542 // Given the head of the old chain, ResChain, insert a token factor containing
5543 // it and NewResChain, and make users of ResChain now be users of that token
5545 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
5546 SDValue NewResChain,
5547 SelectionDAG &DAG) const {
5551 SDLoc dl(NewResChain);
5553 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
5554 NewResChain, DAG.getUNDEF(MVT::Other));
5555 assert(TF.getNode() != NewResChain.getNode() &&
5556 "A new TF really is required here");
5558 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
5559 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
5562 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5563 SelectionDAG &DAG) const {
5565 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5566 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5569 if (Op.getOperand(0).getValueType() == MVT::i1)
5570 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5571 DAG.getConstantFP(1.0, Op.getValueType()),
5572 DAG.getConstantFP(0.0, Op.getValueType()));
5574 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5575 "UINT_TO_FP is supported only with FPCVT");
5577 // If we have FCFIDS, then use it when converting to single-precision.
5578 // Otherwise, convert to double-precision and then round.
5579 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5580 (Op.getOpcode() == ISD::UINT_TO_FP ?
5581 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5582 (Op.getOpcode() == ISD::UINT_TO_FP ?
5583 PPCISD::FCFIDU : PPCISD::FCFID);
5584 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5585 MVT::f32 : MVT::f64;
5587 if (Op.getOperand(0).getValueType() == MVT::i64) {
5588 SDValue SINT = Op.getOperand(0);
5589 // When converting to single-precision, we actually need to convert
5590 // to double-precision first and then round to single-precision.
5591 // To avoid double-rounding effects during that operation, we have
5592 // to prepare the input operand. Bits that might be truncated when
5593 // converting to double-precision are replaced by a bit that won't
5594 // be lost at this stage, but is below the single-precision rounding
5597 // However, if -enable-unsafe-fp-math is in effect, accept double
5598 // rounding to avoid the extra overhead.
5599 if (Op.getValueType() == MVT::f32 &&
5600 !Subtarget.hasFPCVT() &&
5601 !DAG.getTarget().Options.UnsafeFPMath) {
5603 // Twiddle input to make sure the low 11 bits are zero. (If this
5604 // is the case, we are guaranteed the value will fit into the 53 bit
5605 // mantissa of an IEEE double-precision value without rounding.)
5606 // If any of those low 11 bits were not zero originally, make sure
5607 // bit 12 (value 2048) is set instead, so that the final rounding
5608 // to single-precision gets the correct result.
5609 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5610 SINT, DAG.getConstant(2047, MVT::i64));
5611 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5612 Round, DAG.getConstant(2047, MVT::i64));
5613 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5614 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5615 Round, DAG.getConstant(-2048, MVT::i64));
5617 // However, we cannot use that value unconditionally: if the magnitude
5618 // of the input value is small, the bit-twiddling we did above might
5619 // end up visibly changing the output. Fortunately, in that case, we
5620 // don't need to twiddle bits since the original input will convert
5621 // exactly to double-precision floating-point already. Therefore,
5622 // construct a conditional to use the original value if the top 11
5623 // bits are all sign-bit copies, and use the rounded value computed
5625 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5626 SINT, DAG.getConstant(53, MVT::i32));
5627 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5628 Cond, DAG.getConstant(1, MVT::i64));
5629 Cond = DAG.getSetCC(dl, MVT::i32,
5630 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5632 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5638 MachineFunction &MF = DAG.getMachineFunction();
5639 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
5640 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
5641 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
5643 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5644 } else if (Subtarget.hasLFIWAX() &&
5645 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
5646 MachineMemOperand *MMO =
5647 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5648 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5649 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5650 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
5651 DAG.getVTList(MVT::f64, MVT::Other),
5652 Ops, MVT::i32, MMO);
5653 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5654 } else if (Subtarget.hasFPCVT() &&
5655 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
5656 MachineMemOperand *MMO =
5657 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5658 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5659 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5660 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
5661 DAG.getVTList(MVT::f64, MVT::Other),
5662 Ops, MVT::i32, MMO);
5663 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
5664 } else if (((Subtarget.hasLFIWAX() &&
5665 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
5666 (Subtarget.hasFPCVT() &&
5667 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
5668 SINT.getOperand(0).getValueType() == MVT::i32) {
5669 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5670 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5672 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5673 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5676 DAG.getStore(DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
5677 MachinePointerInfo::getFixedStack(FrameIdx),
5680 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5681 "Expected an i32 store");
5685 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5688 MachineMemOperand *MMO =
5689 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5690 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5691 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5692 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
5693 PPCISD::LFIWZX : PPCISD::LFIWAX,
5694 dl, DAG.getVTList(MVT::f64, MVT::Other),
5695 Ops, MVT::i32, MMO);
5697 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5699 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5701 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5702 FP = DAG.getNode(ISD::FP_ROUND, dl,
5703 MVT::f32, FP, DAG.getIntPtrConstant(0));
5707 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5708 "Unhandled INT_TO_FP type in custom expander!");
5709 // Since we only generate this in 64-bit mode, we can take advantage of
5710 // 64-bit registers. In particular, sign extend the input value into the
5711 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5712 // then lfd it and fcfid it.
5713 MachineFunction &MF = DAG.getMachineFunction();
5714 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5715 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5718 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5721 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
5723 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5724 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5726 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5727 MachinePointerInfo::getFixedStack(FrameIdx),
5730 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5731 "Expected an i32 store");
5735 RLI.MPI = MachinePointerInfo::getFixedStack(FrameIdx);
5739 MachineMemOperand *MMO =
5740 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
5741 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
5742 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
5743 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5744 PPCISD::LFIWZX : PPCISD::LFIWAX,
5745 dl, DAG.getVTList(MVT::f64, MVT::Other),
5746 Ops, MVT::i32, MMO);
5748 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
5750 assert(Subtarget.isPPC64() &&
5751 "i32->FP without LFIWAX supported only on PPC64");
5753 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5754 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5756 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5759 // STD the extended value into the stack slot.
5760 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5761 MachinePointerInfo::getFixedStack(FrameIdx),
5764 // Load the value as a double.
5765 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5766 MachinePointerInfo::getFixedStack(FrameIdx),
5767 false, false, false, 0);
5770 // FCFID it and return it.
5771 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5772 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5773 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5777 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5778 SelectionDAG &DAG) const {
5781 The rounding mode is in bits 30:31 of FPSR, and has the following
5788 FLT_ROUNDS, on the other hand, expects the following:
5795 To perform the conversion, we do:
5796 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5799 MachineFunction &MF = DAG.getMachineFunction();
5800 EVT VT = Op.getValueType();
5801 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5803 // Save FP Control Word to register
5805 MVT::f64, // return register
5806 MVT::Glue // unused in this context
5808 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5810 // Save FP register to stack slot
5811 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5812 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5813 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5814 StackSlot, MachinePointerInfo(), false, false,0);
5816 // Load FP Control Word from low 32 bits of stack slot.
5817 SDValue Four = DAG.getConstant(4, PtrVT);
5818 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5819 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5820 false, false, false, 0);
5822 // Transform as necessary
5824 DAG.getNode(ISD::AND, dl, MVT::i32,
5825 CWD, DAG.getConstant(3, MVT::i32));
5827 DAG.getNode(ISD::SRL, dl, MVT::i32,
5828 DAG.getNode(ISD::AND, dl, MVT::i32,
5829 DAG.getNode(ISD::XOR, dl, MVT::i32,
5830 CWD, DAG.getConstant(3, MVT::i32)),
5831 DAG.getConstant(3, MVT::i32)),
5832 DAG.getConstant(1, MVT::i32));
5835 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5837 return DAG.getNode((VT.getSizeInBits() < 16 ?
5838 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5841 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5842 EVT VT = Op.getValueType();
5843 unsigned BitWidth = VT.getSizeInBits();
5845 assert(Op.getNumOperands() == 3 &&
5846 VT == Op.getOperand(1).getValueType() &&
5849 // Expand into a bunch of logical ops. Note that these ops
5850 // depend on the PPC behavior for oversized shift amounts.
5851 SDValue Lo = Op.getOperand(0);
5852 SDValue Hi = Op.getOperand(1);
5853 SDValue Amt = Op.getOperand(2);
5854 EVT AmtVT = Amt.getValueType();
5856 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5857 DAG.getConstant(BitWidth, AmtVT), Amt);
5858 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5859 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5860 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5861 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5862 DAG.getConstant(-BitWidth, AmtVT));
5863 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5864 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5865 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5866 SDValue OutOps[] = { OutLo, OutHi };
5867 return DAG.getMergeValues(OutOps, dl);
5870 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5871 EVT VT = Op.getValueType();
5873 unsigned BitWidth = VT.getSizeInBits();
5874 assert(Op.getNumOperands() == 3 &&
5875 VT == Op.getOperand(1).getValueType() &&
5878 // Expand into a bunch of logical ops. Note that these ops
5879 // depend on the PPC behavior for oversized shift amounts.
5880 SDValue Lo = Op.getOperand(0);
5881 SDValue Hi = Op.getOperand(1);
5882 SDValue Amt = Op.getOperand(2);
5883 EVT AmtVT = Amt.getValueType();
5885 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5886 DAG.getConstant(BitWidth, AmtVT), Amt);
5887 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5888 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5889 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5890 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5891 DAG.getConstant(-BitWidth, AmtVT));
5892 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5893 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5894 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5895 SDValue OutOps[] = { OutLo, OutHi };
5896 return DAG.getMergeValues(OutOps, dl);
5899 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5901 EVT VT = Op.getValueType();
5902 unsigned BitWidth = VT.getSizeInBits();
5903 assert(Op.getNumOperands() == 3 &&
5904 VT == Op.getOperand(1).getValueType() &&
5907 // Expand into a bunch of logical ops, followed by a select_cc.
5908 SDValue Lo = Op.getOperand(0);
5909 SDValue Hi = Op.getOperand(1);
5910 SDValue Amt = Op.getOperand(2);
5911 EVT AmtVT = Amt.getValueType();
5913 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5914 DAG.getConstant(BitWidth, AmtVT), Amt);
5915 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5916 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5917 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5918 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5919 DAG.getConstant(-BitWidth, AmtVT));
5920 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5921 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5922 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5923 Tmp4, Tmp6, ISD::SETLE);
5924 SDValue OutOps[] = { OutLo, OutHi };
5925 return DAG.getMergeValues(OutOps, dl);
5928 //===----------------------------------------------------------------------===//
5929 // Vector related lowering.
5932 /// BuildSplatI - Build a canonical splati of Val with an element size of
5933 /// SplatSize. Cast the result to VT.
5934 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5935 SelectionDAG &DAG, SDLoc dl) {
5936 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5938 static const EVT VTys[] = { // canonical VT to use for each size.
5939 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5942 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5944 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5948 EVT CanonicalVT = VTys[SplatSize-1];
5950 // Build a canonical splat for this value.
5951 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5952 SmallVector<SDValue, 8> Ops;
5953 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5954 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5955 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5958 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5959 /// specified intrinsic ID.
5960 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5961 SelectionDAG &DAG, SDLoc dl,
5962 EVT DestVT = MVT::Other) {
5963 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5964 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5965 DAG.getConstant(IID, MVT::i32), Op);
5968 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5969 /// specified intrinsic ID.
5970 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5971 SelectionDAG &DAG, SDLoc dl,
5972 EVT DestVT = MVT::Other) {
5973 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5974 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5975 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5978 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5979 /// specified intrinsic ID.
5980 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5981 SDValue Op2, SelectionDAG &DAG,
5982 SDLoc dl, EVT DestVT = MVT::Other) {
5983 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5984 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5985 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5989 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5990 /// amount. The result has the specified value type.
5991 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5992 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5993 // Force LHS/RHS to be the right type.
5994 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5995 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5998 for (unsigned i = 0; i != 16; ++i)
6000 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6001 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6004 // If this is a case we can't handle, return null and let the default
6005 // expansion code take care of it. If we CAN select this case, and if it
6006 // selects to a single instruction, return Op. Otherwise, if we can codegen
6007 // this case more efficiently than a constant pool load, lower it to the
6008 // sequence of ops that should be used.
6009 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6010 SelectionDAG &DAG) const {
6012 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6013 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6015 // Check if this is a splat of a constant value.
6016 APInt APSplatBits, APSplatUndef;
6017 unsigned SplatBitSize;
6019 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6020 HasAnyUndefs, 0, true) || SplatBitSize > 32)
6023 unsigned SplatBits = APSplatBits.getZExtValue();
6024 unsigned SplatUndef = APSplatUndef.getZExtValue();
6025 unsigned SplatSize = SplatBitSize / 8;
6027 // First, handle single instruction cases.
6030 if (SplatBits == 0) {
6031 // Canonicalize all zero vectors to be v4i32.
6032 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6033 SDValue Z = DAG.getConstant(0, MVT::i32);
6034 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6035 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6040 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6041 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6043 if (SextVal >= -16 && SextVal <= 15)
6044 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6047 // Two instruction sequences.
6049 // If this value is in the range [-32,30] and is even, use:
6050 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6051 // If this value is in the range [17,31] and is odd, use:
6052 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6053 // If this value is in the range [-31,-17] and is odd, use:
6054 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6055 // Note the last two are three-instruction sequences.
6056 if (SextVal >= -32 && SextVal <= 31) {
6057 // To avoid having these optimizations undone by constant folding,
6058 // we convert to a pseudo that will be expanded later into one of
6060 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
6061 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6062 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6063 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
6064 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6065 if (VT == Op.getValueType())
6068 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6071 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6072 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6074 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6075 // Make -1 and vspltisw -1:
6076 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6078 // Make the VSLW intrinsic, computing 0x8000_0000.
6079 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6082 // xor by OnesV to invert it.
6083 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6084 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6087 // The remaining cases assume either big endian element order or
6088 // a splat-size that equates to the element size of the vector
6089 // to be built. An example that doesn't work for little endian is
6090 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
6091 // and a vector element size of 16 bits. The code below will
6092 // produce the vector in big endian element order, which for little
6093 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
6095 // For now, just avoid these optimizations in that case.
6096 // FIXME: Develop correct optimizations for LE with mismatched
6097 // splat and element sizes.
6099 if (Subtarget.isLittleEndian() &&
6100 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
6103 // Check to see if this is a wide variety of vsplti*, binop self cases.
6104 static const signed char SplatCsts[] = {
6105 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6106 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6109 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6110 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6111 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6112 int i = SplatCsts[idx];
6114 // Figure out what shift amount will be used by altivec if shifted by i in
6116 unsigned TypeShiftAmt = i & (SplatBitSize-1);
6118 // vsplti + shl self.
6119 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
6120 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6121 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6122 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
6123 Intrinsic::ppc_altivec_vslw
6125 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6126 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6129 // vsplti + srl self.
6130 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6131 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6132 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6133 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
6134 Intrinsic::ppc_altivec_vsrw
6136 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6137 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6140 // vsplti + sra self.
6141 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
6142 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6143 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6144 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
6145 Intrinsic::ppc_altivec_vsraw
6147 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6148 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6151 // vsplti + rol self.
6152 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
6153 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
6154 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
6155 static const unsigned IIDs[] = { // Intrinsic to use for each size.
6156 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
6157 Intrinsic::ppc_altivec_vrlw
6159 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
6160 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6163 // t = vsplti c, result = vsldoi t, t, 1
6164 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
6165 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6166 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
6168 // t = vsplti c, result = vsldoi t, t, 2
6169 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
6170 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6171 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
6173 // t = vsplti c, result = vsldoi t, t, 3
6174 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
6175 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
6176 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
6183 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
6184 /// the specified operations to build the shuffle.
6185 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
6186 SDValue RHS, SelectionDAG &DAG,
6188 unsigned OpNum = (PFEntry >> 26) & 0x0F;
6189 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
6190 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
6193 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
6205 if (OpNum == OP_COPY) {
6206 if (LHSID == (1*9+2)*9+3) return LHS;
6207 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
6211 SDValue OpLHS, OpRHS;
6212 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
6213 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
6217 default: llvm_unreachable("Unknown i32 permute!");
6219 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
6220 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
6221 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
6222 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
6225 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
6226 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
6227 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
6228 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
6231 for (unsigned i = 0; i != 16; ++i)
6232 ShufIdxs[i] = (i&3)+0;
6235 for (unsigned i = 0; i != 16; ++i)
6236 ShufIdxs[i] = (i&3)+4;
6239 for (unsigned i = 0; i != 16; ++i)
6240 ShufIdxs[i] = (i&3)+8;
6243 for (unsigned i = 0; i != 16; ++i)
6244 ShufIdxs[i] = (i&3)+12;
6247 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
6249 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
6251 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
6253 EVT VT = OpLHS.getValueType();
6254 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
6255 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
6256 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
6257 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6260 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
6261 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
6262 /// return the code it can be lowered into. Worst case, it can always be
6263 /// lowered into a vperm.
6264 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
6265 SelectionDAG &DAG) const {
6267 SDValue V1 = Op.getOperand(0);
6268 SDValue V2 = Op.getOperand(1);
6269 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
6270 EVT VT = Op.getValueType();
6271 bool isLittleEndian = Subtarget.isLittleEndian();
6273 // Cases that are handled by instructions that take permute immediates
6274 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
6275 // selected by the instruction selector.
6276 if (V2.getOpcode() == ISD::UNDEF) {
6277 if (PPC::isSplatShuffleMask(SVOp, 1) ||
6278 PPC::isSplatShuffleMask(SVOp, 2) ||
6279 PPC::isSplatShuffleMask(SVOp, 4) ||
6280 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
6281 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
6282 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
6283 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
6284 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
6285 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
6286 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
6287 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
6288 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG)) {
6293 // Altivec has a variety of "shuffle immediates" that take two vector inputs
6294 // and produce a fixed permutation. If any of these match, do not lower to
6296 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
6297 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6298 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
6299 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
6300 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6301 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6302 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
6303 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
6304 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
6305 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG))
6308 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
6309 // perfect shuffle table to emit an optimal matching sequence.
6310 ArrayRef<int> PermMask = SVOp->getMask();
6312 unsigned PFIndexes[4];
6313 bool isFourElementShuffle = true;
6314 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
6315 unsigned EltNo = 8; // Start out undef.
6316 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
6317 if (PermMask[i*4+j] < 0)
6318 continue; // Undef, ignore it.
6320 unsigned ByteSource = PermMask[i*4+j];
6321 if ((ByteSource & 3) != j) {
6322 isFourElementShuffle = false;
6327 EltNo = ByteSource/4;
6328 } else if (EltNo != ByteSource/4) {
6329 isFourElementShuffle = false;
6333 PFIndexes[i] = EltNo;
6336 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
6337 // perfect shuffle vector to determine if it is cost effective to do this as
6338 // discrete instructions, or whether we should use a vperm.
6339 // For now, we skip this for little endian until such time as we have a
6340 // little-endian perfect shuffle table.
6341 if (isFourElementShuffle && !isLittleEndian) {
6342 // Compute the index in the perfect shuffle table.
6343 unsigned PFTableIndex =
6344 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
6346 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
6347 unsigned Cost = (PFEntry >> 30);
6349 // Determining when to avoid vperm is tricky. Many things affect the cost
6350 // of vperm, particularly how many times the perm mask needs to be computed.
6351 // For example, if the perm mask can be hoisted out of a loop or is already
6352 // used (perhaps because there are multiple permutes with the same shuffle
6353 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
6354 // the loop requires an extra register.
6356 // As a compromise, we only emit discrete instructions if the shuffle can be
6357 // generated in 3 or fewer operations. When we have loop information
6358 // available, if this block is within a loop, we should avoid using vperm
6359 // for 3-operation perms and use a constant pool load instead.
6361 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
6364 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
6365 // vector that will get spilled to the constant pool.
6366 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
6368 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
6369 // that it is in input element units, not in bytes. Convert now.
6371 // For little endian, the order of the input vectors is reversed, and
6372 // the permutation mask is complemented with respect to 31. This is
6373 // necessary to produce proper semantics with the big-endian-biased vperm
6375 EVT EltVT = V1.getValueType().getVectorElementType();
6376 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
6378 SmallVector<SDValue, 16> ResultMask;
6379 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
6380 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
6382 for (unsigned j = 0; j != BytesPerElement; ++j)
6384 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
6387 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
6391 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
6394 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6397 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
6401 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
6402 /// altivec comparison. If it is, return true and fill in Opc/isDot with
6403 /// information about the intrinsic.
6404 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
6406 unsigned IntrinsicID =
6407 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
6410 switch (IntrinsicID) {
6411 default: return false;
6412 // Comparison predicates.
6413 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
6414 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
6415 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
6416 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
6417 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
6418 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
6419 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
6420 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
6421 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
6422 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
6423 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
6424 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
6425 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
6427 // Normal Comparisons.
6428 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
6429 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
6430 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
6431 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
6432 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
6433 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
6434 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
6435 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
6436 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
6437 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
6438 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
6439 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
6440 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
6445 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
6446 /// lower, do it, otherwise return null.
6447 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
6448 SelectionDAG &DAG) const {
6449 // If this is a lowered altivec predicate compare, CompareOpc is set to the
6450 // opcode number of the comparison.
6454 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
6455 return SDValue(); // Don't custom lower most intrinsics.
6457 // If this is a non-dot comparison, make the VCMP node and we are done.
6459 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
6460 Op.getOperand(1), Op.getOperand(2),
6461 DAG.getConstant(CompareOpc, MVT::i32));
6462 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
6465 // Create the PPCISD altivec 'dot' comparison node.
6467 Op.getOperand(2), // LHS
6468 Op.getOperand(3), // RHS
6469 DAG.getConstant(CompareOpc, MVT::i32)
6471 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
6472 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
6474 // Now that we have the comparison, emit a copy from the CR to a GPR.
6475 // This is flagged to the above dot comparison.
6476 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
6477 DAG.getRegister(PPC::CR6, MVT::i32),
6478 CompNode.getValue(1));
6480 // Unpack the result based on how the target uses it.
6481 unsigned BitNo; // Bit # of CR6.
6482 bool InvertBit; // Invert result?
6483 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6484 default: // Can't happen, don't crash on invalid number though.
6485 case 0: // Return the value of the EQ bit of CR6.
6486 BitNo = 0; InvertBit = false;
6488 case 1: // Return the inverted value of the EQ bit of CR6.
6489 BitNo = 0; InvertBit = true;
6491 case 2: // Return the value of the LT bit of CR6.
6492 BitNo = 2; InvertBit = false;
6494 case 3: // Return the inverted value of the LT bit of CR6.
6495 BitNo = 2; InvertBit = true;
6499 // Shift the bit into the low position.
6500 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6501 DAG.getConstant(8-(3-BitNo), MVT::i32));
6503 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6504 DAG.getConstant(1, MVT::i32));
6506 // If we are supposed to, toggle the bit.
6508 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6509 DAG.getConstant(1, MVT::i32));
6513 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6514 SelectionDAG &DAG) const {
6516 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6517 // instructions), but for smaller types, we need to first extend up to v2i32
6518 // before doing going farther.
6519 if (Op.getValueType() == MVT::v2i64) {
6520 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6521 if (ExtVT != MVT::v2i32) {
6522 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6523 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6524 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6525 ExtVT.getVectorElementType(), 4)));
6526 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6527 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6528 DAG.getValueType(MVT::v2i32));
6537 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6538 SelectionDAG &DAG) const {
6540 // Create a stack slot that is 16-byte aligned.
6541 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6542 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6543 EVT PtrVT = getPointerTy();
6544 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6546 // Store the input value into Value#0 of the stack slot.
6547 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6548 Op.getOperand(0), FIdx, MachinePointerInfo(),
6551 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6552 false, false, false, 0);
6555 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6557 if (Op.getValueType() == MVT::v4i32) {
6558 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6560 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6561 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6563 SDValue RHSSwap = // = vrlw RHS, 16
6564 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6566 // Shrinkify inputs to v8i16.
6567 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6568 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6569 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6571 // Low parts multiplied together, generating 32-bit results (we ignore the
6573 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6574 LHS, RHS, DAG, dl, MVT::v4i32);
6576 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6577 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6578 // Shift the high parts up 16 bits.
6579 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6581 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6582 } else if (Op.getValueType() == MVT::v8i16) {
6583 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6585 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6587 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6588 LHS, RHS, Zero, DAG, dl);
6589 } else if (Op.getValueType() == MVT::v16i8) {
6590 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6591 bool isLittleEndian = Subtarget.isLittleEndian();
6593 // Multiply the even 8-bit parts, producing 16-bit sums.
6594 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6595 LHS, RHS, DAG, dl, MVT::v8i16);
6596 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6598 // Multiply the odd 8-bit parts, producing 16-bit sums.
6599 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6600 LHS, RHS, DAG, dl, MVT::v8i16);
6601 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6603 // Merge the results together. Because vmuleub and vmuloub are
6604 // instructions with a big-endian bias, we must reverse the
6605 // element numbering and reverse the meaning of "odd" and "even"
6606 // when generating little endian code.
6608 for (unsigned i = 0; i != 8; ++i) {
6609 if (isLittleEndian) {
6611 Ops[i*2+1] = 2*i+16;
6614 Ops[i*2+1] = 2*i+1+16;
6618 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6620 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6622 llvm_unreachable("Unknown mul to lower!");
6626 /// LowerOperation - Provide custom lowering hooks for some operations.
6628 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6629 switch (Op.getOpcode()) {
6630 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6631 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6632 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6633 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6634 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6635 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6636 case ISD::SETCC: return LowerSETCC(Op, DAG);
6637 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6638 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6640 return LowerVASTART(Op, DAG, Subtarget);
6643 return LowerVAARG(Op, DAG, Subtarget);
6646 return LowerVACOPY(Op, DAG, Subtarget);
6648 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6649 case ISD::DYNAMIC_STACKALLOC:
6650 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6652 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6653 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6655 case ISD::LOAD: return LowerLOAD(Op, DAG);
6656 case ISD::STORE: return LowerSTORE(Op, DAG);
6657 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6658 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6659 case ISD::FP_TO_UINT:
6660 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6662 case ISD::UINT_TO_FP:
6663 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6664 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6666 // Lower 64-bit shifts.
6667 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6668 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6669 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6671 // Vector-related lowering.
6672 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6673 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6674 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6675 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6676 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6677 case ISD::MUL: return LowerMUL(Op, DAG);
6679 // For counter-based loop handling.
6680 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6682 // Frame & Return address.
6683 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6684 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6688 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6689 SmallVectorImpl<SDValue>&Results,
6690 SelectionDAG &DAG) const {
6691 const TargetMachine &TM = getTargetMachine();
6693 switch (N->getOpcode()) {
6695 llvm_unreachable("Do not know how to custom type legalize this operation!");
6696 case ISD::READCYCLECOUNTER: {
6697 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
6698 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
6700 Results.push_back(RTB);
6701 Results.push_back(RTB.getValue(1));
6702 Results.push_back(RTB.getValue(2));
6705 case ISD::INTRINSIC_W_CHAIN: {
6706 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6707 Intrinsic::ppc_is_decremented_ctr_nonzero)
6710 assert(N->getValueType(0) == MVT::i1 &&
6711 "Unexpected result type for CTR decrement intrinsic");
6712 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6713 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6714 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6717 Results.push_back(NewInt);
6718 Results.push_back(NewInt.getValue(1));
6722 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6723 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6726 EVT VT = N->getValueType(0);
6728 if (VT == MVT::i64) {
6729 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6731 Results.push_back(NewNode);
6732 Results.push_back(NewNode.getValue(1));
6736 case ISD::FP_ROUND_INREG: {
6737 assert(N->getValueType(0) == MVT::ppcf128);
6738 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6739 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6740 MVT::f64, N->getOperand(0),
6741 DAG.getIntPtrConstant(0));
6742 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6743 MVT::f64, N->getOperand(0),
6744 DAG.getIntPtrConstant(1));
6746 // Add the two halves of the long double in round-to-zero mode.
6747 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6749 // We know the low half is about to be thrown away, so just use something
6751 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6755 case ISD::FP_TO_SINT:
6756 // LowerFP_TO_INT() can only handle f32 and f64.
6757 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6759 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6765 //===----------------------------------------------------------------------===//
6766 // Other Lowering Code
6767 //===----------------------------------------------------------------------===//
6769 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
6770 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
6771 Function *Func = Intrinsic::getDeclaration(M, Id);
6772 return Builder.CreateCall(Func);
6775 // The mappings for emitLeading/TrailingFence is taken from
6776 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
6777 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
6778 AtomicOrdering Ord, bool IsStore,
6779 bool IsLoad) const {
6780 if (Ord == SequentiallyConsistent)
6781 return callIntrinsic(Builder, Intrinsic::ppc_sync);
6782 else if (isAtLeastRelease(Ord))
6783 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6788 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
6789 AtomicOrdering Ord, bool IsStore,
6790 bool IsLoad) const {
6791 if (IsLoad && isAtLeastAcquire(Ord))
6792 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
6793 // FIXME: this is too conservative, a dependent branch + isync is enough.
6794 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
6795 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
6796 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
6802 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6803 bool is64bit, unsigned BinOpcode) const {
6804 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6805 const TargetInstrInfo *TII =
6806 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6808 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6809 MachineFunction *F = BB->getParent();
6810 MachineFunction::iterator It = BB;
6813 unsigned dest = MI->getOperand(0).getReg();
6814 unsigned ptrA = MI->getOperand(1).getReg();
6815 unsigned ptrB = MI->getOperand(2).getReg();
6816 unsigned incr = MI->getOperand(3).getReg();
6817 DebugLoc dl = MI->getDebugLoc();
6819 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6820 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6821 F->insert(It, loopMBB);
6822 F->insert(It, exitMBB);
6823 exitMBB->splice(exitMBB->begin(), BB,
6824 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6825 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6827 MachineRegisterInfo &RegInfo = F->getRegInfo();
6828 unsigned TmpReg = (!BinOpcode) ? incr :
6829 RegInfo.createVirtualRegister( is64bit ? &PPC::G8RCRegClass
6830 : &PPC::GPRCRegClass);
6834 // fallthrough --> loopMBB
6835 BB->addSuccessor(loopMBB);
6838 // l[wd]arx dest, ptr
6839 // add r0, dest, incr
6840 // st[wd]cx. r0, ptr
6842 // fallthrough --> exitMBB
6844 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6845 .addReg(ptrA).addReg(ptrB);
6847 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6848 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6849 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6850 BuildMI(BB, dl, TII->get(PPC::BCC))
6851 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6852 BB->addSuccessor(loopMBB);
6853 BB->addSuccessor(exitMBB);
6862 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6863 MachineBasicBlock *BB,
6864 bool is8bit, // operation
6865 unsigned BinOpcode) const {
6866 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6867 const TargetInstrInfo *TII =
6868 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6869 // In 64 bit mode we have to use 64 bits for addresses, even though the
6870 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6871 // registers without caring whether they're 32 or 64, but here we're
6872 // doing actual arithmetic on the addresses.
6873 bool is64bit = Subtarget.isPPC64();
6874 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6876 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6877 MachineFunction *F = BB->getParent();
6878 MachineFunction::iterator It = BB;
6881 unsigned dest = MI->getOperand(0).getReg();
6882 unsigned ptrA = MI->getOperand(1).getReg();
6883 unsigned ptrB = MI->getOperand(2).getReg();
6884 unsigned incr = MI->getOperand(3).getReg();
6885 DebugLoc dl = MI->getDebugLoc();
6887 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6888 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6889 F->insert(It, loopMBB);
6890 F->insert(It, exitMBB);
6891 exitMBB->splice(exitMBB->begin(), BB,
6892 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6893 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6895 MachineRegisterInfo &RegInfo = F->getRegInfo();
6896 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
6897 : &PPC::GPRCRegClass;
6898 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6899 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6900 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6901 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6902 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6903 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6904 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6905 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6906 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6907 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6908 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6910 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6914 // fallthrough --> loopMBB
6915 BB->addSuccessor(loopMBB);
6917 // The 4-byte load must be aligned, while a char or short may be
6918 // anywhere in the word. Hence all this nasty bookkeeping code.
6919 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6920 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6921 // xori shift, shift1, 24 [16]
6922 // rlwinm ptr, ptr1, 0, 0, 29
6923 // slw incr2, incr, shift
6924 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6925 // slw mask, mask2, shift
6927 // lwarx tmpDest, ptr
6928 // add tmp, tmpDest, incr2
6929 // andc tmp2, tmpDest, mask
6930 // and tmp3, tmp, mask
6931 // or tmp4, tmp3, tmp2
6934 // fallthrough --> exitMBB
6935 // srw dest, tmpDest, shift
6936 if (ptrA != ZeroReg) {
6937 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6938 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6939 .addReg(ptrA).addReg(ptrB);
6943 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6944 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6945 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6946 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6948 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6949 .addReg(Ptr1Reg).addImm(0).addImm(61);
6951 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6952 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6953 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6954 .addReg(incr).addReg(ShiftReg);
6956 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6958 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6959 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6961 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6962 .addReg(Mask2Reg).addReg(ShiftReg);
6965 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6966 .addReg(ZeroReg).addReg(PtrReg);
6968 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6969 .addReg(Incr2Reg).addReg(TmpDestReg);
6970 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6971 .addReg(TmpDestReg).addReg(MaskReg);
6972 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6973 .addReg(TmpReg).addReg(MaskReg);
6974 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6975 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6976 BuildMI(BB, dl, TII->get(PPC::STWCX))
6977 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6978 BuildMI(BB, dl, TII->get(PPC::BCC))
6979 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6980 BB->addSuccessor(loopMBB);
6981 BB->addSuccessor(exitMBB);
6986 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6991 llvm::MachineBasicBlock*
6992 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6993 MachineBasicBlock *MBB) const {
6994 DebugLoc DL = MI->getDebugLoc();
6995 const TargetInstrInfo *TII =
6996 getTargetMachine().getSubtargetImpl()->getInstrInfo();
6998 MachineFunction *MF = MBB->getParent();
6999 MachineRegisterInfo &MRI = MF->getRegInfo();
7001 const BasicBlock *BB = MBB->getBasicBlock();
7002 MachineFunction::iterator I = MBB;
7006 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7007 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7009 unsigned DstReg = MI->getOperand(0).getReg();
7010 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
7011 assert(RC->hasType(MVT::i32) && "Invalid destination!");
7012 unsigned mainDstReg = MRI.createVirtualRegister(RC);
7013 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
7015 MVT PVT = getPointerTy();
7016 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7017 "Invalid Pointer Size!");
7018 // For v = setjmp(buf), we generate
7021 // SjLjSetup mainMBB
7027 // buf[LabelOffset] = LR
7031 // v = phi(main, restore)
7034 MachineBasicBlock *thisMBB = MBB;
7035 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
7036 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
7037 MF->insert(I, mainMBB);
7038 MF->insert(I, sinkMBB);
7040 MachineInstrBuilder MIB;
7042 // Transfer the remainder of BB and its successor edges to sinkMBB.
7043 sinkMBB->splice(sinkMBB->begin(), MBB,
7044 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
7045 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
7047 // Note that the structure of the jmp_buf used here is not compatible
7048 // with that used by libc, and is not designed to be. Specifically, it
7049 // stores only those 'reserved' registers that LLVM does not otherwise
7050 // understand how to spill. Also, by convention, by the time this
7051 // intrinsic is called, Clang has already stored the frame address in the
7052 // first slot of the buffer and stack address in the third. Following the
7053 // X86 target code, we'll store the jump address in the second slot. We also
7054 // need to save the TOC pointer (R2) to handle jumps between shared
7055 // libraries, and that will be stored in the fourth slot. The thread
7056 // identifier (R13) is not affected.
7059 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7060 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7061 const int64_t BPOffset = 4 * PVT.getStoreSize();
7063 // Prepare IP either in reg.
7064 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
7065 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
7066 unsigned BufReg = MI->getOperand(1).getReg();
7068 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
7069 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
7073 MIB.setMemRefs(MMOBegin, MMOEnd);
7076 // Naked functions never have a base pointer, and so we use r1. For all
7077 // other functions, this decision must be delayed until during PEI.
7079 if (MF->getFunction()->getAttributes().hasAttribute(
7080 AttributeSet::FunctionIndex, Attribute::Naked))
7081 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
7083 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
7085 MIB = BuildMI(*thisMBB, MI, DL,
7086 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
7090 MIB.setMemRefs(MMOBegin, MMOEnd);
7093 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
7094 const PPCRegisterInfo *TRI =
7095 getTargetMachine().getSubtarget<PPCSubtarget>().getRegisterInfo();
7096 MIB.addRegMask(TRI->getNoPreservedMask());
7098 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
7100 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
7102 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
7104 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
7105 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
7109 MIB = BuildMI(mainMBB, DL,
7110 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
7113 if (Subtarget.isPPC64()) {
7114 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
7116 .addImm(LabelOffset)
7119 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
7121 .addImm(LabelOffset)
7125 MIB.setMemRefs(MMOBegin, MMOEnd);
7127 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
7128 mainMBB->addSuccessor(sinkMBB);
7131 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
7132 TII->get(PPC::PHI), DstReg)
7133 .addReg(mainDstReg).addMBB(mainMBB)
7134 .addReg(restoreDstReg).addMBB(thisMBB);
7136 MI->eraseFromParent();
7141 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
7142 MachineBasicBlock *MBB) const {
7143 DebugLoc DL = MI->getDebugLoc();
7144 const TargetInstrInfo *TII =
7145 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7147 MachineFunction *MF = MBB->getParent();
7148 MachineRegisterInfo &MRI = MF->getRegInfo();
7151 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
7152 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
7154 MVT PVT = getPointerTy();
7155 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
7156 "Invalid Pointer Size!");
7158 const TargetRegisterClass *RC =
7159 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
7160 unsigned Tmp = MRI.createVirtualRegister(RC);
7161 // Since FP is only updated here but NOT referenced, it's treated as GPR.
7162 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
7163 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
7164 unsigned BP = (PVT == MVT::i64) ? PPC::X30 :
7165 (Subtarget.isSVR4ABI() &&
7166 MF->getTarget().getRelocationModel() == Reloc::PIC_ ?
7167 PPC::R29 : PPC::R30);
7169 MachineInstrBuilder MIB;
7171 const int64_t LabelOffset = 1 * PVT.getStoreSize();
7172 const int64_t SPOffset = 2 * PVT.getStoreSize();
7173 const int64_t TOCOffset = 3 * PVT.getStoreSize();
7174 const int64_t BPOffset = 4 * PVT.getStoreSize();
7176 unsigned BufReg = MI->getOperand(0).getReg();
7178 // Reload FP (the jumped-to function may not have had a
7179 // frame pointer, and if so, then its r31 will be restored
7181 if (PVT == MVT::i64) {
7182 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
7186 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
7190 MIB.setMemRefs(MMOBegin, MMOEnd);
7193 if (PVT == MVT::i64) {
7194 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
7195 .addImm(LabelOffset)
7198 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
7199 .addImm(LabelOffset)
7202 MIB.setMemRefs(MMOBegin, MMOEnd);
7205 if (PVT == MVT::i64) {
7206 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
7210 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
7214 MIB.setMemRefs(MMOBegin, MMOEnd);
7217 if (PVT == MVT::i64) {
7218 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
7222 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
7226 MIB.setMemRefs(MMOBegin, MMOEnd);
7229 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
7230 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
7234 MIB.setMemRefs(MMOBegin, MMOEnd);
7238 BuildMI(*MBB, MI, DL,
7239 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
7240 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
7242 MI->eraseFromParent();
7247 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
7248 MachineBasicBlock *BB) const {
7249 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
7250 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
7251 return emitEHSjLjSetJmp(MI, BB);
7252 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
7253 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
7254 return emitEHSjLjLongJmp(MI, BB);
7257 const TargetInstrInfo *TII =
7258 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7260 // To "insert" these instructions we actually have to insert their
7261 // control-flow patterns.
7262 const BasicBlock *LLVM_BB = BB->getBasicBlock();
7263 MachineFunction::iterator It = BB;
7266 MachineFunction *F = BB->getParent();
7268 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7269 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7270 MI->getOpcode() == PPC::SELECT_I4 ||
7271 MI->getOpcode() == PPC::SELECT_I8)) {
7272 SmallVector<MachineOperand, 2> Cond;
7273 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7274 MI->getOpcode() == PPC::SELECT_CC_I8)
7275 Cond.push_back(MI->getOperand(4));
7277 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
7278 Cond.push_back(MI->getOperand(1));
7280 DebugLoc dl = MI->getDebugLoc();
7281 const TargetInstrInfo *TII =
7282 getTargetMachine().getSubtargetImpl()->getInstrInfo();
7283 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
7284 Cond, MI->getOperand(2).getReg(),
7285 MI->getOperand(3).getReg());
7286 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
7287 MI->getOpcode() == PPC::SELECT_CC_I8 ||
7288 MI->getOpcode() == PPC::SELECT_CC_F4 ||
7289 MI->getOpcode() == PPC::SELECT_CC_F8 ||
7290 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
7291 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
7292 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
7293 MI->getOpcode() == PPC::SELECT_I4 ||
7294 MI->getOpcode() == PPC::SELECT_I8 ||
7295 MI->getOpcode() == PPC::SELECT_F4 ||
7296 MI->getOpcode() == PPC::SELECT_F8 ||
7297 MI->getOpcode() == PPC::SELECT_VRRC ||
7298 MI->getOpcode() == PPC::SELECT_VSFRC ||
7299 MI->getOpcode() == PPC::SELECT_VSRC) {
7300 // The incoming instruction knows the destination vreg to set, the
7301 // condition code register to branch on, the true/false values to
7302 // select between, and a branch opcode to use.
7307 // cmpTY ccX, r1, r2
7309 // fallthrough --> copy0MBB
7310 MachineBasicBlock *thisMBB = BB;
7311 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
7312 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7313 DebugLoc dl = MI->getDebugLoc();
7314 F->insert(It, copy0MBB);
7315 F->insert(It, sinkMBB);
7317 // Transfer the remainder of BB and its successor edges to sinkMBB.
7318 sinkMBB->splice(sinkMBB->begin(), BB,
7319 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7320 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7322 // Next, add the true and fallthrough blocks as its successors.
7323 BB->addSuccessor(copy0MBB);
7324 BB->addSuccessor(sinkMBB);
7326 if (MI->getOpcode() == PPC::SELECT_I4 ||
7327 MI->getOpcode() == PPC::SELECT_I8 ||
7328 MI->getOpcode() == PPC::SELECT_F4 ||
7329 MI->getOpcode() == PPC::SELECT_F8 ||
7330 MI->getOpcode() == PPC::SELECT_VRRC ||
7331 MI->getOpcode() == PPC::SELECT_VSFRC ||
7332 MI->getOpcode() == PPC::SELECT_VSRC) {
7333 BuildMI(BB, dl, TII->get(PPC::BC))
7334 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7336 unsigned SelectPred = MI->getOperand(4).getImm();
7337 BuildMI(BB, dl, TII->get(PPC::BCC))
7338 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
7342 // %FalseValue = ...
7343 // # fallthrough to sinkMBB
7346 // Update machine-CFG edges
7347 BB->addSuccessor(sinkMBB);
7350 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
7353 BuildMI(*BB, BB->begin(), dl,
7354 TII->get(PPC::PHI), MI->getOperand(0).getReg())
7355 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
7356 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
7357 } else if (MI->getOpcode() == PPC::ReadTB) {
7358 // To read the 64-bit time-base register on a 32-bit target, we read the
7359 // two halves. Should the counter have wrapped while it was being read, we
7360 // need to try again.
7363 // mfspr Rx,TBU # load from TBU
7364 // mfspr Ry,TB # load from TB
7365 // mfspr Rz,TBU # load from TBU
7366 // cmpw crX,Rx,Rz # check if ‘old’=’new’
7367 // bne readLoop # branch if they're not equal
7370 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
7371 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
7372 DebugLoc dl = MI->getDebugLoc();
7373 F->insert(It, readMBB);
7374 F->insert(It, sinkMBB);
7376 // Transfer the remainder of BB and its successor edges to sinkMBB.
7377 sinkMBB->splice(sinkMBB->begin(), BB,
7378 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7379 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
7381 BB->addSuccessor(readMBB);
7384 MachineRegisterInfo &RegInfo = F->getRegInfo();
7385 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
7386 unsigned LoReg = MI->getOperand(0).getReg();
7387 unsigned HiReg = MI->getOperand(1).getReg();
7389 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
7390 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
7391 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
7393 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
7395 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
7396 .addReg(HiReg).addReg(ReadAgainReg);
7397 BuildMI(BB, dl, TII->get(PPC::BCC))
7398 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
7400 BB->addSuccessor(readMBB);
7401 BB->addSuccessor(sinkMBB);
7403 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
7404 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
7405 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
7406 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
7407 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
7408 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
7409 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
7410 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
7412 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
7413 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
7414 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
7415 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
7416 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
7417 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
7418 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
7419 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
7421 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
7422 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
7423 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
7424 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
7425 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
7426 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
7427 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
7428 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
7430 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
7431 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
7432 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
7433 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
7434 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
7435 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
7436 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
7437 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
7439 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
7440 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
7441 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
7442 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
7443 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
7444 BB = EmitAtomicBinary(MI, BB, false, PPC::NAND);
7445 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
7446 BB = EmitAtomicBinary(MI, BB, true, PPC::NAND8);
7448 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
7449 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
7450 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
7451 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
7452 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
7453 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
7454 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
7455 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
7457 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
7458 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
7459 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
7460 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
7461 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
7462 BB = EmitAtomicBinary(MI, BB, false, 0);
7463 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
7464 BB = EmitAtomicBinary(MI, BB, true, 0);
7466 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
7467 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
7468 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
7470 unsigned dest = MI->getOperand(0).getReg();
7471 unsigned ptrA = MI->getOperand(1).getReg();
7472 unsigned ptrB = MI->getOperand(2).getReg();
7473 unsigned oldval = MI->getOperand(3).getReg();
7474 unsigned newval = MI->getOperand(4).getReg();
7475 DebugLoc dl = MI->getDebugLoc();
7477 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7478 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7479 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7480 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7481 F->insert(It, loop1MBB);
7482 F->insert(It, loop2MBB);
7483 F->insert(It, midMBB);
7484 F->insert(It, exitMBB);
7485 exitMBB->splice(exitMBB->begin(), BB,
7486 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7487 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7491 // fallthrough --> loopMBB
7492 BB->addSuccessor(loop1MBB);
7495 // l[wd]arx dest, ptr
7496 // cmp[wd] dest, oldval
7499 // st[wd]cx. newval, ptr
7503 // st[wd]cx. dest, ptr
7506 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
7507 .addReg(ptrA).addReg(ptrB);
7508 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
7509 .addReg(oldval).addReg(dest);
7510 BuildMI(BB, dl, TII->get(PPC::BCC))
7511 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7512 BB->addSuccessor(loop2MBB);
7513 BB->addSuccessor(midMBB);
7516 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7517 .addReg(newval).addReg(ptrA).addReg(ptrB);
7518 BuildMI(BB, dl, TII->get(PPC::BCC))
7519 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7520 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7521 BB->addSuccessor(loop1MBB);
7522 BB->addSuccessor(exitMBB);
7525 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
7526 .addReg(dest).addReg(ptrA).addReg(ptrB);
7527 BB->addSuccessor(exitMBB);
7532 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
7533 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
7534 // We must use 64-bit registers for addresses when targeting 64-bit,
7535 // since we're actually doing arithmetic on them. Other registers
7537 bool is64bit = Subtarget.isPPC64();
7538 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
7540 unsigned dest = MI->getOperand(0).getReg();
7541 unsigned ptrA = MI->getOperand(1).getReg();
7542 unsigned ptrB = MI->getOperand(2).getReg();
7543 unsigned oldval = MI->getOperand(3).getReg();
7544 unsigned newval = MI->getOperand(4).getReg();
7545 DebugLoc dl = MI->getDebugLoc();
7547 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
7548 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
7549 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
7550 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
7551 F->insert(It, loop1MBB);
7552 F->insert(It, loop2MBB);
7553 F->insert(It, midMBB);
7554 F->insert(It, exitMBB);
7555 exitMBB->splice(exitMBB->begin(), BB,
7556 std::next(MachineBasicBlock::iterator(MI)), BB->end());
7557 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
7559 MachineRegisterInfo &RegInfo = F->getRegInfo();
7560 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
7561 : &PPC::GPRCRegClass;
7562 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
7563 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
7564 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
7565 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
7566 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
7567 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
7568 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
7569 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
7570 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
7571 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
7572 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
7573 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
7574 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
7576 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
7577 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7580 // fallthrough --> loopMBB
7581 BB->addSuccessor(loop1MBB);
7583 // The 4-byte load must be aligned, while a char or short may be
7584 // anywhere in the word. Hence all this nasty bookkeeping code.
7585 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7586 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7587 // xori shift, shift1, 24 [16]
7588 // rlwinm ptr, ptr1, 0, 0, 29
7589 // slw newval2, newval, shift
7590 // slw oldval2, oldval,shift
7591 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7592 // slw mask, mask2, shift
7593 // and newval3, newval2, mask
7594 // and oldval3, oldval2, mask
7596 // lwarx tmpDest, ptr
7597 // and tmp, tmpDest, mask
7598 // cmpw tmp, oldval3
7601 // andc tmp2, tmpDest, mask
7602 // or tmp4, tmp2, newval3
7607 // stwcx. tmpDest, ptr
7609 // srw dest, tmpDest, shift
7610 if (ptrA != ZeroReg) {
7611 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7612 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7613 .addReg(ptrA).addReg(ptrB);
7617 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7618 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7619 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7620 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7622 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7623 .addReg(Ptr1Reg).addImm(0).addImm(61);
7625 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7626 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7627 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7628 .addReg(newval).addReg(ShiftReg);
7629 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7630 .addReg(oldval).addReg(ShiftReg);
7632 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7634 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7635 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7636 .addReg(Mask3Reg).addImm(65535);
7638 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7639 .addReg(Mask2Reg).addReg(ShiftReg);
7640 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7641 .addReg(NewVal2Reg).addReg(MaskReg);
7642 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7643 .addReg(OldVal2Reg).addReg(MaskReg);
7646 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7647 .addReg(ZeroReg).addReg(PtrReg);
7648 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7649 .addReg(TmpDestReg).addReg(MaskReg);
7650 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7651 .addReg(TmpReg).addReg(OldVal3Reg);
7652 BuildMI(BB, dl, TII->get(PPC::BCC))
7653 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7654 BB->addSuccessor(loop2MBB);
7655 BB->addSuccessor(midMBB);
7658 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7659 .addReg(TmpDestReg).addReg(MaskReg);
7660 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7661 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7662 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7663 .addReg(ZeroReg).addReg(PtrReg);
7664 BuildMI(BB, dl, TII->get(PPC::BCC))
7665 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7666 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7667 BB->addSuccessor(loop1MBB);
7668 BB->addSuccessor(exitMBB);
7671 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7672 .addReg(ZeroReg).addReg(PtrReg);
7673 BB->addSuccessor(exitMBB);
7678 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7680 } else if (MI->getOpcode() == PPC::FADDrtz) {
7681 // This pseudo performs an FADD with rounding mode temporarily forced
7682 // to round-to-zero. We emit this via custom inserter since the FPSCR
7683 // is not modeled at the SelectionDAG level.
7684 unsigned Dest = MI->getOperand(0).getReg();
7685 unsigned Src1 = MI->getOperand(1).getReg();
7686 unsigned Src2 = MI->getOperand(2).getReg();
7687 DebugLoc dl = MI->getDebugLoc();
7689 MachineRegisterInfo &RegInfo = F->getRegInfo();
7690 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7692 // Save FPSCR value.
7693 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7695 // Set rounding mode to round-to-zero.
7696 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7697 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7699 // Perform addition.
7700 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7702 // Restore FPSCR value.
7703 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7704 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7705 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7706 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7707 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7708 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7709 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7710 PPC::ANDIo8 : PPC::ANDIo;
7711 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7712 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7714 MachineRegisterInfo &RegInfo = F->getRegInfo();
7715 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7716 &PPC::GPRCRegClass :
7717 &PPC::G8RCRegClass);
7719 DebugLoc dl = MI->getDebugLoc();
7720 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7721 .addReg(MI->getOperand(1).getReg()).addImm(1);
7722 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7723 MI->getOperand(0).getReg())
7724 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7726 llvm_unreachable("Unexpected instr type to insert");
7729 MI->eraseFromParent(); // The pseudo instruction is gone now.
7733 //===----------------------------------------------------------------------===//
7734 // Target Optimization Hooks
7735 //===----------------------------------------------------------------------===//
7737 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
7738 DAGCombinerInfo &DCI,
7739 unsigned &RefinementSteps,
7740 bool &UseOneConstNR) const {
7741 EVT VT = Operand.getValueType();
7742 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7743 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7744 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7745 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7746 // Convergence is quadratic, so we essentially double the number of digits
7747 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7748 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7749 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7750 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7751 if (VT.getScalarType() == MVT::f64)
7753 UseOneConstNR = true;
7754 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
7759 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
7760 DAGCombinerInfo &DCI,
7761 unsigned &RefinementSteps) const {
7762 EVT VT = Operand.getValueType();
7763 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7764 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7765 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7766 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7767 // Convergence is quadratic, so we essentially double the number of digits
7768 // correct after every iteration. For both FRE and FRSQRTE, the minimum
7769 // architected relative accuracy is 2^-5. When hasRecipPrec(), this is
7770 // 2^-14. IEEE float has 23 digits and double has 52 digits.
7771 RefinementSteps = Subtarget.hasRecipPrec() ? 1 : 3;
7772 if (VT.getScalarType() == MVT::f64)
7774 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
7779 bool PPCTargetLowering::combineRepeatedFPDivisors(unsigned NumUsers) const {
7780 // Note: This functionality is used only when unsafe-fp-math is enabled, and
7781 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
7782 // enabled for division), this functionality is redundant with the default
7783 // combiner logic (once the division -> reciprocal/multiply transformation
7784 // has taken place). As a result, this matters more for older cores than for
7787 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
7788 // reciprocal if there are two or more FDIVs (for embedded cores with only
7789 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
7790 switch (Subtarget.getDarwinDirective()) {
7792 return NumUsers > 2;
7795 case PPC::DIR_E500mc:
7796 case PPC::DIR_E5500:
7797 return NumUsers > 1;
7801 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
7802 unsigned Bytes, int Dist,
7803 SelectionDAG &DAG) {
7804 if (VT.getSizeInBits() / 8 != Bytes)
7807 SDValue BaseLoc = Base->getBasePtr();
7808 if (Loc.getOpcode() == ISD::FrameIndex) {
7809 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7811 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7812 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7813 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7814 int FS = MFI->getObjectSize(FI);
7815 int BFS = MFI->getObjectSize(BFI);
7816 if (FS != BFS || FS != (int)Bytes) return false;
7817 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7821 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7822 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7825 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7826 const GlobalValue *GV1 = nullptr;
7827 const GlobalValue *GV2 = nullptr;
7828 int64_t Offset1 = 0;
7829 int64_t Offset2 = 0;
7830 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7831 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7832 if (isGA1 && isGA2 && GV1 == GV2)
7833 return Offset1 == (Offset2 + Dist*Bytes);
7837 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7838 // not enforce equality of the chain operands.
7839 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
7840 unsigned Bytes, int Dist,
7841 SelectionDAG &DAG) {
7842 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
7843 EVT VT = LS->getMemoryVT();
7844 SDValue Loc = LS->getBasePtr();
7845 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
7848 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
7850 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7851 default: return false;
7852 case Intrinsic::ppc_altivec_lvx:
7853 case Intrinsic::ppc_altivec_lvxl:
7854 case Intrinsic::ppc_vsx_lxvw4x:
7857 case Intrinsic::ppc_vsx_lxvd2x:
7860 case Intrinsic::ppc_altivec_lvebx:
7863 case Intrinsic::ppc_altivec_lvehx:
7866 case Intrinsic::ppc_altivec_lvewx:
7871 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
7874 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
7876 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
7877 default: return false;
7878 case Intrinsic::ppc_altivec_stvx:
7879 case Intrinsic::ppc_altivec_stvxl:
7880 case Intrinsic::ppc_vsx_stxvw4x:
7883 case Intrinsic::ppc_vsx_stxvd2x:
7886 case Intrinsic::ppc_altivec_stvebx:
7889 case Intrinsic::ppc_altivec_stvehx:
7892 case Intrinsic::ppc_altivec_stvewx:
7897 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
7903 // Return true is there is a nearyby consecutive load to the one provided
7904 // (regardless of alignment). We search up and down the chain, looking though
7905 // token factors and other loads (but nothing else). As a result, a true result
7906 // indicates that it is safe to create a new consecutive load adjacent to the
7908 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7909 SDValue Chain = LD->getChain();
7910 EVT VT = LD->getMemoryVT();
7912 SmallSet<SDNode *, 16> LoadRoots;
7913 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7914 SmallSet<SDNode *, 16> Visited;
7916 // First, search up the chain, branching to follow all token-factor operands.
7917 // If we find a consecutive load, then we're done, otherwise, record all
7918 // nodes just above the top-level loads and token factors.
7919 while (!Queue.empty()) {
7920 SDNode *ChainNext = Queue.pop_back_val();
7921 if (!Visited.insert(ChainNext).second)
7924 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
7925 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7928 if (!Visited.count(ChainLD->getChain().getNode()))
7929 Queue.push_back(ChainLD->getChain().getNode());
7930 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7931 for (const SDUse &O : ChainNext->ops())
7932 if (!Visited.count(O.getNode()))
7933 Queue.push_back(O.getNode());
7935 LoadRoots.insert(ChainNext);
7938 // Second, search down the chain, starting from the top-level nodes recorded
7939 // in the first phase. These top-level nodes are the nodes just above all
7940 // loads and token factors. Starting with their uses, recursively look though
7941 // all loads (just the chain uses) and token factors to find a consecutive
7946 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7947 IE = LoadRoots.end(); I != IE; ++I) {
7948 Queue.push_back(*I);
7950 while (!Queue.empty()) {
7951 SDNode *LoadRoot = Queue.pop_back_val();
7952 if (!Visited.insert(LoadRoot).second)
7955 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
7956 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7959 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7960 UE = LoadRoot->use_end(); UI != UE; ++UI)
7961 if (((isa<MemSDNode>(*UI) &&
7962 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7963 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7964 Queue.push_back(*UI);
7971 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7972 DAGCombinerInfo &DCI) const {
7973 SelectionDAG &DAG = DCI.DAG;
7976 assert(Subtarget.useCRBits() &&
7977 "Expecting to be tracking CR bits");
7978 // If we're tracking CR bits, we need to be careful that we don't have:
7979 // trunc(binary-ops(zext(x), zext(y)))
7981 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7982 // such that we're unnecessarily moving things into GPRs when it would be
7983 // better to keep them in CR bits.
7985 // Note that trunc here can be an actual i1 trunc, or can be the effective
7986 // truncation that comes from a setcc or select_cc.
7987 if (N->getOpcode() == ISD::TRUNCATE &&
7988 N->getValueType(0) != MVT::i1)
7991 if (N->getOperand(0).getValueType() != MVT::i32 &&
7992 N->getOperand(0).getValueType() != MVT::i64)
7995 if (N->getOpcode() == ISD::SETCC ||
7996 N->getOpcode() == ISD::SELECT_CC) {
7997 // If we're looking at a comparison, then we need to make sure that the
7998 // high bits (all except for the first) don't matter the result.
8000 cast<CondCodeSDNode>(N->getOperand(
8001 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
8002 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
8004 if (ISD::isSignedIntSetCC(CC)) {
8005 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
8006 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
8008 } else if (ISD::isUnsignedIntSetCC(CC)) {
8009 if (!DAG.MaskedValueIsZero(N->getOperand(0),
8010 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
8011 !DAG.MaskedValueIsZero(N->getOperand(1),
8012 APInt::getHighBitsSet(OpBits, OpBits-1)))
8015 // This is neither a signed nor an unsigned comparison, just make sure
8016 // that the high bits are equal.
8017 APInt Op1Zero, Op1One;
8018 APInt Op2Zero, Op2One;
8019 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
8020 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
8022 // We don't really care about what is known about the first bit (if
8023 // anything), so clear it in all masks prior to comparing them.
8024 Op1Zero.clearBit(0); Op1One.clearBit(0);
8025 Op2Zero.clearBit(0); Op2One.clearBit(0);
8027 if (Op1Zero != Op2Zero || Op1One != Op2One)
8032 // We now know that the higher-order bits are irrelevant, we just need to
8033 // make sure that all of the intermediate operations are bit operations, and
8034 // all inputs are extensions.
8035 if (N->getOperand(0).getOpcode() != ISD::AND &&
8036 N->getOperand(0).getOpcode() != ISD::OR &&
8037 N->getOperand(0).getOpcode() != ISD::XOR &&
8038 N->getOperand(0).getOpcode() != ISD::SELECT &&
8039 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
8040 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
8041 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
8042 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
8043 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
8046 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
8047 N->getOperand(1).getOpcode() != ISD::AND &&
8048 N->getOperand(1).getOpcode() != ISD::OR &&
8049 N->getOperand(1).getOpcode() != ISD::XOR &&
8050 N->getOperand(1).getOpcode() != ISD::SELECT &&
8051 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
8052 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
8053 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
8054 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
8055 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
8058 SmallVector<SDValue, 4> Inputs;
8059 SmallVector<SDValue, 8> BinOps, PromOps;
8060 SmallPtrSet<SDNode *, 16> Visited;
8062 for (unsigned i = 0; i < 2; ++i) {
8063 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8064 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8065 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8066 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8067 isa<ConstantSDNode>(N->getOperand(i)))
8068 Inputs.push_back(N->getOperand(i));
8070 BinOps.push_back(N->getOperand(i));
8072 if (N->getOpcode() == ISD::TRUNCATE)
8076 // Visit all inputs, collect all binary operations (and, or, xor and
8077 // select) that are all fed by extensions.
8078 while (!BinOps.empty()) {
8079 SDValue BinOp = BinOps.back();
8082 if (!Visited.insert(BinOp.getNode()).second)
8085 PromOps.push_back(BinOp);
8087 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8088 // The condition of the select is not promoted.
8089 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8091 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8094 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8095 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8096 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
8097 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
8098 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8099 Inputs.push_back(BinOp.getOperand(i));
8100 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8101 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8102 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8103 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8104 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
8105 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8106 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
8107 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
8108 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
8109 BinOps.push_back(BinOp.getOperand(i));
8111 // We have an input that is not an extension or another binary
8112 // operation; we'll abort this transformation.
8118 // Make sure that this is a self-contained cluster of operations (which
8119 // is not quite the same thing as saying that everything has only one
8121 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8122 if (isa<ConstantSDNode>(Inputs[i]))
8125 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8126 UE = Inputs[i].getNode()->use_end();
8129 if (User != N && !Visited.count(User))
8132 // Make sure that we're not going to promote the non-output-value
8133 // operand(s) or SELECT or SELECT_CC.
8134 // FIXME: Although we could sometimes handle this, and it does occur in
8135 // practice that one of the condition inputs to the select is also one of
8136 // the outputs, we currently can't deal with this.
8137 if (User->getOpcode() == ISD::SELECT) {
8138 if (User->getOperand(0) == Inputs[i])
8140 } else if (User->getOpcode() == ISD::SELECT_CC) {
8141 if (User->getOperand(0) == Inputs[i] ||
8142 User->getOperand(1) == Inputs[i])
8148 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8149 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8150 UE = PromOps[i].getNode()->use_end();
8153 if (User != N && !Visited.count(User))
8156 // Make sure that we're not going to promote the non-output-value
8157 // operand(s) or SELECT or SELECT_CC.
8158 // FIXME: Although we could sometimes handle this, and it does occur in
8159 // practice that one of the condition inputs to the select is also one of
8160 // the outputs, we currently can't deal with this.
8161 if (User->getOpcode() == ISD::SELECT) {
8162 if (User->getOperand(0) == PromOps[i])
8164 } else if (User->getOpcode() == ISD::SELECT_CC) {
8165 if (User->getOperand(0) == PromOps[i] ||
8166 User->getOperand(1) == PromOps[i])
8172 // Replace all inputs with the extension operand.
8173 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8174 // Constants may have users outside the cluster of to-be-promoted nodes,
8175 // and so we need to replace those as we do the promotions.
8176 if (isa<ConstantSDNode>(Inputs[i]))
8179 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
8182 // Replace all operations (these are all the same, but have a different
8183 // (i1) return type). DAG.getNode will validate that the types of
8184 // a binary operator match, so go through the list in reverse so that
8185 // we've likely promoted both operands first. Any intermediate truncations or
8186 // extensions disappear.
8187 while (!PromOps.empty()) {
8188 SDValue PromOp = PromOps.back();
8191 if (PromOp.getOpcode() == ISD::TRUNCATE ||
8192 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
8193 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
8194 PromOp.getOpcode() == ISD::ANY_EXTEND) {
8195 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
8196 PromOp.getOperand(0).getValueType() != MVT::i1) {
8197 // The operand is not yet ready (see comment below).
8198 PromOps.insert(PromOps.begin(), PromOp);
8202 SDValue RepValue = PromOp.getOperand(0);
8203 if (isa<ConstantSDNode>(RepValue))
8204 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
8206 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
8211 switch (PromOp.getOpcode()) {
8212 default: C = 0; break;
8213 case ISD::SELECT: C = 1; break;
8214 case ISD::SELECT_CC: C = 2; break;
8217 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8218 PromOp.getOperand(C).getValueType() != MVT::i1) ||
8219 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8220 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
8221 // The to-be-promoted operands of this node have not yet been
8222 // promoted (this should be rare because we're going through the
8223 // list backward, but if one of the operands has several users in
8224 // this cluster of to-be-promoted nodes, it is possible).
8225 PromOps.insert(PromOps.begin(), PromOp);
8229 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8230 PromOp.getNode()->op_end());
8232 // If there are any constant inputs, make sure they're replaced now.
8233 for (unsigned i = 0; i < 2; ++i)
8234 if (isa<ConstantSDNode>(Ops[C+i]))
8235 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
8237 DAG.ReplaceAllUsesOfValueWith(PromOp,
8238 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
8241 // Now we're left with the initial truncation itself.
8242 if (N->getOpcode() == ISD::TRUNCATE)
8243 return N->getOperand(0);
8245 // Otherwise, this is a comparison. The operands to be compared have just
8246 // changed type (to i1), but everything else is the same.
8247 return SDValue(N, 0);
8250 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
8251 DAGCombinerInfo &DCI) const {
8252 SelectionDAG &DAG = DCI.DAG;
8255 // If we're tracking CR bits, we need to be careful that we don't have:
8256 // zext(binary-ops(trunc(x), trunc(y)))
8258 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
8259 // such that we're unnecessarily moving things into CR bits that can more
8260 // efficiently stay in GPRs. Note that if we're not certain that the high
8261 // bits are set as required by the final extension, we still may need to do
8262 // some masking to get the proper behavior.
8264 // This same functionality is important on PPC64 when dealing with
8265 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
8266 // the return values of functions. Because it is so similar, it is handled
8269 if (N->getValueType(0) != MVT::i32 &&
8270 N->getValueType(0) != MVT::i64)
8273 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
8274 Subtarget.useCRBits()) ||
8275 (N->getOperand(0).getValueType() == MVT::i32 &&
8276 Subtarget.isPPC64())))
8279 if (N->getOperand(0).getOpcode() != ISD::AND &&
8280 N->getOperand(0).getOpcode() != ISD::OR &&
8281 N->getOperand(0).getOpcode() != ISD::XOR &&
8282 N->getOperand(0).getOpcode() != ISD::SELECT &&
8283 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
8286 SmallVector<SDValue, 4> Inputs;
8287 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
8288 SmallPtrSet<SDNode *, 16> Visited;
8290 // Visit all inputs, collect all binary operations (and, or, xor and
8291 // select) that are all fed by truncations.
8292 while (!BinOps.empty()) {
8293 SDValue BinOp = BinOps.back();
8296 if (!Visited.insert(BinOp.getNode()).second)
8299 PromOps.push_back(BinOp);
8301 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
8302 // The condition of the select is not promoted.
8303 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
8305 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
8308 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
8309 isa<ConstantSDNode>(BinOp.getOperand(i))) {
8310 Inputs.push_back(BinOp.getOperand(i));
8311 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
8312 BinOp.getOperand(i).getOpcode() == ISD::OR ||
8313 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
8314 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
8315 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
8316 BinOps.push_back(BinOp.getOperand(i));
8318 // We have an input that is not a truncation or another binary
8319 // operation; we'll abort this transformation.
8325 // The operands of a select that must be truncated when the select is
8326 // promoted because the operand is actually part of the to-be-promoted set.
8327 DenseMap<SDNode *, EVT> SelectTruncOp[2];
8329 // Make sure that this is a self-contained cluster of operations (which
8330 // is not quite the same thing as saying that everything has only one
8332 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8333 if (isa<ConstantSDNode>(Inputs[i]))
8336 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
8337 UE = Inputs[i].getNode()->use_end();
8340 if (User != N && !Visited.count(User))
8343 // If we're going to promote the non-output-value operand(s) or SELECT or
8344 // SELECT_CC, record them for truncation.
8345 if (User->getOpcode() == ISD::SELECT) {
8346 if (User->getOperand(0) == Inputs[i])
8347 SelectTruncOp[0].insert(std::make_pair(User,
8348 User->getOperand(0).getValueType()));
8349 } else if (User->getOpcode() == ISD::SELECT_CC) {
8350 if (User->getOperand(0) == Inputs[i])
8351 SelectTruncOp[0].insert(std::make_pair(User,
8352 User->getOperand(0).getValueType()));
8353 if (User->getOperand(1) == Inputs[i])
8354 SelectTruncOp[1].insert(std::make_pair(User,
8355 User->getOperand(1).getValueType()));
8360 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
8361 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
8362 UE = PromOps[i].getNode()->use_end();
8365 if (User != N && !Visited.count(User))
8368 // If we're going to promote the non-output-value operand(s) or SELECT or
8369 // SELECT_CC, record them for truncation.
8370 if (User->getOpcode() == ISD::SELECT) {
8371 if (User->getOperand(0) == PromOps[i])
8372 SelectTruncOp[0].insert(std::make_pair(User,
8373 User->getOperand(0).getValueType()));
8374 } else if (User->getOpcode() == ISD::SELECT_CC) {
8375 if (User->getOperand(0) == PromOps[i])
8376 SelectTruncOp[0].insert(std::make_pair(User,
8377 User->getOperand(0).getValueType()));
8378 if (User->getOperand(1) == PromOps[i])
8379 SelectTruncOp[1].insert(std::make_pair(User,
8380 User->getOperand(1).getValueType()));
8385 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
8386 bool ReallyNeedsExt = false;
8387 if (N->getOpcode() != ISD::ANY_EXTEND) {
8388 // If all of the inputs are not already sign/zero extended, then
8389 // we'll still need to do that at the end.
8390 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8391 if (isa<ConstantSDNode>(Inputs[i]))
8395 Inputs[i].getOperand(0).getValueSizeInBits();
8396 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
8398 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
8399 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
8400 APInt::getHighBitsSet(OpBits,
8401 OpBits-PromBits))) ||
8402 (N->getOpcode() == ISD::SIGN_EXTEND &&
8403 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
8404 (OpBits-(PromBits-1)))) {
8405 ReallyNeedsExt = true;
8411 // Replace all inputs, either with the truncation operand, or a
8412 // truncation or extension to the final output type.
8413 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
8414 // Constant inputs need to be replaced with the to-be-promoted nodes that
8415 // use them because they might have users outside of the cluster of
8417 if (isa<ConstantSDNode>(Inputs[i]))
8420 SDValue InSrc = Inputs[i].getOperand(0);
8421 if (Inputs[i].getValueType() == N->getValueType(0))
8422 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
8423 else if (N->getOpcode() == ISD::SIGN_EXTEND)
8424 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8425 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
8426 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8427 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8428 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
8430 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
8431 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
8434 // Replace all operations (these are all the same, but have a different
8435 // (promoted) return type). DAG.getNode will validate that the types of
8436 // a binary operator match, so go through the list in reverse so that
8437 // we've likely promoted both operands first.
8438 while (!PromOps.empty()) {
8439 SDValue PromOp = PromOps.back();
8443 switch (PromOp.getOpcode()) {
8444 default: C = 0; break;
8445 case ISD::SELECT: C = 1; break;
8446 case ISD::SELECT_CC: C = 2; break;
8449 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
8450 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
8451 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
8452 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
8453 // The to-be-promoted operands of this node have not yet been
8454 // promoted (this should be rare because we're going through the
8455 // list backward, but if one of the operands has several users in
8456 // this cluster of to-be-promoted nodes, it is possible).
8457 PromOps.insert(PromOps.begin(), PromOp);
8461 // For SELECT and SELECT_CC nodes, we do a similar check for any
8462 // to-be-promoted comparison inputs.
8463 if (PromOp.getOpcode() == ISD::SELECT ||
8464 PromOp.getOpcode() == ISD::SELECT_CC) {
8465 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
8466 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
8467 (SelectTruncOp[1].count(PromOp.getNode()) &&
8468 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
8469 PromOps.insert(PromOps.begin(), PromOp);
8474 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
8475 PromOp.getNode()->op_end());
8477 // If this node has constant inputs, then they'll need to be promoted here.
8478 for (unsigned i = 0; i < 2; ++i) {
8479 if (!isa<ConstantSDNode>(Ops[C+i]))
8481 if (Ops[C+i].getValueType() == N->getValueType(0))
8484 if (N->getOpcode() == ISD::SIGN_EXTEND)
8485 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8486 else if (N->getOpcode() == ISD::ZERO_EXTEND)
8487 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8489 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
8492 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
8493 // truncate them again to the original value type.
8494 if (PromOp.getOpcode() == ISD::SELECT ||
8495 PromOp.getOpcode() == ISD::SELECT_CC) {
8496 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
8497 if (SI0 != SelectTruncOp[0].end())
8498 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
8499 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
8500 if (SI1 != SelectTruncOp[1].end())
8501 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
8504 DAG.ReplaceAllUsesOfValueWith(PromOp,
8505 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
8508 // Now we're left with the initial extension itself.
8509 if (!ReallyNeedsExt)
8510 return N->getOperand(0);
8512 // To zero extend, just mask off everything except for the first bit (in the
8514 if (N->getOpcode() == ISD::ZERO_EXTEND)
8515 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
8516 DAG.getConstant(APInt::getLowBitsSet(
8517 N->getValueSizeInBits(0), PromBits),
8518 N->getValueType(0)));
8520 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
8521 "Invalid extension type");
8522 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
8524 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
8525 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
8526 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
8527 N->getOperand(0), ShiftCst), ShiftCst);
8530 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
8531 DAGCombinerInfo &DCI) const {
8532 assert((N->getOpcode() == ISD::SINT_TO_FP ||
8533 N->getOpcode() == ISD::UINT_TO_FP) &&
8534 "Need an int -> FP conversion node here");
8536 if (!Subtarget.has64BitSupport())
8539 SelectionDAG &DAG = DCI.DAG;
8543 // Don't handle ppc_fp128 here or i1 conversions.
8544 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
8546 if (Op.getOperand(0).getValueType() == MVT::i1)
8549 // For i32 intermediate values, unfortunately, the conversion functions
8550 // leave the upper 32 bits of the value are undefined. Within the set of
8551 // scalar instructions, we have no method for zero- or sign-extending the
8552 // value. Thus, we cannot handle i32 intermediate values here.
8553 if (Op.getOperand(0).getValueType() == MVT::i32)
8556 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
8557 "UINT_TO_FP is supported only with FPCVT");
8559 // If we have FCFIDS, then use it when converting to single-precision.
8560 // Otherwise, convert to double-precision and then round.
8561 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8562 (Op.getOpcode() == ISD::UINT_TO_FP ?
8563 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
8564 (Op.getOpcode() == ISD::UINT_TO_FP ?
8565 PPCISD::FCFIDU : PPCISD::FCFID);
8566 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
8567 MVT::f32 : MVT::f64;
8569 // If we're converting from a float, to an int, and back to a float again,
8570 // then we don't need the store/load pair at all.
8571 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
8572 Subtarget.hasFPCVT()) ||
8573 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
8574 SDValue Src = Op.getOperand(0).getOperand(0);
8575 if (Src.getValueType() == MVT::f32) {
8576 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
8577 DCI.AddToWorklist(Src.getNode());
8581 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
8584 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
8585 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
8587 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
8588 FP = DAG.getNode(ISD::FP_ROUND, dl,
8589 MVT::f32, FP, DAG.getIntPtrConstant(0));
8590 DCI.AddToWorklist(FP.getNode());
8599 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
8600 // builtins) into loads with swaps.
8601 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
8602 DAGCombinerInfo &DCI) const {
8603 SelectionDAG &DAG = DCI.DAG;
8607 MachineMemOperand *MMO;
8609 switch (N->getOpcode()) {
8611 llvm_unreachable("Unexpected opcode for little endian VSX load");
8613 LoadSDNode *LD = cast<LoadSDNode>(N);
8614 Chain = LD->getChain();
8615 Base = LD->getBasePtr();
8616 MMO = LD->getMemOperand();
8617 // If the MMO suggests this isn't a load of a full vector, leave
8618 // things alone. For a built-in, we have to make the change for
8619 // correctness, so if there is a size problem that will be a bug.
8620 if (MMO->getSize() < 16)
8624 case ISD::INTRINSIC_W_CHAIN: {
8625 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8626 Chain = Intrin->getChain();
8627 Base = Intrin->getBasePtr();
8628 MMO = Intrin->getMemOperand();
8633 MVT VecTy = N->getValueType(0).getSimpleVT();
8634 SDValue LoadOps[] = { Chain, Base };
8635 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
8636 DAG.getVTList(VecTy, MVT::Other),
8637 LoadOps, VecTy, MMO);
8638 DCI.AddToWorklist(Load.getNode());
8639 Chain = Load.getValue(1);
8640 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8641 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
8642 DCI.AddToWorklist(Swap.getNode());
8646 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
8647 // builtins) into stores with swaps.
8648 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
8649 DAGCombinerInfo &DCI) const {
8650 SelectionDAG &DAG = DCI.DAG;
8655 MachineMemOperand *MMO;
8657 switch (N->getOpcode()) {
8659 llvm_unreachable("Unexpected opcode for little endian VSX store");
8661 StoreSDNode *ST = cast<StoreSDNode>(N);
8662 Chain = ST->getChain();
8663 Base = ST->getBasePtr();
8664 MMO = ST->getMemOperand();
8666 // If the MMO suggests this isn't a store of a full vector, leave
8667 // things alone. For a built-in, we have to make the change for
8668 // correctness, so if there is a size problem that will be a bug.
8669 if (MMO->getSize() < 16)
8673 case ISD::INTRINSIC_VOID: {
8674 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
8675 Chain = Intrin->getChain();
8676 // Intrin->getBasePtr() oddly does not get what we want.
8677 Base = Intrin->getOperand(3);
8678 MMO = Intrin->getMemOperand();
8684 SDValue Src = N->getOperand(SrcOpnd);
8685 MVT VecTy = Src.getValueType().getSimpleVT();
8686 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
8687 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
8688 DCI.AddToWorklist(Swap.getNode());
8689 Chain = Swap.getValue(1);
8690 SDValue StoreOps[] = { Chain, Swap, Base };
8691 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
8692 DAG.getVTList(MVT::Other),
8693 StoreOps, VecTy, MMO);
8694 DCI.AddToWorklist(Store.getNode());
8698 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
8699 DAGCombinerInfo &DCI) const {
8700 const TargetMachine &TM = getTargetMachine();
8701 SelectionDAG &DAG = DCI.DAG;
8703 switch (N->getOpcode()) {
8706 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8707 if (C->isNullValue()) // 0 << V -> 0.
8708 return N->getOperand(0);
8712 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8713 if (C->isNullValue()) // 0 >>u V -> 0.
8714 return N->getOperand(0);
8718 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
8719 if (C->isNullValue() || // 0 >>s V -> 0.
8720 C->isAllOnesValue()) // -1 >>s V -> -1.
8721 return N->getOperand(0);
8724 case ISD::SIGN_EXTEND:
8725 case ISD::ZERO_EXTEND:
8726 case ISD::ANY_EXTEND:
8727 return DAGCombineExtBoolTrunc(N, DCI);
8730 case ISD::SELECT_CC:
8731 return DAGCombineTruncBoolExt(N, DCI);
8732 case ISD::SINT_TO_FP:
8733 case ISD::UINT_TO_FP:
8734 return combineFPToIntToFP(N, DCI);
8736 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8737 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8738 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8739 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8740 N->getOperand(1).getValueType() == MVT::i32 &&
8741 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8742 SDValue Val = N->getOperand(1).getOperand(0);
8743 if (Val.getValueType() == MVT::f32) {
8744 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8745 DCI.AddToWorklist(Val.getNode());
8747 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8748 DCI.AddToWorklist(Val.getNode());
8751 N->getOperand(0), Val, N->getOperand(2),
8752 DAG.getValueType(N->getOperand(1).getValueType())
8755 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8756 DAG.getVTList(MVT::Other), Ops,
8757 cast<StoreSDNode>(N)->getMemoryVT(),
8758 cast<StoreSDNode>(N)->getMemOperand());
8759 DCI.AddToWorklist(Val.getNode());
8763 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8764 if (cast<StoreSDNode>(N)->isUnindexed() &&
8765 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8766 N->getOperand(1).getNode()->hasOneUse() &&
8767 (N->getOperand(1).getValueType() == MVT::i32 ||
8768 N->getOperand(1).getValueType() == MVT::i16 ||
8769 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8770 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8771 N->getOperand(1).getValueType() == MVT::i64))) {
8772 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8773 // Do an any-extend to 32-bits if this is a half-word input.
8774 if (BSwapOp.getValueType() == MVT::i16)
8775 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8778 N->getOperand(0), BSwapOp, N->getOperand(2),
8779 DAG.getValueType(N->getOperand(1).getValueType())
8782 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8783 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8784 cast<StoreSDNode>(N)->getMemOperand());
8787 // For little endian, VSX stores require generating xxswapd/lxvd2x.
8788 EVT VT = N->getOperand(1).getValueType();
8789 if (VT.isSimple()) {
8790 MVT StoreVT = VT.getSimpleVT();
8791 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8792 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8793 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
8794 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
8795 return expandVSXStoreForLE(N, DCI);
8800 LoadSDNode *LD = cast<LoadSDNode>(N);
8801 EVT VT = LD->getValueType(0);
8803 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8804 if (VT.isSimple()) {
8805 MVT LoadVT = VT.getSimpleVT();
8806 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8807 TM.getSubtarget<PPCSubtarget>().isLittleEndian() &&
8808 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
8809 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
8810 return expandVSXLoadForLE(N, DCI);
8813 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8814 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8815 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8816 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8817 // P8 and later hardware should just use LOAD.
8818 !TM.getSubtarget<PPCSubtarget>().hasP8Vector() &&
8819 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8820 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8821 LD->getAlignment() < ABIAlignment) {
8822 // This is a type-legal unaligned Altivec load.
8823 SDValue Chain = LD->getChain();
8824 SDValue Ptr = LD->getBasePtr();
8825 bool isLittleEndian = Subtarget.isLittleEndian();
8827 // This implements the loading of unaligned vectors as described in
8828 // the venerable Apple Velocity Engine overview. Specifically:
8829 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8830 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8832 // The general idea is to expand a sequence of one or more unaligned
8833 // loads into an alignment-based permutation-control instruction (lvsl
8834 // or lvsr), a series of regular vector loads (which always truncate
8835 // their input address to an aligned address), and a series of
8836 // permutations. The results of these permutations are the requested
8837 // loaded values. The trick is that the last "extra" load is not taken
8838 // from the address you might suspect (sizeof(vector) bytes after the
8839 // last requested load), but rather sizeof(vector) - 1 bytes after the
8840 // last requested vector. The point of this is to avoid a page fault if
8841 // the base address happened to be aligned. This works because if the
8842 // base address is aligned, then adding less than a full vector length
8843 // will cause the last vector in the sequence to be (re)loaded.
8844 // Otherwise, the next vector will be fetched as you might suspect was
8847 // We might be able to reuse the permutation generation from
8848 // a different base address offset from this one by an aligned amount.
8849 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8850 // optimization later.
8851 Intrinsic::ID Intr = (isLittleEndian ?
8852 Intrinsic::ppc_altivec_lvsr :
8853 Intrinsic::ppc_altivec_lvsl);
8854 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8856 // Create the new MMO for the new base load. It is like the original MMO,
8857 // but represents an area in memory almost twice the vector size centered
8858 // on the original address. If the address is unaligned, we might start
8859 // reading up to (sizeof(vector)-1) bytes below the address of the
8860 // original unaligned load.
8861 MachineFunction &MF = DAG.getMachineFunction();
8862 MachineMemOperand *BaseMMO =
8863 MF.getMachineMemOperand(LD->getMemOperand(),
8864 -LD->getMemoryVT().getStoreSize()+1,
8865 2*LD->getMemoryVT().getStoreSize()-1);
8867 // Create the new base load.
8868 SDValue LDXIntID = DAG.getTargetConstant(Intrinsic::ppc_altivec_lvx,
8870 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
8872 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8873 DAG.getVTList(MVT::v4i32, MVT::Other),
8874 BaseLoadOps, MVT::v4i32, BaseMMO);
8876 // Note that the value of IncOffset (which is provided to the next
8877 // load's pointer info offset value, and thus used to calculate the
8878 // alignment), and the value of IncValue (which is actually used to
8879 // increment the pointer value) are different! This is because we
8880 // require the next load to appear to be aligned, even though it
8881 // is actually offset from the base pointer by a lesser amount.
8882 int IncOffset = VT.getSizeInBits() / 8;
8883 int IncValue = IncOffset;
8885 // Walk (both up and down) the chain looking for another load at the real
8886 // (aligned) offset (the alignment of the other load does not matter in
8887 // this case). If found, then do not use the offset reduction trick, as
8888 // that will prevent the loads from being later combined (as they would
8889 // otherwise be duplicates).
8890 if (!findConsecutiveLoad(LD, DAG))
8893 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8894 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8896 MachineMemOperand *ExtraMMO =
8897 MF.getMachineMemOperand(LD->getMemOperand(),
8898 1, 2*LD->getMemoryVT().getStoreSize()-1);
8899 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
8901 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
8902 DAG.getVTList(MVT::v4i32, MVT::Other),
8903 ExtraLoadOps, MVT::v4i32, ExtraMMO);
8905 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8906 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8908 // Because vperm has a big-endian bias, we must reverse the order
8909 // of the input vectors and complement the permute control vector
8910 // when generating little endian code. We have already handled the
8911 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8912 // and ExtraLoad here.
8915 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8916 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8918 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8919 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8921 if (VT != MVT::v4i32)
8922 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8924 // The output of the permutation is our loaded result, the TokenFactor is
8926 DCI.CombineTo(N, Perm, TF);
8927 return SDValue(N, 0);
8931 case ISD::INTRINSIC_WO_CHAIN: {
8932 bool isLittleEndian = Subtarget.isLittleEndian();
8933 Intrinsic::ID Intr = (isLittleEndian ?
8934 Intrinsic::ppc_altivec_lvsr :
8935 Intrinsic::ppc_altivec_lvsl);
8936 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8937 N->getOperand(1)->getOpcode() == ISD::ADD) {
8938 SDValue Add = N->getOperand(1);
8940 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8941 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8942 Add.getValueType().getScalarType().getSizeInBits()))) {
8943 SDNode *BasePtr = Add->getOperand(0).getNode();
8944 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8945 UE = BasePtr->use_end(); UI != UE; ++UI) {
8946 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8947 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8949 // We've found another LVSL/LVSR, and this address is an aligned
8950 // multiple of that one. The results will be the same, so use the
8951 // one we've just found instead.
8953 return SDValue(*UI, 0);
8961 case ISD::INTRINSIC_W_CHAIN: {
8962 // For little endian, VSX loads require generating lxvd2x/xxswapd.
8963 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8964 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8965 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8968 case Intrinsic::ppc_vsx_lxvw4x:
8969 case Intrinsic::ppc_vsx_lxvd2x:
8970 return expandVSXLoadForLE(N, DCI);
8975 case ISD::INTRINSIC_VOID: {
8976 // For little endian, VSX stores require generating xxswapd/stxvd2x.
8977 if (TM.getSubtarget<PPCSubtarget>().hasVSX() &&
8978 TM.getSubtarget<PPCSubtarget>().isLittleEndian()) {
8979 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
8982 case Intrinsic::ppc_vsx_stxvw4x:
8983 case Intrinsic::ppc_vsx_stxvd2x:
8984 return expandVSXStoreForLE(N, DCI);
8990 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8991 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8992 N->getOperand(0).hasOneUse() &&
8993 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8994 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8995 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8996 N->getValueType(0) == MVT::i64))) {
8997 SDValue Load = N->getOperand(0);
8998 LoadSDNode *LD = cast<LoadSDNode>(Load);
8999 // Create the byte-swapping load.
9001 LD->getChain(), // Chain
9002 LD->getBasePtr(), // Ptr
9003 DAG.getValueType(N->getValueType(0)) // VT
9006 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
9007 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
9008 MVT::i64 : MVT::i32, MVT::Other),
9009 Ops, LD->getMemoryVT(), LD->getMemOperand());
9011 // If this is an i16 load, insert the truncate.
9012 SDValue ResVal = BSLoad;
9013 if (N->getValueType(0) == MVT::i16)
9014 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
9016 // First, combine the bswap away. This makes the value produced by the
9018 DCI.CombineTo(N, ResVal);
9020 // Next, combine the load away, we give it a bogus result value but a real
9021 // chain result. The result value is dead because the bswap is dead.
9022 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
9024 // Return N so it doesn't get rechecked!
9025 return SDValue(N, 0);
9029 case PPCISD::VCMP: {
9030 // If a VCMPo node already exists with exactly the same operands as this
9031 // node, use its result instead of this node (VCMPo computes both a CR6 and
9032 // a normal output).
9034 if (!N->getOperand(0).hasOneUse() &&
9035 !N->getOperand(1).hasOneUse() &&
9036 !N->getOperand(2).hasOneUse()) {
9038 // Scan all of the users of the LHS, looking for VCMPo's that match.
9039 SDNode *VCMPoNode = nullptr;
9041 SDNode *LHSN = N->getOperand(0).getNode();
9042 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
9044 if (UI->getOpcode() == PPCISD::VCMPo &&
9045 UI->getOperand(1) == N->getOperand(1) &&
9046 UI->getOperand(2) == N->getOperand(2) &&
9047 UI->getOperand(0) == N->getOperand(0)) {
9052 // If there is no VCMPo node, or if the flag value has a single use, don't
9054 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
9057 // Look at the (necessarily single) use of the flag value. If it has a
9058 // chain, this transformation is more complex. Note that multiple things
9059 // could use the value result, which we should ignore.
9060 SDNode *FlagUser = nullptr;
9061 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
9062 FlagUser == nullptr; ++UI) {
9063 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
9065 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
9066 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
9073 // If the user is a MFOCRF instruction, we know this is safe.
9074 // Otherwise we give up for right now.
9075 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
9076 return SDValue(VCMPoNode, 0);
9081 SDValue Cond = N->getOperand(1);
9082 SDValue Target = N->getOperand(2);
9084 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9085 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
9086 Intrinsic::ppc_is_decremented_ctr_nonzero) {
9088 // We now need to make the intrinsic dead (it cannot be instruction
9090 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
9091 assert(Cond.getNode()->hasOneUse() &&
9092 "Counter decrement has more than one use");
9094 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
9095 N->getOperand(0), Target);
9100 // If this is a branch on an altivec predicate comparison, lower this so
9101 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
9102 // lowering is done pre-legalize, because the legalizer lowers the predicate
9103 // compare down to code that is difficult to reassemble.
9104 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
9105 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
9107 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
9108 // value. If so, pass-through the AND to get to the intrinsic.
9109 if (LHS.getOpcode() == ISD::AND &&
9110 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9111 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
9112 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9113 isa<ConstantSDNode>(LHS.getOperand(1)) &&
9114 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
9116 LHS = LHS.getOperand(0);
9118 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
9119 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
9120 Intrinsic::ppc_is_decremented_ctr_nonzero &&
9121 isa<ConstantSDNode>(RHS)) {
9122 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
9123 "Counter decrement comparison is not EQ or NE");
9125 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9126 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
9127 (CC == ISD::SETNE && !Val);
9129 // We now need to make the intrinsic dead (it cannot be instruction
9131 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
9132 assert(LHS.getNode()->hasOneUse() &&
9133 "Counter decrement has more than one use");
9135 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
9136 N->getOperand(0), N->getOperand(4));
9142 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
9143 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
9144 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
9145 assert(isDot && "Can't compare against a vector result!");
9147 // If this is a comparison against something other than 0/1, then we know
9148 // that the condition is never/always true.
9149 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
9150 if (Val != 0 && Val != 1) {
9151 if (CC == ISD::SETEQ) // Cond never true, remove branch.
9152 return N->getOperand(0);
9153 // Always !=, turn it into an unconditional branch.
9154 return DAG.getNode(ISD::BR, dl, MVT::Other,
9155 N->getOperand(0), N->getOperand(4));
9158 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
9160 // Create the PPCISD altivec 'dot' comparison node.
9162 LHS.getOperand(2), // LHS of compare
9163 LHS.getOperand(3), // RHS of compare
9164 DAG.getConstant(CompareOpc, MVT::i32)
9166 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
9167 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
9169 // Unpack the result based on how the target uses it.
9170 PPC::Predicate CompOpc;
9171 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
9172 default: // Can't happen, don't crash on invalid number though.
9173 case 0: // Branch on the value of the EQ bit of CR6.
9174 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
9176 case 1: // Branch on the inverted value of the EQ bit of CR6.
9177 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
9179 case 2: // Branch on the value of the LT bit of CR6.
9180 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
9182 case 3: // Branch on the inverted value of the LT bit of CR6.
9183 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
9187 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
9188 DAG.getConstant(CompOpc, MVT::i32),
9189 DAG.getRegister(PPC::CR6, MVT::i32),
9190 N->getOperand(4), CompNode.getValue(1));
9200 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
9202 std::vector<SDNode *> *Created) const {
9203 // fold (sdiv X, pow2)
9204 EVT VT = N->getValueType(0);
9205 if (VT == MVT::i64 && !Subtarget.isPPC64())
9207 if ((VT != MVT::i32 && VT != MVT::i64) ||
9208 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
9212 SDValue N0 = N->getOperand(0);
9214 bool IsNegPow2 = (-Divisor).isPowerOf2();
9215 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
9216 SDValue ShiftAmt = DAG.getConstant(Lg2, VT);
9218 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
9220 Created->push_back(Op.getNode());
9223 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT), Op);
9225 Created->push_back(Op.getNode());
9231 //===----------------------------------------------------------------------===//
9232 // Inline Assembly Support
9233 //===----------------------------------------------------------------------===//
9235 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
9238 const SelectionDAG &DAG,
9239 unsigned Depth) const {
9240 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
9241 switch (Op.getOpcode()) {
9243 case PPCISD::LBRX: {
9244 // lhbrx is known to have the top bits cleared out.
9245 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
9246 KnownZero = 0xFFFF0000;
9249 case ISD::INTRINSIC_WO_CHAIN: {
9250 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
9252 case Intrinsic::ppc_altivec_vcmpbfp_p:
9253 case Intrinsic::ppc_altivec_vcmpeqfp_p:
9254 case Intrinsic::ppc_altivec_vcmpequb_p:
9255 case Intrinsic::ppc_altivec_vcmpequh_p:
9256 case Intrinsic::ppc_altivec_vcmpequw_p:
9257 case Intrinsic::ppc_altivec_vcmpgefp_p:
9258 case Intrinsic::ppc_altivec_vcmpgtfp_p:
9259 case Intrinsic::ppc_altivec_vcmpgtsb_p:
9260 case Intrinsic::ppc_altivec_vcmpgtsh_p:
9261 case Intrinsic::ppc_altivec_vcmpgtsw_p:
9262 case Intrinsic::ppc_altivec_vcmpgtub_p:
9263 case Intrinsic::ppc_altivec_vcmpgtuh_p:
9264 case Intrinsic::ppc_altivec_vcmpgtuw_p:
9265 KnownZero = ~1U; // All bits but the low one are known to be zero.
9272 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
9273 switch (Subtarget.getDarwinDirective()) {
9278 case PPC::DIR_PWR5X:
9280 case PPC::DIR_PWR6X:
9282 case PPC::DIR_PWR8: {
9286 const PPCInstrInfo *TII =
9287 static_cast<const PPCInstrInfo *>(getTargetMachine().getSubtargetImpl()->
9290 // For small loops (between 5 and 8 instructions), align to a 32-byte
9291 // boundary so that the entire loop fits in one instruction-cache line.
9292 uint64_t LoopSize = 0;
9293 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
9294 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
9295 LoopSize += TII->GetInstSizeInBytes(J);
9297 if (LoopSize > 16 && LoopSize <= 32)
9304 return TargetLowering::getPrefLoopAlignment(ML);
9307 /// getConstraintType - Given a constraint, return the type of
9308 /// constraint it is for this target.
9309 PPCTargetLowering::ConstraintType
9310 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
9311 if (Constraint.size() == 1) {
9312 switch (Constraint[0]) {
9319 return C_RegisterClass;
9321 // FIXME: While Z does indicate a memory constraint, it specifically
9322 // indicates an r+r address (used in conjunction with the 'y' modifier
9323 // in the replacement string). Currently, we're forcing the base
9324 // register to be r0 in the asm printer (which is interpreted as zero)
9325 // and forming the complete address in the second register. This is
9329 } else if (Constraint == "wc") { // individual CR bits.
9330 return C_RegisterClass;
9331 } else if (Constraint == "wa" || Constraint == "wd" ||
9332 Constraint == "wf" || Constraint == "ws") {
9333 return C_RegisterClass; // VSX registers.
9335 return TargetLowering::getConstraintType(Constraint);
9338 /// Examine constraint type and operand type and determine a weight value.
9339 /// This object must already have been set up with the operand type
9340 /// and the current alternative constraint selected.
9341 TargetLowering::ConstraintWeight
9342 PPCTargetLowering::getSingleConstraintMatchWeight(
9343 AsmOperandInfo &info, const char *constraint) const {
9344 ConstraintWeight weight = CW_Invalid;
9345 Value *CallOperandVal = info.CallOperandVal;
9346 // If we don't have a value, we can't do a match,
9347 // but allow it at the lowest weight.
9348 if (!CallOperandVal)
9350 Type *type = CallOperandVal->getType();
9352 // Look at the constraint type.
9353 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
9354 return CW_Register; // an individual CR bit.
9355 else if ((StringRef(constraint) == "wa" ||
9356 StringRef(constraint) == "wd" ||
9357 StringRef(constraint) == "wf") &&
9360 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
9363 switch (*constraint) {
9365 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
9368 if (type->isIntegerTy())
9369 weight = CW_Register;
9372 if (type->isFloatTy())
9373 weight = CW_Register;
9376 if (type->isDoubleTy())
9377 weight = CW_Register;
9380 if (type->isVectorTy())
9381 weight = CW_Register;
9384 weight = CW_Register;
9393 std::pair<unsigned, const TargetRegisterClass*>
9394 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
9396 if (Constraint.size() == 1) {
9397 // GCC RS6000 Constraint Letters
9398 switch (Constraint[0]) {
9400 if (VT == MVT::i64 && Subtarget.isPPC64())
9401 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
9402 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
9404 if (VT == MVT::i64 && Subtarget.isPPC64())
9405 return std::make_pair(0U, &PPC::G8RCRegClass);
9406 return std::make_pair(0U, &PPC::GPRCRegClass);
9408 if (VT == MVT::f32 || VT == MVT::i32)
9409 return std::make_pair(0U, &PPC::F4RCRegClass);
9410 if (VT == MVT::f64 || VT == MVT::i64)
9411 return std::make_pair(0U, &PPC::F8RCRegClass);
9414 return std::make_pair(0U, &PPC::VRRCRegClass);
9416 return std::make_pair(0U, &PPC::CRRCRegClass);
9418 } else if (Constraint == "wc") { // an individual CR bit.
9419 return std::make_pair(0U, &PPC::CRBITRCRegClass);
9420 } else if (Constraint == "wa" || Constraint == "wd" ||
9421 Constraint == "wf") {
9422 return std::make_pair(0U, &PPC::VSRCRegClass);
9423 } else if (Constraint == "ws") {
9424 return std::make_pair(0U, &PPC::VSFRCRegClass);
9427 std::pair<unsigned, const TargetRegisterClass*> R =
9428 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
9430 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
9431 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
9432 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
9434 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
9435 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
9436 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
9437 PPC::GPRCRegClass.contains(R.first)) {
9438 const TargetRegisterInfo *TRI =
9439 getTargetMachine().getSubtargetImpl()->getRegisterInfo();
9440 return std::make_pair(TRI->getMatchingSuperReg(R.first,
9441 PPC::sub_32, &PPC::G8RCRegClass),
9442 &PPC::G8RCRegClass);
9445 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
9446 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
9448 R.second = &PPC::CRRCRegClass;
9455 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
9456 /// vector. If it is invalid, don't add anything to Ops.
9457 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
9458 std::string &Constraint,
9459 std::vector<SDValue>&Ops,
9460 SelectionDAG &DAG) const {
9463 // Only support length 1 constraints.
9464 if (Constraint.length() > 1) return;
9466 char Letter = Constraint[0];
9477 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
9478 if (!CST) return; // Must be an immediate to match.
9479 int64_t Value = CST->getSExtValue();
9480 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9481 // numbers are printed as such.
9483 default: llvm_unreachable("Unknown constraint letter!");
9484 case 'I': // "I" is a signed 16-bit constant.
9485 if (isInt<16>(Value))
9486 Result = DAG.getTargetConstant(Value, TCVT);
9488 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9489 if (isShiftedUInt<16, 16>(Value))
9490 Result = DAG.getTargetConstant(Value, TCVT);
9492 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9493 if (isShiftedInt<16, 16>(Value))
9494 Result = DAG.getTargetConstant(Value, TCVT);
9496 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9497 if (isUInt<16>(Value))
9498 Result = DAG.getTargetConstant(Value, TCVT);
9500 case 'M': // "M" is a constant that is greater than 31.
9502 Result = DAG.getTargetConstant(Value, TCVT);
9504 case 'N': // "N" is a positive constant that is an exact power of two.
9505 if (Value > 0 && isPowerOf2_64(Value))
9506 Result = DAG.getTargetConstant(Value, TCVT);
9508 case 'O': // "O" is the constant zero.
9510 Result = DAG.getTargetConstant(Value, TCVT);
9512 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9513 if (isInt<16>(-Value))
9514 Result = DAG.getTargetConstant(Value, TCVT);
9521 if (Result.getNode()) {
9522 Ops.push_back(Result);
9526 // Handle standard constraint letters.
9527 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
9530 // isLegalAddressingMode - Return true if the addressing mode represented
9531 // by AM is legal for this target, for a load/store of the specified type.
9532 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
9534 // FIXME: PPC does not allow r+i addressing modes for vectors!
9536 // PPC allows a sign-extended 16-bit immediate field.
9537 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
9540 // No global is ever allowed as a base.
9544 // PPC only support r+r,
9546 case 0: // "r+i" or just "i", depending on HasBaseReg.
9549 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
9551 // Otherwise we have r+r or r+i.
9554 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
9556 // Allow 2*r as r+r.
9559 // No other scales are supported.
9566 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
9567 SelectionDAG &DAG) const {
9568 MachineFunction &MF = DAG.getMachineFunction();
9569 MachineFrameInfo *MFI = MF.getFrameInfo();
9570 MFI->setReturnAddressIsTaken(true);
9572 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
9576 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9578 // Make sure the function does not optimize away the store of the RA to
9580 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
9581 FuncInfo->setLRStoreRequired();
9582 bool isPPC64 = Subtarget.isPPC64();
9583 bool isDarwinABI = Subtarget.isDarwinABI();
9586 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
9589 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
9590 isPPC64? MVT::i64 : MVT::i32);
9591 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9592 DAG.getNode(ISD::ADD, dl, getPointerTy(),
9594 MachinePointerInfo(), false, false, false, 0);
9597 // Just load the return address off the stack.
9598 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
9599 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
9600 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
9603 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
9604 SelectionDAG &DAG) const {
9606 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
9608 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
9609 bool isPPC64 = PtrVT == MVT::i64;
9611 MachineFunction &MF = DAG.getMachineFunction();
9612 MachineFrameInfo *MFI = MF.getFrameInfo();
9613 MFI->setFrameAddressIsTaken(true);
9615 // Naked functions never have a frame pointer, and so we use r1. For all
9616 // other functions, this decision must be delayed until during PEI.
9618 if (MF.getFunction()->getAttributes().hasAttribute(
9619 AttributeSet::FunctionIndex, Attribute::Naked))
9620 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
9622 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
9624 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
9627 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
9628 FrameAddr, MachinePointerInfo(), false, false,
9633 // FIXME? Maybe this could be a TableGen attribute on some registers and
9634 // this table could be generated automatically from RegInfo.
9635 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
9637 bool isPPC64 = Subtarget.isPPC64();
9638 bool isDarwinABI = Subtarget.isDarwinABI();
9640 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
9641 (!isPPC64 && VT != MVT::i32))
9642 report_fatal_error("Invalid register global variable type");
9644 bool is64Bit = isPPC64 && VT == MVT::i64;
9645 unsigned Reg = StringSwitch<unsigned>(RegName)
9646 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
9647 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
9648 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
9649 (is64Bit ? PPC::X13 : PPC::R13))
9654 report_fatal_error("Invalid register name global variable");
9658 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
9659 // The PowerPC target isn't yet aware of offsets.
9663 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
9665 unsigned Intrinsic) const {
9667 switch (Intrinsic) {
9668 case Intrinsic::ppc_altivec_lvx:
9669 case Intrinsic::ppc_altivec_lvxl:
9670 case Intrinsic::ppc_altivec_lvebx:
9671 case Intrinsic::ppc_altivec_lvehx:
9672 case Intrinsic::ppc_altivec_lvewx:
9673 case Intrinsic::ppc_vsx_lxvd2x:
9674 case Intrinsic::ppc_vsx_lxvw4x: {
9676 switch (Intrinsic) {
9677 case Intrinsic::ppc_altivec_lvebx:
9680 case Intrinsic::ppc_altivec_lvehx:
9683 case Intrinsic::ppc_altivec_lvewx:
9686 case Intrinsic::ppc_vsx_lxvd2x:
9694 Info.opc = ISD::INTRINSIC_W_CHAIN;
9696 Info.ptrVal = I.getArgOperand(0);
9697 Info.offset = -VT.getStoreSize()+1;
9698 Info.size = 2*VT.getStoreSize()-1;
9701 Info.readMem = true;
9702 Info.writeMem = false;
9705 case Intrinsic::ppc_altivec_stvx:
9706 case Intrinsic::ppc_altivec_stvxl:
9707 case Intrinsic::ppc_altivec_stvebx:
9708 case Intrinsic::ppc_altivec_stvehx:
9709 case Intrinsic::ppc_altivec_stvewx:
9710 case Intrinsic::ppc_vsx_stxvd2x:
9711 case Intrinsic::ppc_vsx_stxvw4x: {
9713 switch (Intrinsic) {
9714 case Intrinsic::ppc_altivec_stvebx:
9717 case Intrinsic::ppc_altivec_stvehx:
9720 case Intrinsic::ppc_altivec_stvewx:
9723 case Intrinsic::ppc_vsx_stxvd2x:
9731 Info.opc = ISD::INTRINSIC_VOID;
9733 Info.ptrVal = I.getArgOperand(1);
9734 Info.offset = -VT.getStoreSize()+1;
9735 Info.size = 2*VT.getStoreSize()-1;
9738 Info.readMem = false;
9739 Info.writeMem = true;
9749 /// getOptimalMemOpType - Returns the target specific optimal type for load
9750 /// and store operations as a result of memset, memcpy, and memmove
9751 /// lowering. If DstAlign is zero that means it's safe to destination
9752 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
9753 /// means there isn't a need to check it against alignment requirement,
9754 /// probably because the source does not need to be loaded. If 'IsMemset' is
9755 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
9756 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
9757 /// source is constant so it does not need to be loaded.
9758 /// It returns EVT::Other if the type should be determined using generic
9759 /// target-independent logic.
9760 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
9761 unsigned DstAlign, unsigned SrcAlign,
9762 bool IsMemset, bool ZeroMemset,
9764 MachineFunction &MF) const {
9765 if (Subtarget.isPPC64()) {
9772 /// \brief Returns true if it is beneficial to convert a load of a constant
9773 /// to just the constant itself.
9774 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
9776 assert(Ty->isIntegerTy());
9778 unsigned BitSize = Ty->getPrimitiveSizeInBits();
9779 if (BitSize == 0 || BitSize > 64)
9784 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
9785 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
9787 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
9788 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
9789 return NumBits1 == 64 && NumBits2 == 32;
9792 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
9793 if (!VT1.isInteger() || !VT2.isInteger())
9795 unsigned NumBits1 = VT1.getSizeInBits();
9796 unsigned NumBits2 = VT2.getSizeInBits();
9797 return NumBits1 == 64 && NumBits2 == 32;
9800 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
9801 // Generally speaking, zexts are not free, but they are free when they can be
9802 // folded with other operations.
9803 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
9804 EVT MemVT = LD->getMemoryVT();
9805 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
9806 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
9807 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
9808 LD->getExtensionType() == ISD::ZEXTLOAD))
9812 // FIXME: Add other cases...
9813 // - 32-bit shifts with a zext to i64
9814 // - zext after ctlz, bswap, etc.
9815 // - zext after and by a constant mask
9817 return TargetLowering::isZExtFree(Val, VT2);
9820 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
9821 return isInt<16>(Imm) || isUInt<16>(Imm);
9824 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
9825 return isInt<16>(Imm) || isUInt<16>(Imm);
9828 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
9832 if (DisablePPCUnaligned)
9835 // PowerPC supports unaligned memory access for simple non-vector types.
9836 // Although accessing unaligned addresses is not as efficient as accessing
9837 // aligned addresses, it is generally more efficient than manual expansion,
9838 // and generally only traps for software emulation when crossing page
9844 if (VT.getSimpleVT().isVector()) {
9845 if (Subtarget.hasVSX()) {
9846 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
9847 VT != MVT::v4f32 && VT != MVT::v4i32)
9854 if (VT == MVT::ppcf128)
9863 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
9864 VT = VT.getScalarType();
9869 switch (VT.getSimpleVT().SimpleTy) {
9881 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9882 EVT VT , unsigned DefinedValues) const {
9883 if (VT == MVT::v2i64)
9886 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9889 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9890 if (DisableILPPref || Subtarget.enableMachineScheduler())
9891 return TargetLowering::getSchedulingPreference(N);
9896 // Create a fast isel object.
9898 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9899 const TargetLibraryInfo *LibInfo) const {
9900 return PPC::createFastISel(FuncInfo, LibInfo);