1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
777 case PPCISD::LOAD: return "PPCISD::LOAD";
778 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
779 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
780 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
781 case PPCISD::SRL: return "PPCISD::SRL";
782 case PPCISD::SRA: return "PPCISD::SRA";
783 case PPCISD::SHL: return "PPCISD::SHL";
784 case PPCISD::CALL: return "PPCISD::CALL";
785 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
786 case PPCISD::MTCTR: return "PPCISD::MTCTR";
787 case PPCISD::BCTRL: return "PPCISD::BCTRL";
788 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
789 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
790 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
791 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
792 case PPCISD::VCMP: return "PPCISD::VCMP";
793 case PPCISD::VCMPo: return "PPCISD::VCMPo";
794 case PPCISD::LBRX: return "PPCISD::LBRX";
795 case PPCISD::STBRX: return "PPCISD::STBRX";
796 case PPCISD::LARX: return "PPCISD::LARX";
797 case PPCISD::STCX: return "PPCISD::STCX";
798 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
799 case PPCISD::BDNZ: return "PPCISD::BDNZ";
800 case PPCISD::BDZ: return "PPCISD::BDZ";
801 case PPCISD::MFFS: return "PPCISD::MFFS";
802 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
803 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
804 case PPCISD::CR6SET: return "PPCISD::CR6SET";
805 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
806 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
807 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
808 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
809 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
810 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
811 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
812 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
813 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
814 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
815 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
816 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
817 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
818 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
819 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
820 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
821 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
822 case PPCISD::SC: return "PPCISD::SC";
826 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
828 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
829 return VT.changeVectorElementTypeToInteger();
832 //===----------------------------------------------------------------------===//
833 // Node matching predicates, for use by the tblgen matching code.
834 //===----------------------------------------------------------------------===//
836 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
837 static bool isFloatingPointZero(SDValue Op) {
838 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
839 return CFP->getValueAPF().isZero();
840 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
841 // Maybe this has already been legalized into the constant pool?
842 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
843 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
844 return CFP->getValueAPF().isZero();
849 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
850 /// true if Op is undef or if it matches the specified value.
851 static bool isConstantOrUndef(int Op, int Val) {
852 return Op < 0 || Op == Val;
855 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
856 /// VPKUHUM instruction.
857 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
859 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
861 for (unsigned i = 0; i != 16; ++i)
862 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
865 for (unsigned i = 0; i != 8; ++i)
866 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
867 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
873 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
874 /// VPKUWUM instruction.
875 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
878 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
886 for (unsigned i = 0; i != 16; i += 2)
887 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
888 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
891 for (unsigned i = 0; i != 8; i += 2)
892 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
893 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
894 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
895 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
901 /// isVMerge - Common function, used to match vmrg* shuffles.
903 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
904 unsigned LHSStart, unsigned RHSStart) {
905 if (N->getValueType(0) != MVT::v16i8)
907 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
908 "Unsupported merge size!");
910 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
911 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
912 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
913 LHSStart+j+i*UnitSize) ||
914 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
915 RHSStart+j+i*UnitSize))
921 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
922 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
923 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
924 bool isUnary, SelectionDAG &DAG) {
925 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
927 return isVMerge(N, UnitSize, 0, 16);
928 return isVMerge(N, UnitSize, 0, 0);
931 return isVMerge(N, UnitSize, 8, 24);
932 return isVMerge(N, UnitSize, 8, 8);
936 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
937 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
938 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
939 bool isUnary, SelectionDAG &DAG) {
940 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
942 return isVMerge(N, UnitSize, 8, 24);
943 return isVMerge(N, UnitSize, 8, 8);
946 return isVMerge(N, UnitSize, 0, 16);
947 return isVMerge(N, UnitSize, 0, 0);
952 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
953 /// amount, otherwise return -1.
954 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
955 if (N->getValueType(0) != MVT::v16i8)
958 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
960 // Find the first non-undef value in the shuffle mask.
962 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
965 if (i == 16) return -1; // all undef.
967 // Otherwise, check to see if the rest of the elements are consecutively
968 // numbered from this value.
969 unsigned ShiftAmt = SVOp->getMaskElt(i);
970 if (ShiftAmt < i) return -1;
972 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
977 // Check the rest of the elements to see if they are consecutive.
978 for (++i; i != 16; ++i)
979 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
982 // Check the rest of the elements to see if they are consecutive.
983 for (++i; i != 16; ++i)
984 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
988 } else { // Big Endian
993 // Check the rest of the elements to see if they are consecutive.
994 for (++i; i != 16; ++i)
995 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
998 // Check the rest of the elements to see if they are consecutive.
999 for (++i; i != 16; ++i)
1000 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1007 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1008 /// specifies a splat of a single element that is suitable for input to
1009 /// VSPLTB/VSPLTH/VSPLTW.
1010 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1011 assert(N->getValueType(0) == MVT::v16i8 &&
1012 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1014 // This is a splat operation if each element of the permute is the same, and
1015 // if the value doesn't reference the second vector.
1016 unsigned ElementBase = N->getMaskElt(0);
1018 // FIXME: Handle UNDEF elements too!
1019 if (ElementBase >= 16)
1022 // Check that the indices are consecutive, in the case of a multi-byte element
1023 // splatted with a v16i8 mask.
1024 for (unsigned i = 1; i != EltSize; ++i)
1025 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1028 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1029 if (N->getMaskElt(i) < 0) continue;
1030 for (unsigned j = 0; j != EltSize; ++j)
1031 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1037 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1039 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1040 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1042 APInt APVal, APUndef;
1046 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1047 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1048 return CFP->getValueAPF().isNegZero();
1053 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1054 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1055 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1056 SelectionDAG &DAG) {
1057 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1058 assert(isSplatShuffleMask(SVOp, EltSize));
1059 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1060 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1062 return SVOp->getMaskElt(0) / EltSize;
1065 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1066 /// by using a vspltis[bhw] instruction of the specified element size, return
1067 /// the constant being splatted. The ByteSize field indicates the number of
1068 /// bytes of each element [124] -> [bhw].
1069 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1070 SDValue OpVal(nullptr, 0);
1072 // If ByteSize of the splat is bigger than the element size of the
1073 // build_vector, then we have a case where we are checking for a splat where
1074 // multiple elements of the buildvector are folded together into a single
1075 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1076 unsigned EltSize = 16/N->getNumOperands();
1077 if (EltSize < ByteSize) {
1078 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1079 SDValue UniquedVals[4];
1080 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1082 // See if all of the elements in the buildvector agree across.
1083 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1084 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1085 // If the element isn't a constant, bail fully out.
1086 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1089 if (!UniquedVals[i&(Multiple-1)].getNode())
1090 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1091 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1092 return SDValue(); // no match.
1095 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1096 // either constant or undef values that are identical for each chunk. See
1097 // if these chunks can form into a larger vspltis*.
1099 // Check to see if all of the leading entries are either 0 or -1. If
1100 // neither, then this won't fit into the immediate field.
1101 bool LeadingZero = true;
1102 bool LeadingOnes = true;
1103 for (unsigned i = 0; i != Multiple-1; ++i) {
1104 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1106 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1107 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1109 // Finally, check the least significant entry.
1111 if (!UniquedVals[Multiple-1].getNode())
1112 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1113 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1115 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1118 if (!UniquedVals[Multiple-1].getNode())
1119 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1120 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1121 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1122 return DAG.getTargetConstant(Val, MVT::i32);
1128 // Check to see if this buildvec has a single non-undef value in its elements.
1129 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1130 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1131 if (!OpVal.getNode())
1132 OpVal = N->getOperand(i);
1133 else if (OpVal != N->getOperand(i))
1137 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1139 unsigned ValSizeInBytes = EltSize;
1141 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1142 Value = CN->getZExtValue();
1143 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1144 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1145 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1148 // If the splat value is larger than the element value, then we can never do
1149 // this splat. The only case that we could fit the replicated bits into our
1150 // immediate field for would be zero, and we prefer to use vxor for it.
1151 if (ValSizeInBytes < ByteSize) return SDValue();
1153 // If the element value is larger than the splat value, cut it in half and
1154 // check to see if the two halves are equal. Continue doing this until we
1155 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1156 while (ValSizeInBytes > ByteSize) {
1157 ValSizeInBytes >>= 1;
1159 // If the top half equals the bottom half, we're still ok.
1160 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1161 (Value & ((1 << (8*ValSizeInBytes))-1)))
1165 // Properly sign extend the value.
1166 int MaskVal = SignExtend32(Value, ByteSize * 8);
1168 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1169 if (MaskVal == 0) return SDValue();
1171 // Finally, if this value fits in a 5 bit sext field, return it
1172 if (SignExtend32<5>(MaskVal) == MaskVal)
1173 return DAG.getTargetConstant(MaskVal, MVT::i32);
1177 //===----------------------------------------------------------------------===//
1178 // Addressing Mode Selection
1179 //===----------------------------------------------------------------------===//
1181 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1182 /// or 64-bit immediate, and if the value can be accurately represented as a
1183 /// sign extension from a 16-bit value. If so, this returns true and the
1185 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1186 if (!isa<ConstantSDNode>(N))
1189 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1190 if (N->getValueType(0) == MVT::i32)
1191 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1193 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1195 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1196 return isIntS16Immediate(Op.getNode(), Imm);
1200 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1201 /// can be represented as an indexed [r+r] operation. Returns false if it
1202 /// can be more efficiently represented with [r+imm].
1203 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1205 SelectionDAG &DAG) const {
1207 if (N.getOpcode() == ISD::ADD) {
1208 if (isIntS16Immediate(N.getOperand(1), imm))
1209 return false; // r+i
1210 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1211 return false; // r+i
1213 Base = N.getOperand(0);
1214 Index = N.getOperand(1);
1216 } else if (N.getOpcode() == ISD::OR) {
1217 if (isIntS16Immediate(N.getOperand(1), imm))
1218 return false; // r+i can fold it if we can.
1220 // If this is an or of disjoint bitfields, we can codegen this as an add
1221 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1223 APInt LHSKnownZero, LHSKnownOne;
1224 APInt RHSKnownZero, RHSKnownOne;
1225 DAG.computeKnownBits(N.getOperand(0),
1226 LHSKnownZero, LHSKnownOne);
1228 if (LHSKnownZero.getBoolValue()) {
1229 DAG.computeKnownBits(N.getOperand(1),
1230 RHSKnownZero, RHSKnownOne);
1231 // If all of the bits are known zero on the LHS or RHS, the add won't
1233 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1234 Base = N.getOperand(0);
1235 Index = N.getOperand(1);
1244 // If we happen to be doing an i64 load or store into a stack slot that has
1245 // less than a 4-byte alignment, then the frame-index elimination may need to
1246 // use an indexed load or store instruction (because the offset may not be a
1247 // multiple of 4). The extra register needed to hold the offset comes from the
1248 // register scavenger, and it is possible that the scavenger will need to use
1249 // an emergency spill slot. As a result, we need to make sure that a spill slot
1250 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1252 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1253 // FIXME: This does not handle the LWA case.
1257 // NOTE: We'll exclude negative FIs here, which come from argument
1258 // lowering, because there are no known test cases triggering this problem
1259 // using packed structures (or similar). We can remove this exclusion if
1260 // we find such a test case. The reason why this is so test-case driven is
1261 // because this entire 'fixup' is only to prevent crashes (from the
1262 // register scavenger) on not-really-valid inputs. For example, if we have:
1264 // %b = bitcast i1* %a to i64*
1265 // store i64* a, i64 b
1266 // then the store should really be marked as 'align 1', but is not. If it
1267 // were marked as 'align 1' then the indexed form would have been
1268 // instruction-selected initially, and the problem this 'fixup' is preventing
1269 // won't happen regardless.
1273 MachineFunction &MF = DAG.getMachineFunction();
1274 MachineFrameInfo *MFI = MF.getFrameInfo();
1276 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1280 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1281 FuncInfo->setHasNonRISpills();
1284 /// Returns true if the address N can be represented by a base register plus
1285 /// a signed 16-bit displacement [r+imm], and if it is not better
1286 /// represented as reg+reg. If Aligned is true, only accept displacements
1287 /// suitable for STD and friends, i.e. multiples of 4.
1288 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1291 bool Aligned) const {
1292 // FIXME dl should come from parent load or store, not from address
1294 // If this can be more profitably realized as r+r, fail.
1295 if (SelectAddressRegReg(N, Disp, Base, DAG))
1298 if (N.getOpcode() == ISD::ADD) {
1300 if (isIntS16Immediate(N.getOperand(1), imm) &&
1301 (!Aligned || (imm & 3) == 0)) {
1302 Disp = DAG.getTargetConstant(imm, N.getValueType());
1303 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1304 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1305 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1307 Base = N.getOperand(0);
1309 return true; // [r+i]
1310 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1311 // Match LOAD (ADD (X, Lo(G))).
1312 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1313 && "Cannot handle constant offsets yet!");
1314 Disp = N.getOperand(1).getOperand(0); // The global address.
1315 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1316 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1317 Disp.getOpcode() == ISD::TargetConstantPool ||
1318 Disp.getOpcode() == ISD::TargetJumpTable);
1319 Base = N.getOperand(0);
1320 return true; // [&g+r]
1322 } else if (N.getOpcode() == ISD::OR) {
1324 if (isIntS16Immediate(N.getOperand(1), imm) &&
1325 (!Aligned || (imm & 3) == 0)) {
1326 // If this is an or of disjoint bitfields, we can codegen this as an add
1327 // (for better address arithmetic) if the LHS and RHS of the OR are
1328 // provably disjoint.
1329 APInt LHSKnownZero, LHSKnownOne;
1330 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1332 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1333 // If all of the bits are known zero on the LHS or RHS, the add won't
1335 Base = N.getOperand(0);
1336 Disp = DAG.getTargetConstant(imm, N.getValueType());
1340 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1341 // Loading from a constant address.
1343 // If this address fits entirely in a 16-bit sext immediate field, codegen
1346 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1347 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1348 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1349 CN->getValueType(0));
1353 // Handle 32-bit sext immediates with LIS + addr mode.
1354 if ((CN->getValueType(0) == MVT::i32 ||
1355 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1356 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1357 int Addr = (int)CN->getZExtValue();
1359 // Otherwise, break this down into an LIS + disp.
1360 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1362 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1363 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1364 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1369 Disp = DAG.getTargetConstant(0, getPointerTy());
1370 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1371 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1372 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1375 return true; // [r+0]
1378 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1379 /// represented as an indexed [r+r] operation.
1380 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1382 SelectionDAG &DAG) const {
1383 // Check to see if we can easily represent this as an [r+r] address. This
1384 // will fail if it thinks that the address is more profitably represented as
1385 // reg+imm, e.g. where imm = 0.
1386 if (SelectAddressRegReg(N, Base, Index, DAG))
1389 // If the operand is an addition, always emit this as [r+r], since this is
1390 // better (for code size, and execution, as the memop does the add for free)
1391 // than emitting an explicit add.
1392 if (N.getOpcode() == ISD::ADD) {
1393 Base = N.getOperand(0);
1394 Index = N.getOperand(1);
1398 // Otherwise, do it the hard way, using R0 as the base register.
1399 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1405 /// getPreIndexedAddressParts - returns true by value, base pointer and
1406 /// offset pointer and addressing mode by reference if the node's address
1407 /// can be legally represented as pre-indexed load / store address.
1408 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1410 ISD::MemIndexedMode &AM,
1411 SelectionDAG &DAG) const {
1412 if (DisablePPCPreinc) return false;
1418 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1419 Ptr = LD->getBasePtr();
1420 VT = LD->getMemoryVT();
1421 Alignment = LD->getAlignment();
1422 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1423 Ptr = ST->getBasePtr();
1424 VT = ST->getMemoryVT();
1425 Alignment = ST->getAlignment();
1430 // PowerPC doesn't have preinc load/store instructions for vectors.
1434 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1436 // Common code will reject creating a pre-inc form if the base pointer
1437 // is a frame index, or if N is a store and the base pointer is either
1438 // the same as or a predecessor of the value being stored. Check for
1439 // those situations here, and try with swapped Base/Offset instead.
1442 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1445 SDValue Val = cast<StoreSDNode>(N)->getValue();
1446 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1451 std::swap(Base, Offset);
1457 // LDU/STU can only handle immediates that are a multiple of 4.
1458 if (VT != MVT::i64) {
1459 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1462 // LDU/STU need an address with at least 4-byte alignment.
1466 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1470 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1471 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1472 // sext i32 to i64 when addr mode is r+i.
1473 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1474 LD->getExtensionType() == ISD::SEXTLOAD &&
1475 isa<ConstantSDNode>(Offset))
1483 //===----------------------------------------------------------------------===//
1484 // LowerOperation implementation
1485 //===----------------------------------------------------------------------===//
1487 /// GetLabelAccessInfo - Return true if we should reference labels using a
1488 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1489 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1490 unsigned &LoOpFlags,
1491 const GlobalValue *GV = nullptr) {
1492 HiOpFlags = PPCII::MO_HA;
1493 LoOpFlags = PPCII::MO_LO;
1495 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1496 // non-darwin platform. We don't support PIC on other platforms yet.
1497 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1498 TM.getSubtarget<PPCSubtarget>().isDarwin();
1500 HiOpFlags |= PPCII::MO_PIC_FLAG;
1501 LoOpFlags |= PPCII::MO_PIC_FLAG;
1504 // If this is a reference to a global value that requires a non-lazy-ptr, make
1505 // sure that instruction lowering adds it.
1506 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1507 HiOpFlags |= PPCII::MO_NLP_FLAG;
1508 LoOpFlags |= PPCII::MO_NLP_FLAG;
1510 if (GV->hasHiddenVisibility()) {
1511 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1512 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1519 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1520 SelectionDAG &DAG) {
1521 EVT PtrVT = HiPart.getValueType();
1522 SDValue Zero = DAG.getConstant(0, PtrVT);
1525 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1526 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1528 // With PIC, the first instruction is actually "GR+hi(&G)".
1530 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1531 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1533 // Generate non-pic code that has direct accesses to the constant pool.
1534 // The address of the global is just (hi(&g)+lo(&g)).
1535 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1538 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1539 SelectionDAG &DAG) const {
1540 EVT PtrVT = Op.getValueType();
1541 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1542 const Constant *C = CP->getConstVal();
1544 // 64-bit SVR4 ABI code is always position-independent.
1545 // The actual address of the GlobalValue is stored in the TOC.
1546 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1547 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1548 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1549 DAG.getRegister(PPC::X2, MVT::i64));
1552 unsigned MOHiFlag, MOLoFlag;
1553 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1555 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1557 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1558 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1561 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1562 EVT PtrVT = Op.getValueType();
1563 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1565 // 64-bit SVR4 ABI code is always position-independent.
1566 // The actual address of the GlobalValue is stored in the TOC.
1567 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1568 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1569 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1570 DAG.getRegister(PPC::X2, MVT::i64));
1573 unsigned MOHiFlag, MOLoFlag;
1574 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1575 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1576 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1577 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1580 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1581 SelectionDAG &DAG) const {
1582 EVT PtrVT = Op.getValueType();
1584 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1586 unsigned MOHiFlag, MOLoFlag;
1587 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1588 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1589 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1590 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1593 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1594 SelectionDAG &DAG) const {
1596 // FIXME: TLS addresses currently use medium model code sequences,
1597 // which is the most useful form. Eventually support for small and
1598 // large models could be added if users need it, at the cost of
1599 // additional complexity.
1600 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1602 const GlobalValue *GV = GA->getGlobal();
1603 EVT PtrVT = getPointerTy();
1604 bool is64bit = Subtarget.isPPC64();
1606 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1608 if (Model == TLSModel::LocalExec) {
1609 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1610 PPCII::MO_TPREL_HA);
1611 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1612 PPCII::MO_TPREL_LO);
1613 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1614 is64bit ? MVT::i64 : MVT::i32);
1615 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1616 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1619 if (Model == TLSModel::InitialExec) {
1620 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1621 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1625 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1626 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1627 PtrVT, GOTReg, TGA);
1629 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1630 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1631 PtrVT, TGA, GOTPtr);
1632 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1635 if (Model == TLSModel::GeneralDynamic) {
1636 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1637 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1638 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1640 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1643 // We need a chain node, and don't have one handy. The underlying
1644 // call has no side effects, so using the function entry node
1646 SDValue Chain = DAG.getEntryNode();
1647 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1648 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1649 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1650 PtrVT, ParmReg, TGA);
1651 // The return value from GET_TLS_ADDR really is in X3 already, but
1652 // some hacks are needed here to tie everything together. The extra
1653 // copies dissolve during subsequent transforms.
1654 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1655 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1658 if (Model == TLSModel::LocalDynamic) {
1659 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1660 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1661 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1663 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1666 // We need a chain node, and don't have one handy. The underlying
1667 // call has no side effects, so using the function entry node
1669 SDValue Chain = DAG.getEntryNode();
1670 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1671 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1672 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1673 PtrVT, ParmReg, TGA);
1674 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1675 // some hacks are needed here to tie everything together. The extra
1676 // copies dissolve during subsequent transforms.
1677 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1678 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1679 Chain, ParmReg, TGA);
1680 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1683 llvm_unreachable("Unknown TLS model!");
1686 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1687 SelectionDAG &DAG) const {
1688 EVT PtrVT = Op.getValueType();
1689 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1691 const GlobalValue *GV = GSDN->getGlobal();
1693 // 64-bit SVR4 ABI code is always position-independent.
1694 // The actual address of the GlobalValue is stored in the TOC.
1695 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1696 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1697 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1698 DAG.getRegister(PPC::X2, MVT::i64));
1701 unsigned MOHiFlag, MOLoFlag;
1702 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1705 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1707 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1709 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1711 // If the global reference is actually to a non-lazy-pointer, we have to do an
1712 // extra load to get the address of the global.
1713 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1714 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1715 false, false, false, 0);
1719 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1720 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1723 if (Op.getValueType() == MVT::v2i64) {
1724 // When the operands themselves are v2i64 values, we need to do something
1725 // special because VSX has no underlying comparison operations for these.
1726 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1727 // Equality can be handled by casting to the legal type for Altivec
1728 // comparisons, everything else needs to be expanded.
1729 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1730 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1731 DAG.getSetCC(dl, MVT::v4i32,
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1733 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1740 // We handle most of these in the usual way.
1744 // If we're comparing for equality to zero, expose the fact that this is
1745 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1746 // fold the new nodes.
1747 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1748 if (C->isNullValue() && CC == ISD::SETEQ) {
1749 EVT VT = Op.getOperand(0).getValueType();
1750 SDValue Zext = Op.getOperand(0);
1751 if (VT.bitsLT(MVT::i32)) {
1753 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1755 unsigned Log2b = Log2_32(VT.getSizeInBits());
1756 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1757 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1758 DAG.getConstant(Log2b, MVT::i32));
1759 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1761 // Leave comparisons against 0 and -1 alone for now, since they're usually
1762 // optimized. FIXME: revisit this when we can custom lower all setcc
1764 if (C->isAllOnesValue() || C->isNullValue())
1768 // If we have an integer seteq/setne, turn it into a compare against zero
1769 // by xor'ing the rhs with the lhs, which is faster than setting a
1770 // condition register, reading it back out, and masking the correct bit. The
1771 // normal approach here uses sub to do this instead of xor. Using xor exposes
1772 // the result to other bit-twiddling opportunities.
1773 EVT LHSVT = Op.getOperand(0).getValueType();
1774 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1775 EVT VT = Op.getValueType();
1776 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1778 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1783 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1784 const PPCSubtarget &Subtarget) const {
1785 SDNode *Node = Op.getNode();
1786 EVT VT = Node->getValueType(0);
1787 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1788 SDValue InChain = Node->getOperand(0);
1789 SDValue VAListPtr = Node->getOperand(1);
1790 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1793 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1796 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1797 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1799 InChain = GprIndex.getValue(1);
1801 if (VT == MVT::i64) {
1802 // Check if GprIndex is even
1803 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1804 DAG.getConstant(1, MVT::i32));
1805 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1806 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1807 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1808 DAG.getConstant(1, MVT::i32));
1809 // Align GprIndex to be even if it isn't
1810 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1814 // fpr index is 1 byte after gpr
1815 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1816 DAG.getConstant(1, MVT::i32));
1819 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1820 FprPtr, MachinePointerInfo(SV), MVT::i8,
1822 InChain = FprIndex.getValue(1);
1824 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1825 DAG.getConstant(8, MVT::i32));
1827 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1828 DAG.getConstant(4, MVT::i32));
1831 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1832 MachinePointerInfo(), false, false,
1834 InChain = OverflowArea.getValue(1);
1836 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1837 MachinePointerInfo(), false, false,
1839 InChain = RegSaveArea.getValue(1);
1841 // select overflow_area if index > 8
1842 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1843 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1845 // adjustment constant gpr_index * 4/8
1846 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1847 VT.isInteger() ? GprIndex : FprIndex,
1848 DAG.getConstant(VT.isInteger() ? 4 : 8,
1851 // OurReg = RegSaveArea + RegConstant
1852 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1855 // Floating types are 32 bytes into RegSaveArea
1856 if (VT.isFloatingPoint())
1857 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1858 DAG.getConstant(32, MVT::i32));
1860 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1861 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1862 VT.isInteger() ? GprIndex : FprIndex,
1863 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1866 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1867 VT.isInteger() ? VAListPtr : FprPtr,
1868 MachinePointerInfo(SV),
1869 MVT::i8, false, false, 0);
1871 // determine if we should load from reg_save_area or overflow_area
1872 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1874 // increase overflow_area by 4/8 if gpr/fpr > 8
1875 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1876 DAG.getConstant(VT.isInteger() ? 4 : 8,
1879 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1882 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1884 MachinePointerInfo(),
1885 MVT::i32, false, false, 0);
1887 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1888 false, false, false, 0);
1891 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1892 const PPCSubtarget &Subtarget) const {
1893 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1895 // We have to copy the entire va_list struct:
1896 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1897 return DAG.getMemcpy(Op.getOperand(0), Op,
1898 Op.getOperand(1), Op.getOperand(2),
1899 DAG.getConstant(12, MVT::i32), 8, false, true,
1900 MachinePointerInfo(), MachinePointerInfo());
1903 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1904 SelectionDAG &DAG) const {
1905 return Op.getOperand(0);
1908 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1909 SelectionDAG &DAG) const {
1910 SDValue Chain = Op.getOperand(0);
1911 SDValue Trmp = Op.getOperand(1); // trampoline
1912 SDValue FPtr = Op.getOperand(2); // nested function
1913 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1916 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1917 bool isPPC64 = (PtrVT == MVT::i64);
1919 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1922 TargetLowering::ArgListTy Args;
1923 TargetLowering::ArgListEntry Entry;
1925 Entry.Ty = IntPtrTy;
1926 Entry.Node = Trmp; Args.push_back(Entry);
1928 // TrampSize == (isPPC64 ? 48 : 40);
1929 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1930 isPPC64 ? MVT::i64 : MVT::i32);
1931 Args.push_back(Entry);
1933 Entry.Node = FPtr; Args.push_back(Entry);
1934 Entry.Node = Nest; Args.push_back(Entry);
1936 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1937 TargetLowering::CallLoweringInfo CLI(DAG);
1938 CLI.setDebugLoc(dl).setChain(Chain)
1939 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1940 DAG.getExternalSymbol("__trampoline_setup", PtrVT), &Args, 0);
1942 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1943 return CallResult.second;
1946 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1947 const PPCSubtarget &Subtarget) const {
1948 MachineFunction &MF = DAG.getMachineFunction();
1949 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1953 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1954 // vastart just stores the address of the VarArgsFrameIndex slot into the
1955 // memory location argument.
1956 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1957 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1958 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1959 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1960 MachinePointerInfo(SV),
1964 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1965 // We suppose the given va_list is already allocated.
1968 // char gpr; /* index into the array of 8 GPRs
1969 // * stored in the register save area
1970 // * gpr=0 corresponds to r3,
1971 // * gpr=1 to r4, etc.
1973 // char fpr; /* index into the array of 8 FPRs
1974 // * stored in the register save area
1975 // * fpr=0 corresponds to f1,
1976 // * fpr=1 to f2, etc.
1978 // char *overflow_arg_area;
1979 // /* location on stack that holds
1980 // * the next overflow argument
1982 // char *reg_save_area;
1983 // /* where r3:r10 and f1:f8 (if saved)
1989 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1990 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1993 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1995 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1997 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2000 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2001 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2003 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2004 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2006 uint64_t FPROffset = 1;
2007 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2009 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2011 // Store first byte : number of int regs
2012 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2014 MachinePointerInfo(SV),
2015 MVT::i8, false, false, 0);
2016 uint64_t nextOffset = FPROffset;
2017 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2020 // Store second byte : number of float regs
2021 SDValue secondStore =
2022 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2023 MachinePointerInfo(SV, nextOffset), MVT::i8,
2025 nextOffset += StackOffset;
2026 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2028 // Store second word : arguments given on stack
2029 SDValue thirdStore =
2030 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2031 MachinePointerInfo(SV, nextOffset),
2033 nextOffset += FrameOffset;
2034 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2036 // Store third word : arguments given in registers
2037 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2038 MachinePointerInfo(SV, nextOffset),
2043 #include "PPCGenCallingConv.inc"
2045 // Function whose sole purpose is to kill compiler warnings
2046 // stemming from unused functions included from PPCGenCallingConv.inc.
2047 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2048 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2051 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2052 CCValAssign::LocInfo &LocInfo,
2053 ISD::ArgFlagsTy &ArgFlags,
2058 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2060 CCValAssign::LocInfo &LocInfo,
2061 ISD::ArgFlagsTy &ArgFlags,
2063 static const MCPhysReg ArgRegs[] = {
2064 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2065 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2067 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2069 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2071 // Skip one register if the first unallocated register has an even register
2072 // number and there are still argument registers available which have not been
2073 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2074 // need to skip a register if RegNum is odd.
2075 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2076 State.AllocateReg(ArgRegs[RegNum]);
2079 // Always return false here, as this function only makes sure that the first
2080 // unallocated register has an odd register number and does not actually
2081 // allocate a register for the current argument.
2085 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2087 CCValAssign::LocInfo &LocInfo,
2088 ISD::ArgFlagsTy &ArgFlags,
2090 static const MCPhysReg ArgRegs[] = {
2091 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2095 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2097 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2099 // If there is only one Floating-point register left we need to put both f64
2100 // values of a split ppc_fp128 value on the stack.
2101 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2102 State.AllocateReg(ArgRegs[RegNum]);
2105 // Always return false here, as this function only makes sure that the two f64
2106 // values a ppc_fp128 value is split into are both passed in registers or both
2107 // passed on the stack and does not actually allocate a register for the
2108 // current argument.
2112 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2114 static const MCPhysReg *GetFPR() {
2115 static const MCPhysReg FPR[] = {
2116 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2117 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2123 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2125 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2126 unsigned PtrByteSize) {
2127 unsigned ArgSize = ArgVT.getStoreSize();
2128 if (Flags.isByVal())
2129 ArgSize = Flags.getByValSize();
2130 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2136 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2137 CallingConv::ID CallConv, bool isVarArg,
2138 const SmallVectorImpl<ISD::InputArg>
2140 SDLoc dl, SelectionDAG &DAG,
2141 SmallVectorImpl<SDValue> &InVals)
2143 if (Subtarget.isSVR4ABI()) {
2144 if (Subtarget.isPPC64())
2145 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2148 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2151 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2157 PPCTargetLowering::LowerFormalArguments_32SVR4(
2159 CallingConv::ID CallConv, bool isVarArg,
2160 const SmallVectorImpl<ISD::InputArg>
2162 SDLoc dl, SelectionDAG &DAG,
2163 SmallVectorImpl<SDValue> &InVals) const {
2165 // 32-bit SVR4 ABI Stack Frame Layout:
2166 // +-----------------------------------+
2167 // +--> | Back chain |
2168 // | +-----------------------------------+
2169 // | | Floating-point register save area |
2170 // | +-----------------------------------+
2171 // | | General register save area |
2172 // | +-----------------------------------+
2173 // | | CR save word |
2174 // | +-----------------------------------+
2175 // | | VRSAVE save word |
2176 // | +-----------------------------------+
2177 // | | Alignment padding |
2178 // | +-----------------------------------+
2179 // | | Vector register save area |
2180 // | +-----------------------------------+
2181 // | | Local variable space |
2182 // | +-----------------------------------+
2183 // | | Parameter list area |
2184 // | +-----------------------------------+
2185 // | | LR save word |
2186 // | +-----------------------------------+
2187 // SP--> +--- | Back chain |
2188 // +-----------------------------------+
2191 // System V Application Binary Interface PowerPC Processor Supplement
2192 // AltiVec Technology Programming Interface Manual
2194 MachineFunction &MF = DAG.getMachineFunction();
2195 MachineFrameInfo *MFI = MF.getFrameInfo();
2196 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2198 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2199 // Potential tail calls could cause overwriting of argument stack slots.
2200 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2201 (CallConv == CallingConv::Fast));
2202 unsigned PtrByteSize = 4;
2204 // Assign locations to all of the incoming arguments.
2205 SmallVector<CCValAssign, 16> ArgLocs;
2206 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2207 getTargetMachine(), ArgLocs, *DAG.getContext());
2209 // Reserve space for the linkage area on the stack.
2210 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2212 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2214 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2215 CCValAssign &VA = ArgLocs[i];
2217 // Arguments stored in registers.
2218 if (VA.isRegLoc()) {
2219 const TargetRegisterClass *RC;
2220 EVT ValVT = VA.getValVT();
2222 switch (ValVT.getSimpleVT().SimpleTy) {
2224 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2227 RC = &PPC::GPRCRegClass;
2230 RC = &PPC::F4RCRegClass;
2233 if (Subtarget.hasVSX())
2234 RC = &PPC::VSFRCRegClass;
2236 RC = &PPC::F8RCRegClass;
2242 RC = &PPC::VRRCRegClass;
2246 RC = &PPC::VSHRCRegClass;
2250 // Transform the arguments stored in physical registers into virtual ones.
2251 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2252 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2253 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2255 if (ValVT == MVT::i1)
2256 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2258 InVals.push_back(ArgValue);
2260 // Argument stored in memory.
2261 assert(VA.isMemLoc());
2263 unsigned ArgSize = VA.getLocVT().getStoreSize();
2264 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2267 // Create load nodes to retrieve arguments from the stack.
2268 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2269 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2270 MachinePointerInfo(),
2271 false, false, false, 0));
2275 // Assign locations to all of the incoming aggregate by value arguments.
2276 // Aggregates passed by value are stored in the local variable space of the
2277 // caller's stack frame, right above the parameter list area.
2278 SmallVector<CCValAssign, 16> ByValArgLocs;
2279 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2280 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2282 // Reserve stack space for the allocations in CCInfo.
2283 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2285 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2287 // Area that is at least reserved in the caller of this function.
2288 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2290 // Set the size that is at least reserved in caller of this function. Tail
2291 // call optimized function's reserved stack space needs to be aligned so that
2292 // taking the difference between two stack areas will result in an aligned
2294 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2297 std::max(MinReservedArea,
2298 PPCFrameLowering::getMinCallFrameSize(false, false));
2300 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2301 getStackAlignment();
2302 unsigned AlignMask = TargetAlign-1;
2303 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2305 FI->setMinReservedArea(MinReservedArea);
2307 SmallVector<SDValue, 8> MemOps;
2309 // If the function takes variable number of arguments, make a frame index for
2310 // the start of the first vararg value... for expansion of llvm.va_start.
2312 static const MCPhysReg GPArgRegs[] = {
2313 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2314 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2316 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2318 static const MCPhysReg FPArgRegs[] = {
2319 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2322 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2324 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2326 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2329 // Make room for NumGPArgRegs and NumFPArgRegs.
2330 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2331 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2333 FuncInfo->setVarArgsStackOffset(
2334 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2335 CCInfo.getNextStackOffset(), true));
2337 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2338 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2340 // The fixed integer arguments of a variadic function are stored to the
2341 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2342 // the result of va_next.
2343 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2344 // Get an existing live-in vreg, or add a new one.
2345 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2347 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2349 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2350 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2351 MachinePointerInfo(), false, false, 0);
2352 MemOps.push_back(Store);
2353 // Increment the address by four for the next argument to store
2354 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2355 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2358 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2360 // The double arguments are stored to the VarArgsFrameIndex
2362 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2363 // Get an existing live-in vreg, or add a new one.
2364 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2366 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2368 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2369 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2370 MachinePointerInfo(), false, false, 0);
2371 MemOps.push_back(Store);
2372 // Increment the address by eight for the next argument to store
2373 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2375 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2379 if (!MemOps.empty())
2380 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2385 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2386 // value to MVT::i64 and then truncate to the correct register size.
2388 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2389 SelectionDAG &DAG, SDValue ArgVal,
2392 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2393 DAG.getValueType(ObjectVT));
2394 else if (Flags.isZExt())
2395 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2396 DAG.getValueType(ObjectVT));
2398 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2401 // Set the size that is at least reserved in caller of this function. Tail
2402 // call optimized functions' reserved stack space needs to be aligned so that
2403 // taking the difference between two stack areas will result in an aligned
2406 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2407 unsigned nAltivecParamsAtEnd,
2408 unsigned MinReservedArea,
2409 bool isPPC64) const {
2410 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2411 // Add the Altivec parameters at the end, if needed.
2412 if (nAltivecParamsAtEnd) {
2413 MinReservedArea = ((MinReservedArea+15)/16)*16;
2414 MinReservedArea += 16*nAltivecParamsAtEnd;
2417 std::max(MinReservedArea,
2418 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2419 unsigned TargetAlign
2420 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2421 getStackAlignment();
2422 unsigned AlignMask = TargetAlign-1;
2423 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2424 FI->setMinReservedArea(MinReservedArea);
2428 PPCTargetLowering::LowerFormalArguments_64SVR4(
2430 CallingConv::ID CallConv, bool isVarArg,
2431 const SmallVectorImpl<ISD::InputArg>
2433 SDLoc dl, SelectionDAG &DAG,
2434 SmallVectorImpl<SDValue> &InVals) const {
2435 // TODO: add description of PPC stack frame format, or at least some docs.
2437 MachineFunction &MF = DAG.getMachineFunction();
2438 MachineFrameInfo *MFI = MF.getFrameInfo();
2439 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2441 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2442 // Potential tail calls could cause overwriting of argument stack slots.
2443 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2444 (CallConv == CallingConv::Fast));
2445 unsigned PtrByteSize = 8;
2447 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2448 // Area that is at least reserved in caller of this function.
2449 unsigned MinReservedArea = ArgOffset;
2451 static const MCPhysReg GPR[] = {
2452 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2453 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2456 static const MCPhysReg *FPR = GetFPR();
2458 static const MCPhysReg VR[] = {
2459 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2460 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2462 static const MCPhysReg VSRH[] = {
2463 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2464 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2467 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2468 const unsigned Num_FPR_Regs = 13;
2469 const unsigned Num_VR_Regs = array_lengthof(VR);
2471 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2473 // Add DAG nodes to load the arguments or copy them out of registers. On
2474 // entry to a function on PPC, the arguments start after the linkage area,
2475 // although the first ones are often in registers.
2477 SmallVector<SDValue, 8> MemOps;
2478 unsigned nAltivecParamsAtEnd = 0;
2479 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2480 unsigned CurArgIdx = 0;
2481 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2483 bool needsLoad = false;
2484 EVT ObjectVT = Ins[ArgNo].VT;
2485 unsigned ObjSize = ObjectVT.getStoreSize();
2486 unsigned ArgSize = ObjSize;
2487 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2488 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2489 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2491 unsigned CurArgOffset = ArgOffset;
2493 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2494 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2495 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2496 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64) {
2498 MinReservedArea = ((MinReservedArea+15)/16)*16;
2499 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2503 nAltivecParamsAtEnd++;
2505 // Calculate min reserved area.
2506 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2510 // FIXME the codegen can be much improved in some cases.
2511 // We do not have to keep everything in memory.
2512 if (Flags.isByVal()) {
2513 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2514 ObjSize = Flags.getByValSize();
2515 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2516 // Empty aggregate parameters do not take up registers. Examples:
2520 // etc. However, we have to provide a place-holder in InVals, so
2521 // pretend we have an 8-byte item at the current address for that
2524 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2525 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2526 InVals.push_back(FIN);
2530 unsigned BVAlign = Flags.getByValAlign();
2532 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2533 CurArgOffset = ArgOffset;
2536 // All aggregates smaller than 8 bytes must be passed right-justified.
2537 if (ObjSize < PtrByteSize)
2538 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2539 // The value of the object is its address.
2540 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2541 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2542 InVals.push_back(FIN);
2545 if (GPR_idx != Num_GPR_Regs) {
2546 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2547 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2550 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2551 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2552 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2553 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2554 MachinePointerInfo(FuncArg),
2555 ObjType, false, false, 0);
2557 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2558 // store the whole register as-is to the parameter save area
2559 // slot. The address of the parameter was already calculated
2560 // above (InVals.push_back(FIN)) to be the right-justified
2561 // offset within the slot. For this store, we need a new
2562 // frame index that points at the beginning of the slot.
2563 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2564 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2565 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2566 MachinePointerInfo(FuncArg),
2570 MemOps.push_back(Store);
2573 // Whether we copied from a register or not, advance the offset
2574 // into the parameter save area by a full doubleword.
2575 ArgOffset += PtrByteSize;
2579 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2580 // Store whatever pieces of the object are in registers
2581 // to memory. ArgOffset will be the address of the beginning
2583 if (GPR_idx != Num_GPR_Regs) {
2585 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2586 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2587 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2588 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2589 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2590 MachinePointerInfo(FuncArg, j),
2592 MemOps.push_back(Store);
2594 ArgOffset += PtrByteSize;
2596 ArgOffset += ArgSize - j;
2603 switch (ObjectVT.getSimpleVT().SimpleTy) {
2604 default: llvm_unreachable("Unhandled argument type!");
2608 if (GPR_idx != Num_GPR_Regs) {
2609 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2610 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2612 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2613 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2614 // value to MVT::i64 and then truncate to the correct register size.
2615 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2620 ArgSize = PtrByteSize;
2627 // Every 8 bytes of argument space consumes one of the GPRs available for
2628 // argument passing.
2629 if (GPR_idx != Num_GPR_Regs) {
2632 if (FPR_idx != Num_FPR_Regs) {
2635 if (ObjectVT == MVT::f32)
2636 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2638 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2639 &PPC::VSFRCRegClass :
2640 &PPC::F8RCRegClass);
2642 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2646 ArgSize = PtrByteSize;
2657 // Note that vector arguments in registers don't reserve stack space,
2658 // except in varargs functions.
2659 if (VR_idx != Num_VR_Regs) {
2660 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2661 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2662 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2663 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2665 while ((ArgOffset % 16) != 0) {
2666 ArgOffset += PtrByteSize;
2667 if (GPR_idx != Num_GPR_Regs)
2671 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2675 // Vectors are aligned.
2676 ArgOffset = ((ArgOffset+15)/16)*16;
2677 CurArgOffset = ArgOffset;
2684 // We need to load the argument to a virtual register if we determined
2685 // above that we ran out of physical registers of the appropriate type.
2687 int FI = MFI->CreateFixedObject(ObjSize,
2688 CurArgOffset + (ArgSize - ObjSize),
2690 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2691 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2692 false, false, false, 0);
2695 InVals.push_back(ArgVal);
2698 // Set the size that is at least reserved in caller of this function. Tail
2699 // call optimized functions' reserved stack space needs to be aligned so that
2700 // taking the difference between two stack areas will result in an aligned
2702 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, true);
2704 // If the function takes variable number of arguments, make a frame index for
2705 // the start of the first vararg value... for expansion of llvm.va_start.
2707 int Depth = ArgOffset;
2709 FuncInfo->setVarArgsFrameIndex(
2710 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2711 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2713 // If this function is vararg, store any remaining integer argument regs
2714 // to their spots on the stack so that they may be loaded by deferencing the
2715 // result of va_next.
2716 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2717 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2718 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2719 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2720 MachinePointerInfo(), false, false, 0);
2721 MemOps.push_back(Store);
2722 // Increment the address by four for the next argument to store
2723 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2724 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2728 if (!MemOps.empty())
2729 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2735 PPCTargetLowering::LowerFormalArguments_Darwin(
2737 CallingConv::ID CallConv, bool isVarArg,
2738 const SmallVectorImpl<ISD::InputArg>
2740 SDLoc dl, SelectionDAG &DAG,
2741 SmallVectorImpl<SDValue> &InVals) const {
2742 // TODO: add description of PPC stack frame format, or at least some docs.
2744 MachineFunction &MF = DAG.getMachineFunction();
2745 MachineFrameInfo *MFI = MF.getFrameInfo();
2746 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2748 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2749 bool isPPC64 = PtrVT == MVT::i64;
2750 // Potential tail calls could cause overwriting of argument stack slots.
2751 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2752 (CallConv == CallingConv::Fast));
2753 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2755 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2756 // Area that is at least reserved in caller of this function.
2757 unsigned MinReservedArea = ArgOffset;
2759 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2760 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2761 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2763 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2764 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2765 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2768 static const MCPhysReg *FPR = GetFPR();
2770 static const MCPhysReg VR[] = {
2771 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2772 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2775 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2776 const unsigned Num_FPR_Regs = 13;
2777 const unsigned Num_VR_Regs = array_lengthof( VR);
2779 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2781 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2783 // In 32-bit non-varargs functions, the stack space for vectors is after the
2784 // stack space for non-vectors. We do not use this space unless we have
2785 // too many vectors to fit in registers, something that only occurs in
2786 // constructed examples:), but we have to walk the arglist to figure
2787 // that out...for the pathological case, compute VecArgOffset as the
2788 // start of the vector parameter area. Computing VecArgOffset is the
2789 // entire point of the following loop.
2790 unsigned VecArgOffset = ArgOffset;
2791 if (!isVarArg && !isPPC64) {
2792 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2794 EVT ObjectVT = Ins[ArgNo].VT;
2795 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2797 if (Flags.isByVal()) {
2798 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2799 unsigned ObjSize = Flags.getByValSize();
2801 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2802 VecArgOffset += ArgSize;
2806 switch(ObjectVT.getSimpleVT().SimpleTy) {
2807 default: llvm_unreachable("Unhandled argument type!");
2813 case MVT::i64: // PPC64
2815 // FIXME: We are guaranteed to be !isPPC64 at this point.
2816 // Does MVT::i64 apply?
2823 // Nothing to do, we're only looking at Nonvector args here.
2828 // We've found where the vector parameter area in memory is. Skip the
2829 // first 12 parameters; these don't use that memory.
2830 VecArgOffset = ((VecArgOffset+15)/16)*16;
2831 VecArgOffset += 12*16;
2833 // Add DAG nodes to load the arguments or copy them out of registers. On
2834 // entry to a function on PPC, the arguments start after the linkage area,
2835 // although the first ones are often in registers.
2837 SmallVector<SDValue, 8> MemOps;
2838 unsigned nAltivecParamsAtEnd = 0;
2839 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2840 unsigned CurArgIdx = 0;
2841 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2843 bool needsLoad = false;
2844 EVT ObjectVT = Ins[ArgNo].VT;
2845 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2846 unsigned ArgSize = ObjSize;
2847 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2848 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2849 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2851 unsigned CurArgOffset = ArgOffset;
2853 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2854 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2855 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2856 if (isVarArg || isPPC64) {
2857 MinReservedArea = ((MinReservedArea+15)/16)*16;
2858 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2861 } else nAltivecParamsAtEnd++;
2863 // Calculate min reserved area.
2864 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2868 // FIXME the codegen can be much improved in some cases.
2869 // We do not have to keep everything in memory.
2870 if (Flags.isByVal()) {
2871 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2872 ObjSize = Flags.getByValSize();
2873 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2874 // Objects of size 1 and 2 are right justified, everything else is
2875 // left justified. This means the memory address is adjusted forwards.
2876 if (ObjSize==1 || ObjSize==2) {
2877 CurArgOffset = CurArgOffset + (4 - ObjSize);
2879 // The value of the object is its address.
2880 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2881 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2882 InVals.push_back(FIN);
2883 if (ObjSize==1 || ObjSize==2) {
2884 if (GPR_idx != Num_GPR_Regs) {
2887 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2889 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2890 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2891 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2892 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2893 MachinePointerInfo(FuncArg),
2894 ObjType, false, false, 0);
2895 MemOps.push_back(Store);
2899 ArgOffset += PtrByteSize;
2903 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2904 // Store whatever pieces of the object are in registers
2905 // to memory. ArgOffset will be the address of the beginning
2907 if (GPR_idx != Num_GPR_Regs) {
2910 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2912 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2913 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2914 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2915 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2916 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2917 MachinePointerInfo(FuncArg, j),
2919 MemOps.push_back(Store);
2921 ArgOffset += PtrByteSize;
2923 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2930 switch (ObjectVT.getSimpleVT().SimpleTy) {
2931 default: llvm_unreachable("Unhandled argument type!");
2935 if (GPR_idx != Num_GPR_Regs) {
2936 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2937 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2939 if (ObjectVT == MVT::i1)
2940 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2945 ArgSize = PtrByteSize;
2947 // All int arguments reserve stack space in the Darwin ABI.
2948 ArgOffset += PtrByteSize;
2952 case MVT::i64: // PPC64
2953 if (GPR_idx != Num_GPR_Regs) {
2954 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2955 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2957 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2958 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2959 // value to MVT::i64 and then truncate to the correct register size.
2960 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2965 ArgSize = PtrByteSize;
2967 // All int arguments reserve stack space in the Darwin ABI.
2973 // Every 4 bytes of argument space consumes one of the GPRs available for
2974 // argument passing.
2975 if (GPR_idx != Num_GPR_Regs) {
2977 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2980 if (FPR_idx != Num_FPR_Regs) {
2983 if (ObjectVT == MVT::f32)
2984 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2986 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2988 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2994 // All FP arguments reserve stack space in the Darwin ABI.
2995 ArgOffset += isPPC64 ? 8 : ObjSize;
3001 // Note that vector arguments in registers don't reserve stack space,
3002 // except in varargs functions.
3003 if (VR_idx != Num_VR_Regs) {
3004 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3005 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3007 while ((ArgOffset % 16) != 0) {
3008 ArgOffset += PtrByteSize;
3009 if (GPR_idx != Num_GPR_Regs)
3013 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3017 if (!isVarArg && !isPPC64) {
3018 // Vectors go after all the nonvectors.
3019 CurArgOffset = VecArgOffset;
3022 // Vectors are aligned.
3023 ArgOffset = ((ArgOffset+15)/16)*16;
3024 CurArgOffset = ArgOffset;
3032 // We need to load the argument to a virtual register if we determined above
3033 // that we ran out of physical registers of the appropriate type.
3035 int FI = MFI->CreateFixedObject(ObjSize,
3036 CurArgOffset + (ArgSize - ObjSize),
3038 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3039 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3040 false, false, false, 0);
3043 InVals.push_back(ArgVal);
3046 // Set the size that is at least reserved in caller of this function. Tail
3047 // call optimized functions' reserved stack space needs to be aligned so that
3048 // taking the difference between two stack areas will result in an aligned
3050 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
3052 // If the function takes variable number of arguments, make a frame index for
3053 // the start of the first vararg value... for expansion of llvm.va_start.
3055 int Depth = ArgOffset;
3057 FuncInfo->setVarArgsFrameIndex(
3058 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3060 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3062 // If this function is vararg, store any remaining integer argument regs
3063 // to their spots on the stack so that they may be loaded by deferencing the
3064 // result of va_next.
3065 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3069 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3071 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3073 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3074 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3075 MachinePointerInfo(), false, false, 0);
3076 MemOps.push_back(Store);
3077 // Increment the address by four for the next argument to store
3078 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3079 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3083 if (!MemOps.empty())
3084 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3089 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
3090 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
3092 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
3096 const SmallVectorImpl<ISD::OutputArg>
3098 const SmallVectorImpl<SDValue> &OutVals,
3099 unsigned &nAltivecParamsAtEnd) {
3100 // Count how many bytes are to be pushed on the stack, including the linkage
3101 // area, and parameter passing area. We start with 24/48 bytes, which is
3102 // prereserved space for [SP][CR][LR][3 x unused].
3103 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
3104 unsigned NumOps = Outs.size();
3105 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3107 // Add up all the space actually used.
3108 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
3109 // they all go in registers, but we must reserve stack space for them for
3110 // possible use by the caller. In varargs or 64-bit calls, parameters are
3111 // assigned stack space in order, with padding so Altivec parameters are
3113 nAltivecParamsAtEnd = 0;
3114 for (unsigned i = 0; i != NumOps; ++i) {
3115 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3116 EVT ArgVT = Outs[i].VT;
3117 // Varargs Altivec parameters are padded to a 16 byte boundary.
3118 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
3119 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8 ||
3120 ArgVT==MVT::v2f64 || ArgVT==MVT::v2i64) {
3121 if (!isVarArg && !isPPC64) {
3122 // Non-varargs Altivec parameters go after all the non-Altivec
3123 // parameters; handle those later so we know how much padding we need.
3124 nAltivecParamsAtEnd++;
3127 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
3128 NumBytes = ((NumBytes+15)/16)*16;
3130 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3133 // Allow for Altivec parameters at the end, if needed.
3134 if (nAltivecParamsAtEnd) {
3135 NumBytes = ((NumBytes+15)/16)*16;
3136 NumBytes += 16*nAltivecParamsAtEnd;
3139 // The prolog code of the callee may store up to 8 GPR argument registers to
3140 // the stack, allowing va_start to index over them in memory if its varargs.
3141 // Because we cannot tell if this is needed on the caller side, we have to
3142 // conservatively assume that it is needed. As such, make sure we have at
3143 // least enough stack space for the caller to store the 8 GPRs.
3144 NumBytes = std::max(NumBytes,
3145 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
3147 // Tail call needs the stack to be aligned.
3148 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
3149 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
3150 getFrameLowering()->getStackAlignment();
3151 unsigned AlignMask = TargetAlign-1;
3152 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3158 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3159 /// adjusted to accommodate the arguments for the tailcall.
3160 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3161 unsigned ParamSize) {
3163 if (!isTailCall) return 0;
3165 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3166 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3167 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3168 // Remember only if the new adjustement is bigger.
3169 if (SPDiff < FI->getTailCallSPDelta())
3170 FI->setTailCallSPDelta(SPDiff);
3175 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3176 /// for tail call optimization. Targets which want to do tail call
3177 /// optimization should implement this function.
3179 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3180 CallingConv::ID CalleeCC,
3182 const SmallVectorImpl<ISD::InputArg> &Ins,
3183 SelectionDAG& DAG) const {
3184 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3187 // Variable argument functions are not supported.
3191 MachineFunction &MF = DAG.getMachineFunction();
3192 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3193 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3194 // Functions containing by val parameters are not supported.
3195 for (unsigned i = 0; i != Ins.size(); i++) {
3196 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3197 if (Flags.isByVal()) return false;
3200 // Non-PIC/GOT tail calls are supported.
3201 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3204 // At the moment we can only do local tail calls (in same module, hidden
3205 // or protected) if we are generating PIC.
3206 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3207 return G->getGlobal()->hasHiddenVisibility()
3208 || G->getGlobal()->hasProtectedVisibility();
3214 /// isCallCompatibleAddress - Return the immediate to use if the specified
3215 /// 32-bit value is representable in the immediate field of a BxA instruction.
3216 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3217 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3218 if (!C) return nullptr;
3220 int Addr = C->getZExtValue();
3221 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3222 SignExtend32<26>(Addr) != Addr)
3223 return nullptr; // Top 6 bits have to be sext of immediate.
3225 return DAG.getConstant((int)C->getZExtValue() >> 2,
3226 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3231 struct TailCallArgumentInfo {
3236 TailCallArgumentInfo() : FrameIdx(0) {}
3241 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3243 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3245 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3246 SmallVectorImpl<SDValue> &MemOpChains,
3248 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3249 SDValue Arg = TailCallArgs[i].Arg;
3250 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3251 int FI = TailCallArgs[i].FrameIdx;
3252 // Store relative to framepointer.
3253 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3254 MachinePointerInfo::getFixedStack(FI),
3259 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3260 /// the appropriate stack slot for the tail call optimized function call.
3261 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3262 MachineFunction &MF,
3271 // Calculate the new stack slot for the return address.
3272 int SlotSize = isPPC64 ? 8 : 4;
3273 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3275 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3276 NewRetAddrLoc, true);
3277 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3278 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3279 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3280 MachinePointerInfo::getFixedStack(NewRetAddr),
3283 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3284 // slot as the FP is never overwritten.
3287 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3288 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3290 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3291 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3292 MachinePointerInfo::getFixedStack(NewFPIdx),
3299 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3300 /// the position of the argument.
3302 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3303 SDValue Arg, int SPDiff, unsigned ArgOffset,
3304 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3305 int Offset = ArgOffset + SPDiff;
3306 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3307 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3308 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3309 SDValue FIN = DAG.getFrameIndex(FI, VT);
3310 TailCallArgumentInfo Info;
3312 Info.FrameIdxOp = FIN;
3314 TailCallArguments.push_back(Info);
3317 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3318 /// stack slot. Returns the chain as result and the loaded frame pointers in
3319 /// LROpOut/FPOpout. Used when tail calling.
3320 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3328 // Load the LR and FP stack slot for later adjusting.
3329 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3330 LROpOut = getReturnAddrFrameIndex(DAG);
3331 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3332 false, false, false, 0);
3333 Chain = SDValue(LROpOut.getNode(), 1);
3335 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3336 // slot as the FP is never overwritten.
3338 FPOpOut = getFramePointerFrameIndex(DAG);
3339 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3340 false, false, false, 0);
3341 Chain = SDValue(FPOpOut.getNode(), 1);
3347 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3348 /// by "Src" to address "Dst" of size "Size". Alignment information is
3349 /// specified by the specific parameter attribute. The copy will be passed as
3350 /// a byval function parameter.
3351 /// Sometimes what we are copying is the end of a larger object, the part that
3352 /// does not fit in registers.
3354 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3355 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3357 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3358 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3359 false, false, MachinePointerInfo(),
3360 MachinePointerInfo());
3363 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3366 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3367 SDValue Arg, SDValue PtrOff, int SPDiff,
3368 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3369 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3370 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3372 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3377 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3379 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3380 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3381 DAG.getConstant(ArgOffset, PtrVT));
3383 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3384 MachinePointerInfo(), false, false, 0));
3385 // Calculate and remember argument location.
3386 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3391 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3392 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3393 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3394 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3395 MachineFunction &MF = DAG.getMachineFunction();
3397 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3398 // might overwrite each other in case of tail call optimization.
3399 SmallVector<SDValue, 8> MemOpChains2;
3400 // Do not flag preceding copytoreg stuff together with the following stuff.
3402 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3404 if (!MemOpChains2.empty())
3405 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3407 // Store the return address to the appropriate stack slot.
3408 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3409 isPPC64, isDarwinABI, dl);
3411 // Emit callseq_end just before tailcall node.
3412 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3413 DAG.getIntPtrConstant(0, true), InFlag, dl);
3414 InFlag = Chain.getValue(1);
3418 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3419 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3420 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3421 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3422 const PPCSubtarget &Subtarget) {
3424 bool isPPC64 = Subtarget.isPPC64();
3425 bool isSVR4ABI = Subtarget.isSVR4ABI();
3427 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3428 NodeTys.push_back(MVT::Other); // Returns a chain
3429 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3431 unsigned CallOpc = PPCISD::CALL;
3433 bool needIndirectCall = true;
3434 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3435 // If this is an absolute destination address, use the munged value.
3436 Callee = SDValue(Dest, 0);
3437 needIndirectCall = false;
3440 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3441 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3442 // Use indirect calls for ALL functions calls in JIT mode, since the
3443 // far-call stubs may be outside relocation limits for a BL instruction.
3444 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3445 unsigned OpFlags = 0;
3446 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3447 (Subtarget.getTargetTriple().isMacOSX() &&
3448 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3449 (G->getGlobal()->isDeclaration() ||
3450 G->getGlobal()->isWeakForLinker())) {
3451 // PC-relative references to external symbols should go through $stub,
3452 // unless we're building with the leopard linker or later, which
3453 // automatically synthesizes these stubs.
3454 OpFlags = PPCII::MO_DARWIN_STUB;
3457 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3458 // every direct call is) turn it into a TargetGlobalAddress /
3459 // TargetExternalSymbol node so that legalize doesn't hack it.
3460 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3461 Callee.getValueType(),
3463 needIndirectCall = false;
3467 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3468 unsigned char OpFlags = 0;
3470 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3471 (Subtarget.getTargetTriple().isMacOSX() &&
3472 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3473 // PC-relative references to external symbols should go through $stub,
3474 // unless we're building with the leopard linker or later, which
3475 // automatically synthesizes these stubs.
3476 OpFlags = PPCII::MO_DARWIN_STUB;
3479 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3481 needIndirectCall = false;
3484 if (needIndirectCall) {
3485 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3486 // to do the call, we can't use PPCISD::CALL.
3487 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3489 if (isSVR4ABI && isPPC64) {
3490 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3491 // entry point, but to the function descriptor (the function entry point
3492 // address is part of the function descriptor though).
3493 // The function descriptor is a three doubleword structure with the
3494 // following fields: function entry point, TOC base address and
3495 // environment pointer.
3496 // Thus for a call through a function pointer, the following actions need
3498 // 1. Save the TOC of the caller in the TOC save area of its stack
3499 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3500 // 2. Load the address of the function entry point from the function
3502 // 3. Load the TOC of the callee from the function descriptor into r2.
3503 // 4. Load the environment pointer from the function descriptor into
3505 // 5. Branch to the function entry point address.
3506 // 6. On return of the callee, the TOC of the caller needs to be
3507 // restored (this is done in FinishCall()).
3509 // All those operations are flagged together to ensure that no other
3510 // operations can be scheduled in between. E.g. without flagging the
3511 // operations together, a TOC access in the caller could be scheduled
3512 // between the load of the callee TOC and the branch to the callee, which
3513 // results in the TOC access going through the TOC of the callee instead
3514 // of going through the TOC of the caller, which leads to incorrect code.
3516 // Load the address of the function entry point from the function
3518 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3519 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3520 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3521 Chain = LoadFuncPtr.getValue(1);
3522 InFlag = LoadFuncPtr.getValue(2);
3524 // Load environment pointer into r11.
3525 // Offset of the environment pointer within the function descriptor.
3526 SDValue PtrOff = DAG.getIntPtrConstant(16);
3528 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3529 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3531 Chain = LoadEnvPtr.getValue(1);
3532 InFlag = LoadEnvPtr.getValue(2);
3534 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3536 Chain = EnvVal.getValue(0);
3537 InFlag = EnvVal.getValue(1);
3539 // Load TOC of the callee into r2. We are using a target-specific load
3540 // with r2 hard coded, because the result of a target-independent load
3541 // would never go directly into r2, since r2 is a reserved register (which
3542 // prevents the register allocator from allocating it), resulting in an
3543 // additional register being allocated and an unnecessary move instruction
3545 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3546 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3548 Chain = LoadTOCPtr.getValue(0);
3549 InFlag = LoadTOCPtr.getValue(1);
3551 MTCTROps[0] = Chain;
3552 MTCTROps[1] = LoadFuncPtr;
3553 MTCTROps[2] = InFlag;
3556 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3557 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3558 InFlag = Chain.getValue(1);
3561 NodeTys.push_back(MVT::Other);
3562 NodeTys.push_back(MVT::Glue);
3563 Ops.push_back(Chain);
3564 CallOpc = PPCISD::BCTRL;
3565 Callee.setNode(nullptr);
3566 // Add use of X11 (holding environment pointer)
3567 if (isSVR4ABI && isPPC64)
3568 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3569 // Add CTR register as callee so a bctr can be emitted later.
3571 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3574 // If this is a direct call, pass the chain and the callee.
3575 if (Callee.getNode()) {
3576 Ops.push_back(Chain);
3577 Ops.push_back(Callee);
3579 // If this is a tail call add stack pointer delta.
3581 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3583 // Add argument registers to the end of the list so that they are known live
3585 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3586 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3587 RegsToPass[i].second.getValueType()));
3593 bool isLocalCall(const SDValue &Callee)
3595 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3596 return !G->getGlobal()->isDeclaration() &&
3597 !G->getGlobal()->isWeakForLinker();
3602 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3603 CallingConv::ID CallConv, bool isVarArg,
3604 const SmallVectorImpl<ISD::InputArg> &Ins,
3605 SDLoc dl, SelectionDAG &DAG,
3606 SmallVectorImpl<SDValue> &InVals) const {
3608 SmallVector<CCValAssign, 16> RVLocs;
3609 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3610 getTargetMachine(), RVLocs, *DAG.getContext());
3611 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3613 // Copy all of the result registers out of their specified physreg.
3614 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3615 CCValAssign &VA = RVLocs[i];
3616 assert(VA.isRegLoc() && "Can only return in registers!");
3618 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3619 VA.getLocReg(), VA.getLocVT(), InFlag);
3620 Chain = Val.getValue(1);
3621 InFlag = Val.getValue(2);
3623 switch (VA.getLocInfo()) {
3624 default: llvm_unreachable("Unknown loc info!");
3625 case CCValAssign::Full: break;
3626 case CCValAssign::AExt:
3627 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3629 case CCValAssign::ZExt:
3630 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3631 DAG.getValueType(VA.getValVT()));
3632 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3634 case CCValAssign::SExt:
3635 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3636 DAG.getValueType(VA.getValVT()));
3637 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3641 InVals.push_back(Val);
3648 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3649 bool isTailCall, bool isVarArg,
3651 SmallVector<std::pair<unsigned, SDValue>, 8>
3653 SDValue InFlag, SDValue Chain,
3655 int SPDiff, unsigned NumBytes,
3656 const SmallVectorImpl<ISD::InputArg> &Ins,
3657 SmallVectorImpl<SDValue> &InVals) const {
3658 std::vector<EVT> NodeTys;
3659 SmallVector<SDValue, 8> Ops;
3660 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3661 isTailCall, RegsToPass, Ops, NodeTys,
3664 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3665 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3666 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3668 // When performing tail call optimization the callee pops its arguments off
3669 // the stack. Account for this here so these bytes can be pushed back on in
3670 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3671 int BytesCalleePops =
3672 (CallConv == CallingConv::Fast &&
3673 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3675 // Add a register mask operand representing the call-preserved registers.
3676 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3677 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3678 assert(Mask && "Missing call preserved mask for calling convention");
3679 Ops.push_back(DAG.getRegisterMask(Mask));
3681 if (InFlag.getNode())
3682 Ops.push_back(InFlag);
3686 assert(((Callee.getOpcode() == ISD::Register &&
3687 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3688 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3689 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3690 isa<ConstantSDNode>(Callee)) &&
3691 "Expecting an global address, external symbol, absolute value or register");
3693 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3696 // Add a NOP immediately after the branch instruction when using the 64-bit
3697 // SVR4 ABI. At link time, if caller and callee are in a different module and
3698 // thus have a different TOC, the call will be replaced with a call to a stub
3699 // function which saves the current TOC, loads the TOC of the callee and
3700 // branches to the callee. The NOP will be replaced with a load instruction
3701 // which restores the TOC of the caller from the TOC save slot of the current
3702 // stack frame. If caller and callee belong to the same module (and have the
3703 // same TOC), the NOP will remain unchanged.
3705 bool needsTOCRestore = false;
3706 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3707 if (CallOpc == PPCISD::BCTRL) {
3708 // This is a call through a function pointer.
3709 // Restore the caller TOC from the save area into R2.
3710 // See PrepareCall() for more information about calls through function
3711 // pointers in the 64-bit SVR4 ABI.
3712 // We are using a target-specific load with r2 hard coded, because the
3713 // result of a target-independent load would never go directly into r2,
3714 // since r2 is a reserved register (which prevents the register allocator
3715 // from allocating it), resulting in an additional register being
3716 // allocated and an unnecessary move instruction being generated.
3717 needsTOCRestore = true;
3718 } else if ((CallOpc == PPCISD::CALL) &&
3719 (!isLocalCall(Callee) ||
3720 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3721 // Otherwise insert NOP for non-local calls.
3722 CallOpc = PPCISD::CALL_NOP;
3726 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3727 InFlag = Chain.getValue(1);
3729 if (needsTOCRestore) {
3730 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3731 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
3732 InFlag = Chain.getValue(1);
3735 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3736 DAG.getIntPtrConstant(BytesCalleePops, true),
3739 InFlag = Chain.getValue(1);
3741 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3742 Ins, dl, DAG, InVals);
3746 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3747 SmallVectorImpl<SDValue> &InVals) const {
3748 SelectionDAG &DAG = CLI.DAG;
3750 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3751 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3752 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3753 SDValue Chain = CLI.Chain;
3754 SDValue Callee = CLI.Callee;
3755 bool &isTailCall = CLI.IsTailCall;
3756 CallingConv::ID CallConv = CLI.CallConv;
3757 bool isVarArg = CLI.IsVarArg;
3760 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3763 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3764 report_fatal_error("failed to perform tail call elimination on a call "
3765 "site marked musttail");
3767 if (Subtarget.isSVR4ABI()) {
3768 if (Subtarget.isPPC64())
3769 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3770 isTailCall, Outs, OutVals, Ins,
3773 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3774 isTailCall, Outs, OutVals, Ins,
3778 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3779 isTailCall, Outs, OutVals, Ins,
3784 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3785 CallingConv::ID CallConv, bool isVarArg,
3787 const SmallVectorImpl<ISD::OutputArg> &Outs,
3788 const SmallVectorImpl<SDValue> &OutVals,
3789 const SmallVectorImpl<ISD::InputArg> &Ins,
3790 SDLoc dl, SelectionDAG &DAG,
3791 SmallVectorImpl<SDValue> &InVals) const {
3792 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3793 // of the 32-bit SVR4 ABI stack frame layout.
3795 assert((CallConv == CallingConv::C ||
3796 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3798 unsigned PtrByteSize = 4;
3800 MachineFunction &MF = DAG.getMachineFunction();
3802 // Mark this function as potentially containing a function that contains a
3803 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3804 // and restoring the callers stack pointer in this functions epilog. This is
3805 // done because by tail calling the called function might overwrite the value
3806 // in this function's (MF) stack pointer stack slot 0(SP).
3807 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3808 CallConv == CallingConv::Fast)
3809 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3811 // Count how many bytes are to be pushed on the stack, including the linkage
3812 // area, parameter list area and the part of the local variable space which
3813 // contains copies of aggregates which are passed by value.
3815 // Assign locations to all of the outgoing arguments.
3816 SmallVector<CCValAssign, 16> ArgLocs;
3817 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3818 getTargetMachine(), ArgLocs, *DAG.getContext());
3820 // Reserve space for the linkage area on the stack.
3821 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3824 // Handle fixed and variable vector arguments differently.
3825 // Fixed vector arguments go into registers as long as registers are
3826 // available. Variable vector arguments always go into memory.
3827 unsigned NumArgs = Outs.size();
3829 for (unsigned i = 0; i != NumArgs; ++i) {
3830 MVT ArgVT = Outs[i].VT;
3831 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3834 if (Outs[i].IsFixed) {
3835 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3838 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3844 errs() << "Call operand #" << i << " has unhandled type "
3845 << EVT(ArgVT).getEVTString() << "\n";
3847 llvm_unreachable(nullptr);
3851 // All arguments are treated the same.
3852 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3855 // Assign locations to all of the outgoing aggregate by value arguments.
3856 SmallVector<CCValAssign, 16> ByValArgLocs;
3857 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3858 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3860 // Reserve stack space for the allocations in CCInfo.
3861 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3863 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3865 // Size of the linkage area, parameter list area and the part of the local
3866 // space variable where copies of aggregates which are passed by value are
3868 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3870 // Calculate by how many bytes the stack has to be adjusted in case of tail
3871 // call optimization.
3872 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3874 // Adjust the stack pointer for the new arguments...
3875 // These operations are automatically eliminated by the prolog/epilog pass
3876 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3878 SDValue CallSeqStart = Chain;
3880 // Load the return address and frame pointer so it can be moved somewhere else
3883 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3886 // Set up a copy of the stack pointer for use loading and storing any
3887 // arguments that may not fit in the registers available for argument
3889 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3891 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3892 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3893 SmallVector<SDValue, 8> MemOpChains;
3895 bool seenFloatArg = false;
3896 // Walk the register/memloc assignments, inserting copies/loads.
3897 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3900 CCValAssign &VA = ArgLocs[i];
3901 SDValue Arg = OutVals[i];
3902 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3904 if (Flags.isByVal()) {
3905 // Argument is an aggregate which is passed by value, thus we need to
3906 // create a copy of it in the local variable space of the current stack
3907 // frame (which is the stack frame of the caller) and pass the address of
3908 // this copy to the callee.
3909 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3910 CCValAssign &ByValVA = ByValArgLocs[j++];
3911 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3913 // Memory reserved in the local variable space of the callers stack frame.
3914 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3916 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3917 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3919 // Create a copy of the argument in the local area of the current
3921 SDValue MemcpyCall =
3922 CreateCopyOfByValArgument(Arg, PtrOff,
3923 CallSeqStart.getNode()->getOperand(0),
3926 // This must go outside the CALLSEQ_START..END.
3927 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3928 CallSeqStart.getNode()->getOperand(1),
3930 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3931 NewCallSeqStart.getNode());
3932 Chain = CallSeqStart = NewCallSeqStart;
3934 // Pass the address of the aggregate copy on the stack either in a
3935 // physical register or in the parameter list area of the current stack
3936 // frame to the callee.
3940 if (VA.isRegLoc()) {
3941 if (Arg.getValueType() == MVT::i1)
3942 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3944 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3945 // Put argument in a physical register.
3946 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3948 // Put argument in the parameter list area of the current stack frame.
3949 assert(VA.isMemLoc());
3950 unsigned LocMemOffset = VA.getLocMemOffset();
3953 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3954 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3956 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3957 MachinePointerInfo(),
3960 // Calculate and remember argument location.
3961 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3967 if (!MemOpChains.empty())
3968 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3970 // Build a sequence of copy-to-reg nodes chained together with token chain
3971 // and flag operands which copy the outgoing args into the appropriate regs.
3973 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3974 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3975 RegsToPass[i].second, InFlag);
3976 InFlag = Chain.getValue(1);
3979 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3982 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3983 SDValue Ops[] = { Chain, InFlag };
3985 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3986 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3988 InFlag = Chain.getValue(1);
3992 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3993 false, TailCallArguments);
3995 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3996 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4000 // Copy an argument into memory, being careful to do this outside the
4001 // call sequence for the call to which the argument belongs.
4003 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4004 SDValue CallSeqStart,
4005 ISD::ArgFlagsTy Flags,
4008 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4009 CallSeqStart.getNode()->getOperand(0),
4011 // The MEMCPY must go outside the CALLSEQ_START..END.
4012 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4013 CallSeqStart.getNode()->getOperand(1),
4015 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4016 NewCallSeqStart.getNode());
4017 return NewCallSeqStart;
4021 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4022 CallingConv::ID CallConv, bool isVarArg,
4024 const SmallVectorImpl<ISD::OutputArg> &Outs,
4025 const SmallVectorImpl<SDValue> &OutVals,
4026 const SmallVectorImpl<ISD::InputArg> &Ins,
4027 SDLoc dl, SelectionDAG &DAG,
4028 SmallVectorImpl<SDValue> &InVals) const {
4030 unsigned NumOps = Outs.size();
4032 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4033 unsigned PtrByteSize = 8;
4035 MachineFunction &MF = DAG.getMachineFunction();
4037 // Mark this function as potentially containing a function that contains a
4038 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4039 // and restoring the callers stack pointer in this functions epilog. This is
4040 // done because by tail calling the called function might overwrite the value
4041 // in this function's (MF) stack pointer stack slot 0(SP).
4042 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4043 CallConv == CallingConv::Fast)
4044 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4046 unsigned nAltivecParamsAtEnd = 0;
4048 // Count how many bytes are to be pushed on the stack, including the linkage
4049 // area, and parameter passing area. We start with at least 48 bytes, which
4050 // is reserved space for [SP][CR][LR][3 x unused].
4051 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
4054 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
4055 Outs, OutVals, nAltivecParamsAtEnd);
4057 // Calculate by how many bytes the stack has to be adjusted in case of tail
4058 // call optimization.
4059 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4061 // To protect arguments on the stack from being clobbered in a tail call,
4062 // force all the loads to happen before doing any other lowering.
4064 Chain = DAG.getStackArgumentTokenFactor(Chain);
4066 // Adjust the stack pointer for the new arguments...
4067 // These operations are automatically eliminated by the prolog/epilog pass
4068 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4070 SDValue CallSeqStart = Chain;
4072 // Load the return address and frame pointer so it can be move somewhere else
4075 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4078 // Set up a copy of the stack pointer for use loading and storing any
4079 // arguments that may not fit in the registers available for argument
4081 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4083 // Figure out which arguments are going to go in registers, and which in
4084 // memory. Also, if this is a vararg function, floating point operations
4085 // must be stored to our stack, and loaded into integer regs as well, if
4086 // any integer regs are available for argument passing.
4087 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
4088 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4090 static const MCPhysReg GPR[] = {
4091 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4092 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4094 static const MCPhysReg *FPR = GetFPR();
4096 static const MCPhysReg VR[] = {
4097 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4098 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4100 static const MCPhysReg VSRH[] = {
4101 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4102 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4105 const unsigned NumGPRs = array_lengthof(GPR);
4106 const unsigned NumFPRs = 13;
4107 const unsigned NumVRs = array_lengthof(VR);
4109 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4110 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4112 SmallVector<SDValue, 8> MemOpChains;
4113 for (unsigned i = 0; i != NumOps; ++i) {
4114 SDValue Arg = OutVals[i];
4115 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4117 // PtrOff will be used to store the current argument to the stack if a
4118 // register cannot be found for it.
4121 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4123 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4125 // Promote integers to 64-bit values.
4126 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4127 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4128 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4129 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4132 // FIXME memcpy is used way more than necessary. Correctness first.
4133 // Note: "by value" is code for passing a structure by value, not
4135 if (Flags.isByVal()) {
4136 // Note: Size includes alignment padding, so
4137 // struct x { short a; char b; }
4138 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4139 // These are the proper values we need for right-justifying the
4140 // aggregate in a parameter register.
4141 unsigned Size = Flags.getByValSize();
4143 // An empty aggregate parameter takes up no storage and no
4148 unsigned BVAlign = Flags.getByValAlign();
4150 if (BVAlign % PtrByteSize != 0)
4152 "ByVal alignment is not a multiple of the pointer size");
4154 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4157 // All aggregates smaller than 8 bytes must be passed right-justified.
4158 if (Size==1 || Size==2 || Size==4) {
4159 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4160 if (GPR_idx != NumGPRs) {
4161 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4162 MachinePointerInfo(), VT,
4164 MemOpChains.push_back(Load.getValue(1));
4165 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4167 ArgOffset += PtrByteSize;
4172 if (GPR_idx == NumGPRs && Size < 8) {
4173 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4174 PtrOff.getValueType());
4175 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4176 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4179 ArgOffset += PtrByteSize;
4182 // Copy entire object into memory. There are cases where gcc-generated
4183 // code assumes it is there, even if it could be put entirely into
4184 // registers. (This is not what the doc says.)
4186 // FIXME: The above statement is likely due to a misunderstanding of the
4187 // documents. All arguments must be copied into the parameter area BY
4188 // THE CALLEE in the event that the callee takes the address of any
4189 // formal argument. That has not yet been implemented. However, it is
4190 // reasonable to use the stack area as a staging area for the register
4193 // Skip this for small aggregates, as we will use the same slot for a
4194 // right-justified copy, below.
4196 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4200 // When a register is available, pass a small aggregate right-justified.
4201 if (Size < 8 && GPR_idx != NumGPRs) {
4202 // The easiest way to get this right-justified in a register
4203 // is to copy the structure into the rightmost portion of a
4204 // local variable slot, then load the whole slot into the
4206 // FIXME: The memcpy seems to produce pretty awful code for
4207 // small aggregates, particularly for packed ones.
4208 // FIXME: It would be preferable to use the slot in the
4209 // parameter save area instead of a new local variable.
4210 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4211 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4212 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4216 // Load the slot into the register.
4217 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4218 MachinePointerInfo(),
4219 false, false, false, 0);
4220 MemOpChains.push_back(Load.getValue(1));
4221 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4223 // Done with this argument.
4224 ArgOffset += PtrByteSize;
4228 // For aggregates larger than PtrByteSize, copy the pieces of the
4229 // object that fit into registers from the parameter save area.
4230 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4231 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4232 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4233 if (GPR_idx != NumGPRs) {
4234 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4235 MachinePointerInfo(),
4236 false, false, false, 0);
4237 MemOpChains.push_back(Load.getValue(1));
4238 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4239 ArgOffset += PtrByteSize;
4241 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4248 switch (Arg.getSimpleValueType().SimpleTy) {
4249 default: llvm_unreachable("Unexpected ValueType for argument!");
4253 if (GPR_idx != NumGPRs) {
4254 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4256 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4257 true, isTailCall, false, MemOpChains,
4258 TailCallArguments, dl);
4260 ArgOffset += PtrByteSize;
4264 if (FPR_idx != NumFPRs) {
4265 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4268 // A single float or an aggregate containing only a single float
4269 // must be passed right-justified in the stack doubleword, and
4270 // in the GPR, if one is available.
4272 if (Arg.getSimpleValueType().SimpleTy == MVT::f32) {
4273 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4274 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4278 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4279 MachinePointerInfo(), false, false, 0);
4280 MemOpChains.push_back(Store);
4282 // Float varargs are always shadowed in available integer registers
4283 if (GPR_idx != NumGPRs) {
4284 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4285 MachinePointerInfo(), false, false,
4287 MemOpChains.push_back(Load.getValue(1));
4288 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4290 } else if (GPR_idx != NumGPRs)
4291 // If we have any FPRs remaining, we may also have GPRs remaining.
4294 // Single-precision floating-point values are mapped to the
4295 // second (rightmost) word of the stack doubleword.
4296 if (Arg.getValueType() == MVT::f32) {
4297 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4298 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4301 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4302 true, isTailCall, false, MemOpChains,
4303 TailCallArguments, dl);
4314 // These go aligned on the stack, or in the corresponding R registers
4315 // when within range. The Darwin PPC ABI doc claims they also go in
4316 // V registers; in fact gcc does this only for arguments that are
4317 // prototyped, not for those that match the ... We do it for all
4318 // arguments, seems to work.
4319 while (ArgOffset % 16 !=0) {
4320 ArgOffset += PtrByteSize;
4321 if (GPR_idx != NumGPRs)
4324 // We could elide this store in the case where the object fits
4325 // entirely in R registers. Maybe later.
4326 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4327 DAG.getConstant(ArgOffset, PtrVT));
4328 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4329 MachinePointerInfo(), false, false, 0);
4330 MemOpChains.push_back(Store);
4331 if (VR_idx != NumVRs) {
4332 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4333 MachinePointerInfo(),
4334 false, false, false, 0);
4335 MemOpChains.push_back(Load.getValue(1));
4337 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4338 Arg.getSimpleValueType() == MVT::v2i64) ?
4339 VSRH[VR_idx] : VR[VR_idx];
4342 RegsToPass.push_back(std::make_pair(VReg, Load));
4345 for (unsigned i=0; i<16; i+=PtrByteSize) {
4346 if (GPR_idx == NumGPRs)
4348 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4349 DAG.getConstant(i, PtrVT));
4350 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4351 false, false, false, 0);
4352 MemOpChains.push_back(Load.getValue(1));
4353 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4358 // Non-varargs Altivec params generally go in registers, but have
4359 // stack space allocated at the end.
4360 if (VR_idx != NumVRs) {
4361 // Doesn't have GPR space allocated.
4362 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4363 Arg.getSimpleValueType() == MVT::v2i64) ?
4364 VSRH[VR_idx] : VR[VR_idx];
4367 RegsToPass.push_back(std::make_pair(VReg, Arg));
4369 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4370 true, isTailCall, true, MemOpChains,
4371 TailCallArguments, dl);
4378 if (!MemOpChains.empty())
4379 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4381 // Check if this is an indirect call (MTCTR/BCTRL).
4382 // See PrepareCall() for more information about calls through function
4383 // pointers in the 64-bit SVR4 ABI.
4385 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4386 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4387 !isBLACompatibleAddress(Callee, DAG)) {
4388 // Load r2 into a virtual register and store it to the TOC save area.
4389 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4390 // TOC save area offset.
4391 SDValue PtrOff = DAG.getIntPtrConstant(40);
4392 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4393 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4395 // R12 must contain the address of an indirect callee. This does not
4396 // mean the MTCTR instruction must use R12; it's easier to model this
4397 // as an extra parameter, so do that.
4398 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
4401 // Build a sequence of copy-to-reg nodes chained together with token chain
4402 // and flag operands which copy the outgoing args into the appropriate regs.
4404 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4405 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4406 RegsToPass[i].second, InFlag);
4407 InFlag = Chain.getValue(1);
4411 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4412 FPOp, true, TailCallArguments);
4414 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4415 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4420 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4421 CallingConv::ID CallConv, bool isVarArg,
4423 const SmallVectorImpl<ISD::OutputArg> &Outs,
4424 const SmallVectorImpl<SDValue> &OutVals,
4425 const SmallVectorImpl<ISD::InputArg> &Ins,
4426 SDLoc dl, SelectionDAG &DAG,
4427 SmallVectorImpl<SDValue> &InVals) const {
4429 unsigned NumOps = Outs.size();
4431 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4432 bool isPPC64 = PtrVT == MVT::i64;
4433 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4435 MachineFunction &MF = DAG.getMachineFunction();
4437 // Mark this function as potentially containing a function that contains a
4438 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4439 // and restoring the callers stack pointer in this functions epilog. This is
4440 // done because by tail calling the called function might overwrite the value
4441 // in this function's (MF) stack pointer stack slot 0(SP).
4442 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4443 CallConv == CallingConv::Fast)
4444 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4446 unsigned nAltivecParamsAtEnd = 0;
4448 // Count how many bytes are to be pushed on the stack, including the linkage
4449 // area, and parameter passing area. We start with 24/48 bytes, which is
4450 // prereserved space for [SP][CR][LR][3 x unused].
4452 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4454 nAltivecParamsAtEnd);
4456 // Calculate by how many bytes the stack has to be adjusted in case of tail
4457 // call optimization.
4458 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4460 // To protect arguments on the stack from being clobbered in a tail call,
4461 // force all the loads to happen before doing any other lowering.
4463 Chain = DAG.getStackArgumentTokenFactor(Chain);
4465 // Adjust the stack pointer for the new arguments...
4466 // These operations are automatically eliminated by the prolog/epilog pass
4467 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4469 SDValue CallSeqStart = Chain;
4471 // Load the return address and frame pointer so it can be move somewhere else
4474 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4477 // Set up a copy of the stack pointer for use loading and storing any
4478 // arguments that may not fit in the registers available for argument
4482 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4484 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4486 // Figure out which arguments are going to go in registers, and which in
4487 // memory. Also, if this is a vararg function, floating point operations
4488 // must be stored to our stack, and loaded into integer regs as well, if
4489 // any integer regs are available for argument passing.
4490 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4491 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4493 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4494 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4495 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4497 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4498 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4499 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4501 static const MCPhysReg *FPR = GetFPR();
4503 static const MCPhysReg VR[] = {
4504 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4505 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4507 const unsigned NumGPRs = array_lengthof(GPR_32);
4508 const unsigned NumFPRs = 13;
4509 const unsigned NumVRs = array_lengthof(VR);
4511 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4513 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4514 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4516 SmallVector<SDValue, 8> MemOpChains;
4517 for (unsigned i = 0; i != NumOps; ++i) {
4518 SDValue Arg = OutVals[i];
4519 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4521 // PtrOff will be used to store the current argument to the stack if a
4522 // register cannot be found for it.
4525 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4527 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4529 // On PPC64, promote integers to 64-bit values.
4530 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4531 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4532 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4533 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4536 // FIXME memcpy is used way more than necessary. Correctness first.
4537 // Note: "by value" is code for passing a structure by value, not
4539 if (Flags.isByVal()) {
4540 unsigned Size = Flags.getByValSize();
4541 // Very small objects are passed right-justified. Everything else is
4542 // passed left-justified.
4543 if (Size==1 || Size==2) {
4544 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4545 if (GPR_idx != NumGPRs) {
4546 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4547 MachinePointerInfo(), VT,
4549 MemOpChains.push_back(Load.getValue(1));
4550 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4552 ArgOffset += PtrByteSize;
4554 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4555 PtrOff.getValueType());
4556 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4557 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4560 ArgOffset += PtrByteSize;
4564 // Copy entire object into memory. There are cases where gcc-generated
4565 // code assumes it is there, even if it could be put entirely into
4566 // registers. (This is not what the doc says.)
4567 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4571 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4572 // copy the pieces of the object that fit into registers from the
4573 // parameter save area.
4574 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4575 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4576 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4577 if (GPR_idx != NumGPRs) {
4578 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4579 MachinePointerInfo(),
4580 false, false, false, 0);
4581 MemOpChains.push_back(Load.getValue(1));
4582 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4583 ArgOffset += PtrByteSize;
4585 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4592 switch (Arg.getSimpleValueType().SimpleTy) {
4593 default: llvm_unreachable("Unexpected ValueType for argument!");
4597 if (GPR_idx != NumGPRs) {
4598 if (Arg.getValueType() == MVT::i1)
4599 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4601 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4603 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4604 isPPC64, isTailCall, false, MemOpChains,
4605 TailCallArguments, dl);
4607 ArgOffset += PtrByteSize;
4611 if (FPR_idx != NumFPRs) {
4612 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4615 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4616 MachinePointerInfo(), false, false, 0);
4617 MemOpChains.push_back(Store);
4619 // Float varargs are always shadowed in available integer registers
4620 if (GPR_idx != NumGPRs) {
4621 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4622 MachinePointerInfo(), false, false,
4624 MemOpChains.push_back(Load.getValue(1));
4625 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4627 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4628 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4629 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4630 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4631 MachinePointerInfo(),
4632 false, false, false, 0);
4633 MemOpChains.push_back(Load.getValue(1));
4634 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4637 // If we have any FPRs remaining, we may also have GPRs remaining.
4638 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4640 if (GPR_idx != NumGPRs)
4642 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4643 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4647 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4648 isPPC64, isTailCall, false, MemOpChains,
4649 TailCallArguments, dl);
4653 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4660 // These go aligned on the stack, or in the corresponding R registers
4661 // when within range. The Darwin PPC ABI doc claims they also go in
4662 // V registers; in fact gcc does this only for arguments that are
4663 // prototyped, not for those that match the ... We do it for all
4664 // arguments, seems to work.
4665 while (ArgOffset % 16 !=0) {
4666 ArgOffset += PtrByteSize;
4667 if (GPR_idx != NumGPRs)
4670 // We could elide this store in the case where the object fits
4671 // entirely in R registers. Maybe later.
4672 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4673 DAG.getConstant(ArgOffset, PtrVT));
4674 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4675 MachinePointerInfo(), false, false, 0);
4676 MemOpChains.push_back(Store);
4677 if (VR_idx != NumVRs) {
4678 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4679 MachinePointerInfo(),
4680 false, false, false, 0);
4681 MemOpChains.push_back(Load.getValue(1));
4682 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4685 for (unsigned i=0; i<16; i+=PtrByteSize) {
4686 if (GPR_idx == NumGPRs)
4688 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4689 DAG.getConstant(i, PtrVT));
4690 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4691 false, false, false, 0);
4692 MemOpChains.push_back(Load.getValue(1));
4693 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4698 // Non-varargs Altivec params generally go in registers, but have
4699 // stack space allocated at the end.
4700 if (VR_idx != NumVRs) {
4701 // Doesn't have GPR space allocated.
4702 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4703 } else if (nAltivecParamsAtEnd==0) {
4704 // We are emitting Altivec params in order.
4705 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4706 isPPC64, isTailCall, true, MemOpChains,
4707 TailCallArguments, dl);
4713 // If all Altivec parameters fit in registers, as they usually do,
4714 // they get stack space following the non-Altivec parameters. We
4715 // don't track this here because nobody below needs it.
4716 // If there are more Altivec parameters than fit in registers emit
4718 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4720 // Offset is aligned; skip 1st 12 params which go in V registers.
4721 ArgOffset = ((ArgOffset+15)/16)*16;
4723 for (unsigned i = 0; i != NumOps; ++i) {
4724 SDValue Arg = OutVals[i];
4725 EVT ArgType = Outs[i].VT;
4726 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4727 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4730 // We are emitting Altivec params in order.
4731 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4732 isPPC64, isTailCall, true, MemOpChains,
4733 TailCallArguments, dl);
4740 if (!MemOpChains.empty())
4741 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4743 // On Darwin, R12 must contain the address of an indirect callee. This does
4744 // not mean the MTCTR instruction must use R12; it's easier to model this as
4745 // an extra parameter, so do that.
4747 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4748 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4749 !isBLACompatibleAddress(Callee, DAG))
4750 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4751 PPC::R12), Callee));
4753 // Build a sequence of copy-to-reg nodes chained together with token chain
4754 // and flag operands which copy the outgoing args into the appropriate regs.
4756 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4757 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4758 RegsToPass[i].second, InFlag);
4759 InFlag = Chain.getValue(1);
4763 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4764 FPOp, true, TailCallArguments);
4766 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4767 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4772 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4773 MachineFunction &MF, bool isVarArg,
4774 const SmallVectorImpl<ISD::OutputArg> &Outs,
4775 LLVMContext &Context) const {
4776 SmallVector<CCValAssign, 16> RVLocs;
4777 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4779 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4783 PPCTargetLowering::LowerReturn(SDValue Chain,
4784 CallingConv::ID CallConv, bool isVarArg,
4785 const SmallVectorImpl<ISD::OutputArg> &Outs,
4786 const SmallVectorImpl<SDValue> &OutVals,
4787 SDLoc dl, SelectionDAG &DAG) const {
4789 SmallVector<CCValAssign, 16> RVLocs;
4790 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4791 getTargetMachine(), RVLocs, *DAG.getContext());
4792 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4795 SmallVector<SDValue, 4> RetOps(1, Chain);
4797 // Copy the result values into the output registers.
4798 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4799 CCValAssign &VA = RVLocs[i];
4800 assert(VA.isRegLoc() && "Can only return in registers!");
4802 SDValue Arg = OutVals[i];
4804 switch (VA.getLocInfo()) {
4805 default: llvm_unreachable("Unknown loc info!");
4806 case CCValAssign::Full: break;
4807 case CCValAssign::AExt:
4808 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4810 case CCValAssign::ZExt:
4811 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4813 case CCValAssign::SExt:
4814 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4818 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4819 Flag = Chain.getValue(1);
4820 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4823 RetOps[0] = Chain; // Update chain.
4825 // Add the flag if we have it.
4827 RetOps.push_back(Flag);
4829 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4832 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4833 const PPCSubtarget &Subtarget) const {
4834 // When we pop the dynamic allocation we need to restore the SP link.
4837 // Get the corect type for pointers.
4838 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4840 // Construct the stack pointer operand.
4841 bool isPPC64 = Subtarget.isPPC64();
4842 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4843 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4845 // Get the operands for the STACKRESTORE.
4846 SDValue Chain = Op.getOperand(0);
4847 SDValue SaveSP = Op.getOperand(1);
4849 // Load the old link SP.
4850 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4851 MachinePointerInfo(),
4852 false, false, false, 0);
4854 // Restore the stack pointer.
4855 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4857 // Store the old link SP.
4858 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4865 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4866 MachineFunction &MF = DAG.getMachineFunction();
4867 bool isPPC64 = Subtarget.isPPC64();
4868 bool isDarwinABI = Subtarget.isDarwinABI();
4869 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4871 // Get current frame pointer save index. The users of this index will be
4872 // primarily DYNALLOC instructions.
4873 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4874 int RASI = FI->getReturnAddrSaveIndex();
4876 // If the frame pointer save index hasn't been defined yet.
4878 // Find out what the fix offset of the frame pointer save area.
4879 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4880 // Allocate the frame index for frame pointer save area.
4881 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4883 FI->setReturnAddrSaveIndex(RASI);
4885 return DAG.getFrameIndex(RASI, PtrVT);
4889 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4890 MachineFunction &MF = DAG.getMachineFunction();
4891 bool isPPC64 = Subtarget.isPPC64();
4892 bool isDarwinABI = Subtarget.isDarwinABI();
4893 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4895 // Get current frame pointer save index. The users of this index will be
4896 // primarily DYNALLOC instructions.
4897 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4898 int FPSI = FI->getFramePointerSaveIndex();
4900 // If the frame pointer save index hasn't been defined yet.
4902 // Find out what the fix offset of the frame pointer save area.
4903 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4906 // Allocate the frame index for frame pointer save area.
4907 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4909 FI->setFramePointerSaveIndex(FPSI);
4911 return DAG.getFrameIndex(FPSI, PtrVT);
4914 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4916 const PPCSubtarget &Subtarget) const {
4918 SDValue Chain = Op.getOperand(0);
4919 SDValue Size = Op.getOperand(1);
4922 // Get the corect type for pointers.
4923 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4925 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4926 DAG.getConstant(0, PtrVT), Size);
4927 // Construct a node for the frame pointer save index.
4928 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4929 // Build a DYNALLOC node.
4930 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4931 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4932 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4935 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4936 SelectionDAG &DAG) const {
4938 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4939 DAG.getVTList(MVT::i32, MVT::Other),
4940 Op.getOperand(0), Op.getOperand(1));
4943 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4944 SelectionDAG &DAG) const {
4946 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4947 Op.getOperand(0), Op.getOperand(1));
4950 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4951 assert(Op.getValueType() == MVT::i1 &&
4952 "Custom lowering only for i1 loads");
4954 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4957 LoadSDNode *LD = cast<LoadSDNode>(Op);
4959 SDValue Chain = LD->getChain();
4960 SDValue BasePtr = LD->getBasePtr();
4961 MachineMemOperand *MMO = LD->getMemOperand();
4963 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4964 BasePtr, MVT::i8, MMO);
4965 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4967 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4968 return DAG.getMergeValues(Ops, dl);
4971 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4972 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4973 "Custom lowering only for i1 stores");
4975 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4978 StoreSDNode *ST = cast<StoreSDNode>(Op);
4980 SDValue Chain = ST->getChain();
4981 SDValue BasePtr = ST->getBasePtr();
4982 SDValue Value = ST->getValue();
4983 MachineMemOperand *MMO = ST->getMemOperand();
4985 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4986 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4989 // FIXME: Remove this once the ANDI glue bug is fixed:
4990 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4991 assert(Op.getValueType() == MVT::i1 &&
4992 "Custom lowering only for i1 results");
4995 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4999 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5001 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5002 // Not FP? Not a fsel.
5003 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5004 !Op.getOperand(2).getValueType().isFloatingPoint())
5007 // We might be able to do better than this under some circumstances, but in
5008 // general, fsel-based lowering of select is a finite-math-only optimization.
5009 // For more information, see section F.3 of the 2.06 ISA specification.
5010 if (!DAG.getTarget().Options.NoInfsFPMath ||
5011 !DAG.getTarget().Options.NoNaNsFPMath)
5014 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5016 EVT ResVT = Op.getValueType();
5017 EVT CmpVT = Op.getOperand(0).getValueType();
5018 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5019 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5022 // If the RHS of the comparison is a 0.0, we don't need to do the
5023 // subtraction at all.
5025 if (isFloatingPointZero(RHS))
5027 default: break; // SETUO etc aren't handled by fsel.
5031 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5032 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5033 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5034 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5035 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5036 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5037 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5040 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5043 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5044 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5045 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5048 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5051 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5052 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5053 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5054 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5059 default: break; // SETUO etc aren't handled by fsel.
5063 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5064 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5065 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5066 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5067 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5068 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5069 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5070 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5073 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5074 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5075 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5076 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5079 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5080 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5081 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5082 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5085 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5086 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5087 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5088 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5091 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5092 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5093 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5094 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5099 // FIXME: Split this code up when LegalizeDAGTypes lands.
5100 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5102 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5103 SDValue Src = Op.getOperand(0);
5104 if (Src.getValueType() == MVT::f32)
5105 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5108 switch (Op.getSimpleValueType().SimpleTy) {
5109 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5111 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5112 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5117 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5118 "i64 FP_TO_UINT is supported only with FPCVT");
5119 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5125 // Convert the FP value to an int value through memory.
5126 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5127 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5128 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5129 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5130 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5132 // Emit a store to the stack slot.
5135 MachineFunction &MF = DAG.getMachineFunction();
5136 MachineMemOperand *MMO =
5137 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5138 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5139 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5140 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5142 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5143 MPI, false, false, 0);
5145 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5147 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5148 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5149 DAG.getConstant(4, FIPtr.getValueType()));
5150 MPI = MachinePointerInfo();
5153 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5154 false, false, false, 0);
5157 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5158 SelectionDAG &DAG) const {
5160 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5161 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5164 if (Op.getOperand(0).getValueType() == MVT::i1)
5165 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5166 DAG.getConstantFP(1.0, Op.getValueType()),
5167 DAG.getConstantFP(0.0, Op.getValueType()));
5169 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5170 "UINT_TO_FP is supported only with FPCVT");
5172 // If we have FCFIDS, then use it when converting to single-precision.
5173 // Otherwise, convert to double-precision and then round.
5174 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5175 (Op.getOpcode() == ISD::UINT_TO_FP ?
5176 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5177 (Op.getOpcode() == ISD::UINT_TO_FP ?
5178 PPCISD::FCFIDU : PPCISD::FCFID);
5179 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5180 MVT::f32 : MVT::f64;
5182 if (Op.getOperand(0).getValueType() == MVT::i64) {
5183 SDValue SINT = Op.getOperand(0);
5184 // When converting to single-precision, we actually need to convert
5185 // to double-precision first and then round to single-precision.
5186 // To avoid double-rounding effects during that operation, we have
5187 // to prepare the input operand. Bits that might be truncated when
5188 // converting to double-precision are replaced by a bit that won't
5189 // be lost at this stage, but is below the single-precision rounding
5192 // However, if -enable-unsafe-fp-math is in effect, accept double
5193 // rounding to avoid the extra overhead.
5194 if (Op.getValueType() == MVT::f32 &&
5195 !Subtarget.hasFPCVT() &&
5196 !DAG.getTarget().Options.UnsafeFPMath) {
5198 // Twiddle input to make sure the low 11 bits are zero. (If this
5199 // is the case, we are guaranteed the value will fit into the 53 bit
5200 // mantissa of an IEEE double-precision value without rounding.)
5201 // If any of those low 11 bits were not zero originally, make sure
5202 // bit 12 (value 2048) is set instead, so that the final rounding
5203 // to single-precision gets the correct result.
5204 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5205 SINT, DAG.getConstant(2047, MVT::i64));
5206 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5207 Round, DAG.getConstant(2047, MVT::i64));
5208 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5209 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5210 Round, DAG.getConstant(-2048, MVT::i64));
5212 // However, we cannot use that value unconditionally: if the magnitude
5213 // of the input value is small, the bit-twiddling we did above might
5214 // end up visibly changing the output. Fortunately, in that case, we
5215 // don't need to twiddle bits since the original input will convert
5216 // exactly to double-precision floating-point already. Therefore,
5217 // construct a conditional to use the original value if the top 11
5218 // bits are all sign-bit copies, and use the rounded value computed
5220 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5221 SINT, DAG.getConstant(53, MVT::i32));
5222 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5223 Cond, DAG.getConstant(1, MVT::i64));
5224 Cond = DAG.getSetCC(dl, MVT::i32,
5225 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5227 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5230 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5231 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5233 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5234 FP = DAG.getNode(ISD::FP_ROUND, dl,
5235 MVT::f32, FP, DAG.getIntPtrConstant(0));
5239 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5240 "Unhandled INT_TO_FP type in custom expander!");
5241 // Since we only generate this in 64-bit mode, we can take advantage of
5242 // 64-bit registers. In particular, sign extend the input value into the
5243 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5244 // then lfd it and fcfid it.
5245 MachineFunction &MF = DAG.getMachineFunction();
5246 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5247 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5250 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5251 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5252 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5254 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5255 MachinePointerInfo::getFixedStack(FrameIdx),
5258 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5259 "Expected an i32 store");
5260 MachineMemOperand *MMO =
5261 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5262 MachineMemOperand::MOLoad, 4, 4);
5263 SDValue Ops[] = { Store, FIdx };
5264 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5265 PPCISD::LFIWZX : PPCISD::LFIWAX,
5266 dl, DAG.getVTList(MVT::f64, MVT::Other),
5267 Ops, MVT::i32, MMO);
5269 assert(Subtarget.isPPC64() &&
5270 "i32->FP without LFIWAX supported only on PPC64");
5272 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5273 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5275 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5278 // STD the extended value into the stack slot.
5279 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5280 MachinePointerInfo::getFixedStack(FrameIdx),
5283 // Load the value as a double.
5284 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5285 MachinePointerInfo::getFixedStack(FrameIdx),
5286 false, false, false, 0);
5289 // FCFID it and return it.
5290 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5291 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5292 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5296 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5297 SelectionDAG &DAG) const {
5300 The rounding mode is in bits 30:31 of FPSR, and has the following
5307 FLT_ROUNDS, on the other hand, expects the following:
5314 To perform the conversion, we do:
5315 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5318 MachineFunction &MF = DAG.getMachineFunction();
5319 EVT VT = Op.getValueType();
5320 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5322 // Save FP Control Word to register
5324 MVT::f64, // return register
5325 MVT::Glue // unused in this context
5327 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5329 // Save FP register to stack slot
5330 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5331 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5332 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5333 StackSlot, MachinePointerInfo(), false, false,0);
5335 // Load FP Control Word from low 32 bits of stack slot.
5336 SDValue Four = DAG.getConstant(4, PtrVT);
5337 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5338 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5339 false, false, false, 0);
5341 // Transform as necessary
5343 DAG.getNode(ISD::AND, dl, MVT::i32,
5344 CWD, DAG.getConstant(3, MVT::i32));
5346 DAG.getNode(ISD::SRL, dl, MVT::i32,
5347 DAG.getNode(ISD::AND, dl, MVT::i32,
5348 DAG.getNode(ISD::XOR, dl, MVT::i32,
5349 CWD, DAG.getConstant(3, MVT::i32)),
5350 DAG.getConstant(3, MVT::i32)),
5351 DAG.getConstant(1, MVT::i32));
5354 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5356 return DAG.getNode((VT.getSizeInBits() < 16 ?
5357 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5360 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5361 EVT VT = Op.getValueType();
5362 unsigned BitWidth = VT.getSizeInBits();
5364 assert(Op.getNumOperands() == 3 &&
5365 VT == Op.getOperand(1).getValueType() &&
5368 // Expand into a bunch of logical ops. Note that these ops
5369 // depend on the PPC behavior for oversized shift amounts.
5370 SDValue Lo = Op.getOperand(0);
5371 SDValue Hi = Op.getOperand(1);
5372 SDValue Amt = Op.getOperand(2);
5373 EVT AmtVT = Amt.getValueType();
5375 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5376 DAG.getConstant(BitWidth, AmtVT), Amt);
5377 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5378 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5379 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5380 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5381 DAG.getConstant(-BitWidth, AmtVT));
5382 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5383 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5384 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5385 SDValue OutOps[] = { OutLo, OutHi };
5386 return DAG.getMergeValues(OutOps, dl);
5389 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5390 EVT VT = Op.getValueType();
5392 unsigned BitWidth = VT.getSizeInBits();
5393 assert(Op.getNumOperands() == 3 &&
5394 VT == Op.getOperand(1).getValueType() &&
5397 // Expand into a bunch of logical ops. Note that these ops
5398 // depend on the PPC behavior for oversized shift amounts.
5399 SDValue Lo = Op.getOperand(0);
5400 SDValue Hi = Op.getOperand(1);
5401 SDValue Amt = Op.getOperand(2);
5402 EVT AmtVT = Amt.getValueType();
5404 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5405 DAG.getConstant(BitWidth, AmtVT), Amt);
5406 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5407 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5408 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5409 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5410 DAG.getConstant(-BitWidth, AmtVT));
5411 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5412 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5413 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5414 SDValue OutOps[] = { OutLo, OutHi };
5415 return DAG.getMergeValues(OutOps, dl);
5418 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5420 EVT VT = Op.getValueType();
5421 unsigned BitWidth = VT.getSizeInBits();
5422 assert(Op.getNumOperands() == 3 &&
5423 VT == Op.getOperand(1).getValueType() &&
5426 // Expand into a bunch of logical ops, followed by a select_cc.
5427 SDValue Lo = Op.getOperand(0);
5428 SDValue Hi = Op.getOperand(1);
5429 SDValue Amt = Op.getOperand(2);
5430 EVT AmtVT = Amt.getValueType();
5432 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5433 DAG.getConstant(BitWidth, AmtVT), Amt);
5434 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5435 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5436 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5437 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5438 DAG.getConstant(-BitWidth, AmtVT));
5439 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5440 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5441 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5442 Tmp4, Tmp6, ISD::SETLE);
5443 SDValue OutOps[] = { OutLo, OutHi };
5444 return DAG.getMergeValues(OutOps, dl);
5447 //===----------------------------------------------------------------------===//
5448 // Vector related lowering.
5451 /// BuildSplatI - Build a canonical splati of Val with an element size of
5452 /// SplatSize. Cast the result to VT.
5453 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5454 SelectionDAG &DAG, SDLoc dl) {
5455 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5457 static const EVT VTys[] = { // canonical VT to use for each size.
5458 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5461 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5463 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5467 EVT CanonicalVT = VTys[SplatSize-1];
5469 // Build a canonical splat for this value.
5470 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5471 SmallVector<SDValue, 8> Ops;
5472 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5473 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5474 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5477 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5478 /// specified intrinsic ID.
5479 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5480 SelectionDAG &DAG, SDLoc dl,
5481 EVT DestVT = MVT::Other) {
5482 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5483 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5484 DAG.getConstant(IID, MVT::i32), Op);
5487 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5488 /// specified intrinsic ID.
5489 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5490 SelectionDAG &DAG, SDLoc dl,
5491 EVT DestVT = MVT::Other) {
5492 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5493 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5494 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5497 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5498 /// specified intrinsic ID.
5499 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5500 SDValue Op2, SelectionDAG &DAG,
5501 SDLoc dl, EVT DestVT = MVT::Other) {
5502 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5503 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5504 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5508 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5509 /// amount. The result has the specified value type.
5510 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5511 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5512 // Force LHS/RHS to be the right type.
5513 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5514 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5517 for (unsigned i = 0; i != 16; ++i)
5519 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5520 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5523 // If this is a case we can't handle, return null and let the default
5524 // expansion code take care of it. If we CAN select this case, and if it
5525 // selects to a single instruction, return Op. Otherwise, if we can codegen
5526 // this case more efficiently than a constant pool load, lower it to the
5527 // sequence of ops that should be used.
5528 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5529 SelectionDAG &DAG) const {
5531 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5532 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5534 // Check if this is a splat of a constant value.
5535 APInt APSplatBits, APSplatUndef;
5536 unsigned SplatBitSize;
5538 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5539 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5542 unsigned SplatBits = APSplatBits.getZExtValue();
5543 unsigned SplatUndef = APSplatUndef.getZExtValue();
5544 unsigned SplatSize = SplatBitSize / 8;
5546 // First, handle single instruction cases.
5549 if (SplatBits == 0) {
5550 // Canonicalize all zero vectors to be v4i32.
5551 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5552 SDValue Z = DAG.getConstant(0, MVT::i32);
5553 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5554 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5559 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5560 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5562 if (SextVal >= -16 && SextVal <= 15)
5563 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5566 // Two instruction sequences.
5568 // If this value is in the range [-32,30] and is even, use:
5569 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5570 // If this value is in the range [17,31] and is odd, use:
5571 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5572 // If this value is in the range [-31,-17] and is odd, use:
5573 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5574 // Note the last two are three-instruction sequences.
5575 if (SextVal >= -32 && SextVal <= 31) {
5576 // To avoid having these optimizations undone by constant folding,
5577 // we convert to a pseudo that will be expanded later into one of
5579 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5580 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5581 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5582 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5583 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5584 if (VT == Op.getValueType())
5587 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5590 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5591 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5593 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5594 // Make -1 and vspltisw -1:
5595 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5597 // Make the VSLW intrinsic, computing 0x8000_0000.
5598 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5601 // xor by OnesV to invert it.
5602 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5603 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5606 // The remaining cases assume either big endian element order or
5607 // a splat-size that equates to the element size of the vector
5608 // to be built. An example that doesn't work for little endian is
5609 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5610 // and a vector element size of 16 bits. The code below will
5611 // produce the vector in big endian element order, which for little
5612 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5614 // For now, just avoid these optimizations in that case.
5615 // FIXME: Develop correct optimizations for LE with mismatched
5616 // splat and element sizes.
5618 if (Subtarget.isLittleEndian() &&
5619 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5622 // Check to see if this is a wide variety of vsplti*, binop self cases.
5623 static const signed char SplatCsts[] = {
5624 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5625 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5628 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5629 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5630 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5631 int i = SplatCsts[idx];
5633 // Figure out what shift amount will be used by altivec if shifted by i in
5635 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5637 // vsplti + shl self.
5638 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5639 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5640 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5641 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5642 Intrinsic::ppc_altivec_vslw
5644 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5645 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5648 // vsplti + srl self.
5649 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5650 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5651 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5652 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5653 Intrinsic::ppc_altivec_vsrw
5655 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5656 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5659 // vsplti + sra self.
5660 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5661 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5662 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5663 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5664 Intrinsic::ppc_altivec_vsraw
5666 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5667 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5670 // vsplti + rol self.
5671 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5672 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5673 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5674 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5675 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5676 Intrinsic::ppc_altivec_vrlw
5678 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5679 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5682 // t = vsplti c, result = vsldoi t, t, 1
5683 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5684 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5685 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5687 // t = vsplti c, result = vsldoi t, t, 2
5688 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5689 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5690 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5692 // t = vsplti c, result = vsldoi t, t, 3
5693 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5694 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5695 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5702 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5703 /// the specified operations to build the shuffle.
5704 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5705 SDValue RHS, SelectionDAG &DAG,
5707 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5708 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5709 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5712 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5724 if (OpNum == OP_COPY) {
5725 if (LHSID == (1*9+2)*9+3) return LHS;
5726 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5730 SDValue OpLHS, OpRHS;
5731 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5732 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5736 default: llvm_unreachable("Unknown i32 permute!");
5738 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5739 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5740 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5741 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5744 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5745 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5746 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5747 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5750 for (unsigned i = 0; i != 16; ++i)
5751 ShufIdxs[i] = (i&3)+0;
5754 for (unsigned i = 0; i != 16; ++i)
5755 ShufIdxs[i] = (i&3)+4;
5758 for (unsigned i = 0; i != 16; ++i)
5759 ShufIdxs[i] = (i&3)+8;
5762 for (unsigned i = 0; i != 16; ++i)
5763 ShufIdxs[i] = (i&3)+12;
5766 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5768 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5770 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5772 EVT VT = OpLHS.getValueType();
5773 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5774 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5775 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5776 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5779 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5780 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5781 /// return the code it can be lowered into. Worst case, it can always be
5782 /// lowered into a vperm.
5783 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5784 SelectionDAG &DAG) const {
5786 SDValue V1 = Op.getOperand(0);
5787 SDValue V2 = Op.getOperand(1);
5788 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5789 EVT VT = Op.getValueType();
5790 bool isLittleEndian = Subtarget.isLittleEndian();
5792 // Cases that are handled by instructions that take permute immediates
5793 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5794 // selected by the instruction selector.
5795 if (V2.getOpcode() == ISD::UNDEF) {
5796 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5797 PPC::isSplatShuffleMask(SVOp, 2) ||
5798 PPC::isSplatShuffleMask(SVOp, 4) ||
5799 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5800 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5801 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5802 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5803 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5804 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5805 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5806 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5807 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5812 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5813 // and produce a fixed permutation. If any of these match, do not lower to
5815 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5816 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5817 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5818 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5819 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5820 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5821 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5822 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5823 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5826 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5827 // perfect shuffle table to emit an optimal matching sequence.
5828 ArrayRef<int> PermMask = SVOp->getMask();
5830 unsigned PFIndexes[4];
5831 bool isFourElementShuffle = true;
5832 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5833 unsigned EltNo = 8; // Start out undef.
5834 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5835 if (PermMask[i*4+j] < 0)
5836 continue; // Undef, ignore it.
5838 unsigned ByteSource = PermMask[i*4+j];
5839 if ((ByteSource & 3) != j) {
5840 isFourElementShuffle = false;
5845 EltNo = ByteSource/4;
5846 } else if (EltNo != ByteSource/4) {
5847 isFourElementShuffle = false;
5851 PFIndexes[i] = EltNo;
5854 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5855 // perfect shuffle vector to determine if it is cost effective to do this as
5856 // discrete instructions, or whether we should use a vperm.
5857 // For now, we skip this for little endian until such time as we have a
5858 // little-endian perfect shuffle table.
5859 if (isFourElementShuffle && !isLittleEndian) {
5860 // Compute the index in the perfect shuffle table.
5861 unsigned PFTableIndex =
5862 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5864 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5865 unsigned Cost = (PFEntry >> 30);
5867 // Determining when to avoid vperm is tricky. Many things affect the cost
5868 // of vperm, particularly how many times the perm mask needs to be computed.
5869 // For example, if the perm mask can be hoisted out of a loop or is already
5870 // used (perhaps because there are multiple permutes with the same shuffle
5871 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5872 // the loop requires an extra register.
5874 // As a compromise, we only emit discrete instructions if the shuffle can be
5875 // generated in 3 or fewer operations. When we have loop information
5876 // available, if this block is within a loop, we should avoid using vperm
5877 // for 3-operation perms and use a constant pool load instead.
5879 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5882 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5883 // vector that will get spilled to the constant pool.
5884 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5886 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5887 // that it is in input element units, not in bytes. Convert now.
5889 // For little endian, the order of the input vectors is reversed, and
5890 // the permutation mask is complemented with respect to 31. This is
5891 // necessary to produce proper semantics with the big-endian-biased vperm
5893 EVT EltVT = V1.getValueType().getVectorElementType();
5894 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5896 SmallVector<SDValue, 16> ResultMask;
5897 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5898 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5900 for (unsigned j = 0; j != BytesPerElement; ++j)
5902 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5905 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5909 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5912 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5915 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5919 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5920 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5921 /// information about the intrinsic.
5922 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5924 unsigned IntrinsicID =
5925 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5928 switch (IntrinsicID) {
5929 default: return false;
5930 // Comparison predicates.
5931 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5932 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5933 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5934 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5935 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5936 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5937 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5938 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5939 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5940 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5941 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5942 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5943 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5945 // Normal Comparisons.
5946 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5947 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5948 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5949 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5950 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5951 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5952 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5953 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5954 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5955 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5956 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5957 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5958 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5963 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5964 /// lower, do it, otherwise return null.
5965 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5966 SelectionDAG &DAG) const {
5967 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5968 // opcode number of the comparison.
5972 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5973 return SDValue(); // Don't custom lower most intrinsics.
5975 // If this is a non-dot comparison, make the VCMP node and we are done.
5977 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5978 Op.getOperand(1), Op.getOperand(2),
5979 DAG.getConstant(CompareOpc, MVT::i32));
5980 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5983 // Create the PPCISD altivec 'dot' comparison node.
5985 Op.getOperand(2), // LHS
5986 Op.getOperand(3), // RHS
5987 DAG.getConstant(CompareOpc, MVT::i32)
5989 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5990 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5992 // Now that we have the comparison, emit a copy from the CR to a GPR.
5993 // This is flagged to the above dot comparison.
5994 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5995 DAG.getRegister(PPC::CR6, MVT::i32),
5996 CompNode.getValue(1));
5998 // Unpack the result based on how the target uses it.
5999 unsigned BitNo; // Bit # of CR6.
6000 bool InvertBit; // Invert result?
6001 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
6002 default: // Can't happen, don't crash on invalid number though.
6003 case 0: // Return the value of the EQ bit of CR6.
6004 BitNo = 0; InvertBit = false;
6006 case 1: // Return the inverted value of the EQ bit of CR6.
6007 BitNo = 0; InvertBit = true;
6009 case 2: // Return the value of the LT bit of CR6.
6010 BitNo = 2; InvertBit = false;
6012 case 3: // Return the inverted value of the LT bit of CR6.
6013 BitNo = 2; InvertBit = true;
6017 // Shift the bit into the low position.
6018 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6019 DAG.getConstant(8-(3-BitNo), MVT::i32));
6021 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6022 DAG.getConstant(1, MVT::i32));
6024 // If we are supposed to, toggle the bit.
6026 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6027 DAG.getConstant(1, MVT::i32));
6031 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6032 SelectionDAG &DAG) const {
6034 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6035 // instructions), but for smaller types, we need to first extend up to v2i32
6036 // before doing going farther.
6037 if (Op.getValueType() == MVT::v2i64) {
6038 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6039 if (ExtVT != MVT::v2i32) {
6040 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6041 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6042 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6043 ExtVT.getVectorElementType(), 4)));
6044 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6045 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6046 DAG.getValueType(MVT::v2i32));
6055 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6056 SelectionDAG &DAG) const {
6058 // Create a stack slot that is 16-byte aligned.
6059 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6060 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6061 EVT PtrVT = getPointerTy();
6062 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6064 // Store the input value into Value#0 of the stack slot.
6065 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6066 Op.getOperand(0), FIdx, MachinePointerInfo(),
6069 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6070 false, false, false, 0);
6073 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6075 if (Op.getValueType() == MVT::v4i32) {
6076 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6078 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6079 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6081 SDValue RHSSwap = // = vrlw RHS, 16
6082 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6084 // Shrinkify inputs to v8i16.
6085 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6086 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6087 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6089 // Low parts multiplied together, generating 32-bit results (we ignore the
6091 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6092 LHS, RHS, DAG, dl, MVT::v4i32);
6094 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6095 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6096 // Shift the high parts up 16 bits.
6097 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6099 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6100 } else if (Op.getValueType() == MVT::v8i16) {
6101 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6103 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6105 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6106 LHS, RHS, Zero, DAG, dl);
6107 } else if (Op.getValueType() == MVT::v16i8) {
6108 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6109 bool isLittleEndian = Subtarget.isLittleEndian();
6111 // Multiply the even 8-bit parts, producing 16-bit sums.
6112 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6113 LHS, RHS, DAG, dl, MVT::v8i16);
6114 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6116 // Multiply the odd 8-bit parts, producing 16-bit sums.
6117 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6118 LHS, RHS, DAG, dl, MVT::v8i16);
6119 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6121 // Merge the results together. Because vmuleub and vmuloub are
6122 // instructions with a big-endian bias, we must reverse the
6123 // element numbering and reverse the meaning of "odd" and "even"
6124 // when generating little endian code.
6126 for (unsigned i = 0; i != 8; ++i) {
6127 if (isLittleEndian) {
6129 Ops[i*2+1] = 2*i+16;
6132 Ops[i*2+1] = 2*i+1+16;
6136 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6138 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6140 llvm_unreachable("Unknown mul to lower!");
6144 /// LowerOperation - Provide custom lowering hooks for some operations.
6146 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6147 switch (Op.getOpcode()) {
6148 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6149 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6150 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6151 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6152 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6153 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6154 case ISD::SETCC: return LowerSETCC(Op, DAG);
6155 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6156 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6158 return LowerVASTART(Op, DAG, Subtarget);
6161 return LowerVAARG(Op, DAG, Subtarget);
6164 return LowerVACOPY(Op, DAG, Subtarget);
6166 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6167 case ISD::DYNAMIC_STACKALLOC:
6168 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6170 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6171 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6173 case ISD::LOAD: return LowerLOAD(Op, DAG);
6174 case ISD::STORE: return LowerSTORE(Op, DAG);
6175 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6176 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6177 case ISD::FP_TO_UINT:
6178 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6180 case ISD::UINT_TO_FP:
6181 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6182 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6184 // Lower 64-bit shifts.
6185 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6186 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6187 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6189 // Vector-related lowering.
6190 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6191 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6192 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6193 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6194 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6195 case ISD::MUL: return LowerMUL(Op, DAG);
6197 // For counter-based loop handling.
6198 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6200 // Frame & Return address.
6201 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6202 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6206 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6207 SmallVectorImpl<SDValue>&Results,
6208 SelectionDAG &DAG) const {
6209 const TargetMachine &TM = getTargetMachine();
6211 switch (N->getOpcode()) {
6213 llvm_unreachable("Do not know how to custom type legalize this operation!");
6214 case ISD::INTRINSIC_W_CHAIN: {
6215 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6216 Intrinsic::ppc_is_decremented_ctr_nonzero)
6219 assert(N->getValueType(0) == MVT::i1 &&
6220 "Unexpected result type for CTR decrement intrinsic");
6221 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6222 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6223 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6226 Results.push_back(NewInt);
6227 Results.push_back(NewInt.getValue(1));
6231 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6232 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6235 EVT VT = N->getValueType(0);
6237 if (VT == MVT::i64) {
6238 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6240 Results.push_back(NewNode);
6241 Results.push_back(NewNode.getValue(1));
6245 case ISD::FP_ROUND_INREG: {
6246 assert(N->getValueType(0) == MVT::ppcf128);
6247 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6248 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6249 MVT::f64, N->getOperand(0),
6250 DAG.getIntPtrConstant(0));
6251 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6252 MVT::f64, N->getOperand(0),
6253 DAG.getIntPtrConstant(1));
6255 // Add the two halves of the long double in round-to-zero mode.
6256 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6258 // We know the low half is about to be thrown away, so just use something
6260 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6264 case ISD::FP_TO_SINT:
6265 // LowerFP_TO_INT() can only handle f32 and f64.
6266 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6268 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6274 //===----------------------------------------------------------------------===//
6275 // Other Lowering Code
6276 //===----------------------------------------------------------------------===//
6279 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6280 bool is64bit, unsigned BinOpcode) const {
6281 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6282 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6284 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6285 MachineFunction *F = BB->getParent();
6286 MachineFunction::iterator It = BB;
6289 unsigned dest = MI->getOperand(0).getReg();
6290 unsigned ptrA = MI->getOperand(1).getReg();
6291 unsigned ptrB = MI->getOperand(2).getReg();
6292 unsigned incr = MI->getOperand(3).getReg();
6293 DebugLoc dl = MI->getDebugLoc();
6295 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6296 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6297 F->insert(It, loopMBB);
6298 F->insert(It, exitMBB);
6299 exitMBB->splice(exitMBB->begin(), BB,
6300 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6301 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6303 MachineRegisterInfo &RegInfo = F->getRegInfo();
6304 unsigned TmpReg = (!BinOpcode) ? incr :
6305 RegInfo.createVirtualRegister(
6306 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6307 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6311 // fallthrough --> loopMBB
6312 BB->addSuccessor(loopMBB);
6315 // l[wd]arx dest, ptr
6316 // add r0, dest, incr
6317 // st[wd]cx. r0, ptr
6319 // fallthrough --> exitMBB
6321 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6322 .addReg(ptrA).addReg(ptrB);
6324 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6325 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6326 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6327 BuildMI(BB, dl, TII->get(PPC::BCC))
6328 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6329 BB->addSuccessor(loopMBB);
6330 BB->addSuccessor(exitMBB);
6339 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6340 MachineBasicBlock *BB,
6341 bool is8bit, // operation
6342 unsigned BinOpcode) const {
6343 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6344 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6345 // In 64 bit mode we have to use 64 bits for addresses, even though the
6346 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6347 // registers without caring whether they're 32 or 64, but here we're
6348 // doing actual arithmetic on the addresses.
6349 bool is64bit = Subtarget.isPPC64();
6350 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6352 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6353 MachineFunction *F = BB->getParent();
6354 MachineFunction::iterator It = BB;
6357 unsigned dest = MI->getOperand(0).getReg();
6358 unsigned ptrA = MI->getOperand(1).getReg();
6359 unsigned ptrB = MI->getOperand(2).getReg();
6360 unsigned incr = MI->getOperand(3).getReg();
6361 DebugLoc dl = MI->getDebugLoc();
6363 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6364 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6365 F->insert(It, loopMBB);
6366 F->insert(It, exitMBB);
6367 exitMBB->splice(exitMBB->begin(), BB,
6368 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6369 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6371 MachineRegisterInfo &RegInfo = F->getRegInfo();
6372 const TargetRegisterClass *RC =
6373 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6374 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6375 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6376 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6377 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6378 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6379 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6380 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6381 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6382 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6383 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6384 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6385 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6387 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6391 // fallthrough --> loopMBB
6392 BB->addSuccessor(loopMBB);
6394 // The 4-byte load must be aligned, while a char or short may be
6395 // anywhere in the word. Hence all this nasty bookkeeping code.
6396 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6397 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6398 // xori shift, shift1, 24 [16]
6399 // rlwinm ptr, ptr1, 0, 0, 29
6400 // slw incr2, incr, shift
6401 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6402 // slw mask, mask2, shift
6404 // lwarx tmpDest, ptr
6405 // add tmp, tmpDest, incr2
6406 // andc tmp2, tmpDest, mask
6407 // and tmp3, tmp, mask
6408 // or tmp4, tmp3, tmp2
6411 // fallthrough --> exitMBB
6412 // srw dest, tmpDest, shift
6413 if (ptrA != ZeroReg) {
6414 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6415 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6416 .addReg(ptrA).addReg(ptrB);
6420 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6421 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6422 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6423 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6425 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6426 .addReg(Ptr1Reg).addImm(0).addImm(61);
6428 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6429 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6430 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6431 .addReg(incr).addReg(ShiftReg);
6433 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6435 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6436 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6438 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6439 .addReg(Mask2Reg).addReg(ShiftReg);
6442 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6443 .addReg(ZeroReg).addReg(PtrReg);
6445 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6446 .addReg(Incr2Reg).addReg(TmpDestReg);
6447 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6448 .addReg(TmpDestReg).addReg(MaskReg);
6449 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6450 .addReg(TmpReg).addReg(MaskReg);
6451 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6452 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6453 BuildMI(BB, dl, TII->get(PPC::STWCX))
6454 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6455 BuildMI(BB, dl, TII->get(PPC::BCC))
6456 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6457 BB->addSuccessor(loopMBB);
6458 BB->addSuccessor(exitMBB);
6463 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6468 llvm::MachineBasicBlock*
6469 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6470 MachineBasicBlock *MBB) const {
6471 DebugLoc DL = MI->getDebugLoc();
6472 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6474 MachineFunction *MF = MBB->getParent();
6475 MachineRegisterInfo &MRI = MF->getRegInfo();
6477 const BasicBlock *BB = MBB->getBasicBlock();
6478 MachineFunction::iterator I = MBB;
6482 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6483 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6485 unsigned DstReg = MI->getOperand(0).getReg();
6486 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6487 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6488 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6489 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6491 MVT PVT = getPointerTy();
6492 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6493 "Invalid Pointer Size!");
6494 // For v = setjmp(buf), we generate
6497 // SjLjSetup mainMBB
6503 // buf[LabelOffset] = LR
6507 // v = phi(main, restore)
6510 MachineBasicBlock *thisMBB = MBB;
6511 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6512 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6513 MF->insert(I, mainMBB);
6514 MF->insert(I, sinkMBB);
6516 MachineInstrBuilder MIB;
6518 // Transfer the remainder of BB and its successor edges to sinkMBB.
6519 sinkMBB->splice(sinkMBB->begin(), MBB,
6520 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6521 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6523 // Note that the structure of the jmp_buf used here is not compatible
6524 // with that used by libc, and is not designed to be. Specifically, it
6525 // stores only those 'reserved' registers that LLVM does not otherwise
6526 // understand how to spill. Also, by convention, by the time this
6527 // intrinsic is called, Clang has already stored the frame address in the
6528 // first slot of the buffer and stack address in the third. Following the
6529 // X86 target code, we'll store the jump address in the second slot. We also
6530 // need to save the TOC pointer (R2) to handle jumps between shared
6531 // libraries, and that will be stored in the fourth slot. The thread
6532 // identifier (R13) is not affected.
6535 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6536 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6537 const int64_t BPOffset = 4 * PVT.getStoreSize();
6539 // Prepare IP either in reg.
6540 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6541 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6542 unsigned BufReg = MI->getOperand(1).getReg();
6544 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6545 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6549 MIB.setMemRefs(MMOBegin, MMOEnd);
6552 // Naked functions never have a base pointer, and so we use r1. For all
6553 // other functions, this decision must be delayed until during PEI.
6555 if (MF->getFunction()->getAttributes().hasAttribute(
6556 AttributeSet::FunctionIndex, Attribute::Naked))
6557 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6559 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6561 MIB = BuildMI(*thisMBB, MI, DL,
6562 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6566 MIB.setMemRefs(MMOBegin, MMOEnd);
6569 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6570 const PPCRegisterInfo *TRI =
6571 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6572 MIB.addRegMask(TRI->getNoPreservedMask());
6574 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6576 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6578 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6580 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6581 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6585 MIB = BuildMI(mainMBB, DL,
6586 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6589 if (Subtarget.isPPC64()) {
6590 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6592 .addImm(LabelOffset)
6595 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6597 .addImm(LabelOffset)
6601 MIB.setMemRefs(MMOBegin, MMOEnd);
6603 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6604 mainMBB->addSuccessor(sinkMBB);
6607 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6608 TII->get(PPC::PHI), DstReg)
6609 .addReg(mainDstReg).addMBB(mainMBB)
6610 .addReg(restoreDstReg).addMBB(thisMBB);
6612 MI->eraseFromParent();
6617 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6618 MachineBasicBlock *MBB) const {
6619 DebugLoc DL = MI->getDebugLoc();
6620 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6622 MachineFunction *MF = MBB->getParent();
6623 MachineRegisterInfo &MRI = MF->getRegInfo();
6626 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6627 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6629 MVT PVT = getPointerTy();
6630 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6631 "Invalid Pointer Size!");
6633 const TargetRegisterClass *RC =
6634 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6635 unsigned Tmp = MRI.createVirtualRegister(RC);
6636 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6637 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6638 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6639 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6641 MachineInstrBuilder MIB;
6643 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6644 const int64_t SPOffset = 2 * PVT.getStoreSize();
6645 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6646 const int64_t BPOffset = 4 * PVT.getStoreSize();
6648 unsigned BufReg = MI->getOperand(0).getReg();
6650 // Reload FP (the jumped-to function may not have had a
6651 // frame pointer, and if so, then its r31 will be restored
6653 if (PVT == MVT::i64) {
6654 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6658 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6662 MIB.setMemRefs(MMOBegin, MMOEnd);
6665 if (PVT == MVT::i64) {
6666 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6667 .addImm(LabelOffset)
6670 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6671 .addImm(LabelOffset)
6674 MIB.setMemRefs(MMOBegin, MMOEnd);
6677 if (PVT == MVT::i64) {
6678 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6682 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6686 MIB.setMemRefs(MMOBegin, MMOEnd);
6689 if (PVT == MVT::i64) {
6690 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6694 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6698 MIB.setMemRefs(MMOBegin, MMOEnd);
6701 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6702 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6706 MIB.setMemRefs(MMOBegin, MMOEnd);
6710 BuildMI(*MBB, MI, DL,
6711 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6712 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6714 MI->eraseFromParent();
6719 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6720 MachineBasicBlock *BB) const {
6721 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6722 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6723 return emitEHSjLjSetJmp(MI, BB);
6724 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6725 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6726 return emitEHSjLjLongJmp(MI, BB);
6729 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6731 // To "insert" these instructions we actually have to insert their
6732 // control-flow patterns.
6733 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6734 MachineFunction::iterator It = BB;
6737 MachineFunction *F = BB->getParent();
6739 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6740 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6741 MI->getOpcode() == PPC::SELECT_I4 ||
6742 MI->getOpcode() == PPC::SELECT_I8)) {
6743 SmallVector<MachineOperand, 2> Cond;
6744 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6745 MI->getOpcode() == PPC::SELECT_CC_I8)
6746 Cond.push_back(MI->getOperand(4));
6748 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6749 Cond.push_back(MI->getOperand(1));
6751 DebugLoc dl = MI->getDebugLoc();
6752 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6753 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6754 Cond, MI->getOperand(2).getReg(),
6755 MI->getOperand(3).getReg());
6756 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6757 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6758 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6759 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6760 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6761 MI->getOpcode() == PPC::SELECT_I4 ||
6762 MI->getOpcode() == PPC::SELECT_I8 ||
6763 MI->getOpcode() == PPC::SELECT_F4 ||
6764 MI->getOpcode() == PPC::SELECT_F8 ||
6765 MI->getOpcode() == PPC::SELECT_VRRC) {
6766 // The incoming instruction knows the destination vreg to set, the
6767 // condition code register to branch on, the true/false values to
6768 // select between, and a branch opcode to use.
6773 // cmpTY ccX, r1, r2
6775 // fallthrough --> copy0MBB
6776 MachineBasicBlock *thisMBB = BB;
6777 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6778 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6779 DebugLoc dl = MI->getDebugLoc();
6780 F->insert(It, copy0MBB);
6781 F->insert(It, sinkMBB);
6783 // Transfer the remainder of BB and its successor edges to sinkMBB.
6784 sinkMBB->splice(sinkMBB->begin(), BB,
6785 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6786 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6788 // Next, add the true and fallthrough blocks as its successors.
6789 BB->addSuccessor(copy0MBB);
6790 BB->addSuccessor(sinkMBB);
6792 if (MI->getOpcode() == PPC::SELECT_I4 ||
6793 MI->getOpcode() == PPC::SELECT_I8 ||
6794 MI->getOpcode() == PPC::SELECT_F4 ||
6795 MI->getOpcode() == PPC::SELECT_F8 ||
6796 MI->getOpcode() == PPC::SELECT_VRRC) {
6797 BuildMI(BB, dl, TII->get(PPC::BC))
6798 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6800 unsigned SelectPred = MI->getOperand(4).getImm();
6801 BuildMI(BB, dl, TII->get(PPC::BCC))
6802 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6806 // %FalseValue = ...
6807 // # fallthrough to sinkMBB
6810 // Update machine-CFG edges
6811 BB->addSuccessor(sinkMBB);
6814 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6817 BuildMI(*BB, BB->begin(), dl,
6818 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6819 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6820 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6822 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6823 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6824 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6825 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6826 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6827 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6828 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6829 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6831 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6832 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6833 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6834 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6835 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6836 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6837 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6838 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6840 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6841 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6842 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6843 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6844 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6845 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6846 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6847 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6849 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6850 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6851 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6852 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6853 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6854 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6855 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6856 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6858 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6859 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6860 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6861 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6862 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6863 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6864 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6865 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6867 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6868 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6869 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6870 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6871 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6872 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6873 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6874 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6876 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6877 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6878 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6879 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6880 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6881 BB = EmitAtomicBinary(MI, BB, false, 0);
6882 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6883 BB = EmitAtomicBinary(MI, BB, true, 0);
6885 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6886 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6887 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6889 unsigned dest = MI->getOperand(0).getReg();
6890 unsigned ptrA = MI->getOperand(1).getReg();
6891 unsigned ptrB = MI->getOperand(2).getReg();
6892 unsigned oldval = MI->getOperand(3).getReg();
6893 unsigned newval = MI->getOperand(4).getReg();
6894 DebugLoc dl = MI->getDebugLoc();
6896 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6897 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6898 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6899 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6900 F->insert(It, loop1MBB);
6901 F->insert(It, loop2MBB);
6902 F->insert(It, midMBB);
6903 F->insert(It, exitMBB);
6904 exitMBB->splice(exitMBB->begin(), BB,
6905 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6906 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6910 // fallthrough --> loopMBB
6911 BB->addSuccessor(loop1MBB);
6914 // l[wd]arx dest, ptr
6915 // cmp[wd] dest, oldval
6918 // st[wd]cx. newval, ptr
6922 // st[wd]cx. dest, ptr
6925 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6926 .addReg(ptrA).addReg(ptrB);
6927 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6928 .addReg(oldval).addReg(dest);
6929 BuildMI(BB, dl, TII->get(PPC::BCC))
6930 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6931 BB->addSuccessor(loop2MBB);
6932 BB->addSuccessor(midMBB);
6935 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6936 .addReg(newval).addReg(ptrA).addReg(ptrB);
6937 BuildMI(BB, dl, TII->get(PPC::BCC))
6938 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6939 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6940 BB->addSuccessor(loop1MBB);
6941 BB->addSuccessor(exitMBB);
6944 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6945 .addReg(dest).addReg(ptrA).addReg(ptrB);
6946 BB->addSuccessor(exitMBB);
6951 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6952 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6953 // We must use 64-bit registers for addresses when targeting 64-bit,
6954 // since we're actually doing arithmetic on them. Other registers
6956 bool is64bit = Subtarget.isPPC64();
6957 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6959 unsigned dest = MI->getOperand(0).getReg();
6960 unsigned ptrA = MI->getOperand(1).getReg();
6961 unsigned ptrB = MI->getOperand(2).getReg();
6962 unsigned oldval = MI->getOperand(3).getReg();
6963 unsigned newval = MI->getOperand(4).getReg();
6964 DebugLoc dl = MI->getDebugLoc();
6966 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6967 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6968 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6969 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6970 F->insert(It, loop1MBB);
6971 F->insert(It, loop2MBB);
6972 F->insert(It, midMBB);
6973 F->insert(It, exitMBB);
6974 exitMBB->splice(exitMBB->begin(), BB,
6975 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6976 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6978 MachineRegisterInfo &RegInfo = F->getRegInfo();
6979 const TargetRegisterClass *RC =
6980 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6981 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6982 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6983 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6984 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6985 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6986 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6987 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6988 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6989 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6990 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6991 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6992 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6993 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6994 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6996 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6997 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
7000 // fallthrough --> loopMBB
7001 BB->addSuccessor(loop1MBB);
7003 // The 4-byte load must be aligned, while a char or short may be
7004 // anywhere in the word. Hence all this nasty bookkeeping code.
7005 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7006 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7007 // xori shift, shift1, 24 [16]
7008 // rlwinm ptr, ptr1, 0, 0, 29
7009 // slw newval2, newval, shift
7010 // slw oldval2, oldval,shift
7011 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7012 // slw mask, mask2, shift
7013 // and newval3, newval2, mask
7014 // and oldval3, oldval2, mask
7016 // lwarx tmpDest, ptr
7017 // and tmp, tmpDest, mask
7018 // cmpw tmp, oldval3
7021 // andc tmp2, tmpDest, mask
7022 // or tmp4, tmp2, newval3
7027 // stwcx. tmpDest, ptr
7029 // srw dest, tmpDest, shift
7030 if (ptrA != ZeroReg) {
7031 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7032 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7033 .addReg(ptrA).addReg(ptrB);
7037 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7038 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7039 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7040 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7042 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7043 .addReg(Ptr1Reg).addImm(0).addImm(61);
7045 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7046 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7047 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7048 .addReg(newval).addReg(ShiftReg);
7049 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7050 .addReg(oldval).addReg(ShiftReg);
7052 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7054 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7055 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7056 .addReg(Mask3Reg).addImm(65535);
7058 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7059 .addReg(Mask2Reg).addReg(ShiftReg);
7060 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7061 .addReg(NewVal2Reg).addReg(MaskReg);
7062 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7063 .addReg(OldVal2Reg).addReg(MaskReg);
7066 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7067 .addReg(ZeroReg).addReg(PtrReg);
7068 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7069 .addReg(TmpDestReg).addReg(MaskReg);
7070 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7071 .addReg(TmpReg).addReg(OldVal3Reg);
7072 BuildMI(BB, dl, TII->get(PPC::BCC))
7073 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7074 BB->addSuccessor(loop2MBB);
7075 BB->addSuccessor(midMBB);
7078 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7079 .addReg(TmpDestReg).addReg(MaskReg);
7080 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7081 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7082 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7083 .addReg(ZeroReg).addReg(PtrReg);
7084 BuildMI(BB, dl, TII->get(PPC::BCC))
7085 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7086 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7087 BB->addSuccessor(loop1MBB);
7088 BB->addSuccessor(exitMBB);
7091 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7092 .addReg(ZeroReg).addReg(PtrReg);
7093 BB->addSuccessor(exitMBB);
7098 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7100 } else if (MI->getOpcode() == PPC::FADDrtz) {
7101 // This pseudo performs an FADD with rounding mode temporarily forced
7102 // to round-to-zero. We emit this via custom inserter since the FPSCR
7103 // is not modeled at the SelectionDAG level.
7104 unsigned Dest = MI->getOperand(0).getReg();
7105 unsigned Src1 = MI->getOperand(1).getReg();
7106 unsigned Src2 = MI->getOperand(2).getReg();
7107 DebugLoc dl = MI->getDebugLoc();
7109 MachineRegisterInfo &RegInfo = F->getRegInfo();
7110 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7112 // Save FPSCR value.
7113 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7115 // Set rounding mode to round-to-zero.
7116 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7117 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7119 // Perform addition.
7120 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7122 // Restore FPSCR value.
7123 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7124 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7125 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7126 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7127 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7128 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7129 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7130 PPC::ANDIo8 : PPC::ANDIo;
7131 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7132 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7134 MachineRegisterInfo &RegInfo = F->getRegInfo();
7135 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7136 &PPC::GPRCRegClass :
7137 &PPC::G8RCRegClass);
7139 DebugLoc dl = MI->getDebugLoc();
7140 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7141 .addReg(MI->getOperand(1).getReg()).addImm(1);
7142 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7143 MI->getOperand(0).getReg())
7144 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7146 llvm_unreachable("Unexpected instr type to insert");
7149 MI->eraseFromParent(); // The pseudo instruction is gone now.
7153 //===----------------------------------------------------------------------===//
7154 // Target Optimization Hooks
7155 //===----------------------------------------------------------------------===//
7157 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7158 DAGCombinerInfo &DCI) const {
7159 if (DCI.isAfterLegalizeVectorOps())
7162 EVT VT = Op.getValueType();
7164 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7165 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7166 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7167 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7169 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7170 // For the reciprocal, we need to find the zero of the function:
7171 // F(X) = A X - 1 [which has a zero at X = 1/A]
7173 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7174 // does not require additional intermediate precision]
7176 // Convergence is quadratic, so we essentially double the number of digits
7177 // correct after every iteration. The minimum architected relative
7178 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7179 // 23 digits and double has 52 digits.
7180 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7181 if (VT.getScalarType() == MVT::f64)
7184 SelectionDAG &DAG = DCI.DAG;
7188 DAG.getConstantFP(1.0, VT.getScalarType());
7189 if (VT.isVector()) {
7190 assert(VT.getVectorNumElements() == 4 &&
7191 "Unknown vector type");
7192 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7193 FPOne, FPOne, FPOne, FPOne);
7196 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7197 DCI.AddToWorklist(Est.getNode());
7199 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7200 for (int i = 0; i < Iterations; ++i) {
7201 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7202 DCI.AddToWorklist(NewEst.getNode());
7204 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7205 DCI.AddToWorklist(NewEst.getNode());
7207 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7208 DCI.AddToWorklist(NewEst.getNode());
7210 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7211 DCI.AddToWorklist(Est.getNode());
7220 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7221 DAGCombinerInfo &DCI) const {
7222 if (DCI.isAfterLegalizeVectorOps())
7225 EVT VT = Op.getValueType();
7227 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7228 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7229 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7230 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7232 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7233 // For the reciprocal sqrt, we need to find the zero of the function:
7234 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7236 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7237 // As a result, we precompute A/2 prior to the iteration loop.
7239 // Convergence is quadratic, so we essentially double the number of digits
7240 // correct after every iteration. The minimum architected relative
7241 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7242 // 23 digits and double has 52 digits.
7243 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7244 if (VT.getScalarType() == MVT::f64)
7247 SelectionDAG &DAG = DCI.DAG;
7250 SDValue FPThreeHalves =
7251 DAG.getConstantFP(1.5, VT.getScalarType());
7252 if (VT.isVector()) {
7253 assert(VT.getVectorNumElements() == 4 &&
7254 "Unknown vector type");
7255 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7256 FPThreeHalves, FPThreeHalves,
7257 FPThreeHalves, FPThreeHalves);
7260 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7261 DCI.AddToWorklist(Est.getNode());
7263 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7264 // this entire sequence requires only one FP constant.
7265 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7266 DCI.AddToWorklist(HalfArg.getNode());
7268 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7269 DCI.AddToWorklist(HalfArg.getNode());
7271 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7272 for (int i = 0; i < Iterations; ++i) {
7273 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7274 DCI.AddToWorklist(NewEst.getNode());
7276 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7277 DCI.AddToWorklist(NewEst.getNode());
7279 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7280 DCI.AddToWorklist(NewEst.getNode());
7282 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7283 DCI.AddToWorklist(Est.getNode());
7292 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7293 // not enforce equality of the chain operands.
7294 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7295 unsigned Bytes, int Dist,
7296 SelectionDAG &DAG) {
7297 EVT VT = LS->getMemoryVT();
7298 if (VT.getSizeInBits() / 8 != Bytes)
7301 SDValue Loc = LS->getBasePtr();
7302 SDValue BaseLoc = Base->getBasePtr();
7303 if (Loc.getOpcode() == ISD::FrameIndex) {
7304 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7306 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7307 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7308 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7309 int FS = MFI->getObjectSize(FI);
7310 int BFS = MFI->getObjectSize(BFI);
7311 if (FS != BFS || FS != (int)Bytes) return false;
7312 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7316 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7317 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7320 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7321 const GlobalValue *GV1 = nullptr;
7322 const GlobalValue *GV2 = nullptr;
7323 int64_t Offset1 = 0;
7324 int64_t Offset2 = 0;
7325 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7326 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7327 if (isGA1 && isGA2 && GV1 == GV2)
7328 return Offset1 == (Offset2 + Dist*Bytes);
7332 // Return true is there is a nearyby consecutive load to the one provided
7333 // (regardless of alignment). We search up and down the chain, looking though
7334 // token factors and other loads (but nothing else). As a result, a true
7335 // results indicates that it is safe to create a new consecutive load adjacent
7336 // to the load provided.
7337 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7338 SDValue Chain = LD->getChain();
7339 EVT VT = LD->getMemoryVT();
7341 SmallSet<SDNode *, 16> LoadRoots;
7342 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7343 SmallSet<SDNode *, 16> Visited;
7345 // First, search up the chain, branching to follow all token-factor operands.
7346 // If we find a consecutive load, then we're done, otherwise, record all
7347 // nodes just above the top-level loads and token factors.
7348 while (!Queue.empty()) {
7349 SDNode *ChainNext = Queue.pop_back_val();
7350 if (!Visited.insert(ChainNext))
7353 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7354 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7357 if (!Visited.count(ChainLD->getChain().getNode()))
7358 Queue.push_back(ChainLD->getChain().getNode());
7359 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7360 for (SDNode::op_iterator O = ChainNext->op_begin(),
7361 OE = ChainNext->op_end(); O != OE; ++O)
7362 if (!Visited.count(O->getNode()))
7363 Queue.push_back(O->getNode());
7365 LoadRoots.insert(ChainNext);
7368 // Second, search down the chain, starting from the top-level nodes recorded
7369 // in the first phase. These top-level nodes are the nodes just above all
7370 // loads and token factors. Starting with their uses, recursively look though
7371 // all loads (just the chain uses) and token factors to find a consecutive
7376 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7377 IE = LoadRoots.end(); I != IE; ++I) {
7378 Queue.push_back(*I);
7380 while (!Queue.empty()) {
7381 SDNode *LoadRoot = Queue.pop_back_val();
7382 if (!Visited.insert(LoadRoot))
7385 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7386 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7389 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7390 UE = LoadRoot->use_end(); UI != UE; ++UI)
7391 if (((isa<LoadSDNode>(*UI) &&
7392 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7393 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7394 Queue.push_back(*UI);
7401 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7402 DAGCombinerInfo &DCI) const {
7403 SelectionDAG &DAG = DCI.DAG;
7406 assert(Subtarget.useCRBits() &&
7407 "Expecting to be tracking CR bits");
7408 // If we're tracking CR bits, we need to be careful that we don't have:
7409 // trunc(binary-ops(zext(x), zext(y)))
7411 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7412 // such that we're unnecessarily moving things into GPRs when it would be
7413 // better to keep them in CR bits.
7415 // Note that trunc here can be an actual i1 trunc, or can be the effective
7416 // truncation that comes from a setcc or select_cc.
7417 if (N->getOpcode() == ISD::TRUNCATE &&
7418 N->getValueType(0) != MVT::i1)
7421 if (N->getOperand(0).getValueType() != MVT::i32 &&
7422 N->getOperand(0).getValueType() != MVT::i64)
7425 if (N->getOpcode() == ISD::SETCC ||
7426 N->getOpcode() == ISD::SELECT_CC) {
7427 // If we're looking at a comparison, then we need to make sure that the
7428 // high bits (all except for the first) don't matter the result.
7430 cast<CondCodeSDNode>(N->getOperand(
7431 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7432 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7434 if (ISD::isSignedIntSetCC(CC)) {
7435 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7436 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7438 } else if (ISD::isUnsignedIntSetCC(CC)) {
7439 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7440 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7441 !DAG.MaskedValueIsZero(N->getOperand(1),
7442 APInt::getHighBitsSet(OpBits, OpBits-1)))
7445 // This is neither a signed nor an unsigned comparison, just make sure
7446 // that the high bits are equal.
7447 APInt Op1Zero, Op1One;
7448 APInt Op2Zero, Op2One;
7449 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7450 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7452 // We don't really care about what is known about the first bit (if
7453 // anything), so clear it in all masks prior to comparing them.
7454 Op1Zero.clearBit(0); Op1One.clearBit(0);
7455 Op2Zero.clearBit(0); Op2One.clearBit(0);
7457 if (Op1Zero != Op2Zero || Op1One != Op2One)
7462 // We now know that the higher-order bits are irrelevant, we just need to
7463 // make sure that all of the intermediate operations are bit operations, and
7464 // all inputs are extensions.
7465 if (N->getOperand(0).getOpcode() != ISD::AND &&
7466 N->getOperand(0).getOpcode() != ISD::OR &&
7467 N->getOperand(0).getOpcode() != ISD::XOR &&
7468 N->getOperand(0).getOpcode() != ISD::SELECT &&
7469 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7470 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7471 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7472 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7473 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7476 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7477 N->getOperand(1).getOpcode() != ISD::AND &&
7478 N->getOperand(1).getOpcode() != ISD::OR &&
7479 N->getOperand(1).getOpcode() != ISD::XOR &&
7480 N->getOperand(1).getOpcode() != ISD::SELECT &&
7481 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7482 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7483 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7484 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7485 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7488 SmallVector<SDValue, 4> Inputs;
7489 SmallVector<SDValue, 8> BinOps, PromOps;
7490 SmallPtrSet<SDNode *, 16> Visited;
7492 for (unsigned i = 0; i < 2; ++i) {
7493 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7494 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7495 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7496 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7497 isa<ConstantSDNode>(N->getOperand(i)))
7498 Inputs.push_back(N->getOperand(i));
7500 BinOps.push_back(N->getOperand(i));
7502 if (N->getOpcode() == ISD::TRUNCATE)
7506 // Visit all inputs, collect all binary operations (and, or, xor and
7507 // select) that are all fed by extensions.
7508 while (!BinOps.empty()) {
7509 SDValue BinOp = BinOps.back();
7512 if (!Visited.insert(BinOp.getNode()))
7515 PromOps.push_back(BinOp);
7517 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7518 // The condition of the select is not promoted.
7519 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7521 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7524 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7525 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7526 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7527 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7528 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7529 Inputs.push_back(BinOp.getOperand(i));
7530 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7531 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7532 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7533 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7534 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7535 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7536 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7537 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7538 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7539 BinOps.push_back(BinOp.getOperand(i));
7541 // We have an input that is not an extension or another binary
7542 // operation; we'll abort this transformation.
7548 // Make sure that this is a self-contained cluster of operations (which
7549 // is not quite the same thing as saying that everything has only one
7551 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7552 if (isa<ConstantSDNode>(Inputs[i]))
7555 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7556 UE = Inputs[i].getNode()->use_end();
7559 if (User != N && !Visited.count(User))
7562 // Make sure that we're not going to promote the non-output-value
7563 // operand(s) or SELECT or SELECT_CC.
7564 // FIXME: Although we could sometimes handle this, and it does occur in
7565 // practice that one of the condition inputs to the select is also one of
7566 // the outputs, we currently can't deal with this.
7567 if (User->getOpcode() == ISD::SELECT) {
7568 if (User->getOperand(0) == Inputs[i])
7570 } else if (User->getOpcode() == ISD::SELECT_CC) {
7571 if (User->getOperand(0) == Inputs[i] ||
7572 User->getOperand(1) == Inputs[i])
7578 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7579 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7580 UE = PromOps[i].getNode()->use_end();
7583 if (User != N && !Visited.count(User))
7586 // Make sure that we're not going to promote the non-output-value
7587 // operand(s) or SELECT or SELECT_CC.
7588 // FIXME: Although we could sometimes handle this, and it does occur in
7589 // practice that one of the condition inputs to the select is also one of
7590 // the outputs, we currently can't deal with this.
7591 if (User->getOpcode() == ISD::SELECT) {
7592 if (User->getOperand(0) == PromOps[i])
7594 } else if (User->getOpcode() == ISD::SELECT_CC) {
7595 if (User->getOperand(0) == PromOps[i] ||
7596 User->getOperand(1) == PromOps[i])
7602 // Replace all inputs with the extension operand.
7603 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7604 // Constants may have users outside the cluster of to-be-promoted nodes,
7605 // and so we need to replace those as we do the promotions.
7606 if (isa<ConstantSDNode>(Inputs[i]))
7609 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7612 // Replace all operations (these are all the same, but have a different
7613 // (i1) return type). DAG.getNode will validate that the types of
7614 // a binary operator match, so go through the list in reverse so that
7615 // we've likely promoted both operands first. Any intermediate truncations or
7616 // extensions disappear.
7617 while (!PromOps.empty()) {
7618 SDValue PromOp = PromOps.back();
7621 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7622 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7623 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7624 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7625 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7626 PromOp.getOperand(0).getValueType() != MVT::i1) {
7627 // The operand is not yet ready (see comment below).
7628 PromOps.insert(PromOps.begin(), PromOp);
7632 SDValue RepValue = PromOp.getOperand(0);
7633 if (isa<ConstantSDNode>(RepValue))
7634 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7636 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7641 switch (PromOp.getOpcode()) {
7642 default: C = 0; break;
7643 case ISD::SELECT: C = 1; break;
7644 case ISD::SELECT_CC: C = 2; break;
7647 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7648 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7649 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7650 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7651 // The to-be-promoted operands of this node have not yet been
7652 // promoted (this should be rare because we're going through the
7653 // list backward, but if one of the operands has several users in
7654 // this cluster of to-be-promoted nodes, it is possible).
7655 PromOps.insert(PromOps.begin(), PromOp);
7659 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7660 PromOp.getNode()->op_end());
7662 // If there are any constant inputs, make sure they're replaced now.
7663 for (unsigned i = 0; i < 2; ++i)
7664 if (isa<ConstantSDNode>(Ops[C+i]))
7665 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7667 DAG.ReplaceAllUsesOfValueWith(PromOp,
7668 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7671 // Now we're left with the initial truncation itself.
7672 if (N->getOpcode() == ISD::TRUNCATE)
7673 return N->getOperand(0);
7675 // Otherwise, this is a comparison. The operands to be compared have just
7676 // changed type (to i1), but everything else is the same.
7677 return SDValue(N, 0);
7680 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7681 DAGCombinerInfo &DCI) const {
7682 SelectionDAG &DAG = DCI.DAG;
7685 // If we're tracking CR bits, we need to be careful that we don't have:
7686 // zext(binary-ops(trunc(x), trunc(y)))
7688 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7689 // such that we're unnecessarily moving things into CR bits that can more
7690 // efficiently stay in GPRs. Note that if we're not certain that the high
7691 // bits are set as required by the final extension, we still may need to do
7692 // some masking to get the proper behavior.
7694 // This same functionality is important on PPC64 when dealing with
7695 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7696 // the return values of functions. Because it is so similar, it is handled
7699 if (N->getValueType(0) != MVT::i32 &&
7700 N->getValueType(0) != MVT::i64)
7703 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7704 Subtarget.useCRBits()) ||
7705 (N->getOperand(0).getValueType() == MVT::i32 &&
7706 Subtarget.isPPC64())))
7709 if (N->getOperand(0).getOpcode() != ISD::AND &&
7710 N->getOperand(0).getOpcode() != ISD::OR &&
7711 N->getOperand(0).getOpcode() != ISD::XOR &&
7712 N->getOperand(0).getOpcode() != ISD::SELECT &&
7713 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7716 SmallVector<SDValue, 4> Inputs;
7717 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7718 SmallPtrSet<SDNode *, 16> Visited;
7720 // Visit all inputs, collect all binary operations (and, or, xor and
7721 // select) that are all fed by truncations.
7722 while (!BinOps.empty()) {
7723 SDValue BinOp = BinOps.back();
7726 if (!Visited.insert(BinOp.getNode()))
7729 PromOps.push_back(BinOp);
7731 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7732 // The condition of the select is not promoted.
7733 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7735 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7738 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7739 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7740 Inputs.push_back(BinOp.getOperand(i));
7741 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7742 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7743 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7744 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7745 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7746 BinOps.push_back(BinOp.getOperand(i));
7748 // We have an input that is not a truncation or another binary
7749 // operation; we'll abort this transformation.
7755 // Make sure that this is a self-contained cluster of operations (which
7756 // is not quite the same thing as saying that everything has only one
7758 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7759 if (isa<ConstantSDNode>(Inputs[i]))
7762 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7763 UE = Inputs[i].getNode()->use_end();
7766 if (User != N && !Visited.count(User))
7769 // Make sure that we're not going to promote the non-output-value
7770 // operand(s) or SELECT or SELECT_CC.
7771 // FIXME: Although we could sometimes handle this, and it does occur in
7772 // practice that one of the condition inputs to the select is also one of
7773 // the outputs, we currently can't deal with this.
7774 if (User->getOpcode() == ISD::SELECT) {
7775 if (User->getOperand(0) == Inputs[i])
7777 } else if (User->getOpcode() == ISD::SELECT_CC) {
7778 if (User->getOperand(0) == Inputs[i] ||
7779 User->getOperand(1) == Inputs[i])
7785 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7786 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7787 UE = PromOps[i].getNode()->use_end();
7790 if (User != N && !Visited.count(User))
7793 // Make sure that we're not going to promote the non-output-value
7794 // operand(s) or SELECT or SELECT_CC.
7795 // FIXME: Although we could sometimes handle this, and it does occur in
7796 // practice that one of the condition inputs to the select is also one of
7797 // the outputs, we currently can't deal with this.
7798 if (User->getOpcode() == ISD::SELECT) {
7799 if (User->getOperand(0) == PromOps[i])
7801 } else if (User->getOpcode() == ISD::SELECT_CC) {
7802 if (User->getOperand(0) == PromOps[i] ||
7803 User->getOperand(1) == PromOps[i])
7809 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7810 bool ReallyNeedsExt = false;
7811 if (N->getOpcode() != ISD::ANY_EXTEND) {
7812 // If all of the inputs are not already sign/zero extended, then
7813 // we'll still need to do that at the end.
7814 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7815 if (isa<ConstantSDNode>(Inputs[i]))
7819 Inputs[i].getOperand(0).getValueSizeInBits();
7820 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7822 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7823 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7824 APInt::getHighBitsSet(OpBits,
7825 OpBits-PromBits))) ||
7826 (N->getOpcode() == ISD::SIGN_EXTEND &&
7827 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7828 (OpBits-(PromBits-1)))) {
7829 ReallyNeedsExt = true;
7835 // Replace all inputs, either with the truncation operand, or a
7836 // truncation or extension to the final output type.
7837 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7838 // Constant inputs need to be replaced with the to-be-promoted nodes that
7839 // use them because they might have users outside of the cluster of
7841 if (isa<ConstantSDNode>(Inputs[i]))
7844 SDValue InSrc = Inputs[i].getOperand(0);
7845 if (Inputs[i].getValueType() == N->getValueType(0))
7846 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7847 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7848 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7849 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7850 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7851 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7852 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7854 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7855 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7858 // Replace all operations (these are all the same, but have a different
7859 // (promoted) return type). DAG.getNode will validate that the types of
7860 // a binary operator match, so go through the list in reverse so that
7861 // we've likely promoted both operands first.
7862 while (!PromOps.empty()) {
7863 SDValue PromOp = PromOps.back();
7867 switch (PromOp.getOpcode()) {
7868 default: C = 0; break;
7869 case ISD::SELECT: C = 1; break;
7870 case ISD::SELECT_CC: C = 2; break;
7873 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7874 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7875 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7876 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7877 // The to-be-promoted operands of this node have not yet been
7878 // promoted (this should be rare because we're going through the
7879 // list backward, but if one of the operands has several users in
7880 // this cluster of to-be-promoted nodes, it is possible).
7881 PromOps.insert(PromOps.begin(), PromOp);
7885 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7886 PromOp.getNode()->op_end());
7888 // If this node has constant inputs, then they'll need to be promoted here.
7889 for (unsigned i = 0; i < 2; ++i) {
7890 if (!isa<ConstantSDNode>(Ops[C+i]))
7892 if (Ops[C+i].getValueType() == N->getValueType(0))
7895 if (N->getOpcode() == ISD::SIGN_EXTEND)
7896 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7897 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7898 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7900 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7903 DAG.ReplaceAllUsesOfValueWith(PromOp,
7904 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7907 // Now we're left with the initial extension itself.
7908 if (!ReallyNeedsExt)
7909 return N->getOperand(0);
7911 // To zero extend, just mask off everything except for the first bit (in the
7913 if (N->getOpcode() == ISD::ZERO_EXTEND)
7914 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7915 DAG.getConstant(APInt::getLowBitsSet(
7916 N->getValueSizeInBits(0), PromBits),
7917 N->getValueType(0)));
7919 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7920 "Invalid extension type");
7921 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7923 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7924 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7925 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7926 N->getOperand(0), ShiftCst), ShiftCst);
7929 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7930 DAGCombinerInfo &DCI) const {
7931 const TargetMachine &TM = getTargetMachine();
7932 SelectionDAG &DAG = DCI.DAG;
7934 switch (N->getOpcode()) {
7937 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7938 if (C->isNullValue()) // 0 << V -> 0.
7939 return N->getOperand(0);
7943 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7944 if (C->isNullValue()) // 0 >>u V -> 0.
7945 return N->getOperand(0);
7949 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7950 if (C->isNullValue() || // 0 >>s V -> 0.
7951 C->isAllOnesValue()) // -1 >>s V -> -1.
7952 return N->getOperand(0);
7955 case ISD::SIGN_EXTEND:
7956 case ISD::ZERO_EXTEND:
7957 case ISD::ANY_EXTEND:
7958 return DAGCombineExtBoolTrunc(N, DCI);
7961 case ISD::SELECT_CC:
7962 return DAGCombineTruncBoolExt(N, DCI);
7964 assert(TM.Options.UnsafeFPMath &&
7965 "Reciprocal estimates require UnsafeFPMath");
7967 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7969 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7971 DCI.AddToWorklist(RV.getNode());
7972 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7973 N->getOperand(0), RV);
7975 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7976 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7978 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7981 DCI.AddToWorklist(RV.getNode());
7982 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7983 N->getValueType(0), RV);
7984 DCI.AddToWorklist(RV.getNode());
7985 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7986 N->getOperand(0), RV);
7988 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7989 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7991 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7994 DCI.AddToWorklist(RV.getNode());
7995 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7996 N->getValueType(0), RV,
7997 N->getOperand(1).getOperand(1));
7998 DCI.AddToWorklist(RV.getNode());
7999 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8000 N->getOperand(0), RV);
8004 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8006 DCI.AddToWorklist(RV.getNode());
8007 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8008 N->getOperand(0), RV);
8014 assert(TM.Options.UnsafeFPMath &&
8015 "Reciprocal estimates require UnsafeFPMath");
8017 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8019 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8021 DCI.AddToWorklist(RV.getNode());
8022 RV = DAGCombineFastRecip(RV, DCI);
8024 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8025 // this case and force the answer to 0.
8027 EVT VT = RV.getValueType();
8029 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8030 if (VT.isVector()) {
8031 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8032 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8036 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8037 N->getOperand(0), Zero, ISD::SETEQ);
8038 DCI.AddToWorklist(ZeroCmp.getNode());
8039 DCI.AddToWorklist(RV.getNode());
8041 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8049 case ISD::SINT_TO_FP:
8050 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8051 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8052 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8053 // We allow the src/dst to be either f32/f64, but the intermediate
8054 // type must be i64.
8055 if (N->getOperand(0).getValueType() == MVT::i64 &&
8056 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8057 SDValue Val = N->getOperand(0).getOperand(0);
8058 if (Val.getValueType() == MVT::f32) {
8059 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8060 DCI.AddToWorklist(Val.getNode());
8063 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8064 DCI.AddToWorklist(Val.getNode());
8065 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8066 DCI.AddToWorklist(Val.getNode());
8067 if (N->getValueType(0) == MVT::f32) {
8068 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8069 DAG.getIntPtrConstant(0));
8070 DCI.AddToWorklist(Val.getNode());
8073 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8074 // If the intermediate type is i32, we can avoid the load/store here
8081 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8082 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8083 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8084 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8085 N->getOperand(1).getValueType() == MVT::i32 &&
8086 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8087 SDValue Val = N->getOperand(1).getOperand(0);
8088 if (Val.getValueType() == MVT::f32) {
8089 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8090 DCI.AddToWorklist(Val.getNode());
8092 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8093 DCI.AddToWorklist(Val.getNode());
8096 N->getOperand(0), Val, N->getOperand(2),
8097 DAG.getValueType(N->getOperand(1).getValueType())
8100 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8101 DAG.getVTList(MVT::Other), Ops,
8102 cast<StoreSDNode>(N)->getMemoryVT(),
8103 cast<StoreSDNode>(N)->getMemOperand());
8104 DCI.AddToWorklist(Val.getNode());
8108 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8109 if (cast<StoreSDNode>(N)->isUnindexed() &&
8110 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8111 N->getOperand(1).getNode()->hasOneUse() &&
8112 (N->getOperand(1).getValueType() == MVT::i32 ||
8113 N->getOperand(1).getValueType() == MVT::i16 ||
8114 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8115 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8116 N->getOperand(1).getValueType() == MVT::i64))) {
8117 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8118 // Do an any-extend to 32-bits if this is a half-word input.
8119 if (BSwapOp.getValueType() == MVT::i16)
8120 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8123 N->getOperand(0), BSwapOp, N->getOperand(2),
8124 DAG.getValueType(N->getOperand(1).getValueType())
8127 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8128 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8129 cast<StoreSDNode>(N)->getMemOperand());
8133 LoadSDNode *LD = cast<LoadSDNode>(N);
8134 EVT VT = LD->getValueType(0);
8135 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8136 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8137 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8138 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8139 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8140 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8141 LD->getAlignment() < ABIAlignment) {
8142 // This is a type-legal unaligned Altivec load.
8143 SDValue Chain = LD->getChain();
8144 SDValue Ptr = LD->getBasePtr();
8145 bool isLittleEndian = Subtarget.isLittleEndian();
8147 // This implements the loading of unaligned vectors as described in
8148 // the venerable Apple Velocity Engine overview. Specifically:
8149 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8150 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8152 // The general idea is to expand a sequence of one or more unaligned
8153 // loads into an alignment-based permutation-control instruction (lvsl
8154 // or lvsr), a series of regular vector loads (which always truncate
8155 // their input address to an aligned address), and a series of
8156 // permutations. The results of these permutations are the requested
8157 // loaded values. The trick is that the last "extra" load is not taken
8158 // from the address you might suspect (sizeof(vector) bytes after the
8159 // last requested load), but rather sizeof(vector) - 1 bytes after the
8160 // last requested vector. The point of this is to avoid a page fault if
8161 // the base address happened to be aligned. This works because if the
8162 // base address is aligned, then adding less than a full vector length
8163 // will cause the last vector in the sequence to be (re)loaded.
8164 // Otherwise, the next vector will be fetched as you might suspect was
8167 // We might be able to reuse the permutation generation from
8168 // a different base address offset from this one by an aligned amount.
8169 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8170 // optimization later.
8171 Intrinsic::ID Intr = (isLittleEndian ?
8172 Intrinsic::ppc_altivec_lvsr :
8173 Intrinsic::ppc_altivec_lvsl);
8174 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8176 // Refine the alignment of the original load (a "new" load created here
8177 // which was identical to the first except for the alignment would be
8178 // merged with the existing node regardless).
8179 MachineFunction &MF = DAG.getMachineFunction();
8180 MachineMemOperand *MMO =
8181 MF.getMachineMemOperand(LD->getPointerInfo(),
8182 LD->getMemOperand()->getFlags(),
8183 LD->getMemoryVT().getStoreSize(),
8185 LD->refineAlignment(MMO);
8186 SDValue BaseLoad = SDValue(LD, 0);
8188 // Note that the value of IncOffset (which is provided to the next
8189 // load's pointer info offset value, and thus used to calculate the
8190 // alignment), and the value of IncValue (which is actually used to
8191 // increment the pointer value) are different! This is because we
8192 // require the next load to appear to be aligned, even though it
8193 // is actually offset from the base pointer by a lesser amount.
8194 int IncOffset = VT.getSizeInBits() / 8;
8195 int IncValue = IncOffset;
8197 // Walk (both up and down) the chain looking for another load at the real
8198 // (aligned) offset (the alignment of the other load does not matter in
8199 // this case). If found, then do not use the offset reduction trick, as
8200 // that will prevent the loads from being later combined (as they would
8201 // otherwise be duplicates).
8202 if (!findConsecutiveLoad(LD, DAG))
8205 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8206 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8209 DAG.getLoad(VT, dl, Chain, Ptr,
8210 LD->getPointerInfo().getWithOffset(IncOffset),
8211 LD->isVolatile(), LD->isNonTemporal(),
8212 LD->isInvariant(), ABIAlignment);
8214 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8215 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8217 if (BaseLoad.getValueType() != MVT::v4i32)
8218 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8220 if (ExtraLoad.getValueType() != MVT::v4i32)
8221 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8223 // Because vperm has a big-endian bias, we must reverse the order
8224 // of the input vectors and complement the permute control vector
8225 // when generating little endian code. We have already handled the
8226 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8227 // and ExtraLoad here.
8230 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8231 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8233 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8234 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8236 if (VT != MVT::v4i32)
8237 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8239 // Now we need to be really careful about how we update the users of the
8240 // original load. We cannot just call DCI.CombineTo (or
8241 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8242 // uses created here (the permutation for example) that need to stay.
8243 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8245 SDUse &Use = UI.getUse();
8247 // Note: BaseLoad is checked here because it might not be N, but a
8249 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8250 User == TF.getNode() || Use.getResNo() > 1) {
8255 SDValue To = Use.getResNo() ? TF : Perm;
8258 SmallVector<SDValue, 8> Ops;
8259 for (SDNode::op_iterator O = User->op_begin(),
8260 OE = User->op_end(); O != OE; ++O) {
8267 DAG.UpdateNodeOperands(User, Ops);
8270 return SDValue(N, 0);
8274 case ISD::INTRINSIC_WO_CHAIN: {
8275 bool isLittleEndian = Subtarget.isLittleEndian();
8276 Intrinsic::ID Intr = (isLittleEndian ?
8277 Intrinsic::ppc_altivec_lvsr :
8278 Intrinsic::ppc_altivec_lvsl);
8279 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8280 N->getOperand(1)->getOpcode() == ISD::ADD) {
8281 SDValue Add = N->getOperand(1);
8283 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8284 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8285 Add.getValueType().getScalarType().getSizeInBits()))) {
8286 SDNode *BasePtr = Add->getOperand(0).getNode();
8287 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8288 UE = BasePtr->use_end(); UI != UE; ++UI) {
8289 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8290 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8292 // We've found another LVSL/LVSR, and this address is an aligned
8293 // multiple of that one. The results will be the same, so use the
8294 // one we've just found instead.
8296 return SDValue(*UI, 0);
8305 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8306 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8307 N->getOperand(0).hasOneUse() &&
8308 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8309 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8310 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8311 N->getValueType(0) == MVT::i64))) {
8312 SDValue Load = N->getOperand(0);
8313 LoadSDNode *LD = cast<LoadSDNode>(Load);
8314 // Create the byte-swapping load.
8316 LD->getChain(), // Chain
8317 LD->getBasePtr(), // Ptr
8318 DAG.getValueType(N->getValueType(0)) // VT
8321 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8322 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8323 MVT::i64 : MVT::i32, MVT::Other),
8324 Ops, LD->getMemoryVT(), LD->getMemOperand());
8326 // If this is an i16 load, insert the truncate.
8327 SDValue ResVal = BSLoad;
8328 if (N->getValueType(0) == MVT::i16)
8329 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8331 // First, combine the bswap away. This makes the value produced by the
8333 DCI.CombineTo(N, ResVal);
8335 // Next, combine the load away, we give it a bogus result value but a real
8336 // chain result. The result value is dead because the bswap is dead.
8337 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8339 // Return N so it doesn't get rechecked!
8340 return SDValue(N, 0);
8344 case PPCISD::VCMP: {
8345 // If a VCMPo node already exists with exactly the same operands as this
8346 // node, use its result instead of this node (VCMPo computes both a CR6 and
8347 // a normal output).
8349 if (!N->getOperand(0).hasOneUse() &&
8350 !N->getOperand(1).hasOneUse() &&
8351 !N->getOperand(2).hasOneUse()) {
8353 // Scan all of the users of the LHS, looking for VCMPo's that match.
8354 SDNode *VCMPoNode = nullptr;
8356 SDNode *LHSN = N->getOperand(0).getNode();
8357 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8359 if (UI->getOpcode() == PPCISD::VCMPo &&
8360 UI->getOperand(1) == N->getOperand(1) &&
8361 UI->getOperand(2) == N->getOperand(2) &&
8362 UI->getOperand(0) == N->getOperand(0)) {
8367 // If there is no VCMPo node, or if the flag value has a single use, don't
8369 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8372 // Look at the (necessarily single) use of the flag value. If it has a
8373 // chain, this transformation is more complex. Note that multiple things
8374 // could use the value result, which we should ignore.
8375 SDNode *FlagUser = nullptr;
8376 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8377 FlagUser == nullptr; ++UI) {
8378 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8380 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8381 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8388 // If the user is a MFOCRF instruction, we know this is safe.
8389 // Otherwise we give up for right now.
8390 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8391 return SDValue(VCMPoNode, 0);
8396 SDValue Cond = N->getOperand(1);
8397 SDValue Target = N->getOperand(2);
8399 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8400 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8401 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8403 // We now need to make the intrinsic dead (it cannot be instruction
8405 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8406 assert(Cond.getNode()->hasOneUse() &&
8407 "Counter decrement has more than one use");
8409 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8410 N->getOperand(0), Target);
8415 // If this is a branch on an altivec predicate comparison, lower this so
8416 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8417 // lowering is done pre-legalize, because the legalizer lowers the predicate
8418 // compare down to code that is difficult to reassemble.
8419 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8420 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8422 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8423 // value. If so, pass-through the AND to get to the intrinsic.
8424 if (LHS.getOpcode() == ISD::AND &&
8425 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8426 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8427 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8428 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8429 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8431 LHS = LHS.getOperand(0);
8433 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8434 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8435 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8436 isa<ConstantSDNode>(RHS)) {
8437 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8438 "Counter decrement comparison is not EQ or NE");
8440 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8441 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8442 (CC == ISD::SETNE && !Val);
8444 // We now need to make the intrinsic dead (it cannot be instruction
8446 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8447 assert(LHS.getNode()->hasOneUse() &&
8448 "Counter decrement has more than one use");
8450 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8451 N->getOperand(0), N->getOperand(4));
8457 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8458 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8459 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8460 assert(isDot && "Can't compare against a vector result!");
8462 // If this is a comparison against something other than 0/1, then we know
8463 // that the condition is never/always true.
8464 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8465 if (Val != 0 && Val != 1) {
8466 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8467 return N->getOperand(0);
8468 // Always !=, turn it into an unconditional branch.
8469 return DAG.getNode(ISD::BR, dl, MVT::Other,
8470 N->getOperand(0), N->getOperand(4));
8473 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8475 // Create the PPCISD altivec 'dot' comparison node.
8477 LHS.getOperand(2), // LHS of compare
8478 LHS.getOperand(3), // RHS of compare
8479 DAG.getConstant(CompareOpc, MVT::i32)
8481 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8482 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8484 // Unpack the result based on how the target uses it.
8485 PPC::Predicate CompOpc;
8486 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8487 default: // Can't happen, don't crash on invalid number though.
8488 case 0: // Branch on the value of the EQ bit of CR6.
8489 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8491 case 1: // Branch on the inverted value of the EQ bit of CR6.
8492 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8494 case 2: // Branch on the value of the LT bit of CR6.
8495 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8497 case 3: // Branch on the inverted value of the LT bit of CR6.
8498 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8502 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8503 DAG.getConstant(CompOpc, MVT::i32),
8504 DAG.getRegister(PPC::CR6, MVT::i32),
8505 N->getOperand(4), CompNode.getValue(1));
8514 //===----------------------------------------------------------------------===//
8515 // Inline Assembly Support
8516 //===----------------------------------------------------------------------===//
8518 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8521 const SelectionDAG &DAG,
8522 unsigned Depth) const {
8523 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8524 switch (Op.getOpcode()) {
8526 case PPCISD::LBRX: {
8527 // lhbrx is known to have the top bits cleared out.
8528 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8529 KnownZero = 0xFFFF0000;
8532 case ISD::INTRINSIC_WO_CHAIN: {
8533 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8535 case Intrinsic::ppc_altivec_vcmpbfp_p:
8536 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8537 case Intrinsic::ppc_altivec_vcmpequb_p:
8538 case Intrinsic::ppc_altivec_vcmpequh_p:
8539 case Intrinsic::ppc_altivec_vcmpequw_p:
8540 case Intrinsic::ppc_altivec_vcmpgefp_p:
8541 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8542 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8543 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8544 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8545 case Intrinsic::ppc_altivec_vcmpgtub_p:
8546 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8547 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8548 KnownZero = ~1U; // All bits but the low one are known to be zero.
8556 /// getConstraintType - Given a constraint, return the type of
8557 /// constraint it is for this target.
8558 PPCTargetLowering::ConstraintType
8559 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8560 if (Constraint.size() == 1) {
8561 switch (Constraint[0]) {
8568 return C_RegisterClass;
8570 // FIXME: While Z does indicate a memory constraint, it specifically
8571 // indicates an r+r address (used in conjunction with the 'y' modifier
8572 // in the replacement string). Currently, we're forcing the base
8573 // register to be r0 in the asm printer (which is interpreted as zero)
8574 // and forming the complete address in the second register. This is
8578 } else if (Constraint == "wc") { // individual CR bits.
8579 return C_RegisterClass;
8580 } else if (Constraint == "wa" || Constraint == "wd" ||
8581 Constraint == "wf" || Constraint == "ws") {
8582 return C_RegisterClass; // VSX registers.
8584 return TargetLowering::getConstraintType(Constraint);
8587 /// Examine constraint type and operand type and determine a weight value.
8588 /// This object must already have been set up with the operand type
8589 /// and the current alternative constraint selected.
8590 TargetLowering::ConstraintWeight
8591 PPCTargetLowering::getSingleConstraintMatchWeight(
8592 AsmOperandInfo &info, const char *constraint) const {
8593 ConstraintWeight weight = CW_Invalid;
8594 Value *CallOperandVal = info.CallOperandVal;
8595 // If we don't have a value, we can't do a match,
8596 // but allow it at the lowest weight.
8597 if (!CallOperandVal)
8599 Type *type = CallOperandVal->getType();
8601 // Look at the constraint type.
8602 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8603 return CW_Register; // an individual CR bit.
8604 else if ((StringRef(constraint) == "wa" ||
8605 StringRef(constraint) == "wd" ||
8606 StringRef(constraint) == "wf") &&
8609 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8612 switch (*constraint) {
8614 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8617 if (type->isIntegerTy())
8618 weight = CW_Register;
8621 if (type->isFloatTy())
8622 weight = CW_Register;
8625 if (type->isDoubleTy())
8626 weight = CW_Register;
8629 if (type->isVectorTy())
8630 weight = CW_Register;
8633 weight = CW_Register;
8642 std::pair<unsigned, const TargetRegisterClass*>
8643 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8645 if (Constraint.size() == 1) {
8646 // GCC RS6000 Constraint Letters
8647 switch (Constraint[0]) {
8649 if (VT == MVT::i64 && Subtarget.isPPC64())
8650 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8651 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8653 if (VT == MVT::i64 && Subtarget.isPPC64())
8654 return std::make_pair(0U, &PPC::G8RCRegClass);
8655 return std::make_pair(0U, &PPC::GPRCRegClass);
8657 if (VT == MVT::f32 || VT == MVT::i32)
8658 return std::make_pair(0U, &PPC::F4RCRegClass);
8659 if (VT == MVT::f64 || VT == MVT::i64)
8660 return std::make_pair(0U, &PPC::F8RCRegClass);
8663 return std::make_pair(0U, &PPC::VRRCRegClass);
8665 return std::make_pair(0U, &PPC::CRRCRegClass);
8667 } else if (Constraint == "wc") { // an individual CR bit.
8668 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8669 } else if (Constraint == "wa" || Constraint == "wd" ||
8670 Constraint == "wf") {
8671 return std::make_pair(0U, &PPC::VSRCRegClass);
8672 } else if (Constraint == "ws") {
8673 return std::make_pair(0U, &PPC::VSFRCRegClass);
8676 std::pair<unsigned, const TargetRegisterClass*> R =
8677 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8679 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8680 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8681 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8683 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8684 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8685 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8686 PPC::GPRCRegClass.contains(R.first)) {
8687 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8688 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8689 PPC::sub_32, &PPC::G8RCRegClass),
8690 &PPC::G8RCRegClass);
8697 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8698 /// vector. If it is invalid, don't add anything to Ops.
8699 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8700 std::string &Constraint,
8701 std::vector<SDValue>&Ops,
8702 SelectionDAG &DAG) const {
8705 // Only support length 1 constraints.
8706 if (Constraint.length() > 1) return;
8708 char Letter = Constraint[0];
8719 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8720 if (!CST) return; // Must be an immediate to match.
8721 unsigned Value = CST->getZExtValue();
8723 default: llvm_unreachable("Unknown constraint letter!");
8724 case 'I': // "I" is a signed 16-bit constant.
8725 if ((short)Value == (int)Value)
8726 Result = DAG.getTargetConstant(Value, Op.getValueType());
8728 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8729 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8730 if ((short)Value == 0)
8731 Result = DAG.getTargetConstant(Value, Op.getValueType());
8733 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8734 if ((Value >> 16) == 0)
8735 Result = DAG.getTargetConstant(Value, Op.getValueType());
8737 case 'M': // "M" is a constant that is greater than 31.
8739 Result = DAG.getTargetConstant(Value, Op.getValueType());
8741 case 'N': // "N" is a positive constant that is an exact power of two.
8742 if ((int)Value > 0 && isPowerOf2_32(Value))
8743 Result = DAG.getTargetConstant(Value, Op.getValueType());
8745 case 'O': // "O" is the constant zero.
8747 Result = DAG.getTargetConstant(Value, Op.getValueType());
8749 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8750 if ((short)-Value == (int)-Value)
8751 Result = DAG.getTargetConstant(Value, Op.getValueType());
8758 if (Result.getNode()) {
8759 Ops.push_back(Result);
8763 // Handle standard constraint letters.
8764 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8767 // isLegalAddressingMode - Return true if the addressing mode represented
8768 // by AM is legal for this target, for a load/store of the specified type.
8769 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8771 // FIXME: PPC does not allow r+i addressing modes for vectors!
8773 // PPC allows a sign-extended 16-bit immediate field.
8774 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8777 // No global is ever allowed as a base.
8781 // PPC only support r+r,
8783 case 0: // "r+i" or just "i", depending on HasBaseReg.
8786 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8788 // Otherwise we have r+r or r+i.
8791 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8793 // Allow 2*r as r+r.
8796 // No other scales are supported.
8803 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8804 SelectionDAG &DAG) const {
8805 MachineFunction &MF = DAG.getMachineFunction();
8806 MachineFrameInfo *MFI = MF.getFrameInfo();
8807 MFI->setReturnAddressIsTaken(true);
8809 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8813 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8815 // Make sure the function does not optimize away the store of the RA to
8817 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8818 FuncInfo->setLRStoreRequired();
8819 bool isPPC64 = Subtarget.isPPC64();
8820 bool isDarwinABI = Subtarget.isDarwinABI();
8823 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8826 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8827 isPPC64? MVT::i64 : MVT::i32);
8828 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8829 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8831 MachinePointerInfo(), false, false, false, 0);
8834 // Just load the return address off the stack.
8835 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8836 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8837 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8840 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8841 SelectionDAG &DAG) const {
8843 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8845 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8846 bool isPPC64 = PtrVT == MVT::i64;
8848 MachineFunction &MF = DAG.getMachineFunction();
8849 MachineFrameInfo *MFI = MF.getFrameInfo();
8850 MFI->setFrameAddressIsTaken(true);
8852 // Naked functions never have a frame pointer, and so we use r1. For all
8853 // other functions, this decision must be delayed until during PEI.
8855 if (MF.getFunction()->getAttributes().hasAttribute(
8856 AttributeSet::FunctionIndex, Attribute::Naked))
8857 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8859 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8861 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8864 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8865 FrameAddr, MachinePointerInfo(), false, false,
8870 // FIXME? Maybe this could be a TableGen attribute on some registers and
8871 // this table could be generated automatically from RegInfo.
8872 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8874 bool isPPC64 = Subtarget.isPPC64();
8875 bool isDarwinABI = Subtarget.isDarwinABI();
8877 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8878 (!isPPC64 && VT != MVT::i32))
8879 report_fatal_error("Invalid register global variable type");
8881 bool is64Bit = isPPC64 && VT == MVT::i64;
8882 unsigned Reg = StringSwitch<unsigned>(RegName)
8883 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8884 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8885 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8886 (is64Bit ? PPC::X13 : PPC::R13))
8891 report_fatal_error("Invalid register name global variable");
8895 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8896 // The PowerPC target isn't yet aware of offsets.
8900 /// getOptimalMemOpType - Returns the target specific optimal type for load
8901 /// and store operations as a result of memset, memcpy, and memmove
8902 /// lowering. If DstAlign is zero that means it's safe to destination
8903 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8904 /// means there isn't a need to check it against alignment requirement,
8905 /// probably because the source does not need to be loaded. If 'IsMemset' is
8906 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8907 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8908 /// source is constant so it does not need to be loaded.
8909 /// It returns EVT::Other if the type should be determined using generic
8910 /// target-independent logic.
8911 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8912 unsigned DstAlign, unsigned SrcAlign,
8913 bool IsMemset, bool ZeroMemset,
8915 MachineFunction &MF) const {
8916 if (Subtarget.isPPC64()) {
8923 /// \brief Returns true if it is beneficial to convert a load of a constant
8924 /// to just the constant itself.
8925 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8927 assert(Ty->isIntegerTy());
8929 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8930 if (BitSize == 0 || BitSize > 64)
8935 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8936 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8938 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8939 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8940 return NumBits1 == 64 && NumBits2 == 32;
8943 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8944 if (!VT1.isInteger() || !VT2.isInteger())
8946 unsigned NumBits1 = VT1.getSizeInBits();
8947 unsigned NumBits2 = VT2.getSizeInBits();
8948 return NumBits1 == 64 && NumBits2 == 32;
8951 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8952 return isInt<16>(Imm) || isUInt<16>(Imm);
8955 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8956 return isInt<16>(Imm) || isUInt<16>(Imm);
8959 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8962 if (DisablePPCUnaligned)
8965 // PowerPC supports unaligned memory access for simple non-vector types.
8966 // Although accessing unaligned addresses is not as efficient as accessing
8967 // aligned addresses, it is generally more efficient than manual expansion,
8968 // and generally only traps for software emulation when crossing page
8974 if (VT.getSimpleVT().isVector()) {
8975 if (Subtarget.hasVSX()) {
8976 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8983 if (VT == MVT::ppcf128)
8992 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8993 VT = VT.getScalarType();
8998 switch (VT.getSimpleVT().SimpleTy) {
9010 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9011 EVT VT , unsigned DefinedValues) const {
9012 if (VT == MVT::v2i64)
9015 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9018 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9019 if (DisableILPPref || Subtarget.enableMachineScheduler())
9020 return TargetLowering::getSchedulingPreference(N);
9025 // Create a fast isel object.
9027 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9028 const TargetLibraryInfo *LibInfo) const {
9029 return PPC::createFastISel(FuncInfo, LibInfo);