1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCCallingConv.h"
17 #include "PPCMachineFunctionInfo.h"
18 #include "PPCPerfectShuffle.h"
19 #include "PPCTargetMachine.h"
20 #include "PPCTargetObjectFile.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringSwitch.h"
23 #include "llvm/ADT/Triple.h"
24 #include "llvm/CodeGen/CallingConvLower.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunction.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineLoopInfo.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAG.h"
31 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
32 #include "llvm/IR/CallingConv.h"
33 #include "llvm/IR/Constants.h"
34 #include "llvm/IR/DerivedTypes.h"
35 #include "llvm/IR/Function.h"
36 #include "llvm/IR/Intrinsics.h"
37 #include "llvm/Support/CommandLine.h"
38 #include "llvm/Support/ErrorHandling.h"
39 #include "llvm/Support/MathExtras.h"
40 #include "llvm/Support/raw_ostream.h"
41 #include "llvm/Target/TargetOptions.h"
45 // FIXME: Remove this once soft-float is supported.
46 static cl::opt<bool> DisablePPCFloatInVariadic("disable-ppc-float-in-variadic",
47 cl::desc("disable saving float registers for va_start on PPC"), cl::Hidden);
49 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
50 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
52 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
53 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
55 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
56 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
58 // FIXME: Remove this once the bug has been fixed!
59 extern cl::opt<bool> ANDIGlueBug;
61 PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
62 const PPCSubtarget &STI)
63 : TargetLowering(TM), Subtarget(STI) {
64 // Use _setjmp/_longjmp instead of setjmp/longjmp.
65 setUseUnderscoreSetJmp(true);
66 setUseUnderscoreLongJmp(true);
68 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
69 // arguments are at least 4/8 bytes aligned.
70 bool isPPC64 = Subtarget.isPPC64();
71 setMinStackArgumentAlignment(isPPC64 ? 8:4);
73 // Set up the register classes.
74 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
75 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
76 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
78 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
79 for (MVT VT : MVT::integer_valuetypes()) {
80 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
81 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
84 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
86 // PowerPC has pre-inc load and store's.
87 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::f32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::f64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 setIndexedStoreAction(ISD::PRE_INC, MVT::f32, Legal);
100 setIndexedStoreAction(ISD::PRE_INC, MVT::f64, Legal);
102 if (Subtarget.useCRBits()) {
103 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
105 if (isPPC64 || Subtarget.hasFPCVT()) {
106 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
107 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
108 isPPC64 ? MVT::i64 : MVT::i32);
109 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
110 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
111 isPPC64 ? MVT::i64 : MVT::i32);
113 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
114 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
117 // PowerPC does not support direct load / store of condition registers
118 setOperationAction(ISD::LOAD, MVT::i1, Custom);
119 setOperationAction(ISD::STORE, MVT::i1, Custom);
121 // FIXME: Remove this once the ANDI glue bug is fixed:
123 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
125 for (MVT VT : MVT::integer_valuetypes()) {
126 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
127 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setTruncStoreAction(VT, MVT::i1, Expand);
131 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
134 // This is used in the ppcf128->int sequence. Note it has different semantics
135 // from FP_ROUND: that rounds to nearest, this rounds to zero.
136 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
138 // We do not currently implement these libm ops for PowerPC.
139 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
144 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
146 // PowerPC has no SREM/UREM instructions
147 setOperationAction(ISD::SREM, MVT::i32, Expand);
148 setOperationAction(ISD::UREM, MVT::i32, Expand);
149 setOperationAction(ISD::SREM, MVT::i64, Expand);
150 setOperationAction(ISD::UREM, MVT::i64, Expand);
152 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
153 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
155 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
157 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
159 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
160 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
162 // We don't support sin/cos/sqrt/fmod/pow
163 setOperationAction(ISD::FSIN , MVT::f64, Expand);
164 setOperationAction(ISD::FCOS , MVT::f64, Expand);
165 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
166 setOperationAction(ISD::FREM , MVT::f64, Expand);
167 setOperationAction(ISD::FPOW , MVT::f64, Expand);
168 setOperationAction(ISD::FMA , MVT::f64, Legal);
169 setOperationAction(ISD::FSIN , MVT::f32, Expand);
170 setOperationAction(ISD::FCOS , MVT::f32, Expand);
171 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
172 setOperationAction(ISD::FREM , MVT::f32, Expand);
173 setOperationAction(ISD::FPOW , MVT::f32, Expand);
174 setOperationAction(ISD::FMA , MVT::f32, Legal);
176 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
178 // If we're enabling GP optimizations, use hardware square root
179 if (!Subtarget.hasFSQRT() &&
180 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTE() &&
182 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
184 if (!Subtarget.hasFSQRT() &&
185 !(TM.Options.UnsafeFPMath && Subtarget.hasFRSQRTES() &&
186 Subtarget.hasFRES()))
187 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
189 if (Subtarget.hasFCPSGN()) {
190 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
191 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
194 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
197 if (Subtarget.hasFPRND()) {
198 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
199 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
200 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
201 setOperationAction(ISD::FROUND, MVT::f64, Legal);
203 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
204 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
205 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
206 setOperationAction(ISD::FROUND, MVT::f32, Legal);
209 // PowerPC does not have BSWAP, CTPOP or CTTZ
210 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
212 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
214 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
216 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
217 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
219 if (Subtarget.hasPOPCNTD()) {
220 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
221 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
223 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
224 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
227 // PowerPC does not have ROTR
228 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
229 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
231 if (!Subtarget.useCRBits()) {
232 // PowerPC does not have Select
233 setOperationAction(ISD::SELECT, MVT::i32, Expand);
234 setOperationAction(ISD::SELECT, MVT::i64, Expand);
235 setOperationAction(ISD::SELECT, MVT::f32, Expand);
236 setOperationAction(ISD::SELECT, MVT::f64, Expand);
239 // PowerPC wants to turn select_cc of FP into fsel when possible.
240 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
241 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
243 // PowerPC wants to optimize integer setcc a bit
244 if (!Subtarget.useCRBits())
245 setOperationAction(ISD::SETCC, MVT::i32, Custom);
247 // PowerPC does not have BRCOND which requires SetCC
248 if (!Subtarget.useCRBits())
249 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
251 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
253 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
254 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
256 // PowerPC does not have [U|S]INT_TO_FP
257 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
258 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
262 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
263 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
265 // We cannot sextinreg(i1). Expand to shifts.
266 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
268 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
269 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
270 // support continuation, user-level threading, and etc.. As a result, no
271 // other SjLj exception interfaces are implemented and please don't build
272 // your own exception handling based on them.
273 // LLVM/Clang supports zero-cost DWARF exception handling.
274 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
275 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
277 // We want to legalize GlobalAddress and ConstantPool nodes into the
278 // appropriate instructions to materialize the address.
279 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
280 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
281 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
282 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
283 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
284 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
285 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
286 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
287 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
288 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
291 setOperationAction(ISD::TRAP, MVT::Other, Legal);
293 // TRAMPOLINE is custom lowered.
294 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
295 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
297 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
298 setOperationAction(ISD::VASTART , MVT::Other, Custom);
300 if (Subtarget.isSVR4ABI()) {
302 // VAARG always uses double-word chunks, so promote anything smaller.
303 setOperationAction(ISD::VAARG, MVT::i1, Promote);
304 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
305 setOperationAction(ISD::VAARG, MVT::i8, Promote);
306 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
307 setOperationAction(ISD::VAARG, MVT::i16, Promote);
308 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
309 setOperationAction(ISD::VAARG, MVT::i32, Promote);
310 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
311 setOperationAction(ISD::VAARG, MVT::Other, Expand);
313 // VAARG is custom lowered with the 32-bit SVR4 ABI.
314 setOperationAction(ISD::VAARG, MVT::Other, Custom);
315 setOperationAction(ISD::VAARG, MVT::i64, Custom);
318 setOperationAction(ISD::VAARG, MVT::Other, Expand);
320 if (Subtarget.isSVR4ABI() && !isPPC64)
321 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
322 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
324 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
326 // Use the default implementation.
327 setOperationAction(ISD::VAEND , MVT::Other, Expand);
328 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
329 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
331 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
333 // We want to custom lower some of our intrinsics.
334 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
336 // To handle counter-based loop conditions.
337 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
339 // Comparisons that require checking two conditions.
340 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
341 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
343 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
345 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
347 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
349 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
351 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
353 if (Subtarget.has64BitSupport()) {
354 // They also have instructions for converting between i64 and fp.
355 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
356 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
357 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
358 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
359 // This is just the low 32 bits of a (signed) fp->i64 conversion.
360 // We cannot do this with Promote because i64 is not a legal type.
361 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
363 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
364 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
366 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
367 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
370 // With the instructions enabled under FPCVT, we can do everything.
371 if (Subtarget.hasFPCVT()) {
372 if (Subtarget.has64BitSupport()) {
373 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
374 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
375 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
376 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
379 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
380 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
381 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
382 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
385 if (Subtarget.use64BitRegs()) {
386 // 64-bit PowerPC implementations can support i64 types directly
387 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
388 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
389 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
390 // 64-bit PowerPC wants to expand i128 shifts itself.
391 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
393 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
395 // 32-bit PowerPC wants to expand i64 shifts itself.
396 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
398 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
401 if (Subtarget.hasAltivec()) {
402 // First set operation action for all vector types to expand. Then we
403 // will selectively turn on ones that can be effectively codegen'd.
404 for (MVT VT : MVT::vector_valuetypes()) {
405 // add/sub are legal for all supported vector VT's.
406 setOperationAction(ISD::ADD , VT, Legal);
407 setOperationAction(ISD::SUB , VT, Legal);
409 // Vector instructions introduced in P8
410 if (Subtarget.hasP8Altivec() && (VT.SimpleTy != MVT::v1i128)) {
411 setOperationAction(ISD::CTPOP, VT, Legal);
412 setOperationAction(ISD::CTLZ, VT, Legal);
415 setOperationAction(ISD::CTPOP, VT, Expand);
416 setOperationAction(ISD::CTLZ, VT, Expand);
419 // We promote all shuffles to v16i8.
420 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
421 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
423 // We promote all non-typed operations to v4i32.
424 setOperationAction(ISD::AND , VT, Promote);
425 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
426 setOperationAction(ISD::OR , VT, Promote);
427 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
428 setOperationAction(ISD::XOR , VT, Promote);
429 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
430 setOperationAction(ISD::LOAD , VT, Promote);
431 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
432 setOperationAction(ISD::SELECT, VT, Promote);
433 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
434 setOperationAction(ISD::SELECT_CC, VT, Promote);
435 AddPromotedToType (ISD::SELECT_CC, VT, MVT::v4i32);
436 setOperationAction(ISD::STORE, VT, Promote);
437 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
439 // No other operations are legal.
440 setOperationAction(ISD::MUL , VT, Expand);
441 setOperationAction(ISD::SDIV, VT, Expand);
442 setOperationAction(ISD::SREM, VT, Expand);
443 setOperationAction(ISD::UDIV, VT, Expand);
444 setOperationAction(ISD::UREM, VT, Expand);
445 setOperationAction(ISD::FDIV, VT, Expand);
446 setOperationAction(ISD::FREM, VT, Expand);
447 setOperationAction(ISD::FNEG, VT, Expand);
448 setOperationAction(ISD::FSQRT, VT, Expand);
449 setOperationAction(ISD::FLOG, VT, Expand);
450 setOperationAction(ISD::FLOG10, VT, Expand);
451 setOperationAction(ISD::FLOG2, VT, Expand);
452 setOperationAction(ISD::FEXP, VT, Expand);
453 setOperationAction(ISD::FEXP2, VT, Expand);
454 setOperationAction(ISD::FSIN, VT, Expand);
455 setOperationAction(ISD::FCOS, VT, Expand);
456 setOperationAction(ISD::FABS, VT, Expand);
457 setOperationAction(ISD::FPOWI, VT, Expand);
458 setOperationAction(ISD::FFLOOR, VT, Expand);
459 setOperationAction(ISD::FCEIL, VT, Expand);
460 setOperationAction(ISD::FTRUNC, VT, Expand);
461 setOperationAction(ISD::FRINT, VT, Expand);
462 setOperationAction(ISD::FNEARBYINT, VT, Expand);
463 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
464 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
465 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
466 setOperationAction(ISD::MULHU, VT, Expand);
467 setOperationAction(ISD::MULHS, VT, Expand);
468 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
469 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
470 setOperationAction(ISD::UDIVREM, VT, Expand);
471 setOperationAction(ISD::SDIVREM, VT, Expand);
472 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
473 setOperationAction(ISD::FPOW, VT, Expand);
474 setOperationAction(ISD::BSWAP, VT, Expand);
475 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
476 setOperationAction(ISD::CTTZ, VT, Expand);
477 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
478 setOperationAction(ISD::VSELECT, VT, Expand);
479 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
481 for (MVT InnerVT : MVT::vector_valuetypes()) {
482 setTruncStoreAction(VT, InnerVT, Expand);
483 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
484 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
485 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
489 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
490 // with merges, splats, etc.
491 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
493 setOperationAction(ISD::AND , MVT::v4i32, Legal);
494 setOperationAction(ISD::OR , MVT::v4i32, Legal);
495 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
496 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
497 setOperationAction(ISD::SELECT, MVT::v4i32,
498 Subtarget.useCRBits() ? Legal : Expand);
499 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
500 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
501 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
502 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
503 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
504 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
505 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
506 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
507 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
509 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
510 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
511 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
512 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
514 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
515 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
517 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
518 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
523 if (Subtarget.hasP8Altivec())
524 setOperationAction(ISD::MUL, MVT::v4i32, Legal);
526 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
528 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
529 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
531 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
532 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
534 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
535 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
536 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
537 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
539 // Altivec does not contain unordered floating-point compare instructions
540 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
541 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
542 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
543 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
545 if (Subtarget.hasVSX()) {
546 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
547 if (Subtarget.hasP8Vector())
548 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
549 if (Subtarget.hasDirectMove()) {
550 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Legal);
551 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Legal);
552 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Legal);
553 // FIXME: this is causing bootstrap failures, disable temporarily
554 //setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i64, Legal);
556 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
558 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
559 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
560 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
561 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
562 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
564 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
566 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
567 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
569 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
570 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
572 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
573 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
574 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
575 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
576 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
578 // Share the Altivec comparison restrictions.
579 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
580 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
581 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
582 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
584 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
585 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
587 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
589 if (Subtarget.hasP8Vector())
590 addRegisterClass(MVT::f32, &PPC::VSSRCRegClass);
592 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
594 addRegisterClass(MVT::v4i32, &PPC::VSRCRegClass);
595 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
596 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
598 if (Subtarget.hasP8Altivec()) {
599 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
600 setOperationAction(ISD::SRA, MVT::v2i64, Legal);
601 setOperationAction(ISD::SRL, MVT::v2i64, Legal);
603 setOperationAction(ISD::SETCC, MVT::v2i64, Legal);
606 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
607 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
608 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
610 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
612 // VSX v2i64 only supports non-arithmetic operations.
613 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
614 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
617 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
618 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
619 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
620 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
622 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
624 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
625 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
626 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
627 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
629 // Vector operation legalization checks the result type of
630 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
631 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
632 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
633 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
634 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
636 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
639 if (Subtarget.hasP8Altivec()) {
640 addRegisterClass(MVT::v2i64, &PPC::VRRCRegClass);
641 addRegisterClass(MVT::v1i128, &PPC::VRRCRegClass);
645 if (Subtarget.hasQPX()) {
646 setOperationAction(ISD::FADD, MVT::v4f64, Legal);
647 setOperationAction(ISD::FSUB, MVT::v4f64, Legal);
648 setOperationAction(ISD::FMUL, MVT::v4f64, Legal);
649 setOperationAction(ISD::FREM, MVT::v4f64, Expand);
651 setOperationAction(ISD::FCOPYSIGN, MVT::v4f64, Legal);
652 setOperationAction(ISD::FGETSIGN, MVT::v4f64, Expand);
654 setOperationAction(ISD::LOAD , MVT::v4f64, Custom);
655 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
657 setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom);
658 setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Custom);
660 if (!Subtarget.useCRBits())
661 setOperationAction(ISD::SELECT, MVT::v4f64, Expand);
662 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
664 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f64, Legal);
665 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f64, Expand);
666 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f64, Expand);
667 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f64, Expand);
668 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f64, Custom);
669 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f64, Legal);
670 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f64, Custom);
672 setOperationAction(ISD::FP_TO_SINT , MVT::v4f64, Legal);
673 setOperationAction(ISD::FP_TO_UINT , MVT::v4f64, Expand);
675 setOperationAction(ISD::FP_ROUND , MVT::v4f32, Legal);
676 setOperationAction(ISD::FP_ROUND_INREG , MVT::v4f32, Expand);
677 setOperationAction(ISD::FP_EXTEND, MVT::v4f64, Legal);
679 setOperationAction(ISD::FNEG , MVT::v4f64, Legal);
680 setOperationAction(ISD::FABS , MVT::v4f64, Legal);
681 setOperationAction(ISD::FSIN , MVT::v4f64, Expand);
682 setOperationAction(ISD::FCOS , MVT::v4f64, Expand);
683 setOperationAction(ISD::FPOWI , MVT::v4f64, Expand);
684 setOperationAction(ISD::FPOW , MVT::v4f64, Expand);
685 setOperationAction(ISD::FLOG , MVT::v4f64, Expand);
686 setOperationAction(ISD::FLOG2 , MVT::v4f64, Expand);
687 setOperationAction(ISD::FLOG10 , MVT::v4f64, Expand);
688 setOperationAction(ISD::FEXP , MVT::v4f64, Expand);
689 setOperationAction(ISD::FEXP2 , MVT::v4f64, Expand);
691 setOperationAction(ISD::FMINNUM, MVT::v4f64, Legal);
692 setOperationAction(ISD::FMAXNUM, MVT::v4f64, Legal);
694 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f64, Legal);
695 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f64, Legal);
697 addRegisterClass(MVT::v4f64, &PPC::QFRCRegClass);
699 setOperationAction(ISD::FADD, MVT::v4f32, Legal);
700 setOperationAction(ISD::FSUB, MVT::v4f32, Legal);
701 setOperationAction(ISD::FMUL, MVT::v4f32, Legal);
702 setOperationAction(ISD::FREM, MVT::v4f32, Expand);
704 setOperationAction(ISD::FCOPYSIGN, MVT::v4f32, Legal);
705 setOperationAction(ISD::FGETSIGN, MVT::v4f32, Expand);
707 setOperationAction(ISD::LOAD , MVT::v4f32, Custom);
708 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
710 if (!Subtarget.useCRBits())
711 setOperationAction(ISD::SELECT, MVT::v4f32, Expand);
712 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
714 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4f32, Legal);
715 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4f32, Expand);
716 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4f32, Expand);
717 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4f32, Expand);
718 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4f32, Custom);
719 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
720 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
722 setOperationAction(ISD::FP_TO_SINT , MVT::v4f32, Legal);
723 setOperationAction(ISD::FP_TO_UINT , MVT::v4f32, Expand);
725 setOperationAction(ISD::FNEG , MVT::v4f32, Legal);
726 setOperationAction(ISD::FABS , MVT::v4f32, Legal);
727 setOperationAction(ISD::FSIN , MVT::v4f32, Expand);
728 setOperationAction(ISD::FCOS , MVT::v4f32, Expand);
729 setOperationAction(ISD::FPOWI , MVT::v4f32, Expand);
730 setOperationAction(ISD::FPOW , MVT::v4f32, Expand);
731 setOperationAction(ISD::FLOG , MVT::v4f32, Expand);
732 setOperationAction(ISD::FLOG2 , MVT::v4f32, Expand);
733 setOperationAction(ISD::FLOG10 , MVT::v4f32, Expand);
734 setOperationAction(ISD::FEXP , MVT::v4f32, Expand);
735 setOperationAction(ISD::FEXP2 , MVT::v4f32, Expand);
737 setOperationAction(ISD::FMINNUM, MVT::v4f32, Legal);
738 setOperationAction(ISD::FMAXNUM, MVT::v4f32, Legal);
740 setIndexedLoadAction(ISD::PRE_INC, MVT::v4f32, Legal);
741 setIndexedStoreAction(ISD::PRE_INC, MVT::v4f32, Legal);
743 addRegisterClass(MVT::v4f32, &PPC::QSRCRegClass);
745 setOperationAction(ISD::AND , MVT::v4i1, Legal);
746 setOperationAction(ISD::OR , MVT::v4i1, Legal);
747 setOperationAction(ISD::XOR , MVT::v4i1, Legal);
749 if (!Subtarget.useCRBits())
750 setOperationAction(ISD::SELECT, MVT::v4i1, Expand);
751 setOperationAction(ISD::VSELECT, MVT::v4i1, Legal);
753 setOperationAction(ISD::LOAD , MVT::v4i1, Custom);
754 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
756 setOperationAction(ISD::EXTRACT_VECTOR_ELT , MVT::v4i1, Custom);
757 setOperationAction(ISD::INSERT_VECTOR_ELT , MVT::v4i1, Expand);
758 setOperationAction(ISD::CONCAT_VECTORS , MVT::v4i1, Expand);
759 setOperationAction(ISD::EXTRACT_SUBVECTOR , MVT::v4i1, Expand);
760 setOperationAction(ISD::VECTOR_SHUFFLE , MVT::v4i1, Custom);
761 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i1, Expand);
762 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i1, Custom);
764 setOperationAction(ISD::SINT_TO_FP, MVT::v4i1, Custom);
765 setOperationAction(ISD::UINT_TO_FP, MVT::v4i1, Custom);
767 addRegisterClass(MVT::v4i1, &PPC::QBRCRegClass);
769 setOperationAction(ISD::FFLOOR, MVT::v4f64, Legal);
770 setOperationAction(ISD::FCEIL, MVT::v4f64, Legal);
771 setOperationAction(ISD::FTRUNC, MVT::v4f64, Legal);
772 setOperationAction(ISD::FROUND, MVT::v4f64, Legal);
774 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
775 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
776 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
777 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
779 setOperationAction(ISD::FNEARBYINT, MVT::v4f64, Expand);
780 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Expand);
782 // These need to set FE_INEXACT, and so cannot be vectorized here.
783 setOperationAction(ISD::FRINT, MVT::v4f64, Expand);
784 setOperationAction(ISD::FRINT, MVT::v4f32, Expand);
786 if (TM.Options.UnsafeFPMath) {
787 setOperationAction(ISD::FDIV, MVT::v4f64, Legal);
788 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
790 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
791 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
793 setOperationAction(ISD::FDIV, MVT::v4f64, Expand);
794 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
796 setOperationAction(ISD::FDIV, MVT::v4f32, Expand);
797 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
801 if (Subtarget.has64BitSupport())
802 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
804 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, isPPC64 ? Legal : Custom);
807 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
808 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
811 setBooleanContents(ZeroOrOneBooleanContent);
813 if (Subtarget.hasAltivec()) {
814 // Altivec instructions set fields to all zeros or all ones.
815 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
819 // These libcalls are not available in 32-bit.
820 setLibcallName(RTLIB::SHL_I128, nullptr);
821 setLibcallName(RTLIB::SRL_I128, nullptr);
822 setLibcallName(RTLIB::SRA_I128, nullptr);
826 setStackPointerRegisterToSaveRestore(PPC::X1);
827 setExceptionPointerRegister(PPC::X3);
828 setExceptionSelectorRegister(PPC::X4);
830 setStackPointerRegisterToSaveRestore(PPC::R1);
831 setExceptionPointerRegister(PPC::R3);
832 setExceptionSelectorRegister(PPC::R4);
835 // We have target-specific dag combine patterns for the following nodes:
836 setTargetDAGCombine(ISD::SINT_TO_FP);
837 if (Subtarget.hasFPCVT())
838 setTargetDAGCombine(ISD::UINT_TO_FP);
839 setTargetDAGCombine(ISD::LOAD);
840 setTargetDAGCombine(ISD::STORE);
841 setTargetDAGCombine(ISD::BR_CC);
842 if (Subtarget.useCRBits())
843 setTargetDAGCombine(ISD::BRCOND);
844 setTargetDAGCombine(ISD::BSWAP);
845 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
846 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
847 setTargetDAGCombine(ISD::INTRINSIC_VOID);
849 setTargetDAGCombine(ISD::SIGN_EXTEND);
850 setTargetDAGCombine(ISD::ZERO_EXTEND);
851 setTargetDAGCombine(ISD::ANY_EXTEND);
853 if (Subtarget.useCRBits()) {
854 setTargetDAGCombine(ISD::TRUNCATE);
855 setTargetDAGCombine(ISD::SETCC);
856 setTargetDAGCombine(ISD::SELECT_CC);
859 // Use reciprocal estimates.
860 if (TM.Options.UnsafeFPMath) {
861 setTargetDAGCombine(ISD::FDIV);
862 setTargetDAGCombine(ISD::FSQRT);
865 // Darwin long double math library functions have $LDBL128 appended.
866 if (Subtarget.isDarwin()) {
867 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
868 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
869 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
870 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
871 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
872 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
873 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
874 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
875 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
876 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
879 // With 32 condition bits, we don't need to sink (and duplicate) compares
880 // aggressively in CodeGenPrep.
881 if (Subtarget.useCRBits()) {
882 setHasMultipleConditionRegisters();
883 setJumpIsExpensive();
886 setMinFunctionAlignment(2);
887 if (Subtarget.isDarwin())
888 setPrefFunctionAlignment(4);
890 switch (Subtarget.getDarwinDirective()) {
894 case PPC::DIR_E500mc:
903 setPrefFunctionAlignment(4);
904 setPrefLoopAlignment(4);
908 setInsertFencesForAtomic(true);
910 if (Subtarget.enableMachineScheduler())
911 setSchedulingPreference(Sched::Source);
913 setSchedulingPreference(Sched::Hybrid);
915 computeRegisterProperties(STI.getRegisterInfo());
917 // The Freescale cores do better with aggressive inlining of memcpy and
918 // friends. GCC uses same threshold of 128 bytes (= 32 word stores).
919 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
920 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
921 MaxStoresPerMemset = 32;
922 MaxStoresPerMemsetOptSize = 16;
923 MaxStoresPerMemcpy = 32;
924 MaxStoresPerMemcpyOptSize = 8;
925 MaxStoresPerMemmove = 32;
926 MaxStoresPerMemmoveOptSize = 8;
927 } else if (Subtarget.getDarwinDirective() == PPC::DIR_A2) {
928 // The A2 also benefits from (very) aggressive inlining of memcpy and
929 // friends. The overhead of a the function call, even when warm, can be
930 // over one hundred cycles.
931 MaxStoresPerMemset = 128;
932 MaxStoresPerMemcpy = 128;
933 MaxStoresPerMemmove = 128;
937 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
938 /// the desired ByVal argument alignment.
939 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
940 unsigned MaxMaxAlign) {
941 if (MaxAlign == MaxMaxAlign)
943 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
944 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
946 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
948 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
949 unsigned EltAlign = 0;
950 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
951 if (EltAlign > MaxAlign)
953 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
954 for (auto *EltTy : STy->elements()) {
955 unsigned EltAlign = 0;
956 getMaxByValAlign(EltTy, EltAlign, MaxMaxAlign);
957 if (EltAlign > MaxAlign)
959 if (MaxAlign == MaxMaxAlign)
965 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
966 /// function arguments in the caller parameter area.
967 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty,
968 const DataLayout &DL) const {
969 // Darwin passes everything on 4 byte boundary.
970 if (Subtarget.isDarwin())
973 // 16byte and wider vectors are passed on 16byte boundary.
974 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
975 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
976 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
977 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
981 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
982 switch ((PPCISD::NodeType)Opcode) {
983 case PPCISD::FIRST_NUMBER: break;
984 case PPCISD::FSEL: return "PPCISD::FSEL";
985 case PPCISD::FCFID: return "PPCISD::FCFID";
986 case PPCISD::FCFIDU: return "PPCISD::FCFIDU";
987 case PPCISD::FCFIDS: return "PPCISD::FCFIDS";
988 case PPCISD::FCFIDUS: return "PPCISD::FCFIDUS";
989 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
990 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
991 case PPCISD::FCTIDUZ: return "PPCISD::FCTIDUZ";
992 case PPCISD::FCTIWUZ: return "PPCISD::FCTIWUZ";
993 case PPCISD::FRE: return "PPCISD::FRE";
994 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
995 case PPCISD::STFIWX: return "PPCISD::STFIWX";
996 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
997 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
998 case PPCISD::VPERM: return "PPCISD::VPERM";
999 case PPCISD::CMPB: return "PPCISD::CMPB";
1000 case PPCISD::Hi: return "PPCISD::Hi";
1001 case PPCISD::Lo: return "PPCISD::Lo";
1002 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
1003 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
1004 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
1005 case PPCISD::SRL: return "PPCISD::SRL";
1006 case PPCISD::SRA: return "PPCISD::SRA";
1007 case PPCISD::SHL: return "PPCISD::SHL";
1008 case PPCISD::SRA_ADDZE: return "PPCISD::SRA_ADDZE";
1009 case PPCISD::CALL: return "PPCISD::CALL";
1010 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
1011 case PPCISD::MTCTR: return "PPCISD::MTCTR";
1012 case PPCISD::BCTRL: return "PPCISD::BCTRL";
1013 case PPCISD::BCTRL_LOAD_TOC: return "PPCISD::BCTRL_LOAD_TOC";
1014 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
1015 case PPCISD::READ_TIME_BASE: return "PPCISD::READ_TIME_BASE";
1016 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
1017 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
1018 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
1019 case PPCISD::MFVSR: return "PPCISD::MFVSR";
1020 case PPCISD::MTVSRA: return "PPCISD::MTVSRA";
1021 case PPCISD::MTVSRZ: return "PPCISD::MTVSRZ";
1022 case PPCISD::ANDIo_1_EQ_BIT: return "PPCISD::ANDIo_1_EQ_BIT";
1023 case PPCISD::ANDIo_1_GT_BIT: return "PPCISD::ANDIo_1_GT_BIT";
1024 case PPCISD::VCMP: return "PPCISD::VCMP";
1025 case PPCISD::VCMPo: return "PPCISD::VCMPo";
1026 case PPCISD::LBRX: return "PPCISD::LBRX";
1027 case PPCISD::STBRX: return "PPCISD::STBRX";
1028 case PPCISD::LFIWAX: return "PPCISD::LFIWAX";
1029 case PPCISD::LFIWZX: return "PPCISD::LFIWZX";
1030 case PPCISD::LXVD2X: return "PPCISD::LXVD2X";
1031 case PPCISD::STXVD2X: return "PPCISD::STXVD2X";
1032 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
1033 case PPCISD::BDNZ: return "PPCISD::BDNZ";
1034 case PPCISD::BDZ: return "PPCISD::BDZ";
1035 case PPCISD::MFFS: return "PPCISD::MFFS";
1036 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
1037 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
1038 case PPCISD::CR6SET: return "PPCISD::CR6SET";
1039 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
1040 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
1041 case PPCISD::PPC32_PICGOT: return "PPCISD::PPC32_PICGOT";
1042 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
1043 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
1044 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
1045 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
1046 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
1047 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
1048 case PPCISD::ADDI_TLSGD_L_ADDR: return "PPCISD::ADDI_TLSGD_L_ADDR";
1049 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
1050 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
1051 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
1052 case PPCISD::ADDI_TLSLD_L_ADDR: return "PPCISD::ADDI_TLSLD_L_ADDR";
1053 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
1054 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
1055 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
1056 case PPCISD::SC: return "PPCISD::SC";
1057 case PPCISD::CLRBHRB: return "PPCISD::CLRBHRB";
1058 case PPCISD::MFBHRBE: return "PPCISD::MFBHRBE";
1059 case PPCISD::RFEBB: return "PPCISD::RFEBB";
1060 case PPCISD::XXSWAPD: return "PPCISD::XXSWAPD";
1061 case PPCISD::QVFPERM: return "PPCISD::QVFPERM";
1062 case PPCISD::QVGPCI: return "PPCISD::QVGPCI";
1063 case PPCISD::QVALIGNI: return "PPCISD::QVALIGNI";
1064 case PPCISD::QVESPLATI: return "PPCISD::QVESPLATI";
1065 case PPCISD::QBFLT: return "PPCISD::QBFLT";
1066 case PPCISD::QVLFSb: return "PPCISD::QVLFSb";
1071 EVT PPCTargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &C,
1074 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
1076 if (Subtarget.hasQPX())
1077 return EVT::getVectorVT(C, MVT::i1, VT.getVectorNumElements());
1079 return VT.changeVectorElementTypeToInteger();
1082 bool PPCTargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1083 assert(VT.isFloatingPoint() && "Non-floating-point FMA?");
1087 //===----------------------------------------------------------------------===//
1088 // Node matching predicates, for use by the tblgen matching code.
1089 //===----------------------------------------------------------------------===//
1091 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
1092 static bool isFloatingPointZero(SDValue Op) {
1093 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
1094 return CFP->getValueAPF().isZero();
1095 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
1096 // Maybe this has already been legalized into the constant pool?
1097 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
1098 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
1099 return CFP->getValueAPF().isZero();
1104 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
1105 /// true if Op is undef or if it matches the specified value.
1106 static bool isConstantOrUndef(int Op, int Val) {
1107 return Op < 0 || Op == Val;
1110 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
1111 /// VPKUHUM instruction.
1112 /// The ShuffleKind distinguishes between big-endian operations with
1113 /// two different inputs (0), either-endian operations with two identical
1114 /// inputs (1), and little-endian operations with two different inputs (2).
1115 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1116 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1117 SelectionDAG &DAG) {
1118 bool IsLE = DAG.getDataLayout().isLittleEndian();
1119 if (ShuffleKind == 0) {
1122 for (unsigned i = 0; i != 16; ++i)
1123 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
1125 } else if (ShuffleKind == 2) {
1128 for (unsigned i = 0; i != 16; ++i)
1129 if (!isConstantOrUndef(N->getMaskElt(i), i*2))
1131 } else if (ShuffleKind == 1) {
1132 unsigned j = IsLE ? 0 : 1;
1133 for (unsigned i = 0; i != 8; ++i)
1134 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
1135 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
1141 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
1142 /// VPKUWUM instruction.
1143 /// The ShuffleKind distinguishes between big-endian operations with
1144 /// two different inputs (0), either-endian operations with two identical
1145 /// inputs (1), and little-endian operations with two different inputs (2).
1146 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1147 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1148 SelectionDAG &DAG) {
1149 bool IsLE = DAG.getDataLayout().isLittleEndian();
1150 if (ShuffleKind == 0) {
1153 for (unsigned i = 0; i != 16; i += 2)
1154 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
1155 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
1157 } else if (ShuffleKind == 2) {
1160 for (unsigned i = 0; i != 16; i += 2)
1161 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1162 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1))
1164 } else if (ShuffleKind == 1) {
1165 unsigned j = IsLE ? 0 : 2;
1166 for (unsigned i = 0; i != 8; i += 2)
1167 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1168 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1169 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1170 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1))
1176 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
1177 /// VPKUDUM instruction, AND the VPKUDUM instruction exists for the
1178 /// current subtarget.
1180 /// The ShuffleKind distinguishes between big-endian operations with
1181 /// two different inputs (0), either-endian operations with two identical
1182 /// inputs (1), and little-endian operations with two different inputs (2).
1183 /// For the latter, the input operands are swapped (see PPCInstrAltivec.td).
1184 bool PPC::isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
1185 SelectionDAG &DAG) {
1186 const PPCSubtarget& Subtarget =
1187 static_cast<const PPCSubtarget&>(DAG.getSubtarget());
1188 if (!Subtarget.hasP8Vector())
1191 bool IsLE = DAG.getDataLayout().isLittleEndian();
1192 if (ShuffleKind == 0) {
1195 for (unsigned i = 0; i != 16; i += 4)
1196 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+4) ||
1197 !isConstantOrUndef(N->getMaskElt(i+1), i*2+5) ||
1198 !isConstantOrUndef(N->getMaskElt(i+2), i*2+6) ||
1199 !isConstantOrUndef(N->getMaskElt(i+3), i*2+7))
1201 } else if (ShuffleKind == 2) {
1204 for (unsigned i = 0; i != 16; i += 4)
1205 if (!isConstantOrUndef(N->getMaskElt(i ), i*2) ||
1206 !isConstantOrUndef(N->getMaskElt(i+1), i*2+1) ||
1207 !isConstantOrUndef(N->getMaskElt(i+2), i*2+2) ||
1208 !isConstantOrUndef(N->getMaskElt(i+3), i*2+3))
1210 } else if (ShuffleKind == 1) {
1211 unsigned j = IsLE ? 0 : 4;
1212 for (unsigned i = 0; i != 8; i += 4)
1213 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
1214 !isConstantOrUndef(N->getMaskElt(i+1), i*2+j+1) ||
1215 !isConstantOrUndef(N->getMaskElt(i+2), i*2+j+2) ||
1216 !isConstantOrUndef(N->getMaskElt(i+3), i*2+j+3) ||
1217 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
1218 !isConstantOrUndef(N->getMaskElt(i+9), i*2+j+1) ||
1219 !isConstantOrUndef(N->getMaskElt(i+10), i*2+j+2) ||
1220 !isConstantOrUndef(N->getMaskElt(i+11), i*2+j+3))
1226 /// isVMerge - Common function, used to match vmrg* shuffles.
1228 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
1229 unsigned LHSStart, unsigned RHSStart) {
1230 if (N->getValueType(0) != MVT::v16i8)
1232 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
1233 "Unsupported merge size!");
1235 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
1236 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
1237 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
1238 LHSStart+j+i*UnitSize) ||
1239 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
1240 RHSStart+j+i*UnitSize))
1246 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
1247 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
1248 /// The ShuffleKind distinguishes between big-endian merges with two
1249 /// different inputs (0), either-endian merges with two identical inputs (1),
1250 /// and little-endian merges with two different inputs (2). For the latter,
1251 /// the input operands are swapped (see PPCInstrAltivec.td).
1252 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1253 unsigned ShuffleKind, SelectionDAG &DAG) {
1254 if (DAG.getDataLayout().isLittleEndian()) {
1255 if (ShuffleKind == 1) // unary
1256 return isVMerge(N, UnitSize, 0, 0);
1257 else if (ShuffleKind == 2) // swapped
1258 return isVMerge(N, UnitSize, 0, 16);
1262 if (ShuffleKind == 1) // unary
1263 return isVMerge(N, UnitSize, 8, 8);
1264 else if (ShuffleKind == 0) // normal
1265 return isVMerge(N, UnitSize, 8, 24);
1271 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
1272 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
1273 /// The ShuffleKind distinguishes between big-endian merges with two
1274 /// different inputs (0), either-endian merges with two identical inputs (1),
1275 /// and little-endian merges with two different inputs (2). For the latter,
1276 /// the input operands are swapped (see PPCInstrAltivec.td).
1277 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
1278 unsigned ShuffleKind, SelectionDAG &DAG) {
1279 if (DAG.getDataLayout().isLittleEndian()) {
1280 if (ShuffleKind == 1) // unary
1281 return isVMerge(N, UnitSize, 8, 8);
1282 else if (ShuffleKind == 2) // swapped
1283 return isVMerge(N, UnitSize, 8, 24);
1287 if (ShuffleKind == 1) // unary
1288 return isVMerge(N, UnitSize, 0, 0);
1289 else if (ShuffleKind == 0) // normal
1290 return isVMerge(N, UnitSize, 0, 16);
1297 * \brief Common function used to match vmrgew and vmrgow shuffles
1299 * The indexOffset determines whether to look for even or odd words in
1300 * the shuffle mask. This is based on the of the endianness of the target
1303 * - Use offset of 0 to check for odd elements
1304 * - Use offset of 4 to check for even elements
1306 * - Use offset of 0 to check for even elements
1307 * - Use offset of 4 to check for odd elements
1308 * A detailed description of the vector element ordering for little endian and
1309 * big endian can be found at
1310 * http://www.ibm.com/developerworks/library/l-ibm-xl-c-cpp-compiler/index.html
1311 * Targeting your applications - what little endian and big endian IBM XL C/C++
1312 * compiler differences mean to you
1314 * The mask to the shuffle vector instruction specifies the indices of the
1315 * elements from the two input vectors to place in the result. The elements are
1316 * numbered in array-access order, starting with the first vector. These vectors
1317 * are always of type v16i8, thus each vector will contain 16 elements of size
1318 * 8. More info on the shuffle vector can be found in the
1319 * http://llvm.org/docs/LangRef.html#shufflevector-instruction
1320 * Language Reference.
1322 * The RHSStartValue indicates whether the same input vectors are used (unary)
1323 * or two different input vectors are used, based on the following:
1324 * - If the instruction uses the same vector for both inputs, the range of the
1325 * indices will be 0 to 15. In this case, the RHSStart value passed should
1327 * - If the instruction has two different vectors then the range of the
1328 * indices will be 0 to 31. In this case, the RHSStart value passed should
1329 * be 16 (indices 0-15 specify elements in the first vector while indices 16
1330 * to 31 specify elements in the second vector).
1332 * \param[in] N The shuffle vector SD Node to analyze
1333 * \param[in] IndexOffset Specifies whether to look for even or odd elements
1334 * \param[in] RHSStartValue Specifies the starting index for the righthand input
1335 * vector to the shuffle_vector instruction
1336 * \return true iff this shuffle vector represents an even or odd word merge
1338 static bool isVMerge(ShuffleVectorSDNode *N, unsigned IndexOffset,
1339 unsigned RHSStartValue) {
1340 if (N->getValueType(0) != MVT::v16i8)
1343 for (unsigned i = 0; i < 2; ++i)
1344 for (unsigned j = 0; j < 4; ++j)
1345 if (!isConstantOrUndef(N->getMaskElt(i*4+j),
1346 i*RHSStartValue+j+IndexOffset) ||
1347 !isConstantOrUndef(N->getMaskElt(i*4+j+8),
1348 i*RHSStartValue+j+IndexOffset+8))
1354 * \brief Determine if the specified shuffle mask is suitable for the vmrgew or
1355 * vmrgow instructions.
1357 * \param[in] N The shuffle vector SD Node to analyze
1358 * \param[in] CheckEven Check for an even merge (true) or an odd merge (false)
1359 * \param[in] ShuffleKind Identify the type of merge:
1360 * - 0 = big-endian merge with two different inputs;
1361 * - 1 = either-endian merge with two identical inputs;
1362 * - 2 = little-endian merge with two different inputs (inputs are swapped for
1363 * little-endian merges).
1364 * \param[in] DAG The current SelectionDAG
1365 * \return true iff this shuffle mask
1367 bool PPC::isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
1368 unsigned ShuffleKind, SelectionDAG &DAG) {
1369 if (DAG.getDataLayout().isLittleEndian()) {
1370 unsigned indexOffset = CheckEven ? 4 : 0;
1371 if (ShuffleKind == 1) // Unary
1372 return isVMerge(N, indexOffset, 0);
1373 else if (ShuffleKind == 2) // swapped
1374 return isVMerge(N, indexOffset, 16);
1379 unsigned indexOffset = CheckEven ? 0 : 4;
1380 if (ShuffleKind == 1) // Unary
1381 return isVMerge(N, indexOffset, 0);
1382 else if (ShuffleKind == 0) // Normal
1383 return isVMerge(N, indexOffset, 16);
1390 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
1391 /// amount, otherwise return -1.
1392 /// The ShuffleKind distinguishes between big-endian operations with two
1393 /// different inputs (0), either-endian operations with two identical inputs
1394 /// (1), and little-endian operations with two different inputs (2). For the
1395 /// latter, the input operands are swapped (see PPCInstrAltivec.td).
1396 int PPC::isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
1397 SelectionDAG &DAG) {
1398 if (N->getValueType(0) != MVT::v16i8)
1401 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1403 // Find the first non-undef value in the shuffle mask.
1405 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
1408 if (i == 16) return -1; // all undef.
1410 // Otherwise, check to see if the rest of the elements are consecutively
1411 // numbered from this value.
1412 unsigned ShiftAmt = SVOp->getMaskElt(i);
1413 if (ShiftAmt < i) return -1;
1416 bool isLE = DAG.getDataLayout().isLittleEndian();
1418 if ((ShuffleKind == 0 && !isLE) || (ShuffleKind == 2 && isLE)) {
1419 // Check the rest of the elements to see if they are consecutive.
1420 for (++i; i != 16; ++i)
1421 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1423 } else if (ShuffleKind == 1) {
1424 // Check the rest of the elements to see if they are consecutive.
1425 for (++i; i != 16; ++i)
1426 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1432 ShiftAmt = 16 - ShiftAmt;
1437 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1438 /// specifies a splat of a single element that is suitable for input to
1439 /// VSPLTB/VSPLTH/VSPLTW.
1440 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1441 assert(N->getValueType(0) == MVT::v16i8 &&
1442 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1444 // The consecutive indices need to specify an element, not part of two
1445 // different elements. So abandon ship early if this isn't the case.
1446 if (N->getMaskElt(0) % EltSize != 0)
1449 // This is a splat operation if each element of the permute is the same, and
1450 // if the value doesn't reference the second vector.
1451 unsigned ElementBase = N->getMaskElt(0);
1453 // FIXME: Handle UNDEF elements too!
1454 if (ElementBase >= 16)
1457 // Check that the indices are consecutive, in the case of a multi-byte element
1458 // splatted with a v16i8 mask.
1459 for (unsigned i = 1; i != EltSize; ++i)
1460 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1463 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1464 if (N->getMaskElt(i) < 0) continue;
1465 for (unsigned j = 0; j != EltSize; ++j)
1466 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1472 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1473 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1474 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1475 SelectionDAG &DAG) {
1476 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1477 assert(isSplatShuffleMask(SVOp, EltSize));
1478 if (DAG.getDataLayout().isLittleEndian())
1479 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1481 return SVOp->getMaskElt(0) / EltSize;
1484 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1485 /// by using a vspltis[bhw] instruction of the specified element size, return
1486 /// the constant being splatted. The ByteSize field indicates the number of
1487 /// bytes of each element [124] -> [bhw].
1488 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1489 SDValue OpVal(nullptr, 0);
1491 // If ByteSize of the splat is bigger than the element size of the
1492 // build_vector, then we have a case where we are checking for a splat where
1493 // multiple elements of the buildvector are folded together into a single
1494 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1495 unsigned EltSize = 16/N->getNumOperands();
1496 if (EltSize < ByteSize) {
1497 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1498 SDValue UniquedVals[4];
1499 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1501 // See if all of the elements in the buildvector agree across.
1502 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1503 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1504 // If the element isn't a constant, bail fully out.
1505 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1508 if (!UniquedVals[i&(Multiple-1)].getNode())
1509 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1510 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1511 return SDValue(); // no match.
1514 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1515 // either constant or undef values that are identical for each chunk. See
1516 // if these chunks can form into a larger vspltis*.
1518 // Check to see if all of the leading entries are either 0 or -1. If
1519 // neither, then this won't fit into the immediate field.
1520 bool LeadingZero = true;
1521 bool LeadingOnes = true;
1522 for (unsigned i = 0; i != Multiple-1; ++i) {
1523 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1525 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1526 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1528 // Finally, check the least significant entry.
1530 if (!UniquedVals[Multiple-1].getNode())
1531 return DAG.getTargetConstant(0, SDLoc(N), MVT::i32); // 0,0,0,undef
1532 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1533 if (Val < 16) // 0,0,0,4 -> vspltisw(4)
1534 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1537 if (!UniquedVals[Multiple-1].getNode())
1538 return DAG.getTargetConstant(~0U, SDLoc(N), MVT::i32); // -1,-1,-1,undef
1539 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1540 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1541 return DAG.getTargetConstant(Val, SDLoc(N), MVT::i32);
1547 // Check to see if this buildvec has a single non-undef value in its elements.
1548 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1549 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1550 if (!OpVal.getNode())
1551 OpVal = N->getOperand(i);
1552 else if (OpVal != N->getOperand(i))
1556 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1558 unsigned ValSizeInBytes = EltSize;
1560 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1561 Value = CN->getZExtValue();
1562 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1563 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1564 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1567 // If the splat value is larger than the element value, then we can never do
1568 // this splat. The only case that we could fit the replicated bits into our
1569 // immediate field for would be zero, and we prefer to use vxor for it.
1570 if (ValSizeInBytes < ByteSize) return SDValue();
1572 // If the element value is larger than the splat value, check if it consists
1573 // of a repeated bit pattern of size ByteSize.
1574 if (!APInt(ValSizeInBytes * 8, Value).isSplat(ByteSize * 8))
1577 // Properly sign extend the value.
1578 int MaskVal = SignExtend32(Value, ByteSize * 8);
1580 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1581 if (MaskVal == 0) return SDValue();
1583 // Finally, if this value fits in a 5 bit sext field, return it
1584 if (SignExtend32<5>(MaskVal) == MaskVal)
1585 return DAG.getTargetConstant(MaskVal, SDLoc(N), MVT::i32);
1589 /// isQVALIGNIShuffleMask - If this is a qvaligni shuffle mask, return the shift
1590 /// amount, otherwise return -1.
1591 int PPC::isQVALIGNIShuffleMask(SDNode *N) {
1592 EVT VT = N->getValueType(0);
1593 if (VT != MVT::v4f64 && VT != MVT::v4f32 && VT != MVT::v4i1)
1596 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1598 // Find the first non-undef value in the shuffle mask.
1600 for (i = 0; i != 4 && SVOp->getMaskElt(i) < 0; ++i)
1603 if (i == 4) return -1; // all undef.
1605 // Otherwise, check to see if the rest of the elements are consecutively
1606 // numbered from this value.
1607 unsigned ShiftAmt = SVOp->getMaskElt(i);
1608 if (ShiftAmt < i) return -1;
1611 // Check the rest of the elements to see if they are consecutive.
1612 for (++i; i != 4; ++i)
1613 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
1619 //===----------------------------------------------------------------------===//
1620 // Addressing Mode Selection
1621 //===----------------------------------------------------------------------===//
1623 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1624 /// or 64-bit immediate, and if the value can be accurately represented as a
1625 /// sign extension from a 16-bit value. If so, this returns true and the
1627 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1628 if (!isa<ConstantSDNode>(N))
1631 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1632 if (N->getValueType(0) == MVT::i32)
1633 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1635 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1637 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1638 return isIntS16Immediate(Op.getNode(), Imm);
1642 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1643 /// can be represented as an indexed [r+r] operation. Returns false if it
1644 /// can be more efficiently represented with [r+imm].
1645 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1647 SelectionDAG &DAG) const {
1649 if (N.getOpcode() == ISD::ADD) {
1650 if (isIntS16Immediate(N.getOperand(1), imm))
1651 return false; // r+i
1652 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1653 return false; // r+i
1655 Base = N.getOperand(0);
1656 Index = N.getOperand(1);
1658 } else if (N.getOpcode() == ISD::OR) {
1659 if (isIntS16Immediate(N.getOperand(1), imm))
1660 return false; // r+i can fold it if we can.
1662 // If this is an or of disjoint bitfields, we can codegen this as an add
1663 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1665 APInt LHSKnownZero, LHSKnownOne;
1666 APInt RHSKnownZero, RHSKnownOne;
1667 DAG.computeKnownBits(N.getOperand(0),
1668 LHSKnownZero, LHSKnownOne);
1670 if (LHSKnownZero.getBoolValue()) {
1671 DAG.computeKnownBits(N.getOperand(1),
1672 RHSKnownZero, RHSKnownOne);
1673 // If all of the bits are known zero on the LHS or RHS, the add won't
1675 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1676 Base = N.getOperand(0);
1677 Index = N.getOperand(1);
1686 // If we happen to be doing an i64 load or store into a stack slot that has
1687 // less than a 4-byte alignment, then the frame-index elimination may need to
1688 // use an indexed load or store instruction (because the offset may not be a
1689 // multiple of 4). The extra register needed to hold the offset comes from the
1690 // register scavenger, and it is possible that the scavenger will need to use
1691 // an emergency spill slot. As a result, we need to make sure that a spill slot
1692 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1694 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1695 // FIXME: This does not handle the LWA case.
1699 // NOTE: We'll exclude negative FIs here, which come from argument
1700 // lowering, because there are no known test cases triggering this problem
1701 // using packed structures (or similar). We can remove this exclusion if
1702 // we find such a test case. The reason why this is so test-case driven is
1703 // because this entire 'fixup' is only to prevent crashes (from the
1704 // register scavenger) on not-really-valid inputs. For example, if we have:
1706 // %b = bitcast i1* %a to i64*
1707 // store i64* a, i64 b
1708 // then the store should really be marked as 'align 1', but is not. If it
1709 // were marked as 'align 1' then the indexed form would have been
1710 // instruction-selected initially, and the problem this 'fixup' is preventing
1711 // won't happen regardless.
1715 MachineFunction &MF = DAG.getMachineFunction();
1716 MachineFrameInfo *MFI = MF.getFrameInfo();
1718 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1722 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1723 FuncInfo->setHasNonRISpills();
1726 /// Returns true if the address N can be represented by a base register plus
1727 /// a signed 16-bit displacement [r+imm], and if it is not better
1728 /// represented as reg+reg. If Aligned is true, only accept displacements
1729 /// suitable for STD and friends, i.e. multiples of 4.
1730 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1733 bool Aligned) const {
1734 // FIXME dl should come from parent load or store, not from address
1736 // If this can be more profitably realized as r+r, fail.
1737 if (SelectAddressRegReg(N, Disp, Base, DAG))
1740 if (N.getOpcode() == ISD::ADD) {
1742 if (isIntS16Immediate(N.getOperand(1), imm) &&
1743 (!Aligned || (imm & 3) == 0)) {
1744 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1745 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1746 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1747 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1749 Base = N.getOperand(0);
1751 return true; // [r+i]
1752 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1753 // Match LOAD (ADD (X, Lo(G))).
1754 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1755 && "Cannot handle constant offsets yet!");
1756 Disp = N.getOperand(1).getOperand(0); // The global address.
1757 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1758 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1759 Disp.getOpcode() == ISD::TargetConstantPool ||
1760 Disp.getOpcode() == ISD::TargetJumpTable);
1761 Base = N.getOperand(0);
1762 return true; // [&g+r]
1764 } else if (N.getOpcode() == ISD::OR) {
1766 if (isIntS16Immediate(N.getOperand(1), imm) &&
1767 (!Aligned || (imm & 3) == 0)) {
1768 // If this is an or of disjoint bitfields, we can codegen this as an add
1769 // (for better address arithmetic) if the LHS and RHS of the OR are
1770 // provably disjoint.
1771 APInt LHSKnownZero, LHSKnownOne;
1772 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1774 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1775 // If all of the bits are known zero on the LHS or RHS, the add won't
1777 if (FrameIndexSDNode *FI =
1778 dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1779 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1780 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1782 Base = N.getOperand(0);
1784 Disp = DAG.getTargetConstant(imm, dl, N.getValueType());
1788 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1789 // Loading from a constant address.
1791 // If this address fits entirely in a 16-bit sext immediate field, codegen
1794 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1795 Disp = DAG.getTargetConstant(Imm, dl, CN->getValueType(0));
1796 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1797 CN->getValueType(0));
1801 // Handle 32-bit sext immediates with LIS + addr mode.
1802 if ((CN->getValueType(0) == MVT::i32 ||
1803 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1804 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1805 int Addr = (int)CN->getZExtValue();
1807 // Otherwise, break this down into an LIS + disp.
1808 Disp = DAG.getTargetConstant((short)Addr, dl, MVT::i32);
1810 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, dl,
1812 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1813 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1818 Disp = DAG.getTargetConstant(0, dl, getPointerTy(DAG.getDataLayout()));
1819 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1820 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1821 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1824 return true; // [r+0]
1827 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1828 /// represented as an indexed [r+r] operation.
1829 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1831 SelectionDAG &DAG) const {
1832 // Check to see if we can easily represent this as an [r+r] address. This
1833 // will fail if it thinks that the address is more profitably represented as
1834 // reg+imm, e.g. where imm = 0.
1835 if (SelectAddressRegReg(N, Base, Index, DAG))
1838 // If the operand is an addition, always emit this as [r+r], since this is
1839 // better (for code size, and execution, as the memop does the add for free)
1840 // than emitting an explicit add.
1841 if (N.getOpcode() == ISD::ADD) {
1842 Base = N.getOperand(0);
1843 Index = N.getOperand(1);
1847 // Otherwise, do it the hard way, using R0 as the base register.
1848 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1854 /// getPreIndexedAddressParts - returns true by value, base pointer and
1855 /// offset pointer and addressing mode by reference if the node's address
1856 /// can be legally represented as pre-indexed load / store address.
1857 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1859 ISD::MemIndexedMode &AM,
1860 SelectionDAG &DAG) const {
1861 if (DisablePPCPreinc) return false;
1867 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1868 Ptr = LD->getBasePtr();
1869 VT = LD->getMemoryVT();
1870 Alignment = LD->getAlignment();
1871 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1872 Ptr = ST->getBasePtr();
1873 VT = ST->getMemoryVT();
1874 Alignment = ST->getAlignment();
1879 // PowerPC doesn't have preinc load/store instructions for vectors (except
1880 // for QPX, which does have preinc r+r forms).
1881 if (VT.isVector()) {
1882 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) {
1884 } else if (SelectAddressRegRegOnly(Ptr, Offset, Base, DAG)) {
1890 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1892 // Common code will reject creating a pre-inc form if the base pointer
1893 // is a frame index, or if N is a store and the base pointer is either
1894 // the same as or a predecessor of the value being stored. Check for
1895 // those situations here, and try with swapped Base/Offset instead.
1898 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1901 SDValue Val = cast<StoreSDNode>(N)->getValue();
1902 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1907 std::swap(Base, Offset);
1913 // LDU/STU can only handle immediates that are a multiple of 4.
1914 if (VT != MVT::i64) {
1915 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1918 // LDU/STU need an address with at least 4-byte alignment.
1922 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1926 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1927 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1928 // sext i32 to i64 when addr mode is r+i.
1929 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1930 LD->getExtensionType() == ISD::SEXTLOAD &&
1931 isa<ConstantSDNode>(Offset))
1939 //===----------------------------------------------------------------------===//
1940 // LowerOperation implementation
1941 //===----------------------------------------------------------------------===//
1943 /// GetLabelAccessInfo - Return true if we should reference labels using a
1944 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1945 static bool GetLabelAccessInfo(const TargetMachine &TM,
1946 const PPCSubtarget &Subtarget,
1947 unsigned &HiOpFlags, unsigned &LoOpFlags,
1948 const GlobalValue *GV = nullptr) {
1949 HiOpFlags = PPCII::MO_HA;
1950 LoOpFlags = PPCII::MO_LO;
1952 // Don't use the pic base if not in PIC relocation model.
1953 bool isPIC = TM.getRelocationModel() == Reloc::PIC_;
1956 HiOpFlags |= PPCII::MO_PIC_FLAG;
1957 LoOpFlags |= PPCII::MO_PIC_FLAG;
1960 // If this is a reference to a global value that requires a non-lazy-ptr, make
1961 // sure that instruction lowering adds it.
1962 if (GV && Subtarget.hasLazyResolverStub(GV)) {
1963 HiOpFlags |= PPCII::MO_NLP_FLAG;
1964 LoOpFlags |= PPCII::MO_NLP_FLAG;
1966 if (GV->hasHiddenVisibility()) {
1967 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1968 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1975 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1976 SelectionDAG &DAG) {
1978 EVT PtrVT = HiPart.getValueType();
1979 SDValue Zero = DAG.getConstant(0, DL, PtrVT);
1981 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1982 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1984 // With PIC, the first instruction is actually "GR+hi(&G)".
1986 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1987 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1989 // Generate non-pic code that has direct accesses to the constant pool.
1990 // The address of the global is just (hi(&g)+lo(&g)).
1991 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1994 static void setUsesTOCBasePtr(MachineFunction &MF) {
1995 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1996 FuncInfo->setUsesTOCBasePtr();
1999 static void setUsesTOCBasePtr(SelectionDAG &DAG) {
2000 setUsesTOCBasePtr(DAG.getMachineFunction());
2003 static SDValue getTOCEntry(SelectionDAG &DAG, SDLoc dl, bool Is64Bit,
2005 EVT VT = Is64Bit ? MVT::i64 : MVT::i32;
2006 SDValue Reg = Is64Bit ? DAG.getRegister(PPC::X2, VT) :
2007 DAG.getNode(PPCISD::GlobalBaseReg, dl, VT);
2009 SDValue Ops[] = { GA, Reg };
2010 return DAG.getMemIntrinsicNode(
2011 PPCISD::TOC_ENTRY, dl, DAG.getVTList(VT, MVT::Other), Ops, VT,
2012 MachinePointerInfo::getGOT(DAG.getMachineFunction()), 0, false, true,
2016 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
2017 SelectionDAG &DAG) const {
2018 EVT PtrVT = Op.getValueType();
2019 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
2020 const Constant *C = CP->getConstVal();
2022 // 64-bit SVR4 ABI code is always position-independent.
2023 // The actual address of the GlobalValue is stored in the TOC.
2024 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2025 setUsesTOCBasePtr(DAG);
2026 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
2027 return getTOCEntry(DAG, SDLoc(CP), true, GA);
2030 unsigned MOHiFlag, MOLoFlag;
2032 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2034 if (isPIC && Subtarget.isSVR4ABI()) {
2035 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(),
2036 PPCII::MO_PIC_FLAG);
2037 return getTOCEntry(DAG, SDLoc(CP), false, GA);
2041 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
2043 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
2044 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
2047 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
2048 EVT PtrVT = Op.getValueType();
2049 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
2051 // 64-bit SVR4 ABI code is always position-independent.
2052 // The actual address of the GlobalValue is stored in the TOC.
2053 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2054 setUsesTOCBasePtr(DAG);
2055 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2056 return getTOCEntry(DAG, SDLoc(JT), true, GA);
2059 unsigned MOHiFlag, MOLoFlag;
2061 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2063 if (isPIC && Subtarget.isSVR4ABI()) {
2064 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT,
2065 PPCII::MO_PIC_FLAG);
2066 return getTOCEntry(DAG, SDLoc(GA), false, GA);
2069 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
2070 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
2071 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
2074 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
2075 SelectionDAG &DAG) const {
2076 EVT PtrVT = Op.getValueType();
2077 BlockAddressSDNode *BASDN = cast<BlockAddressSDNode>(Op);
2078 const BlockAddress *BA = BASDN->getBlockAddress();
2080 // 64-bit SVR4 ABI code is always position-independent.
2081 // The actual BlockAddress is stored in the TOC.
2082 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2083 setUsesTOCBasePtr(DAG);
2084 SDValue GA = DAG.getTargetBlockAddress(BA, PtrVT, BASDN->getOffset());
2085 return getTOCEntry(DAG, SDLoc(BASDN), true, GA);
2088 unsigned MOHiFlag, MOLoFlag;
2090 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag);
2091 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
2092 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
2093 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
2096 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
2097 SelectionDAG &DAG) const {
2099 // FIXME: TLS addresses currently use medium model code sequences,
2100 // which is the most useful form. Eventually support for small and
2101 // large models could be added if users need it, at the cost of
2102 // additional complexity.
2103 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
2104 if (DAG.getTarget().Options.EmulatedTLS)
2105 return LowerToTLSEmulatedModel(GA, DAG);
2108 const GlobalValue *GV = GA->getGlobal();
2109 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2110 bool is64bit = Subtarget.isPPC64();
2111 const Module *M = DAG.getMachineFunction().getFunction()->getParent();
2112 PICLevel::Level picLevel = M->getPICLevel();
2114 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
2116 if (Model == TLSModel::LocalExec) {
2117 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2118 PPCII::MO_TPREL_HA);
2119 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2120 PPCII::MO_TPREL_LO);
2121 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
2122 is64bit ? MVT::i64 : MVT::i32);
2123 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
2124 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
2127 if (Model == TLSModel::InitialExec) {
2128 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2129 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
2133 setUsesTOCBasePtr(DAG);
2134 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2135 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
2136 PtrVT, GOTReg, TGA);
2138 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
2139 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
2140 PtrVT, TGA, GOTPtr);
2141 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
2144 if (Model == TLSModel::GeneralDynamic) {
2145 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2148 setUsesTOCBasePtr(DAG);
2149 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2150 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
2153 if (picLevel == PICLevel::Small)
2154 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2156 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2158 return DAG.getNode(PPCISD::ADDI_TLSGD_L_ADDR, dl, PtrVT,
2162 if (Model == TLSModel::LocalDynamic) {
2163 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
2166 setUsesTOCBasePtr(DAG);
2167 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
2168 GOTPtr = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
2171 if (picLevel == PICLevel::Small)
2172 GOTPtr = DAG.getNode(PPCISD::GlobalBaseReg, dl, PtrVT);
2174 GOTPtr = DAG.getNode(PPCISD::PPC32_PICGOT, dl, PtrVT);
2176 SDValue TLSAddr = DAG.getNode(PPCISD::ADDI_TLSLD_L_ADDR, dl,
2177 PtrVT, GOTPtr, TGA, TGA);
2178 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl,
2179 PtrVT, TLSAddr, TGA);
2180 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
2183 llvm_unreachable("Unknown TLS model!");
2186 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
2187 SelectionDAG &DAG) const {
2188 EVT PtrVT = Op.getValueType();
2189 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
2191 const GlobalValue *GV = GSDN->getGlobal();
2193 // 64-bit SVR4 ABI code is always position-independent.
2194 // The actual address of the GlobalValue is stored in the TOC.
2195 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
2196 setUsesTOCBasePtr(DAG);
2197 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
2198 return getTOCEntry(DAG, DL, true, GA);
2201 unsigned MOHiFlag, MOLoFlag;
2203 GetLabelAccessInfo(DAG.getTarget(), Subtarget, MOHiFlag, MOLoFlag, GV);
2205 if (isPIC && Subtarget.isSVR4ABI()) {
2206 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT,
2208 PPCII::MO_PIC_FLAG);
2209 return getTOCEntry(DAG, DL, false, GA);
2213 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
2215 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
2217 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
2219 // If the global reference is actually to a non-lazy-pointer, we have to do an
2220 // extra load to get the address of the global.
2221 if (MOHiFlag & PPCII::MO_NLP_FLAG)
2222 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
2223 false, false, false, 0);
2227 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
2228 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2231 if (Op.getValueType() == MVT::v2i64) {
2232 // When the operands themselves are v2i64 values, we need to do something
2233 // special because VSX has no underlying comparison operations for these.
2234 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
2235 // Equality can be handled by casting to the legal type for Altivec
2236 // comparisons, everything else needs to be expanded.
2237 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
2238 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
2239 DAG.getSetCC(dl, MVT::v4i32,
2240 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
2241 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
2248 // We handle most of these in the usual way.
2252 // If we're comparing for equality to zero, expose the fact that this is
2253 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
2254 // fold the new nodes.
2255 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
2256 if (C->isNullValue() && CC == ISD::SETEQ) {
2257 EVT VT = Op.getOperand(0).getValueType();
2258 SDValue Zext = Op.getOperand(0);
2259 if (VT.bitsLT(MVT::i32)) {
2261 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
2263 unsigned Log2b = Log2_32(VT.getSizeInBits());
2264 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
2265 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
2266 DAG.getConstant(Log2b, dl, MVT::i32));
2267 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
2269 // Leave comparisons against 0 and -1 alone for now, since they're usually
2270 // optimized. FIXME: revisit this when we can custom lower all setcc
2272 if (C->isAllOnesValue() || C->isNullValue())
2276 // If we have an integer seteq/setne, turn it into a compare against zero
2277 // by xor'ing the rhs with the lhs, which is faster than setting a
2278 // condition register, reading it back out, and masking the correct bit. The
2279 // normal approach here uses sub to do this instead of xor. Using xor exposes
2280 // the result to other bit-twiddling opportunities.
2281 EVT LHSVT = Op.getOperand(0).getValueType();
2282 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
2283 EVT VT = Op.getValueType();
2284 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
2286 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, dl, LHSVT), CC);
2291 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
2292 const PPCSubtarget &Subtarget) const {
2293 SDNode *Node = Op.getNode();
2294 EVT VT = Node->getValueType(0);
2295 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2296 SDValue InChain = Node->getOperand(0);
2297 SDValue VAListPtr = Node->getOperand(1);
2298 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2301 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
2304 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2305 VAListPtr, MachinePointerInfo(SV), MVT::i8,
2306 false, false, false, 0);
2307 InChain = GprIndex.getValue(1);
2309 if (VT == MVT::i64) {
2310 // Check if GprIndex is even
2311 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
2312 DAG.getConstant(1, dl, MVT::i32));
2313 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
2314 DAG.getConstant(0, dl, MVT::i32), ISD::SETNE);
2315 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
2316 DAG.getConstant(1, dl, MVT::i32));
2317 // Align GprIndex to be even if it isn't
2318 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
2322 // fpr index is 1 byte after gpr
2323 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2324 DAG.getConstant(1, dl, MVT::i32));
2327 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
2328 FprPtr, MachinePointerInfo(SV), MVT::i8,
2329 false, false, false, 0);
2330 InChain = FprIndex.getValue(1);
2332 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2333 DAG.getConstant(8, dl, MVT::i32));
2335 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
2336 DAG.getConstant(4, dl, MVT::i32));
2339 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
2340 MachinePointerInfo(), false, false,
2342 InChain = OverflowArea.getValue(1);
2344 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
2345 MachinePointerInfo(), false, false,
2347 InChain = RegSaveArea.getValue(1);
2349 // select overflow_area if index > 8
2350 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
2351 DAG.getConstant(8, dl, MVT::i32), ISD::SETLT);
2353 // adjustment constant gpr_index * 4/8
2354 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
2355 VT.isInteger() ? GprIndex : FprIndex,
2356 DAG.getConstant(VT.isInteger() ? 4 : 8, dl,
2359 // OurReg = RegSaveArea + RegConstant
2360 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
2363 // Floating types are 32 bytes into RegSaveArea
2364 if (VT.isFloatingPoint())
2365 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
2366 DAG.getConstant(32, dl, MVT::i32));
2368 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
2369 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
2370 VT.isInteger() ? GprIndex : FprIndex,
2371 DAG.getConstant(VT == MVT::i64 ? 2 : 1, dl,
2374 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
2375 VT.isInteger() ? VAListPtr : FprPtr,
2376 MachinePointerInfo(SV),
2377 MVT::i8, false, false, 0);
2379 // determine if we should load from reg_save_area or overflow_area
2380 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
2382 // increase overflow_area by 4/8 if gpr/fpr > 8
2383 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
2384 DAG.getConstant(VT.isInteger() ? 4 : 8,
2387 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
2390 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
2392 MachinePointerInfo(),
2393 MVT::i32, false, false, 0);
2395 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
2396 false, false, false, 0);
2399 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
2400 const PPCSubtarget &Subtarget) const {
2401 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
2403 // We have to copy the entire va_list struct:
2404 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
2405 return DAG.getMemcpy(Op.getOperand(0), Op,
2406 Op.getOperand(1), Op.getOperand(2),
2407 DAG.getConstant(12, SDLoc(Op), MVT::i32), 8, false, true,
2408 false, MachinePointerInfo(), MachinePointerInfo());
2411 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
2412 SelectionDAG &DAG) const {
2413 return Op.getOperand(0);
2416 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
2417 SelectionDAG &DAG) const {
2418 SDValue Chain = Op.getOperand(0);
2419 SDValue Trmp = Op.getOperand(1); // trampoline
2420 SDValue FPtr = Op.getOperand(2); // nested function
2421 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
2424 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
2425 bool isPPC64 = (PtrVT == MVT::i64);
2426 Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
2428 TargetLowering::ArgListTy Args;
2429 TargetLowering::ArgListEntry Entry;
2431 Entry.Ty = IntPtrTy;
2432 Entry.Node = Trmp; Args.push_back(Entry);
2434 // TrampSize == (isPPC64 ? 48 : 40);
2435 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40, dl,
2436 isPPC64 ? MVT::i64 : MVT::i32);
2437 Args.push_back(Entry);
2439 Entry.Node = FPtr; Args.push_back(Entry);
2440 Entry.Node = Nest; Args.push_back(Entry);
2442 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
2443 TargetLowering::CallLoweringInfo CLI(DAG);
2444 CLI.setDebugLoc(dl).setChain(Chain)
2445 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
2446 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
2447 std::move(Args), 0);
2449 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
2450 return CallResult.second;
2453 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
2454 const PPCSubtarget &Subtarget) const {
2455 MachineFunction &MF = DAG.getMachineFunction();
2456 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2460 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
2461 // vastart just stores the address of the VarArgsFrameIndex slot into the
2462 // memory location argument.
2463 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2464 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2465 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2466 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
2467 MachinePointerInfo(SV),
2471 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
2472 // We suppose the given va_list is already allocated.
2475 // char gpr; /* index into the array of 8 GPRs
2476 // * stored in the register save area
2477 // * gpr=0 corresponds to r3,
2478 // * gpr=1 to r4, etc.
2480 // char fpr; /* index into the array of 8 FPRs
2481 // * stored in the register save area
2482 // * fpr=0 corresponds to f1,
2483 // * fpr=1 to f2, etc.
2485 // char *overflow_arg_area;
2486 // /* location on stack that holds
2487 // * the next overflow argument
2489 // char *reg_save_area;
2490 // /* where r3:r10 and f1:f8 (if saved)
2496 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), dl, MVT::i32);
2497 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), dl, MVT::i32);
2499 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2501 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
2503 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
2506 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2507 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, dl, PtrVT);
2509 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2510 SDValue ConstStackOffset = DAG.getConstant(StackOffset, dl, PtrVT);
2512 uint64_t FPROffset = 1;
2513 SDValue ConstFPROffset = DAG.getConstant(FPROffset, dl, PtrVT);
2515 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2517 // Store first byte : number of int regs
2518 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2520 MachinePointerInfo(SV),
2521 MVT::i8, false, false, 0);
2522 uint64_t nextOffset = FPROffset;
2523 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2526 // Store second byte : number of float regs
2527 SDValue secondStore =
2528 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2529 MachinePointerInfo(SV, nextOffset), MVT::i8,
2531 nextOffset += StackOffset;
2532 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2534 // Store second word : arguments given on stack
2535 SDValue thirdStore =
2536 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2537 MachinePointerInfo(SV, nextOffset),
2539 nextOffset += FrameOffset;
2540 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2542 // Store third word : arguments given in registers
2543 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2544 MachinePointerInfo(SV, nextOffset),
2549 #include "PPCGenCallingConv.inc"
2551 // Function whose sole purpose is to kill compiler warnings
2552 // stemming from unused functions included from PPCGenCallingConv.inc.
2553 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2554 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2557 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2558 CCValAssign::LocInfo &LocInfo,
2559 ISD::ArgFlagsTy &ArgFlags,
2564 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2566 CCValAssign::LocInfo &LocInfo,
2567 ISD::ArgFlagsTy &ArgFlags,
2569 static const MCPhysReg ArgRegs[] = {
2570 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2571 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2573 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2575 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2577 // Skip one register if the first unallocated register has an even register
2578 // number and there are still argument registers available which have not been
2579 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2580 // need to skip a register if RegNum is odd.
2581 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2582 State.AllocateReg(ArgRegs[RegNum]);
2585 // Always return false here, as this function only makes sure that the first
2586 // unallocated register has an odd register number and does not actually
2587 // allocate a register for the current argument.
2591 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2593 CCValAssign::LocInfo &LocInfo,
2594 ISD::ArgFlagsTy &ArgFlags,
2596 static const MCPhysReg ArgRegs[] = {
2597 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2601 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2603 unsigned RegNum = State.getFirstUnallocated(ArgRegs);
2605 // If there is only one Floating-point register left we need to put both f64
2606 // values of a split ppc_fp128 value on the stack.
2607 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2608 State.AllocateReg(ArgRegs[RegNum]);
2611 // Always return false here, as this function only makes sure that the two f64
2612 // values a ppc_fp128 value is split into are both passed in registers or both
2613 // passed on the stack and does not actually allocate a register for the
2614 // current argument.
2618 /// FPR - The set of FP registers that should be allocated for arguments,
2620 static const MCPhysReg FPR[] = {PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5,
2621 PPC::F6, PPC::F7, PPC::F8, PPC::F9, PPC::F10,
2622 PPC::F11, PPC::F12, PPC::F13};
2624 /// QFPR - The set of QPX registers that should be allocated for arguments.
2625 static const MCPhysReg QFPR[] = {
2626 PPC::QF1, PPC::QF2, PPC::QF3, PPC::QF4, PPC::QF5, PPC::QF6, PPC::QF7,
2627 PPC::QF8, PPC::QF9, PPC::QF10, PPC::QF11, PPC::QF12, PPC::QF13};
2629 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2631 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2632 unsigned PtrByteSize) {
2633 unsigned ArgSize = ArgVT.getStoreSize();
2634 if (Flags.isByVal())
2635 ArgSize = Flags.getByValSize();
2637 // Round up to multiples of the pointer size, except for array members,
2638 // which are always packed.
2639 if (!Flags.isInConsecutiveRegs())
2640 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2645 /// CalculateStackSlotAlignment - Calculates the alignment of this argument
2647 static unsigned CalculateStackSlotAlignment(EVT ArgVT, EVT OrigVT,
2648 ISD::ArgFlagsTy Flags,
2649 unsigned PtrByteSize) {
2650 unsigned Align = PtrByteSize;
2652 // Altivec parameters are padded to a 16 byte boundary.
2653 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2654 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2655 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2656 ArgVT == MVT::v1i128)
2658 // QPX vector types stored in double-precision are padded to a 32 byte
2660 else if (ArgVT == MVT::v4f64 || ArgVT == MVT::v4i1)
2663 // ByVal parameters are aligned as requested.
2664 if (Flags.isByVal()) {
2665 unsigned BVAlign = Flags.getByValAlign();
2666 if (BVAlign > PtrByteSize) {
2667 if (BVAlign % PtrByteSize != 0)
2669 "ByVal alignment is not a multiple of the pointer size");
2675 // Array members are always packed to their original alignment.
2676 if (Flags.isInConsecutiveRegs()) {
2677 // If the array member was split into multiple registers, the first
2678 // needs to be aligned to the size of the full type. (Except for
2679 // ppcf128, which is only aligned as its f64 components.)
2680 if (Flags.isSplit() && OrigVT != MVT::ppcf128)
2681 Align = OrigVT.getStoreSize();
2683 Align = ArgVT.getStoreSize();
2689 /// CalculateStackSlotUsed - Return whether this argument will use its
2690 /// stack slot (instead of being passed in registers). ArgOffset,
2691 /// AvailableFPRs, and AvailableVRs must hold the current argument
2692 /// position, and will be updated to account for this argument.
2693 static bool CalculateStackSlotUsed(EVT ArgVT, EVT OrigVT,
2694 ISD::ArgFlagsTy Flags,
2695 unsigned PtrByteSize,
2696 unsigned LinkageSize,
2697 unsigned ParamAreaSize,
2698 unsigned &ArgOffset,
2699 unsigned &AvailableFPRs,
2700 unsigned &AvailableVRs, bool HasQPX) {
2701 bool UseMemory = false;
2703 // Respect alignment of argument on the stack.
2705 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
2706 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
2707 // If there's no space left in the argument save area, we must
2708 // use memory (this check also catches zero-sized arguments).
2709 if (ArgOffset >= LinkageSize + ParamAreaSize)
2712 // Allocate argument on the stack.
2713 ArgOffset += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2714 if (Flags.isInConsecutiveRegsLast())
2715 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2716 // If we overran the argument save area, we must use memory
2717 // (this check catches arguments passed partially in memory)
2718 if (ArgOffset > LinkageSize + ParamAreaSize)
2721 // However, if the argument is actually passed in an FPR or a VR,
2722 // we don't use memory after all.
2723 if (!Flags.isByVal()) {
2724 if (ArgVT == MVT::f32 || ArgVT == MVT::f64 ||
2725 // QPX registers overlap with the scalar FP registers.
2726 (HasQPX && (ArgVT == MVT::v4f32 ||
2727 ArgVT == MVT::v4f64 ||
2728 ArgVT == MVT::v4i1)))
2729 if (AvailableFPRs > 0) {
2733 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
2734 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
2735 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64 ||
2736 ArgVT == MVT::v1i128)
2737 if (AvailableVRs > 0) {
2746 /// EnsureStackAlignment - Round stack frame size up from NumBytes to
2747 /// ensure minimum alignment required for target.
2748 static unsigned EnsureStackAlignment(const PPCFrameLowering *Lowering,
2749 unsigned NumBytes) {
2750 unsigned TargetAlign = Lowering->getStackAlignment();
2751 unsigned AlignMask = TargetAlign - 1;
2752 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2757 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2758 CallingConv::ID CallConv, bool isVarArg,
2759 const SmallVectorImpl<ISD::InputArg>
2761 SDLoc dl, SelectionDAG &DAG,
2762 SmallVectorImpl<SDValue> &InVals)
2764 if (Subtarget.isSVR4ABI()) {
2765 if (Subtarget.isPPC64())
2766 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2769 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2772 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2778 PPCTargetLowering::LowerFormalArguments_32SVR4(
2780 CallingConv::ID CallConv, bool isVarArg,
2781 const SmallVectorImpl<ISD::InputArg>
2783 SDLoc dl, SelectionDAG &DAG,
2784 SmallVectorImpl<SDValue> &InVals) const {
2786 // 32-bit SVR4 ABI Stack Frame Layout:
2787 // +-----------------------------------+
2788 // +--> | Back chain |
2789 // | +-----------------------------------+
2790 // | | Floating-point register save area |
2791 // | +-----------------------------------+
2792 // | | General register save area |
2793 // | +-----------------------------------+
2794 // | | CR save word |
2795 // | +-----------------------------------+
2796 // | | VRSAVE save word |
2797 // | +-----------------------------------+
2798 // | | Alignment padding |
2799 // | +-----------------------------------+
2800 // | | Vector register save area |
2801 // | +-----------------------------------+
2802 // | | Local variable space |
2803 // | +-----------------------------------+
2804 // | | Parameter list area |
2805 // | +-----------------------------------+
2806 // | | LR save word |
2807 // | +-----------------------------------+
2808 // SP--> +--- | Back chain |
2809 // +-----------------------------------+
2812 // System V Application Binary Interface PowerPC Processor Supplement
2813 // AltiVec Technology Programming Interface Manual
2815 MachineFunction &MF = DAG.getMachineFunction();
2816 MachineFrameInfo *MFI = MF.getFrameInfo();
2817 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2819 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
2820 // Potential tail calls could cause overwriting of argument stack slots.
2821 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2822 (CallConv == CallingConv::Fast));
2823 unsigned PtrByteSize = 4;
2825 // Assign locations to all of the incoming arguments.
2826 SmallVector<CCValAssign, 16> ArgLocs;
2827 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
2830 // Reserve space for the linkage area on the stack.
2831 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
2832 CCInfo.AllocateStack(LinkageSize, PtrByteSize);
2834 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2836 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2837 CCValAssign &VA = ArgLocs[i];
2839 // Arguments stored in registers.
2840 if (VA.isRegLoc()) {
2841 const TargetRegisterClass *RC;
2842 EVT ValVT = VA.getValVT();
2844 switch (ValVT.getSimpleVT().SimpleTy) {
2846 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2849 RC = &PPC::GPRCRegClass;
2852 if (Subtarget.hasP8Vector())
2853 RC = &PPC::VSSRCRegClass;
2855 RC = &PPC::F4RCRegClass;
2858 if (Subtarget.hasVSX())
2859 RC = &PPC::VSFRCRegClass;
2861 RC = &PPC::F8RCRegClass;
2866 RC = &PPC::VRRCRegClass;
2869 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass;
2873 RC = &PPC::VSHRCRegClass;
2876 RC = &PPC::QFRCRegClass;
2879 RC = &PPC::QBRCRegClass;
2883 // Transform the arguments stored in physical registers into virtual ones.
2884 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2885 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2886 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2888 if (ValVT == MVT::i1)
2889 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2891 InVals.push_back(ArgValue);
2893 // Argument stored in memory.
2894 assert(VA.isMemLoc());
2896 unsigned ArgSize = VA.getLocVT().getStoreSize();
2897 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2900 // Create load nodes to retrieve arguments from the stack.
2901 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2902 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2903 MachinePointerInfo(),
2904 false, false, false, 0));
2908 // Assign locations to all of the incoming aggregate by value arguments.
2909 // Aggregates passed by value are stored in the local variable space of the
2910 // caller's stack frame, right above the parameter list area.
2911 SmallVector<CCValAssign, 16> ByValArgLocs;
2912 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2913 ByValArgLocs, *DAG.getContext());
2915 // Reserve stack space for the allocations in CCInfo.
2916 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2918 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2920 // Area that is at least reserved in the caller of this function.
2921 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2922 MinReservedArea = std::max(MinReservedArea, LinkageSize);
2924 // Set the size that is at least reserved in caller of this function. Tail
2925 // call optimized function's reserved stack space needs to be aligned so that
2926 // taking the difference between two stack areas will result in an aligned
2929 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
2930 FuncInfo->setMinReservedArea(MinReservedArea);
2932 SmallVector<SDValue, 8> MemOps;
2934 // If the function takes variable number of arguments, make a frame index for
2935 // the start of the first vararg value... for expansion of llvm.va_start.
2937 static const MCPhysReg GPArgRegs[] = {
2938 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2939 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2941 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2943 static const MCPhysReg FPArgRegs[] = {
2944 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2947 unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2948 if (DisablePPCFloatInVariadic)
2951 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs));
2952 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs));
2954 // Make room for NumGPArgRegs and NumFPArgRegs.
2955 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2956 NumFPArgRegs * MVT(MVT::f64).getSizeInBits()/8;
2958 FuncInfo->setVarArgsStackOffset(
2959 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2960 CCInfo.getNextStackOffset(), true));
2962 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2963 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2965 // The fixed integer arguments of a variadic function are stored to the
2966 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2967 // the result of va_next.
2968 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2969 // Get an existing live-in vreg, or add a new one.
2970 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2972 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2974 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2975 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2976 MachinePointerInfo(), false, false, 0);
2977 MemOps.push_back(Store);
2978 // Increment the address by four for the next argument to store
2979 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
2980 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2983 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2985 // The double arguments are stored to the VarArgsFrameIndex
2987 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2988 // Get an existing live-in vreg, or add a new one.
2989 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2991 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2993 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2994 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2995 MachinePointerInfo(), false, false, 0);
2996 MemOps.push_back(Store);
2997 // Increment the address by eight for the next argument to store
2998 SDValue PtrOff = DAG.getConstant(MVT(MVT::f64).getSizeInBits()/8, dl,
3000 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3004 if (!MemOps.empty())
3005 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3010 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3011 // value to MVT::i64 and then truncate to the correct register size.
3013 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
3014 SelectionDAG &DAG, SDValue ArgVal,
3017 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
3018 DAG.getValueType(ObjectVT));
3019 else if (Flags.isZExt())
3020 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
3021 DAG.getValueType(ObjectVT));
3023 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
3027 PPCTargetLowering::LowerFormalArguments_64SVR4(
3029 CallingConv::ID CallConv, bool isVarArg,
3030 const SmallVectorImpl<ISD::InputArg>
3032 SDLoc dl, SelectionDAG &DAG,
3033 SmallVectorImpl<SDValue> &InVals) const {
3034 // TODO: add description of PPC stack frame format, or at least some docs.
3036 bool isELFv2ABI = Subtarget.isELFv2ABI();
3037 bool isLittleEndian = Subtarget.isLittleEndian();
3038 MachineFunction &MF = DAG.getMachineFunction();
3039 MachineFrameInfo *MFI = MF.getFrameInfo();
3040 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3042 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
3043 "fastcc not supported on varargs functions");
3045 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3046 // Potential tail calls could cause overwriting of argument stack slots.
3047 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3048 (CallConv == CallingConv::Fast));
3049 unsigned PtrByteSize = 8;
3050 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3052 static const MCPhysReg GPR[] = {
3053 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3054 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3056 static const MCPhysReg VR[] = {
3057 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3058 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3060 static const MCPhysReg VSRH[] = {
3061 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
3062 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
3065 const unsigned Num_GPR_Regs = array_lengthof(GPR);
3066 const unsigned Num_FPR_Regs = 13;
3067 const unsigned Num_VR_Regs = array_lengthof(VR);
3068 const unsigned Num_QFPR_Regs = Num_FPR_Regs;
3070 // Do a first pass over the arguments to determine whether the ABI
3071 // guarantees that our caller has allocated the parameter save area
3072 // on its stack frame. In the ELFv1 ABI, this is always the case;
3073 // in the ELFv2 ABI, it is true if this is a vararg function or if
3074 // any parameter is located in a stack slot.
3076 bool HasParameterArea = !isELFv2ABI || isVarArg;
3077 unsigned ParamAreaSize = Num_GPR_Regs * PtrByteSize;
3078 unsigned NumBytes = LinkageSize;
3079 unsigned AvailableFPRs = Num_FPR_Regs;
3080 unsigned AvailableVRs = Num_VR_Regs;
3081 for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
3082 if (Ins[i].Flags.isNest())
3085 if (CalculateStackSlotUsed(Ins[i].VT, Ins[i].ArgVT, Ins[i].Flags,
3086 PtrByteSize, LinkageSize, ParamAreaSize,
3087 NumBytes, AvailableFPRs, AvailableVRs,
3088 Subtarget.hasQPX()))
3089 HasParameterArea = true;
3092 // Add DAG nodes to load the arguments or copy them out of registers. On
3093 // entry to a function on PPC, the arguments start after the linkage area,
3094 // although the first ones are often in registers.
3096 unsigned ArgOffset = LinkageSize;
3097 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3098 unsigned &QFPR_idx = FPR_idx;
3099 SmallVector<SDValue, 8> MemOps;
3100 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3101 unsigned CurArgIdx = 0;
3102 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3104 bool needsLoad = false;
3105 EVT ObjectVT = Ins[ArgNo].VT;
3106 EVT OrigVT = Ins[ArgNo].ArgVT;
3107 unsigned ObjSize = ObjectVT.getStoreSize();
3108 unsigned ArgSize = ObjSize;
3109 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3110 if (Ins[ArgNo].isOrigArg()) {
3111 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3112 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3114 // We re-align the argument offset for each argument, except when using the
3115 // fast calling convention, when we need to make sure we do that only when
3116 // we'll actually use a stack slot.
3117 unsigned CurArgOffset, Align;
3118 auto ComputeArgOffset = [&]() {
3119 /* Respect alignment of argument on the stack. */
3120 Align = CalculateStackSlotAlignment(ObjectVT, OrigVT, Flags, PtrByteSize);
3121 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
3122 CurArgOffset = ArgOffset;
3125 if (CallConv != CallingConv::Fast) {
3128 /* Compute GPR index associated with argument offset. */
3129 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3130 GPR_idx = std::min(GPR_idx, Num_GPR_Regs);
3133 // FIXME the codegen can be much improved in some cases.
3134 // We do not have to keep everything in memory.
3135 if (Flags.isByVal()) {
3136 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3138 if (CallConv == CallingConv::Fast)
3141 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3142 ObjSize = Flags.getByValSize();
3143 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3144 // Empty aggregate parameters do not take up registers. Examples:
3148 // etc. However, we have to provide a place-holder in InVals, so
3149 // pretend we have an 8-byte item at the current address for that
3152 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3153 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3154 InVals.push_back(FIN);
3158 // Create a stack object covering all stack doublewords occupied
3159 // by the argument. If the argument is (fully or partially) on
3160 // the stack, or if the argument is fully in registers but the
3161 // caller has allocated the parameter save anyway, we can refer
3162 // directly to the caller's stack frame. Otherwise, create a
3163 // local copy in our own frame.
3165 if (HasParameterArea ||
3166 ArgSize + ArgOffset > LinkageSize + Num_GPR_Regs * PtrByteSize)
3167 FI = MFI->CreateFixedObject(ArgSize, ArgOffset, false, true);
3169 FI = MFI->CreateStackObject(ArgSize, Align, false);
3170 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3172 // Handle aggregates smaller than 8 bytes.
3173 if (ObjSize < PtrByteSize) {
3174 // The value of the object is its address, which differs from the
3175 // address of the enclosing doubleword on big-endian systems.
3177 if (!isLittleEndian) {
3178 SDValue ArgOff = DAG.getConstant(PtrByteSize - ObjSize, dl, PtrVT);
3179 Arg = DAG.getNode(ISD::ADD, dl, ArgOff.getValueType(), Arg, ArgOff);
3181 InVals.push_back(Arg);
3183 if (GPR_idx != Num_GPR_Regs) {
3184 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3185 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3188 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
3189 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
3190 (ObjSize == 2 ? MVT::i16 : MVT::i32));
3191 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, Arg,
3192 MachinePointerInfo(FuncArg),
3193 ObjType, false, false, 0);
3195 // For sizes that don't fit a truncating store (3, 5, 6, 7),
3196 // store the whole register as-is to the parameter save area
3198 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3199 MachinePointerInfo(FuncArg),
3203 MemOps.push_back(Store);
3205 // Whether we copied from a register or not, advance the offset
3206 // into the parameter save area by a full doubleword.
3207 ArgOffset += PtrByteSize;
3211 // The value of the object is its address, which is the address of
3212 // its first stack doubleword.
3213 InVals.push_back(FIN);
3215 // Store whatever pieces of the object are in registers to memory.
3216 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3217 if (GPR_idx == Num_GPR_Regs)
3220 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3221 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3224 SDValue Off = DAG.getConstant(j, dl, PtrVT);
3225 Addr = DAG.getNode(ISD::ADD, dl, Off.getValueType(), Addr, Off);
3227 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, Addr,
3228 MachinePointerInfo(FuncArg, j),
3230 MemOps.push_back(Store);
3233 ArgOffset += ArgSize;
3237 switch (ObjectVT.getSimpleVT().SimpleTy) {
3238 default: llvm_unreachable("Unhandled argument type!");
3242 if (Flags.isNest()) {
3243 // The 'nest' parameter, if any, is passed in R11.
3244 unsigned VReg = MF.addLiveIn(PPC::X11, &PPC::G8RCRegClass);
3245 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3247 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3248 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3253 // These can be scalar arguments or elements of an integer array type
3254 // passed directly. Clang may use those instead of "byval" aggregate
3255 // types to avoid forcing arguments to memory unnecessarily.
3256 if (GPR_idx != Num_GPR_Regs) {
3257 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3258 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3260 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3261 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3262 // value to MVT::i64 and then truncate to the correct register size.
3263 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3265 if (CallConv == CallingConv::Fast)
3269 ArgSize = PtrByteSize;
3271 if (CallConv != CallingConv::Fast || needsLoad)
3277 // These can be scalar arguments or elements of a float array type
3278 // passed directly. The latter are used to implement ELFv2 homogenous
3279 // float aggregates.
3280 if (FPR_idx != Num_FPR_Regs) {
3283 if (ObjectVT == MVT::f32)
3284 VReg = MF.addLiveIn(FPR[FPR_idx],
3285 Subtarget.hasP8Vector()
3286 ? &PPC::VSSRCRegClass
3287 : &PPC::F4RCRegClass);
3289 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX()
3290 ? &PPC::VSFRCRegClass
3291 : &PPC::F8RCRegClass);
3293 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3295 } else if (GPR_idx != Num_GPR_Regs && CallConv != CallingConv::Fast) {
3296 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
3297 // once we support fp <-> gpr moves.
3299 // This can only ever happen in the presence of f32 array types,
3300 // since otherwise we never run out of FPRs before running out
3302 unsigned VReg = MF.addLiveIn(GPR[GPR_idx++], &PPC::G8RCRegClass);
3303 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3305 if (ObjectVT == MVT::f32) {
3306 if ((ArgOffset % PtrByteSize) == (isLittleEndian ? 4 : 0))
3307 ArgVal = DAG.getNode(ISD::SRL, dl, MVT::i64, ArgVal,
3308 DAG.getConstant(32, dl, MVT::i32));
3309 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
3312 ArgVal = DAG.getNode(ISD::BITCAST, dl, ObjectVT, ArgVal);
3314 if (CallConv == CallingConv::Fast)
3320 // When passing an array of floats, the array occupies consecutive
3321 // space in the argument area; only round up to the next doubleword
3322 // at the end of the array. Otherwise, each float takes 8 bytes.
3323 if (CallConv != CallingConv::Fast || needsLoad) {
3324 ArgSize = Flags.isInConsecutiveRegs() ? ObjSize : PtrByteSize;
3325 ArgOffset += ArgSize;
3326 if (Flags.isInConsecutiveRegsLast())
3327 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3337 if (!Subtarget.hasQPX()) {
3338 // These can be scalar arguments or elements of a vector array type
3339 // passed directly. The latter are used to implement ELFv2 homogenous
3340 // vector aggregates.
3341 if (VR_idx != Num_VR_Regs) {
3342 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
3343 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
3344 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3345 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3348 if (CallConv == CallingConv::Fast)
3353 if (CallConv != CallingConv::Fast || needsLoad)
3358 assert(ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 &&
3359 "Invalid QPX parameter type");
3364 // QPX vectors are treated like their scalar floating-point subregisters
3365 // (except that they're larger).
3366 unsigned Sz = ObjectVT.getSimpleVT().SimpleTy == MVT::v4f32 ? 16 : 32;
3367 if (QFPR_idx != Num_QFPR_Regs) {
3368 const TargetRegisterClass *RC;
3369 switch (ObjectVT.getSimpleVT().SimpleTy) {
3370 case MVT::v4f64: RC = &PPC::QFRCRegClass; break;
3371 case MVT::v4f32: RC = &PPC::QSRCRegClass; break;
3372 default: RC = &PPC::QBRCRegClass; break;
3375 unsigned VReg = MF.addLiveIn(QFPR[QFPR_idx], RC);
3376 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3379 if (CallConv == CallingConv::Fast)
3383 if (CallConv != CallingConv::Fast || needsLoad)
3388 // We need to load the argument to a virtual register if we determined
3389 // above that we ran out of physical registers of the appropriate type.
3391 if (ObjSize < ArgSize && !isLittleEndian)
3392 CurArgOffset += ArgSize - ObjSize;
3393 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
3394 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3395 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3396 false, false, false, 0);
3399 InVals.push_back(ArgVal);
3402 // Area that is at least reserved in the caller of this function.
3403 unsigned MinReservedArea;
3404 if (HasParameterArea)
3405 MinReservedArea = std::max(ArgOffset, LinkageSize + 8 * PtrByteSize);
3407 MinReservedArea = LinkageSize;
3409 // Set the size that is at least reserved in caller of this function. Tail
3410 // call optimized functions' reserved stack space needs to be aligned so that
3411 // taking the difference between two stack areas will result in an aligned
3414 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3415 FuncInfo->setMinReservedArea(MinReservedArea);
3417 // If the function takes variable number of arguments, make a frame index for
3418 // the start of the first vararg value... for expansion of llvm.va_start.
3420 int Depth = ArgOffset;
3422 FuncInfo->setVarArgsFrameIndex(
3423 MFI->CreateFixedObject(PtrByteSize, Depth, true));
3424 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3426 // If this function is vararg, store any remaining integer argument regs
3427 // to their spots on the stack so that they may be loaded by deferencing the
3428 // result of va_next.
3429 for (GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
3430 GPR_idx < Num_GPR_Regs; ++GPR_idx) {
3431 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3432 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3433 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3434 MachinePointerInfo(), false, false, 0);
3435 MemOps.push_back(Store);
3436 // Increment the address by four for the next argument to store
3437 SDValue PtrOff = DAG.getConstant(PtrByteSize, dl, PtrVT);
3438 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3442 if (!MemOps.empty())
3443 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3449 PPCTargetLowering::LowerFormalArguments_Darwin(
3451 CallingConv::ID CallConv, bool isVarArg,
3452 const SmallVectorImpl<ISD::InputArg>
3454 SDLoc dl, SelectionDAG &DAG,
3455 SmallVectorImpl<SDValue> &InVals) const {
3456 // TODO: add description of PPC stack frame format, or at least some docs.
3458 MachineFunction &MF = DAG.getMachineFunction();
3459 MachineFrameInfo *MFI = MF.getFrameInfo();
3460 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3462 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
3463 bool isPPC64 = PtrVT == MVT::i64;
3464 // Potential tail calls could cause overwriting of argument stack slots.
3465 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
3466 (CallConv == CallingConv::Fast));
3467 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3468 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
3469 unsigned ArgOffset = LinkageSize;
3470 // Area that is at least reserved in caller of this function.
3471 unsigned MinReservedArea = ArgOffset;
3473 static const MCPhysReg GPR_32[] = { // 32-bit registers.
3474 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3475 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3477 static const MCPhysReg GPR_64[] = { // 64-bit registers.
3478 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3479 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3481 static const MCPhysReg VR[] = {
3482 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3483 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3486 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
3487 const unsigned Num_FPR_Regs = 13;
3488 const unsigned Num_VR_Regs = array_lengthof( VR);
3490 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3492 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
3494 // In 32-bit non-varargs functions, the stack space for vectors is after the
3495 // stack space for non-vectors. We do not use this space unless we have
3496 // too many vectors to fit in registers, something that only occurs in
3497 // constructed examples:), but we have to walk the arglist to figure
3498 // that out...for the pathological case, compute VecArgOffset as the
3499 // start of the vector parameter area. Computing VecArgOffset is the
3500 // entire point of the following loop.
3501 unsigned VecArgOffset = ArgOffset;
3502 if (!isVarArg && !isPPC64) {
3503 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
3505 EVT ObjectVT = Ins[ArgNo].VT;
3506 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3508 if (Flags.isByVal()) {
3509 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
3510 unsigned ObjSize = Flags.getByValSize();
3512 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3513 VecArgOffset += ArgSize;
3517 switch(ObjectVT.getSimpleVT().SimpleTy) {
3518 default: llvm_unreachable("Unhandled argument type!");
3524 case MVT::i64: // PPC64
3526 // FIXME: We are guaranteed to be !isPPC64 at this point.
3527 // Does MVT::i64 apply?
3534 // Nothing to do, we're only looking at Nonvector args here.
3539 // We've found where the vector parameter area in memory is. Skip the
3540 // first 12 parameters; these don't use that memory.
3541 VecArgOffset = ((VecArgOffset+15)/16)*16;
3542 VecArgOffset += 12*16;
3544 // Add DAG nodes to load the arguments or copy them out of registers. On
3545 // entry to a function on PPC, the arguments start after the linkage area,
3546 // although the first ones are often in registers.
3548 SmallVector<SDValue, 8> MemOps;
3549 unsigned nAltivecParamsAtEnd = 0;
3550 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
3551 unsigned CurArgIdx = 0;
3552 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
3554 bool needsLoad = false;
3555 EVT ObjectVT = Ins[ArgNo].VT;
3556 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
3557 unsigned ArgSize = ObjSize;
3558 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
3559 if (Ins[ArgNo].isOrigArg()) {
3560 std::advance(FuncArg, Ins[ArgNo].getOrigArgIndex() - CurArgIdx);
3561 CurArgIdx = Ins[ArgNo].getOrigArgIndex();
3563 unsigned CurArgOffset = ArgOffset;
3565 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
3566 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
3567 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
3568 if (isVarArg || isPPC64) {
3569 MinReservedArea = ((MinReservedArea+15)/16)*16;
3570 MinReservedArea += CalculateStackSlotSize(ObjectVT,
3573 } else nAltivecParamsAtEnd++;
3575 // Calculate min reserved area.
3576 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
3580 // FIXME the codegen can be much improved in some cases.
3581 // We do not have to keep everything in memory.
3582 if (Flags.isByVal()) {
3583 assert(Ins[ArgNo].isOrigArg() && "Byval arguments cannot be implicit");
3585 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
3586 ObjSize = Flags.getByValSize();
3587 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
3588 // Objects of size 1 and 2 are right justified, everything else is
3589 // left justified. This means the memory address is adjusted forwards.
3590 if (ObjSize==1 || ObjSize==2) {
3591 CurArgOffset = CurArgOffset + (4 - ObjSize);
3593 // The value of the object is its address.
3594 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, false, true);
3595 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3596 InVals.push_back(FIN);
3597 if (ObjSize==1 || ObjSize==2) {
3598 if (GPR_idx != Num_GPR_Regs) {
3601 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3603 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3604 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3605 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
3606 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
3607 MachinePointerInfo(FuncArg),
3608 ObjType, false, false, 0);
3609 MemOps.push_back(Store);
3613 ArgOffset += PtrByteSize;
3617 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
3618 // Store whatever pieces of the object are in registers
3619 // to memory. ArgOffset will be the address of the beginning
3621 if (GPR_idx != Num_GPR_Regs) {
3624 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3626 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3627 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
3628 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3629 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3630 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3631 MachinePointerInfo(FuncArg, j),
3633 MemOps.push_back(Store);
3635 ArgOffset += PtrByteSize;
3637 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
3644 switch (ObjectVT.getSimpleVT().SimpleTy) {
3645 default: llvm_unreachable("Unhandled argument type!");
3649 if (GPR_idx != Num_GPR_Regs) {
3650 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3651 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
3653 if (ObjectVT == MVT::i1)
3654 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
3659 ArgSize = PtrByteSize;
3661 // All int arguments reserve stack space in the Darwin ABI.
3662 ArgOffset += PtrByteSize;
3666 case MVT::i64: // PPC64
3667 if (GPR_idx != Num_GPR_Regs) {
3668 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3669 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
3671 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
3672 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
3673 // value to MVT::i64 and then truncate to the correct register size.
3674 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
3679 ArgSize = PtrByteSize;
3681 // All int arguments reserve stack space in the Darwin ABI.
3687 // Every 4 bytes of argument space consumes one of the GPRs available for
3688 // argument passing.
3689 if (GPR_idx != Num_GPR_Regs) {
3691 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
3694 if (FPR_idx != Num_FPR_Regs) {
3697 if (ObjectVT == MVT::f32)
3698 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
3700 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
3702 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3708 // All FP arguments reserve stack space in the Darwin ABI.
3709 ArgOffset += isPPC64 ? 8 : ObjSize;
3715 // Note that vector arguments in registers don't reserve stack space,
3716 // except in varargs functions.
3717 if (VR_idx != Num_VR_Regs) {
3718 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
3719 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
3721 while ((ArgOffset % 16) != 0) {
3722 ArgOffset += PtrByteSize;
3723 if (GPR_idx != Num_GPR_Regs)
3727 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3731 if (!isVarArg && !isPPC64) {
3732 // Vectors go after all the nonvectors.
3733 CurArgOffset = VecArgOffset;
3736 // Vectors are aligned.
3737 ArgOffset = ((ArgOffset+15)/16)*16;
3738 CurArgOffset = ArgOffset;
3746 // We need to load the argument to a virtual register if we determined above
3747 // that we ran out of physical registers of the appropriate type.
3749 int FI = MFI->CreateFixedObject(ObjSize,
3750 CurArgOffset + (ArgSize - ObjSize),
3752 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3753 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3754 false, false, false, 0);
3757 InVals.push_back(ArgVal);
3760 // Allow for Altivec parameters at the end, if needed.
3761 if (nAltivecParamsAtEnd) {
3762 MinReservedArea = ((MinReservedArea+15)/16)*16;
3763 MinReservedArea += 16*nAltivecParamsAtEnd;
3766 // Area that is at least reserved in the caller of this function.
3767 MinReservedArea = std::max(MinReservedArea, LinkageSize + 8 * PtrByteSize);
3769 // Set the size that is at least reserved in caller of this function. Tail
3770 // call optimized functions' reserved stack space needs to be aligned so that
3771 // taking the difference between two stack areas will result in an aligned
3774 EnsureStackAlignment(Subtarget.getFrameLowering(), MinReservedArea);
3775 FuncInfo->setMinReservedArea(MinReservedArea);
3777 // If the function takes variable number of arguments, make a frame index for
3778 // the start of the first vararg value... for expansion of llvm.va_start.
3780 int Depth = ArgOffset;
3782 FuncInfo->setVarArgsFrameIndex(
3783 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3785 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3787 // If this function is vararg, store any remaining integer argument regs
3788 // to their spots on the stack so that they may be loaded by deferencing the
3789 // result of va_next.
3790 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3794 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3796 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3798 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3799 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3800 MachinePointerInfo(), false, false, 0);
3801 MemOps.push_back(Store);
3802 // Increment the address by four for the next argument to store
3803 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, dl, PtrVT);
3804 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3808 if (!MemOps.empty())
3809 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3814 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3815 /// adjusted to accommodate the arguments for the tailcall.
3816 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3817 unsigned ParamSize) {
3819 if (!isTailCall) return 0;
3821 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3822 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3823 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3824 // Remember only if the new adjustement is bigger.
3825 if (SPDiff < FI->getTailCallSPDelta())
3826 FI->setTailCallSPDelta(SPDiff);
3831 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3832 /// for tail call optimization. Targets which want to do tail call
3833 /// optimization should implement this function.
3835 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3836 CallingConv::ID CalleeCC,
3838 const SmallVectorImpl<ISD::InputArg> &Ins,
3839 SelectionDAG& DAG) const {
3840 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3843 // Variable argument functions are not supported.
3847 MachineFunction &MF = DAG.getMachineFunction();
3848 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3849 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3850 // Functions containing by val parameters are not supported.
3851 for (unsigned i = 0; i != Ins.size(); i++) {
3852 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3853 if (Flags.isByVal()) return false;
3856 // Non-PIC/GOT tail calls are supported.
3857 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3860 // At the moment we can only do local tail calls (in same module, hidden
3861 // or protected) if we are generating PIC.
3862 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3863 return G->getGlobal()->hasHiddenVisibility()
3864 || G->getGlobal()->hasProtectedVisibility();
3870 /// isCallCompatibleAddress - Return the immediate to use if the specified
3871 /// 32-bit value is representable in the immediate field of a BxA instruction.
3872 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3873 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3874 if (!C) return nullptr;
3876 int Addr = C->getZExtValue();
3877 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3878 SignExtend32<26>(Addr) != Addr)
3879 return nullptr; // Top 6 bits have to be sext of immediate.
3881 return DAG.getConstant((int)C->getZExtValue() >> 2, SDLoc(Op),
3882 DAG.getTargetLoweringInfo().getPointerTy(
3883 DAG.getDataLayout())).getNode();
3888 struct TailCallArgumentInfo {
3893 TailCallArgumentInfo() : FrameIdx(0) {}
3898 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3900 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3902 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3903 SmallVectorImpl<SDValue> &MemOpChains,
3905 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3906 SDValue Arg = TailCallArgs[i].Arg;
3907 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3908 int FI = TailCallArgs[i].FrameIdx;
3909 // Store relative to framepointer.
3910 MemOpChains.push_back(DAG.getStore(
3911 Chain, dl, Arg, FIN,
3912 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI), false,
3917 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3918 /// the appropriate stack slot for the tail call optimized function call.
3919 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3920 MachineFunction &MF,
3929 // Calculate the new stack slot for the return address.
3930 int SlotSize = isPPC64 ? 8 : 4;
3931 const PPCFrameLowering *FL =
3932 MF.getSubtarget<PPCSubtarget>().getFrameLowering();
3933 int NewRetAddrLoc = SPDiff + FL->getReturnSaveOffset();
3934 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3935 NewRetAddrLoc, true);
3936 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3937 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3938 Chain = DAG.getStore(
3939 Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3940 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewRetAddr),
3943 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3944 // slot as the FP is never overwritten.
3946 int NewFPLoc = SPDiff + FL->getFramePointerSaveOffset();
3947 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3949 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3950 Chain = DAG.getStore(
3951 Chain, dl, OldFP, NewFramePtrIdx,
3952 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), NewFPIdx),
3959 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3960 /// the position of the argument.
3962 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3963 SDValue Arg, int SPDiff, unsigned ArgOffset,
3964 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3965 int Offset = ArgOffset + SPDiff;
3966 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3967 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3968 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3969 SDValue FIN = DAG.getFrameIndex(FI, VT);
3970 TailCallArgumentInfo Info;
3972 Info.FrameIdxOp = FIN;
3974 TailCallArguments.push_back(Info);
3977 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3978 /// stack slot. Returns the chain as result and the loaded frame pointers in
3979 /// LROpOut/FPOpout. Used when tail calling.
3980 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3988 // Load the LR and FP stack slot for later adjusting.
3989 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3990 LROpOut = getReturnAddrFrameIndex(DAG);
3991 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3992 false, false, false, 0);
3993 Chain = SDValue(LROpOut.getNode(), 1);
3995 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3996 // slot as the FP is never overwritten.
3998 FPOpOut = getFramePointerFrameIndex(DAG);
3999 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
4000 false, false, false, 0);
4001 Chain = SDValue(FPOpOut.getNode(), 1);
4007 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
4008 /// by "Src" to address "Dst" of size "Size". Alignment information is
4009 /// specified by the specific parameter attribute. The copy will be passed as
4010 /// a byval function parameter.
4011 /// Sometimes what we are copying is the end of a larger object, the part that
4012 /// does not fit in registers.
4014 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
4015 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
4017 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), dl, MVT::i32);
4018 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
4019 false, false, false, MachinePointerInfo(),
4020 MachinePointerInfo());
4023 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
4026 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
4027 SDValue Arg, SDValue PtrOff, int SPDiff,
4028 unsigned ArgOffset, bool isPPC64, bool isTailCall,
4029 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
4030 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
4032 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4037 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4039 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4040 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4041 DAG.getConstant(ArgOffset, dl, PtrVT));
4043 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4044 MachinePointerInfo(), false, false, 0));
4045 // Calculate and remember argument location.
4046 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
4051 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
4052 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
4053 SDValue LROp, SDValue FPOp, bool isDarwinABI,
4054 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
4055 MachineFunction &MF = DAG.getMachineFunction();
4057 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
4058 // might overwrite each other in case of tail call optimization.
4059 SmallVector<SDValue, 8> MemOpChains2;
4060 // Do not flag preceding copytoreg stuff together with the following stuff.
4062 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
4064 if (!MemOpChains2.empty())
4065 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
4067 // Store the return address to the appropriate stack slot.
4068 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
4069 isPPC64, isDarwinABI, dl);
4071 // Emit callseq_end just before tailcall node.
4072 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4073 DAG.getIntPtrConstant(0, dl, true), InFlag, dl);
4074 InFlag = Chain.getValue(1);
4077 // Is this global address that of a function that can be called by name? (as
4078 // opposed to something that must hold a descriptor for an indirect call).
4079 static bool isFunctionGlobalAddress(SDValue Callee) {
4080 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
4081 if (Callee.getOpcode() == ISD::GlobalTLSAddress ||
4082 Callee.getOpcode() == ISD::TargetGlobalTLSAddress)
4085 return G->getGlobal()->getType()->getElementType()->isFunctionTy();
4092 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
4093 SDValue &Chain, SDValue CallSeqStart, SDLoc dl, int SPDiff,
4094 bool isTailCall, bool IsPatchPoint, bool hasNest,
4095 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
4096 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
4097 ImmutableCallSite *CS, const PPCSubtarget &Subtarget) {
4099 bool isPPC64 = Subtarget.isPPC64();
4100 bool isSVR4ABI = Subtarget.isSVR4ABI();
4101 bool isELFv2ABI = Subtarget.isELFv2ABI();
4103 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4104 NodeTys.push_back(MVT::Other); // Returns a chain
4105 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
4107 unsigned CallOpc = PPCISD::CALL;
4109 bool needIndirectCall = true;
4110 if (!isSVR4ABI || !isPPC64)
4111 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
4112 // If this is an absolute destination address, use the munged value.
4113 Callee = SDValue(Dest, 0);
4114 needIndirectCall = false;
4117 if (isFunctionGlobalAddress(Callee)) {
4118 GlobalAddressSDNode *G = cast<GlobalAddressSDNode>(Callee);
4119 // A call to a TLS address is actually an indirect call to a
4120 // thread-specific pointer.
4121 unsigned OpFlags = 0;
4122 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4123 (Subtarget.getTargetTriple().isMacOSX() &&
4124 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
4125 !G->getGlobal()->isStrongDefinitionForLinker()) ||
4126 (Subtarget.isTargetELF() && !isPPC64 &&
4127 !G->getGlobal()->hasLocalLinkage() &&
4128 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4129 // PC-relative references to external symbols should go through $stub,
4130 // unless we're building with the leopard linker or later, which
4131 // automatically synthesizes these stubs.
4132 OpFlags = PPCII::MO_PLT_OR_STUB;
4135 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
4136 // every direct call is) turn it into a TargetGlobalAddress /
4137 // TargetExternalSymbol node so that legalize doesn't hack it.
4138 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
4139 Callee.getValueType(), 0, OpFlags);
4140 needIndirectCall = false;
4143 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
4144 unsigned char OpFlags = 0;
4146 if ((DAG.getTarget().getRelocationModel() != Reloc::Static &&
4147 (Subtarget.getTargetTriple().isMacOSX() &&
4148 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) ||
4149 (Subtarget.isTargetELF() && !isPPC64 &&
4150 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
4151 // PC-relative references to external symbols should go through $stub,
4152 // unless we're building with the leopard linker or later, which
4153 // automatically synthesizes these stubs.
4154 OpFlags = PPCII::MO_PLT_OR_STUB;
4157 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
4159 needIndirectCall = false;
4163 // We'll form an invalid direct call when lowering a patchpoint; the full
4164 // sequence for an indirect call is complicated, and many of the
4165 // instructions introduced might have side effects (and, thus, can't be
4166 // removed later). The call itself will be removed as soon as the
4167 // argument/return lowering is complete, so the fact that it has the wrong
4168 // kind of operands should not really matter.
4169 needIndirectCall = false;
4172 if (needIndirectCall) {
4173 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
4174 // to do the call, we can't use PPCISD::CALL.
4175 SDValue MTCTROps[] = {Chain, Callee, InFlag};
4177 if (isSVR4ABI && isPPC64 && !isELFv2ABI) {
4178 // Function pointers in the 64-bit SVR4 ABI do not point to the function
4179 // entry point, but to the function descriptor (the function entry point
4180 // address is part of the function descriptor though).
4181 // The function descriptor is a three doubleword structure with the
4182 // following fields: function entry point, TOC base address and
4183 // environment pointer.
4184 // Thus for a call through a function pointer, the following actions need
4186 // 1. Save the TOC of the caller in the TOC save area of its stack
4187 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
4188 // 2. Load the address of the function entry point from the function
4190 // 3. Load the TOC of the callee from the function descriptor into r2.
4191 // 4. Load the environment pointer from the function descriptor into
4193 // 5. Branch to the function entry point address.
4194 // 6. On return of the callee, the TOC of the caller needs to be
4195 // restored (this is done in FinishCall()).
4197 // The loads are scheduled at the beginning of the call sequence, and the
4198 // register copies are flagged together to ensure that no other
4199 // operations can be scheduled in between. E.g. without flagging the
4200 // copies together, a TOC access in the caller could be scheduled between
4201 // the assignment of the callee TOC and the branch to the callee, which
4202 // results in the TOC access going through the TOC of the callee instead
4203 // of going through the TOC of the caller, which leads to incorrect code.
4205 // Load the address of the function entry point from the function
4207 SDValue LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-1);
4208 if (LDChain.getValueType() == MVT::Glue)
4209 LDChain = CallSeqStart.getValue(CallSeqStart->getNumValues()-2);
4211 bool LoadsInv = Subtarget.hasInvariantFunctionDescriptors();
4213 MachinePointerInfo MPI(CS ? CS->getCalledValue() : nullptr);
4214 SDValue LoadFuncPtr = DAG.getLoad(MVT::i64, dl, LDChain, Callee, MPI,
4215 false, false, LoadsInv, 8);
4217 // Load environment pointer into r11.
4218 SDValue PtrOff = DAG.getIntPtrConstant(16, dl);
4219 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
4220 SDValue LoadEnvPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddPtr,
4221 MPI.getWithOffset(16), false, false,
4224 SDValue TOCOff = DAG.getIntPtrConstant(8, dl);
4225 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
4226 SDValue TOCPtr = DAG.getLoad(MVT::i64, dl, LDChain, AddTOC,
4227 MPI.getWithOffset(8), false, false,
4230 setUsesTOCBasePtr(DAG);
4231 SDValue TOCVal = DAG.getCopyToReg(Chain, dl, PPC::X2, TOCPtr,
4233 Chain = TOCVal.getValue(0);
4234 InFlag = TOCVal.getValue(1);
4236 // If the function call has an explicit 'nest' parameter, it takes the
4237 // place of the environment pointer.
4239 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
4242 Chain = EnvVal.getValue(0);
4243 InFlag = EnvVal.getValue(1);
4246 MTCTROps[0] = Chain;
4247 MTCTROps[1] = LoadFuncPtr;
4248 MTCTROps[2] = InFlag;
4251 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
4252 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
4253 InFlag = Chain.getValue(1);
4256 NodeTys.push_back(MVT::Other);
4257 NodeTys.push_back(MVT::Glue);
4258 Ops.push_back(Chain);
4259 CallOpc = PPCISD::BCTRL;
4260 Callee.setNode(nullptr);
4261 // Add use of X11 (holding environment pointer)
4262 if (isSVR4ABI && isPPC64 && !isELFv2ABI && !hasNest)
4263 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
4264 // Add CTR register as callee so a bctr can be emitted later.
4266 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
4269 // If this is a direct call, pass the chain and the callee.
4270 if (Callee.getNode()) {
4271 Ops.push_back(Chain);
4272 Ops.push_back(Callee);
4274 // If this is a tail call add stack pointer delta.
4276 Ops.push_back(DAG.getConstant(SPDiff, dl, MVT::i32));
4278 // Add argument registers to the end of the list so that they are known live
4280 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
4281 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
4282 RegsToPass[i].second.getValueType()));
4284 // All calls, in both the ELF V1 and V2 ABIs, need the TOC register live
4286 if (isSVR4ABI && isPPC64 && !IsPatchPoint) {
4287 setUsesTOCBasePtr(DAG);
4288 Ops.push_back(DAG.getRegister(PPC::X2, PtrVT));
4295 bool isLocalCall(const SDValue &Callee)
4297 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
4298 return G->getGlobal()->isStrongDefinitionForLinker();
4303 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
4304 CallingConv::ID CallConv, bool isVarArg,
4305 const SmallVectorImpl<ISD::InputArg> &Ins,
4306 SDLoc dl, SelectionDAG &DAG,
4307 SmallVectorImpl<SDValue> &InVals) const {
4309 SmallVector<CCValAssign, 16> RVLocs;
4310 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
4312 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
4314 // Copy all of the result registers out of their specified physreg.
4315 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
4316 CCValAssign &VA = RVLocs[i];
4317 assert(VA.isRegLoc() && "Can only return in registers!");
4319 SDValue Val = DAG.getCopyFromReg(Chain, dl,
4320 VA.getLocReg(), VA.getLocVT(), InFlag);
4321 Chain = Val.getValue(1);
4322 InFlag = Val.getValue(2);
4324 switch (VA.getLocInfo()) {
4325 default: llvm_unreachable("Unknown loc info!");
4326 case CCValAssign::Full: break;
4327 case CCValAssign::AExt:
4328 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4330 case CCValAssign::ZExt:
4331 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
4332 DAG.getValueType(VA.getValVT()));
4333 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4335 case CCValAssign::SExt:
4336 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
4337 DAG.getValueType(VA.getValVT()));
4338 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
4342 InVals.push_back(Val);
4349 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
4350 bool isTailCall, bool isVarArg, bool IsPatchPoint,
4351 bool hasNest, SelectionDAG &DAG,
4352 SmallVector<std::pair<unsigned, SDValue>, 8>
4354 SDValue InFlag, SDValue Chain,
4355 SDValue CallSeqStart, SDValue &Callee,
4356 int SPDiff, unsigned NumBytes,
4357 const SmallVectorImpl<ISD::InputArg> &Ins,
4358 SmallVectorImpl<SDValue> &InVals,
4359 ImmutableCallSite *CS) const {
4361 std::vector<EVT> NodeTys;
4362 SmallVector<SDValue, 8> Ops;
4363 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, CallSeqStart, dl,
4364 SPDiff, isTailCall, IsPatchPoint, hasNest,
4365 RegsToPass, Ops, NodeTys, CS, Subtarget);
4367 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
4368 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
4369 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
4371 // When performing tail call optimization the callee pops its arguments off
4372 // the stack. Account for this here so these bytes can be pushed back on in
4373 // PPCFrameLowering::eliminateCallFramePseudoInstr.
4374 int BytesCalleePops =
4375 (CallConv == CallingConv::Fast &&
4376 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
4378 // Add a register mask operand representing the call-preserved registers.
4379 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4380 const uint32_t *Mask =
4381 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallConv);
4382 assert(Mask && "Missing call preserved mask for calling convention");
4383 Ops.push_back(DAG.getRegisterMask(Mask));
4385 if (InFlag.getNode())
4386 Ops.push_back(InFlag);
4390 assert(((Callee.getOpcode() == ISD::Register &&
4391 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
4392 Callee.getOpcode() == ISD::TargetExternalSymbol ||
4393 Callee.getOpcode() == ISD::TargetGlobalAddress ||
4394 isa<ConstantSDNode>(Callee)) &&
4395 "Expecting an global address, external symbol, absolute value or register");
4397 DAG.getMachineFunction().getFrameInfo()->setHasTailCall();
4398 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
4401 // Add a NOP immediately after the branch instruction when using the 64-bit
4402 // SVR4 ABI. At link time, if caller and callee are in a different module and
4403 // thus have a different TOC, the call will be replaced with a call to a stub
4404 // function which saves the current TOC, loads the TOC of the callee and
4405 // branches to the callee. The NOP will be replaced with a load instruction
4406 // which restores the TOC of the caller from the TOC save slot of the current
4407 // stack frame. If caller and callee belong to the same module (and have the
4408 // same TOC), the NOP will remain unchanged.
4410 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64() &&
4412 if (CallOpc == PPCISD::BCTRL) {
4413 // This is a call through a function pointer.
4414 // Restore the caller TOC from the save area into R2.
4415 // See PrepareCall() for more information about calls through function
4416 // pointers in the 64-bit SVR4 ABI.
4417 // We are using a target-specific load with r2 hard coded, because the
4418 // result of a target-independent load would never go directly into r2,
4419 // since r2 is a reserved register (which prevents the register allocator
4420 // from allocating it), resulting in an additional register being
4421 // allocated and an unnecessary move instruction being generated.
4422 CallOpc = PPCISD::BCTRL_LOAD_TOC;
4424 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4425 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
4426 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
4427 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
4428 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
4430 // The address needs to go after the chain input but before the flag (or
4431 // any other variadic arguments).
4432 Ops.insert(std::next(Ops.begin()), AddTOC);
4433 } else if ((CallOpc == PPCISD::CALL) &&
4434 (!isLocalCall(Callee) ||
4435 DAG.getTarget().getRelocationModel() == Reloc::PIC_))
4436 // Otherwise insert NOP for non-local calls.
4437 CallOpc = PPCISD::CALL_NOP;
4440 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
4441 InFlag = Chain.getValue(1);
4443 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4444 DAG.getIntPtrConstant(BytesCalleePops, dl, true),
4447 InFlag = Chain.getValue(1);
4449 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
4450 Ins, dl, DAG, InVals);
4454 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
4455 SmallVectorImpl<SDValue> &InVals) const {
4456 SelectionDAG &DAG = CLI.DAG;
4458 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
4459 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
4460 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
4461 SDValue Chain = CLI.Chain;
4462 SDValue Callee = CLI.Callee;
4463 bool &isTailCall = CLI.IsTailCall;
4464 CallingConv::ID CallConv = CLI.CallConv;
4465 bool isVarArg = CLI.IsVarArg;
4466 bool IsPatchPoint = CLI.IsPatchPoint;
4467 ImmutableCallSite *CS = CLI.CS;
4470 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
4473 if (!isTailCall && CS && CS->isMustTailCall())
4474 report_fatal_error("failed to perform tail call elimination on a call "
4475 "site marked musttail");
4477 if (Subtarget.isSVR4ABI()) {
4478 if (Subtarget.isPPC64())
4479 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
4480 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4481 dl, DAG, InVals, CS);
4483 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
4484 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4485 dl, DAG, InVals, CS);
4488 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
4489 isTailCall, IsPatchPoint, Outs, OutVals, Ins,
4490 dl, DAG, InVals, CS);
4494 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
4495 CallingConv::ID CallConv, bool isVarArg,
4496 bool isTailCall, bool IsPatchPoint,
4497 const SmallVectorImpl<ISD::OutputArg> &Outs,
4498 const SmallVectorImpl<SDValue> &OutVals,
4499 const SmallVectorImpl<ISD::InputArg> &Ins,
4500 SDLoc dl, SelectionDAG &DAG,
4501 SmallVectorImpl<SDValue> &InVals,
4502 ImmutableCallSite *CS) const {
4503 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
4504 // of the 32-bit SVR4 ABI stack frame layout.
4506 assert((CallConv == CallingConv::C ||
4507 CallConv == CallingConv::Fast) && "Unknown calling convention!");
4509 unsigned PtrByteSize = 4;
4511 MachineFunction &MF = DAG.getMachineFunction();
4513 // Mark this function as potentially containing a function that contains a
4514 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4515 // and restoring the callers stack pointer in this functions epilog. This is
4516 // done because by tail calling the called function might overwrite the value
4517 // in this function's (MF) stack pointer stack slot 0(SP).
4518 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4519 CallConv == CallingConv::Fast)
4520 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4522 // Count how many bytes are to be pushed on the stack, including the linkage
4523 // area, parameter list area and the part of the local variable space which
4524 // contains copies of aggregates which are passed by value.
4526 // Assign locations to all of the outgoing arguments.
4527 SmallVector<CCValAssign, 16> ArgLocs;
4528 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
4531 // Reserve space for the linkage area on the stack.
4532 CCInfo.AllocateStack(Subtarget.getFrameLowering()->getLinkageSize(),
4536 // Handle fixed and variable vector arguments differently.
4537 // Fixed vector arguments go into registers as long as registers are
4538 // available. Variable vector arguments always go into memory.
4539 unsigned NumArgs = Outs.size();
4541 for (unsigned i = 0; i != NumArgs; ++i) {
4542 MVT ArgVT = Outs[i].VT;
4543 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
4546 if (Outs[i].IsFixed) {
4547 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
4550 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
4556 errs() << "Call operand #" << i << " has unhandled type "
4557 << EVT(ArgVT).getEVTString() << "\n";
4559 llvm_unreachable(nullptr);
4563 // All arguments are treated the same.
4564 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
4567 // Assign locations to all of the outgoing aggregate by value arguments.
4568 SmallVector<CCValAssign, 16> ByValArgLocs;
4569 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4570 ByValArgLocs, *DAG.getContext());
4572 // Reserve stack space for the allocations in CCInfo.
4573 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
4575 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
4577 // Size of the linkage area, parameter list area and the part of the local
4578 // space variable where copies of aggregates which are passed by value are
4580 unsigned NumBytes = CCByValInfo.getNextStackOffset();
4582 // Calculate by how many bytes the stack has to be adjusted in case of tail
4583 // call optimization.
4584 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4586 // Adjust the stack pointer for the new arguments...
4587 // These operations are automatically eliminated by the prolog/epilog pass
4588 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4590 SDValue CallSeqStart = Chain;
4592 // Load the return address and frame pointer so it can be moved somewhere else
4595 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
4598 // Set up a copy of the stack pointer for use loading and storing any
4599 // arguments that may not fit in the registers available for argument
4601 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4603 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4604 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4605 SmallVector<SDValue, 8> MemOpChains;
4607 bool seenFloatArg = false;
4608 // Walk the register/memloc assignments, inserting copies/loads.
4609 for (unsigned i = 0, j = 0, e = ArgLocs.size();
4612 CCValAssign &VA = ArgLocs[i];
4613 SDValue Arg = OutVals[i];
4614 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4616 if (Flags.isByVal()) {
4617 // Argument is an aggregate which is passed by value, thus we need to
4618 // create a copy of it in the local variable space of the current stack
4619 // frame (which is the stack frame of the caller) and pass the address of
4620 // this copy to the callee.
4621 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
4622 CCValAssign &ByValVA = ByValArgLocs[j++];
4623 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
4625 // Memory reserved in the local variable space of the callers stack frame.
4626 unsigned LocMemOffset = ByValVA.getLocMemOffset();
4628 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4629 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4632 // Create a copy of the argument in the local area of the current
4634 SDValue MemcpyCall =
4635 CreateCopyOfByValArgument(Arg, PtrOff,
4636 CallSeqStart.getNode()->getOperand(0),
4639 // This must go outside the CALLSEQ_START..END.
4640 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4641 CallSeqStart.getNode()->getOperand(1),
4643 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4644 NewCallSeqStart.getNode());
4645 Chain = CallSeqStart = NewCallSeqStart;
4647 // Pass the address of the aggregate copy on the stack either in a
4648 // physical register or in the parameter list area of the current stack
4649 // frame to the callee.
4653 if (VA.isRegLoc()) {
4654 if (Arg.getValueType() == MVT::i1)
4655 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
4657 seenFloatArg |= VA.getLocVT().isFloatingPoint();
4658 // Put argument in a physical register.
4659 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
4661 // Put argument in the parameter list area of the current stack frame.
4662 assert(VA.isMemLoc());
4663 unsigned LocMemOffset = VA.getLocMemOffset();
4666 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset, dl);
4667 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(MF.getDataLayout()),
4670 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
4671 MachinePointerInfo(),
4674 // Calculate and remember argument location.
4675 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
4681 if (!MemOpChains.empty())
4682 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4684 // Build a sequence of copy-to-reg nodes chained together with token chain
4685 // and flag operands which copy the outgoing args into the appropriate regs.
4687 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4688 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4689 RegsToPass[i].second, InFlag);
4690 InFlag = Chain.getValue(1);
4693 // Set CR bit 6 to true if this is a vararg call with floating args passed in
4696 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
4697 SDValue Ops[] = { Chain, InFlag };
4699 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
4700 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
4702 InFlag = Chain.getValue(1);
4706 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
4707 false, TailCallArguments);
4709 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
4710 /* unused except on PPC64 ELFv1 */ false, DAG,
4711 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
4712 NumBytes, Ins, InVals, CS);
4715 // Copy an argument into memory, being careful to do this outside the
4716 // call sequence for the call to which the argument belongs.
4718 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
4719 SDValue CallSeqStart,
4720 ISD::ArgFlagsTy Flags,
4723 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4724 CallSeqStart.getNode()->getOperand(0),
4726 // The MEMCPY must go outside the CALLSEQ_START..END.
4727 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4728 CallSeqStart.getNode()->getOperand(1),
4730 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4731 NewCallSeqStart.getNode());
4732 return NewCallSeqStart;
4736 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4737 CallingConv::ID CallConv, bool isVarArg,
4738 bool isTailCall, bool IsPatchPoint,
4739 const SmallVectorImpl<ISD::OutputArg> &Outs,
4740 const SmallVectorImpl<SDValue> &OutVals,
4741 const SmallVectorImpl<ISD::InputArg> &Ins,
4742 SDLoc dl, SelectionDAG &DAG,
4743 SmallVectorImpl<SDValue> &InVals,
4744 ImmutableCallSite *CS) const {
4746 bool isELFv2ABI = Subtarget.isELFv2ABI();
4747 bool isLittleEndian = Subtarget.isLittleEndian();
4748 unsigned NumOps = Outs.size();
4749 bool hasNest = false;
4751 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
4752 unsigned PtrByteSize = 8;
4754 MachineFunction &MF = DAG.getMachineFunction();
4756 // Mark this function as potentially containing a function that contains a
4757 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4758 // and restoring the callers stack pointer in this functions epilog. This is
4759 // done because by tail calling the called function might overwrite the value
4760 // in this function's (MF) stack pointer stack slot 0(SP).
4761 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4762 CallConv == CallingConv::Fast)
4763 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4765 assert(!(CallConv == CallingConv::Fast && isVarArg) &&
4766 "fastcc not supported on varargs functions");
4768 // Count how many bytes are to be pushed on the stack, including the linkage
4769 // area, and parameter passing area. On ELFv1, the linkage area is 48 bytes
4770 // reserved space for [SP][CR][LR][2 x unused][TOC]; on ELFv2, the linkage
4771 // area is 32 bytes reserved space for [SP][CR][LR][TOC].
4772 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
4773 unsigned NumBytes = LinkageSize;
4774 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4775 unsigned &QFPR_idx = FPR_idx;
4777 static const MCPhysReg GPR[] = {
4778 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4779 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4781 static const MCPhysReg VR[] = {
4782 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4783 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4785 static const MCPhysReg VSRH[] = {
4786 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4787 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4790 const unsigned NumGPRs = array_lengthof(GPR);
4791 const unsigned NumFPRs = 13;
4792 const unsigned NumVRs = array_lengthof(VR);
4793 const unsigned NumQFPRs = NumFPRs;
4795 // When using the fast calling convention, we don't provide backing for
4796 // arguments that will be in registers.
4797 unsigned NumGPRsUsed = 0, NumFPRsUsed = 0, NumVRsUsed = 0;
4799 // Add up all the space actually used.
4800 for (unsigned i = 0; i != NumOps; ++i) {
4801 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4802 EVT ArgVT = Outs[i].VT;
4803 EVT OrigVT = Outs[i].ArgVT;
4808 if (CallConv == CallingConv::Fast) {
4809 if (Flags.isByVal())
4810 NumGPRsUsed += (Flags.getByValSize()+7)/8;
4812 switch (ArgVT.getSimpleVT().SimpleTy) {
4813 default: llvm_unreachable("Unexpected ValueType for argument!");
4817 if (++NumGPRsUsed <= NumGPRs)
4826 if (++NumVRsUsed <= NumVRs)
4830 // When using QPX, this is handled like a FP register, otherwise, it
4831 // is an Altivec register.
4832 if (Subtarget.hasQPX()) {
4833 if (++NumFPRsUsed <= NumFPRs)
4836 if (++NumVRsUsed <= NumVRs)
4842 case MVT::v4f64: // QPX
4843 case MVT::v4i1: // QPX
4844 if (++NumFPRsUsed <= NumFPRs)
4850 /* Respect alignment of argument on the stack. */
4852 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4853 NumBytes = ((NumBytes + Align - 1) / Align) * Align;
4855 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
4856 if (Flags.isInConsecutiveRegsLast())
4857 NumBytes = ((NumBytes + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
4860 unsigned NumBytesActuallyUsed = NumBytes;
4862 // The prolog code of the callee may store up to 8 GPR argument registers to
4863 // the stack, allowing va_start to index over them in memory if its varargs.
4864 // Because we cannot tell if this is needed on the caller side, we have to
4865 // conservatively assume that it is needed. As such, make sure we have at
4866 // least enough stack space for the caller to store the 8 GPRs.
4867 // FIXME: On ELFv2, it may be unnecessary to allocate the parameter area.
4868 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
4870 // Tail call needs the stack to be aligned.
4871 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4872 CallConv == CallingConv::Fast)
4873 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
4875 // Calculate by how many bytes the stack has to be adjusted in case of tail
4876 // call optimization.
4877 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4879 // To protect arguments on the stack from being clobbered in a tail call,
4880 // force all the loads to happen before doing any other lowering.
4882 Chain = DAG.getStackArgumentTokenFactor(Chain);
4884 // Adjust the stack pointer for the new arguments...
4885 // These operations are automatically eliminated by the prolog/epilog pass
4886 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
4888 SDValue CallSeqStart = Chain;
4890 // Load the return address and frame pointer so it can be move somewhere else
4893 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4896 // Set up a copy of the stack pointer for use loading and storing any
4897 // arguments that may not fit in the registers available for argument
4899 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4901 // Figure out which arguments are going to go in registers, and which in
4902 // memory. Also, if this is a vararg function, floating point operations
4903 // must be stored to our stack, and loaded into integer regs as well, if
4904 // any integer regs are available for argument passing.
4905 unsigned ArgOffset = LinkageSize;
4907 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4908 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4910 SmallVector<SDValue, 8> MemOpChains;
4911 for (unsigned i = 0; i != NumOps; ++i) {
4912 SDValue Arg = OutVals[i];
4913 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4914 EVT ArgVT = Outs[i].VT;
4915 EVT OrigVT = Outs[i].ArgVT;
4917 // PtrOff will be used to store the current argument to the stack if a
4918 // register cannot be found for it.
4921 // We re-align the argument offset for each argument, except when using the
4922 // fast calling convention, when we need to make sure we do that only when
4923 // we'll actually use a stack slot.
4924 auto ComputePtrOff = [&]() {
4925 /* Respect alignment of argument on the stack. */
4927 CalculateStackSlotAlignment(ArgVT, OrigVT, Flags, PtrByteSize);
4928 ArgOffset = ((ArgOffset + Align - 1) / Align) * Align;
4930 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
4932 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4935 if (CallConv != CallingConv::Fast) {
4938 /* Compute GPR index associated with argument offset. */
4939 GPR_idx = (ArgOffset - LinkageSize) / PtrByteSize;
4940 GPR_idx = std::min(GPR_idx, NumGPRs);
4943 // Promote integers to 64-bit values.
4944 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4945 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4946 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4947 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4950 // FIXME memcpy is used way more than necessary. Correctness first.
4951 // Note: "by value" is code for passing a structure by value, not
4953 if (Flags.isByVal()) {
4954 // Note: Size includes alignment padding, so
4955 // struct x { short a; char b; }
4956 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4957 // These are the proper values we need for right-justifying the
4958 // aggregate in a parameter register.
4959 unsigned Size = Flags.getByValSize();
4961 // An empty aggregate parameter takes up no storage and no
4966 if (CallConv == CallingConv::Fast)
4969 // All aggregates smaller than 8 bytes must be passed right-justified.
4970 if (Size==1 || Size==2 || Size==4) {
4971 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4972 if (GPR_idx != NumGPRs) {
4973 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4974 MachinePointerInfo(), VT,
4975 false, false, false, 0);
4976 MemOpChains.push_back(Load.getValue(1));
4977 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4979 ArgOffset += PtrByteSize;
4984 if (GPR_idx == NumGPRs && Size < 8) {
4985 SDValue AddPtr = PtrOff;
4986 if (!isLittleEndian) {
4987 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
4988 PtrOff.getValueType());
4989 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4991 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4994 ArgOffset += PtrByteSize;
4997 // Copy entire object into memory. There are cases where gcc-generated
4998 // code assumes it is there, even if it could be put entirely into
4999 // registers. (This is not what the doc says.)
5001 // FIXME: The above statement is likely due to a misunderstanding of the
5002 // documents. All arguments must be copied into the parameter area BY
5003 // THE CALLEE in the event that the callee takes the address of any
5004 // formal argument. That has not yet been implemented. However, it is
5005 // reasonable to use the stack area as a staging area for the register
5008 // Skip this for small aggregates, as we will use the same slot for a
5009 // right-justified copy, below.
5011 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5015 // When a register is available, pass a small aggregate right-justified.
5016 if (Size < 8 && GPR_idx != NumGPRs) {
5017 // The easiest way to get this right-justified in a register
5018 // is to copy the structure into the rightmost portion of a
5019 // local variable slot, then load the whole slot into the
5021 // FIXME: The memcpy seems to produce pretty awful code for
5022 // small aggregates, particularly for packed ones.
5023 // FIXME: It would be preferable to use the slot in the
5024 // parameter save area instead of a new local variable.
5025 SDValue AddPtr = PtrOff;
5026 if (!isLittleEndian) {
5027 SDValue Const = DAG.getConstant(8 - Size, dl, PtrOff.getValueType());
5028 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5030 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5034 // Load the slot into the register.
5035 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
5036 MachinePointerInfo(),
5037 false, false, false, 0);
5038 MemOpChains.push_back(Load.getValue(1));
5039 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5041 // Done with this argument.
5042 ArgOffset += PtrByteSize;
5046 // For aggregates larger than PtrByteSize, copy the pieces of the
5047 // object that fit into registers from the parameter save area.
5048 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5049 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5050 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5051 if (GPR_idx != NumGPRs) {
5052 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5053 MachinePointerInfo(),
5054 false, false, false, 0);
5055 MemOpChains.push_back(Load.getValue(1));
5056 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5057 ArgOffset += PtrByteSize;
5059 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5066 switch (Arg.getSimpleValueType().SimpleTy) {
5067 default: llvm_unreachable("Unexpected ValueType for argument!");
5071 if (Flags.isNest()) {
5072 // The 'nest' parameter, if any, is passed in R11.
5073 RegsToPass.push_back(std::make_pair(PPC::X11, Arg));
5078 // These can be scalar arguments or elements of an integer array type
5079 // passed directly. Clang may use those instead of "byval" aggregate
5080 // types to avoid forcing arguments to memory unnecessarily.
5081 if (GPR_idx != NumGPRs) {
5082 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5084 if (CallConv == CallingConv::Fast)
5087 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5088 true, isTailCall, false, MemOpChains,
5089 TailCallArguments, dl);
5090 if (CallConv == CallingConv::Fast)
5091 ArgOffset += PtrByteSize;
5093 if (CallConv != CallingConv::Fast)
5094 ArgOffset += PtrByteSize;
5098 // These can be scalar arguments or elements of a float array type
5099 // passed directly. The latter are used to implement ELFv2 homogenous
5100 // float aggregates.
5102 // Named arguments go into FPRs first, and once they overflow, the
5103 // remaining arguments go into GPRs and then the parameter save area.
5104 // Unnamed arguments for vararg functions always go to GPRs and
5105 // then the parameter save area. For now, put all arguments to vararg
5106 // routines always in both locations (FPR *and* GPR or stack slot).
5107 bool NeedGPROrStack = isVarArg || FPR_idx == NumFPRs;
5108 bool NeededLoad = false;
5110 // First load the argument into the next available FPR.
5111 if (FPR_idx != NumFPRs)
5112 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5114 // Next, load the argument into GPR or stack slot if needed.
5115 if (!NeedGPROrStack)
5117 else if (GPR_idx != NumGPRs && CallConv != CallingConv::Fast) {
5118 // FIXME: We may want to re-enable this for CallingConv::Fast on the P8
5119 // once we support fp <-> gpr moves.
5121 // In the non-vararg case, this can only ever happen in the
5122 // presence of f32 array types, since otherwise we never run
5123 // out of FPRs before running out of GPRs.
5126 // Double values are always passed in a single GPR.
5127 if (Arg.getValueType() != MVT::f32) {
5128 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
5130 // Non-array float values are extended and passed in a GPR.
5131 } else if (!Flags.isInConsecutiveRegs()) {
5132 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5133 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5135 // If we have an array of floats, we collect every odd element
5136 // together with its predecessor into one GPR.
5137 } else if (ArgOffset % PtrByteSize != 0) {
5139 Lo = DAG.getNode(ISD::BITCAST, dl, MVT::i32, OutVals[i - 1]);
5140 Hi = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5141 if (!isLittleEndian)
5143 ArgVal = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
5145 // The final element, if even, goes into the first half of a GPR.
5146 } else if (Flags.isInConsecutiveRegsLast()) {
5147 ArgVal = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
5148 ArgVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i64, ArgVal);
5149 if (!isLittleEndian)
5150 ArgVal = DAG.getNode(ISD::SHL, dl, MVT::i64, ArgVal,
5151 DAG.getConstant(32, dl, MVT::i32));
5153 // Non-final even elements are skipped; they will be handled
5154 // together the with subsequent argument on the next go-around.
5158 if (ArgVal.getNode())
5159 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], ArgVal));
5161 if (CallConv == CallingConv::Fast)
5164 // Single-precision floating-point values are mapped to the
5165 // second (rightmost) word of the stack doubleword.
5166 if (Arg.getValueType() == MVT::f32 &&
5167 !isLittleEndian && !Flags.isInConsecutiveRegs()) {
5168 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5169 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5172 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5173 true, isTailCall, false, MemOpChains,
5174 TailCallArguments, dl);
5178 // When passing an array of floats, the array occupies consecutive
5179 // space in the argument area; only round up to the next doubleword
5180 // at the end of the array. Otherwise, each float takes 8 bytes.
5181 if (CallConv != CallingConv::Fast || NeededLoad) {
5182 ArgOffset += (Arg.getValueType() == MVT::f32 &&
5183 Flags.isInConsecutiveRegs()) ? 4 : 8;
5184 if (Flags.isInConsecutiveRegsLast())
5185 ArgOffset = ((ArgOffset + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
5196 if (!Subtarget.hasQPX()) {
5197 // These can be scalar arguments or elements of a vector array type
5198 // passed directly. The latter are used to implement ELFv2 homogenous
5199 // vector aggregates.
5201 // For a varargs call, named arguments go into VRs or on the stack as
5202 // usual; unnamed arguments always go to the stack or the corresponding
5203 // GPRs when within range. For now, we always put the value in both
5204 // locations (or even all three).
5206 // We could elide this store in the case where the object fits
5207 // entirely in R registers. Maybe later.
5208 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5209 MachinePointerInfo(), false, false, 0);
5210 MemOpChains.push_back(Store);
5211 if (VR_idx != NumVRs) {
5212 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5213 MachinePointerInfo(),
5214 false, false, false, 0);
5215 MemOpChains.push_back(Load.getValue(1));
5217 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5218 Arg.getSimpleValueType() == MVT::v2i64) ?
5219 VSRH[VR_idx] : VR[VR_idx];
5222 RegsToPass.push_back(std::make_pair(VReg, Load));
5225 for (unsigned i=0; i<16; i+=PtrByteSize) {
5226 if (GPR_idx == NumGPRs)
5228 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5229 DAG.getConstant(i, dl, PtrVT));
5230 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5231 false, false, false, 0);
5232 MemOpChains.push_back(Load.getValue(1));
5233 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5238 // Non-varargs Altivec params go into VRs or on the stack.
5239 if (VR_idx != NumVRs) {
5240 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
5241 Arg.getSimpleValueType() == MVT::v2i64) ?
5242 VSRH[VR_idx] : VR[VR_idx];
5245 RegsToPass.push_back(std::make_pair(VReg, Arg));
5247 if (CallConv == CallingConv::Fast)
5250 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5251 true, isTailCall, true, MemOpChains,
5252 TailCallArguments, dl);
5253 if (CallConv == CallingConv::Fast)
5257 if (CallConv != CallingConv::Fast)
5262 assert(Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32 &&
5263 "Invalid QPX parameter type");
5268 bool IsF32 = Arg.getValueType().getSimpleVT().SimpleTy == MVT::v4f32;
5270 // We could elide this store in the case where the object fits
5271 // entirely in R registers. Maybe later.
5272 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5273 MachinePointerInfo(), false, false, 0);
5274 MemOpChains.push_back(Store);
5275 if (QFPR_idx != NumQFPRs) {
5276 SDValue Load = DAG.getLoad(IsF32 ? MVT::v4f32 : MVT::v4f64, dl,
5277 Store, PtrOff, MachinePointerInfo(),
5278 false, false, false, 0);
5279 MemOpChains.push_back(Load.getValue(1));
5280 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Load));
5282 ArgOffset += (IsF32 ? 16 : 32);
5283 for (unsigned i = 0; i < (IsF32 ? 16U : 32U); i += PtrByteSize) {
5284 if (GPR_idx == NumGPRs)
5286 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5287 DAG.getConstant(i, dl, PtrVT));
5288 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5289 false, false, false, 0);
5290 MemOpChains.push_back(Load.getValue(1));
5291 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5296 // Non-varargs QPX params go into registers or on the stack.
5297 if (QFPR_idx != NumQFPRs) {
5298 RegsToPass.push_back(std::make_pair(QFPR[QFPR_idx++], Arg));
5300 if (CallConv == CallingConv::Fast)
5303 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5304 true, isTailCall, true, MemOpChains,
5305 TailCallArguments, dl);
5306 if (CallConv == CallingConv::Fast)
5307 ArgOffset += (IsF32 ? 16 : 32);
5310 if (CallConv != CallingConv::Fast)
5311 ArgOffset += (IsF32 ? 16 : 32);
5317 assert(NumBytesActuallyUsed == ArgOffset);
5318 (void)NumBytesActuallyUsed;
5320 if (!MemOpChains.empty())
5321 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5323 // Check if this is an indirect call (MTCTR/BCTRL).
5324 // See PrepareCall() for more information about calls through function
5325 // pointers in the 64-bit SVR4 ABI.
5326 if (!isTailCall && !IsPatchPoint &&
5327 !isFunctionGlobalAddress(Callee) &&
5328 !isa<ExternalSymbolSDNode>(Callee)) {
5329 // Load r2 into a virtual register and store it to the TOC save area.
5330 setUsesTOCBasePtr(DAG);
5331 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
5332 // TOC save area offset.
5333 unsigned TOCSaveOffset = Subtarget.getFrameLowering()->getTOCSaveOffset();
5334 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset, dl);
5335 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5336 Chain = DAG.getStore(
5337 Val.getValue(1), dl, Val, AddPtr,
5338 MachinePointerInfo::getStack(DAG.getMachineFunction(), TOCSaveOffset),
5340 // In the ELFv2 ABI, R12 must contain the address of an indirect callee.
5341 // This does not mean the MTCTR instruction must use R12; it's easier
5342 // to model this as an extra parameter, so do that.
5343 if (isELFv2ABI && !IsPatchPoint)
5344 RegsToPass.push_back(std::make_pair((unsigned)PPC::X12, Callee));
5347 // Build a sequence of copy-to-reg nodes chained together with token chain
5348 // and flag operands which copy the outgoing args into the appropriate regs.
5350 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5351 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5352 RegsToPass[i].second, InFlag);
5353 InFlag = Chain.getValue(1);
5357 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
5358 FPOp, true, TailCallArguments);
5360 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5361 hasNest, DAG, RegsToPass, InFlag, Chain, CallSeqStart,
5362 Callee, SPDiff, NumBytes, Ins, InVals, CS);
5366 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
5367 CallingConv::ID CallConv, bool isVarArg,
5368 bool isTailCall, bool IsPatchPoint,
5369 const SmallVectorImpl<ISD::OutputArg> &Outs,
5370 const SmallVectorImpl<SDValue> &OutVals,
5371 const SmallVectorImpl<ISD::InputArg> &Ins,
5372 SDLoc dl, SelectionDAG &DAG,
5373 SmallVectorImpl<SDValue> &InVals,
5374 ImmutableCallSite *CS) const {
5376 unsigned NumOps = Outs.size();
5378 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5379 bool isPPC64 = PtrVT == MVT::i64;
5380 unsigned PtrByteSize = isPPC64 ? 8 : 4;
5382 MachineFunction &MF = DAG.getMachineFunction();
5384 // Mark this function as potentially containing a function that contains a
5385 // tail call. As a consequence the frame pointer will be used for dynamicalloc
5386 // and restoring the callers stack pointer in this functions epilog. This is
5387 // done because by tail calling the called function might overwrite the value
5388 // in this function's (MF) stack pointer stack slot 0(SP).
5389 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5390 CallConv == CallingConv::Fast)
5391 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
5393 // Count how many bytes are to be pushed on the stack, including the linkage
5394 // area, and parameter passing area. We start with 24/48 bytes, which is
5395 // prereserved space for [SP][CR][LR][3 x unused].
5396 unsigned LinkageSize = Subtarget.getFrameLowering()->getLinkageSize();
5397 unsigned NumBytes = LinkageSize;
5399 // Add up all the space actually used.
5400 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
5401 // they all go in registers, but we must reserve stack space for them for
5402 // possible use by the caller. In varargs or 64-bit calls, parameters are
5403 // assigned stack space in order, with padding so Altivec parameters are
5405 unsigned nAltivecParamsAtEnd = 0;
5406 for (unsigned i = 0; i != NumOps; ++i) {
5407 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5408 EVT ArgVT = Outs[i].VT;
5409 // Varargs Altivec parameters are padded to a 16 byte boundary.
5410 if (ArgVT == MVT::v4f32 || ArgVT == MVT::v4i32 ||
5411 ArgVT == MVT::v8i16 || ArgVT == MVT::v16i8 ||
5412 ArgVT == MVT::v2f64 || ArgVT == MVT::v2i64) {
5413 if (!isVarArg && !isPPC64) {
5414 // Non-varargs Altivec parameters go after all the non-Altivec
5415 // parameters; handle those later so we know how much padding we need.
5416 nAltivecParamsAtEnd++;
5419 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
5420 NumBytes = ((NumBytes+15)/16)*16;
5422 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
5425 // Allow for Altivec parameters at the end, if needed.
5426 if (nAltivecParamsAtEnd) {
5427 NumBytes = ((NumBytes+15)/16)*16;
5428 NumBytes += 16*nAltivecParamsAtEnd;
5431 // The prolog code of the callee may store up to 8 GPR argument registers to
5432 // the stack, allowing va_start to index over them in memory if its varargs.
5433 // Because we cannot tell if this is needed on the caller side, we have to
5434 // conservatively assume that it is needed. As such, make sure we have at
5435 // least enough stack space for the caller to store the 8 GPRs.
5436 NumBytes = std::max(NumBytes, LinkageSize + 8 * PtrByteSize);
5438 // Tail call needs the stack to be aligned.
5439 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
5440 CallConv == CallingConv::Fast)
5441 NumBytes = EnsureStackAlignment(Subtarget.getFrameLowering(), NumBytes);
5443 // Calculate by how many bytes the stack has to be adjusted in case of tail
5444 // call optimization.
5445 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
5447 // To protect arguments on the stack from being clobbered in a tail call,
5448 // force all the loads to happen before doing any other lowering.
5450 Chain = DAG.getStackArgumentTokenFactor(Chain);
5452 // Adjust the stack pointer for the new arguments...
5453 // These operations are automatically eliminated by the prolog/epilog pass
5454 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, dl, true),
5456 SDValue CallSeqStart = Chain;
5458 // Load the return address and frame pointer so it can be move somewhere else
5461 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
5464 // Set up a copy of the stack pointer for use loading and storing any
5465 // arguments that may not fit in the registers available for argument
5469 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
5471 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
5473 // Figure out which arguments are going to go in registers, and which in
5474 // memory. Also, if this is a vararg function, floating point operations
5475 // must be stored to our stack, and loaded into integer regs as well, if
5476 // any integer regs are available for argument passing.
5477 unsigned ArgOffset = LinkageSize;
5478 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
5480 static const MCPhysReg GPR_32[] = { // 32-bit registers.
5481 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
5482 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
5484 static const MCPhysReg GPR_64[] = { // 64-bit registers.
5485 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
5486 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
5488 static const MCPhysReg VR[] = {
5489 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
5490 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
5492 const unsigned NumGPRs = array_lengthof(GPR_32);
5493 const unsigned NumFPRs = 13;
5494 const unsigned NumVRs = array_lengthof(VR);
5496 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
5498 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
5499 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
5501 SmallVector<SDValue, 8> MemOpChains;
5502 for (unsigned i = 0; i != NumOps; ++i) {
5503 SDValue Arg = OutVals[i];
5504 ISD::ArgFlagsTy Flags = Outs[i].Flags;
5506 // PtrOff will be used to store the current argument to the stack if a
5507 // register cannot be found for it.
5510 PtrOff = DAG.getConstant(ArgOffset, dl, StackPtr.getValueType());
5512 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
5514 // On PPC64, promote integers to 64-bit values.
5515 if (isPPC64 && Arg.getValueType() == MVT::i32) {
5516 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
5517 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
5518 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
5521 // FIXME memcpy is used way more than necessary. Correctness first.
5522 // Note: "by value" is code for passing a structure by value, not
5524 if (Flags.isByVal()) {
5525 unsigned Size = Flags.getByValSize();
5526 // Very small objects are passed right-justified. Everything else is
5527 // passed left-justified.
5528 if (Size==1 || Size==2) {
5529 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
5530 if (GPR_idx != NumGPRs) {
5531 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
5532 MachinePointerInfo(), VT,
5533 false, false, false, 0);
5534 MemOpChains.push_back(Load.getValue(1));
5535 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5537 ArgOffset += PtrByteSize;
5539 SDValue Const = DAG.getConstant(PtrByteSize - Size, dl,
5540 PtrOff.getValueType());
5541 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
5542 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
5545 ArgOffset += PtrByteSize;
5549 // Copy entire object into memory. There are cases where gcc-generated
5550 // code assumes it is there, even if it could be put entirely into
5551 // registers. (This is not what the doc says.)
5552 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
5556 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
5557 // copy the pieces of the object that fit into registers from the
5558 // parameter save area.
5559 for (unsigned j=0; j<Size; j+=PtrByteSize) {
5560 SDValue Const = DAG.getConstant(j, dl, PtrOff.getValueType());
5561 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
5562 if (GPR_idx != NumGPRs) {
5563 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
5564 MachinePointerInfo(),
5565 false, false, false, 0);
5566 MemOpChains.push_back(Load.getValue(1));
5567 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5568 ArgOffset += PtrByteSize;
5570 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
5577 switch (Arg.getSimpleValueType().SimpleTy) {
5578 default: llvm_unreachable("Unexpected ValueType for argument!");
5582 if (GPR_idx != NumGPRs) {
5583 if (Arg.getValueType() == MVT::i1)
5584 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
5586 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
5588 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5589 isPPC64, isTailCall, false, MemOpChains,
5590 TailCallArguments, dl);
5592 ArgOffset += PtrByteSize;
5596 if (FPR_idx != NumFPRs) {
5597 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
5600 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5601 MachinePointerInfo(), false, false, 0);
5602 MemOpChains.push_back(Store);
5604 // Float varargs are always shadowed in available integer registers
5605 if (GPR_idx != NumGPRs) {
5606 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5607 MachinePointerInfo(), false, false,
5609 MemOpChains.push_back(Load.getValue(1));
5610 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5612 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
5613 SDValue ConstFour = DAG.getConstant(4, dl, PtrOff.getValueType());
5614 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
5615 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
5616 MachinePointerInfo(),
5617 false, false, false, 0);
5618 MemOpChains.push_back(Load.getValue(1));
5619 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5622 // If we have any FPRs remaining, we may also have GPRs remaining.
5623 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
5625 if (GPR_idx != NumGPRs)
5627 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
5628 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
5632 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5633 isPPC64, isTailCall, false, MemOpChains,
5634 TailCallArguments, dl);
5638 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
5645 // These go aligned on the stack, or in the corresponding R registers
5646 // when within range. The Darwin PPC ABI doc claims they also go in
5647 // V registers; in fact gcc does this only for arguments that are
5648 // prototyped, not for those that match the ... We do it for all
5649 // arguments, seems to work.
5650 while (ArgOffset % 16 !=0) {
5651 ArgOffset += PtrByteSize;
5652 if (GPR_idx != NumGPRs)
5655 // We could elide this store in the case where the object fits
5656 // entirely in R registers. Maybe later.
5657 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
5658 DAG.getConstant(ArgOffset, dl, PtrVT));
5659 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
5660 MachinePointerInfo(), false, false, 0);
5661 MemOpChains.push_back(Store);
5662 if (VR_idx != NumVRs) {
5663 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
5664 MachinePointerInfo(),
5665 false, false, false, 0);
5666 MemOpChains.push_back(Load.getValue(1));
5667 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
5670 for (unsigned i=0; i<16; i+=PtrByteSize) {
5671 if (GPR_idx == NumGPRs)
5673 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
5674 DAG.getConstant(i, dl, PtrVT));
5675 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
5676 false, false, false, 0);
5677 MemOpChains.push_back(Load.getValue(1));
5678 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
5683 // Non-varargs Altivec params generally go in registers, but have
5684 // stack space allocated at the end.
5685 if (VR_idx != NumVRs) {
5686 // Doesn't have GPR space allocated.
5687 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
5688 } else if (nAltivecParamsAtEnd==0) {
5689 // We are emitting Altivec params in order.
5690 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5691 isPPC64, isTailCall, true, MemOpChains,
5692 TailCallArguments, dl);
5698 // If all Altivec parameters fit in registers, as they usually do,
5699 // they get stack space following the non-Altivec parameters. We
5700 // don't track this here because nobody below needs it.
5701 // If there are more Altivec parameters than fit in registers emit
5703 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
5705 // Offset is aligned; skip 1st 12 params which go in V registers.
5706 ArgOffset = ((ArgOffset+15)/16)*16;
5708 for (unsigned i = 0; i != NumOps; ++i) {
5709 SDValue Arg = OutVals[i];
5710 EVT ArgType = Outs[i].VT;
5711 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
5712 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
5715 // We are emitting Altivec params in order.
5716 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
5717 isPPC64, isTailCall, true, MemOpChains,
5718 TailCallArguments, dl);
5725 if (!MemOpChains.empty())
5726 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
5728 // On Darwin, R12 must contain the address of an indirect callee. This does
5729 // not mean the MTCTR instruction must use R12; it's easier to model this as
5730 // an extra parameter, so do that.
5732 !isFunctionGlobalAddress(Callee) &&
5733 !isa<ExternalSymbolSDNode>(Callee) &&
5734 !isBLACompatibleAddress(Callee, DAG))
5735 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
5736 PPC::R12), Callee));
5738 // Build a sequence of copy-to-reg nodes chained together with token chain
5739 // and flag operands which copy the outgoing args into the appropriate regs.
5741 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
5742 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
5743 RegsToPass[i].second, InFlag);
5744 InFlag = Chain.getValue(1);
5748 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
5749 FPOp, true, TailCallArguments);
5751 return FinishCall(CallConv, dl, isTailCall, isVarArg, IsPatchPoint,
5752 /* unused except on PPC64 ELFv1 */ false, DAG,
5753 RegsToPass, InFlag, Chain, CallSeqStart, Callee, SPDiff,
5754 NumBytes, Ins, InVals, CS);
5758 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
5759 MachineFunction &MF, bool isVarArg,
5760 const SmallVectorImpl<ISD::OutputArg> &Outs,
5761 LLVMContext &Context) const {
5762 SmallVector<CCValAssign, 16> RVLocs;
5763 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
5764 return CCInfo.CheckReturn(Outs, RetCC_PPC);
5768 PPCTargetLowering::LowerReturn(SDValue Chain,
5769 CallingConv::ID CallConv, bool isVarArg,
5770 const SmallVectorImpl<ISD::OutputArg> &Outs,
5771 const SmallVectorImpl<SDValue> &OutVals,
5772 SDLoc dl, SelectionDAG &DAG) const {
5774 SmallVector<CCValAssign, 16> RVLocs;
5775 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
5777 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
5780 SmallVector<SDValue, 4> RetOps(1, Chain);
5782 // Copy the result values into the output registers.
5783 for (unsigned i = 0; i != RVLocs.size(); ++i) {
5784 CCValAssign &VA = RVLocs[i];
5785 assert(VA.isRegLoc() && "Can only return in registers!");
5787 SDValue Arg = OutVals[i];
5789 switch (VA.getLocInfo()) {
5790 default: llvm_unreachable("Unknown loc info!");
5791 case CCValAssign::Full: break;
5792 case CCValAssign::AExt:
5793 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
5795 case CCValAssign::ZExt:
5796 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
5798 case CCValAssign::SExt:
5799 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
5803 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
5804 Flag = Chain.getValue(1);
5805 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
5808 RetOps[0] = Chain; // Update chain.
5810 // Add the flag if we have it.
5812 RetOps.push_back(Flag);
5814 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
5817 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
5818 const PPCSubtarget &Subtarget) const {
5819 // When we pop the dynamic allocation we need to restore the SP link.
5822 // Get the corect type for pointers.
5823 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5825 // Construct the stack pointer operand.
5826 bool isPPC64 = Subtarget.isPPC64();
5827 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
5828 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
5830 // Get the operands for the STACKRESTORE.
5831 SDValue Chain = Op.getOperand(0);
5832 SDValue SaveSP = Op.getOperand(1);
5834 // Load the old link SP.
5835 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
5836 MachinePointerInfo(),
5837 false, false, false, 0);
5839 // Restore the stack pointer.
5840 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
5842 // Store the old link SP.
5843 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
5850 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
5851 MachineFunction &MF = DAG.getMachineFunction();
5852 bool isPPC64 = Subtarget.isPPC64();
5853 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5855 // Get current frame pointer save index. The users of this index will be
5856 // primarily DYNALLOC instructions.
5857 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5858 int RASI = FI->getReturnAddrSaveIndex();
5860 // If the frame pointer save index hasn't been defined yet.
5862 // Find out what the fix offset of the frame pointer save area.
5863 int LROffset = Subtarget.getFrameLowering()->getReturnSaveOffset();
5864 // Allocate the frame index for frame pointer save area.
5865 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, false);
5867 FI->setReturnAddrSaveIndex(RASI);
5869 return DAG.getFrameIndex(RASI, PtrVT);
5873 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
5874 MachineFunction &MF = DAG.getMachineFunction();
5875 bool isPPC64 = Subtarget.isPPC64();
5876 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
5878 // Get current frame pointer save index. The users of this index will be
5879 // primarily DYNALLOC instructions.
5880 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
5881 int FPSI = FI->getFramePointerSaveIndex();
5883 // If the frame pointer save index hasn't been defined yet.
5885 // Find out what the fix offset of the frame pointer save area.
5886 int FPOffset = Subtarget.getFrameLowering()->getFramePointerSaveOffset();
5887 // Allocate the frame index for frame pointer save area.
5888 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
5890 FI->setFramePointerSaveIndex(FPSI);
5892 return DAG.getFrameIndex(FPSI, PtrVT);
5895 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
5897 const PPCSubtarget &Subtarget) const {
5899 SDValue Chain = Op.getOperand(0);
5900 SDValue Size = Op.getOperand(1);
5903 // Get the corect type for pointers.
5904 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
5906 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
5907 DAG.getConstant(0, dl, PtrVT), Size);
5908 // Construct a node for the frame pointer save index.
5909 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
5910 // Build a DYNALLOC node.
5911 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
5912 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
5913 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
5916 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
5917 SelectionDAG &DAG) const {
5919 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
5920 DAG.getVTList(MVT::i32, MVT::Other),
5921 Op.getOperand(0), Op.getOperand(1));
5924 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
5925 SelectionDAG &DAG) const {
5927 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
5928 Op.getOperand(0), Op.getOperand(1));
5931 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
5932 if (Op.getValueType().isVector())
5933 return LowerVectorLoad(Op, DAG);
5935 assert(Op.getValueType() == MVT::i1 &&
5936 "Custom lowering only for i1 loads");
5938 // First, load 8 bits into 32 bits, then truncate to 1 bit.
5941 LoadSDNode *LD = cast<LoadSDNode>(Op);
5943 SDValue Chain = LD->getChain();
5944 SDValue BasePtr = LD->getBasePtr();
5945 MachineMemOperand *MMO = LD->getMemOperand();
5948 DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(DAG.getDataLayout()), Chain,
5949 BasePtr, MVT::i8, MMO);
5950 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
5952 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
5953 return DAG.getMergeValues(Ops, dl);
5956 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
5957 if (Op.getOperand(1).getValueType().isVector())
5958 return LowerVectorStore(Op, DAG);
5960 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
5961 "Custom lowering only for i1 stores");
5963 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
5966 StoreSDNode *ST = cast<StoreSDNode>(Op);
5968 SDValue Chain = ST->getChain();
5969 SDValue BasePtr = ST->getBasePtr();
5970 SDValue Value = ST->getValue();
5971 MachineMemOperand *MMO = ST->getMemOperand();
5973 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(DAG.getDataLayout()),
5975 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
5978 // FIXME: Remove this once the ANDI glue bug is fixed:
5979 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
5980 assert(Op.getValueType() == MVT::i1 &&
5981 "Custom lowering only for i1 results");
5984 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
5988 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
5990 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
5991 // Not FP? Not a fsel.
5992 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5993 !Op.getOperand(2).getValueType().isFloatingPoint())
5996 // We might be able to do better than this under some circumstances, but in
5997 // general, fsel-based lowering of select is a finite-math-only optimization.
5998 // For more information, see section F.3 of the 2.06 ISA specification.
5999 if (!DAG.getTarget().Options.NoInfsFPMath ||
6000 !DAG.getTarget().Options.NoNaNsFPMath)
6002 // TODO: Propagate flags from the select rather than global settings.
6004 Flags.setNoInfs(true);
6005 Flags.setNoNaNs(true);
6007 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
6009 EVT ResVT = Op.getValueType();
6010 EVT CmpVT = Op.getOperand(0).getValueType();
6011 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6012 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
6015 // If the RHS of the comparison is a 0.0, we don't need to do the
6016 // subtraction at all.
6018 if (isFloatingPointZero(RHS))
6020 default: break; // SETUO etc aren't handled by fsel.
6024 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6025 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6026 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6027 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6028 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6029 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6030 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
6033 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6036 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6037 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6038 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
6041 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
6044 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
6045 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
6046 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6047 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
6052 default: break; // SETUO etc aren't handled by fsel.
6056 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6057 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6058 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6059 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6060 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
6061 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
6062 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
6063 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
6066 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6067 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6068 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6069 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6072 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS, &Flags);
6073 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6074 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6075 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6078 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6079 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6080 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6081 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
6084 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS, &Flags);
6085 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
6086 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
6087 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
6092 void PPCTargetLowering::LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
6095 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6096 SDValue Src = Op.getOperand(0);
6097 if (Src.getValueType() == MVT::f32)
6098 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6101 switch (Op.getSimpleValueType().SimpleTy) {
6102 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6105 Op.getOpcode() == ISD::FP_TO_SINT
6107 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6111 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6112 "i64 FP_TO_UINT is supported only with FPCVT");
6113 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6119 // Convert the FP value to an int value through memory.
6120 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
6121 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
6122 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
6123 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
6124 MachinePointerInfo MPI =
6125 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI);
6127 // Emit a store to the stack slot.
6130 MachineFunction &MF = DAG.getMachineFunction();
6131 MachineMemOperand *MMO =
6132 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
6133 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
6134 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
6135 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
6137 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
6138 MPI, false, false, 0);
6140 // Result is a load from the stack slot. If loading 4 bytes, make sure to
6142 if (Op.getValueType() == MVT::i32 && !i32Stack) {
6143 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
6144 DAG.getConstant(4, dl, FIPtr.getValueType()));
6145 MPI = MPI.getWithOffset(4);
6153 /// \brief Custom lowers floating point to integer conversions to use
6154 /// the direct move instructions available in ISA 2.07 to avoid the
6155 /// need for load/store combinations.
6156 SDValue PPCTargetLowering::LowerFP_TO_INTDirectMove(SDValue Op,
6159 assert(Op.getOperand(0).getValueType().isFloatingPoint());
6160 SDValue Src = Op.getOperand(0);
6162 if (Src.getValueType() == MVT::f32)
6163 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
6166 switch (Op.getSimpleValueType().SimpleTy) {
6167 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
6170 Op.getOpcode() == ISD::FP_TO_SINT
6172 : (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ : PPCISD::FCTIDZ),
6174 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i32, Tmp);
6177 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
6178 "i64 FP_TO_UINT is supported only with FPCVT");
6179 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
6182 Tmp = DAG.getNode(PPCISD::MFVSR, dl, MVT::i64, Tmp);
6188 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
6190 if (Subtarget.hasDirectMove() && Subtarget.isPPC64())
6191 return LowerFP_TO_INTDirectMove(Op, DAG, dl);
6194 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6196 return DAG.getLoad(Op.getValueType(), dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6197 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6201 // We're trying to insert a regular store, S, and then a load, L. If the
6202 // incoming value, O, is a load, we might just be able to have our load use the
6203 // address used by O. However, we don't know if anything else will store to
6204 // that address before we can load from it. To prevent this situation, we need
6205 // to insert our load, L, into the chain as a peer of O. To do this, we give L
6206 // the same chain operand as O, we create a token factor from the chain results
6207 // of O and L, and we replace all uses of O's chain result with that token
6208 // factor (see spliceIntoChain below for this last part).
6209 bool PPCTargetLowering::canReuseLoadAddress(SDValue Op, EVT MemVT,
6212 ISD::LoadExtType ET) const {
6214 if (ET == ISD::NON_EXTLOAD &&
6215 (Op.getOpcode() == ISD::FP_TO_UINT ||
6216 Op.getOpcode() == ISD::FP_TO_SINT) &&
6217 isOperationLegalOrCustom(Op.getOpcode(),
6218 Op.getOperand(0).getValueType())) {
6220 LowerFP_TO_INTForReuse(Op, RLI, DAG, dl);
6224 LoadSDNode *LD = dyn_cast<LoadSDNode>(Op);
6225 if (!LD || LD->getExtensionType() != ET || LD->isVolatile() ||
6226 LD->isNonTemporal())
6228 if (LD->getMemoryVT() != MemVT)
6231 RLI.Ptr = LD->getBasePtr();
6232 if (LD->isIndexed() && LD->getOffset().getOpcode() != ISD::UNDEF) {
6233 assert(LD->getAddressingMode() == ISD::PRE_INC &&
6234 "Non-pre-inc AM on PPC?");
6235 RLI.Ptr = DAG.getNode(ISD::ADD, dl, RLI.Ptr.getValueType(), RLI.Ptr,
6239 RLI.Chain = LD->getChain();
6240 RLI.MPI = LD->getPointerInfo();
6241 RLI.IsInvariant = LD->isInvariant();
6242 RLI.Alignment = LD->getAlignment();
6243 RLI.AAInfo = LD->getAAInfo();
6244 RLI.Ranges = LD->getRanges();
6246 RLI.ResChain = SDValue(LD, LD->isIndexed() ? 2 : 1);
6250 // Given the head of the old chain, ResChain, insert a token factor containing
6251 // it and NewResChain, and make users of ResChain now be users of that token
6253 void PPCTargetLowering::spliceIntoChain(SDValue ResChain,
6254 SDValue NewResChain,
6255 SelectionDAG &DAG) const {
6259 SDLoc dl(NewResChain);
6261 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
6262 NewResChain, DAG.getUNDEF(MVT::Other));
6263 assert(TF.getNode() != NewResChain.getNode() &&
6264 "A new TF really is required here");
6266 DAG.ReplaceAllUsesOfValueWith(ResChain, TF);
6267 DAG.UpdateNodeOperands(TF.getNode(), ResChain, NewResChain);
6270 /// \brief Custom lowers integer to floating point conversions to use
6271 /// the direct move instructions available in ISA 2.07 to avoid the
6272 /// need for load/store combinations.
6273 SDValue PPCTargetLowering::LowerINT_TO_FPDirectMove(SDValue Op,
6276 assert((Op.getValueType() == MVT::f32 ||
6277 Op.getValueType() == MVT::f64) &&
6278 "Invalid floating point type as target of conversion");
6279 assert(Subtarget.hasFPCVT() &&
6280 "Int to FP conversions with direct moves require FPCVT");
6282 SDValue Src = Op.getOperand(0);
6283 bool SinglePrec = Op.getValueType() == MVT::f32;
6284 bool WordInt = Src.getSimpleValueType().SimpleTy == MVT::i32;
6285 bool Signed = Op.getOpcode() == ISD::SINT_TO_FP;
6286 unsigned ConvOp = Signed ? (SinglePrec ? PPCISD::FCFIDS : PPCISD::FCFID) :
6287 (SinglePrec ? PPCISD::FCFIDUS : PPCISD::FCFIDU);
6290 FP = DAG.getNode(Signed ? PPCISD::MTVSRA : PPCISD::MTVSRZ,
6292 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6295 FP = DAG.getNode(PPCISD::MTVSRA, dl, MVT::f64, Src);
6296 FP = DAG.getNode(ConvOp, dl, SinglePrec ? MVT::f32 : MVT::f64, FP);
6302 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
6303 SelectionDAG &DAG) const {
6306 if (Subtarget.hasQPX() && Op.getOperand(0).getValueType() == MVT::v4i1) {
6307 if (Op.getValueType() != MVT::v4f32 && Op.getValueType() != MVT::v4f64)
6310 SDValue Value = Op.getOperand(0);
6311 // The values are now known to be -1 (false) or 1 (true). To convert this
6312 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
6313 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
6314 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
6316 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
6317 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6318 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
6320 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
6322 if (Op.getValueType() != MVT::v4f64)
6323 Value = DAG.getNode(ISD::FP_ROUND, dl,
6324 Op.getValueType(), Value,
6325 DAG.getIntPtrConstant(1, dl));
6329 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
6330 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
6333 if (Op.getOperand(0).getValueType() == MVT::i1)
6334 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
6335 DAG.getConstantFP(1.0, dl, Op.getValueType()),
6336 DAG.getConstantFP(0.0, dl, Op.getValueType()));
6338 // If we have direct moves, we can do all the conversion, skip the store/load
6339 // however, without FPCVT we can't do most conversions.
6340 if (Subtarget.hasDirectMove() && Subtarget.isPPC64() && Subtarget.hasFPCVT())
6341 return LowerINT_TO_FPDirectMove(Op, DAG, dl);
6343 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
6344 "UINT_TO_FP is supported only with FPCVT");
6346 // If we have FCFIDS, then use it when converting to single-precision.
6347 // Otherwise, convert to double-precision and then round.
6348 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6349 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
6351 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
6353 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
6357 if (Op.getOperand(0).getValueType() == MVT::i64) {
6358 SDValue SINT = Op.getOperand(0);
6359 // When converting to single-precision, we actually need to convert
6360 // to double-precision first and then round to single-precision.
6361 // To avoid double-rounding effects during that operation, we have
6362 // to prepare the input operand. Bits that might be truncated when
6363 // converting to double-precision are replaced by a bit that won't
6364 // be lost at this stage, but is below the single-precision rounding
6367 // However, if -enable-unsafe-fp-math is in effect, accept double
6368 // rounding to avoid the extra overhead.
6369 if (Op.getValueType() == MVT::f32 &&
6370 !Subtarget.hasFPCVT() &&
6371 !DAG.getTarget().Options.UnsafeFPMath) {
6373 // Twiddle input to make sure the low 11 bits are zero. (If this
6374 // is the case, we are guaranteed the value will fit into the 53 bit
6375 // mantissa of an IEEE double-precision value without rounding.)
6376 // If any of those low 11 bits were not zero originally, make sure
6377 // bit 12 (value 2048) is set instead, so that the final rounding
6378 // to single-precision gets the correct result.
6379 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6380 SINT, DAG.getConstant(2047, dl, MVT::i64));
6381 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
6382 Round, DAG.getConstant(2047, dl, MVT::i64));
6383 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
6384 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
6385 Round, DAG.getConstant(-2048, dl, MVT::i64));
6387 // However, we cannot use that value unconditionally: if the magnitude
6388 // of the input value is small, the bit-twiddling we did above might
6389 // end up visibly changing the output. Fortunately, in that case, we
6390 // don't need to twiddle bits since the original input will convert
6391 // exactly to double-precision floating-point already. Therefore,
6392 // construct a conditional to use the original value if the top 11
6393 // bits are all sign-bit copies, and use the rounded value computed
6395 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
6396 SINT, DAG.getConstant(53, dl, MVT::i32));
6397 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
6398 Cond, DAG.getConstant(1, dl, MVT::i64));
6399 Cond = DAG.getSetCC(dl, MVT::i32,
6400 Cond, DAG.getConstant(1, dl, MVT::i64), ISD::SETUGT);
6402 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
6408 MachineFunction &MF = DAG.getMachineFunction();
6409 if (canReuseLoadAddress(SINT, MVT::i64, RLI, DAG)) {
6410 Bits = DAG.getLoad(MVT::f64, dl, RLI.Chain, RLI.Ptr, RLI.MPI, false,
6411 false, RLI.IsInvariant, RLI.Alignment, RLI.AAInfo,
6413 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6414 } else if (Subtarget.hasLFIWAX() &&
6415 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::SEXTLOAD)) {
6416 MachineMemOperand *MMO =
6417 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6418 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6419 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6420 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWAX, dl,
6421 DAG.getVTList(MVT::f64, MVT::Other),
6422 Ops, MVT::i32, MMO);
6423 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6424 } else if (Subtarget.hasFPCVT() &&
6425 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
6426 MachineMemOperand *MMO =
6427 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6428 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6429 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6430 Bits = DAG.getMemIntrinsicNode(PPCISD::LFIWZX, dl,
6431 DAG.getVTList(MVT::f64, MVT::Other),
6432 Ops, MVT::i32, MMO);
6433 spliceIntoChain(RLI.ResChain, Bits.getValue(1), DAG);
6434 } else if (((Subtarget.hasLFIWAX() &&
6435 SINT.getOpcode() == ISD::SIGN_EXTEND) ||
6436 (Subtarget.hasFPCVT() &&
6437 SINT.getOpcode() == ISD::ZERO_EXTEND)) &&
6438 SINT.getOperand(0).getValueType() == MVT::i32) {
6439 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6440 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(DAG.getDataLayout());
6442 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6443 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6445 SDValue Store = DAG.getStore(
6446 DAG.getEntryNode(), dl, SINT.getOperand(0), FIdx,
6447 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6450 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6451 "Expected an i32 store");
6456 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6459 MachineMemOperand *MMO =
6460 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6461 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6462 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6463 Bits = DAG.getMemIntrinsicNode(SINT.getOpcode() == ISD::ZERO_EXTEND ?
6464 PPCISD::LFIWZX : PPCISD::LFIWAX,
6465 dl, DAG.getVTList(MVT::f64, MVT::Other),
6466 Ops, MVT::i32, MMO);
6468 Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
6470 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
6472 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6473 FP = DAG.getNode(ISD::FP_ROUND, dl,
6474 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
6478 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
6479 "Unhandled INT_TO_FP type in custom expander!");
6480 // Since we only generate this in 64-bit mode, we can take advantage of
6481 // 64-bit registers. In particular, sign extend the input value into the
6482 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
6483 // then lfd it and fcfid it.
6484 MachineFunction &MF = DAG.getMachineFunction();
6485 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
6486 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6489 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
6492 if (!(ReusingLoad = canReuseLoadAddress(Op.getOperand(0), MVT::i32, RLI,
6494 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
6495 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6497 SDValue Store = DAG.getStore(
6498 DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
6499 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6502 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
6503 "Expected an i32 store");
6508 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6512 MachineMemOperand *MMO =
6513 MF.getMachineMemOperand(RLI.MPI, MachineMemOperand::MOLoad, 4,
6514 RLI.Alignment, RLI.AAInfo, RLI.Ranges);
6515 SDValue Ops[] = { RLI.Chain, RLI.Ptr };
6516 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
6517 PPCISD::LFIWZX : PPCISD::LFIWAX,
6518 dl, DAG.getVTList(MVT::f64, MVT::Other),
6519 Ops, MVT::i32, MMO);
6521 spliceIntoChain(RLI.ResChain, Ld.getValue(1), DAG);
6523 assert(Subtarget.isPPC64() &&
6524 "i32->FP without LFIWAX supported only on PPC64");
6526 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
6527 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6529 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
6532 // STD the extended value into the stack slot.
6533 SDValue Store = DAG.getStore(
6534 DAG.getEntryNode(), dl, Ext64, FIdx,
6535 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6538 // Load the value as a double.
6540 MVT::f64, dl, Store, FIdx,
6541 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx),
6542 false, false, false, 0);
6545 // FCFID it and return it.
6546 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
6547 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
6548 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP,
6549 DAG.getIntPtrConstant(0, dl));
6553 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
6554 SelectionDAG &DAG) const {
6557 The rounding mode is in bits 30:31 of FPSR, and has the following
6564 FLT_ROUNDS, on the other hand, expects the following:
6571 To perform the conversion, we do:
6572 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
6575 MachineFunction &MF = DAG.getMachineFunction();
6576 EVT VT = Op.getValueType();
6577 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
6579 // Save FP Control Word to register
6581 MVT::f64, // return register
6582 MVT::Glue // unused in this context
6584 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
6586 // Save FP register to stack slot
6587 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
6588 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
6589 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
6590 StackSlot, MachinePointerInfo(), false, false,0);
6592 // Load FP Control Word from low 32 bits of stack slot.
6593 SDValue Four = DAG.getConstant(4, dl, PtrVT);
6594 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
6595 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
6596 false, false, false, 0);
6598 // Transform as necessary
6600 DAG.getNode(ISD::AND, dl, MVT::i32,
6601 CWD, DAG.getConstant(3, dl, MVT::i32));
6603 DAG.getNode(ISD::SRL, dl, MVT::i32,
6604 DAG.getNode(ISD::AND, dl, MVT::i32,
6605 DAG.getNode(ISD::XOR, dl, MVT::i32,
6606 CWD, DAG.getConstant(3, dl, MVT::i32)),
6607 DAG.getConstant(3, dl, MVT::i32)),
6608 DAG.getConstant(1, dl, MVT::i32));
6611 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
6613 return DAG.getNode((VT.getSizeInBits() < 16 ?
6614 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
6617 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6618 EVT VT = Op.getValueType();
6619 unsigned BitWidth = VT.getSizeInBits();
6621 assert(Op.getNumOperands() == 3 &&
6622 VT == Op.getOperand(1).getValueType() &&
6625 // Expand into a bunch of logical ops. Note that these ops
6626 // depend on the PPC behavior for oversized shift amounts.
6627 SDValue Lo = Op.getOperand(0);
6628 SDValue Hi = Op.getOperand(1);
6629 SDValue Amt = Op.getOperand(2);
6630 EVT AmtVT = Amt.getValueType();
6632 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6633 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6634 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
6635 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
6636 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
6637 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6638 DAG.getConstant(-BitWidth, dl, AmtVT));
6639 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
6640 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6641 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
6642 SDValue OutOps[] = { OutLo, OutHi };
6643 return DAG.getMergeValues(OutOps, dl);
6646 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
6647 EVT VT = Op.getValueType();
6649 unsigned BitWidth = VT.getSizeInBits();
6650 assert(Op.getNumOperands() == 3 &&
6651 VT == Op.getOperand(1).getValueType() &&
6654 // Expand into a bunch of logical ops. Note that these ops
6655 // depend on the PPC behavior for oversized shift amounts.
6656 SDValue Lo = Op.getOperand(0);
6657 SDValue Hi = Op.getOperand(1);
6658 SDValue Amt = Op.getOperand(2);
6659 EVT AmtVT = Amt.getValueType();
6661 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6662 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6663 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6664 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6665 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6666 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6667 DAG.getConstant(-BitWidth, dl, AmtVT));
6668 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
6669 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
6670 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
6671 SDValue OutOps[] = { OutLo, OutHi };
6672 return DAG.getMergeValues(OutOps, dl);
6675 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
6677 EVT VT = Op.getValueType();
6678 unsigned BitWidth = VT.getSizeInBits();
6679 assert(Op.getNumOperands() == 3 &&
6680 VT == Op.getOperand(1).getValueType() &&
6683 // Expand into a bunch of logical ops, followed by a select_cc.
6684 SDValue Lo = Op.getOperand(0);
6685 SDValue Hi = Op.getOperand(1);
6686 SDValue Amt = Op.getOperand(2);
6687 EVT AmtVT = Amt.getValueType();
6689 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
6690 DAG.getConstant(BitWidth, dl, AmtVT), Amt);
6691 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
6692 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
6693 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
6694 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
6695 DAG.getConstant(-BitWidth, dl, AmtVT));
6696 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
6697 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
6698 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, dl, AmtVT),
6699 Tmp4, Tmp6, ISD::SETLE);
6700 SDValue OutOps[] = { OutLo, OutHi };
6701 return DAG.getMergeValues(OutOps, dl);
6704 //===----------------------------------------------------------------------===//
6705 // Vector related lowering.
6708 /// BuildSplatI - Build a canonical splati of Val with an element size of
6709 /// SplatSize. Cast the result to VT.
6710 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
6711 SelectionDAG &DAG, SDLoc dl) {
6712 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
6714 static const MVT VTys[] = { // canonical VT to use for each size.
6715 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
6718 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
6720 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
6724 EVT CanonicalVT = VTys[SplatSize-1];
6726 // Build a canonical splat for this value.
6727 SDValue Elt = DAG.getConstant(Val, dl, MVT::i32);
6728 SmallVector<SDValue, 8> Ops;
6729 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
6730 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
6731 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
6734 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
6735 /// specified intrinsic ID.
6736 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
6737 SelectionDAG &DAG, SDLoc dl,
6738 EVT DestVT = MVT::Other) {
6739 if (DestVT == MVT::Other) DestVT = Op.getValueType();
6740 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6741 DAG.getConstant(IID, dl, MVT::i32), Op);
6744 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
6745 /// specified intrinsic ID.
6746 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
6747 SelectionDAG &DAG, SDLoc dl,
6748 EVT DestVT = MVT::Other) {
6749 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
6750 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6751 DAG.getConstant(IID, dl, MVT::i32), LHS, RHS);
6754 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
6755 /// specified intrinsic ID.
6756 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
6757 SDValue Op2, SelectionDAG &DAG,
6758 SDLoc dl, EVT DestVT = MVT::Other) {
6759 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
6760 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
6761 DAG.getConstant(IID, dl, MVT::i32), Op0, Op1, Op2);
6765 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
6766 /// amount. The result has the specified value type.
6767 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
6768 EVT VT, SelectionDAG &DAG, SDLoc dl) {
6769 // Force LHS/RHS to be the right type.
6770 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
6771 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
6774 for (unsigned i = 0; i != 16; ++i)
6776 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
6777 return DAG.getNode(ISD::BITCAST, dl, VT, T);
6780 // If this is a case we can't handle, return null and let the default
6781 // expansion code take care of it. If we CAN select this case, and if it
6782 // selects to a single instruction, return Op. Otherwise, if we can codegen
6783 // this case more efficiently than a constant pool load, lower it to the
6784 // sequence of ops that should be used.
6785 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
6786 SelectionDAG &DAG) const {
6788 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
6789 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
6791 if (Subtarget.hasQPX() && Op.getValueType() == MVT::v4i1) {
6792 // We first build an i32 vector, load it into a QPX register,
6793 // then convert it to a floating-point vector and compare it
6794 // to a zero vector to get the boolean result.
6795 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6796 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6797 MachinePointerInfo PtrInfo =
6798 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
6799 EVT PtrVT = getPointerTy(DAG.getDataLayout());
6800 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6802 assert(BVN->getNumOperands() == 4 &&
6803 "BUILD_VECTOR for v4i1 does not have 4 operands");
6805 bool IsConst = true;
6806 for (unsigned i = 0; i < 4; ++i) {
6807 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6808 if (!isa<ConstantSDNode>(BVN->getOperand(i))) {
6816 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), 1.0);
6818 ConstantFP::get(Type::getFloatTy(*DAG.getContext()), -1.0);
6820 SmallVector<Constant*, 4> CV(4, NegOne);
6821 for (unsigned i = 0; i < 4; ++i) {
6822 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF)
6823 CV[i] = UndefValue::get(Type::getFloatTy(*DAG.getContext()));
6824 else if (cast<ConstantSDNode>(BVN->getOperand(i))->
6825 getConstantIntValue()->isZero())
6831 Constant *CP = ConstantVector::get(CV);
6832 SDValue CPIdx = DAG.getConstantPool(CP, getPointerTy(DAG.getDataLayout()),
6833 16 /* alignment */);
6835 SmallVector<SDValue, 2> Ops;
6836 Ops.push_back(DAG.getEntryNode());
6837 Ops.push_back(CPIdx);
6839 SmallVector<EVT, 2> ValueVTs;
6840 ValueVTs.push_back(MVT::v4i1);
6841 ValueVTs.push_back(MVT::Other); // chain
6842 SDVTList VTs = DAG.getVTList(ValueVTs);
6844 return DAG.getMemIntrinsicNode(
6845 PPCISD::QVLFSb, dl, VTs, Ops, MVT::v4f32,
6846 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()));
6849 SmallVector<SDValue, 4> Stores;
6850 for (unsigned i = 0; i < 4; ++i) {
6851 if (BVN->getOperand(i).getOpcode() == ISD::UNDEF) continue;
6853 unsigned Offset = 4*i;
6854 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
6855 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
6857 unsigned StoreSize = BVN->getOperand(i).getValueType().getStoreSize();
6858 if (StoreSize > 4) {
6859 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl,
6860 BVN->getOperand(i), Idx,
6861 PtrInfo.getWithOffset(Offset),
6862 MVT::i32, false, false, 0));
6864 SDValue StoreValue = BVN->getOperand(i);
6866 StoreValue = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, StoreValue);
6868 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl,
6870 PtrInfo.getWithOffset(Offset),
6876 if (!Stores.empty())
6877 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
6879 StoreChain = DAG.getEntryNode();
6881 // Now load from v4i32 into the QPX register; this will extend it to
6882 // v4i64 but not yet convert it to a floating point. Nevertheless, this
6883 // is typed as v4f64 because the QPX register integer states are not
6884 // explicitly represented.
6886 SmallVector<SDValue, 2> Ops;
6887 Ops.push_back(StoreChain);
6888 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvlfiwz, dl, MVT::i32));
6889 Ops.push_back(FIdx);
6891 SmallVector<EVT, 2> ValueVTs;
6892 ValueVTs.push_back(MVT::v4f64);
6893 ValueVTs.push_back(MVT::Other); // chain
6894 SDVTList VTs = DAG.getVTList(ValueVTs);
6896 SDValue LoadedVect = DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN,
6897 dl, VTs, Ops, MVT::v4i32, PtrInfo);
6898 LoadedVect = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
6899 DAG.getConstant(Intrinsic::ppc_qpx_qvfcfidu, dl, MVT::i32),
6902 SDValue FPZeros = DAG.getConstantFP(0.0, dl, MVT::f64);
6903 FPZeros = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
6904 FPZeros, FPZeros, FPZeros, FPZeros);
6906 return DAG.getSetCC(dl, MVT::v4i1, LoadedVect, FPZeros, ISD::SETEQ);
6909 // All other QPX vectors are handled by generic code.
6910 if (Subtarget.hasQPX())
6913 // Check if this is a splat of a constant value.
6914 APInt APSplatBits, APSplatUndef;
6915 unsigned SplatBitSize;
6917 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
6918 HasAnyUndefs, 0, !Subtarget.isLittleEndian()) ||
6922 unsigned SplatBits = APSplatBits.getZExtValue();
6923 unsigned SplatUndef = APSplatUndef.getZExtValue();
6924 unsigned SplatSize = SplatBitSize / 8;
6926 // First, handle single instruction cases.
6929 if (SplatBits == 0) {
6930 // Canonicalize all zero vectors to be v4i32.
6931 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
6932 SDValue Z = DAG.getConstant(0, dl, MVT::i32);
6933 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
6934 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
6939 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
6940 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
6942 if (SextVal >= -16 && SextVal <= 15)
6943 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
6946 // Two instruction sequences.
6948 // If this value is in the range [-32,30] and is even, use:
6949 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
6950 // If this value is in the range [17,31] and is odd, use:
6951 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
6952 // If this value is in the range [-31,-17] and is odd, use:
6953 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
6954 // Note the last two are three-instruction sequences.
6955 if (SextVal >= -32 && SextVal <= 31) {
6956 // To avoid having these optimizations undone by constant folding,
6957 // we convert to a pseudo that will be expanded later into one of
6959 SDValue Elt = DAG.getConstant(SextVal, dl, MVT::i32);
6960 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
6961 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
6962 SDValue EltSize = DAG.getConstant(SplatSize, dl, MVT::i32);
6963 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
6964 if (VT == Op.getValueType())
6967 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
6970 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
6971 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
6973 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
6974 // Make -1 and vspltisw -1:
6975 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
6977 // Make the VSLW intrinsic, computing 0x8000_0000.
6978 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
6981 // xor by OnesV to invert it.
6982 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
6983 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
6986 // Check to see if this is a wide variety of vsplti*, binop self cases.
6987 static const signed char SplatCsts[] = {
6988 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
6989 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
6992 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
6993 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
6994 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
6995 int i = SplatCsts[idx];
6997 // Figure out what shift amount will be used by altivec if shifted by i in
6999 unsigned TypeShiftAmt = i & (SplatBitSize-1);
7001 // vsplti + shl self.
7002 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
7003 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7004 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7005 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
7006 Intrinsic::ppc_altivec_vslw
7008 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7009 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7012 // vsplti + srl self.
7013 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7014 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7015 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7016 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
7017 Intrinsic::ppc_altivec_vsrw
7019 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7020 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7023 // vsplti + sra self.
7024 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
7025 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7026 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7027 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
7028 Intrinsic::ppc_altivec_vsraw
7030 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7031 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7034 // vsplti + rol self.
7035 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
7036 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
7037 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
7038 static const unsigned IIDs[] = { // Intrinsic to use for each size.
7039 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
7040 Intrinsic::ppc_altivec_vrlw
7042 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
7043 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
7046 // t = vsplti c, result = vsldoi t, t, 1
7047 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
7048 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7049 unsigned Amt = Subtarget.isLittleEndian() ? 15 : 1;
7050 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7052 // t = vsplti c, result = vsldoi t, t, 2
7053 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
7054 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7055 unsigned Amt = Subtarget.isLittleEndian() ? 14 : 2;
7056 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7058 // t = vsplti c, result = vsldoi t, t, 3
7059 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
7060 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
7061 unsigned Amt = Subtarget.isLittleEndian() ? 13 : 3;
7062 return BuildVSLDOI(T, T, Amt, Op.getValueType(), DAG, dl);
7069 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
7070 /// the specified operations to build the shuffle.
7071 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
7072 SDValue RHS, SelectionDAG &DAG,
7074 unsigned OpNum = (PFEntry >> 26) & 0x0F;
7075 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
7076 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
7079 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
7091 if (OpNum == OP_COPY) {
7092 if (LHSID == (1*9+2)*9+3) return LHS;
7093 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
7097 SDValue OpLHS, OpRHS;
7098 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
7099 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
7103 default: llvm_unreachable("Unknown i32 permute!");
7105 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
7106 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
7107 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
7108 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
7111 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
7112 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
7113 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
7114 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
7117 for (unsigned i = 0; i != 16; ++i)
7118 ShufIdxs[i] = (i&3)+0;
7121 for (unsigned i = 0; i != 16; ++i)
7122 ShufIdxs[i] = (i&3)+4;
7125 for (unsigned i = 0; i != 16; ++i)
7126 ShufIdxs[i] = (i&3)+8;
7129 for (unsigned i = 0; i != 16; ++i)
7130 ShufIdxs[i] = (i&3)+12;
7133 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
7135 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
7137 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
7139 EVT VT = OpLHS.getValueType();
7140 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
7141 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
7142 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
7143 return DAG.getNode(ISD::BITCAST, dl, VT, T);
7146 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
7147 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
7148 /// return the code it can be lowered into. Worst case, it can always be
7149 /// lowered into a vperm.
7150 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
7151 SelectionDAG &DAG) const {
7153 SDValue V1 = Op.getOperand(0);
7154 SDValue V2 = Op.getOperand(1);
7155 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
7156 EVT VT = Op.getValueType();
7157 bool isLittleEndian = Subtarget.isLittleEndian();
7159 if (Subtarget.hasQPX()) {
7160 if (VT.getVectorNumElements() != 4)
7163 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7165 int AlignIdx = PPC::isQVALIGNIShuffleMask(SVOp);
7166 if (AlignIdx != -1) {
7167 return DAG.getNode(PPCISD::QVALIGNI, dl, VT, V1, V2,
7168 DAG.getConstant(AlignIdx, dl, MVT::i32));
7169 } else if (SVOp->isSplat()) {
7170 int SplatIdx = SVOp->getSplatIndex();
7171 if (SplatIdx >= 4) {
7176 // FIXME: If SplatIdx == 0 and the input came from a load, then there is
7179 return DAG.getNode(PPCISD::QVESPLATI, dl, VT, V1,
7180 DAG.getConstant(SplatIdx, dl, MVT::i32));
7183 // Lower this into a qvgpci/qvfperm pair.
7185 // Compute the qvgpci literal
7187 for (unsigned i = 0; i < 4; ++i) {
7188 int m = SVOp->getMaskElt(i);
7189 unsigned mm = m >= 0 ? (unsigned) m : i;
7190 idx |= mm << (3-i)*3;
7193 SDValue V3 = DAG.getNode(PPCISD::QVGPCI, dl, MVT::v4f64,
7194 DAG.getConstant(idx, dl, MVT::i32));
7195 return DAG.getNode(PPCISD::QVFPERM, dl, VT, V1, V2, V3);
7198 // Cases that are handled by instructions that take permute immediates
7199 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
7200 // selected by the instruction selector.
7201 if (V2.getOpcode() == ISD::UNDEF) {
7202 if (PPC::isSplatShuffleMask(SVOp, 1) ||
7203 PPC::isSplatShuffleMask(SVOp, 2) ||
7204 PPC::isSplatShuffleMask(SVOp, 4) ||
7205 PPC::isVPKUWUMShuffleMask(SVOp, 1, DAG) ||
7206 PPC::isVPKUHUMShuffleMask(SVOp, 1, DAG) ||
7207 PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) != -1 ||
7208 PPC::isVMRGLShuffleMask(SVOp, 1, 1, DAG) ||
7209 PPC::isVMRGLShuffleMask(SVOp, 2, 1, DAG) ||
7210 PPC::isVMRGLShuffleMask(SVOp, 4, 1, DAG) ||
7211 PPC::isVMRGHShuffleMask(SVOp, 1, 1, DAG) ||
7212 PPC::isVMRGHShuffleMask(SVOp, 2, 1, DAG) ||
7213 PPC::isVMRGHShuffleMask(SVOp, 4, 1, DAG) ||
7214 (Subtarget.hasP8Altivec() && (
7215 PPC::isVPKUDUMShuffleMask(SVOp, 1, DAG) ||
7216 PPC::isVMRGEOShuffleMask(SVOp, true, 1, DAG) ||
7217 PPC::isVMRGEOShuffleMask(SVOp, false, 1, DAG)))) {
7222 // Altivec has a variety of "shuffle immediates" that take two vector inputs
7223 // and produce a fixed permutation. If any of these match, do not lower to
7225 unsigned int ShuffleKind = isLittleEndian ? 2 : 0;
7226 if (PPC::isVPKUWUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7227 PPC::isVPKUHUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7228 PPC::isVSLDOIShuffleMask(SVOp, ShuffleKind, DAG) != -1 ||
7229 PPC::isVMRGLShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7230 PPC::isVMRGLShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7231 PPC::isVMRGLShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7232 PPC::isVMRGHShuffleMask(SVOp, 1, ShuffleKind, DAG) ||
7233 PPC::isVMRGHShuffleMask(SVOp, 2, ShuffleKind, DAG) ||
7234 PPC::isVMRGHShuffleMask(SVOp, 4, ShuffleKind, DAG) ||
7235 (Subtarget.hasP8Altivec() && (
7236 PPC::isVPKUDUMShuffleMask(SVOp, ShuffleKind, DAG) ||
7237 PPC::isVMRGEOShuffleMask(SVOp, true, ShuffleKind, DAG) ||
7238 PPC::isVMRGEOShuffleMask(SVOp, false, ShuffleKind, DAG))))
7241 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
7242 // perfect shuffle table to emit an optimal matching sequence.
7243 ArrayRef<int> PermMask = SVOp->getMask();
7245 unsigned PFIndexes[4];
7246 bool isFourElementShuffle = true;
7247 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
7248 unsigned EltNo = 8; // Start out undef.
7249 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
7250 if (PermMask[i*4+j] < 0)
7251 continue; // Undef, ignore it.
7253 unsigned ByteSource = PermMask[i*4+j];
7254 if ((ByteSource & 3) != j) {
7255 isFourElementShuffle = false;
7260 EltNo = ByteSource/4;
7261 } else if (EltNo != ByteSource/4) {
7262 isFourElementShuffle = false;
7266 PFIndexes[i] = EltNo;
7269 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
7270 // perfect shuffle vector to determine if it is cost effective to do this as
7271 // discrete instructions, or whether we should use a vperm.
7272 // For now, we skip this for little endian until such time as we have a
7273 // little-endian perfect shuffle table.
7274 if (isFourElementShuffle && !isLittleEndian) {
7275 // Compute the index in the perfect shuffle table.
7276 unsigned PFTableIndex =
7277 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
7279 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
7280 unsigned Cost = (PFEntry >> 30);
7282 // Determining when to avoid vperm is tricky. Many things affect the cost
7283 // of vperm, particularly how many times the perm mask needs to be computed.
7284 // For example, if the perm mask can be hoisted out of a loop or is already
7285 // used (perhaps because there are multiple permutes with the same shuffle
7286 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
7287 // the loop requires an extra register.
7289 // As a compromise, we only emit discrete instructions if the shuffle can be
7290 // generated in 3 or fewer operations. When we have loop information
7291 // available, if this block is within a loop, we should avoid using vperm
7292 // for 3-operation perms and use a constant pool load instead.
7294 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
7297 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
7298 // vector that will get spilled to the constant pool.
7299 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
7301 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
7302 // that it is in input element units, not in bytes. Convert now.
7304 // For little endian, the order of the input vectors is reversed, and
7305 // the permutation mask is complemented with respect to 31. This is
7306 // necessary to produce proper semantics with the big-endian-biased vperm
7308 EVT EltVT = V1.getValueType().getVectorElementType();
7309 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
7311 SmallVector<SDValue, 16> ResultMask;
7312 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
7313 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
7315 for (unsigned j = 0; j != BytesPerElement; ++j)
7317 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement + j),
7320 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement + j, dl,
7324 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
7327 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7330 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
7334 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
7335 /// altivec comparison. If it is, return true and fill in Opc/isDot with
7336 /// information about the intrinsic.
7337 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
7338 bool &isDot, const PPCSubtarget &Subtarget) {
7339 unsigned IntrinsicID =
7340 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
7343 switch (IntrinsicID) {
7344 default: return false;
7345 // Comparison predicates.
7346 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
7347 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
7348 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
7349 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
7350 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
7351 case Intrinsic::ppc_altivec_vcmpequd_p:
7352 if (Subtarget.hasP8Altivec()) {
7360 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
7361 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
7362 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
7363 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
7364 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
7365 case Intrinsic::ppc_altivec_vcmpgtsd_p:
7366 if (Subtarget.hasP8Altivec()) {
7374 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
7375 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
7376 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
7377 case Intrinsic::ppc_altivec_vcmpgtud_p:
7378 if (Subtarget.hasP8Altivec()) {
7387 // Normal Comparisons.
7388 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
7389 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
7390 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
7391 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
7392 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
7393 case Intrinsic::ppc_altivec_vcmpequd:
7394 if (Subtarget.hasP8Altivec()) {
7402 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
7403 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
7404 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
7405 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
7406 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
7407 case Intrinsic::ppc_altivec_vcmpgtsd:
7408 if (Subtarget.hasP8Altivec()) {
7416 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
7417 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
7418 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
7419 case Intrinsic::ppc_altivec_vcmpgtud:
7420 if (Subtarget.hasP8Altivec()) {
7432 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
7433 /// lower, do it, otherwise return null.
7434 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
7435 SelectionDAG &DAG) const {
7436 // If this is a lowered altivec predicate compare, CompareOpc is set to the
7437 // opcode number of the comparison.
7441 if (!getAltivecCompareInfo(Op, CompareOpc, isDot, Subtarget))
7442 return SDValue(); // Don't custom lower most intrinsics.
7444 // If this is a non-dot comparison, make the VCMP node and we are done.
7446 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
7447 Op.getOperand(1), Op.getOperand(2),
7448 DAG.getConstant(CompareOpc, dl, MVT::i32));
7449 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
7452 // Create the PPCISD altivec 'dot' comparison node.
7454 Op.getOperand(2), // LHS
7455 Op.getOperand(3), // RHS
7456 DAG.getConstant(CompareOpc, dl, MVT::i32)
7458 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
7459 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
7461 // Now that we have the comparison, emit a copy from the CR to a GPR.
7462 // This is flagged to the above dot comparison.
7463 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
7464 DAG.getRegister(PPC::CR6, MVT::i32),
7465 CompNode.getValue(1));
7467 // Unpack the result based on how the target uses it.
7468 unsigned BitNo; // Bit # of CR6.
7469 bool InvertBit; // Invert result?
7470 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
7471 default: // Can't happen, don't crash on invalid number though.
7472 case 0: // Return the value of the EQ bit of CR6.
7473 BitNo = 0; InvertBit = false;
7475 case 1: // Return the inverted value of the EQ bit of CR6.
7476 BitNo = 0; InvertBit = true;
7478 case 2: // Return the value of the LT bit of CR6.
7479 BitNo = 2; InvertBit = false;
7481 case 3: // Return the inverted value of the LT bit of CR6.
7482 BitNo = 2; InvertBit = true;
7486 // Shift the bit into the low position.
7487 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
7488 DAG.getConstant(8 - (3 - BitNo), dl, MVT::i32));
7490 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
7491 DAG.getConstant(1, dl, MVT::i32));
7493 // If we are supposed to, toggle the bit.
7495 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
7496 DAG.getConstant(1, dl, MVT::i32));
7500 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
7501 SelectionDAG &DAG) const {
7503 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
7504 // instructions), but for smaller types, we need to first extend up to v2i32
7505 // before doing going farther.
7506 if (Op.getValueType() == MVT::v2i64) {
7507 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
7508 if (ExtVT != MVT::v2i32) {
7509 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
7510 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
7511 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
7512 ExtVT.getVectorElementType(), 4)));
7513 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
7514 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
7515 DAG.getValueType(MVT::v2i32));
7524 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
7525 SelectionDAG &DAG) const {
7527 // Create a stack slot that is 16-byte aligned.
7528 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7529 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7530 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7531 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7533 // Store the input value into Value#0 of the stack slot.
7534 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
7535 Op.getOperand(0), FIdx, MachinePointerInfo(),
7538 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
7539 false, false, false, 0);
7542 SDValue PPCTargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op,
7543 SelectionDAG &DAG) const {
7545 SDNode *N = Op.getNode();
7547 assert(N->getOperand(0).getValueType() == MVT::v4i1 &&
7548 "Unknown extract_vector_elt type");
7550 SDValue Value = N->getOperand(0);
7552 // The first part of this is like the store lowering except that we don't
7553 // need to track the chain.
7555 // The values are now known to be -1 (false) or 1 (true). To convert this
7556 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7557 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7558 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7560 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7561 // understand how to form the extending load.
7562 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7563 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7564 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7566 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7568 // Now convert to an integer and store.
7569 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7570 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7573 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7574 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7575 MachinePointerInfo PtrInfo =
7576 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7577 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7578 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7580 SDValue StoreChain = DAG.getEntryNode();
7581 SmallVector<SDValue, 2> Ops;
7582 Ops.push_back(StoreChain);
7583 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7584 Ops.push_back(Value);
7585 Ops.push_back(FIdx);
7587 SmallVector<EVT, 2> ValueVTs;
7588 ValueVTs.push_back(MVT::Other); // chain
7589 SDVTList VTs = DAG.getVTList(ValueVTs);
7591 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7592 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7594 // Extract the value requested.
7595 unsigned Offset = 4*cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
7596 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7597 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7599 SDValue IntVal = DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7600 PtrInfo.getWithOffset(Offset),
7601 false, false, false, 0);
7603 if (!Subtarget.useCRBits())
7606 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, IntVal);
7609 /// Lowering for QPX v4i1 loads
7610 SDValue PPCTargetLowering::LowerVectorLoad(SDValue Op,
7611 SelectionDAG &DAG) const {
7613 LoadSDNode *LN = cast<LoadSDNode>(Op.getNode());
7614 SDValue LoadChain = LN->getChain();
7615 SDValue BasePtr = LN->getBasePtr();
7617 if (Op.getValueType() == MVT::v4f64 ||
7618 Op.getValueType() == MVT::v4f32) {
7619 EVT MemVT = LN->getMemoryVT();
7620 unsigned Alignment = LN->getAlignment();
7622 // If this load is properly aligned, then it is legal.
7623 if (Alignment >= MemVT.getStoreSize())
7626 EVT ScalarVT = Op.getValueType().getScalarType(),
7627 ScalarMemVT = MemVT.getScalarType();
7628 unsigned Stride = ScalarMemVT.getStoreSize();
7630 SmallVector<SDValue, 8> Vals, LoadChains;
7631 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7633 if (ScalarVT != ScalarMemVT)
7635 DAG.getExtLoad(LN->getExtensionType(), dl, ScalarVT, LoadChain,
7637 LN->getPointerInfo().getWithOffset(Idx*Stride),
7638 ScalarMemVT, LN->isVolatile(), LN->isNonTemporal(),
7639 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7643 DAG.getLoad(ScalarVT, dl, LoadChain, BasePtr,
7644 LN->getPointerInfo().getWithOffset(Idx*Stride),
7645 LN->isVolatile(), LN->isNonTemporal(),
7646 LN->isInvariant(), MinAlign(Alignment, Idx*Stride),
7649 if (Idx == 0 && LN->isIndexed()) {
7650 assert(LN->getAddressingMode() == ISD::PRE_INC &&
7651 "Unknown addressing mode on vector load");
7652 Load = DAG.getIndexedLoad(Load, dl, BasePtr, LN->getOffset(),
7653 LN->getAddressingMode());
7656 Vals.push_back(Load);
7657 LoadChains.push_back(Load.getValue(1));
7659 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7660 DAG.getConstant(Stride, dl,
7661 BasePtr.getValueType()));
7664 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7665 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl,
7666 Op.getValueType(), Vals);
7668 if (LN->isIndexed()) {
7669 SDValue RetOps[] = { Value, Vals[0].getValue(1), TF };
7670 return DAG.getMergeValues(RetOps, dl);
7673 SDValue RetOps[] = { Value, TF };
7674 return DAG.getMergeValues(RetOps, dl);
7677 assert(Op.getValueType() == MVT::v4i1 && "Unknown load to lower");
7678 assert(LN->isUnindexed() && "Indexed v4i1 loads are not supported");
7680 // To lower v4i1 from a byte array, we load the byte elements of the
7681 // vector and then reuse the BUILD_VECTOR logic.
7683 SmallVector<SDValue, 4> VectElmts, VectElmtChains;
7684 for (unsigned i = 0; i < 4; ++i) {
7685 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7686 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7688 VectElmts.push_back(DAG.getExtLoad(ISD::EXTLOAD,
7689 dl, MVT::i32, LoadChain, Idx,
7690 LN->getPointerInfo().getWithOffset(i),
7691 MVT::i8 /* memory type */,
7692 LN->isVolatile(), LN->isNonTemporal(),
7694 1 /* alignment */, LN->getAAInfo()));
7695 VectElmtChains.push_back(VectElmts[i].getValue(1));
7698 LoadChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, VectElmtChains);
7699 SDValue Value = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i1, VectElmts);
7701 SDValue RVals[] = { Value, LoadChain };
7702 return DAG.getMergeValues(RVals, dl);
7705 /// Lowering for QPX v4i1 stores
7706 SDValue PPCTargetLowering::LowerVectorStore(SDValue Op,
7707 SelectionDAG &DAG) const {
7709 StoreSDNode *SN = cast<StoreSDNode>(Op.getNode());
7710 SDValue StoreChain = SN->getChain();
7711 SDValue BasePtr = SN->getBasePtr();
7712 SDValue Value = SN->getValue();
7714 if (Value.getValueType() == MVT::v4f64 ||
7715 Value.getValueType() == MVT::v4f32) {
7716 EVT MemVT = SN->getMemoryVT();
7717 unsigned Alignment = SN->getAlignment();
7719 // If this store is properly aligned, then it is legal.
7720 if (Alignment >= MemVT.getStoreSize())
7723 EVT ScalarVT = Value.getValueType().getScalarType(),
7724 ScalarMemVT = MemVT.getScalarType();
7725 unsigned Stride = ScalarMemVT.getStoreSize();
7727 SmallVector<SDValue, 8> Stores;
7728 for (unsigned Idx = 0; Idx < 4; ++Idx) {
7729 SDValue Ex = DAG.getNode(
7730 ISD::EXTRACT_VECTOR_ELT, dl, ScalarVT, Value,
7731 DAG.getConstant(Idx, dl, getVectorIdxTy(DAG.getDataLayout())));
7733 if (ScalarVT != ScalarMemVT)
7735 DAG.getTruncStore(StoreChain, dl, Ex, BasePtr,
7736 SN->getPointerInfo().getWithOffset(Idx*Stride),
7737 ScalarMemVT, SN->isVolatile(), SN->isNonTemporal(),
7738 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7741 DAG.getStore(StoreChain, dl, Ex, BasePtr,
7742 SN->getPointerInfo().getWithOffset(Idx*Stride),
7743 SN->isVolatile(), SN->isNonTemporal(),
7744 MinAlign(Alignment, Idx*Stride), SN->getAAInfo());
7746 if (Idx == 0 && SN->isIndexed()) {
7747 assert(SN->getAddressingMode() == ISD::PRE_INC &&
7748 "Unknown addressing mode on vector store");
7749 Store = DAG.getIndexedStore(Store, dl, BasePtr, SN->getOffset(),
7750 SN->getAddressingMode());
7753 BasePtr = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr,
7754 DAG.getConstant(Stride, dl,
7755 BasePtr.getValueType()));
7756 Stores.push_back(Store);
7759 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7761 if (SN->isIndexed()) {
7762 SDValue RetOps[] = { TF, Stores[0].getValue(1) };
7763 return DAG.getMergeValues(RetOps, dl);
7769 assert(SN->isUnindexed() && "Indexed v4i1 stores are not supported");
7770 assert(Value.getValueType() == MVT::v4i1 && "Unknown store to lower");
7772 // The values are now known to be -1 (false) or 1 (true). To convert this
7773 // into 0 (false) and 1 (true), add 1 and then divide by 2 (multiply by 0.5).
7774 // This can be done with an fma and the 0.5 constant: (V+1.0)*0.5 = 0.5*V+0.5
7775 Value = DAG.getNode(PPCISD::QBFLT, dl, MVT::v4f64, Value);
7777 // FIXME: We can make this an f32 vector, but the BUILD_VECTOR code needs to
7778 // understand how to form the extending load.
7779 SDValue FPHalfs = DAG.getConstantFP(0.5, dl, MVT::f64);
7780 FPHalfs = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f64,
7781 FPHalfs, FPHalfs, FPHalfs, FPHalfs);
7783 Value = DAG.getNode(ISD::FMA, dl, MVT::v4f64, Value, FPHalfs, FPHalfs);
7785 // Now convert to an integer and store.
7786 Value = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f64,
7787 DAG.getConstant(Intrinsic::ppc_qpx_qvfctiwu, dl, MVT::i32),
7790 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
7791 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
7792 MachinePointerInfo PtrInfo =
7793 MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FrameIdx);
7794 EVT PtrVT = getPointerTy(DAG.getDataLayout());
7795 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
7797 SmallVector<SDValue, 2> Ops;
7798 Ops.push_back(StoreChain);
7799 Ops.push_back(DAG.getConstant(Intrinsic::ppc_qpx_qvstfiw, dl, MVT::i32));
7800 Ops.push_back(Value);
7801 Ops.push_back(FIdx);
7803 SmallVector<EVT, 2> ValueVTs;
7804 ValueVTs.push_back(MVT::Other); // chain
7805 SDVTList VTs = DAG.getVTList(ValueVTs);
7807 StoreChain = DAG.getMemIntrinsicNode(ISD::INTRINSIC_VOID,
7808 dl, VTs, Ops, MVT::v4i32, PtrInfo);
7810 // Move data into the byte array.
7811 SmallVector<SDValue, 4> Loads, LoadChains;
7812 for (unsigned i = 0; i < 4; ++i) {
7813 unsigned Offset = 4*i;
7814 SDValue Idx = DAG.getConstant(Offset, dl, FIdx.getValueType());
7815 Idx = DAG.getNode(ISD::ADD, dl, FIdx.getValueType(), FIdx, Idx);
7817 Loads.push_back(DAG.getLoad(MVT::i32, dl, StoreChain, Idx,
7818 PtrInfo.getWithOffset(Offset),
7819 false, false, false, 0));
7820 LoadChains.push_back(Loads[i].getValue(1));
7823 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, LoadChains);
7825 SmallVector<SDValue, 4> Stores;
7826 for (unsigned i = 0; i < 4; ++i) {
7827 SDValue Idx = DAG.getConstant(i, dl, BasePtr.getValueType());
7828 Idx = DAG.getNode(ISD::ADD, dl, BasePtr.getValueType(), BasePtr, Idx);
7830 Stores.push_back(DAG.getTruncStore(StoreChain, dl, Loads[i], Idx,
7831 SN->getPointerInfo().getWithOffset(i),
7832 MVT::i8 /* memory type */,
7833 SN->isNonTemporal(), SN->isVolatile(),
7834 1 /* alignment */, SN->getAAInfo()));
7837 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Stores);
7842 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
7844 if (Op.getValueType() == MVT::v4i32) {
7845 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7847 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
7848 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
7850 SDValue RHSSwap = // = vrlw RHS, 16
7851 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
7853 // Shrinkify inputs to v8i16.
7854 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
7855 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
7856 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
7858 // Low parts multiplied together, generating 32-bit results (we ignore the
7860 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
7861 LHS, RHS, DAG, dl, MVT::v4i32);
7863 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
7864 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
7865 // Shift the high parts up 16 bits.
7866 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
7868 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
7869 } else if (Op.getValueType() == MVT::v8i16) {
7870 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7872 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
7874 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
7875 LHS, RHS, Zero, DAG, dl);
7876 } else if (Op.getValueType() == MVT::v16i8) {
7877 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
7878 bool isLittleEndian = Subtarget.isLittleEndian();
7880 // Multiply the even 8-bit parts, producing 16-bit sums.
7881 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
7882 LHS, RHS, DAG, dl, MVT::v8i16);
7883 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
7885 // Multiply the odd 8-bit parts, producing 16-bit sums.
7886 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
7887 LHS, RHS, DAG, dl, MVT::v8i16);
7888 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
7890 // Merge the results together. Because vmuleub and vmuloub are
7891 // instructions with a big-endian bias, we must reverse the
7892 // element numbering and reverse the meaning of "odd" and "even"
7893 // when generating little endian code.
7895 for (unsigned i = 0; i != 8; ++i) {
7896 if (isLittleEndian) {
7898 Ops[i*2+1] = 2*i+16;
7901 Ops[i*2+1] = 2*i+1+16;
7905 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
7907 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
7909 llvm_unreachable("Unknown mul to lower!");
7913 /// LowerOperation - Provide custom lowering hooks for some operations.
7915 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
7916 switch (Op.getOpcode()) {
7917 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
7918 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
7919 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
7920 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
7921 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
7922 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
7923 case ISD::SETCC: return LowerSETCC(Op, DAG);
7924 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
7925 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
7927 return LowerVASTART(Op, DAG, Subtarget);
7930 return LowerVAARG(Op, DAG, Subtarget);
7933 return LowerVACOPY(Op, DAG, Subtarget);
7935 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
7936 case ISD::DYNAMIC_STACKALLOC:
7937 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
7939 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
7940 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
7942 case ISD::LOAD: return LowerLOAD(Op, DAG);
7943 case ISD::STORE: return LowerSTORE(Op, DAG);
7944 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
7945 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
7946 case ISD::FP_TO_UINT:
7947 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
7949 case ISD::UINT_TO_FP:
7950 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
7951 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
7953 // Lower 64-bit shifts.
7954 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
7955 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
7956 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
7958 // Vector-related lowering.
7959 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
7960 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
7961 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
7962 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
7963 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
7964 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG);
7965 case ISD::MUL: return LowerMUL(Op, DAG);
7967 // For counter-based loop handling.
7968 case ISD::INTRINSIC_W_CHAIN: return SDValue();
7970 // Frame & Return address.
7971 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
7972 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
7976 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
7977 SmallVectorImpl<SDValue>&Results,
7978 SelectionDAG &DAG) const {
7980 switch (N->getOpcode()) {
7982 llvm_unreachable("Do not know how to custom type legalize this operation!");
7983 case ISD::READCYCLECOUNTER: {
7984 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other);
7985 SDValue RTB = DAG.getNode(PPCISD::READ_TIME_BASE, dl, VTs, N->getOperand(0));
7987 Results.push_back(RTB);
7988 Results.push_back(RTB.getValue(1));
7989 Results.push_back(RTB.getValue(2));
7992 case ISD::INTRINSIC_W_CHAIN: {
7993 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
7994 Intrinsic::ppc_is_decremented_ctr_nonzero)
7997 assert(N->getValueType(0) == MVT::i1 &&
7998 "Unexpected result type for CTR decrement intrinsic");
7999 EVT SVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(),
8000 N->getValueType(0));
8001 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
8002 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
8005 Results.push_back(NewInt);
8006 Results.push_back(NewInt.getValue(1));
8010 if (!Subtarget.isSVR4ABI() || Subtarget.isPPC64())
8013 EVT VT = N->getValueType(0);
8015 if (VT == MVT::i64) {
8016 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
8018 Results.push_back(NewNode);
8019 Results.push_back(NewNode.getValue(1));
8023 case ISD::FP_ROUND_INREG: {
8024 assert(N->getValueType(0) == MVT::ppcf128);
8025 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
8026 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8027 MVT::f64, N->getOperand(0),
8028 DAG.getIntPtrConstant(0, dl));
8029 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
8030 MVT::f64, N->getOperand(0),
8031 DAG.getIntPtrConstant(1, dl));
8033 // Add the two halves of the long double in round-to-zero mode.
8034 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
8036 // We know the low half is about to be thrown away, so just use something
8038 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
8042 case ISD::FP_TO_SINT:
8043 case ISD::FP_TO_UINT:
8044 // LowerFP_TO_INT() can only handle f32 and f64.
8045 if (N->getOperand(0).getValueType() == MVT::ppcf128)
8047 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
8053 //===----------------------------------------------------------------------===//
8054 // Other Lowering Code
8055 //===----------------------------------------------------------------------===//
8057 static Instruction* callIntrinsic(IRBuilder<> &Builder, Intrinsic::ID Id) {
8058 Module *M = Builder.GetInsertBlock()->getParent()->getParent();
8059 Function *Func = Intrinsic::getDeclaration(M, Id);
8060 return Builder.CreateCall(Func, {});
8063 // The mappings for emitLeading/TrailingFence is taken from
8064 // http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
8065 Instruction* PPCTargetLowering::emitLeadingFence(IRBuilder<> &Builder,
8066 AtomicOrdering Ord, bool IsStore,
8067 bool IsLoad) const {
8068 if (Ord == SequentiallyConsistent)
8069 return callIntrinsic(Builder, Intrinsic::ppc_sync);
8070 if (isAtLeastRelease(Ord))
8071 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8075 Instruction* PPCTargetLowering::emitTrailingFence(IRBuilder<> &Builder,
8076 AtomicOrdering Ord, bool IsStore,
8077 bool IsLoad) const {
8078 if (IsLoad && isAtLeastAcquire(Ord))
8079 return callIntrinsic(Builder, Intrinsic::ppc_lwsync);
8080 // FIXME: this is too conservative, a dependent branch + isync is enough.
8081 // See http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html and
8082 // http://www.rdrop.com/users/paulmck/scalability/paper/N2745r.2011.03.04a.html
8083 // and http://www.cl.cam.ac.uk/~pes20/cppppc/ for justification.
8088 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
8089 unsigned AtomicSize,
8090 unsigned BinOpcode) const {
8091 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8092 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8094 auto LoadMnemonic = PPC::LDARX;
8095 auto StoreMnemonic = PPC::STDCX;
8096 switch (AtomicSize) {
8098 llvm_unreachable("Unexpected size of atomic entity");
8100 LoadMnemonic = PPC::LBARX;
8101 StoreMnemonic = PPC::STBCX;
8102 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8105 LoadMnemonic = PPC::LHARX;
8106 StoreMnemonic = PPC::STHCX;
8107 assert(Subtarget.hasPartwordAtomics() && "Call this only with size >=4");
8110 LoadMnemonic = PPC::LWARX;
8111 StoreMnemonic = PPC::STWCX;
8114 LoadMnemonic = PPC::LDARX;
8115 StoreMnemonic = PPC::STDCX;
8119 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8120 MachineFunction *F = BB->getParent();
8121 MachineFunction::iterator It = BB;
8124 unsigned dest = MI->getOperand(0).getReg();
8125 unsigned ptrA = MI->getOperand(1).getReg();
8126 unsigned ptrB = MI->getOperand(2).getReg();
8127 unsigned incr = MI->getOperand(3).getReg();
8128 DebugLoc dl = MI->getDebugLoc();
8130 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8131 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8132 F->insert(It, loopMBB);
8133 F->insert(It, exitMBB);
8134 exitMBB->splice(exitMBB->begin(), BB,
8135 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8136 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8138 MachineRegisterInfo &RegInfo = F->getRegInfo();
8139 unsigned TmpReg = (!BinOpcode) ? incr :
8140 RegInfo.createVirtualRegister( AtomicSize == 8 ? &PPC::G8RCRegClass
8141 : &PPC::GPRCRegClass);
8145 // fallthrough --> loopMBB
8146 BB->addSuccessor(loopMBB);
8149 // l[wd]arx dest, ptr
8150 // add r0, dest, incr
8151 // st[wd]cx. r0, ptr
8153 // fallthrough --> exitMBB
8155 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8156 .addReg(ptrA).addReg(ptrB);
8158 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
8159 BuildMI(BB, dl, TII->get(StoreMnemonic))
8160 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
8161 BuildMI(BB, dl, TII->get(PPC::BCC))
8162 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8163 BB->addSuccessor(loopMBB);
8164 BB->addSuccessor(exitMBB);
8173 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
8174 MachineBasicBlock *BB,
8175 bool is8bit, // operation
8176 unsigned BinOpcode) const {
8177 // If we support part-word atomic mnemonics, just use them
8178 if (Subtarget.hasPartwordAtomics())
8179 return EmitAtomicBinary(MI, BB, is8bit ? 1 : 2, BinOpcode);
8181 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
8182 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8183 // In 64 bit mode we have to use 64 bits for addresses, even though the
8184 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
8185 // registers without caring whether they're 32 or 64, but here we're
8186 // doing actual arithmetic on the addresses.
8187 bool is64bit = Subtarget.isPPC64();
8188 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8190 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8191 MachineFunction *F = BB->getParent();
8192 MachineFunction::iterator It = BB;
8195 unsigned dest = MI->getOperand(0).getReg();
8196 unsigned ptrA = MI->getOperand(1).getReg();
8197 unsigned ptrB = MI->getOperand(2).getReg();
8198 unsigned incr = MI->getOperand(3).getReg();
8199 DebugLoc dl = MI->getDebugLoc();
8201 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
8202 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8203 F->insert(It, loopMBB);
8204 F->insert(It, exitMBB);
8205 exitMBB->splice(exitMBB->begin(), BB,
8206 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8207 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8209 MachineRegisterInfo &RegInfo = F->getRegInfo();
8210 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8211 : &PPC::GPRCRegClass;
8212 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8213 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8214 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8215 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
8216 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8217 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8218 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8219 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8220 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
8221 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8222 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8224 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
8228 // fallthrough --> loopMBB
8229 BB->addSuccessor(loopMBB);
8231 // The 4-byte load must be aligned, while a char or short may be
8232 // anywhere in the word. Hence all this nasty bookkeeping code.
8233 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8234 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8235 // xori shift, shift1, 24 [16]
8236 // rlwinm ptr, ptr1, 0, 0, 29
8237 // slw incr2, incr, shift
8238 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8239 // slw mask, mask2, shift
8241 // lwarx tmpDest, ptr
8242 // add tmp, tmpDest, incr2
8243 // andc tmp2, tmpDest, mask
8244 // and tmp3, tmp, mask
8245 // or tmp4, tmp3, tmp2
8248 // fallthrough --> exitMBB
8249 // srw dest, tmpDest, shift
8250 if (ptrA != ZeroReg) {
8251 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8252 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8253 .addReg(ptrA).addReg(ptrB);
8257 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8258 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8259 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8260 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8262 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8263 .addReg(Ptr1Reg).addImm(0).addImm(61);
8265 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8266 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8267 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
8268 .addReg(incr).addReg(ShiftReg);
8270 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
8272 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
8273 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
8275 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
8276 .addReg(Mask2Reg).addReg(ShiftReg);
8279 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
8280 .addReg(ZeroReg).addReg(PtrReg);
8282 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
8283 .addReg(Incr2Reg).addReg(TmpDestReg);
8284 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
8285 .addReg(TmpDestReg).addReg(MaskReg);
8286 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
8287 .addReg(TmpReg).addReg(MaskReg);
8288 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
8289 .addReg(Tmp3Reg).addReg(Tmp2Reg);
8290 BuildMI(BB, dl, TII->get(PPC::STWCX))
8291 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
8292 BuildMI(BB, dl, TII->get(PPC::BCC))
8293 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
8294 BB->addSuccessor(loopMBB);
8295 BB->addSuccessor(exitMBB);
8300 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
8305 llvm::MachineBasicBlock*
8306 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
8307 MachineBasicBlock *MBB) const {
8308 DebugLoc DL = MI->getDebugLoc();
8309 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8311 MachineFunction *MF = MBB->getParent();
8312 MachineRegisterInfo &MRI = MF->getRegInfo();
8314 const BasicBlock *BB = MBB->getBasicBlock();
8315 MachineFunction::iterator I = MBB;
8319 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8320 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8322 unsigned DstReg = MI->getOperand(0).getReg();
8323 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
8324 assert(RC->hasType(MVT::i32) && "Invalid destination!");
8325 unsigned mainDstReg = MRI.createVirtualRegister(RC);
8326 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
8328 MVT PVT = getPointerTy(MF->getDataLayout());
8329 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8330 "Invalid Pointer Size!");
8331 // For v = setjmp(buf), we generate
8334 // SjLjSetup mainMBB
8340 // buf[LabelOffset] = LR
8344 // v = phi(main, restore)
8347 MachineBasicBlock *thisMBB = MBB;
8348 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
8349 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
8350 MF->insert(I, mainMBB);
8351 MF->insert(I, sinkMBB);
8353 MachineInstrBuilder MIB;
8355 // Transfer the remainder of BB and its successor edges to sinkMBB.
8356 sinkMBB->splice(sinkMBB->begin(), MBB,
8357 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
8358 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
8360 // Note that the structure of the jmp_buf used here is not compatible
8361 // with that used by libc, and is not designed to be. Specifically, it
8362 // stores only those 'reserved' registers that LLVM does not otherwise
8363 // understand how to spill. Also, by convention, by the time this
8364 // intrinsic is called, Clang has already stored the frame address in the
8365 // first slot of the buffer and stack address in the third. Following the
8366 // X86 target code, we'll store the jump address in the second slot. We also
8367 // need to save the TOC pointer (R2) to handle jumps between shared
8368 // libraries, and that will be stored in the fourth slot. The thread
8369 // identifier (R13) is not affected.
8372 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8373 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8374 const int64_t BPOffset = 4 * PVT.getStoreSize();
8376 // Prepare IP either in reg.
8377 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
8378 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
8379 unsigned BufReg = MI->getOperand(1).getReg();
8381 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
8382 setUsesTOCBasePtr(*MBB->getParent());
8383 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
8387 MIB.setMemRefs(MMOBegin, MMOEnd);
8390 // Naked functions never have a base pointer, and so we use r1. For all
8391 // other functions, this decision must be delayed until during PEI.
8393 if (MF->getFunction()->hasFnAttribute(Attribute::Naked))
8394 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
8396 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
8398 MIB = BuildMI(*thisMBB, MI, DL,
8399 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
8403 MIB.setMemRefs(MMOBegin, MMOEnd);
8406 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
8407 const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
8408 MIB.addRegMask(TRI->getNoPreservedMask());
8410 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
8412 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
8414 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
8416 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
8417 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
8422 BuildMI(mainMBB, DL,
8423 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
8426 if (Subtarget.isPPC64()) {
8427 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
8429 .addImm(LabelOffset)
8432 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
8434 .addImm(LabelOffset)
8438 MIB.setMemRefs(MMOBegin, MMOEnd);
8440 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
8441 mainMBB->addSuccessor(sinkMBB);
8444 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
8445 TII->get(PPC::PHI), DstReg)
8446 .addReg(mainDstReg).addMBB(mainMBB)
8447 .addReg(restoreDstReg).addMBB(thisMBB);
8449 MI->eraseFromParent();
8454 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
8455 MachineBasicBlock *MBB) const {
8456 DebugLoc DL = MI->getDebugLoc();
8457 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8459 MachineFunction *MF = MBB->getParent();
8460 MachineRegisterInfo &MRI = MF->getRegInfo();
8463 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
8464 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
8466 MVT PVT = getPointerTy(MF->getDataLayout());
8467 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
8468 "Invalid Pointer Size!");
8470 const TargetRegisterClass *RC =
8471 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
8472 unsigned Tmp = MRI.createVirtualRegister(RC);
8473 // Since FP is only updated here but NOT referenced, it's treated as GPR.
8474 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
8475 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
8479 : (Subtarget.isSVR4ABI() &&
8480 MF->getTarget().getRelocationModel() == Reloc::PIC_
8484 MachineInstrBuilder MIB;
8486 const int64_t LabelOffset = 1 * PVT.getStoreSize();
8487 const int64_t SPOffset = 2 * PVT.getStoreSize();
8488 const int64_t TOCOffset = 3 * PVT.getStoreSize();
8489 const int64_t BPOffset = 4 * PVT.getStoreSize();
8491 unsigned BufReg = MI->getOperand(0).getReg();
8493 // Reload FP (the jumped-to function may not have had a
8494 // frame pointer, and if so, then its r31 will be restored
8496 if (PVT == MVT::i64) {
8497 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
8501 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
8505 MIB.setMemRefs(MMOBegin, MMOEnd);
8508 if (PVT == MVT::i64) {
8509 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
8510 .addImm(LabelOffset)
8513 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
8514 .addImm(LabelOffset)
8517 MIB.setMemRefs(MMOBegin, MMOEnd);
8520 if (PVT == MVT::i64) {
8521 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
8525 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
8529 MIB.setMemRefs(MMOBegin, MMOEnd);
8532 if (PVT == MVT::i64) {
8533 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
8537 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
8541 MIB.setMemRefs(MMOBegin, MMOEnd);
8544 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
8545 setUsesTOCBasePtr(*MBB->getParent());
8546 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
8550 MIB.setMemRefs(MMOBegin, MMOEnd);
8554 BuildMI(*MBB, MI, DL,
8555 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
8556 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
8558 MI->eraseFromParent();
8563 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
8564 MachineBasicBlock *BB) const {
8565 if (MI->getOpcode() == TargetOpcode::STACKMAP ||
8566 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8567 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI() &&
8568 MI->getOpcode() == TargetOpcode::PATCHPOINT) {
8569 // Call lowering should have added an r2 operand to indicate a dependence
8570 // on the TOC base pointer value. It can't however, because there is no
8571 // way to mark the dependence as implicit there, and so the stackmap code
8572 // will confuse it with a regular operand. Instead, add the dependence
8574 setUsesTOCBasePtr(*BB->getParent());
8575 MI->addOperand(MachineOperand::CreateReg(PPC::X2, false, true));
8578 return emitPatchPoint(MI, BB);
8581 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
8582 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
8583 return emitEHSjLjSetJmp(MI, BB);
8584 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
8585 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
8586 return emitEHSjLjLongJmp(MI, BB);
8589 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
8591 // To "insert" these instructions we actually have to insert their
8592 // control-flow patterns.
8593 const BasicBlock *LLVM_BB = BB->getBasicBlock();
8594 MachineFunction::iterator It = BB;
8597 MachineFunction *F = BB->getParent();
8599 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8600 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8601 MI->getOpcode() == PPC::SELECT_I4 ||
8602 MI->getOpcode() == PPC::SELECT_I8)) {
8603 SmallVector<MachineOperand, 2> Cond;
8604 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8605 MI->getOpcode() == PPC::SELECT_CC_I8)
8606 Cond.push_back(MI->getOperand(4));
8608 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
8609 Cond.push_back(MI->getOperand(1));
8611 DebugLoc dl = MI->getDebugLoc();
8612 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
8613 Cond, MI->getOperand(2).getReg(),
8614 MI->getOperand(3).getReg());
8615 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
8616 MI->getOpcode() == PPC::SELECT_CC_I8 ||
8617 MI->getOpcode() == PPC::SELECT_CC_F4 ||
8618 MI->getOpcode() == PPC::SELECT_CC_F8 ||
8619 MI->getOpcode() == PPC::SELECT_CC_QFRC ||
8620 MI->getOpcode() == PPC::SELECT_CC_QSRC ||
8621 MI->getOpcode() == PPC::SELECT_CC_QBRC ||
8622 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
8623 MI->getOpcode() == PPC::SELECT_CC_VSFRC ||
8624 MI->getOpcode() == PPC::SELECT_CC_VSSRC ||
8625 MI->getOpcode() == PPC::SELECT_CC_VSRC ||
8626 MI->getOpcode() == PPC::SELECT_I4 ||
8627 MI->getOpcode() == PPC::SELECT_I8 ||
8628 MI->getOpcode() == PPC::SELECT_F4 ||
8629 MI->getOpcode() == PPC::SELECT_F8 ||
8630 MI->getOpcode() == PPC::SELECT_QFRC ||
8631 MI->getOpcode() == PPC::SELECT_QSRC ||
8632 MI->getOpcode() == PPC::SELECT_QBRC ||
8633 MI->getOpcode() == PPC::SELECT_VRRC ||
8634 MI->getOpcode() == PPC::SELECT_VSFRC ||
8635 MI->getOpcode() == PPC::SELECT_VSSRC ||
8636 MI->getOpcode() == PPC::SELECT_VSRC) {
8637 // The incoming instruction knows the destination vreg to set, the
8638 // condition code register to branch on, the true/false values to
8639 // select between, and a branch opcode to use.
8644 // cmpTY ccX, r1, r2
8646 // fallthrough --> copy0MBB
8647 MachineBasicBlock *thisMBB = BB;
8648 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
8649 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8650 DebugLoc dl = MI->getDebugLoc();
8651 F->insert(It, copy0MBB);
8652 F->insert(It, sinkMBB);
8654 // Transfer the remainder of BB and its successor edges to sinkMBB.
8655 sinkMBB->splice(sinkMBB->begin(), BB,
8656 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8657 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8659 // Next, add the true and fallthrough blocks as its successors.
8660 BB->addSuccessor(copy0MBB);
8661 BB->addSuccessor(sinkMBB);
8663 if (MI->getOpcode() == PPC::SELECT_I4 ||
8664 MI->getOpcode() == PPC::SELECT_I8 ||
8665 MI->getOpcode() == PPC::SELECT_F4 ||
8666 MI->getOpcode() == PPC::SELECT_F8 ||
8667 MI->getOpcode() == PPC::SELECT_QFRC ||
8668 MI->getOpcode() == PPC::SELECT_QSRC ||
8669 MI->getOpcode() == PPC::SELECT_QBRC ||
8670 MI->getOpcode() == PPC::SELECT_VRRC ||
8671 MI->getOpcode() == PPC::SELECT_VSFRC ||
8672 MI->getOpcode() == PPC::SELECT_VSSRC ||
8673 MI->getOpcode() == PPC::SELECT_VSRC) {
8674 BuildMI(BB, dl, TII->get(PPC::BC))
8675 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8677 unsigned SelectPred = MI->getOperand(4).getImm();
8678 BuildMI(BB, dl, TII->get(PPC::BCC))
8679 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
8683 // %FalseValue = ...
8684 // # fallthrough to sinkMBB
8687 // Update machine-CFG edges
8688 BB->addSuccessor(sinkMBB);
8691 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
8694 BuildMI(*BB, BB->begin(), dl,
8695 TII->get(PPC::PHI), MI->getOperand(0).getReg())
8696 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
8697 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
8698 } else if (MI->getOpcode() == PPC::ReadTB) {
8699 // To read the 64-bit time-base register on a 32-bit target, we read the
8700 // two halves. Should the counter have wrapped while it was being read, we
8701 // need to try again.
8704 // mfspr Rx,TBU # load from TBU
8705 // mfspr Ry,TB # load from TB
8706 // mfspr Rz,TBU # load from TBU
8707 // cmpw crX,Rx,Rz # check if 'old'='new'
8708 // bne readLoop # branch if they're not equal
8711 MachineBasicBlock *readMBB = F->CreateMachineBasicBlock(LLVM_BB);
8712 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
8713 DebugLoc dl = MI->getDebugLoc();
8714 F->insert(It, readMBB);
8715 F->insert(It, sinkMBB);
8717 // Transfer the remainder of BB and its successor edges to sinkMBB.
8718 sinkMBB->splice(sinkMBB->begin(), BB,
8719 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8720 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
8722 BB->addSuccessor(readMBB);
8725 MachineRegisterInfo &RegInfo = F->getRegInfo();
8726 unsigned ReadAgainReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
8727 unsigned LoReg = MI->getOperand(0).getReg();
8728 unsigned HiReg = MI->getOperand(1).getReg();
8730 BuildMI(BB, dl, TII->get(PPC::MFSPR), HiReg).addImm(269);
8731 BuildMI(BB, dl, TII->get(PPC::MFSPR), LoReg).addImm(268);
8732 BuildMI(BB, dl, TII->get(PPC::MFSPR), ReadAgainReg).addImm(269);
8734 unsigned CmpReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
8736 BuildMI(BB, dl, TII->get(PPC::CMPW), CmpReg)
8737 .addReg(HiReg).addReg(ReadAgainReg);
8738 BuildMI(BB, dl, TII->get(PPC::BCC))
8739 .addImm(PPC::PRED_NE).addReg(CmpReg).addMBB(readMBB);
8741 BB->addSuccessor(readMBB);
8742 BB->addSuccessor(sinkMBB);
8744 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
8745 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
8746 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
8747 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
8748 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
8749 BB = EmitAtomicBinary(MI, BB, 4, PPC::ADD4);
8750 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
8751 BB = EmitAtomicBinary(MI, BB, 8, PPC::ADD8);
8753 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
8754 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
8755 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
8756 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
8757 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
8758 BB = EmitAtomicBinary(MI, BB, 4, PPC::AND);
8759 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
8760 BB = EmitAtomicBinary(MI, BB, 8, PPC::AND8);
8762 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
8763 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
8764 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
8765 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
8766 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
8767 BB = EmitAtomicBinary(MI, BB, 4, PPC::OR);
8768 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
8769 BB = EmitAtomicBinary(MI, BB, 8, PPC::OR8);
8771 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
8772 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
8773 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
8774 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
8775 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
8776 BB = EmitAtomicBinary(MI, BB, 4, PPC::XOR);
8777 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
8778 BB = EmitAtomicBinary(MI, BB, 8, PPC::XOR8);
8780 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
8781 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::NAND);
8782 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
8783 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::NAND);
8784 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
8785 BB = EmitAtomicBinary(MI, BB, 4, PPC::NAND);
8786 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
8787 BB = EmitAtomicBinary(MI, BB, 8, PPC::NAND8);
8789 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
8790 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
8791 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
8792 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
8793 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
8794 BB = EmitAtomicBinary(MI, BB, 4, PPC::SUBF);
8795 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
8796 BB = EmitAtomicBinary(MI, BB, 8, PPC::SUBF8);
8798 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
8799 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
8800 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
8801 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
8802 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
8803 BB = EmitAtomicBinary(MI, BB, 4, 0);
8804 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
8805 BB = EmitAtomicBinary(MI, BB, 8, 0);
8807 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
8808 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64 ||
8809 (Subtarget.hasPartwordAtomics() &&
8810 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8) ||
8811 (Subtarget.hasPartwordAtomics() &&
8812 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16)) {
8813 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
8815 auto LoadMnemonic = PPC::LDARX;
8816 auto StoreMnemonic = PPC::STDCX;
8817 switch(MI->getOpcode()) {
8819 llvm_unreachable("Compare and swap of unknown size");
8820 case PPC::ATOMIC_CMP_SWAP_I8:
8821 LoadMnemonic = PPC::LBARX;
8822 StoreMnemonic = PPC::STBCX;
8823 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8825 case PPC::ATOMIC_CMP_SWAP_I16:
8826 LoadMnemonic = PPC::LHARX;
8827 StoreMnemonic = PPC::STHCX;
8828 assert(Subtarget.hasPartwordAtomics() && "No support partword atomics.");
8830 case PPC::ATOMIC_CMP_SWAP_I32:
8831 LoadMnemonic = PPC::LWARX;
8832 StoreMnemonic = PPC::STWCX;
8834 case PPC::ATOMIC_CMP_SWAP_I64:
8835 LoadMnemonic = PPC::LDARX;
8836 StoreMnemonic = PPC::STDCX;
8839 unsigned dest = MI->getOperand(0).getReg();
8840 unsigned ptrA = MI->getOperand(1).getReg();
8841 unsigned ptrB = MI->getOperand(2).getReg();
8842 unsigned oldval = MI->getOperand(3).getReg();
8843 unsigned newval = MI->getOperand(4).getReg();
8844 DebugLoc dl = MI->getDebugLoc();
8846 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8847 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8848 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8849 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8850 F->insert(It, loop1MBB);
8851 F->insert(It, loop2MBB);
8852 F->insert(It, midMBB);
8853 F->insert(It, exitMBB);
8854 exitMBB->splice(exitMBB->begin(), BB,
8855 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8856 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8860 // fallthrough --> loopMBB
8861 BB->addSuccessor(loop1MBB);
8864 // l[bhwd]arx dest, ptr
8865 // cmp[wd] dest, oldval
8868 // st[bhwd]cx. newval, ptr
8872 // st[bhwd]cx. dest, ptr
8875 BuildMI(BB, dl, TII->get(LoadMnemonic), dest)
8876 .addReg(ptrA).addReg(ptrB);
8877 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
8878 .addReg(oldval).addReg(dest);
8879 BuildMI(BB, dl, TII->get(PPC::BCC))
8880 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
8881 BB->addSuccessor(loop2MBB);
8882 BB->addSuccessor(midMBB);
8885 BuildMI(BB, dl, TII->get(StoreMnemonic))
8886 .addReg(newval).addReg(ptrA).addReg(ptrB);
8887 BuildMI(BB, dl, TII->get(PPC::BCC))
8888 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
8889 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
8890 BB->addSuccessor(loop1MBB);
8891 BB->addSuccessor(exitMBB);
8894 BuildMI(BB, dl, TII->get(StoreMnemonic))
8895 .addReg(dest).addReg(ptrA).addReg(ptrB);
8896 BB->addSuccessor(exitMBB);
8901 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
8902 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
8903 // We must use 64-bit registers for addresses when targeting 64-bit,
8904 // since we're actually doing arithmetic on them. Other registers
8906 bool is64bit = Subtarget.isPPC64();
8907 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
8909 unsigned dest = MI->getOperand(0).getReg();
8910 unsigned ptrA = MI->getOperand(1).getReg();
8911 unsigned ptrB = MI->getOperand(2).getReg();
8912 unsigned oldval = MI->getOperand(3).getReg();
8913 unsigned newval = MI->getOperand(4).getReg();
8914 DebugLoc dl = MI->getDebugLoc();
8916 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
8917 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
8918 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
8919 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
8920 F->insert(It, loop1MBB);
8921 F->insert(It, loop2MBB);
8922 F->insert(It, midMBB);
8923 F->insert(It, exitMBB);
8924 exitMBB->splice(exitMBB->begin(), BB,
8925 std::next(MachineBasicBlock::iterator(MI)), BB->end());
8926 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
8928 MachineRegisterInfo &RegInfo = F->getRegInfo();
8929 const TargetRegisterClass *RC = is64bit ? &PPC::G8RCRegClass
8930 : &PPC::GPRCRegClass;
8931 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
8932 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
8933 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
8934 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
8935 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
8936 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
8937 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
8938 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
8939 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
8940 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
8941 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
8942 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
8943 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
8945 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
8946 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
8949 // fallthrough --> loopMBB
8950 BB->addSuccessor(loop1MBB);
8952 // The 4-byte load must be aligned, while a char or short may be
8953 // anywhere in the word. Hence all this nasty bookkeeping code.
8954 // add ptr1, ptrA, ptrB [copy if ptrA==0]
8955 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
8956 // xori shift, shift1, 24 [16]
8957 // rlwinm ptr, ptr1, 0, 0, 29
8958 // slw newval2, newval, shift
8959 // slw oldval2, oldval,shift
8960 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
8961 // slw mask, mask2, shift
8962 // and newval3, newval2, mask
8963 // and oldval3, oldval2, mask
8965 // lwarx tmpDest, ptr
8966 // and tmp, tmpDest, mask
8967 // cmpw tmp, oldval3
8970 // andc tmp2, tmpDest, mask
8971 // or tmp4, tmp2, newval3
8976 // stwcx. tmpDest, ptr
8978 // srw dest, tmpDest, shift
8979 if (ptrA != ZeroReg) {
8980 Ptr1Reg = RegInfo.createVirtualRegister(RC);
8981 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
8982 .addReg(ptrA).addReg(ptrB);
8986 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
8987 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
8988 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
8989 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
8991 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
8992 .addReg(Ptr1Reg).addImm(0).addImm(61);
8994 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
8995 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
8996 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
8997 .addReg(newval).addReg(ShiftReg);
8998 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
8999 .addReg(oldval).addReg(ShiftReg);
9001 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
9003 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
9004 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
9005 .addReg(Mask3Reg).addImm(65535);
9007 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
9008 .addReg(Mask2Reg).addReg(ShiftReg);
9009 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
9010 .addReg(NewVal2Reg).addReg(MaskReg);
9011 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
9012 .addReg(OldVal2Reg).addReg(MaskReg);
9015 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
9016 .addReg(ZeroReg).addReg(PtrReg);
9017 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
9018 .addReg(TmpDestReg).addReg(MaskReg);
9019 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
9020 .addReg(TmpReg).addReg(OldVal3Reg);
9021 BuildMI(BB, dl, TII->get(PPC::BCC))
9022 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
9023 BB->addSuccessor(loop2MBB);
9024 BB->addSuccessor(midMBB);
9027 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
9028 .addReg(TmpDestReg).addReg(MaskReg);
9029 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
9030 .addReg(Tmp2Reg).addReg(NewVal3Reg);
9031 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
9032 .addReg(ZeroReg).addReg(PtrReg);
9033 BuildMI(BB, dl, TII->get(PPC::BCC))
9034 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
9035 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
9036 BB->addSuccessor(loop1MBB);
9037 BB->addSuccessor(exitMBB);
9040 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
9041 .addReg(ZeroReg).addReg(PtrReg);
9042 BB->addSuccessor(exitMBB);
9047 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
9049 } else if (MI->getOpcode() == PPC::FADDrtz) {
9050 // This pseudo performs an FADD with rounding mode temporarily forced
9051 // to round-to-zero. We emit this via custom inserter since the FPSCR
9052 // is not modeled at the SelectionDAG level.
9053 unsigned Dest = MI->getOperand(0).getReg();
9054 unsigned Src1 = MI->getOperand(1).getReg();
9055 unsigned Src2 = MI->getOperand(2).getReg();
9056 DebugLoc dl = MI->getDebugLoc();
9058 MachineRegisterInfo &RegInfo = F->getRegInfo();
9059 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
9061 // Save FPSCR value.
9062 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
9064 // Set rounding mode to round-to-zero.
9065 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
9066 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
9068 // Perform addition.
9069 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
9071 // Restore FPSCR value.
9072 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
9073 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9074 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
9075 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9076 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
9077 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
9078 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
9079 PPC::ANDIo8 : PPC::ANDIo;
9080 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
9081 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
9083 MachineRegisterInfo &RegInfo = F->getRegInfo();
9084 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
9085 &PPC::GPRCRegClass :
9086 &PPC::G8RCRegClass);
9088 DebugLoc dl = MI->getDebugLoc();
9089 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
9090 .addReg(MI->getOperand(1).getReg()).addImm(1);
9091 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
9092 MI->getOperand(0).getReg())
9093 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
9094 } else if (MI->getOpcode() == PPC::TCHECK_RET) {
9095 DebugLoc Dl = MI->getDebugLoc();
9096 MachineRegisterInfo &RegInfo = F->getRegInfo();
9097 unsigned CRReg = RegInfo.createVirtualRegister(&PPC::CRRCRegClass);
9098 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
9101 llvm_unreachable("Unexpected instr type to insert");
9104 MI->eraseFromParent(); // The pseudo instruction is gone now.
9108 //===----------------------------------------------------------------------===//
9109 // Target Optimization Hooks
9110 //===----------------------------------------------------------------------===//
9112 static std::string getRecipOp(const char *Base, EVT VT) {
9113 std::string RecipOp(Base);
9114 if (VT.getScalarType() == MVT::f64)
9120 RecipOp = "vec-" + RecipOp;
9125 SDValue PPCTargetLowering::getRsqrtEstimate(SDValue Operand,
9126 DAGCombinerInfo &DCI,
9127 unsigned &RefinementSteps,
9128 bool &UseOneConstNR) const {
9129 EVT VT = Operand.getValueType();
9130 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
9131 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
9132 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9133 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9134 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9135 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9136 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9137 std::string RecipOp = getRecipOp("sqrt", VT);
9138 if (!Recips.isEnabled(RecipOp))
9141 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9142 UseOneConstNR = true;
9143 return DCI.DAG.getNode(PPCISD::FRSQRTE, SDLoc(Operand), VT, Operand);
9148 SDValue PPCTargetLowering::getRecipEstimate(SDValue Operand,
9149 DAGCombinerInfo &DCI,
9150 unsigned &RefinementSteps) const {
9151 EVT VT = Operand.getValueType();
9152 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
9153 (VT == MVT::f64 && Subtarget.hasFRE()) ||
9154 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
9155 (VT == MVT::v2f64 && Subtarget.hasVSX()) ||
9156 (VT == MVT::v4f32 && Subtarget.hasQPX()) ||
9157 (VT == MVT::v4f64 && Subtarget.hasQPX())) {
9158 TargetRecip Recips = DCI.DAG.getTarget().Options.Reciprocals;
9159 std::string RecipOp = getRecipOp("div", VT);
9160 if (!Recips.isEnabled(RecipOp))
9163 RefinementSteps = Recips.getRefinementSteps(RecipOp);
9164 return DCI.DAG.getNode(PPCISD::FRE, SDLoc(Operand), VT, Operand);
9169 unsigned PPCTargetLowering::combineRepeatedFPDivisors() const {
9170 // Note: This functionality is used only when unsafe-fp-math is enabled, and
9171 // on cores with reciprocal estimates (which are used when unsafe-fp-math is
9172 // enabled for division), this functionality is redundant with the default
9173 // combiner logic (once the division -> reciprocal/multiply transformation
9174 // has taken place). As a result, this matters more for older cores than for
9177 // Combine multiple FDIVs with the same divisor into multiple FMULs by the
9178 // reciprocal if there are two or more FDIVs (for embedded cores with only
9179 // one FP pipeline) for three or more FDIVs (for generic OOO cores).
9180 switch (Subtarget.getDarwinDirective()) {
9185 case PPC::DIR_E500mc:
9186 case PPC::DIR_E5500:
9191 // isConsecutiveLSLoc needs to work even if all adds have not yet been
9192 // collapsed, and so we need to look through chains of them.
9193 static void getBaseWithConstantOffset(SDValue Loc, SDValue &Base,
9194 int64_t& Offset, SelectionDAG &DAG) {
9195 if (DAG.isBaseWithConstantOffset(Loc)) {
9196 Base = Loc.getOperand(0);
9197 Offset += cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue();
9199 // The base might itself be a base plus an offset, and if so, accumulate
9201 getBaseWithConstantOffset(Loc.getOperand(0), Base, Offset, DAG);
9205 static bool isConsecutiveLSLoc(SDValue Loc, EVT VT, LSBaseSDNode *Base,
9206 unsigned Bytes, int Dist,
9207 SelectionDAG &DAG) {
9208 if (VT.getSizeInBits() / 8 != Bytes)
9211 SDValue BaseLoc = Base->getBasePtr();
9212 if (Loc.getOpcode() == ISD::FrameIndex) {
9213 if (BaseLoc.getOpcode() != ISD::FrameIndex)
9215 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
9216 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
9217 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
9218 int FS = MFI->getObjectSize(FI);
9219 int BFS = MFI->getObjectSize(BFI);
9220 if (FS != BFS || FS != (int)Bytes) return false;
9221 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
9224 SDValue Base1 = Loc, Base2 = BaseLoc;
9225 int64_t Offset1 = 0, Offset2 = 0;
9226 getBaseWithConstantOffset(Loc, Base1, Offset1, DAG);
9227 getBaseWithConstantOffset(BaseLoc, Base2, Offset2, DAG);
9228 if (Base1 == Base2 && Offset1 == (Offset2 + Dist*Bytes))
9231 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
9232 const GlobalValue *GV1 = nullptr;
9233 const GlobalValue *GV2 = nullptr;
9236 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
9237 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
9238 if (isGA1 && isGA2 && GV1 == GV2)
9239 return Offset1 == (Offset2 + Dist*Bytes);
9243 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
9244 // not enforce equality of the chain operands.
9245 static bool isConsecutiveLS(SDNode *N, LSBaseSDNode *Base,
9246 unsigned Bytes, int Dist,
9247 SelectionDAG &DAG) {
9248 if (LSBaseSDNode *LS = dyn_cast<LSBaseSDNode>(N)) {
9249 EVT VT = LS->getMemoryVT();
9250 SDValue Loc = LS->getBasePtr();
9251 return isConsecutiveLSLoc(Loc, VT, Base, Bytes, Dist, DAG);
9254 if (N->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
9256 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9257 default: return false;
9258 case Intrinsic::ppc_qpx_qvlfd:
9259 case Intrinsic::ppc_qpx_qvlfda:
9262 case Intrinsic::ppc_qpx_qvlfs:
9263 case Intrinsic::ppc_qpx_qvlfsa:
9266 case Intrinsic::ppc_qpx_qvlfcd:
9267 case Intrinsic::ppc_qpx_qvlfcda:
9270 case Intrinsic::ppc_qpx_qvlfcs:
9271 case Intrinsic::ppc_qpx_qvlfcsa:
9274 case Intrinsic::ppc_qpx_qvlfiwa:
9275 case Intrinsic::ppc_qpx_qvlfiwz:
9276 case Intrinsic::ppc_altivec_lvx:
9277 case Intrinsic::ppc_altivec_lvxl:
9278 case Intrinsic::ppc_vsx_lxvw4x:
9281 case Intrinsic::ppc_vsx_lxvd2x:
9284 case Intrinsic::ppc_altivec_lvebx:
9287 case Intrinsic::ppc_altivec_lvehx:
9290 case Intrinsic::ppc_altivec_lvewx:
9295 return isConsecutiveLSLoc(N->getOperand(2), VT, Base, Bytes, Dist, DAG);
9298 if (N->getOpcode() == ISD::INTRINSIC_VOID) {
9300 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
9301 default: return false;
9302 case Intrinsic::ppc_qpx_qvstfd:
9303 case Intrinsic::ppc_qpx_qvstfda:
9306 case Intrinsic::ppc_qpx_qvstfs:
9307 case Intrinsic::ppc_qpx_qvstfsa:
9310 case Intrinsic::ppc_qpx_qvstfcd:
9311 case Intrinsic::ppc_qpx_qvstfcda:
9314 case Intrinsic::ppc_qpx_qvstfcs:
9315 case Intrinsic::ppc_qpx_qvstfcsa:
9318 case Intrinsic::ppc_qpx_qvstfiw:
9319 case Intrinsic::ppc_qpx_qvstfiwa:
9320 case Intrinsic::ppc_altivec_stvx:
9321 case Intrinsic::ppc_altivec_stvxl:
9322 case Intrinsic::ppc_vsx_stxvw4x:
9325 case Intrinsic::ppc_vsx_stxvd2x:
9328 case Intrinsic::ppc_altivec_stvebx:
9331 case Intrinsic::ppc_altivec_stvehx:
9334 case Intrinsic::ppc_altivec_stvewx:
9339 return isConsecutiveLSLoc(N->getOperand(3), VT, Base, Bytes, Dist, DAG);
9345 // Return true is there is a nearyby consecutive load to the one provided
9346 // (regardless of alignment). We search up and down the chain, looking though
9347 // token factors and other loads (but nothing else). As a result, a true result
9348 // indicates that it is safe to create a new consecutive load adjacent to the
9350 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
9351 SDValue Chain = LD->getChain();
9352 EVT VT = LD->getMemoryVT();
9354 SmallSet<SDNode *, 16> LoadRoots;
9355 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
9356 SmallSet<SDNode *, 16> Visited;
9358 // First, search up the chain, branching to follow all token-factor operands.
9359 // If we find a consecutive load, then we're done, otherwise, record all
9360 // nodes just above the top-level loads and token factors.
9361 while (!Queue.empty()) {
9362 SDNode *ChainNext = Queue.pop_back_val();
9363 if (!Visited.insert(ChainNext).second)
9366 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(ChainNext)) {
9367 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9370 if (!Visited.count(ChainLD->getChain().getNode()))
9371 Queue.push_back(ChainLD->getChain().getNode());
9372 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
9373 for (const SDUse &O : ChainNext->ops())
9374 if (!Visited.count(O.getNode()))
9375 Queue.push_back(O.getNode());
9377 LoadRoots.insert(ChainNext);
9380 // Second, search down the chain, starting from the top-level nodes recorded
9381 // in the first phase. These top-level nodes are the nodes just above all
9382 // loads and token factors. Starting with their uses, recursively look though
9383 // all loads (just the chain uses) and token factors to find a consecutive
9388 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
9389 IE = LoadRoots.end(); I != IE; ++I) {
9390 Queue.push_back(*I);
9392 while (!Queue.empty()) {
9393 SDNode *LoadRoot = Queue.pop_back_val();
9394 if (!Visited.insert(LoadRoot).second)
9397 if (MemSDNode *ChainLD = dyn_cast<MemSDNode>(LoadRoot))
9398 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
9401 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
9402 UE = LoadRoot->use_end(); UI != UE; ++UI)
9403 if (((isa<MemSDNode>(*UI) &&
9404 cast<MemSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
9405 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
9406 Queue.push_back(*UI);
9413 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
9414 DAGCombinerInfo &DCI) const {
9415 SelectionDAG &DAG = DCI.DAG;
9418 assert(Subtarget.useCRBits() && "Expecting to be tracking CR bits");
9419 // If we're tracking CR bits, we need to be careful that we don't have:
9420 // trunc(binary-ops(zext(x), zext(y)))
9422 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
9423 // such that we're unnecessarily moving things into GPRs when it would be
9424 // better to keep them in CR bits.
9426 // Note that trunc here can be an actual i1 trunc, or can be the effective
9427 // truncation that comes from a setcc or select_cc.
9428 if (N->getOpcode() == ISD::TRUNCATE &&
9429 N->getValueType(0) != MVT::i1)
9432 if (N->getOperand(0).getValueType() != MVT::i32 &&
9433 N->getOperand(0).getValueType() != MVT::i64)
9436 if (N->getOpcode() == ISD::SETCC ||
9437 N->getOpcode() == ISD::SELECT_CC) {
9438 // If we're looking at a comparison, then we need to make sure that the
9439 // high bits (all except for the first) don't matter the result.
9441 cast<CondCodeSDNode>(N->getOperand(
9442 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
9443 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
9445 if (ISD::isSignedIntSetCC(CC)) {
9446 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
9447 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
9449 } else if (ISD::isUnsignedIntSetCC(CC)) {
9450 if (!DAG.MaskedValueIsZero(N->getOperand(0),
9451 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
9452 !DAG.MaskedValueIsZero(N->getOperand(1),
9453 APInt::getHighBitsSet(OpBits, OpBits-1)))
9456 // This is neither a signed nor an unsigned comparison, just make sure
9457 // that the high bits are equal.
9458 APInt Op1Zero, Op1One;
9459 APInt Op2Zero, Op2One;
9460 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
9461 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
9463 // We don't really care about what is known about the first bit (if
9464 // anything), so clear it in all masks prior to comparing them.
9465 Op1Zero.clearBit(0); Op1One.clearBit(0);
9466 Op2Zero.clearBit(0); Op2One.clearBit(0);
9468 if (Op1Zero != Op2Zero || Op1One != Op2One)
9473 // We now know that the higher-order bits are irrelevant, we just need to
9474 // make sure that all of the intermediate operations are bit operations, and
9475 // all inputs are extensions.
9476 if (N->getOperand(0).getOpcode() != ISD::AND &&
9477 N->getOperand(0).getOpcode() != ISD::OR &&
9478 N->getOperand(0).getOpcode() != ISD::XOR &&
9479 N->getOperand(0).getOpcode() != ISD::SELECT &&
9480 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
9481 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
9482 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
9483 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
9484 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
9487 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
9488 N->getOperand(1).getOpcode() != ISD::AND &&
9489 N->getOperand(1).getOpcode() != ISD::OR &&
9490 N->getOperand(1).getOpcode() != ISD::XOR &&
9491 N->getOperand(1).getOpcode() != ISD::SELECT &&
9492 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
9493 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
9494 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
9495 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
9496 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
9499 SmallVector<SDValue, 4> Inputs;
9500 SmallVector<SDValue, 8> BinOps, PromOps;
9501 SmallPtrSet<SDNode *, 16> Visited;
9503 for (unsigned i = 0; i < 2; ++i) {
9504 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9505 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9506 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9507 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9508 isa<ConstantSDNode>(N->getOperand(i)))
9509 Inputs.push_back(N->getOperand(i));
9511 BinOps.push_back(N->getOperand(i));
9513 if (N->getOpcode() == ISD::TRUNCATE)
9517 // Visit all inputs, collect all binary operations (and, or, xor and
9518 // select) that are all fed by extensions.
9519 while (!BinOps.empty()) {
9520 SDValue BinOp = BinOps.back();
9523 if (!Visited.insert(BinOp.getNode()).second)
9526 PromOps.push_back(BinOp);
9528 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9529 // The condition of the select is not promoted.
9530 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9532 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9535 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9536 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9537 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
9538 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
9539 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9540 Inputs.push_back(BinOp.getOperand(i));
9541 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9542 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9543 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9544 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9545 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
9546 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9547 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
9548 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
9549 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
9550 BinOps.push_back(BinOp.getOperand(i));
9552 // We have an input that is not an extension or another binary
9553 // operation; we'll abort this transformation.
9559 // Make sure that this is a self-contained cluster of operations (which
9560 // is not quite the same thing as saying that everything has only one
9562 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9563 if (isa<ConstantSDNode>(Inputs[i]))
9566 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9567 UE = Inputs[i].getNode()->use_end();
9570 if (User != N && !Visited.count(User))
9573 // Make sure that we're not going to promote the non-output-value
9574 // operand(s) or SELECT or SELECT_CC.
9575 // FIXME: Although we could sometimes handle this, and it does occur in
9576 // practice that one of the condition inputs to the select is also one of
9577 // the outputs, we currently can't deal with this.
9578 if (User->getOpcode() == ISD::SELECT) {
9579 if (User->getOperand(0) == Inputs[i])
9581 } else if (User->getOpcode() == ISD::SELECT_CC) {
9582 if (User->getOperand(0) == Inputs[i] ||
9583 User->getOperand(1) == Inputs[i])
9589 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9590 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9591 UE = PromOps[i].getNode()->use_end();
9594 if (User != N && !Visited.count(User))
9597 // Make sure that we're not going to promote the non-output-value
9598 // operand(s) or SELECT or SELECT_CC.
9599 // FIXME: Although we could sometimes handle this, and it does occur in
9600 // practice that one of the condition inputs to the select is also one of
9601 // the outputs, we currently can't deal with this.
9602 if (User->getOpcode() == ISD::SELECT) {
9603 if (User->getOperand(0) == PromOps[i])
9605 } else if (User->getOpcode() == ISD::SELECT_CC) {
9606 if (User->getOperand(0) == PromOps[i] ||
9607 User->getOperand(1) == PromOps[i])
9613 // Replace all inputs with the extension operand.
9614 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9615 // Constants may have users outside the cluster of to-be-promoted nodes,
9616 // and so we need to replace those as we do the promotions.
9617 if (isa<ConstantSDNode>(Inputs[i]))
9620 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
9623 // Replace all operations (these are all the same, but have a different
9624 // (i1) return type). DAG.getNode will validate that the types of
9625 // a binary operator match, so go through the list in reverse so that
9626 // we've likely promoted both operands first. Any intermediate truncations or
9627 // extensions disappear.
9628 while (!PromOps.empty()) {
9629 SDValue PromOp = PromOps.back();
9632 if (PromOp.getOpcode() == ISD::TRUNCATE ||
9633 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
9634 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
9635 PromOp.getOpcode() == ISD::ANY_EXTEND) {
9636 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
9637 PromOp.getOperand(0).getValueType() != MVT::i1) {
9638 // The operand is not yet ready (see comment below).
9639 PromOps.insert(PromOps.begin(), PromOp);
9643 SDValue RepValue = PromOp.getOperand(0);
9644 if (isa<ConstantSDNode>(RepValue))
9645 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
9647 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
9652 switch (PromOp.getOpcode()) {
9653 default: C = 0; break;
9654 case ISD::SELECT: C = 1; break;
9655 case ISD::SELECT_CC: C = 2; break;
9658 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9659 PromOp.getOperand(C).getValueType() != MVT::i1) ||
9660 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9661 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
9662 // The to-be-promoted operands of this node have not yet been
9663 // promoted (this should be rare because we're going through the
9664 // list backward, but if one of the operands has several users in
9665 // this cluster of to-be-promoted nodes, it is possible).
9666 PromOps.insert(PromOps.begin(), PromOp);
9670 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9671 PromOp.getNode()->op_end());
9673 // If there are any constant inputs, make sure they're replaced now.
9674 for (unsigned i = 0; i < 2; ++i)
9675 if (isa<ConstantSDNode>(Ops[C+i]))
9676 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
9678 DAG.ReplaceAllUsesOfValueWith(PromOp,
9679 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
9682 // Now we're left with the initial truncation itself.
9683 if (N->getOpcode() == ISD::TRUNCATE)
9684 return N->getOperand(0);
9686 // Otherwise, this is a comparison. The operands to be compared have just
9687 // changed type (to i1), but everything else is the same.
9688 return SDValue(N, 0);
9691 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
9692 DAGCombinerInfo &DCI) const {
9693 SelectionDAG &DAG = DCI.DAG;
9696 // If we're tracking CR bits, we need to be careful that we don't have:
9697 // zext(binary-ops(trunc(x), trunc(y)))
9699 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
9700 // such that we're unnecessarily moving things into CR bits that can more
9701 // efficiently stay in GPRs. Note that if we're not certain that the high
9702 // bits are set as required by the final extension, we still may need to do
9703 // some masking to get the proper behavior.
9705 // This same functionality is important on PPC64 when dealing with
9706 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
9707 // the return values of functions. Because it is so similar, it is handled
9710 if (N->getValueType(0) != MVT::i32 &&
9711 N->getValueType(0) != MVT::i64)
9714 if (!((N->getOperand(0).getValueType() == MVT::i1 && Subtarget.useCRBits()) ||
9715 (N->getOperand(0).getValueType() == MVT::i32 && Subtarget.isPPC64())))
9718 if (N->getOperand(0).getOpcode() != ISD::AND &&
9719 N->getOperand(0).getOpcode() != ISD::OR &&
9720 N->getOperand(0).getOpcode() != ISD::XOR &&
9721 N->getOperand(0).getOpcode() != ISD::SELECT &&
9722 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
9725 SmallVector<SDValue, 4> Inputs;
9726 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
9727 SmallPtrSet<SDNode *, 16> Visited;
9729 // Visit all inputs, collect all binary operations (and, or, xor and
9730 // select) that are all fed by truncations.
9731 while (!BinOps.empty()) {
9732 SDValue BinOp = BinOps.back();
9735 if (!Visited.insert(BinOp.getNode()).second)
9738 PromOps.push_back(BinOp);
9740 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
9741 // The condition of the select is not promoted.
9742 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
9744 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
9747 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
9748 isa<ConstantSDNode>(BinOp.getOperand(i))) {
9749 Inputs.push_back(BinOp.getOperand(i));
9750 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
9751 BinOp.getOperand(i).getOpcode() == ISD::OR ||
9752 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
9753 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
9754 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
9755 BinOps.push_back(BinOp.getOperand(i));
9757 // We have an input that is not a truncation or another binary
9758 // operation; we'll abort this transformation.
9764 // The operands of a select that must be truncated when the select is
9765 // promoted because the operand is actually part of the to-be-promoted set.
9766 DenseMap<SDNode *, EVT> SelectTruncOp[2];
9768 // Make sure that this is a self-contained cluster of operations (which
9769 // is not quite the same thing as saying that everything has only one
9771 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9772 if (isa<ConstantSDNode>(Inputs[i]))
9775 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
9776 UE = Inputs[i].getNode()->use_end();
9779 if (User != N && !Visited.count(User))
9782 // If we're going to promote the non-output-value operand(s) or SELECT or
9783 // SELECT_CC, record them for truncation.
9784 if (User->getOpcode() == ISD::SELECT) {
9785 if (User->getOperand(0) == Inputs[i])
9786 SelectTruncOp[0].insert(std::make_pair(User,
9787 User->getOperand(0).getValueType()));
9788 } else if (User->getOpcode() == ISD::SELECT_CC) {
9789 if (User->getOperand(0) == Inputs[i])
9790 SelectTruncOp[0].insert(std::make_pair(User,
9791 User->getOperand(0).getValueType()));
9792 if (User->getOperand(1) == Inputs[i])
9793 SelectTruncOp[1].insert(std::make_pair(User,
9794 User->getOperand(1).getValueType()));
9799 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
9800 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
9801 UE = PromOps[i].getNode()->use_end();
9804 if (User != N && !Visited.count(User))
9807 // If we're going to promote the non-output-value operand(s) or SELECT or
9808 // SELECT_CC, record them for truncation.
9809 if (User->getOpcode() == ISD::SELECT) {
9810 if (User->getOperand(0) == PromOps[i])
9811 SelectTruncOp[0].insert(std::make_pair(User,
9812 User->getOperand(0).getValueType()));
9813 } else if (User->getOpcode() == ISD::SELECT_CC) {
9814 if (User->getOperand(0) == PromOps[i])
9815 SelectTruncOp[0].insert(std::make_pair(User,
9816 User->getOperand(0).getValueType()));
9817 if (User->getOperand(1) == PromOps[i])
9818 SelectTruncOp[1].insert(std::make_pair(User,
9819 User->getOperand(1).getValueType()));
9824 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
9825 bool ReallyNeedsExt = false;
9826 if (N->getOpcode() != ISD::ANY_EXTEND) {
9827 // If all of the inputs are not already sign/zero extended, then
9828 // we'll still need to do that at the end.
9829 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9830 if (isa<ConstantSDNode>(Inputs[i]))
9834 Inputs[i].getOperand(0).getValueSizeInBits();
9835 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
9837 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
9838 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
9839 APInt::getHighBitsSet(OpBits,
9840 OpBits-PromBits))) ||
9841 (N->getOpcode() == ISD::SIGN_EXTEND &&
9842 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
9843 (OpBits-(PromBits-1)))) {
9844 ReallyNeedsExt = true;
9850 // Replace all inputs, either with the truncation operand, or a
9851 // truncation or extension to the final output type.
9852 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
9853 // Constant inputs need to be replaced with the to-be-promoted nodes that
9854 // use them because they might have users outside of the cluster of
9856 if (isa<ConstantSDNode>(Inputs[i]))
9859 SDValue InSrc = Inputs[i].getOperand(0);
9860 if (Inputs[i].getValueType() == N->getValueType(0))
9861 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
9862 else if (N->getOpcode() == ISD::SIGN_EXTEND)
9863 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9864 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
9865 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9866 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9867 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
9869 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
9870 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
9873 // Replace all operations (these are all the same, but have a different
9874 // (promoted) return type). DAG.getNode will validate that the types of
9875 // a binary operator match, so go through the list in reverse so that
9876 // we've likely promoted both operands first.
9877 while (!PromOps.empty()) {
9878 SDValue PromOp = PromOps.back();
9882 switch (PromOp.getOpcode()) {
9883 default: C = 0; break;
9884 case ISD::SELECT: C = 1; break;
9885 case ISD::SELECT_CC: C = 2; break;
9888 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
9889 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
9890 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
9891 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
9892 // The to-be-promoted operands of this node have not yet been
9893 // promoted (this should be rare because we're going through the
9894 // list backward, but if one of the operands has several users in
9895 // this cluster of to-be-promoted nodes, it is possible).
9896 PromOps.insert(PromOps.begin(), PromOp);
9900 // For SELECT and SELECT_CC nodes, we do a similar check for any
9901 // to-be-promoted comparison inputs.
9902 if (PromOp.getOpcode() == ISD::SELECT ||
9903 PromOp.getOpcode() == ISD::SELECT_CC) {
9904 if ((SelectTruncOp[0].count(PromOp.getNode()) &&
9905 PromOp.getOperand(0).getValueType() != N->getValueType(0)) ||
9906 (SelectTruncOp[1].count(PromOp.getNode()) &&
9907 PromOp.getOperand(1).getValueType() != N->getValueType(0))) {
9908 PromOps.insert(PromOps.begin(), PromOp);
9913 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
9914 PromOp.getNode()->op_end());
9916 // If this node has constant inputs, then they'll need to be promoted here.
9917 for (unsigned i = 0; i < 2; ++i) {
9918 if (!isa<ConstantSDNode>(Ops[C+i]))
9920 if (Ops[C+i].getValueType() == N->getValueType(0))
9923 if (N->getOpcode() == ISD::SIGN_EXTEND)
9924 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9925 else if (N->getOpcode() == ISD::ZERO_EXTEND)
9926 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9928 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
9931 // If we've promoted the comparison inputs of a SELECT or SELECT_CC,
9932 // truncate them again to the original value type.
9933 if (PromOp.getOpcode() == ISD::SELECT ||
9934 PromOp.getOpcode() == ISD::SELECT_CC) {
9935 auto SI0 = SelectTruncOp[0].find(PromOp.getNode());
9936 if (SI0 != SelectTruncOp[0].end())
9937 Ops[0] = DAG.getNode(ISD::TRUNCATE, dl, SI0->second, Ops[0]);
9938 auto SI1 = SelectTruncOp[1].find(PromOp.getNode());
9939 if (SI1 != SelectTruncOp[1].end())
9940 Ops[1] = DAG.getNode(ISD::TRUNCATE, dl, SI1->second, Ops[1]);
9943 DAG.ReplaceAllUsesOfValueWith(PromOp,
9944 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
9947 // Now we're left with the initial extension itself.
9948 if (!ReallyNeedsExt)
9949 return N->getOperand(0);
9951 // To zero extend, just mask off everything except for the first bit (in the
9953 if (N->getOpcode() == ISD::ZERO_EXTEND)
9954 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
9955 DAG.getConstant(APInt::getLowBitsSet(
9956 N->getValueSizeInBits(0), PromBits),
9957 dl, N->getValueType(0)));
9959 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
9960 "Invalid extension type");
9961 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0), DAG.getDataLayout());
9963 DAG.getConstant(N->getValueSizeInBits(0) - PromBits, dl, ShiftAmountTy);
9964 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
9965 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
9966 N->getOperand(0), ShiftCst), ShiftCst);
9969 SDValue PPCTargetLowering::combineFPToIntToFP(SDNode *N,
9970 DAGCombinerInfo &DCI) const {
9971 assert((N->getOpcode() == ISD::SINT_TO_FP ||
9972 N->getOpcode() == ISD::UINT_TO_FP) &&
9973 "Need an int -> FP conversion node here");
9975 if (!Subtarget.has64BitSupport())
9978 SelectionDAG &DAG = DCI.DAG;
9982 // Don't handle ppc_fp128 here or i1 conversions.
9983 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
9985 if (Op.getOperand(0).getValueType() == MVT::i1)
9988 // For i32 intermediate values, unfortunately, the conversion functions
9989 // leave the upper 32 bits of the value are undefined. Within the set of
9990 // scalar instructions, we have no method for zero- or sign-extending the
9991 // value. Thus, we cannot handle i32 intermediate values here.
9992 if (Op.getOperand(0).getValueType() == MVT::i32)
9995 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
9996 "UINT_TO_FP is supported only with FPCVT");
9998 // If we have FCFIDS, then use it when converting to single-precision.
9999 // Otherwise, convert to double-precision and then round.
10000 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10001 ? (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDUS
10003 : (Op.getOpcode() == ISD::UINT_TO_FP ? PPCISD::FCFIDU
10005 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32)
10009 // If we're converting from a float, to an int, and back to a float again,
10010 // then we don't need the store/load pair at all.
10011 if ((Op.getOperand(0).getOpcode() == ISD::FP_TO_UINT &&
10012 Subtarget.hasFPCVT()) ||
10013 (Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT)) {
10014 SDValue Src = Op.getOperand(0).getOperand(0);
10015 if (Src.getValueType() == MVT::f32) {
10016 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
10017 DCI.AddToWorklist(Src.getNode());
10018 } else if (Src.getValueType() != MVT::f64) {
10019 // Make sure that we don't pick up a ppc_fp128 source value.
10024 Op.getOperand(0).getOpcode() == ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
10027 SDValue Tmp = DAG.getNode(FCTOp, dl, MVT::f64, Src);
10028 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Tmp);
10030 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT()) {
10031 FP = DAG.getNode(ISD::FP_ROUND, dl,
10032 MVT::f32, FP, DAG.getIntPtrConstant(0, dl));
10033 DCI.AddToWorklist(FP.getNode());
10042 // expandVSXLoadForLE - Convert VSX loads (which may be intrinsics for
10043 // builtins) into loads with swaps.
10044 SDValue PPCTargetLowering::expandVSXLoadForLE(SDNode *N,
10045 DAGCombinerInfo &DCI) const {
10046 SelectionDAG &DAG = DCI.DAG;
10050 MachineMemOperand *MMO;
10052 switch (N->getOpcode()) {
10054 llvm_unreachable("Unexpected opcode for little endian VSX load");
10056 LoadSDNode *LD = cast<LoadSDNode>(N);
10057 Chain = LD->getChain();
10058 Base = LD->getBasePtr();
10059 MMO = LD->getMemOperand();
10060 // If the MMO suggests this isn't a load of a full vector, leave
10061 // things alone. For a built-in, we have to make the change for
10062 // correctness, so if there is a size problem that will be a bug.
10063 if (MMO->getSize() < 16)
10067 case ISD::INTRINSIC_W_CHAIN: {
10068 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10069 Chain = Intrin->getChain();
10070 // Similarly to the store case below, Intrin->getBasePtr() doesn't get
10071 // us what we want. Get operand 2 instead.
10072 Base = Intrin->getOperand(2);
10073 MMO = Intrin->getMemOperand();
10078 MVT VecTy = N->getValueType(0).getSimpleVT();
10079 SDValue LoadOps[] = { Chain, Base };
10080 SDValue Load = DAG.getMemIntrinsicNode(PPCISD::LXVD2X, dl,
10081 DAG.getVTList(VecTy, MVT::Other),
10082 LoadOps, VecTy, MMO);
10083 DCI.AddToWorklist(Load.getNode());
10084 Chain = Load.getValue(1);
10085 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10086 DAG.getVTList(VecTy, MVT::Other), Chain, Load);
10087 DCI.AddToWorklist(Swap.getNode());
10091 // expandVSXStoreForLE - Convert VSX stores (which may be intrinsics for
10092 // builtins) into stores with swaps.
10093 SDValue PPCTargetLowering::expandVSXStoreForLE(SDNode *N,
10094 DAGCombinerInfo &DCI) const {
10095 SelectionDAG &DAG = DCI.DAG;
10100 MachineMemOperand *MMO;
10102 switch (N->getOpcode()) {
10104 llvm_unreachable("Unexpected opcode for little endian VSX store");
10106 StoreSDNode *ST = cast<StoreSDNode>(N);
10107 Chain = ST->getChain();
10108 Base = ST->getBasePtr();
10109 MMO = ST->getMemOperand();
10111 // If the MMO suggests this isn't a store of a full vector, leave
10112 // things alone. For a built-in, we have to make the change for
10113 // correctness, so if there is a size problem that will be a bug.
10114 if (MMO->getSize() < 16)
10118 case ISD::INTRINSIC_VOID: {
10119 MemIntrinsicSDNode *Intrin = cast<MemIntrinsicSDNode>(N);
10120 Chain = Intrin->getChain();
10121 // Intrin->getBasePtr() oddly does not get what we want.
10122 Base = Intrin->getOperand(3);
10123 MMO = Intrin->getMemOperand();
10129 SDValue Src = N->getOperand(SrcOpnd);
10130 MVT VecTy = Src.getValueType().getSimpleVT();
10131 SDValue Swap = DAG.getNode(PPCISD::XXSWAPD, dl,
10132 DAG.getVTList(VecTy, MVT::Other), Chain, Src);
10133 DCI.AddToWorklist(Swap.getNode());
10134 Chain = Swap.getValue(1);
10135 SDValue StoreOps[] = { Chain, Swap, Base };
10136 SDValue Store = DAG.getMemIntrinsicNode(PPCISD::STXVD2X, dl,
10137 DAG.getVTList(MVT::Other),
10138 StoreOps, VecTy, MMO);
10139 DCI.AddToWorklist(Store.getNode());
10143 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
10144 DAGCombinerInfo &DCI) const {
10145 SelectionDAG &DAG = DCI.DAG;
10147 switch (N->getOpcode()) {
10150 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10151 if (C->isNullValue()) // 0 << V -> 0.
10152 return N->getOperand(0);
10156 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10157 if (C->isNullValue()) // 0 >>u V -> 0.
10158 return N->getOperand(0);
10162 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
10163 if (C->isNullValue() || // 0 >>s V -> 0.
10164 C->isAllOnesValue()) // -1 >>s V -> -1.
10165 return N->getOperand(0);
10168 case ISD::SIGN_EXTEND:
10169 case ISD::ZERO_EXTEND:
10170 case ISD::ANY_EXTEND:
10171 return DAGCombineExtBoolTrunc(N, DCI);
10172 case ISD::TRUNCATE:
10174 case ISD::SELECT_CC:
10175 return DAGCombineTruncBoolExt(N, DCI);
10176 case ISD::SINT_TO_FP:
10177 case ISD::UINT_TO_FP:
10178 return combineFPToIntToFP(N, DCI);
10180 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
10181 if (Subtarget.hasSTFIWX() && !cast<StoreSDNode>(N)->isTruncatingStore() &&
10182 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
10183 N->getOperand(1).getValueType() == MVT::i32 &&
10184 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
10185 SDValue Val = N->getOperand(1).getOperand(0);
10186 if (Val.getValueType() == MVT::f32) {
10187 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
10188 DCI.AddToWorklist(Val.getNode());
10190 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
10191 DCI.AddToWorklist(Val.getNode());
10194 N->getOperand(0), Val, N->getOperand(2),
10195 DAG.getValueType(N->getOperand(1).getValueType())
10198 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
10199 DAG.getVTList(MVT::Other), Ops,
10200 cast<StoreSDNode>(N)->getMemoryVT(),
10201 cast<StoreSDNode>(N)->getMemOperand());
10202 DCI.AddToWorklist(Val.getNode());
10206 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
10207 if (cast<StoreSDNode>(N)->isUnindexed() &&
10208 N->getOperand(1).getOpcode() == ISD::BSWAP &&
10209 N->getOperand(1).getNode()->hasOneUse() &&
10210 (N->getOperand(1).getValueType() == MVT::i32 ||
10211 N->getOperand(1).getValueType() == MVT::i16 ||
10212 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10213 N->getOperand(1).getValueType() == MVT::i64))) {
10214 SDValue BSwapOp = N->getOperand(1).getOperand(0);
10215 // Do an any-extend to 32-bits if this is a half-word input.
10216 if (BSwapOp.getValueType() == MVT::i16)
10217 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
10220 N->getOperand(0), BSwapOp, N->getOperand(2),
10221 DAG.getValueType(N->getOperand(1).getValueType())
10224 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
10225 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
10226 cast<StoreSDNode>(N)->getMemOperand());
10229 // For little endian, VSX stores require generating xxswapd/lxvd2x.
10230 EVT VT = N->getOperand(1).getValueType();
10231 if (VT.isSimple()) {
10232 MVT StoreVT = VT.getSimpleVT();
10233 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10234 (StoreVT == MVT::v2f64 || StoreVT == MVT::v2i64 ||
10235 StoreVT == MVT::v4f32 || StoreVT == MVT::v4i32))
10236 return expandVSXStoreForLE(N, DCI);
10241 LoadSDNode *LD = cast<LoadSDNode>(N);
10242 EVT VT = LD->getValueType(0);
10244 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10245 if (VT.isSimple()) {
10246 MVT LoadVT = VT.getSimpleVT();
10247 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() &&
10248 (LoadVT == MVT::v2f64 || LoadVT == MVT::v2i64 ||
10249 LoadVT == MVT::v4f32 || LoadVT == MVT::v4i32))
10250 return expandVSXLoadForLE(N, DCI);
10253 EVT MemVT = LD->getMemoryVT();
10254 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
10255 unsigned ABIAlignment = DAG.getDataLayout().getABITypeAlignment(Ty);
10256 Type *STy = MemVT.getScalarType().getTypeForEVT(*DAG.getContext());
10257 unsigned ScalarABIAlignment = DAG.getDataLayout().getABITypeAlignment(STy);
10258 if (LD->isUnindexed() && VT.isVector() &&
10259 ((Subtarget.hasAltivec() && ISD::isNON_EXTLoad(N) &&
10260 // P8 and later hardware should just use LOAD.
10261 !Subtarget.hasP8Vector() && (VT == MVT::v16i8 || VT == MVT::v8i16 ||
10262 VT == MVT::v4i32 || VT == MVT::v4f32)) ||
10263 (Subtarget.hasQPX() && (VT == MVT::v4f64 || VT == MVT::v4f32) &&
10264 LD->getAlignment() >= ScalarABIAlignment)) &&
10265 LD->getAlignment() < ABIAlignment) {
10266 // This is a type-legal unaligned Altivec or QPX load.
10267 SDValue Chain = LD->getChain();
10268 SDValue Ptr = LD->getBasePtr();
10269 bool isLittleEndian = Subtarget.isLittleEndian();
10271 // This implements the loading of unaligned vectors as described in
10272 // the venerable Apple Velocity Engine overview. Specifically:
10273 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
10274 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
10276 // The general idea is to expand a sequence of one or more unaligned
10277 // loads into an alignment-based permutation-control instruction (lvsl
10278 // or lvsr), a series of regular vector loads (which always truncate
10279 // their input address to an aligned address), and a series of
10280 // permutations. The results of these permutations are the requested
10281 // loaded values. The trick is that the last "extra" load is not taken
10282 // from the address you might suspect (sizeof(vector) bytes after the
10283 // last requested load), but rather sizeof(vector) - 1 bytes after the
10284 // last requested vector. The point of this is to avoid a page fault if
10285 // the base address happened to be aligned. This works because if the
10286 // base address is aligned, then adding less than a full vector length
10287 // will cause the last vector in the sequence to be (re)loaded.
10288 // Otherwise, the next vector will be fetched as you might suspect was
10291 // We might be able to reuse the permutation generation from
10292 // a different base address offset from this one by an aligned amount.
10293 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
10294 // optimization later.
10295 Intrinsic::ID Intr, IntrLD, IntrPerm;
10296 MVT PermCntlTy, PermTy, LDTy;
10297 if (Subtarget.hasAltivec()) {
10298 Intr = isLittleEndian ? Intrinsic::ppc_altivec_lvsr :
10299 Intrinsic::ppc_altivec_lvsl;
10300 IntrLD = Intrinsic::ppc_altivec_lvx;
10301 IntrPerm = Intrinsic::ppc_altivec_vperm;
10302 PermCntlTy = MVT::v16i8;
10303 PermTy = MVT::v4i32;
10306 Intr = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlpcld :
10307 Intrinsic::ppc_qpx_qvlpcls;
10308 IntrLD = MemVT == MVT::v4f64 ? Intrinsic::ppc_qpx_qvlfd :
10309 Intrinsic::ppc_qpx_qvlfs;
10310 IntrPerm = Intrinsic::ppc_qpx_qvfperm;
10311 PermCntlTy = MVT::v4f64;
10312 PermTy = MVT::v4f64;
10313 LDTy = MemVT.getSimpleVT();
10316 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, PermCntlTy);
10318 // Create the new MMO for the new base load. It is like the original MMO,
10319 // but represents an area in memory almost twice the vector size centered
10320 // on the original address. If the address is unaligned, we might start
10321 // reading up to (sizeof(vector)-1) bytes below the address of the
10322 // original unaligned load.
10323 MachineFunction &MF = DAG.getMachineFunction();
10324 MachineMemOperand *BaseMMO =
10325 MF.getMachineMemOperand(LD->getMemOperand(),
10326 -(long)MemVT.getStoreSize()+1,
10327 2*MemVT.getStoreSize()-1);
10329 // Create the new base load.
10331 DAG.getTargetConstant(IntrLD, dl, getPointerTy(MF.getDataLayout()));
10332 SDValue BaseLoadOps[] = { Chain, LDXIntID, Ptr };
10334 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10335 DAG.getVTList(PermTy, MVT::Other),
10336 BaseLoadOps, LDTy, BaseMMO);
10338 // Note that the value of IncOffset (which is provided to the next
10339 // load's pointer info offset value, and thus used to calculate the
10340 // alignment), and the value of IncValue (which is actually used to
10341 // increment the pointer value) are different! This is because we
10342 // require the next load to appear to be aligned, even though it
10343 // is actually offset from the base pointer by a lesser amount.
10344 int IncOffset = VT.getSizeInBits() / 8;
10345 int IncValue = IncOffset;
10347 // Walk (both up and down) the chain looking for another load at the real
10348 // (aligned) offset (the alignment of the other load does not matter in
10349 // this case). If found, then do not use the offset reduction trick, as
10350 // that will prevent the loads from being later combined (as they would
10351 // otherwise be duplicates).
10352 if (!findConsecutiveLoad(LD, DAG))
10355 SDValue Increment =
10356 DAG.getConstant(IncValue, dl, getPointerTy(MF.getDataLayout()));
10357 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
10359 MachineMemOperand *ExtraMMO =
10360 MF.getMachineMemOperand(LD->getMemOperand(),
10361 1, 2*MemVT.getStoreSize()-1);
10362 SDValue ExtraLoadOps[] = { Chain, LDXIntID, Ptr };
10363 SDValue ExtraLoad =
10364 DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, dl,
10365 DAG.getVTList(PermTy, MVT::Other),
10366 ExtraLoadOps, LDTy, ExtraMMO);
10368 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
10369 BaseLoad.getValue(1), ExtraLoad.getValue(1));
10371 // Because vperm has a big-endian bias, we must reverse the order
10372 // of the input vectors and complement the permute control vector
10373 // when generating little endian code. We have already handled the
10374 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
10375 // and ExtraLoad here.
10377 if (isLittleEndian)
10378 Perm = BuildIntrinsicOp(IntrPerm,
10379 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
10381 Perm = BuildIntrinsicOp(IntrPerm,
10382 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
10385 Perm = Subtarget.hasAltivec() ?
10386 DAG.getNode(ISD::BITCAST, dl, VT, Perm) :
10387 DAG.getNode(ISD::FP_ROUND, dl, VT, Perm, // QPX
10388 DAG.getTargetConstant(1, dl, MVT::i64));
10389 // second argument is 1 because this rounding
10390 // is always exact.
10392 // The output of the permutation is our loaded result, the TokenFactor is
10394 DCI.CombineTo(N, Perm, TF);
10395 return SDValue(N, 0);
10399 case ISD::INTRINSIC_WO_CHAIN: {
10400 bool isLittleEndian = Subtarget.isLittleEndian();
10401 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
10402 Intrinsic::ID Intr = (isLittleEndian ? Intrinsic::ppc_altivec_lvsr
10403 : Intrinsic::ppc_altivec_lvsl);
10404 if ((IID == Intr ||
10405 IID == Intrinsic::ppc_qpx_qvlpcld ||
10406 IID == Intrinsic::ppc_qpx_qvlpcls) &&
10407 N->getOperand(1)->getOpcode() == ISD::ADD) {
10408 SDValue Add = N->getOperand(1);
10410 int Bits = IID == Intrinsic::ppc_qpx_qvlpcld ?
10411 5 /* 32 byte alignment */ : 4 /* 16 byte alignment */;
10413 if (DAG.MaskedValueIsZero(
10414 Add->getOperand(1),
10415 APInt::getAllOnesValue(Bits /* alignment */)
10417 Add.getValueType().getScalarType().getSizeInBits()))) {
10418 SDNode *BasePtr = Add->getOperand(0).getNode();
10419 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10420 UE = BasePtr->use_end();
10422 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10423 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() == IID) {
10424 // We've found another LVSL/LVSR, and this address is an aligned
10425 // multiple of that one. The results will be the same, so use the
10426 // one we've just found instead.
10428 return SDValue(*UI, 0);
10433 if (isa<ConstantSDNode>(Add->getOperand(1))) {
10434 SDNode *BasePtr = Add->getOperand(0).getNode();
10435 for (SDNode::use_iterator UI = BasePtr->use_begin(),
10436 UE = BasePtr->use_end(); UI != UE; ++UI) {
10437 if (UI->getOpcode() == ISD::ADD &&
10438 isa<ConstantSDNode>(UI->getOperand(1)) &&
10439 (cast<ConstantSDNode>(Add->getOperand(1))->getZExtValue() -
10440 cast<ConstantSDNode>(UI->getOperand(1))->getZExtValue()) %
10441 (1ULL << Bits) == 0) {
10442 SDNode *OtherAdd = *UI;
10443 for (SDNode::use_iterator VI = OtherAdd->use_begin(),
10444 VE = OtherAdd->use_end(); VI != VE; ++VI) {
10445 if (VI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10446 cast<ConstantSDNode>(VI->getOperand(0))->getZExtValue() == IID) {
10447 return SDValue(*VI, 0);
10457 case ISD::INTRINSIC_W_CHAIN: {
10458 // For little endian, VSX loads require generating lxvd2x/xxswapd.
10459 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10460 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10463 case Intrinsic::ppc_vsx_lxvw4x:
10464 case Intrinsic::ppc_vsx_lxvd2x:
10465 return expandVSXLoadForLE(N, DCI);
10470 case ISD::INTRINSIC_VOID: {
10471 // For little endian, VSX stores require generating xxswapd/stxvd2x.
10472 if (Subtarget.hasVSX() && Subtarget.isLittleEndian()) {
10473 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
10476 case Intrinsic::ppc_vsx_stxvw4x:
10477 case Intrinsic::ppc_vsx_stxvd2x:
10478 return expandVSXStoreForLE(N, DCI);
10484 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
10485 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
10486 N->getOperand(0).hasOneUse() &&
10487 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
10488 (Subtarget.hasLDBRX() && Subtarget.isPPC64() &&
10489 N->getValueType(0) == MVT::i64))) {
10490 SDValue Load = N->getOperand(0);
10491 LoadSDNode *LD = cast<LoadSDNode>(Load);
10492 // Create the byte-swapping load.
10494 LD->getChain(), // Chain
10495 LD->getBasePtr(), // Ptr
10496 DAG.getValueType(N->getValueType(0)) // VT
10499 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
10500 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
10501 MVT::i64 : MVT::i32, MVT::Other),
10502 Ops, LD->getMemoryVT(), LD->getMemOperand());
10504 // If this is an i16 load, insert the truncate.
10505 SDValue ResVal = BSLoad;
10506 if (N->getValueType(0) == MVT::i16)
10507 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
10509 // First, combine the bswap away. This makes the value produced by the
10511 DCI.CombineTo(N, ResVal);
10513 // Next, combine the load away, we give it a bogus result value but a real
10514 // chain result. The result value is dead because the bswap is dead.
10515 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
10517 // Return N so it doesn't get rechecked!
10518 return SDValue(N, 0);
10522 case PPCISD::VCMP: {
10523 // If a VCMPo node already exists with exactly the same operands as this
10524 // node, use its result instead of this node (VCMPo computes both a CR6 and
10525 // a normal output).
10527 if (!N->getOperand(0).hasOneUse() &&
10528 !N->getOperand(1).hasOneUse() &&
10529 !N->getOperand(2).hasOneUse()) {
10531 // Scan all of the users of the LHS, looking for VCMPo's that match.
10532 SDNode *VCMPoNode = nullptr;
10534 SDNode *LHSN = N->getOperand(0).getNode();
10535 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
10537 if (UI->getOpcode() == PPCISD::VCMPo &&
10538 UI->getOperand(1) == N->getOperand(1) &&
10539 UI->getOperand(2) == N->getOperand(2) &&
10540 UI->getOperand(0) == N->getOperand(0)) {
10545 // If there is no VCMPo node, or if the flag value has a single use, don't
10547 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
10550 // Look at the (necessarily single) use of the flag value. If it has a
10551 // chain, this transformation is more complex. Note that multiple things
10552 // could use the value result, which we should ignore.
10553 SDNode *FlagUser = nullptr;
10554 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
10555 FlagUser == nullptr; ++UI) {
10556 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
10557 SDNode *User = *UI;
10558 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
10559 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
10566 // If the user is a MFOCRF instruction, we know this is safe.
10567 // Otherwise we give up for right now.
10568 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
10569 return SDValue(VCMPoNode, 0);
10573 case ISD::BRCOND: {
10574 SDValue Cond = N->getOperand(1);
10575 SDValue Target = N->getOperand(2);
10577 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10578 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
10579 Intrinsic::ppc_is_decremented_ctr_nonzero) {
10581 // We now need to make the intrinsic dead (it cannot be instruction
10583 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
10584 assert(Cond.getNode()->hasOneUse() &&
10585 "Counter decrement has more than one use");
10587 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
10588 N->getOperand(0), Target);
10593 // If this is a branch on an altivec predicate comparison, lower this so
10594 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
10595 // lowering is done pre-legalize, because the legalizer lowers the predicate
10596 // compare down to code that is difficult to reassemble.
10597 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
10598 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
10600 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
10601 // value. If so, pass-through the AND to get to the intrinsic.
10602 if (LHS.getOpcode() == ISD::AND &&
10603 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10604 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
10605 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10606 isa<ConstantSDNode>(LHS.getOperand(1)) &&
10607 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
10609 LHS = LHS.getOperand(0);
10611 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
10612 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
10613 Intrinsic::ppc_is_decremented_ctr_nonzero &&
10614 isa<ConstantSDNode>(RHS)) {
10615 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
10616 "Counter decrement comparison is not EQ or NE");
10618 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10619 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
10620 (CC == ISD::SETNE && !Val);
10622 // We now need to make the intrinsic dead (it cannot be instruction
10624 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
10625 assert(LHS.getNode()->hasOneUse() &&
10626 "Counter decrement has more than one use");
10628 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
10629 N->getOperand(0), N->getOperand(4));
10635 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
10636 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
10637 getAltivecCompareInfo(LHS, CompareOpc, isDot, Subtarget)) {
10638 assert(isDot && "Can't compare against a vector result!");
10640 // If this is a comparison against something other than 0/1, then we know
10641 // that the condition is never/always true.
10642 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
10643 if (Val != 0 && Val != 1) {
10644 if (CC == ISD::SETEQ) // Cond never true, remove branch.
10645 return N->getOperand(0);
10646 // Always !=, turn it into an unconditional branch.
10647 return DAG.getNode(ISD::BR, dl, MVT::Other,
10648 N->getOperand(0), N->getOperand(4));
10651 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
10653 // Create the PPCISD altivec 'dot' comparison node.
10655 LHS.getOperand(2), // LHS of compare
10656 LHS.getOperand(3), // RHS of compare
10657 DAG.getConstant(CompareOpc, dl, MVT::i32)
10659 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
10660 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
10662 // Unpack the result based on how the target uses it.
10663 PPC::Predicate CompOpc;
10664 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
10665 default: // Can't happen, don't crash on invalid number though.
10666 case 0: // Branch on the value of the EQ bit of CR6.
10667 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
10669 case 1: // Branch on the inverted value of the EQ bit of CR6.
10670 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
10672 case 2: // Branch on the value of the LT bit of CR6.
10673 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
10675 case 3: // Branch on the inverted value of the LT bit of CR6.
10676 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
10680 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
10681 DAG.getConstant(CompOpc, dl, MVT::i32),
10682 DAG.getRegister(PPC::CR6, MVT::i32),
10683 N->getOperand(4), CompNode.getValue(1));
10693 PPCTargetLowering::BuildSDIVPow2(SDNode *N, const APInt &Divisor,
10695 std::vector<SDNode *> *Created) const {
10696 // fold (sdiv X, pow2)
10697 EVT VT = N->getValueType(0);
10698 if (VT == MVT::i64 && !Subtarget.isPPC64())
10700 if ((VT != MVT::i32 && VT != MVT::i64) ||
10701 !(Divisor.isPowerOf2() || (-Divisor).isPowerOf2()))
10705 SDValue N0 = N->getOperand(0);
10707 bool IsNegPow2 = (-Divisor).isPowerOf2();
10708 unsigned Lg2 = (IsNegPow2 ? -Divisor : Divisor).countTrailingZeros();
10709 SDValue ShiftAmt = DAG.getConstant(Lg2, DL, VT);
10711 SDValue Op = DAG.getNode(PPCISD::SRA_ADDZE, DL, VT, N0, ShiftAmt);
10713 Created->push_back(Op.getNode());
10716 Op = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, DL, VT), Op);
10718 Created->push_back(Op.getNode());
10724 //===----------------------------------------------------------------------===//
10725 // Inline Assembly Support
10726 //===----------------------------------------------------------------------===//
10728 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
10731 const SelectionDAG &DAG,
10732 unsigned Depth) const {
10733 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
10734 switch (Op.getOpcode()) {
10736 case PPCISD::LBRX: {
10737 // lhbrx is known to have the top bits cleared out.
10738 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
10739 KnownZero = 0xFFFF0000;
10742 case ISD::INTRINSIC_WO_CHAIN: {
10743 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
10745 case Intrinsic::ppc_altivec_vcmpbfp_p:
10746 case Intrinsic::ppc_altivec_vcmpeqfp_p:
10747 case Intrinsic::ppc_altivec_vcmpequb_p:
10748 case Intrinsic::ppc_altivec_vcmpequh_p:
10749 case Intrinsic::ppc_altivec_vcmpequw_p:
10750 case Intrinsic::ppc_altivec_vcmpequd_p:
10751 case Intrinsic::ppc_altivec_vcmpgefp_p:
10752 case Intrinsic::ppc_altivec_vcmpgtfp_p:
10753 case Intrinsic::ppc_altivec_vcmpgtsb_p:
10754 case Intrinsic::ppc_altivec_vcmpgtsh_p:
10755 case Intrinsic::ppc_altivec_vcmpgtsw_p:
10756 case Intrinsic::ppc_altivec_vcmpgtsd_p:
10757 case Intrinsic::ppc_altivec_vcmpgtub_p:
10758 case Intrinsic::ppc_altivec_vcmpgtuh_p:
10759 case Intrinsic::ppc_altivec_vcmpgtuw_p:
10760 case Intrinsic::ppc_altivec_vcmpgtud_p:
10761 KnownZero = ~1U; // All bits but the low one are known to be zero.
10768 unsigned PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
10769 switch (Subtarget.getDarwinDirective()) {
10772 case PPC::DIR_PWR4:
10773 case PPC::DIR_PWR5:
10774 case PPC::DIR_PWR5X:
10775 case PPC::DIR_PWR6:
10776 case PPC::DIR_PWR6X:
10777 case PPC::DIR_PWR7:
10778 case PPC::DIR_PWR8: {
10782 const PPCInstrInfo *TII = Subtarget.getInstrInfo();
10784 // For small loops (between 5 and 8 instructions), align to a 32-byte
10785 // boundary so that the entire loop fits in one instruction-cache line.
10786 uint64_t LoopSize = 0;
10787 for (auto I = ML->block_begin(), IE = ML->block_end(); I != IE; ++I)
10788 for (auto J = (*I)->begin(), JE = (*I)->end(); J != JE; ++J)
10789 LoopSize += TII->GetInstSizeInBytes(J);
10791 if (LoopSize > 16 && LoopSize <= 32)
10798 return TargetLowering::getPrefLoopAlignment(ML);
10801 /// getConstraintType - Given a constraint, return the type of
10802 /// constraint it is for this target.
10803 PPCTargetLowering::ConstraintType
10804 PPCTargetLowering::getConstraintType(StringRef Constraint) const {
10805 if (Constraint.size() == 1) {
10806 switch (Constraint[0]) {
10813 return C_RegisterClass;
10815 // FIXME: While Z does indicate a memory constraint, it specifically
10816 // indicates an r+r address (used in conjunction with the 'y' modifier
10817 // in the replacement string). Currently, we're forcing the base
10818 // register to be r0 in the asm printer (which is interpreted as zero)
10819 // and forming the complete address in the second register. This is
10823 } else if (Constraint == "wc") { // individual CR bits.
10824 return C_RegisterClass;
10825 } else if (Constraint == "wa" || Constraint == "wd" ||
10826 Constraint == "wf" || Constraint == "ws") {
10827 return C_RegisterClass; // VSX registers.
10829 return TargetLowering::getConstraintType(Constraint);
10832 /// Examine constraint type and operand type and determine a weight value.
10833 /// This object must already have been set up with the operand type
10834 /// and the current alternative constraint selected.
10835 TargetLowering::ConstraintWeight
10836 PPCTargetLowering::getSingleConstraintMatchWeight(
10837 AsmOperandInfo &info, const char *constraint) const {
10838 ConstraintWeight weight = CW_Invalid;
10839 Value *CallOperandVal = info.CallOperandVal;
10840 // If we don't have a value, we can't do a match,
10841 // but allow it at the lowest weight.
10842 if (!CallOperandVal)
10844 Type *type = CallOperandVal->getType();
10846 // Look at the constraint type.
10847 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
10848 return CW_Register; // an individual CR bit.
10849 else if ((StringRef(constraint) == "wa" ||
10850 StringRef(constraint) == "wd" ||
10851 StringRef(constraint) == "wf") &&
10852 type->isVectorTy())
10853 return CW_Register;
10854 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
10855 return CW_Register;
10857 switch (*constraint) {
10859 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
10862 if (type->isIntegerTy())
10863 weight = CW_Register;
10866 if (type->isFloatTy())
10867 weight = CW_Register;
10870 if (type->isDoubleTy())
10871 weight = CW_Register;
10874 if (type->isVectorTy())
10875 weight = CW_Register;
10878 weight = CW_Register;
10881 weight = CW_Memory;
10887 std::pair<unsigned, const TargetRegisterClass *>
10888 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
10889 StringRef Constraint,
10891 if (Constraint.size() == 1) {
10892 // GCC RS6000 Constraint Letters
10893 switch (Constraint[0]) {
10894 case 'b': // R1-R31
10895 if (VT == MVT::i64 && Subtarget.isPPC64())
10896 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
10897 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
10898 case 'r': // R0-R31
10899 if (VT == MVT::i64 && Subtarget.isPPC64())
10900 return std::make_pair(0U, &PPC::G8RCRegClass);
10901 return std::make_pair(0U, &PPC::GPRCRegClass);
10903 if (VT == MVT::f32 || VT == MVT::i32)
10904 return std::make_pair(0U, &PPC::F4RCRegClass);
10905 if (VT == MVT::f64 || VT == MVT::i64)
10906 return std::make_pair(0U, &PPC::F8RCRegClass);
10907 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10908 return std::make_pair(0U, &PPC::QFRCRegClass);
10909 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10910 return std::make_pair(0U, &PPC::QSRCRegClass);
10913 if (VT == MVT::v4f64 && Subtarget.hasQPX())
10914 return std::make_pair(0U, &PPC::QFRCRegClass);
10915 if (VT == MVT::v4f32 && Subtarget.hasQPX())
10916 return std::make_pair(0U, &PPC::QSRCRegClass);
10917 return std::make_pair(0U, &PPC::VRRCRegClass);
10919 return std::make_pair(0U, &PPC::CRRCRegClass);
10921 } else if (Constraint == "wc") { // an individual CR bit.
10922 return std::make_pair(0U, &PPC::CRBITRCRegClass);
10923 } else if (Constraint == "wa" || Constraint == "wd" ||
10924 Constraint == "wf") {
10925 return std::make_pair(0U, &PPC::VSRCRegClass);
10926 } else if (Constraint == "ws") {
10927 if (VT == MVT::f32)
10928 return std::make_pair(0U, &PPC::VSSRCRegClass);
10930 return std::make_pair(0U, &PPC::VSFRCRegClass);
10933 std::pair<unsigned, const TargetRegisterClass *> R =
10934 TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
10936 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
10937 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
10938 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
10940 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
10941 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
10942 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
10943 PPC::GPRCRegClass.contains(R.first))
10944 return std::make_pair(TRI->getMatchingSuperReg(R.first,
10945 PPC::sub_32, &PPC::G8RCRegClass),
10946 &PPC::G8RCRegClass);
10948 // GCC accepts 'cc' as an alias for 'cr0', and we need to do the same.
10949 if (!R.second && StringRef("{cc}").equals_lower(Constraint)) {
10950 R.first = PPC::CR0;
10951 R.second = &PPC::CRRCRegClass;
10958 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
10959 /// vector. If it is invalid, don't add anything to Ops.
10960 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
10961 std::string &Constraint,
10962 std::vector<SDValue>&Ops,
10963 SelectionDAG &DAG) const {
10966 // Only support length 1 constraints.
10967 if (Constraint.length() > 1) return;
10969 char Letter = Constraint[0];
10980 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
10981 if (!CST) return; // Must be an immediate to match.
10983 int64_t Value = CST->getSExtValue();
10984 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
10985 // numbers are printed as such.
10987 default: llvm_unreachable("Unknown constraint letter!");
10988 case 'I': // "I" is a signed 16-bit constant.
10989 if (isInt<16>(Value))
10990 Result = DAG.getTargetConstant(Value, dl, TCVT);
10992 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
10993 if (isShiftedUInt<16, 16>(Value))
10994 Result = DAG.getTargetConstant(Value, dl, TCVT);
10996 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
10997 if (isShiftedInt<16, 16>(Value))
10998 Result = DAG.getTargetConstant(Value, dl, TCVT);
11000 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
11001 if (isUInt<16>(Value))
11002 Result = DAG.getTargetConstant(Value, dl, TCVT);
11004 case 'M': // "M" is a constant that is greater than 31.
11006 Result = DAG.getTargetConstant(Value, dl, TCVT);
11008 case 'N': // "N" is a positive constant that is an exact power of two.
11009 if (Value > 0 && isPowerOf2_64(Value))
11010 Result = DAG.getTargetConstant(Value, dl, TCVT);
11012 case 'O': // "O" is the constant zero.
11014 Result = DAG.getTargetConstant(Value, dl, TCVT);
11016 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
11017 if (isInt<16>(-Value))
11018 Result = DAG.getTargetConstant(Value, dl, TCVT);
11025 if (Result.getNode()) {
11026 Ops.push_back(Result);
11030 // Handle standard constraint letters.
11031 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
11034 // isLegalAddressingMode - Return true if the addressing mode represented
11035 // by AM is legal for this target, for a load/store of the specified type.
11036 bool PPCTargetLowering::isLegalAddressingMode(const DataLayout &DL,
11037 const AddrMode &AM, Type *Ty,
11038 unsigned AS) const {
11039 // PPC does not allow r+i addressing modes for vectors!
11040 if (Ty->isVectorTy() && AM.BaseOffs != 0)
11043 // PPC allows a sign-extended 16-bit immediate field.
11044 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
11047 // No global is ever allowed as a base.
11051 // PPC only support r+r,
11052 switch (AM.Scale) {
11053 case 0: // "r+i" or just "i", depending on HasBaseReg.
11056 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
11058 // Otherwise we have r+r or r+i.
11061 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
11063 // Allow 2*r as r+r.
11066 // No other scales are supported.
11073 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
11074 SelectionDAG &DAG) const {
11075 MachineFunction &MF = DAG.getMachineFunction();
11076 MachineFrameInfo *MFI = MF.getFrameInfo();
11077 MFI->setReturnAddressIsTaken(true);
11079 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
11083 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11085 // Make sure the function does not optimize away the store of the RA to
11087 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
11088 FuncInfo->setLRStoreRequired();
11089 bool isPPC64 = Subtarget.isPPC64();
11090 auto PtrVT = getPointerTy(MF.getDataLayout());
11093 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
11095 DAG.getConstant(Subtarget.getFrameLowering()->getReturnSaveOffset(), dl,
11096 isPPC64 ? MVT::i64 : MVT::i32);
11097 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
11098 DAG.getNode(ISD::ADD, dl, PtrVT, FrameAddr, Offset),
11099 MachinePointerInfo(), false, false, false, 0);
11102 // Just load the return address off the stack.
11103 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
11104 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), RetAddrFI,
11105 MachinePointerInfo(), false, false, false, 0);
11108 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
11109 SelectionDAG &DAG) const {
11111 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
11113 MachineFunction &MF = DAG.getMachineFunction();
11114 MachineFrameInfo *MFI = MF.getFrameInfo();
11115 MFI->setFrameAddressIsTaken(true);
11117 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy(MF.getDataLayout());
11118 bool isPPC64 = PtrVT == MVT::i64;
11120 // Naked functions never have a frame pointer, and so we use r1. For all
11121 // other functions, this decision must be delayed until during PEI.
11123 if (MF.getFunction()->hasFnAttribute(Attribute::Naked))
11124 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
11126 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
11128 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
11131 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
11132 FrameAddr, MachinePointerInfo(), false, false,
11137 // FIXME? Maybe this could be a TableGen attribute on some registers and
11138 // this table could be generated automatically from RegInfo.
11139 unsigned PPCTargetLowering::getRegisterByName(const char* RegName, EVT VT,
11140 SelectionDAG &DAG) const {
11141 bool isPPC64 = Subtarget.isPPC64();
11142 bool isDarwinABI = Subtarget.isDarwinABI();
11144 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
11145 (!isPPC64 && VT != MVT::i32))
11146 report_fatal_error("Invalid register global variable type");
11148 bool is64Bit = isPPC64 && VT == MVT::i64;
11149 unsigned Reg = StringSwitch<unsigned>(RegName)
11150 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
11151 .Case("r2", (isDarwinABI || isPPC64) ? 0 : PPC::R2)
11152 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
11153 (is64Bit ? PPC::X13 : PPC::R13))
11158 report_fatal_error("Invalid register name global variable");
11162 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
11163 // The PowerPC target isn't yet aware of offsets.
11167 bool PPCTargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
11169 unsigned Intrinsic) const {
11171 switch (Intrinsic) {
11172 case Intrinsic::ppc_qpx_qvlfd:
11173 case Intrinsic::ppc_qpx_qvlfs:
11174 case Intrinsic::ppc_qpx_qvlfcd:
11175 case Intrinsic::ppc_qpx_qvlfcs:
11176 case Intrinsic::ppc_qpx_qvlfiwa:
11177 case Intrinsic::ppc_qpx_qvlfiwz:
11178 case Intrinsic::ppc_altivec_lvx:
11179 case Intrinsic::ppc_altivec_lvxl:
11180 case Intrinsic::ppc_altivec_lvebx:
11181 case Intrinsic::ppc_altivec_lvehx:
11182 case Intrinsic::ppc_altivec_lvewx:
11183 case Intrinsic::ppc_vsx_lxvd2x:
11184 case Intrinsic::ppc_vsx_lxvw4x: {
11186 switch (Intrinsic) {
11187 case Intrinsic::ppc_altivec_lvebx:
11190 case Intrinsic::ppc_altivec_lvehx:
11193 case Intrinsic::ppc_altivec_lvewx:
11196 case Intrinsic::ppc_vsx_lxvd2x:
11199 case Intrinsic::ppc_qpx_qvlfd:
11202 case Intrinsic::ppc_qpx_qvlfs:
11205 case Intrinsic::ppc_qpx_qvlfcd:
11208 case Intrinsic::ppc_qpx_qvlfcs:
11216 Info.opc = ISD::INTRINSIC_W_CHAIN;
11218 Info.ptrVal = I.getArgOperand(0);
11219 Info.offset = -VT.getStoreSize()+1;
11220 Info.size = 2*VT.getStoreSize()-1;
11223 Info.readMem = true;
11224 Info.writeMem = false;
11227 case Intrinsic::ppc_qpx_qvlfda:
11228 case Intrinsic::ppc_qpx_qvlfsa:
11229 case Intrinsic::ppc_qpx_qvlfcda:
11230 case Intrinsic::ppc_qpx_qvlfcsa:
11231 case Intrinsic::ppc_qpx_qvlfiwaa:
11232 case Intrinsic::ppc_qpx_qvlfiwza: {
11234 switch (Intrinsic) {
11235 case Intrinsic::ppc_qpx_qvlfda:
11238 case Intrinsic::ppc_qpx_qvlfsa:
11241 case Intrinsic::ppc_qpx_qvlfcda:
11244 case Intrinsic::ppc_qpx_qvlfcsa:
11252 Info.opc = ISD::INTRINSIC_W_CHAIN;
11254 Info.ptrVal = I.getArgOperand(0);
11256 Info.size = VT.getStoreSize();
11259 Info.readMem = true;
11260 Info.writeMem = false;
11263 case Intrinsic::ppc_qpx_qvstfd:
11264 case Intrinsic::ppc_qpx_qvstfs:
11265 case Intrinsic::ppc_qpx_qvstfcd:
11266 case Intrinsic::ppc_qpx_qvstfcs:
11267 case Intrinsic::ppc_qpx_qvstfiw:
11268 case Intrinsic::ppc_altivec_stvx:
11269 case Intrinsic::ppc_altivec_stvxl:
11270 case Intrinsic::ppc_altivec_stvebx:
11271 case Intrinsic::ppc_altivec_stvehx:
11272 case Intrinsic::ppc_altivec_stvewx:
11273 case Intrinsic::ppc_vsx_stxvd2x:
11274 case Intrinsic::ppc_vsx_stxvw4x: {
11276 switch (Intrinsic) {
11277 case Intrinsic::ppc_altivec_stvebx:
11280 case Intrinsic::ppc_altivec_stvehx:
11283 case Intrinsic::ppc_altivec_stvewx:
11286 case Intrinsic::ppc_vsx_stxvd2x:
11289 case Intrinsic::ppc_qpx_qvstfd:
11292 case Intrinsic::ppc_qpx_qvstfs:
11295 case Intrinsic::ppc_qpx_qvstfcd:
11298 case Intrinsic::ppc_qpx_qvstfcs:
11306 Info.opc = ISD::INTRINSIC_VOID;
11308 Info.ptrVal = I.getArgOperand(1);
11309 Info.offset = -VT.getStoreSize()+1;
11310 Info.size = 2*VT.getStoreSize()-1;
11313 Info.readMem = false;
11314 Info.writeMem = true;
11317 case Intrinsic::ppc_qpx_qvstfda:
11318 case Intrinsic::ppc_qpx_qvstfsa:
11319 case Intrinsic::ppc_qpx_qvstfcda:
11320 case Intrinsic::ppc_qpx_qvstfcsa:
11321 case Intrinsic::ppc_qpx_qvstfiwa: {
11323 switch (Intrinsic) {
11324 case Intrinsic::ppc_qpx_qvstfda:
11327 case Intrinsic::ppc_qpx_qvstfsa:
11330 case Intrinsic::ppc_qpx_qvstfcda:
11333 case Intrinsic::ppc_qpx_qvstfcsa:
11341 Info.opc = ISD::INTRINSIC_VOID;
11343 Info.ptrVal = I.getArgOperand(1);
11345 Info.size = VT.getStoreSize();
11348 Info.readMem = false;
11349 Info.writeMem = true;
11359 /// getOptimalMemOpType - Returns the target specific optimal type for load
11360 /// and store operations as a result of memset, memcpy, and memmove
11361 /// lowering. If DstAlign is zero that means it's safe to destination
11362 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
11363 /// means there isn't a need to check it against alignment requirement,
11364 /// probably because the source does not need to be loaded. If 'IsMemset' is
11365 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
11366 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
11367 /// source is constant so it does not need to be loaded.
11368 /// It returns EVT::Other if the type should be determined using generic
11369 /// target-independent logic.
11370 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
11371 unsigned DstAlign, unsigned SrcAlign,
11372 bool IsMemset, bool ZeroMemset,
11374 MachineFunction &MF) const {
11375 if (getTargetMachine().getOptLevel() != CodeGenOpt::None) {
11376 const Function *F = MF.getFunction();
11377 // When expanding a memset, require at least two QPX instructions to cover
11378 // the cost of loading the value to be stored from the constant pool.
11379 if (Subtarget.hasQPX() && Size >= 32 && (!IsMemset || Size >= 64) &&
11380 (!SrcAlign || SrcAlign >= 32) && (!DstAlign || DstAlign >= 32) &&
11381 !F->hasFnAttribute(Attribute::NoImplicitFloat)) {
11385 // We should use Altivec/VSX loads and stores when available. For unaligned
11386 // addresses, unaligned VSX loads are only fast starting with the P8.
11387 if (Subtarget.hasAltivec() && Size >= 16 &&
11388 (((!SrcAlign || SrcAlign >= 16) && (!DstAlign || DstAlign >= 16)) ||
11389 ((IsMemset && Subtarget.hasVSX()) || Subtarget.hasP8Vector())))
11393 if (Subtarget.isPPC64()) {
11400 /// \brief Returns true if it is beneficial to convert a load of a constant
11401 /// to just the constant itself.
11402 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
11404 assert(Ty->isIntegerTy());
11406 unsigned BitSize = Ty->getPrimitiveSizeInBits();
11407 if (BitSize == 0 || BitSize > 64)
11412 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
11413 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
11415 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
11416 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
11417 return NumBits1 == 64 && NumBits2 == 32;
11420 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
11421 if (!VT1.isInteger() || !VT2.isInteger())
11423 unsigned NumBits1 = VT1.getSizeInBits();
11424 unsigned NumBits2 = VT2.getSizeInBits();
11425 return NumBits1 == 64 && NumBits2 == 32;
11428 bool PPCTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
11429 // Generally speaking, zexts are not free, but they are free when they can be
11430 // folded with other operations.
11431 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(Val)) {
11432 EVT MemVT = LD->getMemoryVT();
11433 if ((MemVT == MVT::i1 || MemVT == MVT::i8 || MemVT == MVT::i16 ||
11434 (Subtarget.isPPC64() && MemVT == MVT::i32)) &&
11435 (LD->getExtensionType() == ISD::NON_EXTLOAD ||
11436 LD->getExtensionType() == ISD::ZEXTLOAD))
11440 // FIXME: Add other cases...
11441 // - 32-bit shifts with a zext to i64
11442 // - zext after ctlz, bswap, etc.
11443 // - zext after and by a constant mask
11445 return TargetLowering::isZExtFree(Val, VT2);
11448 bool PPCTargetLowering::isFPExtFree(EVT VT) const {
11449 assert(VT.isFloatingPoint());
11453 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
11454 return isInt<16>(Imm) || isUInt<16>(Imm);
11457 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
11458 return isInt<16>(Imm) || isUInt<16>(Imm);
11461 bool PPCTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
11464 bool *Fast) const {
11465 if (DisablePPCUnaligned)
11468 // PowerPC supports unaligned memory access for simple non-vector types.
11469 // Although accessing unaligned addresses is not as efficient as accessing
11470 // aligned addresses, it is generally more efficient than manual expansion,
11471 // and generally only traps for software emulation when crossing page
11474 if (!VT.isSimple())
11477 if (VT.getSimpleVT().isVector()) {
11478 if (Subtarget.hasVSX()) {
11479 if (VT != MVT::v2f64 && VT != MVT::v2i64 &&
11480 VT != MVT::v4f32 && VT != MVT::v4i32)
11487 if (VT == MVT::ppcf128)
11496 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
11497 VT = VT.getScalarType();
11499 if (!VT.isSimple())
11502 switch (VT.getSimpleVT().SimpleTy) {
11514 PPCTargetLowering::getScratchRegisters(CallingConv::ID) const {
11515 // LR is a callee-save register, but we must treat it as clobbered by any call
11516 // site. Hence we include LR in the scratch registers, which are in turn added
11517 // as implicit-defs for stackmaps and patchpoints. The same reasoning applies
11518 // to CTR, which is used by any indirect call.
11519 static const MCPhysReg ScratchRegs[] = {
11520 PPC::X12, PPC::LR8, PPC::CTR8, 0
11523 return ScratchRegs;
11527 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
11528 EVT VT , unsigned DefinedValues) const {
11529 if (VT == MVT::v2i64)
11530 return Subtarget.hasDirectMove(); // Don't need stack ops with direct moves
11532 if (Subtarget.hasQPX()) {
11533 if (VT == MVT::v4f32 || VT == MVT::v4f64 || VT == MVT::v4i1)
11537 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
11540 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
11541 if (DisableILPPref || Subtarget.enableMachineScheduler())
11542 return TargetLowering::getSchedulingPreference(N);
11547 // Create a fast isel object.
11549 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
11550 const TargetLibraryInfo *LibInfo) const {
11551 return PPC::createFastISel(FuncInfo, LibInfo);