1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPerfectShuffle.h"
17 #include "PPCPredicates.h"
18 #include "PPCTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineInstrBuilder.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/PseudoSourceValue.h"
27 #include "llvm/CodeGen/SelectionDAG.h"
28 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
29 #include "llvm/CallingConv.h"
30 #include "llvm/Constants.h"
31 #include "llvm/Function.h"
32 #include "llvm/Intrinsics.h"
33 #include "llvm/Support/MathExtras.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include "llvm/DerivedTypes.h"
41 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
42 CCValAssign::LocInfo &LocInfo,
43 ISD::ArgFlagsTy &ArgFlags,
45 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
47 CCValAssign::LocInfo &LocInfo,
48 ISD::ArgFlagsTy &ArgFlags,
50 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
52 CCValAssign::LocInfo &LocInfo,
53 ISD::ArgFlagsTy &ArgFlags,
56 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
57 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
60 static TargetLoweringObjectFile *CreateTLOF(const PPCTargetMachine &TM) {
61 if (TM.getSubtargetImpl()->isDarwin())
62 return new TargetLoweringObjectFileMachO();
64 return new TargetLoweringObjectFileELF();
67 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
68 : TargetLowering(TM, CreateTLOF(TM)), PPCSubTarget(*TM.getSubtargetImpl()) {
72 // Use _setjmp/_longjmp instead of setjmp/longjmp.
73 setUseUnderscoreSetJmp(true);
74 setUseUnderscoreLongJmp(true);
76 // Set up the register classes.
77 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
78 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
79 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
81 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
82 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
85 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
87 // PowerPC has pre-inc load and store's.
88 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
93 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
99 // This is used in the ppcf128->int sequence. Note it has different semantics
100 // from FP_ROUND: that rounds to nearest, this rounds to zero.
101 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
103 // PowerPC has no SREM/UREM instructions
104 setOperationAction(ISD::SREM, MVT::i32, Expand);
105 setOperationAction(ISD::UREM, MVT::i32, Expand);
106 setOperationAction(ISD::SREM, MVT::i64, Expand);
107 setOperationAction(ISD::UREM, MVT::i64, Expand);
109 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
110 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
111 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
112 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
113 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
114 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
115 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
116 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
117 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
119 // We don't support sin/cos/sqrt/fmod/pow
120 setOperationAction(ISD::FSIN , MVT::f64, Expand);
121 setOperationAction(ISD::FCOS , MVT::f64, Expand);
122 setOperationAction(ISD::FREM , MVT::f64, Expand);
123 setOperationAction(ISD::FPOW , MVT::f64, Expand);
124 setOperationAction(ISD::FSIN , MVT::f32, Expand);
125 setOperationAction(ISD::FCOS , MVT::f32, Expand);
126 setOperationAction(ISD::FREM , MVT::f32, Expand);
127 setOperationAction(ISD::FPOW , MVT::f32, Expand);
129 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
131 // If we're enabling GP optimizations, use hardware square root
132 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
133 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
134 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
137 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
138 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
140 // PowerPC does not have BSWAP, CTPOP or CTTZ
141 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
142 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
143 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
144 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
145 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
146 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
148 // PowerPC does not have ROTR
149 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
150 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
152 // PowerPC does not have Select
153 setOperationAction(ISD::SELECT, MVT::i32, Expand);
154 setOperationAction(ISD::SELECT, MVT::i64, Expand);
155 setOperationAction(ISD::SELECT, MVT::f32, Expand);
156 setOperationAction(ISD::SELECT, MVT::f64, Expand);
158 // PowerPC wants to turn select_cc of FP into fsel when possible.
159 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
160 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
162 // PowerPC wants to optimize integer setcc a bit
163 setOperationAction(ISD::SETCC, MVT::i32, Custom);
165 // PowerPC does not have BRCOND which requires SetCC
166 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
168 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
170 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
171 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
173 // PowerPC does not have [U|S]INT_TO_FP
174 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
175 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
177 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
178 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
179 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
180 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
182 // We cannot sextinreg(i1). Expand to shifts.
183 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
185 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
186 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
187 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
188 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
191 // We want to legalize GlobalAddress and ConstantPool nodes into the
192 // appropriate instructions to materialize the address.
193 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
194 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
195 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
196 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
197 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
198 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
199 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
200 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
201 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
202 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
205 setOperationAction(ISD::TRAP, MVT::Other, Legal);
207 // TRAMPOLINE is custom lowered.
208 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
210 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
211 setOperationAction(ISD::VASTART , MVT::Other, Custom);
213 // VAARG is custom lowered with the 32-bit SVR4 ABI.
214 if ( TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
215 && !TM.getSubtarget<PPCSubtarget>().isPPC64())
216 setOperationAction(ISD::VAARG, MVT::Other, Custom);
218 setOperationAction(ISD::VAARG, MVT::Other, Expand);
220 // Use the default implementation.
221 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
222 setOperationAction(ISD::VAEND , MVT::Other, Expand);
223 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
224 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
225 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
226 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
228 // We want to custom lower some of our intrinsics.
229 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
231 // Comparisons that require checking two conditions.
232 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
233 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
234 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
235 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
236 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
237 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
238 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
239 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
240 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
241 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
242 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
243 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
245 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
246 // They also have instructions for converting between i64 and fp.
247 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
248 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
249 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
250 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
251 // This is just the low 32 bits of a (signed) fp->i64 conversion.
252 // We cannot do this with Promote because i64 is not a legal type.
253 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
255 // FIXME: disable this lowered code. This generates 64-bit register values,
256 // and we don't model the fact that the top part is clobbered by calls. We
257 // need to flag these together so that the value isn't live across a call.
258 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
260 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
261 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
264 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
265 // 64-bit PowerPC implementations can support i64 types directly
266 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
267 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
268 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
269 // 64-bit PowerPC wants to expand i128 shifts itself.
270 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
271 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
272 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
274 // 32-bit PowerPC wants to expand i64 shifts itself.
275 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
276 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
277 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
280 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
281 // First set operation action for all vector types to expand. Then we
282 // will selectively turn on ones that can be effectively codegen'd.
283 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
284 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
285 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
287 // add/sub are legal for all supported vector VT's.
288 setOperationAction(ISD::ADD , VT, Legal);
289 setOperationAction(ISD::SUB , VT, Legal);
291 // We promote all shuffles to v16i8.
292 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
293 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
295 // We promote all non-typed operations to v4i32.
296 setOperationAction(ISD::AND , VT, Promote);
297 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
298 setOperationAction(ISD::OR , VT, Promote);
299 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
300 setOperationAction(ISD::XOR , VT, Promote);
301 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
302 setOperationAction(ISD::LOAD , VT, Promote);
303 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
304 setOperationAction(ISD::SELECT, VT, Promote);
305 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
306 setOperationAction(ISD::STORE, VT, Promote);
307 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
309 // No other operations are legal.
310 setOperationAction(ISD::MUL , VT, Expand);
311 setOperationAction(ISD::SDIV, VT, Expand);
312 setOperationAction(ISD::SREM, VT, Expand);
313 setOperationAction(ISD::UDIV, VT, Expand);
314 setOperationAction(ISD::UREM, VT, Expand);
315 setOperationAction(ISD::FDIV, VT, Expand);
316 setOperationAction(ISD::FNEG, VT, Expand);
317 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
318 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
319 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
320 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
321 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
322 setOperationAction(ISD::UDIVREM, VT, Expand);
323 setOperationAction(ISD::SDIVREM, VT, Expand);
324 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
325 setOperationAction(ISD::FPOW, VT, Expand);
326 setOperationAction(ISD::CTPOP, VT, Expand);
327 setOperationAction(ISD::CTLZ, VT, Expand);
328 setOperationAction(ISD::CTTZ, VT, Expand);
331 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
332 // with merges, splats, etc.
333 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
335 setOperationAction(ISD::AND , MVT::v4i32, Legal);
336 setOperationAction(ISD::OR , MVT::v4i32, Legal);
337 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
338 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
339 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
340 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
342 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
343 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
344 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
345 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
347 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
348 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
349 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
350 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
352 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
353 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
355 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
356 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
357 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
358 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
361 setShiftAmountType(MVT::i32);
362 setBooleanContents(ZeroOrOneBooleanContent);
364 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
365 setStackPointerRegisterToSaveRestore(PPC::X1);
366 setExceptionPointerRegister(PPC::X3);
367 setExceptionSelectorRegister(PPC::X4);
369 setStackPointerRegisterToSaveRestore(PPC::R1);
370 setExceptionPointerRegister(PPC::R3);
371 setExceptionSelectorRegister(PPC::R4);
374 // We have target-specific dag combine patterns for the following nodes:
375 setTargetDAGCombine(ISD::SINT_TO_FP);
376 setTargetDAGCombine(ISD::STORE);
377 setTargetDAGCombine(ISD::BR_CC);
378 setTargetDAGCombine(ISD::BSWAP);
380 // Darwin long double math library functions have $LDBL128 appended.
381 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
382 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
383 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
384 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
385 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
386 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
387 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
388 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
389 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
390 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
391 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
394 computeRegisterProperties();
397 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
398 /// function arguments in the caller parameter area.
399 unsigned PPCTargetLowering::getByValTypeAlignment(const Type *Ty) const {
400 const TargetMachine &TM = getTargetMachine();
401 // Darwin passes everything on 4 byte boundary.
402 if (TM.getSubtarget<PPCSubtarget>().isDarwin())
408 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
411 case PPCISD::FSEL: return "PPCISD::FSEL";
412 case PPCISD::FCFID: return "PPCISD::FCFID";
413 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
414 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
415 case PPCISD::STFIWX: return "PPCISD::STFIWX";
416 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
417 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
418 case PPCISD::VPERM: return "PPCISD::VPERM";
419 case PPCISD::Hi: return "PPCISD::Hi";
420 case PPCISD::Lo: return "PPCISD::Lo";
421 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
422 case PPCISD::TOC_RESTORE: return "PPCISD::TOC_RESTORE";
423 case PPCISD::LOAD: return "PPCISD::LOAD";
424 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
425 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
426 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
427 case PPCISD::SRL: return "PPCISD::SRL";
428 case PPCISD::SRA: return "PPCISD::SRA";
429 case PPCISD::SHL: return "PPCISD::SHL";
430 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
431 case PPCISD::STD_32: return "PPCISD::STD_32";
432 case PPCISD::CALL_SVR4: return "PPCISD::CALL_SVR4";
433 case PPCISD::CALL_Darwin: return "PPCISD::CALL_Darwin";
434 case PPCISD::NOP: return "PPCISD::NOP";
435 case PPCISD::MTCTR: return "PPCISD::MTCTR";
436 case PPCISD::BCTRL_Darwin: return "PPCISD::BCTRL_Darwin";
437 case PPCISD::BCTRL_SVR4: return "PPCISD::BCTRL_SVR4";
438 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
439 case PPCISD::MFCR: return "PPCISD::MFCR";
440 case PPCISD::VCMP: return "PPCISD::VCMP";
441 case PPCISD::VCMPo: return "PPCISD::VCMPo";
442 case PPCISD::LBRX: return "PPCISD::LBRX";
443 case PPCISD::STBRX: return "PPCISD::STBRX";
444 case PPCISD::LARX: return "PPCISD::LARX";
445 case PPCISD::STCX: return "PPCISD::STCX";
446 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
447 case PPCISD::MFFS: return "PPCISD::MFFS";
448 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
449 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
450 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
451 case PPCISD::MTFSF: return "PPCISD::MTFSF";
452 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
456 MVT::SimpleValueType PPCTargetLowering::getSetCCResultType(EVT VT) const {
460 /// getFunctionAlignment - Return the Log2 alignment of this function.
461 unsigned PPCTargetLowering::getFunctionAlignment(const Function *F) const {
462 if (getTargetMachine().getSubtarget<PPCSubtarget>().isDarwin())
463 return F->hasFnAttr(Attribute::OptimizeForSize) ? 2 : 4;
468 //===----------------------------------------------------------------------===//
469 // Node matching predicates, for use by the tblgen matching code.
470 //===----------------------------------------------------------------------===//
472 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
473 static bool isFloatingPointZero(SDValue Op) {
474 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
475 return CFP->getValueAPF().isZero();
476 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
477 // Maybe this has already been legalized into the constant pool?
478 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
479 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
480 return CFP->getValueAPF().isZero();
485 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
486 /// true if Op is undef or if it matches the specified value.
487 static bool isConstantOrUndef(int Op, int Val) {
488 return Op < 0 || Op == Val;
491 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
492 /// VPKUHUM instruction.
493 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
495 for (unsigned i = 0; i != 16; ++i)
496 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1))
499 for (unsigned i = 0; i != 8; ++i)
500 if (!isConstantOrUndef(N->getMaskElt(i), i*2+1) ||
501 !isConstantOrUndef(N->getMaskElt(i+8), i*2+1))
507 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
508 /// VPKUWUM instruction.
509 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary) {
511 for (unsigned i = 0; i != 16; i += 2)
512 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
513 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3))
516 for (unsigned i = 0; i != 8; i += 2)
517 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+2) ||
518 !isConstantOrUndef(N->getMaskElt(i+1), i*2+3) ||
519 !isConstantOrUndef(N->getMaskElt(i+8), i*2+2) ||
520 !isConstantOrUndef(N->getMaskElt(i+9), i*2+3))
526 /// isVMerge - Common function, used to match vmrg* shuffles.
528 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
529 unsigned LHSStart, unsigned RHSStart) {
530 assert(N->getValueType(0) == MVT::v16i8 &&
531 "PPC only supports shuffles by bytes!");
532 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
533 "Unsupported merge size!");
535 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
536 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
537 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
538 LHSStart+j+i*UnitSize) ||
539 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
540 RHSStart+j+i*UnitSize))
546 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
547 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
548 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
551 return isVMerge(N, UnitSize, 8, 24);
552 return isVMerge(N, UnitSize, 8, 8);
555 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
556 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
557 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
560 return isVMerge(N, UnitSize, 0, 16);
561 return isVMerge(N, UnitSize, 0, 0);
565 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
566 /// amount, otherwise return -1.
567 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
568 assert(N->getValueType(0) == MVT::v16i8 &&
569 "PPC only supports shuffles by bytes!");
571 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
573 // Find the first non-undef value in the shuffle mask.
575 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
578 if (i == 16) return -1; // all undef.
580 // Otherwise, check to see if the rest of the elements are consecutively
581 // numbered from this value.
582 unsigned ShiftAmt = SVOp->getMaskElt(i);
583 if (ShiftAmt < i) return -1;
587 // Check the rest of the elements to see if they are consecutive.
588 for (++i; i != 16; ++i)
589 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
592 // Check the rest of the elements to see if they are consecutive.
593 for (++i; i != 16; ++i)
594 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
600 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
601 /// specifies a splat of a single element that is suitable for input to
602 /// VSPLTB/VSPLTH/VSPLTW.
603 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
604 assert(N->getValueType(0) == MVT::v16i8 &&
605 (EltSize == 1 || EltSize == 2 || EltSize == 4));
607 // This is a splat operation if each element of the permute is the same, and
608 // if the value doesn't reference the second vector.
609 unsigned ElementBase = N->getMaskElt(0);
611 // FIXME: Handle UNDEF elements too!
612 if (ElementBase >= 16)
615 // Check that the indices are consecutive, in the case of a multi-byte element
616 // splatted with a v16i8 mask.
617 for (unsigned i = 1; i != EltSize; ++i)
618 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
621 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
622 if (N->getMaskElt(i) < 0) continue;
623 for (unsigned j = 0; j != EltSize; ++j)
624 if (N->getMaskElt(i+j) != N->getMaskElt(j))
630 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
632 bool PPC::isAllNegativeZeroVector(SDNode *N) {
633 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
635 APInt APVal, APUndef;
639 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
640 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
641 return CFP->getValueAPF().isNegZero();
646 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
647 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
648 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
649 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
650 assert(isSplatShuffleMask(SVOp, EltSize));
651 return SVOp->getMaskElt(0) / EltSize;
654 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
655 /// by using a vspltis[bhw] instruction of the specified element size, return
656 /// the constant being splatted. The ByteSize field indicates the number of
657 /// bytes of each element [124] -> [bhw].
658 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
661 // If ByteSize of the splat is bigger than the element size of the
662 // build_vector, then we have a case where we are checking for a splat where
663 // multiple elements of the buildvector are folded together into a single
664 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
665 unsigned EltSize = 16/N->getNumOperands();
666 if (EltSize < ByteSize) {
667 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
668 SDValue UniquedVals[4];
669 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
671 // See if all of the elements in the buildvector agree across.
672 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
673 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
674 // If the element isn't a constant, bail fully out.
675 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
678 if (UniquedVals[i&(Multiple-1)].getNode() == 0)
679 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
680 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
681 return SDValue(); // no match.
684 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
685 // either constant or undef values that are identical for each chunk. See
686 // if these chunks can form into a larger vspltis*.
688 // Check to see if all of the leading entries are either 0 or -1. If
689 // neither, then this won't fit into the immediate field.
690 bool LeadingZero = true;
691 bool LeadingOnes = true;
692 for (unsigned i = 0; i != Multiple-1; ++i) {
693 if (UniquedVals[i].getNode() == 0) continue; // Must have been undefs.
695 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
696 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
698 // Finally, check the least significant entry.
700 if (UniquedVals[Multiple-1].getNode() == 0)
701 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
702 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
704 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
707 if (UniquedVals[Multiple-1].getNode() == 0)
708 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
709 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
710 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
711 return DAG.getTargetConstant(Val, MVT::i32);
717 // Check to see if this buildvec has a single non-undef value in its elements.
718 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
719 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
720 if (OpVal.getNode() == 0)
721 OpVal = N->getOperand(i);
722 else if (OpVal != N->getOperand(i))
726 if (OpVal.getNode() == 0) return SDValue(); // All UNDEF: use implicit def.
728 unsigned ValSizeInBytes = EltSize;
730 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
731 Value = CN->getZExtValue();
732 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
733 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
734 Value = FloatToBits(CN->getValueAPF().convertToFloat());
737 // If the splat value is larger than the element value, then we can never do
738 // this splat. The only case that we could fit the replicated bits into our
739 // immediate field for would be zero, and we prefer to use vxor for it.
740 if (ValSizeInBytes < ByteSize) return SDValue();
742 // If the element value is larger than the splat value, cut it in half and
743 // check to see if the two halves are equal. Continue doing this until we
744 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
745 while (ValSizeInBytes > ByteSize) {
746 ValSizeInBytes >>= 1;
748 // If the top half equals the bottom half, we're still ok.
749 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
750 (Value & ((1 << (8*ValSizeInBytes))-1)))
754 // Properly sign extend the value.
755 int ShAmt = (4-ByteSize)*8;
756 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
758 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
759 if (MaskVal == 0) return SDValue();
761 // Finally, if this value fits in a 5 bit sext field, return it
762 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
763 return DAG.getTargetConstant(MaskVal, MVT::i32);
767 //===----------------------------------------------------------------------===//
768 // Addressing Mode Selection
769 //===----------------------------------------------------------------------===//
771 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
772 /// or 64-bit immediate, and if the value can be accurately represented as a
773 /// sign extension from a 16-bit value. If so, this returns true and the
775 static bool isIntS16Immediate(SDNode *N, short &Imm) {
776 if (N->getOpcode() != ISD::Constant)
779 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
780 if (N->getValueType(0) == MVT::i32)
781 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
783 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
785 static bool isIntS16Immediate(SDValue Op, short &Imm) {
786 return isIntS16Immediate(Op.getNode(), Imm);
790 /// SelectAddressRegReg - Given the specified addressed, check to see if it
791 /// can be represented as an indexed [r+r] operation. Returns false if it
792 /// can be more efficiently represented with [r+imm].
793 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
795 SelectionDAG &DAG) const {
797 if (N.getOpcode() == ISD::ADD) {
798 if (isIntS16Immediate(N.getOperand(1), imm))
800 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
803 Base = N.getOperand(0);
804 Index = N.getOperand(1);
806 } else if (N.getOpcode() == ISD::OR) {
807 if (isIntS16Immediate(N.getOperand(1), imm))
808 return false; // r+i can fold it if we can.
810 // If this is an or of disjoint bitfields, we can codegen this as an add
811 // (for better address arithmetic) if the LHS and RHS of the OR are provably
813 APInt LHSKnownZero, LHSKnownOne;
814 APInt RHSKnownZero, RHSKnownOne;
815 DAG.ComputeMaskedBits(N.getOperand(0),
816 APInt::getAllOnesValue(N.getOperand(0)
817 .getValueSizeInBits()),
818 LHSKnownZero, LHSKnownOne);
820 if (LHSKnownZero.getBoolValue()) {
821 DAG.ComputeMaskedBits(N.getOperand(1),
822 APInt::getAllOnesValue(N.getOperand(1)
823 .getValueSizeInBits()),
824 RHSKnownZero, RHSKnownOne);
825 // If all of the bits are known zero on the LHS or RHS, the add won't
827 if (~(LHSKnownZero | RHSKnownZero) == 0) {
828 Base = N.getOperand(0);
829 Index = N.getOperand(1);
838 /// Returns true if the address N can be represented by a base register plus
839 /// a signed 16-bit displacement [r+imm], and if it is not better
840 /// represented as reg+reg.
841 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
843 SelectionDAG &DAG) const {
844 // FIXME dl should come from parent load or store, not from address
845 DebugLoc dl = N.getDebugLoc();
846 // If this can be more profitably realized as r+r, fail.
847 if (SelectAddressRegReg(N, Disp, Base, DAG))
850 if (N.getOpcode() == ISD::ADD) {
852 if (isIntS16Immediate(N.getOperand(1), imm)) {
853 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
854 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
855 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
857 Base = N.getOperand(0);
859 return true; // [r+i]
860 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
861 // Match LOAD (ADD (X, Lo(G))).
862 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
863 && "Cannot handle constant offsets yet!");
864 Disp = N.getOperand(1).getOperand(0); // The global address.
865 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
866 Disp.getOpcode() == ISD::TargetConstantPool ||
867 Disp.getOpcode() == ISD::TargetJumpTable);
868 Base = N.getOperand(0);
869 return true; // [&g+r]
871 } else if (N.getOpcode() == ISD::OR) {
873 if (isIntS16Immediate(N.getOperand(1), imm)) {
874 // If this is an or of disjoint bitfields, we can codegen this as an add
875 // (for better address arithmetic) if the LHS and RHS of the OR are
876 // provably disjoint.
877 APInt LHSKnownZero, LHSKnownOne;
878 DAG.ComputeMaskedBits(N.getOperand(0),
879 APInt::getAllOnesValue(N.getOperand(0)
880 .getValueSizeInBits()),
881 LHSKnownZero, LHSKnownOne);
883 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
884 // If all of the bits are known zero on the LHS or RHS, the add won't
886 Base = N.getOperand(0);
887 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
891 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
892 // Loading from a constant address.
894 // If this address fits entirely in a 16-bit sext immediate field, codegen
897 if (isIntS16Immediate(CN, Imm)) {
898 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
899 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
903 // Handle 32-bit sext immediates with LIS + addr mode.
904 if (CN->getValueType(0) == MVT::i32 ||
905 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
906 int Addr = (int)CN->getZExtValue();
908 // Otherwise, break this down into an LIS + disp.
909 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
911 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
912 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
913 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
918 Disp = DAG.getTargetConstant(0, getPointerTy());
919 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
920 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
923 return true; // [r+0]
926 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
927 /// represented as an indexed [r+r] operation.
928 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
930 SelectionDAG &DAG) const {
931 // Check to see if we can easily represent this as an [r+r] address. This
932 // will fail if it thinks that the address is more profitably represented as
933 // reg+imm, e.g. where imm = 0.
934 if (SelectAddressRegReg(N, Base, Index, DAG))
937 // If the operand is an addition, always emit this as [r+r], since this is
938 // better (for code size, and execution, as the memop does the add for free)
939 // than emitting an explicit add.
940 if (N.getOpcode() == ISD::ADD) {
941 Base = N.getOperand(0);
942 Index = N.getOperand(1);
946 // Otherwise, do it the hard way, using R0 as the base register.
947 Base = DAG.getRegister(PPC::R0, N.getValueType());
952 /// SelectAddressRegImmShift - Returns true if the address N can be
953 /// represented by a base register plus a signed 14-bit displacement
954 /// [r+imm*4]. Suitable for use by STD and friends.
955 bool PPCTargetLowering::SelectAddressRegImmShift(SDValue N, SDValue &Disp,
957 SelectionDAG &DAG) const {
958 // FIXME dl should come from the parent load or store, not the address
959 DebugLoc dl = N.getDebugLoc();
960 // If this can be more profitably realized as r+r, fail.
961 if (SelectAddressRegReg(N, Disp, Base, DAG))
964 if (N.getOpcode() == ISD::ADD) {
966 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
967 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
968 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
969 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
971 Base = N.getOperand(0);
973 return true; // [r+i]
974 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
975 // Match LOAD (ADD (X, Lo(G))).
976 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
977 && "Cannot handle constant offsets yet!");
978 Disp = N.getOperand(1).getOperand(0); // The global address.
979 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
980 Disp.getOpcode() == ISD::TargetConstantPool ||
981 Disp.getOpcode() == ISD::TargetJumpTable);
982 Base = N.getOperand(0);
983 return true; // [&g+r]
985 } else if (N.getOpcode() == ISD::OR) {
987 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
988 // If this is an or of disjoint bitfields, we can codegen this as an add
989 // (for better address arithmetic) if the LHS and RHS of the OR are
990 // provably disjoint.
991 APInt LHSKnownZero, LHSKnownOne;
992 DAG.ComputeMaskedBits(N.getOperand(0),
993 APInt::getAllOnesValue(N.getOperand(0)
994 .getValueSizeInBits()),
995 LHSKnownZero, LHSKnownOne);
996 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
997 // If all of the bits are known zero on the LHS or RHS, the add won't
999 Base = N.getOperand(0);
1000 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
1004 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1005 // Loading from a constant address. Verify low two bits are clear.
1006 if ((CN->getZExtValue() & 3) == 0) {
1007 // If this address fits entirely in a 14-bit sext immediate field, codegen
1010 if (isIntS16Immediate(CN, Imm)) {
1011 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
1012 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
1016 // Fold the low-part of 32-bit absolute addresses into addr mode.
1017 if (CN->getValueType(0) == MVT::i32 ||
1018 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) {
1019 int Addr = (int)CN->getZExtValue();
1021 // Otherwise, break this down into an LIS + disp.
1022 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
1023 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
1024 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1025 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base),0);
1031 Disp = DAG.getTargetConstant(0, getPointerTy());
1032 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
1033 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1036 return true; // [r+0]
1040 /// getPreIndexedAddressParts - returns true by value, base pointer and
1041 /// offset pointer and addressing mode by reference if the node's address
1042 /// can be legally represented as pre-indexed load / store address.
1043 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1045 ISD::MemIndexedMode &AM,
1046 SelectionDAG &DAG) const {
1047 // Disabled by default for now.
1048 if (!EnablePPCPreinc) return false;
1052 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1053 Ptr = LD->getBasePtr();
1054 VT = LD->getMemoryVT();
1056 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1058 Ptr = ST->getBasePtr();
1059 VT = ST->getMemoryVT();
1063 // PowerPC doesn't have preinc load/store instructions for vectors.
1067 // TODO: Check reg+reg first.
1069 // LDU/STU use reg+imm*4, others use reg+imm.
1070 if (VT != MVT::i64) {
1072 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
1076 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
1080 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1081 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1082 // sext i32 to i64 when addr mode is r+i.
1083 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1084 LD->getExtensionType() == ISD::SEXTLOAD &&
1085 isa<ConstantSDNode>(Offset))
1093 //===----------------------------------------------------------------------===//
1094 // LowerOperation implementation
1095 //===----------------------------------------------------------------------===//
1097 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1098 SelectionDAG &DAG) const {
1099 EVT PtrVT = Op.getValueType();
1100 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1101 const Constant *C = CP->getConstVal();
1102 SDValue CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1103 SDValue Zero = DAG.getConstant(0, PtrVT);
1104 // FIXME there isn't really any debug info here
1105 DebugLoc dl = Op.getDebugLoc();
1107 const TargetMachine &TM = DAG.getTarget();
1109 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, CPI, Zero);
1110 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, CPI, Zero);
1112 // If this is a non-darwin platform, we don't support non-static relo models
1114 if (TM.getRelocationModel() == Reloc::Static ||
1115 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1116 // Generate non-pic code that has direct accesses to the constant pool.
1117 // The address of the global is just (hi(&g)+lo(&g)).
1118 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1121 if (TM.getRelocationModel() == Reloc::PIC_) {
1122 // With PIC, the first instruction is actually "GR+hi(&G)".
1123 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1124 DAG.getNode(PPCISD::GlobalBaseReg,
1125 DebugLoc(), PtrVT), Hi);
1128 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1132 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1133 EVT PtrVT = Op.getValueType();
1134 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1135 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1136 SDValue Zero = DAG.getConstant(0, PtrVT);
1137 // FIXME there isn't really any debug loc here
1138 DebugLoc dl = Op.getDebugLoc();
1140 const TargetMachine &TM = DAG.getTarget();
1142 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, JTI, Zero);
1143 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, JTI, Zero);
1145 // If this is a non-darwin platform, we don't support non-static relo models
1147 if (TM.getRelocationModel() == Reloc::Static ||
1148 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1149 // Generate non-pic code that has direct accesses to the constant pool.
1150 // The address of the global is just (hi(&g)+lo(&g)).
1151 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1154 if (TM.getRelocationModel() == Reloc::PIC_) {
1155 // With PIC, the first instruction is actually "GR+hi(&G)".
1156 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1157 DAG.getNode(PPCISD::GlobalBaseReg,
1158 DebugLoc(), PtrVT), Hi);
1161 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1165 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1166 SelectionDAG &DAG) const {
1167 llvm_unreachable("TLS not implemented for PPC.");
1168 return SDValue(); // Not reached
1171 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1172 SelectionDAG &DAG) const {
1173 EVT PtrVT = Op.getValueType();
1174 DebugLoc DL = Op.getDebugLoc();
1176 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1177 SDValue TgtBA = DAG.getBlockAddress(BA, PtrVT, /*isTarget=*/true);
1178 SDValue Zero = DAG.getConstant(0, PtrVT);
1179 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, TgtBA, Zero);
1180 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, TgtBA, Zero);
1182 // If this is a non-darwin platform, we don't support non-static relo models
1184 const TargetMachine &TM = DAG.getTarget();
1185 if (TM.getRelocationModel() == Reloc::Static ||
1186 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1187 // Generate non-pic code that has direct accesses to globals.
1188 // The address of the global is just (hi(&g)+lo(&g)).
1189 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1192 if (TM.getRelocationModel() == Reloc::PIC_) {
1193 // With PIC, the first instruction is actually "GR+hi(&G)".
1194 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1195 DAG.getNode(PPCISD::GlobalBaseReg,
1196 DebugLoc(), PtrVT), Hi);
1199 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1202 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1203 SelectionDAG &DAG) const {
1204 EVT PtrVT = Op.getValueType();
1205 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1206 // FIXME there isn't really any debug info here
1207 DebugLoc dl = GSDN->getDebugLoc();
1208 const GlobalValue *GV = GSDN->getGlobal();
1209 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, GSDN->getOffset());
1210 SDValue Zero = DAG.getConstant(0, PtrVT);
1212 const TargetMachine &TM = DAG.getTarget();
1214 // 64-bit SVR4 ABI code is always position-independent.
1215 // The actual address of the GlobalValue is stored in the TOC.
1216 if (PPCSubTarget.isSVR4ABI() && PPCSubTarget.isPPC64()) {
1217 return DAG.getNode(PPCISD::TOC_ENTRY, dl, MVT::i64, GA,
1218 DAG.getRegister(PPC::X2, MVT::i64));
1221 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, GA, Zero);
1222 SDValue Lo = DAG.getNode(PPCISD::Lo, dl, PtrVT, GA, Zero);
1224 // If this is a non-darwin platform, we don't support non-static relo models
1226 if (TM.getRelocationModel() == Reloc::Static ||
1227 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1228 // Generate non-pic code that has direct accesses to globals.
1229 // The address of the global is just (hi(&g)+lo(&g)).
1230 return DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1233 if (TM.getRelocationModel() == Reloc::PIC_) {
1234 // With PIC, the first instruction is actually "GR+hi(&G)".
1235 Hi = DAG.getNode(ISD::ADD, dl, PtrVT,
1236 DAG.getNode(PPCISD::GlobalBaseReg,
1237 DebugLoc(), PtrVT), Hi);
1240 Lo = DAG.getNode(ISD::ADD, dl, PtrVT, Hi, Lo);
1242 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM))
1245 // If the global is weak or external, we have to go through the lazy
1247 return DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Lo, NULL, 0,
1251 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1252 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1253 DebugLoc dl = Op.getDebugLoc();
1255 // If we're comparing for equality to zero, expose the fact that this is
1256 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1257 // fold the new nodes.
1258 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1259 if (C->isNullValue() && CC == ISD::SETEQ) {
1260 EVT VT = Op.getOperand(0).getValueType();
1261 SDValue Zext = Op.getOperand(0);
1262 if (VT.bitsLT(MVT::i32)) {
1264 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1266 unsigned Log2b = Log2_32(VT.getSizeInBits());
1267 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1268 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1269 DAG.getConstant(Log2b, MVT::i32));
1270 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1272 // Leave comparisons against 0 and -1 alone for now, since they're usually
1273 // optimized. FIXME: revisit this when we can custom lower all setcc
1275 if (C->isAllOnesValue() || C->isNullValue())
1279 // If we have an integer seteq/setne, turn it into a compare against zero
1280 // by xor'ing the rhs with the lhs, which is faster than setting a
1281 // condition register, reading it back out, and masking the correct bit. The
1282 // normal approach here uses sub to do this instead of xor. Using xor exposes
1283 // the result to other bit-twiddling opportunities.
1284 EVT LHSVT = Op.getOperand(0).getValueType();
1285 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1286 EVT VT = Op.getValueType();
1287 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1289 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1294 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1295 const PPCSubtarget &Subtarget) const {
1297 llvm_unreachable("VAARG not yet implemented for the SVR4 ABI!");
1298 return SDValue(); // Not reached
1301 SDValue PPCTargetLowering::LowerTRAMPOLINE(SDValue Op,
1302 SelectionDAG &DAG) const {
1303 SDValue Chain = Op.getOperand(0);
1304 SDValue Trmp = Op.getOperand(1); // trampoline
1305 SDValue FPtr = Op.getOperand(2); // nested function
1306 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1307 DebugLoc dl = Op.getDebugLoc();
1309 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1310 bool isPPC64 = (PtrVT == MVT::i64);
1311 const Type *IntPtrTy =
1312 DAG.getTargetLoweringInfo().getTargetData()->getIntPtrType(
1315 TargetLowering::ArgListTy Args;
1316 TargetLowering::ArgListEntry Entry;
1318 Entry.Ty = IntPtrTy;
1319 Entry.Node = Trmp; Args.push_back(Entry);
1321 // TrampSize == (isPPC64 ? 48 : 40);
1322 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1323 isPPC64 ? MVT::i64 : MVT::i32);
1324 Args.push_back(Entry);
1326 Entry.Node = FPtr; Args.push_back(Entry);
1327 Entry.Node = Nest; Args.push_back(Entry);
1329 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1330 std::pair<SDValue, SDValue> CallResult =
1331 LowerCallTo(Chain, Op.getValueType().getTypeForEVT(*DAG.getContext()),
1332 false, false, false, false, 0, CallingConv::C, false,
1333 /*isReturnValueUsed=*/true,
1334 DAG.getExternalSymbol("__trampoline_setup", PtrVT),
1338 { CallResult.first, CallResult.second };
1340 return DAG.getMergeValues(Ops, 2, dl);
1343 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1344 const PPCSubtarget &Subtarget) const {
1345 MachineFunction &MF = DAG.getMachineFunction();
1346 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1348 DebugLoc dl = Op.getDebugLoc();
1350 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1351 // vastart just stores the address of the VarArgsFrameIndex slot into the
1352 // memory location argument.
1353 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1354 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1355 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1356 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1), SV, 0,
1360 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1361 // We suppose the given va_list is already allocated.
1364 // char gpr; /* index into the array of 8 GPRs
1365 // * stored in the register save area
1366 // * gpr=0 corresponds to r3,
1367 // * gpr=1 to r4, etc.
1369 // char fpr; /* index into the array of 8 FPRs
1370 // * stored in the register save area
1371 // * fpr=0 corresponds to f1,
1372 // * fpr=1 to f2, etc.
1374 // char *overflow_arg_area;
1375 // /* location on stack that holds
1376 // * the next overflow argument
1378 // char *reg_save_area;
1379 // /* where r3:r10 and f1:f8 (if saved)
1385 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1386 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1389 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1391 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1393 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1396 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
1397 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1399 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
1400 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1402 uint64_t FPROffset = 1;
1403 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1405 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1407 // Store first byte : number of int regs
1408 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
1409 Op.getOperand(1), SV, 0, MVT::i8,
1411 uint64_t nextOffset = FPROffset;
1412 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
1415 // Store second byte : number of float regs
1416 SDValue secondStore =
1417 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr, SV, nextOffset, MVT::i8,
1419 nextOffset += StackOffset;
1420 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
1422 // Store second word : arguments given on stack
1423 SDValue thirdStore =
1424 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr, SV, nextOffset,
1426 nextOffset += FrameOffset;
1427 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
1429 // Store third word : arguments given in registers
1430 return DAG.getStore(thirdStore, dl, FR, nextPtr, SV, nextOffset,
1435 #include "PPCGenCallingConv.inc"
1437 static bool CC_PPC_SVR4_Custom_Dummy(unsigned &ValNo, EVT &ValVT, EVT &LocVT,
1438 CCValAssign::LocInfo &LocInfo,
1439 ISD::ArgFlagsTy &ArgFlags,
1444 static bool CC_PPC_SVR4_Custom_AlignArgRegs(unsigned &ValNo, EVT &ValVT,
1446 CCValAssign::LocInfo &LocInfo,
1447 ISD::ArgFlagsTy &ArgFlags,
1449 static const unsigned ArgRegs[] = {
1450 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1451 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1453 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1455 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1457 // Skip one register if the first unallocated register has an even register
1458 // number and there are still argument registers available which have not been
1459 // allocated yet. RegNum is actually an index into ArgRegs, which means we
1460 // need to skip a register if RegNum is odd.
1461 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
1462 State.AllocateReg(ArgRegs[RegNum]);
1465 // Always return false here, as this function only makes sure that the first
1466 // unallocated register has an odd register number and does not actually
1467 // allocate a register for the current argument.
1471 static bool CC_PPC_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, EVT &ValVT,
1473 CCValAssign::LocInfo &LocInfo,
1474 ISD::ArgFlagsTy &ArgFlags,
1476 static const unsigned ArgRegs[] = {
1477 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1481 const unsigned NumArgRegs = array_lengthof(ArgRegs);
1483 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
1485 // If there is only one Floating-point register left we need to put both f64
1486 // values of a split ppc_fp128 value on the stack.
1487 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
1488 State.AllocateReg(ArgRegs[RegNum]);
1491 // Always return false here, as this function only makes sure that the two f64
1492 // values a ppc_fp128 value is split into are both passed in registers or both
1493 // passed on the stack and does not actually allocate a register for the
1494 // current argument.
1498 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1500 static const unsigned *GetFPR() {
1501 static const unsigned FPR[] = {
1502 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1503 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1509 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
1511 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
1512 unsigned PtrByteSize) {
1513 unsigned ArgSize = ArgVT.getSizeInBits()/8;
1514 if (Flags.isByVal())
1515 ArgSize = Flags.getByValSize();
1516 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1522 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
1523 CallingConv::ID CallConv, bool isVarArg,
1524 const SmallVectorImpl<ISD::InputArg>
1526 DebugLoc dl, SelectionDAG &DAG,
1527 SmallVectorImpl<SDValue> &InVals)
1529 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
1530 return LowerFormalArguments_SVR4(Chain, CallConv, isVarArg, Ins,
1533 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
1539 PPCTargetLowering::LowerFormalArguments_SVR4(
1541 CallingConv::ID CallConv, bool isVarArg,
1542 const SmallVectorImpl<ISD::InputArg>
1544 DebugLoc dl, SelectionDAG &DAG,
1545 SmallVectorImpl<SDValue> &InVals) const {
1547 // 32-bit SVR4 ABI Stack Frame Layout:
1548 // +-----------------------------------+
1549 // +--> | Back chain |
1550 // | +-----------------------------------+
1551 // | | Floating-point register save area |
1552 // | +-----------------------------------+
1553 // | | General register save area |
1554 // | +-----------------------------------+
1555 // | | CR save word |
1556 // | +-----------------------------------+
1557 // | | VRSAVE save word |
1558 // | +-----------------------------------+
1559 // | | Alignment padding |
1560 // | +-----------------------------------+
1561 // | | Vector register save area |
1562 // | +-----------------------------------+
1563 // | | Local variable space |
1564 // | +-----------------------------------+
1565 // | | Parameter list area |
1566 // | +-----------------------------------+
1567 // | | LR save word |
1568 // | +-----------------------------------+
1569 // SP--> +--- | Back chain |
1570 // +-----------------------------------+
1573 // System V Application Binary Interface PowerPC Processor Supplement
1574 // AltiVec Technology Programming Interface Manual
1576 MachineFunction &MF = DAG.getMachineFunction();
1577 MachineFrameInfo *MFI = MF.getFrameInfo();
1578 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1580 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1581 // Potential tail calls could cause overwriting of argument stack slots.
1582 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1583 unsigned PtrByteSize = 4;
1585 // Assign locations to all of the incoming arguments.
1586 SmallVector<CCValAssign, 16> ArgLocs;
1587 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
1590 // Reserve space for the linkage area on the stack.
1591 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
1593 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4);
1595 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1596 CCValAssign &VA = ArgLocs[i];
1598 // Arguments stored in registers.
1599 if (VA.isRegLoc()) {
1600 TargetRegisterClass *RC;
1601 EVT ValVT = VA.getValVT();
1603 switch (ValVT.getSimpleVT().SimpleTy) {
1605 llvm_unreachable("ValVT not supported by formal arguments Lowering");
1607 RC = PPC::GPRCRegisterClass;
1610 RC = PPC::F4RCRegisterClass;
1613 RC = PPC::F8RCRegisterClass;
1619 RC = PPC::VRRCRegisterClass;
1623 // Transform the arguments stored in physical registers into virtual ones.
1624 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
1625 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
1627 InVals.push_back(ArgValue);
1629 // Argument stored in memory.
1630 assert(VA.isMemLoc());
1632 unsigned ArgSize = VA.getLocVT().getSizeInBits() / 8;
1633 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
1636 // Create load nodes to retrieve arguments from the stack.
1637 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1638 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, NULL, 0,
1643 // Assign locations to all of the incoming aggregate by value arguments.
1644 // Aggregates passed by value are stored in the local variable space of the
1645 // caller's stack frame, right above the parameter list area.
1646 SmallVector<CCValAssign, 16> ByValArgLocs;
1647 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(),
1648 ByValArgLocs, *DAG.getContext());
1650 // Reserve stack space for the allocations in CCInfo.
1651 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
1653 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC_SVR4_ByVal);
1655 // Area that is at least reserved in the caller of this function.
1656 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
1658 // Set the size that is at least reserved in caller of this function. Tail
1659 // call optimized function's reserved stack space needs to be aligned so that
1660 // taking the difference between two stack areas will result in an aligned
1662 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1665 std::max(MinReservedArea,
1666 PPCFrameInfo::getMinCallFrameSize(false, false));
1668 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
1669 getStackAlignment();
1670 unsigned AlignMask = TargetAlign-1;
1671 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
1673 FI->setMinReservedArea(MinReservedArea);
1675 SmallVector<SDValue, 8> MemOps;
1677 // If the function takes variable number of arguments, make a frame index for
1678 // the start of the first vararg value... for expansion of llvm.va_start.
1680 static const unsigned GPArgRegs[] = {
1681 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1682 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1684 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
1686 static const unsigned FPArgRegs[] = {
1687 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1690 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
1692 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
1694 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
1697 // Make room for NumGPArgRegs and NumFPArgRegs.
1698 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
1699 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
1701 FuncInfo->setVarArgsStackOffset(
1702 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
1703 CCInfo.getNextStackOffset(), true));
1705 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
1706 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1708 // The fixed integer arguments of a variadic function are
1709 // stored to the VarArgsFrameIndex on the stack.
1710 unsigned GPRIndex = 0;
1711 for (; GPRIndex != FuncInfo->getVarArgsNumGPR(); ++GPRIndex) {
1712 SDValue Val = DAG.getRegister(GPArgRegs[GPRIndex], PtrVT);
1713 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0,
1715 MemOps.push_back(Store);
1716 // Increment the address by four for the next argument to store
1717 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1718 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1721 // If this function is vararg, store any remaining integer argument regs
1722 // to their spots on the stack so that they may be loaded by deferencing the
1723 // result of va_next.
1724 for (; GPRIndex != NumGPArgRegs; ++GPRIndex) {
1725 unsigned VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
1727 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1728 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
1730 MemOps.push_back(Store);
1731 // Increment the address by four for the next argument to store
1732 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
1733 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1736 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
1739 // The double arguments are stored to the VarArgsFrameIndex
1741 unsigned FPRIndex = 0;
1742 for (FPRIndex = 0; FPRIndex != FuncInfo->getVarArgsNumFPR(); ++FPRIndex) {
1743 SDValue Val = DAG.getRegister(FPArgRegs[FPRIndex], MVT::f64);
1744 SDValue Store = DAG.getStore(Chain, dl, Val, FIN, NULL, 0,
1746 MemOps.push_back(Store);
1747 // Increment the address by eight for the next argument to store
1748 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1750 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1753 for (; FPRIndex != NumFPArgRegs; ++FPRIndex) {
1754 unsigned VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
1756 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
1757 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
1759 MemOps.push_back(Store);
1760 // Increment the address by eight for the next argument to store
1761 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
1763 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
1767 if (!MemOps.empty())
1768 Chain = DAG.getNode(ISD::TokenFactor, dl,
1769 MVT::Other, &MemOps[0], MemOps.size());
1775 PPCTargetLowering::LowerFormalArguments_Darwin(
1777 CallingConv::ID CallConv, bool isVarArg,
1778 const SmallVectorImpl<ISD::InputArg>
1780 DebugLoc dl, SelectionDAG &DAG,
1781 SmallVectorImpl<SDValue> &InVals) const {
1782 // TODO: add description of PPC stack frame format, or at least some docs.
1784 MachineFunction &MF = DAG.getMachineFunction();
1785 MachineFrameInfo *MFI = MF.getFrameInfo();
1786 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1788 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1789 bool isPPC64 = PtrVT == MVT::i64;
1790 // Potential tail calls could cause overwriting of argument stack slots.
1791 bool isImmutable = !(GuaranteedTailCallOpt && (CallConv==CallingConv::Fast));
1792 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1794 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
1795 // Area that is at least reserved in caller of this function.
1796 unsigned MinReservedArea = ArgOffset;
1798 static const unsigned GPR_32[] = { // 32-bit registers.
1799 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1800 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1802 static const unsigned GPR_64[] = { // 64-bit registers.
1803 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1804 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1807 static const unsigned *FPR = GetFPR();
1809 static const unsigned VR[] = {
1810 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1811 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1814 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1815 const unsigned Num_FPR_Regs = 13;
1816 const unsigned Num_VR_Regs = array_lengthof( VR);
1818 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1820 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1822 // In 32-bit non-varargs functions, the stack space for vectors is after the
1823 // stack space for non-vectors. We do not use this space unless we have
1824 // too many vectors to fit in registers, something that only occurs in
1825 // constructed examples:), but we have to walk the arglist to figure
1826 // that out...for the pathological case, compute VecArgOffset as the
1827 // start of the vector parameter area. Computing VecArgOffset is the
1828 // entire point of the following loop.
1829 unsigned VecArgOffset = ArgOffset;
1830 if (!isVarArg && !isPPC64) {
1831 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
1833 EVT ObjectVT = Ins[ArgNo].VT;
1834 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1835 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1837 if (Flags.isByVal()) {
1838 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
1839 ObjSize = Flags.getByValSize();
1841 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1842 VecArgOffset += ArgSize;
1846 switch(ObjectVT.getSimpleVT().SimpleTy) {
1847 default: llvm_unreachable("Unhandled argument type!");
1850 VecArgOffset += isPPC64 ? 8 : 4;
1852 case MVT::i64: // PPC64
1860 // Nothing to do, we're only looking at Nonvector args here.
1865 // We've found where the vector parameter area in memory is. Skip the
1866 // first 12 parameters; these don't use that memory.
1867 VecArgOffset = ((VecArgOffset+15)/16)*16;
1868 VecArgOffset += 12*16;
1870 // Add DAG nodes to load the arguments or copy them out of registers. On
1871 // entry to a function on PPC, the arguments start after the linkage area,
1872 // although the first ones are often in registers.
1874 SmallVector<SDValue, 8> MemOps;
1875 unsigned nAltivecParamsAtEnd = 0;
1876 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
1878 bool needsLoad = false;
1879 EVT ObjectVT = Ins[ArgNo].VT;
1880 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
1881 unsigned ArgSize = ObjSize;
1882 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
1884 unsigned CurArgOffset = ArgOffset;
1886 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
1887 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
1888 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
1889 if (isVarArg || isPPC64) {
1890 MinReservedArea = ((MinReservedArea+15)/16)*16;
1891 MinReservedArea += CalculateStackSlotSize(ObjectVT,
1894 } else nAltivecParamsAtEnd++;
1896 // Calculate min reserved area.
1897 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
1901 // FIXME the codegen can be much improved in some cases.
1902 // We do not have to keep everything in memory.
1903 if (Flags.isByVal()) {
1904 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
1905 ObjSize = Flags.getByValSize();
1906 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
1907 // Objects of size 1 and 2 are right justified, everything else is
1908 // left justified. This means the memory address is adjusted forwards.
1909 if (ObjSize==1 || ObjSize==2) {
1910 CurArgOffset = CurArgOffset + (4 - ObjSize);
1912 // The value of the object is its address.
1913 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
1914 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1915 InVals.push_back(FIN);
1916 if (ObjSize==1 || ObjSize==2) {
1917 if (GPR_idx != Num_GPR_Regs) {
1918 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1919 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1920 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
1922 ObjSize==1 ? MVT::i8 : MVT::i16,
1924 MemOps.push_back(Store);
1928 ArgOffset += PtrByteSize;
1932 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
1933 // Store whatever pieces of the object are in registers
1934 // to memory. ArgVal will be address of the beginning of
1936 if (GPR_idx != Num_GPR_Regs) {
1937 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1938 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
1939 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
1940 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
1941 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
1943 MemOps.push_back(Store);
1945 ArgOffset += PtrByteSize;
1947 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
1954 switch (ObjectVT.getSimpleVT().SimpleTy) {
1955 default: llvm_unreachable("Unhandled argument type!");
1958 if (GPR_idx != Num_GPR_Regs) {
1959 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
1960 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1964 ArgSize = PtrByteSize;
1966 // All int arguments reserve stack space in the Darwin ABI.
1967 ArgOffset += PtrByteSize;
1971 case MVT::i64: // PPC64
1972 if (GPR_idx != Num_GPR_Regs) {
1973 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
1974 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
1976 if (ObjectVT == MVT::i32) {
1977 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
1978 // value to MVT::i64 and then truncate to the correct register size.
1980 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
1981 DAG.getValueType(ObjectVT));
1982 else if (Flags.isZExt())
1983 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
1984 DAG.getValueType(ObjectVT));
1986 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, ArgVal);
1992 ArgSize = PtrByteSize;
1994 // All int arguments reserve stack space in the Darwin ABI.
2000 // Every 4 bytes of argument space consumes one of the GPRs available for
2001 // argument passing.
2002 if (GPR_idx != Num_GPR_Regs) {
2004 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2007 if (FPR_idx != Num_FPR_Regs) {
2010 if (ObjectVT == MVT::f32)
2011 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2013 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2015 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2021 // All FP arguments reserve stack space in the Darwin ABI.
2022 ArgOffset += isPPC64 ? 8 : ObjSize;
2028 // Note that vector arguments in registers don't reserve stack space,
2029 // except in varargs functions.
2030 if (VR_idx != Num_VR_Regs) {
2031 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2032 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2034 while ((ArgOffset % 16) != 0) {
2035 ArgOffset += PtrByteSize;
2036 if (GPR_idx != Num_GPR_Regs)
2040 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
2044 if (!isVarArg && !isPPC64) {
2045 // Vectors go after all the nonvectors.
2046 CurArgOffset = VecArgOffset;
2049 // Vectors are aligned.
2050 ArgOffset = ((ArgOffset+15)/16)*16;
2051 CurArgOffset = ArgOffset;
2059 // We need to load the argument to a virtual register if we determined above
2060 // that we ran out of physical registers of the appropriate type.
2062 int FI = MFI->CreateFixedObject(ObjSize,
2063 CurArgOffset + (ArgSize - ObjSize),
2065 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2066 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, NULL, 0,
2070 InVals.push_back(ArgVal);
2073 // Set the size that is at least reserved in caller of this function. Tail
2074 // call optimized function's reserved stack space needs to be aligned so that
2075 // taking the difference between two stack areas will result in an aligned
2077 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2078 // Add the Altivec parameters at the end, if needed.
2079 if (nAltivecParamsAtEnd) {
2080 MinReservedArea = ((MinReservedArea+15)/16)*16;
2081 MinReservedArea += 16*nAltivecParamsAtEnd;
2084 std::max(MinReservedArea,
2085 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2086 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2087 getStackAlignment();
2088 unsigned AlignMask = TargetAlign-1;
2089 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2090 FI->setMinReservedArea(MinReservedArea);
2092 // If the function takes variable number of arguments, make a frame index for
2093 // the start of the first vararg value... for expansion of llvm.va_start.
2095 int Depth = ArgOffset;
2097 FuncInfo->setVarArgsFrameIndex(
2098 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2100 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2102 // If this function is vararg, store any remaining integer argument regs
2103 // to their spots on the stack so that they may be loaded by deferencing the
2104 // result of va_next.
2105 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2109 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2111 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2113 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2114 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
2116 MemOps.push_back(Store);
2117 // Increment the address by four for the next argument to store
2118 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2119 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2123 if (!MemOps.empty())
2124 Chain = DAG.getNode(ISD::TokenFactor, dl,
2125 MVT::Other, &MemOps[0], MemOps.size());
2130 /// CalculateParameterAndLinkageAreaSize - Get the size of the paramter plus
2131 /// linkage area for the Darwin ABI.
2133 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
2137 const SmallVectorImpl<ISD::OutputArg>
2139 const SmallVectorImpl<SDValue> &OutVals,
2140 unsigned &nAltivecParamsAtEnd) {
2141 // Count how many bytes are to be pushed on the stack, including the linkage
2142 // area, and parameter passing area. We start with 24/48 bytes, which is
2143 // prereserved space for [SP][CR][LR][3 x unused].
2144 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, true);
2145 unsigned NumOps = Outs.size();
2146 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2148 // Add up all the space actually used.
2149 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
2150 // they all go in registers, but we must reserve stack space for them for
2151 // possible use by the caller. In varargs or 64-bit calls, parameters are
2152 // assigned stack space in order, with padding so Altivec parameters are
2154 nAltivecParamsAtEnd = 0;
2155 for (unsigned i = 0; i != NumOps; ++i) {
2156 SDValue Arg = OutVals[i];
2157 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2158 EVT ArgVT = Outs[i].VT;
2159 // Varargs Altivec parameters are padded to a 16 byte boundary.
2160 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
2161 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8) {
2162 if (!isVarArg && !isPPC64) {
2163 // Non-varargs Altivec parameters go after all the non-Altivec
2164 // parameters; handle those later so we know how much padding we need.
2165 nAltivecParamsAtEnd++;
2168 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
2169 NumBytes = ((NumBytes+15)/16)*16;
2171 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
2174 // Allow for Altivec parameters at the end, if needed.
2175 if (nAltivecParamsAtEnd) {
2176 NumBytes = ((NumBytes+15)/16)*16;
2177 NumBytes += 16*nAltivecParamsAtEnd;
2180 // The prolog code of the callee may store up to 8 GPR argument registers to
2181 // the stack, allowing va_start to index over them in memory if its varargs.
2182 // Because we cannot tell if this is needed on the caller side, we have to
2183 // conservatively assume that it is needed. As such, make sure we have at
2184 // least enough stack space for the caller to store the 8 GPRs.
2185 NumBytes = std::max(NumBytes,
2186 PPCFrameInfo::getMinCallFrameSize(isPPC64, true));
2188 // Tail call needs the stack to be aligned.
2189 if (CC==CallingConv::Fast && GuaranteedTailCallOpt) {
2190 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameInfo()->
2191 getStackAlignment();
2192 unsigned AlignMask = TargetAlign-1;
2193 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
2199 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
2200 /// adjusted to accomodate the arguments for the tailcall.
2201 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
2202 unsigned ParamSize) {
2204 if (!isTailCall) return 0;
2206 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
2207 unsigned CallerMinReservedArea = FI->getMinReservedArea();
2208 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
2209 // Remember only if the new adjustement is bigger.
2210 if (SPDiff < FI->getTailCallSPDelta())
2211 FI->setTailCallSPDelta(SPDiff);
2216 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
2217 /// for tail call optimization. Targets which want to do tail call
2218 /// optimization should implement this function.
2220 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
2221 CallingConv::ID CalleeCC,
2223 const SmallVectorImpl<ISD::InputArg> &Ins,
2224 SelectionDAG& DAG) const {
2225 if (!GuaranteedTailCallOpt)
2228 // Variable argument functions are not supported.
2232 MachineFunction &MF = DAG.getMachineFunction();
2233 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
2234 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
2235 // Functions containing by val parameters are not supported.
2236 for (unsigned i = 0; i != Ins.size(); i++) {
2237 ISD::ArgFlagsTy Flags = Ins[i].Flags;
2238 if (Flags.isByVal()) return false;
2241 // Non PIC/GOT tail calls are supported.
2242 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
2245 // At the moment we can only do local tail calls (in same module, hidden
2246 // or protected) if we are generating PIC.
2247 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2248 return G->getGlobal()->hasHiddenVisibility()
2249 || G->getGlobal()->hasProtectedVisibility();
2255 /// isCallCompatibleAddress - Return the immediate to use if the specified
2256 /// 32-bit value is representable in the immediate field of a BxA instruction.
2257 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
2258 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
2261 int Addr = C->getZExtValue();
2262 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
2263 (Addr << 6 >> 6) != Addr)
2264 return 0; // Top 6 bits have to be sext of immediate.
2266 return DAG.getConstant((int)C->getZExtValue() >> 2,
2267 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
2272 struct TailCallArgumentInfo {
2277 TailCallArgumentInfo() : FrameIdx(0) {}
2282 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
2284 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
2286 const SmallVector<TailCallArgumentInfo, 8> &TailCallArgs,
2287 SmallVector<SDValue, 8> &MemOpChains,
2289 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
2290 SDValue Arg = TailCallArgs[i].Arg;
2291 SDValue FIN = TailCallArgs[i].FrameIdxOp;
2292 int FI = TailCallArgs[i].FrameIdx;
2293 // Store relative to framepointer.
2294 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
2295 PseudoSourceValue::getFixedStack(FI),
2296 0, false, false, 0));
2300 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
2301 /// the appropriate stack slot for the tail call optimized function call.
2302 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
2303 MachineFunction &MF,
2312 // Calculate the new stack slot for the return address.
2313 int SlotSize = isPPC64 ? 8 : 4;
2314 int NewRetAddrLoc = SPDiff + PPCFrameInfo::getReturnSaveOffset(isPPC64,
2316 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
2317 NewRetAddrLoc, true);
2318 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2319 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
2320 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
2321 PseudoSourceValue::getFixedStack(NewRetAddr), 0,
2324 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
2325 // slot as the FP is never overwritten.
2328 SPDiff + PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI);
2329 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
2331 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
2332 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
2333 PseudoSourceValue::getFixedStack(NewFPIdx), 0,
2340 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
2341 /// the position of the argument.
2343 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
2344 SDValue Arg, int SPDiff, unsigned ArgOffset,
2345 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments) {
2346 int Offset = ArgOffset + SPDiff;
2347 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
2348 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
2349 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
2350 SDValue FIN = DAG.getFrameIndex(FI, VT);
2351 TailCallArgumentInfo Info;
2353 Info.FrameIdxOp = FIN;
2355 TailCallArguments.push_back(Info);
2358 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
2359 /// stack slot. Returns the chain as result and the loaded frame pointers in
2360 /// LROpOut/FPOpout. Used when tail calling.
2361 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
2367 DebugLoc dl) const {
2369 // Load the LR and FP stack slot for later adjusting.
2370 EVT VT = PPCSubTarget.isPPC64() ? MVT::i64 : MVT::i32;
2371 LROpOut = getReturnAddrFrameIndex(DAG);
2372 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, NULL, 0,
2374 Chain = SDValue(LROpOut.getNode(), 1);
2376 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
2377 // slot as the FP is never overwritten.
2379 FPOpOut = getFramePointerFrameIndex(DAG);
2380 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, NULL, 0,
2382 Chain = SDValue(FPOpOut.getNode(), 1);
2388 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
2389 /// by "Src" to address "Dst" of size "Size". Alignment information is
2390 /// specified by the specific parameter attribute. The copy will be passed as
2391 /// a byval function parameter.
2392 /// Sometimes what we are copying is the end of a larger object, the part that
2393 /// does not fit in registers.
2395 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
2396 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
2398 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
2399 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
2400 false, false, NULL, 0, NULL, 0);
2403 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
2406 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
2407 SDValue Arg, SDValue PtrOff, int SPDiff,
2408 unsigned ArgOffset, bool isPPC64, bool isTailCall,
2409 bool isVector, SmallVector<SDValue, 8> &MemOpChains,
2410 SmallVector<TailCallArgumentInfo, 8>& TailCallArguments,
2412 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2417 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2419 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2420 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
2421 DAG.getConstant(ArgOffset, PtrVT));
2423 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
2425 // Calculate and remember argument location.
2426 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
2431 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
2432 DebugLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
2433 SDValue LROp, SDValue FPOp, bool isDarwinABI,
2434 SmallVector<TailCallArgumentInfo, 8> &TailCallArguments) {
2435 MachineFunction &MF = DAG.getMachineFunction();
2437 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
2438 // might overwrite each other in case of tail call optimization.
2439 SmallVector<SDValue, 8> MemOpChains2;
2440 // Do not flag preceeding copytoreg stuff together with the following stuff.
2442 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
2444 if (!MemOpChains2.empty())
2445 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2446 &MemOpChains2[0], MemOpChains2.size());
2448 // Store the return address to the appropriate stack slot.
2449 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
2450 isPPC64, isDarwinABI, dl);
2452 // Emit callseq_end just before tailcall node.
2453 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2454 DAG.getIntPtrConstant(0, true), InFlag);
2455 InFlag = Chain.getValue(1);
2459 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
2460 SDValue &Chain, DebugLoc dl, int SPDiff, bool isTailCall,
2461 SmallVector<std::pair<unsigned, SDValue>, 8> &RegsToPass,
2462 SmallVector<SDValue, 8> &Ops, std::vector<EVT> &NodeTys,
2463 bool isPPC64, bool isSVR4ABI) {
2464 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2465 NodeTys.push_back(MVT::Other); // Returns a chain
2466 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
2468 unsigned CallOpc = isSVR4ABI ? PPCISD::CALL_SVR4 : PPCISD::CALL_Darwin;
2470 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
2471 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
2472 // node so that legalize doesn't hack it.
2473 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
2474 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
2475 Callee.getValueType());
2476 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
2477 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
2478 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
2479 // If this is an absolute destination address, use the munged value.
2480 Callee = SDValue(Dest, 0);
2482 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
2483 // to do the call, we can't use PPCISD::CALL.
2484 SDValue MTCTROps[] = {Chain, Callee, InFlag};
2486 if (isSVR4ABI && isPPC64) {
2487 // Function pointers in the 64-bit SVR4 ABI do not point to the function
2488 // entry point, but to the function descriptor (the function entry point
2489 // address is part of the function descriptor though).
2490 // The function descriptor is a three doubleword structure with the
2491 // following fields: function entry point, TOC base address and
2492 // environment pointer.
2493 // Thus for a call through a function pointer, the following actions need
2495 // 1. Save the TOC of the caller in the TOC save area of its stack
2496 // frame (this is done in LowerCall_Darwin()).
2497 // 2. Load the address of the function entry point from the function
2499 // 3. Load the TOC of the callee from the function descriptor into r2.
2500 // 4. Load the environment pointer from the function descriptor into
2502 // 5. Branch to the function entry point address.
2503 // 6. On return of the callee, the TOC of the caller needs to be
2504 // restored (this is done in FinishCall()).
2506 // All those operations are flagged together to ensure that no other
2507 // operations can be scheduled in between. E.g. without flagging the
2508 // operations together, a TOC access in the caller could be scheduled
2509 // between the load of the callee TOC and the branch to the callee, which
2510 // results in the TOC access going through the TOC of the callee instead
2511 // of going through the TOC of the caller, which leads to incorrect code.
2513 // Load the address of the function entry point from the function
2515 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Flag);
2516 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, MTCTROps,
2517 InFlag.getNode() ? 3 : 2);
2518 Chain = LoadFuncPtr.getValue(1);
2519 InFlag = LoadFuncPtr.getValue(2);
2521 // Load environment pointer into r11.
2522 // Offset of the environment pointer within the function descriptor.
2523 SDValue PtrOff = DAG.getIntPtrConstant(16);
2525 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
2526 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
2528 Chain = LoadEnvPtr.getValue(1);
2529 InFlag = LoadEnvPtr.getValue(2);
2531 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
2533 Chain = EnvVal.getValue(0);
2534 InFlag = EnvVal.getValue(1);
2536 // Load TOC of the callee into r2. We are using a target-specific load
2537 // with r2 hard coded, because the result of a target-independent load
2538 // would never go directly into r2, since r2 is a reserved register (which
2539 // prevents the register allocator from allocating it), resulting in an
2540 // additional register being allocated and an unnecessary move instruction
2542 VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2543 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
2545 Chain = LoadTOCPtr.getValue(0);
2546 InFlag = LoadTOCPtr.getValue(1);
2548 MTCTROps[0] = Chain;
2549 MTCTROps[1] = LoadFuncPtr;
2550 MTCTROps[2] = InFlag;
2553 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys, MTCTROps,
2554 2 + (InFlag.getNode() != 0));
2555 InFlag = Chain.getValue(1);
2558 NodeTys.push_back(MVT::Other);
2559 NodeTys.push_back(MVT::Flag);
2560 Ops.push_back(Chain);
2561 CallOpc = isSVR4ABI ? PPCISD::BCTRL_SVR4 : PPCISD::BCTRL_Darwin;
2563 // Add CTR register as callee so a bctr can be emitted later.
2565 Ops.push_back(DAG.getRegister(PPC::CTR, PtrVT));
2568 // If this is a direct call, pass the chain and the callee.
2569 if (Callee.getNode()) {
2570 Ops.push_back(Chain);
2571 Ops.push_back(Callee);
2573 // If this is a tail call add stack pointer delta.
2575 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
2577 // Add argument registers to the end of the list so that they are known live
2579 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
2580 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
2581 RegsToPass[i].second.getValueType()));
2587 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
2588 CallingConv::ID CallConv, bool isVarArg,
2589 const SmallVectorImpl<ISD::InputArg> &Ins,
2590 DebugLoc dl, SelectionDAG &DAG,
2591 SmallVectorImpl<SDValue> &InVals) const {
2593 SmallVector<CCValAssign, 16> RVLocs;
2594 CCState CCRetInfo(CallConv, isVarArg, getTargetMachine(),
2595 RVLocs, *DAG.getContext());
2596 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2598 // Copy all of the result registers out of their specified physreg.
2599 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
2600 CCValAssign &VA = RVLocs[i];
2601 EVT VT = VA.getValVT();
2602 assert(VA.isRegLoc() && "Can only return in registers!");
2603 Chain = DAG.getCopyFromReg(Chain, dl,
2604 VA.getLocReg(), VT, InFlag).getValue(1);
2605 InVals.push_back(Chain.getValue(0));
2606 InFlag = Chain.getValue(2);
2613 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
2614 bool isTailCall, bool isVarArg,
2616 SmallVector<std::pair<unsigned, SDValue>, 8>
2618 SDValue InFlag, SDValue Chain,
2620 int SPDiff, unsigned NumBytes,
2621 const SmallVectorImpl<ISD::InputArg> &Ins,
2622 SmallVectorImpl<SDValue> &InVals) const {
2623 std::vector<EVT> NodeTys;
2624 SmallVector<SDValue, 8> Ops;
2625 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
2626 isTailCall, RegsToPass, Ops, NodeTys,
2627 PPCSubTarget.isPPC64(),
2628 PPCSubTarget.isSVR4ABI());
2630 // When performing tail call optimization the callee pops its arguments off
2631 // the stack. Account for this here so these bytes can be pushed back on in
2632 // PPCRegisterInfo::eliminateCallFramePseudoInstr.
2633 int BytesCalleePops =
2634 (CallConv==CallingConv::Fast && GuaranteedTailCallOpt) ? NumBytes : 0;
2636 if (InFlag.getNode())
2637 Ops.push_back(InFlag);
2641 // If this is the first return lowered for this function, add the regs
2642 // to the liveout set for the function.
2643 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
2644 SmallVector<CCValAssign, 16> RVLocs;
2645 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
2647 CCInfo.AnalyzeCallResult(Ins, RetCC_PPC);
2648 for (unsigned i = 0; i != RVLocs.size(); ++i)
2649 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
2652 assert(((Callee.getOpcode() == ISD::Register &&
2653 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
2654 Callee.getOpcode() == ISD::TargetExternalSymbol ||
2655 Callee.getOpcode() == ISD::TargetGlobalAddress ||
2656 isa<ConstantSDNode>(Callee)) &&
2657 "Expecting an global address, external symbol, absolute value or register");
2659 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, &Ops[0], Ops.size());
2662 Chain = DAG.getNode(CallOpc, dl, NodeTys, &Ops[0], Ops.size());
2663 InFlag = Chain.getValue(1);
2665 // Add a NOP immediately after the branch instruction when using the 64-bit
2666 // SVR4 ABI. At link time, if caller and callee are in a different module and
2667 // thus have a different TOC, the call will be replaced with a call to a stub
2668 // function which saves the current TOC, loads the TOC of the callee and
2669 // branches to the callee. The NOP will be replaced with a load instruction
2670 // which restores the TOC of the caller from the TOC save slot of the current
2671 // stack frame. If caller and callee belong to the same module (and have the
2672 // same TOC), the NOP will remain unchanged.
2673 if (!isTailCall && PPCSubTarget.isSVR4ABI()&& PPCSubTarget.isPPC64()) {
2674 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Flag);
2675 if (CallOpc == PPCISD::BCTRL_SVR4) {
2676 // This is a call through a function pointer.
2677 // Restore the caller TOC from the save area into R2.
2678 // See PrepareCall() for more information about calls through function
2679 // pointers in the 64-bit SVR4 ABI.
2680 // We are using a target-specific load with r2 hard coded, because the
2681 // result of a target-independent load would never go directly into r2,
2682 // since r2 is a reserved register (which prevents the register allocator
2683 // from allocating it), resulting in an additional register being
2684 // allocated and an unnecessary move instruction being generated.
2685 Chain = DAG.getNode(PPCISD::TOC_RESTORE, dl, VTs, Chain, InFlag);
2686 InFlag = Chain.getValue(1);
2688 // Otherwise insert NOP.
2689 InFlag = DAG.getNode(PPCISD::NOP, dl, MVT::Flag, InFlag);
2693 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
2694 DAG.getIntPtrConstant(BytesCalleePops, true),
2697 InFlag = Chain.getValue(1);
2699 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
2700 Ins, dl, DAG, InVals);
2704 PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
2705 CallingConv::ID CallConv, bool isVarArg,
2707 const SmallVectorImpl<ISD::OutputArg> &Outs,
2708 const SmallVectorImpl<SDValue> &OutVals,
2709 const SmallVectorImpl<ISD::InputArg> &Ins,
2710 DebugLoc dl, SelectionDAG &DAG,
2711 SmallVectorImpl<SDValue> &InVals) const {
2713 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
2716 if (PPCSubTarget.isSVR4ABI() && !PPCSubTarget.isPPC64()) {
2717 return LowerCall_SVR4(Chain, Callee, CallConv, isVarArg,
2718 isTailCall, Outs, OutVals, Ins,
2721 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
2722 isTailCall, Outs, OutVals, Ins,
2728 PPCTargetLowering::LowerCall_SVR4(SDValue Chain, SDValue Callee,
2729 CallingConv::ID CallConv, bool isVarArg,
2731 const SmallVectorImpl<ISD::OutputArg> &Outs,
2732 const SmallVectorImpl<SDValue> &OutVals,
2733 const SmallVectorImpl<ISD::InputArg> &Ins,
2734 DebugLoc dl, SelectionDAG &DAG,
2735 SmallVectorImpl<SDValue> &InVals) const {
2736 // See PPCTargetLowering::LowerFormalArguments_SVR4() for a description
2737 // of the 32-bit SVR4 ABI stack frame layout.
2739 assert((CallConv == CallingConv::C ||
2740 CallConv == CallingConv::Fast) && "Unknown calling convention!");
2742 unsigned PtrByteSize = 4;
2744 MachineFunction &MF = DAG.getMachineFunction();
2746 // Mark this function as potentially containing a function that contains a
2747 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2748 // and restoring the callers stack pointer in this functions epilog. This is
2749 // done because by tail calling the called function might overwrite the value
2750 // in this function's (MF) stack pointer stack slot 0(SP).
2751 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2752 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2754 // Count how many bytes are to be pushed on the stack, including the linkage
2755 // area, parameter list area and the part of the local variable space which
2756 // contains copies of aggregates which are passed by value.
2758 // Assign locations to all of the outgoing arguments.
2759 SmallVector<CCValAssign, 16> ArgLocs;
2760 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
2761 ArgLocs, *DAG.getContext());
2763 // Reserve space for the linkage area on the stack.
2764 CCInfo.AllocateStack(PPCFrameInfo::getLinkageSize(false, false), PtrByteSize);
2767 // Handle fixed and variable vector arguments differently.
2768 // Fixed vector arguments go into registers as long as registers are
2769 // available. Variable vector arguments always go into memory.
2770 unsigned NumArgs = Outs.size();
2772 for (unsigned i = 0; i != NumArgs; ++i) {
2773 EVT ArgVT = Outs[i].VT;
2774 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
2777 if (Outs[i].IsFixed) {
2778 Result = CC_PPC_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
2781 Result = CC_PPC_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
2787 errs() << "Call operand #" << i << " has unhandled type "
2788 << ArgVT.getEVTString() << "\n";
2790 llvm_unreachable(0);
2794 // All arguments are treated the same.
2795 CCInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4);
2798 // Assign locations to all of the outgoing aggregate by value arguments.
2799 SmallVector<CCValAssign, 16> ByValArgLocs;
2800 CCState CCByValInfo(CallConv, isVarArg, getTargetMachine(), ByValArgLocs,
2803 // Reserve stack space for the allocations in CCInfo.
2804 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2806 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC_SVR4_ByVal);
2808 // Size of the linkage area, parameter list area and the part of the local
2809 // space variable where copies of aggregates which are passed by value are
2811 unsigned NumBytes = CCByValInfo.getNextStackOffset();
2813 // Calculate by how many bytes the stack has to be adjusted in case of tail
2814 // call optimization.
2815 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2817 // Adjust the stack pointer for the new arguments...
2818 // These operations are automatically eliminated by the prolog/epilog pass
2819 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2820 SDValue CallSeqStart = Chain;
2822 // Load the return address and frame pointer so it can be moved somewhere else
2825 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
2828 // Set up a copy of the stack pointer for use loading and storing any
2829 // arguments that may not fit in the registers available for argument
2831 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2833 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
2834 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
2835 SmallVector<SDValue, 8> MemOpChains;
2837 // Walk the register/memloc assignments, inserting copies/loads.
2838 for (unsigned i = 0, j = 0, e = ArgLocs.size();
2841 CCValAssign &VA = ArgLocs[i];
2842 SDValue Arg = OutVals[i];
2843 ISD::ArgFlagsTy Flags = Outs[i].Flags;
2845 if (Flags.isByVal()) {
2846 // Argument is an aggregate which is passed by value, thus we need to
2847 // create a copy of it in the local variable space of the current stack
2848 // frame (which is the stack frame of the caller) and pass the address of
2849 // this copy to the callee.
2850 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
2851 CCValAssign &ByValVA = ByValArgLocs[j++];
2852 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
2854 // Memory reserved in the local variable space of the callers stack frame.
2855 unsigned LocMemOffset = ByValVA.getLocMemOffset();
2857 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2858 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2860 // Create a copy of the argument in the local area of the current
2862 SDValue MemcpyCall =
2863 CreateCopyOfByValArgument(Arg, PtrOff,
2864 CallSeqStart.getNode()->getOperand(0),
2867 // This must go outside the CALLSEQ_START..END.
2868 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
2869 CallSeqStart.getNode()->getOperand(1));
2870 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
2871 NewCallSeqStart.getNode());
2872 Chain = CallSeqStart = NewCallSeqStart;
2874 // Pass the address of the aggregate copy on the stack either in a
2875 // physical register or in the parameter list area of the current stack
2876 // frame to the callee.
2880 if (VA.isRegLoc()) {
2881 // Put argument in a physical register.
2882 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
2884 // Put argument in the parameter list area of the current stack frame.
2885 assert(VA.isMemLoc());
2886 unsigned LocMemOffset = VA.getLocMemOffset();
2889 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
2890 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
2892 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
2893 PseudoSourceValue::getStack(), LocMemOffset,
2896 // Calculate and remember argument location.
2897 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
2903 if (!MemOpChains.empty())
2904 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
2905 &MemOpChains[0], MemOpChains.size());
2907 // Build a sequence of copy-to-reg nodes chained together with token chain
2908 // and flag operands which copy the outgoing args into the appropriate regs.
2910 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
2911 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
2912 RegsToPass[i].second, InFlag);
2913 InFlag = Chain.getValue(1);
2916 // Set CR6 to true if this is a vararg call.
2918 SDValue SetCR(DAG.getMachineNode(PPC::CRSET, dl, MVT::i32), 0);
2919 Chain = DAG.getCopyToReg(Chain, dl, PPC::CR1EQ, SetCR, InFlag);
2920 InFlag = Chain.getValue(1);
2924 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
2925 false, TailCallArguments);
2928 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
2929 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
2934 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
2935 CallingConv::ID CallConv, bool isVarArg,
2937 const SmallVectorImpl<ISD::OutputArg> &Outs,
2938 const SmallVectorImpl<SDValue> &OutVals,
2939 const SmallVectorImpl<ISD::InputArg> &Ins,
2940 DebugLoc dl, SelectionDAG &DAG,
2941 SmallVectorImpl<SDValue> &InVals) const {
2943 unsigned NumOps = Outs.size();
2945 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2946 bool isPPC64 = PtrVT == MVT::i64;
2947 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2949 MachineFunction &MF = DAG.getMachineFunction();
2951 // Mark this function as potentially containing a function that contains a
2952 // tail call. As a consequence the frame pointer will be used for dynamicalloc
2953 // and restoring the callers stack pointer in this functions epilog. This is
2954 // done because by tail calling the called function might overwrite the value
2955 // in this function's (MF) stack pointer stack slot 0(SP).
2956 if (GuaranteedTailCallOpt && CallConv==CallingConv::Fast)
2957 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
2959 unsigned nAltivecParamsAtEnd = 0;
2961 // Count how many bytes are to be pushed on the stack, including the linkage
2962 // area, and parameter passing area. We start with 24/48 bytes, which is
2963 // prereserved space for [SP][CR][LR][3 x unused].
2965 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
2967 nAltivecParamsAtEnd);
2969 // Calculate by how many bytes the stack has to be adjusted in case of tail
2970 // call optimization.
2971 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
2973 // To protect arguments on the stack from being clobbered in a tail call,
2974 // force all the loads to happen before doing any other lowering.
2976 Chain = DAG.getStackArgumentTokenFactor(Chain);
2978 // Adjust the stack pointer for the new arguments...
2979 // These operations are automatically eliminated by the prolog/epilog pass
2980 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
2981 SDValue CallSeqStart = Chain;
2983 // Load the return address and frame pointer so it can be move somewhere else
2986 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
2989 // Set up a copy of the stack pointer for use loading and storing any
2990 // arguments that may not fit in the registers available for argument
2994 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
2996 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
2998 // Figure out which arguments are going to go in registers, and which in
2999 // memory. Also, if this is a vararg function, floating point operations
3000 // must be stored to our stack, and loaded into integer regs as well, if
3001 // any integer regs are available for argument passing.
3002 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, true);
3003 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
3005 static const unsigned GPR_32[] = { // 32-bit registers.
3006 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
3007 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
3009 static const unsigned GPR_64[] = { // 64-bit registers.
3010 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
3011 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
3013 static const unsigned *FPR = GetFPR();
3015 static const unsigned VR[] = {
3016 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
3017 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
3019 const unsigned NumGPRs = array_lengthof(GPR_32);
3020 const unsigned NumFPRs = 13;
3021 const unsigned NumVRs = array_lengthof(VR);
3023 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
3025 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3026 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3028 SmallVector<SDValue, 8> MemOpChains;
3029 for (unsigned i = 0; i != NumOps; ++i) {
3030 SDValue Arg = OutVals[i];
3031 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3033 // PtrOff will be used to store the current argument to the stack if a
3034 // register cannot be found for it.
3037 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
3039 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3041 // On PPC64, promote integers to 64-bit values.
3042 if (isPPC64 && Arg.getValueType() == MVT::i32) {
3043 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
3044 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3045 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
3048 // FIXME memcpy is used way more than necessary. Correctness first.
3049 if (Flags.isByVal()) {
3050 unsigned Size = Flags.getByValSize();
3051 if (Size==1 || Size==2) {
3052 // Very small objects are passed right-justified.
3053 // Everything else is passed left-justified.
3054 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
3055 if (GPR_idx != NumGPRs) {
3056 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, PtrVT, dl, Chain, Arg,
3057 NULL, 0, VT, false, false, 0);
3058 MemOpChains.push_back(Load.getValue(1));
3059 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3061 ArgOffset += PtrByteSize;
3063 SDValue Const = DAG.getConstant(4 - Size, PtrOff.getValueType());
3064 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
3065 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, AddPtr,
3066 CallSeqStart.getNode()->getOperand(0),
3068 // This must go outside the CALLSEQ_START..END.
3069 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3070 CallSeqStart.getNode()->getOperand(1));
3071 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3072 NewCallSeqStart.getNode());
3073 Chain = CallSeqStart = NewCallSeqStart;
3074 ArgOffset += PtrByteSize;
3078 // Copy entire object into memory. There are cases where gcc-generated
3079 // code assumes it is there, even if it could be put entirely into
3080 // registers. (This is not what the doc says.)
3081 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
3082 CallSeqStart.getNode()->getOperand(0),
3084 // This must go outside the CALLSEQ_START..END.
3085 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3086 CallSeqStart.getNode()->getOperand(1));
3087 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(), NewCallSeqStart.getNode());
3088 Chain = CallSeqStart = NewCallSeqStart;
3089 // And copy the pieces of it that fit into registers.
3090 for (unsigned j=0; j<Size; j+=PtrByteSize) {
3091 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
3092 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
3093 if (GPR_idx != NumGPRs) {
3094 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg, NULL, 0,
3096 MemOpChains.push_back(Load.getValue(1));
3097 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3098 ArgOffset += PtrByteSize;
3100 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
3107 switch (Arg.getValueType().getSimpleVT().SimpleTy) {
3108 default: llvm_unreachable("Unexpected ValueType for argument!");
3111 if (GPR_idx != NumGPRs) {
3112 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
3114 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3115 isPPC64, isTailCall, false, MemOpChains,
3116 TailCallArguments, dl);
3118 ArgOffset += PtrByteSize;
3122 if (FPR_idx != NumFPRs) {
3123 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
3126 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
3128 MemOpChains.push_back(Store);
3130 // Float varargs are always shadowed in available integer registers
3131 if (GPR_idx != NumGPRs) {
3132 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0,
3134 MemOpChains.push_back(Load.getValue(1));
3135 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3137 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
3138 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
3139 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
3140 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff, NULL, 0,
3142 MemOpChains.push_back(Load.getValue(1));
3143 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3146 // If we have any FPRs remaining, we may also have GPRs remaining.
3147 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
3149 if (GPR_idx != NumGPRs)
3151 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
3152 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
3156 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3157 isPPC64, isTailCall, false, MemOpChains,
3158 TailCallArguments, dl);
3163 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
3170 // These go aligned on the stack, or in the corresponding R registers
3171 // when within range. The Darwin PPC ABI doc claims they also go in
3172 // V registers; in fact gcc does this only for arguments that are
3173 // prototyped, not for those that match the ... We do it for all
3174 // arguments, seems to work.
3175 while (ArgOffset % 16 !=0) {
3176 ArgOffset += PtrByteSize;
3177 if (GPR_idx != NumGPRs)
3180 // We could elide this store in the case where the object fits
3181 // entirely in R registers. Maybe later.
3182 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3183 DAG.getConstant(ArgOffset, PtrVT));
3184 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff, NULL, 0,
3186 MemOpChains.push_back(Store);
3187 if (VR_idx != NumVRs) {
3188 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff, NULL, 0,
3190 MemOpChains.push_back(Load.getValue(1));
3191 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
3194 for (unsigned i=0; i<16; i+=PtrByteSize) {
3195 if (GPR_idx == NumGPRs)
3197 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
3198 DAG.getConstant(i, PtrVT));
3199 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, NULL, 0,
3201 MemOpChains.push_back(Load.getValue(1));
3202 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
3207 // Non-varargs Altivec params generally go in registers, but have
3208 // stack space allocated at the end.
3209 if (VR_idx != NumVRs) {
3210 // Doesn't have GPR space allocated.
3211 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
3212 } else if (nAltivecParamsAtEnd==0) {
3213 // We are emitting Altivec params in order.
3214 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3215 isPPC64, isTailCall, true, MemOpChains,
3216 TailCallArguments, dl);
3222 // If all Altivec parameters fit in registers, as they usually do,
3223 // they get stack space following the non-Altivec parameters. We
3224 // don't track this here because nobody below needs it.
3225 // If there are more Altivec parameters than fit in registers emit
3227 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
3229 // Offset is aligned; skip 1st 12 params which go in V registers.
3230 ArgOffset = ((ArgOffset+15)/16)*16;
3232 for (unsigned i = 0; i != NumOps; ++i) {
3233 SDValue Arg = OutVals[i];
3234 EVT ArgType = Outs[i].VT;
3235 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
3236 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
3239 // We are emitting Altivec params in order.
3240 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
3241 isPPC64, isTailCall, true, MemOpChains,
3242 TailCallArguments, dl);
3249 if (!MemOpChains.empty())
3250 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
3251 &MemOpChains[0], MemOpChains.size());
3253 // Check if this is an indirect call (MTCTR/BCTRL).
3254 // See PrepareCall() for more information about calls through function
3255 // pointers in the 64-bit SVR4 ABI.
3256 if (!isTailCall && isPPC64 && PPCSubTarget.isSVR4ABI() &&
3257 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3258 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3259 !isBLACompatibleAddress(Callee, DAG)) {
3260 // Load r2 into a virtual register and store it to the TOC save area.
3261 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
3262 // TOC save area offset.
3263 SDValue PtrOff = DAG.getIntPtrConstant(40);
3264 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
3265 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, NULL, 0,
3269 // On Darwin, R12 must contain the address of an indirect callee. This does
3270 // not mean the MTCTR instruction must use R12; it's easier to model this as
3271 // an extra parameter, so do that.
3273 !dyn_cast<GlobalAddressSDNode>(Callee) &&
3274 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
3275 !isBLACompatibleAddress(Callee, DAG))
3276 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
3277 PPC::R12), Callee));
3279 // Build a sequence of copy-to-reg nodes chained together with token chain
3280 // and flag operands which copy the outgoing args into the appropriate regs.
3282 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3283 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3284 RegsToPass[i].second, InFlag);
3285 InFlag = Chain.getValue(1);
3289 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
3290 FPOp, true, TailCallArguments);
3293 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3294 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3299 PPCTargetLowering::LowerReturn(SDValue Chain,
3300 CallingConv::ID CallConv, bool isVarArg,
3301 const SmallVectorImpl<ISD::OutputArg> &Outs,
3302 const SmallVectorImpl<SDValue> &OutVals,
3303 DebugLoc dl, SelectionDAG &DAG) const {
3305 SmallVector<CCValAssign, 16> RVLocs;
3306 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
3307 RVLocs, *DAG.getContext());
3308 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
3310 // If this is the first return lowered for this function, add the regs to the
3311 // liveout set for the function.
3312 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
3313 for (unsigned i = 0; i != RVLocs.size(); ++i)
3314 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
3319 // Copy the result values into the output registers.
3320 for (unsigned i = 0; i != RVLocs.size(); ++i) {
3321 CCValAssign &VA = RVLocs[i];
3322 assert(VA.isRegLoc() && "Can only return in registers!");
3323 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
3325 Flag = Chain.getValue(1);
3329 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
3331 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, Chain);
3334 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
3335 const PPCSubtarget &Subtarget) const {
3336 // When we pop the dynamic allocation we need to restore the SP link.
3337 DebugLoc dl = Op.getDebugLoc();
3339 // Get the corect type for pointers.
3340 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3342 // Construct the stack pointer operand.
3343 bool isPPC64 = Subtarget.isPPC64();
3344 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
3345 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
3347 // Get the operands for the STACKRESTORE.
3348 SDValue Chain = Op.getOperand(0);
3349 SDValue SaveSP = Op.getOperand(1);
3351 // Load the old link SP.
3352 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr, NULL, 0,
3355 // Restore the stack pointer.
3356 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
3358 // Store the old link SP.
3359 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, NULL, 0,
3366 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
3367 MachineFunction &MF = DAG.getMachineFunction();
3368 bool isPPC64 = PPCSubTarget.isPPC64();
3369 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3370 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3372 // Get current frame pointer save index. The users of this index will be
3373 // primarily DYNALLOC instructions.
3374 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3375 int RASI = FI->getReturnAddrSaveIndex();
3377 // If the frame pointer save index hasn't been defined yet.
3379 // Find out what the fix offset of the frame pointer save area.
3380 int LROffset = PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI);
3381 // Allocate the frame index for frame pointer save area.
3382 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
3384 FI->setReturnAddrSaveIndex(RASI);
3386 return DAG.getFrameIndex(RASI, PtrVT);
3390 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
3391 MachineFunction &MF = DAG.getMachineFunction();
3392 bool isPPC64 = PPCSubTarget.isPPC64();
3393 bool isDarwinABI = PPCSubTarget.isDarwinABI();
3394 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3396 // Get current frame pointer save index. The users of this index will be
3397 // primarily DYNALLOC instructions.
3398 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
3399 int FPSI = FI->getFramePointerSaveIndex();
3401 // If the frame pointer save index hasn't been defined yet.
3403 // Find out what the fix offset of the frame pointer save area.
3404 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64,
3407 // Allocate the frame index for frame pointer save area.
3408 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
3410 FI->setFramePointerSaveIndex(FPSI);
3412 return DAG.getFrameIndex(FPSI, PtrVT);
3415 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
3417 const PPCSubtarget &Subtarget) const {
3419 SDValue Chain = Op.getOperand(0);
3420 SDValue Size = Op.getOperand(1);
3421 DebugLoc dl = Op.getDebugLoc();
3423 // Get the corect type for pointers.
3424 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3426 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
3427 DAG.getConstant(0, PtrVT), Size);
3428 // Construct a node for the frame pointer save index.
3429 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
3430 // Build a DYNALLOC node.
3431 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
3432 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
3433 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops, 3);
3436 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
3438 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
3439 // Not FP? Not a fsel.
3440 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
3441 !Op.getOperand(2).getValueType().isFloatingPoint())
3444 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
3446 // Cannot handle SETEQ/SETNE.
3447 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op;
3449 EVT ResVT = Op.getValueType();
3450 EVT CmpVT = Op.getOperand(0).getValueType();
3451 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3452 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
3453 DebugLoc dl = Op.getDebugLoc();
3455 // If the RHS of the comparison is a 0.0, we don't need to do the
3456 // subtraction at all.
3457 if (isFloatingPointZero(RHS))
3459 default: break; // SETUO etc aren't handled by fsel.
3462 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3465 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3466 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3467 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
3470 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
3473 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
3474 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
3475 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
3476 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
3481 default: break; // SETUO etc aren't handled by fsel.
3484 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3485 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3486 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3487 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3490 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
3491 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3492 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3493 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3496 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3497 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3498 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3499 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
3502 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
3503 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
3504 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
3505 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
3510 // FIXME: Split this code up when LegalizeDAGTypes lands.
3511 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
3512 DebugLoc dl) const {
3513 assert(Op.getOperand(0).getValueType().isFloatingPoint());
3514 SDValue Src = Op.getOperand(0);
3515 if (Src.getValueType() == MVT::f32)
3516 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
3519 switch (Op.getValueType().getSimpleVT().SimpleTy) {
3520 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
3522 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
3527 Tmp = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Src);
3531 // Convert the FP value to an int value through memory.
3532 SDValue FIPtr = DAG.CreateStackTemporary(MVT::f64);
3534 // Emit a store to the stack slot.
3535 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr, NULL, 0,
3538 // Result is a load from the stack slot. If loading 4 bytes, make sure to
3540 if (Op.getValueType() == MVT::i32)
3541 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
3542 DAG.getConstant(4, FIPtr.getValueType()));
3543 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, NULL, 0,
3547 SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op,
3548 SelectionDAG &DAG) const {
3549 DebugLoc dl = Op.getDebugLoc();
3550 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
3551 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
3554 if (Op.getOperand(0).getValueType() == MVT::i64) {
3555 SDValue Bits = DAG.getNode(ISD::BIT_CONVERT, dl,
3556 MVT::f64, Op.getOperand(0));
3557 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Bits);
3558 if (Op.getValueType() == MVT::f32)
3559 FP = DAG.getNode(ISD::FP_ROUND, dl,
3560 MVT::f32, FP, DAG.getIntPtrConstant(0));
3564 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
3565 "Unhandled SINT_TO_FP type in custom expander!");
3566 // Since we only generate this in 64-bit mode, we can take advantage of
3567 // 64-bit registers. In particular, sign extend the input value into the
3568 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
3569 // then lfd it and fcfid it.
3570 MachineFunction &MF = DAG.getMachineFunction();
3571 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
3572 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
3573 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3574 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3576 SDValue Ext64 = DAG.getNode(PPCISD::EXTSW_32, dl, MVT::i32,
3579 // STD the extended value into the stack slot.
3580 MachineMemOperand *MMO =
3581 MF.getMachineMemOperand(PseudoSourceValue::getFixedStack(FrameIdx),
3582 MachineMemOperand::MOStore, 0, 8, 8);
3583 SDValue Ops[] = { DAG.getEntryNode(), Ext64, FIdx };
3585 DAG.getMemIntrinsicNode(PPCISD::STD_32, dl, DAG.getVTList(MVT::Other),
3586 Ops, 4, MVT::i64, MMO);
3587 // Load the value as a double.
3588 SDValue Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx, NULL, 0, false, false, 0);
3590 // FCFID it and return it.
3591 SDValue FP = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Ld);
3592 if (Op.getValueType() == MVT::f32)
3593 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
3597 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
3598 SelectionDAG &DAG) const {
3599 DebugLoc dl = Op.getDebugLoc();
3601 The rounding mode is in bits 30:31 of FPSR, and has the following
3608 FLT_ROUNDS, on the other hand, expects the following:
3615 To perform the conversion, we do:
3616 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
3619 MachineFunction &MF = DAG.getMachineFunction();
3620 EVT VT = Op.getValueType();
3621 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3622 std::vector<EVT> NodeTys;
3623 SDValue MFFSreg, InFlag;
3625 // Save FP Control Word to register
3626 NodeTys.push_back(MVT::f64); // return register
3627 NodeTys.push_back(MVT::Flag); // unused in this context
3628 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
3630 // Save FP register to stack slot
3631 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
3632 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
3633 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
3634 StackSlot, NULL, 0, false, false, 0);
3636 // Load FP Control Word from low 32 bits of stack slot.
3637 SDValue Four = DAG.getConstant(4, PtrVT);
3638 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
3639 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, NULL, 0,
3642 // Transform as necessary
3644 DAG.getNode(ISD::AND, dl, MVT::i32,
3645 CWD, DAG.getConstant(3, MVT::i32));
3647 DAG.getNode(ISD::SRL, dl, MVT::i32,
3648 DAG.getNode(ISD::AND, dl, MVT::i32,
3649 DAG.getNode(ISD::XOR, dl, MVT::i32,
3650 CWD, DAG.getConstant(3, MVT::i32)),
3651 DAG.getConstant(3, MVT::i32)),
3652 DAG.getConstant(1, MVT::i32));
3655 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
3657 return DAG.getNode((VT.getSizeInBits() < 16 ?
3658 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
3661 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3662 EVT VT = Op.getValueType();
3663 unsigned BitWidth = VT.getSizeInBits();
3664 DebugLoc dl = Op.getDebugLoc();
3665 assert(Op.getNumOperands() == 3 &&
3666 VT == Op.getOperand(1).getValueType() &&
3669 // Expand into a bunch of logical ops. Note that these ops
3670 // depend on the PPC behavior for oversized shift amounts.
3671 SDValue Lo = Op.getOperand(0);
3672 SDValue Hi = Op.getOperand(1);
3673 SDValue Amt = Op.getOperand(2);
3674 EVT AmtVT = Amt.getValueType();
3676 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3677 DAG.getConstant(BitWidth, AmtVT), Amt);
3678 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
3679 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
3680 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
3681 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3682 DAG.getConstant(-BitWidth, AmtVT));
3683 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
3684 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3685 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
3686 SDValue OutOps[] = { OutLo, OutHi };
3687 return DAG.getMergeValues(OutOps, 2, dl);
3690 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
3691 EVT VT = Op.getValueType();
3692 DebugLoc dl = Op.getDebugLoc();
3693 unsigned BitWidth = VT.getSizeInBits();
3694 assert(Op.getNumOperands() == 3 &&
3695 VT == Op.getOperand(1).getValueType() &&
3698 // Expand into a bunch of logical ops. Note that these ops
3699 // depend on the PPC behavior for oversized shift amounts.
3700 SDValue Lo = Op.getOperand(0);
3701 SDValue Hi = Op.getOperand(1);
3702 SDValue Amt = Op.getOperand(2);
3703 EVT AmtVT = Amt.getValueType();
3705 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3706 DAG.getConstant(BitWidth, AmtVT), Amt);
3707 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3708 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3709 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3710 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3711 DAG.getConstant(-BitWidth, AmtVT));
3712 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
3713 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
3714 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
3715 SDValue OutOps[] = { OutLo, OutHi };
3716 return DAG.getMergeValues(OutOps, 2, dl);
3719 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
3720 DebugLoc dl = Op.getDebugLoc();
3721 EVT VT = Op.getValueType();
3722 unsigned BitWidth = VT.getSizeInBits();
3723 assert(Op.getNumOperands() == 3 &&
3724 VT == Op.getOperand(1).getValueType() &&
3727 // Expand into a bunch of logical ops, followed by a select_cc.
3728 SDValue Lo = Op.getOperand(0);
3729 SDValue Hi = Op.getOperand(1);
3730 SDValue Amt = Op.getOperand(2);
3731 EVT AmtVT = Amt.getValueType();
3733 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
3734 DAG.getConstant(BitWidth, AmtVT), Amt);
3735 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
3736 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
3737 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
3738 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
3739 DAG.getConstant(-BitWidth, AmtVT));
3740 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
3741 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
3742 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
3743 Tmp4, Tmp6, ISD::SETLE);
3744 SDValue OutOps[] = { OutLo, OutHi };
3745 return DAG.getMergeValues(OutOps, 2, dl);
3748 //===----------------------------------------------------------------------===//
3749 // Vector related lowering.
3752 /// BuildSplatI - Build a canonical splati of Val with an element size of
3753 /// SplatSize. Cast the result to VT.
3754 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
3755 SelectionDAG &DAG, DebugLoc dl) {
3756 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
3758 static const EVT VTys[] = { // canonical VT to use for each size.
3759 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
3762 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
3764 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
3768 EVT CanonicalVT = VTys[SplatSize-1];
3770 // Build a canonical splat for this value.
3771 SDValue Elt = DAG.getConstant(Val, MVT::i32);
3772 SmallVector<SDValue, 8> Ops;
3773 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
3774 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT,
3775 &Ops[0], Ops.size());
3776 return DAG.getNode(ISD::BIT_CONVERT, dl, ReqVT, Res);
3779 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
3780 /// specified intrinsic ID.
3781 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
3782 SelectionDAG &DAG, DebugLoc dl,
3783 EVT DestVT = MVT::Other) {
3784 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
3785 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3786 DAG.getConstant(IID, MVT::i32), LHS, RHS);
3789 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
3790 /// specified intrinsic ID.
3791 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
3792 SDValue Op2, SelectionDAG &DAG,
3793 DebugLoc dl, EVT DestVT = MVT::Other) {
3794 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
3795 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
3796 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
3800 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
3801 /// amount. The result has the specified value type.
3802 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
3803 EVT VT, SelectionDAG &DAG, DebugLoc dl) {
3804 // Force LHS/RHS to be the right type.
3805 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, LHS);
3806 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, RHS);
3809 for (unsigned i = 0; i != 16; ++i)
3811 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
3812 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
3815 // If this is a case we can't handle, return null and let the default
3816 // expansion code take care of it. If we CAN select this case, and if it
3817 // selects to a single instruction, return Op. Otherwise, if we can codegen
3818 // this case more efficiently than a constant pool load, lower it to the
3819 // sequence of ops that should be used.
3820 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
3821 SelectionDAG &DAG) const {
3822 DebugLoc dl = Op.getDebugLoc();
3823 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
3824 assert(BVN != 0 && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
3826 // Check if this is a splat of a constant value.
3827 APInt APSplatBits, APSplatUndef;
3828 unsigned SplatBitSize;
3830 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
3831 HasAnyUndefs, 0, true) || SplatBitSize > 32)
3834 unsigned SplatBits = APSplatBits.getZExtValue();
3835 unsigned SplatUndef = APSplatUndef.getZExtValue();
3836 unsigned SplatSize = SplatBitSize / 8;
3838 // First, handle single instruction cases.
3841 if (SplatBits == 0) {
3842 // Canonicalize all zero vectors to be v4i32.
3843 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
3844 SDValue Z = DAG.getConstant(0, MVT::i32);
3845 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
3846 Op = DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Z);
3851 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
3852 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
3854 if (SextVal >= -16 && SextVal <= 15)
3855 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
3858 // Two instruction sequences.
3860 // If this value is in the range [-32,30] and is even, use:
3861 // tmp = VSPLTI[bhw], result = add tmp, tmp
3862 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
3863 SDValue Res = BuildSplatI(SextVal >> 1, SplatSize, MVT::Other, DAG, dl);
3864 Res = DAG.getNode(ISD::ADD, dl, Res.getValueType(), Res, Res);
3865 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3868 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
3869 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
3871 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
3872 // Make -1 and vspltisw -1:
3873 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
3875 // Make the VSLW intrinsic, computing 0x8000_0000.
3876 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
3879 // xor by OnesV to invert it.
3880 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
3881 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3884 // Check to see if this is a wide variety of vsplti*, binop self cases.
3885 static const signed char SplatCsts[] = {
3886 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
3887 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
3890 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
3891 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
3892 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
3893 int i = SplatCsts[idx];
3895 // Figure out what shift amount will be used by altivec if shifted by i in
3897 unsigned TypeShiftAmt = i & (SplatBitSize-1);
3899 // vsplti + shl self.
3900 if (SextVal == (i << (int)TypeShiftAmt)) {
3901 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3902 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3903 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
3904 Intrinsic::ppc_altivec_vslw
3906 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3907 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3910 // vsplti + srl self.
3911 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3912 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3913 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3914 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
3915 Intrinsic::ppc_altivec_vsrw
3917 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3918 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3921 // vsplti + sra self.
3922 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
3923 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3924 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3925 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
3926 Intrinsic::ppc_altivec_vsraw
3928 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3929 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3932 // vsplti + rol self.
3933 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
3934 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
3935 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
3936 static const unsigned IIDs[] = { // Intrinsic to use for each size.
3937 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
3938 Intrinsic::ppc_altivec_vrlw
3940 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
3941 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Res);
3944 // t = vsplti c, result = vsldoi t, t, 1
3945 if (SextVal == ((i << 8) | (i < 0 ? 0xFF : 0))) {
3946 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3947 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
3949 // t = vsplti c, result = vsldoi t, t, 2
3950 if (SextVal == ((i << 16) | (i < 0 ? 0xFFFF : 0))) {
3951 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3952 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
3954 // t = vsplti c, result = vsldoi t, t, 3
3955 if (SextVal == ((i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
3956 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
3957 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
3961 // Three instruction sequences.
3963 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
3964 if (SextVal >= 0 && SextVal <= 31) {
3965 SDValue LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG, dl);
3966 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3967 LHS = DAG.getNode(ISD::SUB, dl, LHS.getValueType(), LHS, RHS);
3968 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3970 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
3971 if (SextVal >= -31 && SextVal <= 0) {
3972 SDValue LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG, dl);
3973 SDValue RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG, dl);
3974 LHS = DAG.getNode(ISD::ADD, dl, LHS.getValueType(), LHS, RHS);
3975 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), LHS);
3981 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
3982 /// the specified operations to build the shuffle.
3983 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
3984 SDValue RHS, SelectionDAG &DAG,
3986 unsigned OpNum = (PFEntry >> 26) & 0x0F;
3987 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
3988 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
3991 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
4003 if (OpNum == OP_COPY) {
4004 if (LHSID == (1*9+2)*9+3) return LHS;
4005 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
4009 SDValue OpLHS, OpRHS;
4010 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
4011 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
4015 default: llvm_unreachable("Unknown i32 permute!");
4017 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
4018 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
4019 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
4020 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
4023 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
4024 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
4025 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
4026 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
4029 for (unsigned i = 0; i != 16; ++i)
4030 ShufIdxs[i] = (i&3)+0;
4033 for (unsigned i = 0; i != 16; ++i)
4034 ShufIdxs[i] = (i&3)+4;
4037 for (unsigned i = 0; i != 16; ++i)
4038 ShufIdxs[i] = (i&3)+8;
4041 for (unsigned i = 0; i != 16; ++i)
4042 ShufIdxs[i] = (i&3)+12;
4045 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
4047 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
4049 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
4051 EVT VT = OpLHS.getValueType();
4052 OpLHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpLHS);
4053 OpRHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OpRHS);
4054 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
4055 return DAG.getNode(ISD::BIT_CONVERT, dl, VT, T);
4058 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
4059 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
4060 /// return the code it can be lowered into. Worst case, it can always be
4061 /// lowered into a vperm.
4062 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
4063 SelectionDAG &DAG) const {
4064 DebugLoc dl = Op.getDebugLoc();
4065 SDValue V1 = Op.getOperand(0);
4066 SDValue V2 = Op.getOperand(1);
4067 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
4068 EVT VT = Op.getValueType();
4070 // Cases that are handled by instructions that take permute immediates
4071 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
4072 // selected by the instruction selector.
4073 if (V2.getOpcode() == ISD::UNDEF) {
4074 if (PPC::isSplatShuffleMask(SVOp, 1) ||
4075 PPC::isSplatShuffleMask(SVOp, 2) ||
4076 PPC::isSplatShuffleMask(SVOp, 4) ||
4077 PPC::isVPKUWUMShuffleMask(SVOp, true) ||
4078 PPC::isVPKUHUMShuffleMask(SVOp, true) ||
4079 PPC::isVSLDOIShuffleMask(SVOp, true) != -1 ||
4080 PPC::isVMRGLShuffleMask(SVOp, 1, true) ||
4081 PPC::isVMRGLShuffleMask(SVOp, 2, true) ||
4082 PPC::isVMRGLShuffleMask(SVOp, 4, true) ||
4083 PPC::isVMRGHShuffleMask(SVOp, 1, true) ||
4084 PPC::isVMRGHShuffleMask(SVOp, 2, true) ||
4085 PPC::isVMRGHShuffleMask(SVOp, 4, true)) {
4090 // Altivec has a variety of "shuffle immediates" that take two vector inputs
4091 // and produce a fixed permutation. If any of these match, do not lower to
4093 if (PPC::isVPKUWUMShuffleMask(SVOp, false) ||
4094 PPC::isVPKUHUMShuffleMask(SVOp, false) ||
4095 PPC::isVSLDOIShuffleMask(SVOp, false) != -1 ||
4096 PPC::isVMRGLShuffleMask(SVOp, 1, false) ||
4097 PPC::isVMRGLShuffleMask(SVOp, 2, false) ||
4098 PPC::isVMRGLShuffleMask(SVOp, 4, false) ||
4099 PPC::isVMRGHShuffleMask(SVOp, 1, false) ||
4100 PPC::isVMRGHShuffleMask(SVOp, 2, false) ||
4101 PPC::isVMRGHShuffleMask(SVOp, 4, false))
4104 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
4105 // perfect shuffle table to emit an optimal matching sequence.
4106 SmallVector<int, 16> PermMask;
4107 SVOp->getMask(PermMask);
4109 unsigned PFIndexes[4];
4110 bool isFourElementShuffle = true;
4111 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
4112 unsigned EltNo = 8; // Start out undef.
4113 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
4114 if (PermMask[i*4+j] < 0)
4115 continue; // Undef, ignore it.
4117 unsigned ByteSource = PermMask[i*4+j];
4118 if ((ByteSource & 3) != j) {
4119 isFourElementShuffle = false;
4124 EltNo = ByteSource/4;
4125 } else if (EltNo != ByteSource/4) {
4126 isFourElementShuffle = false;
4130 PFIndexes[i] = EltNo;
4133 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
4134 // perfect shuffle vector to determine if it is cost effective to do this as
4135 // discrete instructions, or whether we should use a vperm.
4136 if (isFourElementShuffle) {
4137 // Compute the index in the perfect shuffle table.
4138 unsigned PFTableIndex =
4139 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
4141 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
4142 unsigned Cost = (PFEntry >> 30);
4144 // Determining when to avoid vperm is tricky. Many things affect the cost
4145 // of vperm, particularly how many times the perm mask needs to be computed.
4146 // For example, if the perm mask can be hoisted out of a loop or is already
4147 // used (perhaps because there are multiple permutes with the same shuffle
4148 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
4149 // the loop requires an extra register.
4151 // As a compromise, we only emit discrete instructions if the shuffle can be
4152 // generated in 3 or fewer operations. When we have loop information
4153 // available, if this block is within a loop, we should avoid using vperm
4154 // for 3-operation perms and use a constant pool load instead.
4156 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
4159 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
4160 // vector that will get spilled to the constant pool.
4161 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
4163 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
4164 // that it is in input element units, not in bytes. Convert now.
4165 EVT EltVT = V1.getValueType().getVectorElementType();
4166 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
4168 SmallVector<SDValue, 16> ResultMask;
4169 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
4170 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
4172 for (unsigned j = 0; j != BytesPerElement; ++j)
4173 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
4177 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
4178 &ResultMask[0], ResultMask.size());
4179 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(), V1, V2, VPermMask);
4182 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
4183 /// altivec comparison. If it is, return true and fill in Opc/isDot with
4184 /// information about the intrinsic.
4185 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
4187 unsigned IntrinsicID =
4188 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
4191 switch (IntrinsicID) {
4192 default: return false;
4193 // Comparison predicates.
4194 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
4195 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
4196 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
4197 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
4198 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
4199 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
4200 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
4201 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
4202 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
4203 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
4204 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
4205 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
4206 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
4208 // Normal Comparisons.
4209 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
4210 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
4211 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
4212 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
4213 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
4214 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
4215 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
4216 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
4217 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
4218 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
4219 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
4220 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
4221 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
4226 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
4227 /// lower, do it, otherwise return null.
4228 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
4229 SelectionDAG &DAG) const {
4230 // If this is a lowered altivec predicate compare, CompareOpc is set to the
4231 // opcode number of the comparison.
4232 DebugLoc dl = Op.getDebugLoc();
4235 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
4236 return SDValue(); // Don't custom lower most intrinsics.
4238 // If this is a non-dot comparison, make the VCMP node and we are done.
4240 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
4241 Op.getOperand(1), Op.getOperand(2),
4242 DAG.getConstant(CompareOpc, MVT::i32));
4243 return DAG.getNode(ISD::BIT_CONVERT, dl, Op.getValueType(), Tmp);
4246 // Create the PPCISD altivec 'dot' comparison node.
4248 Op.getOperand(2), // LHS
4249 Op.getOperand(3), // RHS
4250 DAG.getConstant(CompareOpc, MVT::i32)
4252 std::vector<EVT> VTs;
4253 VTs.push_back(Op.getOperand(2).getValueType());
4254 VTs.push_back(MVT::Flag);
4255 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
4257 // Now that we have the comparison, emit a copy from the CR to a GPR.
4258 // This is flagged to the above dot comparison.
4259 SDValue Flags = DAG.getNode(PPCISD::MFCR, dl, MVT::i32,
4260 DAG.getRegister(PPC::CR6, MVT::i32),
4261 CompNode.getValue(1));
4263 // Unpack the result based on how the target uses it.
4264 unsigned BitNo; // Bit # of CR6.
4265 bool InvertBit; // Invert result?
4266 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
4267 default: // Can't happen, don't crash on invalid number though.
4268 case 0: // Return the value of the EQ bit of CR6.
4269 BitNo = 0; InvertBit = false;
4271 case 1: // Return the inverted value of the EQ bit of CR6.
4272 BitNo = 0; InvertBit = true;
4274 case 2: // Return the value of the LT bit of CR6.
4275 BitNo = 2; InvertBit = false;
4277 case 3: // Return the inverted value of the LT bit of CR6.
4278 BitNo = 2; InvertBit = true;
4282 // Shift the bit into the low position.
4283 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
4284 DAG.getConstant(8-(3-BitNo), MVT::i32));
4286 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
4287 DAG.getConstant(1, MVT::i32));
4289 // If we are supposed to, toggle the bit.
4291 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
4292 DAG.getConstant(1, MVT::i32));
4296 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
4297 SelectionDAG &DAG) const {
4298 DebugLoc dl = Op.getDebugLoc();
4299 // Create a stack slot that is 16-byte aligned.
4300 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
4301 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
4302 EVT PtrVT = getPointerTy();
4303 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
4305 // Store the input value into Value#0 of the stack slot.
4306 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
4307 Op.getOperand(0), FIdx, NULL, 0,
4310 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, NULL, 0,
4314 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
4315 DebugLoc dl = Op.getDebugLoc();
4316 if (Op.getValueType() == MVT::v4i32) {
4317 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4319 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
4320 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
4322 SDValue RHSSwap = // = vrlw RHS, 16
4323 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
4325 // Shrinkify inputs to v8i16.
4326 LHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, LHS);
4327 RHS = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHS);
4328 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, RHSSwap);
4330 // Low parts multiplied together, generating 32-bit results (we ignore the
4332 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
4333 LHS, RHS, DAG, dl, MVT::v4i32);
4335 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
4336 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
4337 // Shift the high parts up 16 bits.
4338 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
4340 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
4341 } else if (Op.getValueType() == MVT::v8i16) {
4342 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4344 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
4346 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
4347 LHS, RHS, Zero, DAG, dl);
4348 } else if (Op.getValueType() == MVT::v16i8) {
4349 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
4351 // Multiply the even 8-bit parts, producing 16-bit sums.
4352 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
4353 LHS, RHS, DAG, dl, MVT::v8i16);
4354 EvenParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, EvenParts);
4356 // Multiply the odd 8-bit parts, producing 16-bit sums.
4357 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
4358 LHS, RHS, DAG, dl, MVT::v8i16);
4359 OddParts = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, OddParts);
4361 // Merge the results together.
4363 for (unsigned i = 0; i != 8; ++i) {
4365 Ops[i*2+1] = 2*i+1+16;
4367 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
4369 llvm_unreachable("Unknown mul to lower!");
4373 /// LowerOperation - Provide custom lowering hooks for some operations.
4375 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
4376 switch (Op.getOpcode()) {
4377 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
4378 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
4379 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
4380 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
4381 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
4382 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
4383 case ISD::SETCC: return LowerSETCC(Op, DAG);
4384 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
4386 return LowerVASTART(Op, DAG, PPCSubTarget);
4389 return LowerVAARG(Op, DAG, PPCSubTarget);
4391 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
4392 case ISD::DYNAMIC_STACKALLOC:
4393 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
4395 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
4396 case ISD::FP_TO_UINT:
4397 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
4399 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
4400 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
4402 // Lower 64-bit shifts.
4403 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
4404 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
4405 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
4407 // Vector-related lowering.
4408 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
4409 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
4410 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
4411 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
4412 case ISD::MUL: return LowerMUL(Op, DAG);
4414 // Frame & Return address.
4415 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
4416 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
4421 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
4422 SmallVectorImpl<SDValue>&Results,
4423 SelectionDAG &DAG) const {
4424 DebugLoc dl = N->getDebugLoc();
4425 switch (N->getOpcode()) {
4427 assert(false && "Do not know how to custom type legalize this operation!");
4429 case ISD::FP_ROUND_INREG: {
4430 assert(N->getValueType(0) == MVT::ppcf128);
4431 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
4432 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4433 MVT::f64, N->getOperand(0),
4434 DAG.getIntPtrConstant(0));
4435 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
4436 MVT::f64, N->getOperand(0),
4437 DAG.getIntPtrConstant(1));
4439 // This sequence changes FPSCR to do round-to-zero, adds the two halves
4440 // of the long double, and puts FPSCR back the way it was. We do not
4441 // actually model FPSCR.
4442 std::vector<EVT> NodeTys;
4443 SDValue Ops[4], Result, MFFSreg, InFlag, FPreg;
4445 NodeTys.push_back(MVT::f64); // Return register
4446 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
4447 Result = DAG.getNode(PPCISD::MFFS, dl, NodeTys, &InFlag, 0);
4448 MFFSreg = Result.getValue(0);
4449 InFlag = Result.getValue(1);
4452 NodeTys.push_back(MVT::Flag); // Returns a flag
4453 Ops[0] = DAG.getConstant(31, MVT::i32);
4455 Result = DAG.getNode(PPCISD::MTFSB1, dl, NodeTys, Ops, 2);
4456 InFlag = Result.getValue(0);
4459 NodeTys.push_back(MVT::Flag); // Returns a flag
4460 Ops[0] = DAG.getConstant(30, MVT::i32);
4462 Result = DAG.getNode(PPCISD::MTFSB0, dl, NodeTys, Ops, 2);
4463 InFlag = Result.getValue(0);
4466 NodeTys.push_back(MVT::f64); // result of add
4467 NodeTys.push_back(MVT::Flag); // Returns a flag
4471 Result = DAG.getNode(PPCISD::FADDRTZ, dl, NodeTys, Ops, 3);
4472 FPreg = Result.getValue(0);
4473 InFlag = Result.getValue(1);
4476 NodeTys.push_back(MVT::f64);
4477 Ops[0] = DAG.getConstant(1, MVT::i32);
4481 Result = DAG.getNode(PPCISD::MTFSF, dl, NodeTys, Ops, 4);
4482 FPreg = Result.getValue(0);
4484 // We know the low half is about to be thrown away, so just use something
4486 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
4490 case ISD::FP_TO_SINT:
4491 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
4497 //===----------------------------------------------------------------------===//
4498 // Other Lowering Code
4499 //===----------------------------------------------------------------------===//
4502 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
4503 bool is64bit, unsigned BinOpcode) const {
4504 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4505 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4507 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4508 MachineFunction *F = BB->getParent();
4509 MachineFunction::iterator It = BB;
4512 unsigned dest = MI->getOperand(0).getReg();
4513 unsigned ptrA = MI->getOperand(1).getReg();
4514 unsigned ptrB = MI->getOperand(2).getReg();
4515 unsigned incr = MI->getOperand(3).getReg();
4516 DebugLoc dl = MI->getDebugLoc();
4518 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4519 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4520 F->insert(It, loopMBB);
4521 F->insert(It, exitMBB);
4522 exitMBB->splice(exitMBB->begin(), BB,
4523 llvm::next(MachineBasicBlock::iterator(MI)),
4525 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4527 MachineRegisterInfo &RegInfo = F->getRegInfo();
4528 unsigned TmpReg = (!BinOpcode) ? incr :
4529 RegInfo.createVirtualRegister(
4530 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4531 (const TargetRegisterClass *) &PPC::GPRCRegClass);
4535 // fallthrough --> loopMBB
4536 BB->addSuccessor(loopMBB);
4539 // l[wd]arx dest, ptr
4540 // add r0, dest, incr
4541 // st[wd]cx. r0, ptr
4543 // fallthrough --> exitMBB
4545 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4546 .addReg(ptrA).addReg(ptrB);
4548 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
4549 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4550 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
4551 BuildMI(BB, dl, TII->get(PPC::BCC))
4552 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4553 BB->addSuccessor(loopMBB);
4554 BB->addSuccessor(exitMBB);
4563 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
4564 MachineBasicBlock *BB,
4565 bool is8bit, // operation
4566 unsigned BinOpcode) const {
4567 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
4568 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4569 // In 64 bit mode we have to use 64 bits for addresses, even though the
4570 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
4571 // registers without caring whether they're 32 or 64, but here we're
4572 // doing actual arithmetic on the addresses.
4573 bool is64bit = PPCSubTarget.isPPC64();
4575 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4576 MachineFunction *F = BB->getParent();
4577 MachineFunction::iterator It = BB;
4580 unsigned dest = MI->getOperand(0).getReg();
4581 unsigned ptrA = MI->getOperand(1).getReg();
4582 unsigned ptrB = MI->getOperand(2).getReg();
4583 unsigned incr = MI->getOperand(3).getReg();
4584 DebugLoc dl = MI->getDebugLoc();
4586 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
4587 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4588 F->insert(It, loopMBB);
4589 F->insert(It, exitMBB);
4590 exitMBB->splice(exitMBB->begin(), BB,
4591 llvm::next(MachineBasicBlock::iterator(MI)),
4593 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4595 MachineRegisterInfo &RegInfo = F->getRegInfo();
4596 const TargetRegisterClass *RC =
4597 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4598 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4599 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4600 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4601 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4602 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
4603 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4604 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4605 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4606 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4607 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
4608 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4609 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4611 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
4615 // fallthrough --> loopMBB
4616 BB->addSuccessor(loopMBB);
4618 // The 4-byte load must be aligned, while a char or short may be
4619 // anywhere in the word. Hence all this nasty bookkeeping code.
4620 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4621 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4622 // xori shift, shift1, 24 [16]
4623 // rlwinm ptr, ptr1, 0, 0, 29
4624 // slw incr2, incr, shift
4625 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4626 // slw mask, mask2, shift
4628 // lwarx tmpDest, ptr
4629 // add tmp, tmpDest, incr2
4630 // andc tmp2, tmpDest, mask
4631 // and tmp3, tmp, mask
4632 // or tmp4, tmp3, tmp2
4635 // fallthrough --> exitMBB
4636 // srw dest, tmpDest, shift
4638 if (ptrA!=PPC::R0) {
4639 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4640 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4641 .addReg(ptrA).addReg(ptrB);
4645 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4646 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4647 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4648 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4650 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4651 .addReg(Ptr1Reg).addImm(0).addImm(61);
4653 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4654 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4655 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
4656 .addReg(incr).addReg(ShiftReg);
4658 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4660 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4661 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
4663 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4664 .addReg(Mask2Reg).addReg(ShiftReg);
4667 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
4668 .addReg(PPC::R0).addReg(PtrReg);
4670 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
4671 .addReg(Incr2Reg).addReg(TmpDestReg);
4672 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
4673 .addReg(TmpDestReg).addReg(MaskReg);
4674 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
4675 .addReg(TmpReg).addReg(MaskReg);
4676 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
4677 .addReg(Tmp3Reg).addReg(Tmp2Reg);
4678 BuildMI(BB, dl, TII->get(PPC::STWCX))
4679 .addReg(Tmp4Reg).addReg(PPC::R0).addReg(PtrReg);
4680 BuildMI(BB, dl, TII->get(PPC::BCC))
4681 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
4682 BB->addSuccessor(loopMBB);
4683 BB->addSuccessor(exitMBB);
4688 BuildMI(BB, dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg).addReg(ShiftReg);
4693 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
4694 MachineBasicBlock *BB) const {
4695 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
4697 // To "insert" these instructions we actually have to insert their
4698 // control-flow patterns.
4699 const BasicBlock *LLVM_BB = BB->getBasicBlock();
4700 MachineFunction::iterator It = BB;
4703 MachineFunction *F = BB->getParent();
4705 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
4706 MI->getOpcode() == PPC::SELECT_CC_I8 ||
4707 MI->getOpcode() == PPC::SELECT_CC_F4 ||
4708 MI->getOpcode() == PPC::SELECT_CC_F8 ||
4709 MI->getOpcode() == PPC::SELECT_CC_VRRC) {
4711 // The incoming instruction knows the destination vreg to set, the
4712 // condition code register to branch on, the true/false values to
4713 // select between, and a branch opcode to use.
4718 // cmpTY ccX, r1, r2
4720 // fallthrough --> copy0MBB
4721 MachineBasicBlock *thisMBB = BB;
4722 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
4723 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
4724 unsigned SelectPred = MI->getOperand(4).getImm();
4725 DebugLoc dl = MI->getDebugLoc();
4726 F->insert(It, copy0MBB);
4727 F->insert(It, sinkMBB);
4729 // Transfer the remainder of BB and its successor edges to sinkMBB.
4730 sinkMBB->splice(sinkMBB->begin(), BB,
4731 llvm::next(MachineBasicBlock::iterator(MI)),
4733 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
4735 // Next, add the true and fallthrough blocks as its successors.
4736 BB->addSuccessor(copy0MBB);
4737 BB->addSuccessor(sinkMBB);
4739 BuildMI(BB, dl, TII->get(PPC::BCC))
4740 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
4743 // %FalseValue = ...
4744 // # fallthrough to sinkMBB
4747 // Update machine-CFG edges
4748 BB->addSuccessor(sinkMBB);
4751 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
4754 BuildMI(*BB, BB->begin(), dl,
4755 TII->get(PPC::PHI), MI->getOperand(0).getReg())
4756 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
4757 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
4759 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
4760 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
4761 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
4762 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
4763 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
4764 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
4765 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
4766 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
4768 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
4769 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
4770 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
4771 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
4772 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
4773 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
4774 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
4775 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
4777 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
4778 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
4779 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
4780 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
4781 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
4782 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
4783 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
4784 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
4786 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
4787 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
4788 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
4789 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
4790 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
4791 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
4792 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
4793 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
4795 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
4796 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
4797 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
4798 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
4799 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
4800 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
4801 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
4802 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
4804 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
4805 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
4806 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
4807 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
4808 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
4809 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
4810 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
4811 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
4813 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
4814 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
4815 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
4816 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
4817 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
4818 BB = EmitAtomicBinary(MI, BB, false, 0);
4819 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
4820 BB = EmitAtomicBinary(MI, BB, true, 0);
4822 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
4823 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
4824 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
4826 unsigned dest = MI->getOperand(0).getReg();
4827 unsigned ptrA = MI->getOperand(1).getReg();
4828 unsigned ptrB = MI->getOperand(2).getReg();
4829 unsigned oldval = MI->getOperand(3).getReg();
4830 unsigned newval = MI->getOperand(4).getReg();
4831 DebugLoc dl = MI->getDebugLoc();
4833 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4834 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4835 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4836 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4837 F->insert(It, loop1MBB);
4838 F->insert(It, loop2MBB);
4839 F->insert(It, midMBB);
4840 F->insert(It, exitMBB);
4841 exitMBB->splice(exitMBB->begin(), BB,
4842 llvm::next(MachineBasicBlock::iterator(MI)),
4844 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4848 // fallthrough --> loopMBB
4849 BB->addSuccessor(loop1MBB);
4852 // l[wd]arx dest, ptr
4853 // cmp[wd] dest, oldval
4856 // st[wd]cx. newval, ptr
4860 // st[wd]cx. dest, ptr
4863 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
4864 .addReg(ptrA).addReg(ptrB);
4865 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
4866 .addReg(oldval).addReg(dest);
4867 BuildMI(BB, dl, TII->get(PPC::BCC))
4868 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
4869 BB->addSuccessor(loop2MBB);
4870 BB->addSuccessor(midMBB);
4873 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4874 .addReg(newval).addReg(ptrA).addReg(ptrB);
4875 BuildMI(BB, dl, TII->get(PPC::BCC))
4876 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
4877 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
4878 BB->addSuccessor(loop1MBB);
4879 BB->addSuccessor(exitMBB);
4882 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
4883 .addReg(dest).addReg(ptrA).addReg(ptrB);
4884 BB->addSuccessor(exitMBB);
4889 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
4890 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
4891 // We must use 64-bit registers for addresses when targeting 64-bit,
4892 // since we're actually doing arithmetic on them. Other registers
4894 bool is64bit = PPCSubTarget.isPPC64();
4895 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
4897 unsigned dest = MI->getOperand(0).getReg();
4898 unsigned ptrA = MI->getOperand(1).getReg();
4899 unsigned ptrB = MI->getOperand(2).getReg();
4900 unsigned oldval = MI->getOperand(3).getReg();
4901 unsigned newval = MI->getOperand(4).getReg();
4902 DebugLoc dl = MI->getDebugLoc();
4904 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
4905 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
4906 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
4907 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
4908 F->insert(It, loop1MBB);
4909 F->insert(It, loop2MBB);
4910 F->insert(It, midMBB);
4911 F->insert(It, exitMBB);
4912 exitMBB->splice(exitMBB->begin(), BB,
4913 llvm::next(MachineBasicBlock::iterator(MI)),
4915 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
4917 MachineRegisterInfo &RegInfo = F->getRegInfo();
4918 const TargetRegisterClass *RC =
4919 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
4920 (const TargetRegisterClass *) &PPC::GPRCRegClass;
4921 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
4922 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
4923 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
4924 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
4925 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
4926 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
4927 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
4928 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
4929 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
4930 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
4931 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
4932 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
4933 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
4935 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
4938 // fallthrough --> loopMBB
4939 BB->addSuccessor(loop1MBB);
4941 // The 4-byte load must be aligned, while a char or short may be
4942 // anywhere in the word. Hence all this nasty bookkeeping code.
4943 // add ptr1, ptrA, ptrB [copy if ptrA==0]
4944 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
4945 // xori shift, shift1, 24 [16]
4946 // rlwinm ptr, ptr1, 0, 0, 29
4947 // slw newval2, newval, shift
4948 // slw oldval2, oldval,shift
4949 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
4950 // slw mask, mask2, shift
4951 // and newval3, newval2, mask
4952 // and oldval3, oldval2, mask
4954 // lwarx tmpDest, ptr
4955 // and tmp, tmpDest, mask
4956 // cmpw tmp, oldval3
4959 // andc tmp2, tmpDest, mask
4960 // or tmp4, tmp2, newval3
4965 // stwcx. tmpDest, ptr
4967 // srw dest, tmpDest, shift
4968 if (ptrA!=PPC::R0) {
4969 Ptr1Reg = RegInfo.createVirtualRegister(RC);
4970 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
4971 .addReg(ptrA).addReg(ptrB);
4975 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
4976 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
4977 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
4978 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
4980 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
4981 .addReg(Ptr1Reg).addImm(0).addImm(61);
4983 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
4984 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
4985 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
4986 .addReg(newval).addReg(ShiftReg);
4987 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
4988 .addReg(oldval).addReg(ShiftReg);
4990 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
4992 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
4993 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
4994 .addReg(Mask3Reg).addImm(65535);
4996 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
4997 .addReg(Mask2Reg).addReg(ShiftReg);
4998 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
4999 .addReg(NewVal2Reg).addReg(MaskReg);
5000 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
5001 .addReg(OldVal2Reg).addReg(MaskReg);
5004 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
5005 .addReg(PPC::R0).addReg(PtrReg);
5006 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
5007 .addReg(TmpDestReg).addReg(MaskReg);
5008 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
5009 .addReg(TmpReg).addReg(OldVal3Reg);
5010 BuildMI(BB, dl, TII->get(PPC::BCC))
5011 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
5012 BB->addSuccessor(loop2MBB);
5013 BB->addSuccessor(midMBB);
5016 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
5017 .addReg(TmpDestReg).addReg(MaskReg);
5018 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
5019 .addReg(Tmp2Reg).addReg(NewVal3Reg);
5020 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
5021 .addReg(PPC::R0).addReg(PtrReg);
5022 BuildMI(BB, dl, TII->get(PPC::BCC))
5023 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
5024 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
5025 BB->addSuccessor(loop1MBB);
5026 BB->addSuccessor(exitMBB);
5029 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
5030 .addReg(PPC::R0).addReg(PtrReg);
5031 BB->addSuccessor(exitMBB);
5036 BuildMI(BB, dl, TII->get(PPC::SRW),dest).addReg(TmpReg).addReg(ShiftReg);
5038 llvm_unreachable("Unexpected instr type to insert");
5041 MI->eraseFromParent(); // The pseudo instruction is gone now.
5045 //===----------------------------------------------------------------------===//
5046 // Target Optimization Hooks
5047 //===----------------------------------------------------------------------===//
5049 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
5050 DAGCombinerInfo &DCI) const {
5051 const TargetMachine &TM = getTargetMachine();
5052 SelectionDAG &DAG = DCI.DAG;
5053 DebugLoc dl = N->getDebugLoc();
5054 switch (N->getOpcode()) {
5057 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5058 if (C->isNullValue()) // 0 << V -> 0.
5059 return N->getOperand(0);
5063 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5064 if (C->isNullValue()) // 0 >>u V -> 0.
5065 return N->getOperand(0);
5069 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
5070 if (C->isNullValue() || // 0 >>s V -> 0.
5071 C->isAllOnesValue()) // -1 >>s V -> -1.
5072 return N->getOperand(0);
5076 case ISD::SINT_TO_FP:
5077 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
5078 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
5079 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
5080 // We allow the src/dst to be either f32/f64, but the intermediate
5081 // type must be i64.
5082 if (N->getOperand(0).getValueType() == MVT::i64 &&
5083 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
5084 SDValue Val = N->getOperand(0).getOperand(0);
5085 if (Val.getValueType() == MVT::f32) {
5086 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5087 DCI.AddToWorklist(Val.getNode());
5090 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
5091 DCI.AddToWorklist(Val.getNode());
5092 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
5093 DCI.AddToWorklist(Val.getNode());
5094 if (N->getValueType(0) == MVT::f32) {
5095 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
5096 DAG.getIntPtrConstant(0));
5097 DCI.AddToWorklist(Val.getNode());
5100 } else if (N->getOperand(0).getValueType() == MVT::i32) {
5101 // If the intermediate type is i32, we can avoid the load/store here
5108 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
5109 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
5110 !cast<StoreSDNode>(N)->isTruncatingStore() &&
5111 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
5112 N->getOperand(1).getValueType() == MVT::i32 &&
5113 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
5114 SDValue Val = N->getOperand(1).getOperand(0);
5115 if (Val.getValueType() == MVT::f32) {
5116 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
5117 DCI.AddToWorklist(Val.getNode());
5119 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
5120 DCI.AddToWorklist(Val.getNode());
5122 Val = DAG.getNode(PPCISD::STFIWX, dl, MVT::Other, N->getOperand(0), Val,
5123 N->getOperand(2), N->getOperand(3));
5124 DCI.AddToWorklist(Val.getNode());
5128 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
5129 if (cast<StoreSDNode>(N)->isUnindexed() &&
5130 N->getOperand(1).getOpcode() == ISD::BSWAP &&
5131 N->getOperand(1).getNode()->hasOneUse() &&
5132 (N->getOperand(1).getValueType() == MVT::i32 ||
5133 N->getOperand(1).getValueType() == MVT::i16)) {
5134 SDValue BSwapOp = N->getOperand(1).getOperand(0);
5135 // Do an any-extend to 32-bits if this is a half-word input.
5136 if (BSwapOp.getValueType() == MVT::i16)
5137 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
5140 N->getOperand(0), BSwapOp, N->getOperand(2),
5141 DAG.getValueType(N->getOperand(1).getValueType())
5144 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
5145 Ops, array_lengthof(Ops),
5146 cast<StoreSDNode>(N)->getMemoryVT(),
5147 cast<StoreSDNode>(N)->getMemOperand());
5151 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
5152 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
5153 N->getOperand(0).hasOneUse() &&
5154 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
5155 SDValue Load = N->getOperand(0);
5156 LoadSDNode *LD = cast<LoadSDNode>(Load);
5157 // Create the byte-swapping load.
5159 LD->getChain(), // Chain
5160 LD->getBasePtr(), // Ptr
5161 DAG.getValueType(N->getValueType(0)) // VT
5164 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
5165 DAG.getVTList(MVT::i32, MVT::Other), Ops, 3,
5166 LD->getMemoryVT(), LD->getMemOperand());
5168 // If this is an i16 load, insert the truncate.
5169 SDValue ResVal = BSLoad;
5170 if (N->getValueType(0) == MVT::i16)
5171 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
5173 // First, combine the bswap away. This makes the value produced by the
5175 DCI.CombineTo(N, ResVal);
5177 // Next, combine the load away, we give it a bogus result value but a real
5178 // chain result. The result value is dead because the bswap is dead.
5179 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
5181 // Return N so it doesn't get rechecked!
5182 return SDValue(N, 0);
5186 case PPCISD::VCMP: {
5187 // If a VCMPo node already exists with exactly the same operands as this
5188 // node, use its result instead of this node (VCMPo computes both a CR6 and
5189 // a normal output).
5191 if (!N->getOperand(0).hasOneUse() &&
5192 !N->getOperand(1).hasOneUse() &&
5193 !N->getOperand(2).hasOneUse()) {
5195 // Scan all of the users of the LHS, looking for VCMPo's that match.
5196 SDNode *VCMPoNode = 0;
5198 SDNode *LHSN = N->getOperand(0).getNode();
5199 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
5201 if (UI->getOpcode() == PPCISD::VCMPo &&
5202 UI->getOperand(1) == N->getOperand(1) &&
5203 UI->getOperand(2) == N->getOperand(2) &&
5204 UI->getOperand(0) == N->getOperand(0)) {
5209 // If there is no VCMPo node, or if the flag value has a single use, don't
5211 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
5214 // Look at the (necessarily single) use of the flag value. If it has a
5215 // chain, this transformation is more complex. Note that multiple things
5216 // could use the value result, which we should ignore.
5217 SDNode *FlagUser = 0;
5218 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
5219 FlagUser == 0; ++UI) {
5220 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
5222 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
5223 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
5230 // If the user is a MFCR instruction, we know this is safe. Otherwise we
5231 // give up for right now.
5232 if (FlagUser->getOpcode() == PPCISD::MFCR)
5233 return SDValue(VCMPoNode, 0);
5238 // If this is a branch on an altivec predicate comparison, lower this so
5239 // that we don't have to do a MFCR: instead, branch directly on CR6. This
5240 // lowering is done pre-legalize, because the legalizer lowers the predicate
5241 // compare down to code that is difficult to reassemble.
5242 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
5243 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
5247 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
5248 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
5249 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
5250 assert(isDot && "Can't compare against a vector result!");
5252 // If this is a comparison against something other than 0/1, then we know
5253 // that the condition is never/always true.
5254 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
5255 if (Val != 0 && Val != 1) {
5256 if (CC == ISD::SETEQ) // Cond never true, remove branch.
5257 return N->getOperand(0);
5258 // Always !=, turn it into an unconditional branch.
5259 return DAG.getNode(ISD::BR, dl, MVT::Other,
5260 N->getOperand(0), N->getOperand(4));
5263 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
5265 // Create the PPCISD altivec 'dot' comparison node.
5266 std::vector<EVT> VTs;
5268 LHS.getOperand(2), // LHS of compare
5269 LHS.getOperand(3), // RHS of compare
5270 DAG.getConstant(CompareOpc, MVT::i32)
5272 VTs.push_back(LHS.getOperand(2).getValueType());
5273 VTs.push_back(MVT::Flag);
5274 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops, 3);
5276 // Unpack the result based on how the target uses it.
5277 PPC::Predicate CompOpc;
5278 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
5279 default: // Can't happen, don't crash on invalid number though.
5280 case 0: // Branch on the value of the EQ bit of CR6.
5281 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
5283 case 1: // Branch on the inverted value of the EQ bit of CR6.
5284 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
5286 case 2: // Branch on the value of the LT bit of CR6.
5287 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
5289 case 3: // Branch on the inverted value of the LT bit of CR6.
5290 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
5294 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
5295 DAG.getConstant(CompOpc, MVT::i32),
5296 DAG.getRegister(PPC::CR6, MVT::i32),
5297 N->getOperand(4), CompNode.getValue(1));
5306 //===----------------------------------------------------------------------===//
5307 // Inline Assembly Support
5308 //===----------------------------------------------------------------------===//
5310 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
5314 const SelectionDAG &DAG,
5315 unsigned Depth) const {
5316 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
5317 switch (Op.getOpcode()) {
5319 case PPCISD::LBRX: {
5320 // lhbrx is known to have the top bits cleared out.
5321 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
5322 KnownZero = 0xFFFF0000;
5325 case ISD::INTRINSIC_WO_CHAIN: {
5326 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
5328 case Intrinsic::ppc_altivec_vcmpbfp_p:
5329 case Intrinsic::ppc_altivec_vcmpeqfp_p:
5330 case Intrinsic::ppc_altivec_vcmpequb_p:
5331 case Intrinsic::ppc_altivec_vcmpequh_p:
5332 case Intrinsic::ppc_altivec_vcmpequw_p:
5333 case Intrinsic::ppc_altivec_vcmpgefp_p:
5334 case Intrinsic::ppc_altivec_vcmpgtfp_p:
5335 case Intrinsic::ppc_altivec_vcmpgtsb_p:
5336 case Intrinsic::ppc_altivec_vcmpgtsh_p:
5337 case Intrinsic::ppc_altivec_vcmpgtsw_p:
5338 case Intrinsic::ppc_altivec_vcmpgtub_p:
5339 case Intrinsic::ppc_altivec_vcmpgtuh_p:
5340 case Intrinsic::ppc_altivec_vcmpgtuw_p:
5341 KnownZero = ~1U; // All bits but the low one are known to be zero.
5349 /// getConstraintType - Given a constraint, return the type of
5350 /// constraint it is for this target.
5351 PPCTargetLowering::ConstraintType
5352 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
5353 if (Constraint.size() == 1) {
5354 switch (Constraint[0]) {
5361 return C_RegisterClass;
5364 return TargetLowering::getConstraintType(Constraint);
5367 std::pair<unsigned, const TargetRegisterClass*>
5368 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
5370 if (Constraint.size() == 1) {
5371 // GCC RS6000 Constraint Letters
5372 switch (Constraint[0]) {
5375 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
5376 return std::make_pair(0U, PPC::G8RCRegisterClass);
5377 return std::make_pair(0U, PPC::GPRCRegisterClass);
5380 return std::make_pair(0U, PPC::F4RCRegisterClass);
5381 else if (VT == MVT::f64)
5382 return std::make_pair(0U, PPC::F8RCRegisterClass);
5385 return std::make_pair(0U, PPC::VRRCRegisterClass);
5387 return std::make_pair(0U, PPC::CRRCRegisterClass);
5391 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
5395 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
5396 /// vector. If it is invalid, don't add anything to Ops.
5397 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op, char Letter,
5398 std::vector<SDValue>&Ops,
5399 SelectionDAG &DAG) const {
5400 SDValue Result(0,0);
5411 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
5412 if (!CST) return; // Must be an immediate to match.
5413 unsigned Value = CST->getZExtValue();
5415 default: llvm_unreachable("Unknown constraint letter!");
5416 case 'I': // "I" is a signed 16-bit constant.
5417 if ((short)Value == (int)Value)
5418 Result = DAG.getTargetConstant(Value, Op.getValueType());
5420 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
5421 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
5422 if ((short)Value == 0)
5423 Result = DAG.getTargetConstant(Value, Op.getValueType());
5425 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
5426 if ((Value >> 16) == 0)
5427 Result = DAG.getTargetConstant(Value, Op.getValueType());
5429 case 'M': // "M" is a constant that is greater than 31.
5431 Result = DAG.getTargetConstant(Value, Op.getValueType());
5433 case 'N': // "N" is a positive constant that is an exact power of two.
5434 if ((int)Value > 0 && isPowerOf2_32(Value))
5435 Result = DAG.getTargetConstant(Value, Op.getValueType());
5437 case 'O': // "O" is the constant zero.
5439 Result = DAG.getTargetConstant(Value, Op.getValueType());
5441 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
5442 if ((short)-Value == (int)-Value)
5443 Result = DAG.getTargetConstant(Value, Op.getValueType());
5450 if (Result.getNode()) {
5451 Ops.push_back(Result);
5455 // Handle standard constraint letters.
5456 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
5459 // isLegalAddressingMode - Return true if the addressing mode represented
5460 // by AM is legal for this target, for a load/store of the specified type.
5461 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
5462 const Type *Ty) const {
5463 // FIXME: PPC does not allow r+i addressing modes for vectors!
5465 // PPC allows a sign-extended 16-bit immediate field.
5466 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
5469 // No global is ever allowed as a base.
5473 // PPC only support r+r,
5475 case 0: // "r+i" or just "i", depending on HasBaseReg.
5478 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
5480 // Otherwise we have r+r or r+i.
5483 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
5485 // Allow 2*r as r+r.
5488 // No other scales are supported.
5495 /// isLegalAddressImmediate - Return true if the integer value can be used
5496 /// as the offset of the target addressing mode for load / store of the
5498 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
5499 // PPC allows a sign-extended 16-bit immediate field.
5500 return (V > -(1 << 16) && V < (1 << 16)-1);
5503 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
5507 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
5508 SelectionDAG &DAG) const {
5509 MachineFunction &MF = DAG.getMachineFunction();
5510 MachineFrameInfo *MFI = MF.getFrameInfo();
5511 MFI->setReturnAddressIsTaken(true);
5513 DebugLoc dl = Op.getDebugLoc();
5514 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5516 // Make sure the function does not optimize away the store of the RA to
5518 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
5519 FuncInfo->setLRStoreRequired();
5520 bool isPPC64 = PPCSubTarget.isPPC64();
5521 bool isDarwinABI = PPCSubTarget.isDarwinABI();
5524 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
5527 DAG.getConstant(PPCFrameInfo::getReturnSaveOffset(isPPC64, isDarwinABI),
5528 isPPC64? MVT::i64 : MVT::i32);
5529 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5530 DAG.getNode(ISD::ADD, dl, getPointerTy(),
5532 NULL, 0, false, false, 0);
5535 // Just load the return address off the stack.
5536 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
5537 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
5538 RetAddrFI, NULL, 0, false, false, 0);
5541 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
5542 SelectionDAG &DAG) const {
5543 DebugLoc dl = Op.getDebugLoc();
5544 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
5546 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5547 bool isPPC64 = PtrVT == MVT::i64;
5549 MachineFunction &MF = DAG.getMachineFunction();
5550 MachineFrameInfo *MFI = MF.getFrameInfo();
5551 MFI->setFrameAddressIsTaken(true);
5552 bool is31 = (DisableFramePointerElim(MF) || MFI->hasVarSizedObjects()) &&
5553 MFI->getStackSize() &&
5554 !MF.getFunction()->hasFnAttr(Attribute::Naked);
5555 unsigned FrameReg = isPPC64 ? (is31 ? PPC::X31 : PPC::X1) :
5556 (is31 ? PPC::R31 : PPC::R1);
5557 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
5560 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
5561 FrameAddr, NULL, 0, false, false, 0);
5566 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
5567 // The PowerPC target isn't yet aware of offsets.
5571 /// getOptimalMemOpType - Returns the target specific optimal type for load
5572 /// and store operations as a result of memset, memcpy, and memmove
5573 /// lowering. If DstAlign is zero that means it's safe to destination
5574 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
5575 /// means there isn't a need to check it against alignment requirement,
5576 /// probably because the source does not need to be loaded. If
5577 /// 'NonScalarIntSafe' is true, that means it's safe to return a
5578 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
5579 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
5580 /// constant so it does not need to be loaded.
5581 /// It returns EVT::Other if the type should be determined using generic
5582 /// target-independent logic.
5583 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
5584 unsigned DstAlign, unsigned SrcAlign,
5585 bool NonScalarIntSafe,
5587 MachineFunction &MF) const {
5588 if (this->PPCSubTarget.isPPC64()) {