1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
24 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
25 : TargetLowering(TM) {
27 // Fold away setcc operations if possible.
28 setSetCCIsExpensive();
30 // Set up the register classes.
31 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
32 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
33 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
35 // PowerPC has no intrinsics for these particular operations
36 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
37 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
38 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
40 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
41 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
42 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
44 // PowerPC has no SREM/UREM instructions
45 setOperationAction(ISD::SREM, MVT::i32, Expand);
46 setOperationAction(ISD::UREM, MVT::i32, Expand);
48 // We don't support sin/cos/sqrt/fmod
49 setOperationAction(ISD::FSIN , MVT::f64, Expand);
50 setOperationAction(ISD::FCOS , MVT::f64, Expand);
51 setOperationAction(ISD::SREM , MVT::f64, Expand);
52 setOperationAction(ISD::FSIN , MVT::f32, Expand);
53 setOperationAction(ISD::FCOS , MVT::f32, Expand);
54 setOperationAction(ISD::SREM , MVT::f32, Expand);
56 // If we're enabling GP optimizations, use hardware square root
57 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
58 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
59 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
62 // PowerPC does not have CTPOP or CTTZ
63 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
64 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
66 // PowerPC does not have Select
67 setOperationAction(ISD::SELECT, MVT::i32, Expand);
68 setOperationAction(ISD::SELECT, MVT::f32, Expand);
69 setOperationAction(ISD::SELECT, MVT::f64, Expand);
71 // PowerPC wants to turn select_cc of FP into fsel when possible.
72 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
73 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
75 // PowerPC wants to expand i64 shifts itself.
76 setOperationAction(ISD::SHL, MVT::i64, Custom);
77 setOperationAction(ISD::SRL, MVT::i64, Custom);
78 setOperationAction(ISD::SRA, MVT::i64, Custom);
80 // PowerPC does not have BRCOND* which requires SetCC
81 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
82 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
84 // PowerPC does not have FP_TO_UINT
85 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
87 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
88 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
90 // PowerPC does not have [U|S]INT_TO_FP
91 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
92 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
94 // PowerPC does not have truncstore for i1.
95 setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
97 // 64 bit PowerPC implementations have instructions to facilitate conversion
98 // between i64 and fp.
99 if (TM.getSubtarget<PPCSubtarget>().is64Bit()) {
100 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
101 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
104 setSetCCResultContents(ZeroOrOneSetCCResult);
106 computeRegisterProperties();
109 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
110 static bool isFloatingPointZero(SDOperand Op) {
111 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
112 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
113 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
114 // Maybe this has already been legalized into the constant pool?
115 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
116 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
117 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
122 /// LowerOperation - Provide custom lowering hooks for some operations.
124 SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
125 switch (Op.getOpcode()) {
126 default: assert(0 && "Wasn't expecting to be able to lower this!");
127 case ISD::FP_TO_SINT: {
128 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
129 switch (Op.getValueType()) {
130 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
132 Op = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Op.getOperand(0));
135 Op = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Op.getOperand(0));
140 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
141 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
142 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
143 Op, FI, DAG.getSrcValue(0));
144 if (Op.getOpcode() == PPCISD::FCTIDZ) {
145 Op = DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
147 FI = DAG.getNode(ISD::ADD, MVT::i32, FI, DAG.getConstant(4, MVT::i32));
148 Op = DAG.getLoad(MVT::i32, ST, FI, DAG.getSrcValue(0));
152 case ISD::SINT_TO_FP: {
153 assert(MVT::i64 == Op.getOperand(0).getValueType() &&
154 "Unhandled SINT_TO_FP type in custom expander!");
156 DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
157 SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i32);
158 SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
159 Op.getOperand(0), FI, DAG.getSrcValue(0));
160 SDOperand LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
161 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, LD);
162 if (MVT::f32 == Op.getValueType())
163 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP);
166 case ISD::SELECT_CC: {
167 // Turn FP only select_cc's into fsel instructions.
168 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
169 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
172 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
174 // Cannot handle SETEQ/SETNE.
175 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
177 MVT::ValueType ResVT = Op.getValueType();
178 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
179 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
180 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
182 // If the RHS of the comparison is a 0.0, we don't need to do the
183 // subtraction at all.
184 if (isFloatingPointZero(RHS))
186 default: assert(0 && "Invalid FSEL condition"); abort();
189 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
192 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
195 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
198 return DAG.getNode(PPCISD::FSEL, ResVT,
199 DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
203 default: assert(0 && "Invalid FSEL condition"); abort();
206 return DAG.getNode(PPCISD::FSEL, ResVT,
207 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
210 return DAG.getNode(PPCISD::FSEL, ResVT,
211 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
214 return DAG.getNode(PPCISD::FSEL, ResVT,
215 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
218 return DAG.getNode(PPCISD::FSEL, ResVT,
219 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
224 assert(Op.getValueType() == MVT::i64 &&
225 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
226 // The generic code does a fine job expanding shift by a constant.
227 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
229 // Otherwise, expand into a bunch of logical ops. Note that these ops
230 // depend on the PPC behavior for oversized shift amounts.
231 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
232 DAG.getConstant(0, MVT::i32));
233 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
234 DAG.getConstant(1, MVT::i32));
235 SDOperand Amt = Op.getOperand(1);
237 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
238 DAG.getConstant(32, MVT::i32), Amt);
239 SDOperand Tmp2 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Amt);
240 SDOperand Tmp3 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Tmp1);
241 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
242 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
243 DAG.getConstant(-32U, MVT::i32));
244 SDOperand Tmp6 = DAG.getNode(ISD::SHL, MVT::i32, Lo, Tmp5);
245 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
246 SDOperand OutLo = DAG.getNode(ISD::SHL, MVT::i32, Lo, Amt);
247 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
250 assert(Op.getValueType() == MVT::i64 &&
251 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
252 // The generic code does a fine job expanding shift by a constant.
253 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
255 // Otherwise, expand into a bunch of logical ops. Note that these ops
256 // depend on the PPC behavior for oversized shift amounts.
257 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
258 DAG.getConstant(0, MVT::i32));
259 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
260 DAG.getConstant(1, MVT::i32));
261 SDOperand Amt = Op.getOperand(1);
263 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
264 DAG.getConstant(32, MVT::i32), Amt);
265 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
266 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
267 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
268 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
269 DAG.getConstant(-32U, MVT::i32));
270 SDOperand Tmp6 = DAG.getNode(ISD::SRL, MVT::i32, Hi, Tmp5);
271 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
272 SDOperand OutHi = DAG.getNode(ISD::SRL, MVT::i32, Hi, Amt);
273 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
276 assert(Op.getValueType() == MVT::i64 &&
277 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
278 // The generic code does a fine job expanding shift by a constant.
279 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
281 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
282 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
283 DAG.getConstant(0, MVT::i32));
284 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
285 DAG.getConstant(1, MVT::i32));
286 SDOperand Amt = Op.getOperand(1);
288 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
289 DAG.getConstant(32, MVT::i32), Amt);
290 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
291 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
292 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
293 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
294 DAG.getConstant(-32U, MVT::i32));
295 SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
296 SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
297 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
298 Tmp4, Tmp6, ISD::SETLE);
299 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
305 std::vector<SDOperand>
306 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
308 // add beautiful description of PPC stack frame format, or at least some docs
310 MachineFunction &MF = DAG.getMachineFunction();
311 MachineFrameInfo *MFI = MF.getFrameInfo();
312 MachineBasicBlock& BB = MF.front();
313 std::vector<SDOperand> ArgValues;
315 // Due to the rather complicated nature of the PowerPC ABI, rather than a
316 // fixed size array of physical args, for the sake of simplicity let the STL
317 // handle tracking them for us.
318 std::vector<unsigned> argVR, argPR, argOp;
319 unsigned ArgOffset = 24;
320 unsigned GPR_remaining = 8;
321 unsigned FPR_remaining = 13;
322 unsigned GPR_idx = 0, FPR_idx = 0;
323 static const unsigned GPR[] = {
324 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
325 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
327 static const unsigned FPR[] = {
328 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
329 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
332 // Add DAG nodes to load the arguments... On entry to a function on PPC,
333 // the arguments start at offset 24, although they are likely to be passed
335 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
336 SDOperand newroot, argt;
338 bool needsLoad = false;
339 bool ArgLive = !I->use_empty();
340 MVT::ValueType ObjectVT = getValueType(I->getType());
343 default: assert(0 && "Unhandled argument type!");
350 if (GPR_remaining > 0) {
351 MF.addLiveIn(GPR[GPR_idx]);
352 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
353 GPR[GPR_idx], MVT::i32);
354 if (ObjectVT != MVT::i32) {
355 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
357 argt = DAG.getNode(AssertOp, MVT::i32, argt,
358 DAG.getValueType(ObjectVT));
359 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
365 case MVT::i64: ObjSize = 8;
367 if (GPR_remaining > 0) {
368 SDOperand argHi, argLo;
369 MF.addLiveIn(GPR[GPR_idx]);
370 argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
371 // If we have two or more remaining argument registers, then both halves
372 // of the i64 can be sourced from there. Otherwise, the lower half will
373 // have to come off the stack. This can happen when an i64 is preceded
374 // by 28 bytes of arguments.
375 if (GPR_remaining > 1) {
376 MF.addLiveIn(GPR[GPR_idx+1]);
377 argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
379 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
380 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
381 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
382 DAG.getSrcValue(NULL));
384 // Build the outgoing arg thingy
385 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
393 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
395 if (FPR_remaining > 0) {
396 MF.addLiveIn(FPR[FPR_idx]);
397 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
398 FPR[FPR_idx], ObjectVT);
407 // We need to load the argument to a virtual register if we determined above
408 // that we ran out of physical registers of the appropriate type
410 unsigned SubregOffset = 0;
411 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
412 if (ObjectVT == MVT::i16) SubregOffset = 2;
413 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
414 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
415 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
416 DAG.getConstant(SubregOffset, MVT::i32));
417 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
418 DAG.getSrcValue(NULL));
421 // Every 4 bytes of argument space consumes one of the GPRs available for
423 if (GPR_remaining > 0) {
424 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
425 GPR_remaining -= delta;
428 ArgOffset += ObjSize;
430 DAG.setRoot(newroot.getValue(1));
432 ArgValues.push_back(argt);
435 // If the function takes variable number of arguments, make a frame index for
436 // the start of the first vararg value... for expansion of llvm.va_start.
438 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
439 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
440 // If this function is vararg, store any remaining integer argument regs
441 // to their spots on the stack so that they may be loaded by deferencing the
442 // result of va_next.
443 std::vector<SDOperand> MemOps;
444 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
445 MF.addLiveIn(GPR[GPR_idx]);
446 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
447 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
448 Val, FIN, DAG.getSrcValue(NULL));
449 MemOps.push_back(Store);
450 // Increment the address by four for the next argument to store
451 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
452 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
454 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
457 // Finally, inform the code generator which regs we return values in.
458 switch (getValueType(F.getReturnType())) {
459 default: assert(0 && "Unknown type!");
460 case MVT::isVoid: break;
465 MF.addLiveOut(PPC::R3);
468 MF.addLiveOut(PPC::R3);
469 MF.addLiveOut(PPC::R4);
473 MF.addLiveOut(PPC::F1);
480 std::pair<SDOperand, SDOperand>
481 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
482 const Type *RetTy, bool isVarArg,
483 unsigned CallingConv, bool isTailCall,
484 SDOperand Callee, ArgListTy &Args,
486 // args_to_use will accumulate outgoing args for the ISD::CALL case in
487 // SelectExpr to use to put the arguments in the appropriate registers.
488 std::vector<SDOperand> args_to_use;
490 // Count how many bytes are to be pushed on the stack, including the linkage
491 // area, and parameter passing area.
492 unsigned NumBytes = 24;
495 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
496 DAG.getConstant(NumBytes, getPointerTy()));
498 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
499 switch (getValueType(Args[i].second)) {
500 default: assert(0 && "Unknown value type!");
515 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
516 // plus 32 bytes of argument space in case any called code gets funky on us.
517 // (Required by ABI to support var arg)
518 if (NumBytes < 56) NumBytes = 56;
520 // Adjust the stack pointer for the new arguments...
521 // These operations are automatically eliminated by the prolog/epilog pass
522 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
523 DAG.getConstant(NumBytes, getPointerTy()));
525 // Set up a copy of the stack pointer for use loading and storing any
526 // arguments that may not fit in the registers available for argument
528 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
531 // Figure out which arguments are going to go in registers, and which in
532 // memory. Also, if this is a vararg function, floating point operations
533 // must be stored to our stack, and loaded into integer regs as well, if
534 // any integer regs are available for argument passing.
535 unsigned ArgOffset = 24;
536 unsigned GPR_remaining = 8;
537 unsigned FPR_remaining = 13;
539 std::vector<SDOperand> MemOps;
540 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
541 // PtrOff will be used to store the current argument to the stack if a
542 // register cannot be found for it.
543 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
544 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
545 MVT::ValueType ArgVT = getValueType(Args[i].second);
548 default: assert(0 && "Unexpected ValueType for argument!");
552 // Promote the integer to 32 bits. If the input type is signed use a
553 // sign extend, otherwise use a zero extend.
554 if (Args[i].second->isSigned())
555 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
557 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
560 if (GPR_remaining > 0) {
561 args_to_use.push_back(Args[i].first);
564 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
565 Args[i].first, PtrOff,
566 DAG.getSrcValue(NULL)));
571 // If we have one free GPR left, we can place the upper half of the i64
572 // in it, and store the other half to the stack. If we have two or more
573 // free GPRs, then we can pass both halves of the i64 in registers.
574 if (GPR_remaining > 0) {
575 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
576 Args[i].first, DAG.getConstant(1, MVT::i32));
577 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
578 Args[i].first, DAG.getConstant(0, MVT::i32));
579 args_to_use.push_back(Hi);
581 if (GPR_remaining > 0) {
582 args_to_use.push_back(Lo);
585 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
586 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
587 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
588 Lo, PtrOff, DAG.getSrcValue(NULL)));
591 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
592 Args[i].first, PtrOff,
593 DAG.getSrcValue(NULL)));
599 if (FPR_remaining > 0) {
600 args_to_use.push_back(Args[i].first);
603 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
604 Args[i].first, PtrOff,
605 DAG.getSrcValue(NULL));
606 MemOps.push_back(Store);
607 // Float varargs are always shadowed in available integer registers
608 if (GPR_remaining > 0) {
609 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
610 DAG.getSrcValue(NULL));
611 MemOps.push_back(Load);
612 args_to_use.push_back(Load);
615 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
616 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
617 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
618 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
619 DAG.getSrcValue(NULL));
620 MemOps.push_back(Load);
621 args_to_use.push_back(Load);
625 // If we have any FPRs remaining, we may also have GPRs remaining.
626 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
628 if (GPR_remaining > 0) {
629 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
632 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
633 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
638 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
639 Args[i].first, PtrOff,
640 DAG.getSrcValue(NULL)));
642 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
647 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
650 std::vector<MVT::ValueType> RetVals;
651 MVT::ValueType RetTyVT = getValueType(RetTy);
652 MVT::ValueType ActualRetTyVT = RetTyVT;
653 if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i16)
654 ActualRetTyVT = MVT::i32; // Promote result to i32.
656 if (RetTyVT != MVT::isVoid)
657 RetVals.push_back(ActualRetTyVT);
658 RetVals.push_back(MVT::Other);
660 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
661 Chain, Callee, args_to_use), 0);
662 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
663 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
664 DAG.getConstant(NumBytes, getPointerTy()));
665 SDOperand RetVal = TheCall;
667 // If the result is a small value, add a note so that we keep track of the
668 // information about whether it is sign or zero extended.
669 if (RetTyVT != ActualRetTyVT) {
670 RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
671 MVT::i32, RetVal, DAG.getValueType(RetTyVT));
672 RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
675 return std::make_pair(RetVal, Chain);
678 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
679 Value *VAListV, SelectionDAG &DAG) {
680 // vastart just stores the address of the VarArgsFrameIndex slot into the
681 // memory location argument.
682 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
683 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
684 DAG.getSrcValue(VAListV));
687 std::pair<SDOperand,SDOperand>
688 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
689 SDOperand VAListP, Value *VAListV,
690 const Type *ArgTy, SelectionDAG &DAG) {
691 MVT::ValueType ArgVT = getValueType(ArgTy);
694 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
695 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
697 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
700 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
701 "Other types should have been promoted for varargs!");
704 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
705 DAG.getConstant(Amt, VAList.getValueType()));
706 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
707 VAList, VAListP, DAG.getSrcValue(VAListV));
708 return std::make_pair(Result, Chain);
712 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
713 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
715 assert(0 && "LowerFrameReturnAddress unimplemented");
720 PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
721 MachineBasicBlock *BB) {
722 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
723 MI->getOpcode() == PPC::SELECT_CC_FP) &&
724 "Unexpected instr type to insert");
726 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
727 // control-flow pattern. The incoming instruction knows the destination vreg
728 // to set, the condition code register to branch on, the true/false values to
729 // select between, and a branch opcode to use.
730 const BasicBlock *LLVM_BB = BB->getBasicBlock();
731 ilist<MachineBasicBlock>::iterator It = BB;
739 // fallthrough --> copy0MBB
740 MachineBasicBlock *thisMBB = BB;
741 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
742 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
743 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
744 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
745 MachineFunction *F = BB->getParent();
746 F->getBasicBlockList().insert(It, copy0MBB);
747 F->getBasicBlockList().insert(It, sinkMBB);
748 // Update machine-CFG edges
749 BB->addSuccessor(copy0MBB);
750 BB->addSuccessor(sinkMBB);
754 // # fallthrough to sinkMBB
757 // Update machine-CFG edges
758 BB->addSuccessor(sinkMBB);
761 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
764 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
765 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
766 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
768 delete MI; // The pseudo instruction is gone now.