1 //===-- PPC32ISelLowering.cpp - PPC32 DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPC32ISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPC32ISelLowering.h"
15 #include "PPC32TargetMachine.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
20 #include "llvm/Constants.h"
21 #include "llvm/Function.h"
24 PPC32TargetLowering::PPC32TargetLowering(TargetMachine &TM)
25 : TargetLowering(TM) {
27 // Fold away setcc operations if possible.
28 setSetCCIsExpensive();
30 // Set up the register classes.
31 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
32 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
33 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
35 // PowerPC has no intrinsics for these particular operations
36 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
37 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
38 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
40 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
41 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
42 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
44 // PowerPC has no SREM/UREM instructions
45 setOperationAction(ISD::SREM, MVT::i32, Expand);
46 setOperationAction(ISD::UREM, MVT::i32, Expand);
48 // We don't support sin/cos/sqrt/fmod
49 setOperationAction(ISD::FSIN , MVT::f64, Expand);
50 setOperationAction(ISD::FCOS , MVT::f64, Expand);
51 setOperationAction(ISD::SREM , MVT::f64, Expand);
52 setOperationAction(ISD::FSIN , MVT::f32, Expand);
53 setOperationAction(ISD::FCOS , MVT::f32, Expand);
54 setOperationAction(ISD::SREM , MVT::f32, Expand);
56 // If we're enabling GP optimizations, use hardware square root
57 if (!TM.getSubtarget<PPCSubtarget>().isGigaProcessor()) {
58 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
59 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
62 // PowerPC does not have CTPOP or CTTZ
63 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
64 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
66 // PowerPC does not have Select
67 setOperationAction(ISD::SELECT, MVT::i32, Expand);
68 setOperationAction(ISD::SELECT, MVT::f32, Expand);
69 setOperationAction(ISD::SELECT, MVT::f64, Expand);
71 // PowerPC wants to turn select_cc of FP into fsel when possible.
72 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
73 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
75 // PowerPC wants to expand SRA_PARTS into SELECT_CC and stuff.
76 setOperationAction(ISD::SRA, MVT::i64, Custom);
78 // PowerPC does not have BRCOND* which requires SetCC
79 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
80 setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
82 // PowerPC does not have FP_TO_UINT
83 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
85 // PowerPC does not have [U|S]INT_TO_FP
86 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
87 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
89 setSetCCResultContents(ZeroOrOneSetCCResult);
91 computeRegisterProperties();
94 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
95 static bool isFloatingPointZero(SDOperand Op) {
96 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
97 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
98 else if (Op.getOpcode() == ISD::EXTLOAD || Op.getOpcode() == ISD::LOAD) {
99 // Maybe this has already been legalized into the constant pool?
100 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
101 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->get()))
102 return CFP->isExactlyValue(-0.0) || CFP->isExactlyValue(0.0);
107 /// LowerOperation - Provide custom lowering hooks for some operations.
109 SDOperand PPC32TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
110 switch (Op.getOpcode()) {
111 default: assert(0 && "Wasn't expecting to be able to lower this!");
113 // Turn FP only select_cc's into fsel instructions.
114 if (MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
115 MVT::isFloatingPoint(Op.getOperand(2).getValueType())) {
116 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
118 // Cannot handle SETEQ/SETNE.
119 if (CC == ISD::SETEQ || CC == ISD::SETNE) break;
121 MVT::ValueType ResVT = Op.getValueType();
122 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
123 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
124 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
126 // If the RHS of the comparison is a 0.0, we don't need to do the
127 // subtraction at all.
128 if (isFloatingPointZero(RHS))
130 default: assert(0 && "Invalid FSEL condition"); abort();
133 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
136 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
139 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
142 return DAG.getNode(PPCISD::FSEL, ResVT,
143 DAG.getNode(ISD::FNEG, ResVT, LHS), TV, FV);
147 default: assert(0 && "Invalid FSEL condition"); abort();
150 return DAG.getNode(PPCISD::FSEL, ResVT,
151 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), FV, TV);
154 return DAG.getNode(PPCISD::FSEL, ResVT,
155 DAG.getNode(ISD::SUB, CmpVT, LHS, RHS), TV, FV);
158 return DAG.getNode(PPCISD::FSEL, ResVT,
159 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), FV, TV);
162 return DAG.getNode(PPCISD::FSEL, ResVT,
163 DAG.getNode(ISD::SUB, CmpVT, RHS, LHS), TV, FV);
168 assert(Op.getValueType() == MVT::i64 &&
169 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
170 // The generic code does a fine job expanding shift by a constant.
171 if (isa<ConstantSDNode>(Op.getOperand(1))) break;
173 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
174 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
175 DAG.getConstant(0, MVT::i32));
176 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Op.getOperand(0),
177 DAG.getConstant(1, MVT::i32));
178 SDOperand Amt = Op.getOperand(1);
180 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
181 DAG.getConstant(32, MVT::i32), Amt);
182 SDOperand Tmp2 = DAG.getNode(ISD::SRL, MVT::i32, Lo, Amt);
183 SDOperand Tmp3 = DAG.getNode(ISD::SHL, MVT::i32, Hi, Tmp1);
184 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
185 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
186 DAG.getConstant(-32U, MVT::i32));
187 SDOperand Tmp6 = DAG.getNode(ISD::SRA, MVT::i32, Hi, Tmp5);
188 SDOperand OutHi = DAG.getNode(ISD::SRA, MVT::i32, Hi, Amt);
189 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
190 Tmp4, Tmp6, ISD::SETLE);
191 return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, OutLo, OutHi);
196 std::vector<SDOperand>
197 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
199 // add beautiful description of PPC stack frame format, or at least some docs
201 MachineFunction &MF = DAG.getMachineFunction();
202 MachineFrameInfo *MFI = MF.getFrameInfo();
203 MachineBasicBlock& BB = MF.front();
204 std::vector<SDOperand> ArgValues;
206 // Due to the rather complicated nature of the PowerPC ABI, rather than a
207 // fixed size array of physical args, for the sake of simplicity let the STL
208 // handle tracking them for us.
209 std::vector<unsigned> argVR, argPR, argOp;
210 unsigned ArgOffset = 24;
211 unsigned GPR_remaining = 8;
212 unsigned FPR_remaining = 13;
213 unsigned GPR_idx = 0, FPR_idx = 0;
214 static const unsigned GPR[] = {
215 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
216 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
218 static const unsigned FPR[] = {
219 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
220 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
223 // Add DAG nodes to load the arguments... On entry to a function on PPC,
224 // the arguments start at offset 24, although they are likely to be passed
226 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
227 SDOperand newroot, argt;
229 bool needsLoad = false;
230 bool ArgLive = !I->use_empty();
231 MVT::ValueType ObjectVT = getValueType(I->getType());
234 default: assert(0 && "Unhandled argument type!");
241 if (GPR_remaining > 0) {
242 MF.addLiveIn(GPR[GPR_idx]);
243 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
244 GPR[GPR_idx], MVT::i32);
245 if (ObjectVT != MVT::i32) {
246 unsigned AssertOp = I->getType()->isSigned() ? ISD::AssertSext
248 argt = DAG.getNode(AssertOp, MVT::i32, argt,
249 DAG.getValueType(ObjectVT));
250 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, argt);
256 case MVT::i64: ObjSize = 8;
258 if (GPR_remaining > 0) {
259 SDOperand argHi, argLo;
260 MF.addLiveIn(GPR[GPR_idx]);
261 argHi = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
262 // If we have two or more remaining argument registers, then both halves
263 // of the i64 can be sourced from there. Otherwise, the lower half will
264 // have to come off the stack. This can happen when an i64 is preceded
265 // by 28 bytes of arguments.
266 if (GPR_remaining > 1) {
267 MF.addLiveIn(GPR[GPR_idx+1]);
268 argLo = DAG.getCopyFromReg(argHi, GPR[GPR_idx+1], MVT::i32);
270 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
271 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
272 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
273 DAG.getSrcValue(NULL));
275 // Build the outgoing arg thingy
276 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
284 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
286 if (FPR_remaining > 0) {
287 MF.addLiveIn(FPR[FPR_idx]);
288 argt = newroot = DAG.getCopyFromReg(DAG.getRoot(),
289 FPR[FPR_idx], ObjectVT);
298 // We need to load the argument to a virtual register if we determined above
299 // that we ran out of physical registers of the appropriate type
301 unsigned SubregOffset = 0;
302 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
303 if (ObjectVT == MVT::i16) SubregOffset = 2;
304 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
305 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
306 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
307 DAG.getConstant(SubregOffset, MVT::i32));
308 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
309 DAG.getSrcValue(NULL));
312 // Every 4 bytes of argument space consumes one of the GPRs available for
314 if (GPR_remaining > 0) {
315 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
316 GPR_remaining -= delta;
319 ArgOffset += ObjSize;
321 DAG.setRoot(newroot.getValue(1));
323 ArgValues.push_back(argt);
326 // If the function takes variable number of arguments, make a frame index for
327 // the start of the first vararg value... for expansion of llvm.va_start.
329 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
330 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
331 // If this function is vararg, store any remaining integer argument regs
332 // to their spots on the stack so that they may be loaded by deferencing the
333 // result of va_next.
334 std::vector<SDOperand> MemOps;
335 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
336 MF.addLiveIn(GPR[GPR_idx]);
337 SDOperand Val = DAG.getCopyFromReg(DAG.getRoot(), GPR[GPR_idx], MVT::i32);
338 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
339 Val, FIN, DAG.getSrcValue(NULL));
340 MemOps.push_back(Store);
341 // Increment the address by four for the next argument to store
342 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
343 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
345 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
348 // Finally, inform the code generator which regs we return values in.
349 switch (getValueType(F.getReturnType())) {
350 default: assert(0 && "Unknown type!");
351 case MVT::isVoid: break;
356 MF.addLiveOut(PPC::R3);
359 MF.addLiveOut(PPC::R3);
360 MF.addLiveOut(PPC::R4);
364 MF.addLiveOut(PPC::F1);
371 std::pair<SDOperand, SDOperand>
372 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
373 const Type *RetTy, bool isVarArg,
374 unsigned CallingConv, bool isTailCall,
375 SDOperand Callee, ArgListTy &Args,
377 // args_to_use will accumulate outgoing args for the ISD::CALL case in
378 // SelectExpr to use to put the arguments in the appropriate registers.
379 std::vector<SDOperand> args_to_use;
381 // Count how many bytes are to be pushed on the stack, including the linkage
382 // area, and parameter passing area.
383 unsigned NumBytes = 24;
386 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
387 DAG.getConstant(NumBytes, getPointerTy()));
389 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
390 switch (getValueType(Args[i].second)) {
391 default: assert(0 && "Unknown value type!");
406 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
407 // plus 32 bytes of argument space in case any called code gets funky on us.
408 // (Required by ABI to support var arg)
409 if (NumBytes < 56) NumBytes = 56;
411 // Adjust the stack pointer for the new arguments...
412 // These operations are automatically eliminated by the prolog/epilog pass
413 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
414 DAG.getConstant(NumBytes, getPointerTy()));
416 // Set up a copy of the stack pointer for use loading and storing any
417 // arguments that may not fit in the registers available for argument
419 SDOperand StackPtr = DAG.getCopyFromReg(DAG.getEntryNode(),
422 // Figure out which arguments are going to go in registers, and which in
423 // memory. Also, if this is a vararg function, floating point operations
424 // must be stored to our stack, and loaded into integer regs as well, if
425 // any integer regs are available for argument passing.
426 unsigned ArgOffset = 24;
427 unsigned GPR_remaining = 8;
428 unsigned FPR_remaining = 13;
430 std::vector<SDOperand> MemOps;
431 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
432 // PtrOff will be used to store the current argument to the stack if a
433 // register cannot be found for it.
434 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
435 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
436 MVT::ValueType ArgVT = getValueType(Args[i].second);
439 default: assert(0 && "Unexpected ValueType for argument!");
443 // Promote the integer to 32 bits. If the input type is signed use a
444 // sign extend, otherwise use a zero extend.
445 if (Args[i].second->isSigned())
446 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
448 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
451 if (GPR_remaining > 0) {
452 args_to_use.push_back(Args[i].first);
455 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
456 Args[i].first, PtrOff,
457 DAG.getSrcValue(NULL)));
462 // If we have one free GPR left, we can place the upper half of the i64
463 // in it, and store the other half to the stack. If we have two or more
464 // free GPRs, then we can pass both halves of the i64 in registers.
465 if (GPR_remaining > 0) {
466 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
467 Args[i].first, DAG.getConstant(1, MVT::i32));
468 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
469 Args[i].first, DAG.getConstant(0, MVT::i32));
470 args_to_use.push_back(Hi);
472 if (GPR_remaining > 0) {
473 args_to_use.push_back(Lo);
476 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
477 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
478 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
479 Lo, PtrOff, DAG.getSrcValue(NULL)));
482 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
483 Args[i].first, PtrOff,
484 DAG.getSrcValue(NULL)));
490 if (FPR_remaining > 0) {
491 args_to_use.push_back(Args[i].first);
494 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
495 Args[i].first, PtrOff,
496 DAG.getSrcValue(NULL));
497 MemOps.push_back(Store);
498 // Float varargs are always shadowed in available integer registers
499 if (GPR_remaining > 0) {
500 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
501 DAG.getSrcValue(NULL));
502 MemOps.push_back(Load);
503 args_to_use.push_back(Load);
506 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
507 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
508 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
509 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
510 DAG.getSrcValue(NULL));
511 MemOps.push_back(Load);
512 args_to_use.push_back(Load);
516 // If we have any FPRs remaining, we may also have GPRs remaining.
517 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
519 if (GPR_remaining > 0) {
520 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
523 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
524 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
529 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
530 Args[i].first, PtrOff,
531 DAG.getSrcValue(NULL)));
533 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
538 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
541 std::vector<MVT::ValueType> RetVals;
542 MVT::ValueType RetTyVT = getValueType(RetTy);
543 if (RetTyVT != MVT::isVoid)
544 RetVals.push_back(RetTyVT);
545 RetVals.push_back(MVT::Other);
547 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
548 Chain, Callee, args_to_use), 0);
549 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
550 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
551 DAG.getConstant(NumBytes, getPointerTy()));
552 return std::make_pair(TheCall, Chain);
555 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
556 Value *VAListV, SelectionDAG &DAG) {
557 // vastart just stores the address of the VarArgsFrameIndex slot into the
558 // memory location argument.
559 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
560 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
561 DAG.getSrcValue(VAListV));
564 std::pair<SDOperand,SDOperand>
565 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
566 SDOperand VAListP, Value *VAListV,
567 const Type *ArgTy, SelectionDAG &DAG) {
568 MVT::ValueType ArgVT = getValueType(ArgTy);
571 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
572 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
574 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
577 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
578 "Other types should have been promoted for varargs!");
581 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
582 DAG.getConstant(Amt, VAList.getValueType()));
583 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
584 VAList, VAListP, DAG.getSrcValue(VAListV));
585 return std::make_pair(Result, Chain);
589 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
590 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
592 assert(0 && "LowerFrameReturnAddress unimplemented");
597 PPC32TargetLowering::InsertAtEndOfBasicBlock(MachineInstr *MI,
598 MachineBasicBlock *BB) {
599 assert((MI->getOpcode() == PPC::SELECT_CC_Int ||
600 MI->getOpcode() == PPC::SELECT_CC_FP) &&
601 "Unexpected instr type to insert");
603 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
604 // control-flow pattern. The incoming instruction knows the destination vreg
605 // to set, the condition code register to branch on, the true/false values to
606 // select between, and a branch opcode to use.
607 const BasicBlock *LLVM_BB = BB->getBasicBlock();
608 ilist<MachineBasicBlock>::iterator It = BB;
616 // fallthrough --> copy0MBB
617 MachineBasicBlock *thisMBB = BB;
618 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
619 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
620 BuildMI(BB, MI->getOperand(4).getImmedValue(), 2)
621 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
622 MachineFunction *F = BB->getParent();
623 F->getBasicBlockList().insert(It, copy0MBB);
624 F->getBasicBlockList().insert(It, sinkMBB);
625 // Update machine-CFG edges
626 BB->addSuccessor(copy0MBB);
627 BB->addSuccessor(sinkMBB);
631 // # fallthrough to sinkMBB
634 // Update machine-CFG edges
635 BB->addSuccessor(sinkMBB);
638 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
641 BuildMI(BB, PPC::PHI, 4, MI->getOperand(0).getReg())
642 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
643 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
645 delete MI; // The pseudo instruction is gone now.