1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "PPCMachineFunctionInfo.h"
16 #include "PPCPredicates.h"
17 #include "PPCTargetMachine.h"
18 #include "PPCPerfectShuffle.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/ADT/VectorExtras.h"
21 #include "llvm/Analysis/ScalarEvolutionExpressions.h"
22 #include "llvm/CodeGen/CallingConvLower.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/PseudoSourceValue.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/Constants.h"
30 #include "llvm/Function.h"
31 #include "llvm/Intrinsics.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/Target/TargetOptions.h"
34 #include "llvm/Support/CommandLine.h"
37 static cl::opt<bool> EnablePPCPreinc("enable-ppc-preinc",
38 cl::desc("enable preincrement load/store generation on PPC (experimental)"),
41 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
42 : TargetLowering(TM), PPCSubTarget(*TM.getSubtargetImpl()) {
46 // Use _setjmp/_longjmp instead of setjmp/longjmp.
47 setUseUnderscoreSetJmp(true);
48 setUseUnderscoreLongJmp(true);
50 // Set up the register classes.
51 addRegisterClass(MVT::i32, PPC::GPRCRegisterClass);
52 addRegisterClass(MVT::f32, PPC::F4RCRegisterClass);
53 addRegisterClass(MVT::f64, PPC::F8RCRegisterClass);
55 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
56 setLoadXAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadXAction(ISD::SEXTLOAD, MVT::i8, Expand);
59 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
61 // PowerPC has pre-inc load and store's.
62 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
63 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
64 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
65 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
66 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
67 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
68 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
69 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
70 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
71 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
73 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
74 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
76 // Shortening conversions involving ppcf128 get expanded (2 regs -> 1 reg)
77 setConvertAction(MVT::ppcf128, MVT::f64, Expand);
78 setConvertAction(MVT::ppcf128, MVT::f32, Expand);
79 // This is used in the ppcf128->int sequence. Note it has different semantics
80 // from FP_ROUND: that rounds to nearest, this rounds to zero.
81 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
83 // PowerPC has no intrinsics for these particular operations
84 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
85 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
86 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
88 // PowerPC has no SREM/UREM instructions
89 setOperationAction(ISD::SREM, MVT::i32, Expand);
90 setOperationAction(ISD::UREM, MVT::i32, Expand);
91 setOperationAction(ISD::SREM, MVT::i64, Expand);
92 setOperationAction(ISD::UREM, MVT::i64, Expand);
94 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
95 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
96 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
97 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
98 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
99 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
100 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
101 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
102 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
104 // We don't support sin/cos/sqrt/fmod/pow
105 setOperationAction(ISD::FSIN , MVT::f64, Expand);
106 setOperationAction(ISD::FCOS , MVT::f64, Expand);
107 setOperationAction(ISD::FREM , MVT::f64, Expand);
108 setOperationAction(ISD::FPOW , MVT::f64, Expand);
109 setOperationAction(ISD::FSIN , MVT::f32, Expand);
110 setOperationAction(ISD::FCOS , MVT::f32, Expand);
111 setOperationAction(ISD::FREM , MVT::f32, Expand);
112 setOperationAction(ISD::FPOW , MVT::f32, Expand);
114 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
116 // If we're enabling GP optimizations, use hardware square root
117 if (!TM.getSubtarget<PPCSubtarget>().hasFSQRT()) {
118 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
119 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
122 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
123 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
125 // PowerPC does not have BSWAP, CTPOP or CTTZ
126 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
127 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
128 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
129 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
130 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
131 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
133 // PowerPC does not have ROTR
134 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
136 // PowerPC does not have Select
137 setOperationAction(ISD::SELECT, MVT::i32, Expand);
138 setOperationAction(ISD::SELECT, MVT::i64, Expand);
139 setOperationAction(ISD::SELECT, MVT::f32, Expand);
140 setOperationAction(ISD::SELECT, MVT::f64, Expand);
142 // PowerPC wants to turn select_cc of FP into fsel when possible.
143 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
144 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
146 // PowerPC wants to optimize integer setcc a bit
147 setOperationAction(ISD::SETCC, MVT::i32, Custom);
149 // PowerPC does not have BRCOND which requires SetCC
150 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
152 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
154 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
155 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
157 // PowerPC does not have [U|S]INT_TO_FP
158 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
159 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
161 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
162 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
163 setOperationAction(ISD::BIT_CONVERT, MVT::i64, Expand);
164 setOperationAction(ISD::BIT_CONVERT, MVT::f64, Expand);
166 // We cannot sextinreg(i1). Expand to shifts.
167 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
169 // Support label based line numbers.
170 setOperationAction(ISD::LOCATION, MVT::Other, Expand);
171 setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
173 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand);
174 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand);
175 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand);
176 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand);
179 // We want to legalize GlobalAddress and ConstantPool nodes into the
180 // appropriate instructions to materialize the address.
181 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
182 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
183 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
184 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
185 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
186 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
187 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
188 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
190 // RET must be custom lowered, to meet ABI requirements
191 setOperationAction(ISD::RET , MVT::Other, Custom);
193 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
194 setOperationAction(ISD::VASTART , MVT::Other, Custom);
196 // VAARG is custom lowered with ELF 32 ABI
197 if (TM.getSubtarget<PPCSubtarget>().isELF32_ABI())
198 setOperationAction(ISD::VAARG, MVT::Other, Custom);
200 setOperationAction(ISD::VAARG, MVT::Other, Expand);
202 // Use the default implementation.
203 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
204 setOperationAction(ISD::VAEND , MVT::Other, Expand);
205 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
206 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
207 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
208 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
210 // We want to custom lower some of our intrinsics.
211 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
213 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
214 // They also have instructions for converting between i64 and fp.
215 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
216 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
217 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
218 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
219 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
221 // FIXME: disable this lowered code. This generates 64-bit register values,
222 // and we don't model the fact that the top part is clobbered by calls. We
223 // need to flag these together so that the value isn't live across a call.
224 //setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
226 // To take advantage of the above i64 FP_TO_SINT, promote i32 FP_TO_UINT
227 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Promote);
229 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
230 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
233 if (TM.getSubtarget<PPCSubtarget>().use64BitRegs()) {
234 // 64-bit PowerPC implementations can support i64 types directly
235 addRegisterClass(MVT::i64, PPC::G8RCRegisterClass);
236 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
237 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
239 // 32-bit PowerPC wants to expand i64 shifts itself.
240 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
241 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
242 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
245 if (TM.getSubtarget<PPCSubtarget>().hasAltivec()) {
246 // First set operation action for all vector types to expand. Then we
247 // will selectively turn on ones that can be effectively codegen'd.
248 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
249 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) {
250 // add/sub are legal for all supported vector VT's.
251 setOperationAction(ISD::ADD , (MVT::ValueType)VT, Legal);
252 setOperationAction(ISD::SUB , (MVT::ValueType)VT, Legal);
254 // We promote all shuffles to v16i8.
255 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, Promote);
256 AddPromotedToType (ISD::VECTOR_SHUFFLE, (MVT::ValueType)VT, MVT::v16i8);
258 // We promote all non-typed operations to v4i32.
259 setOperationAction(ISD::AND , (MVT::ValueType)VT, Promote);
260 AddPromotedToType (ISD::AND , (MVT::ValueType)VT, MVT::v4i32);
261 setOperationAction(ISD::OR , (MVT::ValueType)VT, Promote);
262 AddPromotedToType (ISD::OR , (MVT::ValueType)VT, MVT::v4i32);
263 setOperationAction(ISD::XOR , (MVT::ValueType)VT, Promote);
264 AddPromotedToType (ISD::XOR , (MVT::ValueType)VT, MVT::v4i32);
265 setOperationAction(ISD::LOAD , (MVT::ValueType)VT, Promote);
266 AddPromotedToType (ISD::LOAD , (MVT::ValueType)VT, MVT::v4i32);
267 setOperationAction(ISD::SELECT, (MVT::ValueType)VT, Promote);
268 AddPromotedToType (ISD::SELECT, (MVT::ValueType)VT, MVT::v4i32);
269 setOperationAction(ISD::STORE, (MVT::ValueType)VT, Promote);
270 AddPromotedToType (ISD::STORE, (MVT::ValueType)VT, MVT::v4i32);
272 // No other operations are legal.
273 setOperationAction(ISD::MUL , (MVT::ValueType)VT, Expand);
274 setOperationAction(ISD::SDIV, (MVT::ValueType)VT, Expand);
275 setOperationAction(ISD::SREM, (MVT::ValueType)VT, Expand);
276 setOperationAction(ISD::UDIV, (MVT::ValueType)VT, Expand);
277 setOperationAction(ISD::UREM, (MVT::ValueType)VT, Expand);
278 setOperationAction(ISD::FDIV, (MVT::ValueType)VT, Expand);
279 setOperationAction(ISD::FNEG, (MVT::ValueType)VT, Expand);
280 setOperationAction(ISD::EXTRACT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
281 setOperationAction(ISD::INSERT_VECTOR_ELT, (MVT::ValueType)VT, Expand);
282 setOperationAction(ISD::BUILD_VECTOR, (MVT::ValueType)VT, Expand);
283 setOperationAction(ISD::UMUL_LOHI, (MVT::ValueType)VT, Expand);
284 setOperationAction(ISD::SMUL_LOHI, (MVT::ValueType)VT, Expand);
285 setOperationAction(ISD::UDIVREM, (MVT::ValueType)VT, Expand);
286 setOperationAction(ISD::SDIVREM, (MVT::ValueType)VT, Expand);
287 setOperationAction(ISD::SCALAR_TO_VECTOR, (MVT::ValueType)VT, Expand);
288 setOperationAction(ISD::FPOW, (MVT::ValueType)VT, Expand);
289 setOperationAction(ISD::CTPOP, (MVT::ValueType)VT, Expand);
290 setOperationAction(ISD::CTLZ, (MVT::ValueType)VT, Expand);
291 setOperationAction(ISD::CTTZ, (MVT::ValueType)VT, Expand);
294 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
295 // with merges, splats, etc.
296 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
298 setOperationAction(ISD::AND , MVT::v4i32, Legal);
299 setOperationAction(ISD::OR , MVT::v4i32, Legal);
300 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
301 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
302 setOperationAction(ISD::SELECT, MVT::v4i32, Expand);
303 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
305 addRegisterClass(MVT::v4f32, PPC::VRRCRegisterClass);
306 addRegisterClass(MVT::v4i32, PPC::VRRCRegisterClass);
307 addRegisterClass(MVT::v8i16, PPC::VRRCRegisterClass);
308 addRegisterClass(MVT::v16i8, PPC::VRRCRegisterClass);
310 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
311 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
312 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
313 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
315 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
316 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
318 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
319 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
320 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
321 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
324 setSetCCResultType(MVT::i32);
325 setShiftAmountType(MVT::i32);
326 setSetCCResultContents(ZeroOrOneSetCCResult);
328 if (TM.getSubtarget<PPCSubtarget>().isPPC64()) {
329 setStackPointerRegisterToSaveRestore(PPC::X1);
330 setExceptionPointerRegister(PPC::X3);
331 setExceptionSelectorRegister(PPC::X4);
333 setStackPointerRegisterToSaveRestore(PPC::R1);
334 setExceptionPointerRegister(PPC::R3);
335 setExceptionSelectorRegister(PPC::R4);
338 // We have target-specific dag combine patterns for the following nodes:
339 setTargetDAGCombine(ISD::SINT_TO_FP);
340 setTargetDAGCombine(ISD::STORE);
341 setTargetDAGCombine(ISD::BR_CC);
342 setTargetDAGCombine(ISD::BSWAP);
344 // Darwin long double math library functions have $LDBL128 appended.
345 if (TM.getSubtarget<PPCSubtarget>().isDarwin()) {
346 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
347 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
348 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
349 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
350 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
353 computeRegisterProperties();
356 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
359 case PPCISD::FSEL: return "PPCISD::FSEL";
360 case PPCISD::FCFID: return "PPCISD::FCFID";
361 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
362 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
363 case PPCISD::STFIWX: return "PPCISD::STFIWX";
364 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
365 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
366 case PPCISD::VPERM: return "PPCISD::VPERM";
367 case PPCISD::Hi: return "PPCISD::Hi";
368 case PPCISD::Lo: return "PPCISD::Lo";
369 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
370 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
371 case PPCISD::SRL: return "PPCISD::SRL";
372 case PPCISD::SRA: return "PPCISD::SRA";
373 case PPCISD::SHL: return "PPCISD::SHL";
374 case PPCISD::EXTSW_32: return "PPCISD::EXTSW_32";
375 case PPCISD::STD_32: return "PPCISD::STD_32";
376 case PPCISD::CALL_ELF: return "PPCISD::CALL_ELF";
377 case PPCISD::CALL_Macho: return "PPCISD::CALL_Macho";
378 case PPCISD::MTCTR: return "PPCISD::MTCTR";
379 case PPCISD::BCTRL_Macho: return "PPCISD::BCTRL_Macho";
380 case PPCISD::BCTRL_ELF: return "PPCISD::BCTRL_ELF";
381 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
382 case PPCISD::MFCR: return "PPCISD::MFCR";
383 case PPCISD::VCMP: return "PPCISD::VCMP";
384 case PPCISD::VCMPo: return "PPCISD::VCMPo";
385 case PPCISD::LBRX: return "PPCISD::LBRX";
386 case PPCISD::STBRX: return "PPCISD::STBRX";
387 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
388 case PPCISD::MFFS: return "PPCISD::MFFS";
389 case PPCISD::MTFSB0: return "PPCISD::MTFSB0";
390 case PPCISD::MTFSB1: return "PPCISD::MTFSB1";
391 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
392 case PPCISD::MTFSF: return "PPCISD::MTFSF";
396 //===----------------------------------------------------------------------===//
397 // Node matching predicates, for use by the tblgen matching code.
398 //===----------------------------------------------------------------------===//
400 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
401 static bool isFloatingPointZero(SDOperand Op) {
402 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
403 return CFP->getValueAPF().isZero();
404 else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
405 // Maybe this has already been legalized into the constant pool?
406 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
407 if (ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
408 return CFP->getValueAPF().isZero();
413 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
414 /// true if Op is undef or if it matches the specified value.
415 static bool isConstantOrUndef(SDOperand Op, unsigned Val) {
416 return Op.getOpcode() == ISD::UNDEF ||
417 cast<ConstantSDNode>(Op)->getValue() == Val;
420 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
421 /// VPKUHUM instruction.
422 bool PPC::isVPKUHUMShuffleMask(SDNode *N, bool isUnary) {
424 for (unsigned i = 0; i != 16; ++i)
425 if (!isConstantOrUndef(N->getOperand(i), i*2+1))
428 for (unsigned i = 0; i != 8; ++i)
429 if (!isConstantOrUndef(N->getOperand(i), i*2+1) ||
430 !isConstantOrUndef(N->getOperand(i+8), i*2+1))
436 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
437 /// VPKUWUM instruction.
438 bool PPC::isVPKUWUMShuffleMask(SDNode *N, bool isUnary) {
440 for (unsigned i = 0; i != 16; i += 2)
441 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
442 !isConstantOrUndef(N->getOperand(i+1), i*2+3))
445 for (unsigned i = 0; i != 8; i += 2)
446 if (!isConstantOrUndef(N->getOperand(i ), i*2+2) ||
447 !isConstantOrUndef(N->getOperand(i+1), i*2+3) ||
448 !isConstantOrUndef(N->getOperand(i+8), i*2+2) ||
449 !isConstantOrUndef(N->getOperand(i+9), i*2+3))
455 /// isVMerge - Common function, used to match vmrg* shuffles.
457 static bool isVMerge(SDNode *N, unsigned UnitSize,
458 unsigned LHSStart, unsigned RHSStart) {
459 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
460 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
461 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
462 "Unsupported merge size!");
464 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
465 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
466 if (!isConstantOrUndef(N->getOperand(i*UnitSize*2+j),
467 LHSStart+j+i*UnitSize) ||
468 !isConstantOrUndef(N->getOperand(i*UnitSize*2+UnitSize+j),
469 RHSStart+j+i*UnitSize))
475 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
476 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
477 bool PPC::isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
479 return isVMerge(N, UnitSize, 8, 24);
480 return isVMerge(N, UnitSize, 8, 8);
483 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
484 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
485 bool PPC::isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary) {
487 return isVMerge(N, UnitSize, 0, 16);
488 return isVMerge(N, UnitSize, 0, 0);
492 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
493 /// amount, otherwise return -1.
494 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary) {
495 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
496 N->getNumOperands() == 16 && "PPC only supports shuffles by bytes!");
497 // Find the first non-undef value in the shuffle mask.
499 for (i = 0; i != 16 && N->getOperand(i).getOpcode() == ISD::UNDEF; ++i)
502 if (i == 16) return -1; // all undef.
504 // Otherwise, check to see if the rest of the elements are consequtively
505 // numbered from this value.
506 unsigned ShiftAmt = cast<ConstantSDNode>(N->getOperand(i))->getValue();
507 if (ShiftAmt < i) return -1;
511 // Check the rest of the elements to see if they are consequtive.
512 for (++i; i != 16; ++i)
513 if (!isConstantOrUndef(N->getOperand(i), ShiftAmt+i))
516 // Check the rest of the elements to see if they are consequtive.
517 for (++i; i != 16; ++i)
518 if (!isConstantOrUndef(N->getOperand(i), (ShiftAmt+i) & 15))
525 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
526 /// specifies a splat of a single element that is suitable for input to
527 /// VSPLTB/VSPLTH/VSPLTW.
528 bool PPC::isSplatShuffleMask(SDNode *N, unsigned EltSize) {
529 assert(N->getOpcode() == ISD::BUILD_VECTOR &&
530 N->getNumOperands() == 16 &&
531 (EltSize == 1 || EltSize == 2 || EltSize == 4));
533 // This is a splat operation if each element of the permute is the same, and
534 // if the value doesn't reference the second vector.
535 unsigned ElementBase = 0;
536 SDOperand Elt = N->getOperand(0);
537 if (ConstantSDNode *EltV = dyn_cast<ConstantSDNode>(Elt))
538 ElementBase = EltV->getValue();
540 return false; // FIXME: Handle UNDEF elements too!
542 if (cast<ConstantSDNode>(Elt)->getValue() >= 16)
545 // Check that they are consequtive.
546 for (unsigned i = 1; i != EltSize; ++i) {
547 if (!isa<ConstantSDNode>(N->getOperand(i)) ||
548 cast<ConstantSDNode>(N->getOperand(i))->getValue() != i+ElementBase)
552 assert(isa<ConstantSDNode>(Elt) && "Invalid VECTOR_SHUFFLE mask!");
553 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
554 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
555 assert(isa<ConstantSDNode>(N->getOperand(i)) &&
556 "Invalid VECTOR_SHUFFLE mask!");
557 for (unsigned j = 0; j != EltSize; ++j)
558 if (N->getOperand(i+j) != N->getOperand(j))
565 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
567 bool PPC::isAllNegativeZeroVector(SDNode *N) {
568 assert(N->getOpcode() == ISD::BUILD_VECTOR);
569 if (PPC::isSplatShuffleMask(N, N->getNumOperands()))
570 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N))
571 return CFP->getValueAPF().isNegZero();
575 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
576 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
577 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize) {
578 assert(isSplatShuffleMask(N, EltSize));
579 return cast<ConstantSDNode>(N->getOperand(0))->getValue() / EltSize;
582 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
583 /// by using a vspltis[bhw] instruction of the specified element size, return
584 /// the constant being splatted. The ByteSize field indicates the number of
585 /// bytes of each element [124] -> [bhw].
586 SDOperand PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
587 SDOperand OpVal(0, 0);
589 // If ByteSize of the splat is bigger than the element size of the
590 // build_vector, then we have a case where we are checking for a splat where
591 // multiple elements of the buildvector are folded together into a single
592 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
593 unsigned EltSize = 16/N->getNumOperands();
594 if (EltSize < ByteSize) {
595 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
596 SDOperand UniquedVals[4];
597 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
599 // See if all of the elements in the buildvector agree across.
600 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
601 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
602 // If the element isn't a constant, bail fully out.
603 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDOperand();
606 if (UniquedVals[i&(Multiple-1)].Val == 0)
607 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
608 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
609 return SDOperand(); // no match.
612 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
613 // either constant or undef values that are identical for each chunk. See
614 // if these chunks can form into a larger vspltis*.
616 // Check to see if all of the leading entries are either 0 or -1. If
617 // neither, then this won't fit into the immediate field.
618 bool LeadingZero = true;
619 bool LeadingOnes = true;
620 for (unsigned i = 0; i != Multiple-1; ++i) {
621 if (UniquedVals[i].Val == 0) continue; // Must have been undefs.
623 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
624 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
626 // Finally, check the least significant entry.
628 if (UniquedVals[Multiple-1].Val == 0)
629 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
630 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getValue();
632 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
635 if (UniquedVals[Multiple-1].Val == 0)
636 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
637 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSignExtended();
638 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
639 return DAG.getTargetConstant(Val, MVT::i32);
645 // Check to see if this buildvec has a single non-undef value in its elements.
646 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
647 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
649 OpVal = N->getOperand(i);
650 else if (OpVal != N->getOperand(i))
654 if (OpVal.Val == 0) return SDOperand(); // All UNDEF: use implicit def.
656 unsigned ValSizeInBytes = 0;
658 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
659 Value = CN->getValue();
660 ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;
661 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
662 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
663 Value = FloatToBits(CN->getValueAPF().convertToFloat());
667 // If the splat value is larger than the element value, then we can never do
668 // this splat. The only case that we could fit the replicated bits into our
669 // immediate field for would be zero, and we prefer to use vxor for it.
670 if (ValSizeInBytes < ByteSize) return SDOperand();
672 // If the element value is larger than the splat value, cut it in half and
673 // check to see if the two halves are equal. Continue doing this until we
674 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
675 while (ValSizeInBytes > ByteSize) {
676 ValSizeInBytes >>= 1;
678 // If the top half equals the bottom half, we're still ok.
679 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
680 (Value & ((1 << (8*ValSizeInBytes))-1)))
684 // Properly sign extend the value.
685 int ShAmt = (4-ByteSize)*8;
686 int MaskVal = ((int)Value << ShAmt) >> ShAmt;
688 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
689 if (MaskVal == 0) return SDOperand();
691 // Finally, if this value fits in a 5 bit sext field, return it
692 if (((MaskVal << (32-5)) >> (32-5)) == MaskVal)
693 return DAG.getTargetConstant(MaskVal, MVT::i32);
697 //===----------------------------------------------------------------------===//
698 // Addressing Mode Selection
699 //===----------------------------------------------------------------------===//
701 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
702 /// or 64-bit immediate, and if the value can be accurately represented as a
703 /// sign extension from a 16-bit value. If so, this returns true and the
705 static bool isIntS16Immediate(SDNode *N, short &Imm) {
706 if (N->getOpcode() != ISD::Constant)
709 Imm = (short)cast<ConstantSDNode>(N)->getValue();
710 if (N->getValueType(0) == MVT::i32)
711 return Imm == (int32_t)cast<ConstantSDNode>(N)->getValue();
713 return Imm == (int64_t)cast<ConstantSDNode>(N)->getValue();
715 static bool isIntS16Immediate(SDOperand Op, short &Imm) {
716 return isIntS16Immediate(Op.Val, Imm);
720 /// SelectAddressRegReg - Given the specified addressed, check to see if it
721 /// can be represented as an indexed [r+r] operation. Returns false if it
722 /// can be more efficiently represented with [r+imm].
723 bool PPCTargetLowering::SelectAddressRegReg(SDOperand N, SDOperand &Base,
727 if (N.getOpcode() == ISD::ADD) {
728 if (isIntS16Immediate(N.getOperand(1), imm))
730 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
733 Base = N.getOperand(0);
734 Index = N.getOperand(1);
736 } else if (N.getOpcode() == ISD::OR) {
737 if (isIntS16Immediate(N.getOperand(1), imm))
738 return false; // r+i can fold it if we can.
740 // If this is an or of disjoint bitfields, we can codegen this as an add
741 // (for better address arithmetic) if the LHS and RHS of the OR are provably
743 uint64_t LHSKnownZero, LHSKnownOne;
744 uint64_t RHSKnownZero, RHSKnownOne;
745 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
748 DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
749 // If all of the bits are known zero on the LHS or RHS, the add won't
751 if ((LHSKnownZero | RHSKnownZero) == ~0U) {
752 Base = N.getOperand(0);
753 Index = N.getOperand(1);
762 /// Returns true if the address N can be represented by a base register plus
763 /// a signed 16-bit displacement [r+imm], and if it is not better
764 /// represented as reg+reg.
765 bool PPCTargetLowering::SelectAddressRegImm(SDOperand N, SDOperand &Disp,
766 SDOperand &Base, SelectionDAG &DAG){
767 // If this can be more profitably realized as r+r, fail.
768 if (SelectAddressRegReg(N, Disp, Base, DAG))
771 if (N.getOpcode() == ISD::ADD) {
773 if (isIntS16Immediate(N.getOperand(1), imm)) {
774 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
775 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
776 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
778 Base = N.getOperand(0);
780 return true; // [r+i]
781 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
782 // Match LOAD (ADD (X, Lo(G))).
783 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
784 && "Cannot handle constant offsets yet!");
785 Disp = N.getOperand(1).getOperand(0); // The global address.
786 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
787 Disp.getOpcode() == ISD::TargetConstantPool ||
788 Disp.getOpcode() == ISD::TargetJumpTable);
789 Base = N.getOperand(0);
790 return true; // [&g+r]
792 } else if (N.getOpcode() == ISD::OR) {
794 if (isIntS16Immediate(N.getOperand(1), imm)) {
795 // If this is an or of disjoint bitfields, we can codegen this as an add
796 // (for better address arithmetic) if the LHS and RHS of the OR are
797 // provably disjoint.
798 uint64_t LHSKnownZero, LHSKnownOne;
799 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
800 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
801 // If all of the bits are known zero on the LHS or RHS, the add won't
803 Base = N.getOperand(0);
804 Disp = DAG.getTargetConstant((int)imm & 0xFFFF, MVT::i32);
808 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
809 // Loading from a constant address.
811 // If this address fits entirely in a 16-bit sext immediate field, codegen
814 if (isIntS16Immediate(CN, Imm)) {
815 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
816 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
820 // Handle 32-bit sext immediates with LIS + addr mode.
821 if (CN->getValueType(0) == MVT::i32 ||
822 (int64_t)CN->getValue() == (int)CN->getValue()) {
823 int Addr = (int)CN->getValue();
825 // Otherwise, break this down into an LIS + disp.
826 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
828 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
829 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
830 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
835 Disp = DAG.getTargetConstant(0, getPointerTy());
836 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
837 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
840 return true; // [r+0]
843 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
844 /// represented as an indexed [r+r] operation.
845 bool PPCTargetLowering::SelectAddressRegRegOnly(SDOperand N, SDOperand &Base,
848 // Check to see if we can easily represent this as an [r+r] address. This
849 // will fail if it thinks that the address is more profitably represented as
850 // reg+imm, e.g. where imm = 0.
851 if (SelectAddressRegReg(N, Base, Index, DAG))
854 // If the operand is an addition, always emit this as [r+r], since this is
855 // better (for code size, and execution, as the memop does the add for free)
856 // than emitting an explicit add.
857 if (N.getOpcode() == ISD::ADD) {
858 Base = N.getOperand(0);
859 Index = N.getOperand(1);
863 // Otherwise, do it the hard way, using R0 as the base register.
864 Base = DAG.getRegister(PPC::R0, N.getValueType());
869 /// SelectAddressRegImmShift - Returns true if the address N can be
870 /// represented by a base register plus a signed 14-bit displacement
871 /// [r+imm*4]. Suitable for use by STD and friends.
872 bool PPCTargetLowering::SelectAddressRegImmShift(SDOperand N, SDOperand &Disp,
875 // If this can be more profitably realized as r+r, fail.
876 if (SelectAddressRegReg(N, Disp, Base, DAG))
879 if (N.getOpcode() == ISD::ADD) {
881 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
882 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
883 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
884 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
886 Base = N.getOperand(0);
888 return true; // [r+i]
889 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
890 // Match LOAD (ADD (X, Lo(G))).
891 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getValue()
892 && "Cannot handle constant offsets yet!");
893 Disp = N.getOperand(1).getOperand(0); // The global address.
894 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
895 Disp.getOpcode() == ISD::TargetConstantPool ||
896 Disp.getOpcode() == ISD::TargetJumpTable);
897 Base = N.getOperand(0);
898 return true; // [&g+r]
900 } else if (N.getOpcode() == ISD::OR) {
902 if (isIntS16Immediate(N.getOperand(1), imm) && (imm & 3) == 0) {
903 // If this is an or of disjoint bitfields, we can codegen this as an add
904 // (for better address arithmetic) if the LHS and RHS of the OR are
905 // provably disjoint.
906 uint64_t LHSKnownZero, LHSKnownOne;
907 DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
908 if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
909 // If all of the bits are known zero on the LHS or RHS, the add won't
911 Base = N.getOperand(0);
912 Disp = DAG.getTargetConstant(((int)imm & 0xFFFF) >> 2, MVT::i32);
916 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
917 // Loading from a constant address. Verify low two bits are clear.
918 if ((CN->getValue() & 3) == 0) {
919 // If this address fits entirely in a 14-bit sext immediate field, codegen
922 if (isIntS16Immediate(CN, Imm)) {
923 Disp = DAG.getTargetConstant((unsigned short)Imm >> 2, getPointerTy());
924 Base = DAG.getRegister(PPC::R0, CN->getValueType(0));
928 // Fold the low-part of 32-bit absolute addresses into addr mode.
929 if (CN->getValueType(0) == MVT::i32 ||
930 (int64_t)CN->getValue() == (int)CN->getValue()) {
931 int Addr = (int)CN->getValue();
933 // Otherwise, break this down into an LIS + disp.
934 Disp = DAG.getTargetConstant((short)Addr >> 2, MVT::i32);
936 Base = DAG.getTargetConstant((Addr-(signed short)Addr) >> 16, MVT::i32);
937 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
938 Base = SDOperand(DAG.getTargetNode(Opc, CN->getValueType(0), Base), 0);
944 Disp = DAG.getTargetConstant(0, getPointerTy());
945 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N))
946 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
949 return true; // [r+0]
953 /// getPreIndexedAddressParts - returns true by value, base pointer and
954 /// offset pointer and addressing mode by reference if the node's address
955 /// can be legally represented as pre-indexed load / store address.
956 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
958 ISD::MemIndexedMode &AM,
960 // Disabled by default for now.
961 if (!EnablePPCPreinc) return false;
965 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
966 Ptr = LD->getBasePtr();
967 VT = LD->getMemoryVT();
969 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
971 Ptr = ST->getBasePtr();
972 VT = ST->getMemoryVT();
976 // PowerPC doesn't have preinc load/store instructions for vectors.
977 if (MVT::isVector(VT))
980 // TODO: Check reg+reg first.
982 // LDU/STU use reg+imm*4, others use reg+imm.
983 if (VT != MVT::i64) {
985 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG))
989 if (!SelectAddressRegImmShift(Ptr, Offset, Base, DAG))
993 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
994 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
995 // sext i32 to i64 when addr mode is r+i.
996 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
997 LD->getExtensionType() == ISD::SEXTLOAD &&
998 isa<ConstantSDNode>(Offset))
1006 //===----------------------------------------------------------------------===//
1007 // LowerOperation implementation
1008 //===----------------------------------------------------------------------===//
1010 static SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG) {
1011 MVT::ValueType PtrVT = Op.getValueType();
1012 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1013 Constant *C = CP->getConstVal();
1014 SDOperand CPI = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment());
1015 SDOperand Zero = DAG.getConstant(0, PtrVT);
1017 const TargetMachine &TM = DAG.getTarget();
1019 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, CPI, Zero);
1020 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, CPI, Zero);
1022 // If this is a non-darwin platform, we don't support non-static relo models
1024 if (TM.getRelocationModel() == Reloc::Static ||
1025 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1026 // Generate non-pic code that has direct accesses to the constant pool.
1027 // The address of the global is just (hi(&g)+lo(&g)).
1028 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1031 if (TM.getRelocationModel() == Reloc::PIC_) {
1032 // With PIC, the first instruction is actually "GR+hi(&G)".
1033 Hi = DAG.getNode(ISD::ADD, PtrVT,
1034 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1037 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1041 static SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG) {
1042 MVT::ValueType PtrVT = Op.getValueType();
1043 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1044 SDOperand JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1045 SDOperand Zero = DAG.getConstant(0, PtrVT);
1047 const TargetMachine &TM = DAG.getTarget();
1049 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, JTI, Zero);
1050 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, JTI, Zero);
1052 // If this is a non-darwin platform, we don't support non-static relo models
1054 if (TM.getRelocationModel() == Reloc::Static ||
1055 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1056 // Generate non-pic code that has direct accesses to the constant pool.
1057 // The address of the global is just (hi(&g)+lo(&g)).
1058 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1061 if (TM.getRelocationModel() == Reloc::PIC_) {
1062 // With PIC, the first instruction is actually "GR+hi(&G)".
1063 Hi = DAG.getNode(ISD::ADD, PtrVT,
1064 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1067 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1071 static SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG) {
1072 assert(0 && "TLS not implemented for PPC.");
1075 static SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG) {
1076 MVT::ValueType PtrVT = Op.getValueType();
1077 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1078 GlobalValue *GV = GSDN->getGlobal();
1079 SDOperand GA = DAG.getTargetGlobalAddress(GV, PtrVT, GSDN->getOffset());
1080 // If it's a debug information descriptor, don't mess with it.
1081 if (DAG.isVerifiedDebugInfoDesc(Op))
1083 SDOperand Zero = DAG.getConstant(0, PtrVT);
1085 const TargetMachine &TM = DAG.getTarget();
1087 SDOperand Hi = DAG.getNode(PPCISD::Hi, PtrVT, GA, Zero);
1088 SDOperand Lo = DAG.getNode(PPCISD::Lo, PtrVT, GA, Zero);
1090 // If this is a non-darwin platform, we don't support non-static relo models
1092 if (TM.getRelocationModel() == Reloc::Static ||
1093 !TM.getSubtarget<PPCSubtarget>().isDarwin()) {
1094 // Generate non-pic code that has direct accesses to globals.
1095 // The address of the global is just (hi(&g)+lo(&g)).
1096 return DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1099 if (TM.getRelocationModel() == Reloc::PIC_) {
1100 // With PIC, the first instruction is actually "GR+hi(&G)".
1101 Hi = DAG.getNode(ISD::ADD, PtrVT,
1102 DAG.getNode(PPCISD::GlobalBaseReg, PtrVT), Hi);
1105 Lo = DAG.getNode(ISD::ADD, PtrVT, Hi, Lo);
1107 if (!TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV))
1110 // If the global is weak or external, we have to go through the lazy
1112 return DAG.getLoad(PtrVT, DAG.getEntryNode(), Lo, NULL, 0);
1115 static SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG) {
1116 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1118 // If we're comparing for equality to zero, expose the fact that this is
1119 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1120 // fold the new nodes.
1121 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1122 if (C->isNullValue() && CC == ISD::SETEQ) {
1123 MVT::ValueType VT = Op.getOperand(0).getValueType();
1124 SDOperand Zext = Op.getOperand(0);
1125 if (VT < MVT::i32) {
1127 Zext = DAG.getNode(ISD::ZERO_EXTEND, VT, Op.getOperand(0));
1129 unsigned Log2b = Log2_32(MVT::getSizeInBits(VT));
1130 SDOperand Clz = DAG.getNode(ISD::CTLZ, VT, Zext);
1131 SDOperand Scc = DAG.getNode(ISD::SRL, VT, Clz,
1132 DAG.getConstant(Log2b, MVT::i32));
1133 return DAG.getNode(ISD::TRUNCATE, MVT::i32, Scc);
1135 // Leave comparisons against 0 and -1 alone for now, since they're usually
1136 // optimized. FIXME: revisit this when we can custom lower all setcc
1138 if (C->isAllOnesValue() || C->isNullValue())
1142 // If we have an integer seteq/setne, turn it into a compare against zero
1143 // by xor'ing the rhs with the lhs, which is faster than setting a
1144 // condition register, reading it back out, and masking the correct bit. The
1145 // normal approach here uses sub to do this instead of xor. Using xor exposes
1146 // the result to other bit-twiddling opportunities.
1147 MVT::ValueType LHSVT = Op.getOperand(0).getValueType();
1148 if (MVT::isInteger(LHSVT) && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1149 MVT::ValueType VT = Op.getValueType();
1150 SDOperand Sub = DAG.getNode(ISD::XOR, LHSVT, Op.getOperand(0),
1152 return DAG.getSetCC(VT, Sub, DAG.getConstant(0, LHSVT), CC);
1157 static SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG,
1158 int VarArgsFrameIndex,
1159 int VarArgsStackOffset,
1160 unsigned VarArgsNumGPR,
1161 unsigned VarArgsNumFPR,
1162 const PPCSubtarget &Subtarget) {
1164 assert(0 && "VAARG in ELF32 ABI not implemented yet!");
1167 static SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
1168 int VarArgsFrameIndex,
1169 int VarArgsStackOffset,
1170 unsigned VarArgsNumGPR,
1171 unsigned VarArgsNumFPR,
1172 const PPCSubtarget &Subtarget) {
1174 if (Subtarget.isMachoABI()) {
1175 // vastart just stores the address of the VarArgsFrameIndex slot into the
1176 // memory location argument.
1177 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1178 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1179 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1180 return DAG.getStore(Op.getOperand(0), FR, Op.getOperand(1), SV, 0);
1183 // For ELF 32 ABI we follow the layout of the va_list struct.
1184 // We suppose the given va_list is already allocated.
1187 // char gpr; /* index into the array of 8 GPRs
1188 // * stored in the register save area
1189 // * gpr=0 corresponds to r3,
1190 // * gpr=1 to r4, etc.
1192 // char fpr; /* index into the array of 8 FPRs
1193 // * stored in the register save area
1194 // * fpr=0 corresponds to f1,
1195 // * fpr=1 to f2, etc.
1197 // char *overflow_arg_area;
1198 // /* location on stack that holds
1199 // * the next overflow argument
1201 // char *reg_save_area;
1202 // /* where r3:r10 and f1:f8 (if saved)
1208 SDOperand ArgGPR = DAG.getConstant(VarArgsNumGPR, MVT::i8);
1209 SDOperand ArgFPR = DAG.getConstant(VarArgsNumFPR, MVT::i8);
1212 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1214 SDOperand StackOffsetFI = DAG.getFrameIndex(VarArgsStackOffset, PtrVT);
1215 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1217 uint64_t FrameOffset = MVT::getSizeInBits(PtrVT)/8;
1218 SDOperand ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
1220 uint64_t StackOffset = MVT::getSizeInBits(PtrVT)/8 - 1;
1221 SDOperand ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
1223 uint64_t FPROffset = 1;
1224 SDOperand ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
1226 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1228 // Store first byte : number of int regs
1229 SDOperand firstStore = DAG.getStore(Op.getOperand(0), ArgGPR,
1230 Op.getOperand(1), SV, 0);
1231 uint64_t nextOffset = FPROffset;
1232 SDOperand nextPtr = DAG.getNode(ISD::ADD, PtrVT, Op.getOperand(1),
1235 // Store second byte : number of float regs
1236 SDOperand secondStore =
1237 DAG.getStore(firstStore, ArgFPR, nextPtr, SV, nextOffset);
1238 nextOffset += StackOffset;
1239 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstStackOffset);
1241 // Store second word : arguments given on stack
1242 SDOperand thirdStore =
1243 DAG.getStore(secondStore, StackOffsetFI, nextPtr, SV, nextOffset);
1244 nextOffset += FrameOffset;
1245 nextPtr = DAG.getNode(ISD::ADD, PtrVT, nextPtr, ConstFrameOffset);
1247 // Store third word : arguments given in registers
1248 return DAG.getStore(thirdStore, FR, nextPtr, SV, nextOffset);
1252 #include "PPCGenCallingConv.inc"
1254 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
1255 /// depending on which subtarget is selected.
1256 static const unsigned *GetFPR(const PPCSubtarget &Subtarget) {
1257 if (Subtarget.isMachoABI()) {
1258 static const unsigned FPR[] = {
1259 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1260 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1266 static const unsigned FPR[] = {
1267 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1273 static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
1274 int &VarArgsFrameIndex,
1275 int &VarArgsStackOffset,
1276 unsigned &VarArgsNumGPR,
1277 unsigned &VarArgsNumFPR,
1278 const PPCSubtarget &Subtarget) {
1279 // TODO: add description of PPC stack frame format, or at least some docs.
1281 MachineFunction &MF = DAG.getMachineFunction();
1282 MachineFrameInfo *MFI = MF.getFrameInfo();
1283 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1284 SmallVector<SDOperand, 8> ArgValues;
1285 SDOperand Root = Op.getOperand(0);
1287 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1288 bool isPPC64 = PtrVT == MVT::i64;
1289 bool isMachoABI = Subtarget.isMachoABI();
1290 bool isELF32_ABI = Subtarget.isELF32_ABI();
1291 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1293 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1295 static const unsigned GPR_32[] = { // 32-bit registers.
1296 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1297 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1299 static const unsigned GPR_64[] = { // 64-bit registers.
1300 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1301 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1304 static const unsigned *FPR = GetFPR(Subtarget);
1306 static const unsigned VR[] = {
1307 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1308 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1311 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
1312 const unsigned Num_FPR_Regs = isMachoABI ? 13 : 8;
1313 const unsigned Num_VR_Regs = array_lengthof( VR);
1315 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1317 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1319 // Add DAG nodes to load the arguments or copy them out of registers. On
1320 // entry to a function on PPC, the arguments start after the linkage area,
1321 // although the first ones are often in registers.
1323 // In the ELF 32 ABI, GPRs and stack are double word align: an argument
1324 // represented with two words (long long or double) must be copied to an
1325 // even GPR_idx value or to an even ArgOffset value.
1327 for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
1329 bool needsLoad = false;
1330 MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
1331 unsigned ObjSize = MVT::getSizeInBits(ObjectVT)/8;
1332 unsigned ArgSize = ObjSize;
1333 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(ArgNo+3))->getValue();
1334 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1335 // See if next argument requires stack alignment in ELF
1336 bool Expand = (ObjectVT == MVT::f64) || ((ArgNo + 1 < e) &&
1337 (cast<ConstantSDNode>(Op.getOperand(ArgNo+4))->getValue() & AlignFlag) &&
1338 (!(Flags & AlignFlag)));
1340 unsigned CurArgOffset = ArgOffset;
1342 default: assert(0 && "Unhandled argument type!");
1344 // Double word align in ELF
1345 if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
1346 if (GPR_idx != Num_GPR_Regs) {
1347 unsigned VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1348 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1349 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i32);
1353 ArgSize = PtrByteSize;
1355 // Stack align in ELF
1356 if (needsLoad && Expand && isELF32_ABI)
1357 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1358 // All int arguments reserve stack space in Macho ABI.
1359 if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
1362 case MVT::i64: // PPC64
1363 if (GPR_idx != Num_GPR_Regs) {
1364 unsigned VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1365 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1366 ArgVal = DAG.getCopyFromReg(Root, VReg, MVT::i64);
1371 // All int arguments reserve stack space in Macho ABI.
1372 if (isMachoABI || needsLoad) ArgOffset += 8;
1377 // Every 4 bytes of argument space consumes one of the GPRs available for
1378 // argument passing.
1379 if (GPR_idx != Num_GPR_Regs && isMachoABI) {
1381 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
1384 if (FPR_idx != Num_FPR_Regs) {
1386 if (ObjectVT == MVT::f32)
1387 VReg = RegInfo.createVirtualRegister(&PPC::F4RCRegClass);
1389 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1390 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1391 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1397 // Stack align in ELF
1398 if (needsLoad && Expand && isELF32_ABI)
1399 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1400 // All FP arguments reserve stack space in Macho ABI.
1401 if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
1407 // Note that vector arguments in registers don't reserve stack space.
1408 if (VR_idx != Num_VR_Regs) {
1409 unsigned VReg = RegInfo.createVirtualRegister(&PPC::VRRCRegClass);
1410 RegInfo.addLiveIn(VR[VR_idx], VReg);
1411 ArgVal = DAG.getCopyFromReg(Root, VReg, ObjectVT);
1414 // This should be simple, but requires getting 16-byte aligned stack
1416 assert(0 && "Loading VR argument not implemented yet!");
1422 // We need to load the argument to a virtual register if we determined above
1423 // that we ran out of physical registers of the appropriate type
1425 // If the argument is actually used, emit a load from the right stack
1427 if (!Op.Val->hasNUsesOfValue(0, ArgNo)) {
1428 int FI = MFI->CreateFixedObject(ObjSize,
1429 CurArgOffset + (ArgSize - ObjSize));
1430 SDOperand FIN = DAG.getFrameIndex(FI, PtrVT);
1431 ArgVal = DAG.getLoad(ObjectVT, Root, FIN, NULL, 0);
1433 // Don't emit a dead load.
1434 ArgVal = DAG.getNode(ISD::UNDEF, ObjectVT);
1438 ArgValues.push_back(ArgVal);
1441 // If the function takes variable number of arguments, make a frame index for
1442 // the start of the first vararg value... for expansion of llvm.va_start.
1443 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1448 VarArgsNumGPR = GPR_idx;
1449 VarArgsNumFPR = FPR_idx;
1451 // Make room for Num_GPR_Regs, Num_FPR_Regs and for a possible frame
1453 depth = -(Num_GPR_Regs * MVT::getSizeInBits(PtrVT)/8 +
1454 Num_FPR_Regs * MVT::getSizeInBits(MVT::f64)/8 +
1455 MVT::getSizeInBits(PtrVT)/8);
1457 VarArgsStackOffset = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1464 VarArgsFrameIndex = MFI->CreateFixedObject(MVT::getSizeInBits(PtrVT)/8,
1466 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, PtrVT);
1468 SmallVector<SDOperand, 8> MemOps;
1470 // In ELF 32 ABI, the fixed integer arguments of a variadic function are
1471 // stored to the VarArgsFrameIndex on the stack.
1473 for (GPR_idx = 0; GPR_idx != VarArgsNumGPR; ++GPR_idx) {
1474 SDOperand Val = DAG.getRegister(GPR[GPR_idx], PtrVT);
1475 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1476 MemOps.push_back(Store);
1477 // Increment the address by four for the next argument to store
1478 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1479 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1483 // If this function is vararg, store any remaining integer argument regs
1484 // to their spots on the stack so that they may be loaded by deferencing the
1485 // result of va_next.
1486 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
1489 VReg = RegInfo.createVirtualRegister(&PPC::G8RCRegClass);
1491 VReg = RegInfo.createVirtualRegister(&PPC::GPRCRegClass);
1493 RegInfo.addLiveIn(GPR[GPR_idx], VReg);
1494 SDOperand Val = DAG.getCopyFromReg(Root, VReg, PtrVT);
1495 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1496 MemOps.push_back(Store);
1497 // Increment the address by four for the next argument to store
1498 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(PtrVT)/8, PtrVT);
1499 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1502 // In ELF 32 ABI, the double arguments are stored to the VarArgsFrameIndex
1505 for (FPR_idx = 0; FPR_idx != VarArgsNumFPR; ++FPR_idx) {
1506 SDOperand Val = DAG.getRegister(FPR[FPR_idx], MVT::f64);
1507 SDOperand Store = DAG.getStore(Root, Val, FIN, NULL, 0);
1508 MemOps.push_back(Store);
1509 // Increment the address by eight for the next argument to store
1510 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1512 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1515 for (; FPR_idx != Num_FPR_Regs; ++FPR_idx) {
1517 VReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
1519 RegInfo.addLiveIn(FPR[FPR_idx], VReg);
1520 SDOperand Val = DAG.getCopyFromReg(Root, VReg, MVT::f64);
1521 SDOperand Store = DAG.getStore(Val.getValue(1), Val, FIN, NULL, 0);
1522 MemOps.push_back(Store);
1523 // Increment the address by eight for the next argument to store
1524 SDOperand PtrOff = DAG.getConstant(MVT::getSizeInBits(MVT::f64)/8,
1526 FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
1530 if (!MemOps.empty())
1531 Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
1534 ArgValues.push_back(Root);
1536 // Return the new list of results.
1537 std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
1538 Op.Val->value_end());
1539 return DAG.getNode(ISD::MERGE_VALUES, RetVT, &ArgValues[0], ArgValues.size());
1542 /// isCallCompatibleAddress - Return the immediate to use if the specified
1543 /// 32-bit value is representable in the immediate field of a BxA instruction.
1544 static SDNode *isBLACompatibleAddress(SDOperand Op, SelectionDAG &DAG) {
1545 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
1548 int Addr = C->getValue();
1549 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
1550 (Addr << 6 >> 6) != Addr)
1551 return 0; // Top 6 bits have to be sext of immediate.
1553 return DAG.getConstant((int)C->getValue() >> 2,
1554 DAG.getTargetLoweringInfo().getPointerTy()).Val;
1558 static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
1559 const PPCSubtarget &Subtarget) {
1560 SDOperand Chain = Op.getOperand(0);
1561 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
1562 SDOperand Callee = Op.getOperand(4);
1563 unsigned NumOps = (Op.getNumOperands() - 5) / 2;
1565 bool isMachoABI = Subtarget.isMachoABI();
1566 bool isELF32_ABI = Subtarget.isELF32_ABI();
1568 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1569 bool isPPC64 = PtrVT == MVT::i64;
1570 unsigned PtrByteSize = isPPC64 ? 8 : 4;
1572 // args_to_use will accumulate outgoing args for the PPCISD::CALL case in
1573 // SelectExpr to use to put the arguments in the appropriate registers.
1574 std::vector<SDOperand> args_to_use;
1576 // Count how many bytes are to be pushed on the stack, including the linkage
1577 // area, and parameter passing area. We start with 24/48 bytes, which is
1578 // prereserved space for [SP][CR][LR][3 x unused].
1579 unsigned NumBytes = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1581 // Add up all the space actually used.
1582 for (unsigned i = 0; i != NumOps; ++i) {
1583 unsigned ArgSize =MVT::getSizeInBits(Op.getOperand(5+2*i).getValueType())/8;
1584 ArgSize = std::max(ArgSize, PtrByteSize);
1585 NumBytes += ArgSize;
1588 // The prolog code of the callee may store up to 8 GPR argument registers to
1589 // the stack, allowing va_start to index over them in memory if its varargs.
1590 // Because we cannot tell if this is needed on the caller side, we have to
1591 // conservatively assume that it is needed. As such, make sure we have at
1592 // least enough stack space for the caller to store the 8 GPRs.
1593 NumBytes = std::max(NumBytes,
1594 PPCFrameInfo::getMinCallFrameSize(isPPC64, isMachoABI));
1596 // Adjust the stack pointer for the new arguments...
1597 // These operations are automatically eliminated by the prolog/epilog pass
1598 Chain = DAG.getCALLSEQ_START(Chain,
1599 DAG.getConstant(NumBytes, PtrVT));
1601 // Set up a copy of the stack pointer for use loading and storing any
1602 // arguments that may not fit in the registers available for argument
1606 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
1608 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
1610 // Figure out which arguments are going to go in registers, and which in
1611 // memory. Also, if this is a vararg function, floating point operations
1612 // must be stored to our stack, and loaded into integer regs as well, if
1613 // any integer regs are available for argument passing.
1614 unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
1615 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
1617 static const unsigned GPR_32[] = { // 32-bit registers.
1618 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1619 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1621 static const unsigned GPR_64[] = { // 64-bit registers.
1622 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
1623 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
1625 static const unsigned *FPR = GetFPR(Subtarget);
1627 static const unsigned VR[] = {
1628 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
1629 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
1631 const unsigned NumGPRs = array_lengthof(GPR_32);
1632 const unsigned NumFPRs = isMachoABI ? 13 : 8;
1633 const unsigned NumVRs = array_lengthof( VR);
1635 const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
1637 std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
1638 SmallVector<SDOperand, 8> MemOpChains;
1639 for (unsigned i = 0; i != NumOps; ++i) {
1641 SDOperand Arg = Op.getOperand(5+2*i);
1642 unsigned Flags = cast<ConstantSDNode>(Op.getOperand(5+2*i+1))->getValue();
1643 unsigned AlignFlag = 1 << ISD::ParamFlags::OrigAlignmentOffs;
1644 // See if next argument requires stack alignment in ELF
1645 unsigned next = 5+2*(i+1)+1;
1646 bool Expand = (Arg.getValueType() == MVT::f64) || ((i + 1 < NumOps) &&
1647 (cast<ConstantSDNode>(Op.getOperand(next))->getValue() & AlignFlag) &&
1648 (!(Flags & AlignFlag)));
1650 // PtrOff will be used to store the current argument to the stack if a
1651 // register cannot be found for it.
1654 // Stack align in ELF 32
1655 if (isELF32_ABI && Expand)
1656 PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
1657 StackPtr.getValueType());
1659 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
1661 PtrOff = DAG.getNode(ISD::ADD, PtrVT, StackPtr, PtrOff);
1663 // On PPC64, promote integers to 64-bit values.
1664 if (isPPC64 && Arg.getValueType() == MVT::i32) {
1665 unsigned ExtOp = (Flags & 1) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
1667 Arg = DAG.getNode(ExtOp, MVT::i64, Arg);
1670 switch (Arg.getValueType()) {
1671 default: assert(0 && "Unexpected ValueType for argument!");
1674 // Double word align in ELF
1675 if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
1676 if (GPR_idx != NumGPRs) {
1677 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
1679 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1682 if (inMem || isMachoABI) {
1683 // Stack align in ELF
1684 if (isELF32_ABI && Expand)
1685 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1687 ArgOffset += PtrByteSize;
1693 // Float varargs need to be promoted to double.
1694 if (Arg.getValueType() == MVT::f32)
1695 Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg);
1698 if (FPR_idx != NumFPRs) {
1699 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
1702 SDOperand Store = DAG.getStore(Chain, Arg, PtrOff, NULL, 0);
1703 MemOpChains.push_back(Store);
1705 // Float varargs are always shadowed in available integer registers
1706 if (GPR_idx != NumGPRs) {
1707 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1708 MemOpChains.push_back(Load.getValue(1));
1709 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1712 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
1713 SDOperand ConstFour = DAG.getConstant(4, PtrOff.getValueType());
1714 PtrOff = DAG.getNode(ISD::ADD, PtrVT, PtrOff, ConstFour);
1715 SDOperand Load = DAG.getLoad(PtrVT, Store, PtrOff, NULL, 0);
1716 MemOpChains.push_back(Load.getValue(1));
1717 if (isMachoABI) RegsToPass.push_back(std::make_pair(GPR[GPR_idx++],
1721 // If we have any FPRs remaining, we may also have GPRs remaining.
1722 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
1725 if (GPR_idx != NumGPRs)
1727 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
1728 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
1733 MemOpChains.push_back(DAG.getStore(Chain, Arg, PtrOff, NULL, 0));
1736 if (inMem || isMachoABI) {
1737 // Stack align in ELF
1738 if (isELF32_ABI && Expand)
1739 ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
1743 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
1750 assert(!isVarArg && "Don't support passing vectors to varargs yet!");
1751 assert(VR_idx != NumVRs &&
1752 "Don't support passing more than 12 vector args yet!");
1753 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
1757 if (!MemOpChains.empty())
1758 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
1759 &MemOpChains[0], MemOpChains.size());
1761 // Build a sequence of copy-to-reg nodes chained together with token chain
1762 // and flag operands which copy the outgoing args into the appropriate regs.
1764 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1765 Chain = DAG.getCopyToReg(Chain, RegsToPass[i].first, RegsToPass[i].second,
1767 InFlag = Chain.getValue(1);
1770 // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
1771 if (isVarArg && isELF32_ABI) {
1772 SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
1773 Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
1774 InFlag = Chain.getValue(1);
1777 std::vector<MVT::ValueType> NodeTys;
1778 NodeTys.push_back(MVT::Other); // Returns a chain
1779 NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
1781 SmallVector<SDOperand, 8> Ops;
1782 unsigned CallOpc = isMachoABI? PPCISD::CALL_Macho : PPCISD::CALL_ELF;
1784 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
1785 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
1786 // node so that legalize doesn't hack it.
1787 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1788 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), Callee.getValueType());
1789 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
1790 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType());
1791 else if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG))
1792 // If this is an absolute destination address, use the munged value.
1793 Callee = SDOperand(Dest, 0);
1795 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
1796 // to do the call, we can't use PPCISD::CALL.
1797 SDOperand MTCTROps[] = {Chain, Callee, InFlag};
1798 Chain = DAG.getNode(PPCISD::MTCTR, NodeTys, MTCTROps, 2+(InFlag.Val!=0));
1799 InFlag = Chain.getValue(1);
1801 // Copy the callee address into R12 on darwin.
1803 Chain = DAG.getCopyToReg(Chain, PPC::R12, Callee, InFlag);
1804 InFlag = Chain.getValue(1);
1808 NodeTys.push_back(MVT::Other);
1809 NodeTys.push_back(MVT::Flag);
1810 Ops.push_back(Chain);
1811 CallOpc = isMachoABI ? PPCISD::BCTRL_Macho : PPCISD::BCTRL_ELF;
1815 // If this is a direct call, pass the chain and the callee.
1817 Ops.push_back(Chain);
1818 Ops.push_back(Callee);
1821 // Add argument registers to the end of the list so that they are known live
1823 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1824 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1825 RegsToPass[i].second.getValueType()));
1828 Ops.push_back(InFlag);
1829 Chain = DAG.getNode(CallOpc, NodeTys, &Ops[0], Ops.size());
1830 InFlag = Chain.getValue(1);
1832 Chain = DAG.getCALLSEQ_END(Chain,
1833 DAG.getConstant(NumBytes, PtrVT),
1834 DAG.getConstant(0, PtrVT),
1836 if (Op.Val->getValueType(0) != MVT::Other)
1837 InFlag = Chain.getValue(1);
1839 SDOperand ResultVals[3];
1840 unsigned NumResults = 0;
1843 // If the call has results, copy the values out of the ret val registers.
1844 switch (Op.Val->getValueType(0)) {
1845 default: assert(0 && "Unexpected ret value!");
1846 case MVT::Other: break;
1848 if (Op.Val->getValueType(1) == MVT::i32) {
1849 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1850 ResultVals[0] = Chain.getValue(0);
1851 Chain = DAG.getCopyFromReg(Chain, PPC::R4, MVT::i32,
1852 Chain.getValue(2)).getValue(1);
1853 ResultVals[1] = Chain.getValue(0);
1855 NodeTys.push_back(MVT::i32);
1857 Chain = DAG.getCopyFromReg(Chain, PPC::R3, MVT::i32, InFlag).getValue(1);
1858 ResultVals[0] = Chain.getValue(0);
1861 NodeTys.push_back(MVT::i32);
1864 Chain = DAG.getCopyFromReg(Chain, PPC::X3, MVT::i64, InFlag).getValue(1);
1865 ResultVals[0] = Chain.getValue(0);
1867 NodeTys.push_back(MVT::i64);
1870 if (Op.Val->getValueType(1) == MVT::f64) {
1871 Chain = DAG.getCopyFromReg(Chain, PPC::F1, MVT::f64, InFlag).getValue(1);
1872 ResultVals[0] = Chain.getValue(0);
1873 Chain = DAG.getCopyFromReg(Chain, PPC::F2, MVT::f64,
1874 Chain.getValue(2)).getValue(1);
1875 ResultVals[1] = Chain.getValue(0);
1877 NodeTys.push_back(MVT::f64);
1878 NodeTys.push_back(MVT::f64);
1881 // else fall through
1883 Chain = DAG.getCopyFromReg(Chain, PPC::F1, Op.Val->getValueType(0),
1884 InFlag).getValue(1);
1885 ResultVals[0] = Chain.getValue(0);
1887 NodeTys.push_back(Op.Val->getValueType(0));
1893 Chain = DAG.getCopyFromReg(Chain, PPC::V2, Op.Val->getValueType(0),
1894 InFlag).getValue(1);
1895 ResultVals[0] = Chain.getValue(0);
1897 NodeTys.push_back(Op.Val->getValueType(0));
1901 NodeTys.push_back(MVT::Other);
1903 // If the function returns void, just return the chain.
1904 if (NumResults == 0)
1907 // Otherwise, merge everything together with a MERGE_VALUES node.
1908 ResultVals[NumResults++] = Chain;
1909 SDOperand Res = DAG.getNode(ISD::MERGE_VALUES, NodeTys,
1910 ResultVals, NumResults);
1911 return Res.getValue(Op.ResNo);
1914 static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM) {
1915 SmallVector<CCValAssign, 16> RVLocs;
1916 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
1917 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
1918 CCState CCInfo(CC, isVarArg, TM, RVLocs);
1919 CCInfo.AnalyzeReturn(Op.Val, RetCC_PPC);
1921 // If this is the first return lowered for this function, add the regs to the
1922 // liveout set for the function.
1923 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1924 for (unsigned i = 0; i != RVLocs.size(); ++i)
1925 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1928 SDOperand Chain = Op.getOperand(0);
1931 // Copy the result values into the output registers.
1932 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1933 CCValAssign &VA = RVLocs[i];
1934 assert(VA.isRegLoc() && "Can only return in registers!");
1935 Chain = DAG.getCopyToReg(Chain, VA.getLocReg(), Op.getOperand(i*2+1), Flag);
1936 Flag = Chain.getValue(1);
1940 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain, Flag);
1942 return DAG.getNode(PPCISD::RET_FLAG, MVT::Other, Chain);
1945 static SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
1946 const PPCSubtarget &Subtarget) {
1947 // When we pop the dynamic allocation we need to restore the SP link.
1949 // Get the corect type for pointers.
1950 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1952 // Construct the stack pointer operand.
1953 bool IsPPC64 = Subtarget.isPPC64();
1954 unsigned SP = IsPPC64 ? PPC::X1 : PPC::R1;
1955 SDOperand StackPtr = DAG.getRegister(SP, PtrVT);
1957 // Get the operands for the STACKRESTORE.
1958 SDOperand Chain = Op.getOperand(0);
1959 SDOperand SaveSP = Op.getOperand(1);
1961 // Load the old link SP.
1962 SDOperand LoadLinkSP = DAG.getLoad(PtrVT, Chain, StackPtr, NULL, 0);
1964 // Restore the stack pointer.
1965 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), SP, SaveSP);
1967 // Store the old link SP.
1968 return DAG.getStore(Chain, LoadLinkSP, StackPtr, NULL, 0);
1971 static SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
1972 const PPCSubtarget &Subtarget) {
1973 MachineFunction &MF = DAG.getMachineFunction();
1974 bool IsPPC64 = Subtarget.isPPC64();
1975 bool isMachoABI = Subtarget.isMachoABI();
1977 // Get current frame pointer save index. The users of this index will be
1978 // primarily DYNALLOC instructions.
1979 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1980 int FPSI = FI->getFramePointerSaveIndex();
1982 // If the frame pointer save index hasn't been defined yet.
1984 // Find out what the fix offset of the frame pointer save area.
1985 int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(IsPPC64, isMachoABI);
1987 // Allocate the frame index for frame pointer save area.
1988 FPSI = MF.getFrameInfo()->CreateFixedObject(IsPPC64? 8 : 4, FPOffset);
1990 FI->setFramePointerSaveIndex(FPSI);
1994 SDOperand Chain = Op.getOperand(0);
1995 SDOperand Size = Op.getOperand(1);
1997 // Get the corect type for pointers.
1998 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2000 SDOperand NegSize = DAG.getNode(ISD::SUB, PtrVT,
2001 DAG.getConstant(0, PtrVT), Size);
2002 // Construct a node for the frame pointer save index.
2003 SDOperand FPSIdx = DAG.getFrameIndex(FPSI, PtrVT);
2004 // Build a DYNALLOC node.
2005 SDOperand Ops[3] = { Chain, NegSize, FPSIdx };
2006 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
2007 return DAG.getNode(PPCISD::DYNALLOC, VTs, Ops, 3);
2011 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
2013 static SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG) {
2014 // Not FP? Not a fsel.
2015 if (!MVT::isFloatingPoint(Op.getOperand(0).getValueType()) ||
2016 !MVT::isFloatingPoint(Op.getOperand(2).getValueType()))
2019 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2021 // Cannot handle SETEQ/SETNE.
2022 if (CC == ISD::SETEQ || CC == ISD::SETNE) return SDOperand();
2024 MVT::ValueType ResVT = Op.getValueType();
2025 MVT::ValueType CmpVT = Op.getOperand(0).getValueType();
2026 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
2027 SDOperand TV = Op.getOperand(2), FV = Op.getOperand(3);
2029 // If the RHS of the comparison is a 0.0, we don't need to do the
2030 // subtraction at all.
2031 if (isFloatingPointZero(RHS))
2033 default: break; // SETUO etc aren't handled by fsel.
2037 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2041 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2042 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2043 return DAG.getNode(PPCISD::FSEL, ResVT, LHS, TV, FV);
2047 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
2051 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
2052 LHS = DAG.getNode(ISD::FP_EXTEND, MVT::f64, LHS);
2053 return DAG.getNode(PPCISD::FSEL, ResVT,
2054 DAG.getNode(ISD::FNEG, MVT::f64, LHS), TV, FV);
2059 default: break; // SETUO etc aren't handled by fsel.
2063 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2064 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2065 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2066 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2070 Cmp = DAG.getNode(ISD::FSUB, CmpVT, LHS, RHS);
2071 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2072 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2073 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2077 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2078 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2079 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2080 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, FV, TV);
2084 Cmp = DAG.getNode(ISD::FSUB, CmpVT, RHS, LHS);
2085 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
2086 Cmp = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Cmp);
2087 return DAG.getNode(PPCISD::FSEL, ResVT, Cmp, TV, FV);
2092 // FIXME: Split this code up when LegalizeDAGTypes lands.
2093 static SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG) {
2094 assert(MVT::isFloatingPoint(Op.getOperand(0).getValueType()));
2095 SDOperand Src = Op.getOperand(0);
2096 if (Src.getValueType() == MVT::f32)
2097 Src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Src);
2100 switch (Op.getValueType()) {
2101 default: assert(0 && "Unhandled FP_TO_SINT type in custom expander!");
2103 Tmp = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Src);
2106 Tmp = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Src);
2110 // Convert the FP value to an int value through memory.
2111 SDOperand FIPtr = DAG.CreateStackTemporary(MVT::f64);
2113 // Emit a store to the stack slot.
2114 SDOperand Chain = DAG.getStore(DAG.getEntryNode(), Tmp, FIPtr, NULL, 0);
2116 // Result is a load from the stack slot. If loading 4 bytes, make sure to
2118 if (Op.getValueType() == MVT::i32)
2119 FIPtr = DAG.getNode(ISD::ADD, FIPtr.getValueType(), FIPtr,
2120 DAG.getConstant(4, FIPtr.getValueType()));
2121 return DAG.getLoad(Op.getValueType(), Chain, FIPtr, NULL, 0);
2124 static SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG) {
2125 assert(Op.getValueType() == MVT::ppcf128);
2126 SDNode *Node = Op.Val;
2127 assert(Node->getOperand(0).getValueType() == MVT::ppcf128);
2128 assert(Node->getOperand(0).Val->getOpcode() == ISD::BUILD_PAIR);
2129 SDOperand Lo = Node->getOperand(0).Val->getOperand(0);
2130 SDOperand Hi = Node->getOperand(0).Val->getOperand(1);
2132 // This sequence changes FPSCR to do round-to-zero, adds the two halves
2133 // of the long double, and puts FPSCR back the way it was. We do not
2134 // actually model FPSCR.
2135 std::vector<MVT::ValueType> NodeTys;
2136 SDOperand Ops[4], Result, MFFSreg, InFlag, FPreg;
2138 NodeTys.push_back(MVT::f64); // Return register
2139 NodeTys.push_back(MVT::Flag); // Returns a flag for later insns
2140 Result = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2141 MFFSreg = Result.getValue(0);
2142 InFlag = Result.getValue(1);
2145 NodeTys.push_back(MVT::Flag); // Returns a flag
2146 Ops[0] = DAG.getConstant(31, MVT::i32);
2148 Result = DAG.getNode(PPCISD::MTFSB1, NodeTys, Ops, 2);
2149 InFlag = Result.getValue(0);
2152 NodeTys.push_back(MVT::Flag); // Returns a flag
2153 Ops[0] = DAG.getConstant(30, MVT::i32);
2155 Result = DAG.getNode(PPCISD::MTFSB0, NodeTys, Ops, 2);
2156 InFlag = Result.getValue(0);
2159 NodeTys.push_back(MVT::f64); // result of add
2160 NodeTys.push_back(MVT::Flag); // Returns a flag
2164 Result = DAG.getNode(PPCISD::FADDRTZ, NodeTys, Ops, 3);
2165 FPreg = Result.getValue(0);
2166 InFlag = Result.getValue(1);
2169 NodeTys.push_back(MVT::f64);
2170 Ops[0] = DAG.getConstant(1, MVT::i32);
2174 Result = DAG.getNode(PPCISD::MTFSF, NodeTys, Ops, 4);
2175 FPreg = Result.getValue(0);
2177 // We know the low half is about to be thrown away, so just use something
2179 return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg);
2182 static SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG) {
2183 if (Op.getOperand(0).getValueType() == MVT::i64) {
2184 SDOperand Bits = DAG.getNode(ISD::BIT_CONVERT, MVT::f64, Op.getOperand(0));
2185 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Bits);
2186 if (Op.getValueType() == MVT::f32)
2187 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2191 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
2192 "Unhandled SINT_TO_FP type in custom expander!");
2193 // Since we only generate this in 64-bit mode, we can take advantage of
2194 // 64-bit registers. In particular, sign extend the input value into the
2195 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
2196 // then lfd it and fcfid it.
2197 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2198 int FrameIdx = FrameInfo->CreateStackObject(8, 8);
2199 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2200 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
2202 SDOperand Ext64 = DAG.getNode(PPCISD::EXTSW_32, MVT::i32,
2205 // STD the extended value into the stack slot.
2206 MemOperand MO(PseudoSourceValue::getFixedStack(),
2207 MemOperand::MOStore, FrameIdx, 8, 8);
2208 SDOperand Store = DAG.getNode(PPCISD::STD_32, MVT::Other,
2209 DAG.getEntryNode(), Ext64, FIdx,
2210 DAG.getMemOperand(MO));
2211 // Load the value as a double.
2212 SDOperand Ld = DAG.getLoad(MVT::f64, Store, FIdx, NULL, 0);
2214 // FCFID it and return it.
2215 SDOperand FP = DAG.getNode(PPCISD::FCFID, MVT::f64, Ld);
2216 if (Op.getValueType() == MVT::f32)
2217 FP = DAG.getNode(ISD::FP_ROUND, MVT::f32, FP, DAG.getIntPtrConstant(0));
2221 static SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG) {
2223 The rounding mode is in bits 30:31 of FPSR, and has the following
2230 FLT_ROUNDS, on the other hand, expects the following:
2237 To perform the conversion, we do:
2238 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
2241 MachineFunction &MF = DAG.getMachineFunction();
2242 MVT::ValueType VT = Op.getValueType();
2243 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2244 std::vector<MVT::ValueType> NodeTys;
2245 SDOperand MFFSreg, InFlag;
2247 // Save FP Control Word to register
2248 NodeTys.push_back(MVT::f64); // return register
2249 NodeTys.push_back(MVT::Flag); // unused in this context
2250 SDOperand Chain = DAG.getNode(PPCISD::MFFS, NodeTys, &InFlag, 0);
2252 // Save FP register to stack slot
2253 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8);
2254 SDOperand StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
2255 SDOperand Store = DAG.getStore(DAG.getEntryNode(), Chain,
2256 StackSlot, NULL, 0);
2258 // Load FP Control Word from low 32 bits of stack slot.
2259 SDOperand Four = DAG.getConstant(4, PtrVT);
2260 SDOperand Addr = DAG.getNode(ISD::ADD, PtrVT, StackSlot, Four);
2261 SDOperand CWD = DAG.getLoad(MVT::i32, Store, Addr, NULL, 0);
2263 // Transform as necessary
2265 DAG.getNode(ISD::AND, MVT::i32,
2266 CWD, DAG.getConstant(3, MVT::i32));
2268 DAG.getNode(ISD::SRL, MVT::i32,
2269 DAG.getNode(ISD::AND, MVT::i32,
2270 DAG.getNode(ISD::XOR, MVT::i32,
2271 CWD, DAG.getConstant(3, MVT::i32)),
2272 DAG.getConstant(3, MVT::i32)),
2273 DAG.getConstant(1, MVT::i8));
2276 DAG.getNode(ISD::XOR, MVT::i32, CWD1, CWD2);
2278 return DAG.getNode((MVT::getSizeInBits(VT) < 16 ?
2279 ISD::TRUNCATE : ISD::ZERO_EXTEND), VT, RetVal);
2282 static SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2283 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2284 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SHL!");
2286 // Expand into a bunch of logical ops. Note that these ops
2287 // depend on the PPC behavior for oversized shift amounts.
2288 SDOperand Lo = Op.getOperand(0);
2289 SDOperand Hi = Op.getOperand(1);
2290 SDOperand Amt = Op.getOperand(2);
2292 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2293 DAG.getConstant(32, MVT::i32), Amt);
2294 SDOperand Tmp2 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Amt);
2295 SDOperand Tmp3 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Tmp1);
2296 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2297 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2298 DAG.getConstant(-32U, MVT::i32));
2299 SDOperand Tmp6 = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Tmp5);
2300 SDOperand OutHi = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2301 SDOperand OutLo = DAG.getNode(PPCISD::SHL, MVT::i32, Lo, Amt);
2302 SDOperand OutOps[] = { OutLo, OutHi };
2303 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2307 static SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG) {
2308 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2309 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRL!");
2311 // Otherwise, expand into a bunch of logical ops. Note that these ops
2312 // depend on the PPC behavior for oversized shift amounts.
2313 SDOperand Lo = Op.getOperand(0);
2314 SDOperand Hi = Op.getOperand(1);
2315 SDOperand Amt = Op.getOperand(2);
2317 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2318 DAG.getConstant(32, MVT::i32), Amt);
2319 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2320 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2321 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2322 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2323 DAG.getConstant(-32U, MVT::i32));
2324 SDOperand Tmp6 = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Tmp5);
2325 SDOperand OutLo = DAG.getNode(ISD::OR, MVT::i32, Tmp4, Tmp6);
2326 SDOperand OutHi = DAG.getNode(PPCISD::SRL, MVT::i32, Hi, Amt);
2327 SDOperand OutOps[] = { OutLo, OutHi };
2328 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2332 static SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG) {
2333 assert(Op.getNumOperands() == 3 && Op.getValueType() == MVT::i32 &&
2334 Op.getOperand(1).getValueType() == MVT::i32 && "Unexpected SRA!");
2336 // Otherwise, expand into a bunch of logical ops, followed by a select_cc.
2337 SDOperand Lo = Op.getOperand(0);
2338 SDOperand Hi = Op.getOperand(1);
2339 SDOperand Amt = Op.getOperand(2);
2341 SDOperand Tmp1 = DAG.getNode(ISD::SUB, MVT::i32,
2342 DAG.getConstant(32, MVT::i32), Amt);
2343 SDOperand Tmp2 = DAG.getNode(PPCISD::SRL, MVT::i32, Lo, Amt);
2344 SDOperand Tmp3 = DAG.getNode(PPCISD::SHL, MVT::i32, Hi, Tmp1);
2345 SDOperand Tmp4 = DAG.getNode(ISD::OR , MVT::i32, Tmp2, Tmp3);
2346 SDOperand Tmp5 = DAG.getNode(ISD::ADD, MVT::i32, Amt,
2347 DAG.getConstant(-32U, MVT::i32));
2348 SDOperand Tmp6 = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Tmp5);
2349 SDOperand OutHi = DAG.getNode(PPCISD::SRA, MVT::i32, Hi, Amt);
2350 SDOperand OutLo = DAG.getSelectCC(Tmp5, DAG.getConstant(0, MVT::i32),
2351 Tmp4, Tmp6, ISD::SETLE);
2352 SDOperand OutOps[] = { OutLo, OutHi };
2353 return DAG.getNode(ISD::MERGE_VALUES, DAG.getVTList(MVT::i32, MVT::i32),
2357 //===----------------------------------------------------------------------===//
2358 // Vector related lowering.
2361 // If this is a vector of constants or undefs, get the bits. A bit in
2362 // UndefBits is set if the corresponding element of the vector is an
2363 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2364 // zero. Return true if this is not an array of constants, false if it is.
2366 static bool GetConstantBuildVectorBits(SDNode *BV, uint64_t VectorBits[2],
2367 uint64_t UndefBits[2]) {
2368 // Start with zero'd results.
2369 VectorBits[0] = VectorBits[1] = UndefBits[0] = UndefBits[1] = 0;
2371 unsigned EltBitSize = MVT::getSizeInBits(BV->getOperand(0).getValueType());
2372 for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
2373 SDOperand OpVal = BV->getOperand(i);
2375 unsigned PartNo = i >= e/2; // In the upper 128 bits?
2376 unsigned SlotNo = e/2 - (i & (e/2-1))-1; // Which subpiece of the uint64_t.
2378 uint64_t EltBits = 0;
2379 if (OpVal.getOpcode() == ISD::UNDEF) {
2380 uint64_t EltUndefBits = ~0U >> (32-EltBitSize);
2381 UndefBits[PartNo] |= EltUndefBits << (SlotNo*EltBitSize);
2383 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
2384 EltBits = CN->getValue() & (~0U >> (32-EltBitSize));
2385 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
2386 assert(CN->getValueType(0) == MVT::f32 &&
2387 "Only one legal FP vector type!");
2388 EltBits = FloatToBits(CN->getValueAPF().convertToFloat());
2390 // Nonconstant element.
2394 VectorBits[PartNo] |= EltBits << (SlotNo*EltBitSize);
2397 //printf("%llx %llx %llx %llx\n",
2398 // VectorBits[0], VectorBits[1], UndefBits[0], UndefBits[1]);
2402 // If this is a splat (repetition) of a value across the whole vector, return
2403 // the smallest size that splats it. For example, "0x01010101010101..." is a
2404 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2405 // SplatSize = 1 byte.
2406 static bool isConstantSplat(const uint64_t Bits128[2],
2407 const uint64_t Undef128[2],
2408 unsigned &SplatBits, unsigned &SplatUndef,
2409 unsigned &SplatSize) {
2411 // Don't let undefs prevent splats from matching. See if the top 64-bits are
2412 // the same as the lower 64-bits, ignoring undefs.
2413 if ((Bits128[0] & ~Undef128[1]) != (Bits128[1] & ~Undef128[0]))
2414 return false; // Can't be a splat if two pieces don't match.
2416 uint64_t Bits64 = Bits128[0] | Bits128[1];
2417 uint64_t Undef64 = Undef128[0] & Undef128[1];
2419 // Check that the top 32-bits are the same as the lower 32-bits, ignoring
2421 if ((Bits64 & (~Undef64 >> 32)) != ((Bits64 >> 32) & ~Undef64))
2422 return false; // Can't be a splat if two pieces don't match.
2424 uint32_t Bits32 = uint32_t(Bits64) | uint32_t(Bits64 >> 32);
2425 uint32_t Undef32 = uint32_t(Undef64) & uint32_t(Undef64 >> 32);
2427 // If the top 16-bits are different than the lower 16-bits, ignoring
2428 // undefs, we have an i32 splat.
2429 if ((Bits32 & (~Undef32 >> 16)) != ((Bits32 >> 16) & ~Undef32)) {
2431 SplatUndef = Undef32;
2436 uint16_t Bits16 = uint16_t(Bits32) | uint16_t(Bits32 >> 16);
2437 uint16_t Undef16 = uint16_t(Undef32) & uint16_t(Undef32 >> 16);
2439 // If the top 8-bits are different than the lower 8-bits, ignoring
2440 // undefs, we have an i16 splat.
2441 if ((Bits16 & (uint16_t(~Undef16) >> 8)) != ((Bits16 >> 8) & ~Undef16)) {
2443 SplatUndef = Undef16;
2448 // Otherwise, we have an 8-bit splat.
2449 SplatBits = uint8_t(Bits16) | uint8_t(Bits16 >> 8);
2450 SplatUndef = uint8_t(Undef16) & uint8_t(Undef16 >> 8);
2455 /// BuildSplatI - Build a canonical splati of Val with an element size of
2456 /// SplatSize. Cast the result to VT.
2457 static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
2458 SelectionDAG &DAG) {
2459 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
2461 static const MVT::ValueType VTys[] = { // canonical VT to use for each size.
2462 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
2465 MVT::ValueType ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
2467 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
2471 MVT::ValueType CanonicalVT = VTys[SplatSize-1];
2473 // Build a canonical splat for this value.
2474 SDOperand Elt = DAG.getConstant(Val, MVT::getVectorElementType(CanonicalVT));
2475 SmallVector<SDOperand, 8> Ops;
2476 Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
2477 SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
2478 &Ops[0], Ops.size());
2479 return DAG.getNode(ISD::BIT_CONVERT, ReqVT, Res);
2482 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
2483 /// specified intrinsic ID.
2484 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand LHS, SDOperand RHS,
2486 MVT::ValueType DestVT = MVT::Other) {
2487 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
2488 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2489 DAG.getConstant(IID, MVT::i32), LHS, RHS);
2492 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
2493 /// specified intrinsic ID.
2494 static SDOperand BuildIntrinsicOp(unsigned IID, SDOperand Op0, SDOperand Op1,
2495 SDOperand Op2, SelectionDAG &DAG,
2496 MVT::ValueType DestVT = MVT::Other) {
2497 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
2498 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DestVT,
2499 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
2503 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
2504 /// amount. The result has the specified value type.
2505 static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
2506 MVT::ValueType VT, SelectionDAG &DAG) {
2507 // Force LHS/RHS to be the right type.
2508 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
2509 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
2512 for (unsigned i = 0; i != 16; ++i)
2513 Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
2514 SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
2515 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
2516 return DAG.getNode(ISD::BIT_CONVERT, VT, T);
2519 // If this is a case we can't handle, return null and let the default
2520 // expansion code take care of it. If we CAN select this case, and if it
2521 // selects to a single instruction, return Op. Otherwise, if we can codegen
2522 // this case more efficiently than a constant pool load, lower it to the
2523 // sequence of ops that should be used.
2524 static SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2525 // If this is a vector of constants or undefs, get the bits. A bit in
2526 // UndefBits is set if the corresponding element of the vector is an
2527 // ISD::UNDEF value. For undefs, the corresponding VectorBits values are
2529 uint64_t VectorBits[2];
2530 uint64_t UndefBits[2];
2531 if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits))
2532 return SDOperand(); // Not a constant vector.
2534 // If this is a splat (repetition) of a value across the whole vector, return
2535 // the smallest size that splats it. For example, "0x01010101010101..." is a
2536 // splat of 0x01, 0x0101, and 0x01010101. We return SplatBits = 0x01 and
2537 // SplatSize = 1 byte.
2538 unsigned SplatBits, SplatUndef, SplatSize;
2539 if (isConstantSplat(VectorBits, UndefBits, SplatBits, SplatUndef, SplatSize)){
2540 bool HasAnyUndefs = (UndefBits[0] | UndefBits[1]) != 0;
2542 // First, handle single instruction cases.
2545 if (SplatBits == 0) {
2546 // Canonicalize all zero vectors to be v4i32.
2547 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
2548 SDOperand Z = DAG.getConstant(0, MVT::i32);
2549 Z = DAG.getNode(ISD::BUILD_VECTOR, MVT::v4i32, Z, Z, Z, Z);
2550 Op = DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Z);
2555 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
2556 int32_t SextVal= int32_t(SplatBits << (32-8*SplatSize)) >> (32-8*SplatSize);
2557 if (SextVal >= -16 && SextVal <= 15)
2558 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG);
2561 // Two instruction sequences.
2563 // If this value is in the range [-32,30] and is even, use:
2564 // tmp = VSPLTI[bhw], result = add tmp, tmp
2565 if (SextVal >= -32 && SextVal <= 30 && (SextVal & 1) == 0) {
2566 Op = BuildSplatI(SextVal >> 1, SplatSize, Op.getValueType(), DAG);
2567 return DAG.getNode(ISD::ADD, Op.getValueType(), Op, Op);
2570 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
2571 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
2573 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
2574 // Make -1 and vspltisw -1:
2575 SDOperand OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG);
2577 // Make the VSLW intrinsic, computing 0x8000_0000.
2578 SDOperand Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
2581 // xor by OnesV to invert it.
2582 Res = DAG.getNode(ISD::XOR, MVT::v4i32, Res, OnesV);
2583 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2586 // Check to see if this is a wide variety of vsplti*, binop self cases.
2587 unsigned SplatBitSize = SplatSize*8;
2588 static const signed char SplatCsts[] = {
2589 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
2590 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
2593 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
2594 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
2595 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
2596 int i = SplatCsts[idx];
2598 // Figure out what shift amount will be used by altivec if shifted by i in
2600 unsigned TypeShiftAmt = i & (SplatBitSize-1);
2602 // vsplti + shl self.
2603 if (SextVal == (i << (int)TypeShiftAmt)) {
2604 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2605 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2606 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
2607 Intrinsic::ppc_altivec_vslw
2609 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2610 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2613 // vsplti + srl self.
2614 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2615 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2616 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2617 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
2618 Intrinsic::ppc_altivec_vsrw
2620 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2621 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2624 // vsplti + sra self.
2625 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
2626 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2627 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2628 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
2629 Intrinsic::ppc_altivec_vsraw
2631 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2632 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2635 // vsplti + rol self.
2636 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
2637 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
2638 SDOperand Res = BuildSplatI(i, SplatSize, MVT::Other, DAG);
2639 static const unsigned IIDs[] = { // Intrinsic to use for each size.
2640 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
2641 Intrinsic::ppc_altivec_vrlw
2643 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG);
2644 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Res);
2647 // t = vsplti c, result = vsldoi t, t, 1
2648 if (SextVal == ((i << 8) | (i >> (TypeShiftAmt-8)))) {
2649 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2650 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG);
2652 // t = vsplti c, result = vsldoi t, t, 2
2653 if (SextVal == ((i << 16) | (i >> (TypeShiftAmt-16)))) {
2654 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2655 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG);
2657 // t = vsplti c, result = vsldoi t, t, 3
2658 if (SextVal == ((i << 24) | (i >> (TypeShiftAmt-24)))) {
2659 SDOperand T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG);
2660 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG);
2664 // Three instruction sequences.
2666 // Odd, in range [17,31]: (vsplti C)-(vsplti -16).
2667 if (SextVal >= 0 && SextVal <= 31) {
2668 SDOperand LHS = BuildSplatI(SextVal-16, SplatSize, MVT::Other, DAG);
2669 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2670 LHS = DAG.getNode(ISD::SUB, LHS.getValueType(), LHS, RHS);
2671 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2673 // Odd, in range [-31,-17]: (vsplti C)+(vsplti -16).
2674 if (SextVal >= -31 && SextVal <= 0) {
2675 SDOperand LHS = BuildSplatI(SextVal+16, SplatSize, MVT::Other, DAG);
2676 SDOperand RHS = BuildSplatI(-16, SplatSize, MVT::Other, DAG);
2677 LHS = DAG.getNode(ISD::ADD, LHS.getValueType(), LHS, RHS);
2678 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), LHS);
2685 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
2686 /// the specified operations to build the shuffle.
2687 static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
2688 SDOperand RHS, SelectionDAG &DAG) {
2689 unsigned OpNum = (PFEntry >> 26) & 0x0F;
2690 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
2691 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
2694 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
2706 if (OpNum == OP_COPY) {
2707 if (LHSID == (1*9+2)*9+3) return LHS;
2708 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
2712 SDOperand OpLHS, OpRHS;
2713 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG);
2714 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG);
2716 unsigned ShufIdxs[16];
2718 default: assert(0 && "Unknown i32 permute!");
2720 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
2721 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
2722 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
2723 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
2726 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
2727 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
2728 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
2729 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
2732 for (unsigned i = 0; i != 16; ++i)
2733 ShufIdxs[i] = (i&3)+0;
2736 for (unsigned i = 0; i != 16; ++i)
2737 ShufIdxs[i] = (i&3)+4;
2740 for (unsigned i = 0; i != 16; ++i)
2741 ShufIdxs[i] = (i&3)+8;
2744 for (unsigned i = 0; i != 16; ++i)
2745 ShufIdxs[i] = (i&3)+12;
2748 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG);
2750 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG);
2752 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
2755 for (unsigned i = 0; i != 16; ++i)
2756 Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
2758 return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
2759 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
2762 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
2763 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
2764 /// return the code it can be lowered into. Worst case, it can always be
2765 /// lowered into a vperm.
2766 static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
2767 SDOperand V1 = Op.getOperand(0);
2768 SDOperand V2 = Op.getOperand(1);
2769 SDOperand PermMask = Op.getOperand(2);
2771 // Cases that are handled by instructions that take permute immediates
2772 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
2773 // selected by the instruction selector.
2774 if (V2.getOpcode() == ISD::UNDEF) {
2775 if (PPC::isSplatShuffleMask(PermMask.Val, 1) ||
2776 PPC::isSplatShuffleMask(PermMask.Val, 2) ||
2777 PPC::isSplatShuffleMask(PermMask.Val, 4) ||
2778 PPC::isVPKUWUMShuffleMask(PermMask.Val, true) ||
2779 PPC::isVPKUHUMShuffleMask(PermMask.Val, true) ||
2780 PPC::isVSLDOIShuffleMask(PermMask.Val, true) != -1 ||
2781 PPC::isVMRGLShuffleMask(PermMask.Val, 1, true) ||
2782 PPC::isVMRGLShuffleMask(PermMask.Val, 2, true) ||
2783 PPC::isVMRGLShuffleMask(PermMask.Val, 4, true) ||
2784 PPC::isVMRGHShuffleMask(PermMask.Val, 1, true) ||
2785 PPC::isVMRGHShuffleMask(PermMask.Val, 2, true) ||
2786 PPC::isVMRGHShuffleMask(PermMask.Val, 4, true)) {
2791 // Altivec has a variety of "shuffle immediates" that take two vector inputs
2792 // and produce a fixed permutation. If any of these match, do not lower to
2794 if (PPC::isVPKUWUMShuffleMask(PermMask.Val, false) ||
2795 PPC::isVPKUHUMShuffleMask(PermMask.Val, false) ||
2796 PPC::isVSLDOIShuffleMask(PermMask.Val, false) != -1 ||
2797 PPC::isVMRGLShuffleMask(PermMask.Val, 1, false) ||
2798 PPC::isVMRGLShuffleMask(PermMask.Val, 2, false) ||
2799 PPC::isVMRGLShuffleMask(PermMask.Val, 4, false) ||
2800 PPC::isVMRGHShuffleMask(PermMask.Val, 1, false) ||
2801 PPC::isVMRGHShuffleMask(PermMask.Val, 2, false) ||
2802 PPC::isVMRGHShuffleMask(PermMask.Val, 4, false))
2805 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
2806 // perfect shuffle table to emit an optimal matching sequence.
2807 unsigned PFIndexes[4];
2808 bool isFourElementShuffle = true;
2809 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
2810 unsigned EltNo = 8; // Start out undef.
2811 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
2812 if (PermMask.getOperand(i*4+j).getOpcode() == ISD::UNDEF)
2813 continue; // Undef, ignore it.
2815 unsigned ByteSource =
2816 cast<ConstantSDNode>(PermMask.getOperand(i*4+j))->getValue();
2817 if ((ByteSource & 3) != j) {
2818 isFourElementShuffle = false;
2823 EltNo = ByteSource/4;
2824 } else if (EltNo != ByteSource/4) {
2825 isFourElementShuffle = false;
2829 PFIndexes[i] = EltNo;
2832 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
2833 // perfect shuffle vector to determine if it is cost effective to do this as
2834 // discrete instructions, or whether we should use a vperm.
2835 if (isFourElementShuffle) {
2836 // Compute the index in the perfect shuffle table.
2837 unsigned PFTableIndex =
2838 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
2840 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
2841 unsigned Cost = (PFEntry >> 30);
2843 // Determining when to avoid vperm is tricky. Many things affect the cost
2844 // of vperm, particularly how many times the perm mask needs to be computed.
2845 // For example, if the perm mask can be hoisted out of a loop or is already
2846 // used (perhaps because there are multiple permutes with the same shuffle
2847 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
2848 // the loop requires an extra register.
2850 // As a compromise, we only emit discrete instructions if the shuffle can be
2851 // generated in 3 or fewer operations. When we have loop information
2852 // available, if this block is within a loop, we should avoid using vperm
2853 // for 3-operation perms and use a constant pool load instead.
2855 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG);
2858 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
2859 // vector that will get spilled to the constant pool.
2860 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
2862 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
2863 // that it is in input element units, not in bytes. Convert now.
2864 MVT::ValueType EltVT = MVT::getVectorElementType(V1.getValueType());
2865 unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
2867 SmallVector<SDOperand, 16> ResultMask;
2868 for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
2870 if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
2873 SrcElt = cast<ConstantSDNode>(PermMask.getOperand(i))->getValue();
2875 for (unsigned j = 0; j != BytesPerElement; ++j)
2876 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
2880 SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
2881 &ResultMask[0], ResultMask.size());
2882 return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
2885 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
2886 /// altivec comparison. If it is, return true and fill in Opc/isDot with
2887 /// information about the intrinsic.
2888 static bool getAltivecCompareInfo(SDOperand Intrin, int &CompareOpc,
2890 unsigned IntrinsicID = cast<ConstantSDNode>(Intrin.getOperand(0))->getValue();
2893 switch (IntrinsicID) {
2894 default: return false;
2895 // Comparison predicates.
2896 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
2897 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
2898 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
2899 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
2900 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
2901 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
2902 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
2903 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
2904 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
2905 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
2906 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
2907 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
2908 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
2910 // Normal Comparisons.
2911 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
2912 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
2913 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
2914 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
2915 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
2916 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
2917 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
2918 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
2919 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
2920 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
2921 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
2922 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
2923 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
2928 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
2929 /// lower, do it, otherwise return null.
2930 static SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG) {
2931 // If this is a lowered altivec predicate compare, CompareOpc is set to the
2932 // opcode number of the comparison.
2935 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
2936 return SDOperand(); // Don't custom lower most intrinsics.
2938 // If this is a non-dot comparison, make the VCMP node and we are done.
2940 SDOperand Tmp = DAG.getNode(PPCISD::VCMP, Op.getOperand(2).getValueType(),
2941 Op.getOperand(1), Op.getOperand(2),
2942 DAG.getConstant(CompareOpc, MVT::i32));
2943 return DAG.getNode(ISD::BIT_CONVERT, Op.getValueType(), Tmp);
2946 // Create the PPCISD altivec 'dot' comparison node.
2948 Op.getOperand(2), // LHS
2949 Op.getOperand(3), // RHS
2950 DAG.getConstant(CompareOpc, MVT::i32)
2952 std::vector<MVT::ValueType> VTs;
2953 VTs.push_back(Op.getOperand(2).getValueType());
2954 VTs.push_back(MVT::Flag);
2955 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
2957 // Now that we have the comparison, emit a copy from the CR to a GPR.
2958 // This is flagged to the above dot comparison.
2959 SDOperand Flags = DAG.getNode(PPCISD::MFCR, MVT::i32,
2960 DAG.getRegister(PPC::CR6, MVT::i32),
2961 CompNode.getValue(1));
2963 // Unpack the result based on how the target uses it.
2964 unsigned BitNo; // Bit # of CR6.
2965 bool InvertBit; // Invert result?
2966 switch (cast<ConstantSDNode>(Op.getOperand(1))->getValue()) {
2967 default: // Can't happen, don't crash on invalid number though.
2968 case 0: // Return the value of the EQ bit of CR6.
2969 BitNo = 0; InvertBit = false;
2971 case 1: // Return the inverted value of the EQ bit of CR6.
2972 BitNo = 0; InvertBit = true;
2974 case 2: // Return the value of the LT bit of CR6.
2975 BitNo = 2; InvertBit = false;
2977 case 3: // Return the inverted value of the LT bit of CR6.
2978 BitNo = 2; InvertBit = true;
2982 // Shift the bit into the low position.
2983 Flags = DAG.getNode(ISD::SRL, MVT::i32, Flags,
2984 DAG.getConstant(8-(3-BitNo), MVT::i32));
2986 Flags = DAG.getNode(ISD::AND, MVT::i32, Flags,
2987 DAG.getConstant(1, MVT::i32));
2989 // If we are supposed to, toggle the bit.
2991 Flags = DAG.getNode(ISD::XOR, MVT::i32, Flags,
2992 DAG.getConstant(1, MVT::i32));
2996 static SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG) {
2997 // Create a stack slot that is 16-byte aligned.
2998 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
2999 int FrameIdx = FrameInfo->CreateStackObject(16, 16);
3000 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3001 SDOperand FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
3003 // Store the input value into Value#0 of the stack slot.
3004 SDOperand Store = DAG.getStore(DAG.getEntryNode(),
3005 Op.getOperand(0), FIdx, NULL, 0);
3007 return DAG.getLoad(Op.getValueType(), Store, FIdx, NULL, 0);
3010 static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
3011 if (Op.getValueType() == MVT::v4i32) {
3012 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3014 SDOperand Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG);
3015 SDOperand Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG); // +16 as shift amt.
3017 SDOperand RHSSwap = // = vrlw RHS, 16
3018 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG);
3020 // Shrinkify inputs to v8i16.
3021 LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, LHS);
3022 RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHS);
3023 RHSSwap = DAG.getNode(ISD::BIT_CONVERT, MVT::v8i16, RHSSwap);
3025 // Low parts multiplied together, generating 32-bit results (we ignore the
3027 SDOperand LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
3028 LHS, RHS, DAG, MVT::v4i32);
3030 SDOperand HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
3031 LHS, RHSSwap, Zero, DAG, MVT::v4i32);
3032 // Shift the high parts up 16 bits.
3033 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd, Neg16, DAG);
3034 return DAG.getNode(ISD::ADD, MVT::v4i32, LoProd, HiProd);
3035 } else if (Op.getValueType() == MVT::v8i16) {
3036 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3038 SDOperand Zero = BuildSplatI(0, 1, MVT::v8i16, DAG);
3040 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
3041 LHS, RHS, Zero, DAG);
3042 } else if (Op.getValueType() == MVT::v16i8) {
3043 SDOperand LHS = Op.getOperand(0), RHS = Op.getOperand(1);
3045 // Multiply the even 8-bit parts, producing 16-bit sums.
3046 SDOperand EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
3047 LHS, RHS, DAG, MVT::v8i16);
3048 EvenParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, EvenParts);
3050 // Multiply the odd 8-bit parts, producing 16-bit sums.
3051 SDOperand OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
3052 LHS, RHS, DAG, MVT::v8i16);
3053 OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
3055 // Merge the results together.
3057 for (unsigned i = 0; i != 8; ++i) {
3058 Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
3059 Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
3061 return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
3062 DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
3064 assert(0 && "Unknown mul to lower!");
3069 /// LowerOperation - Provide custom lowering hooks for some operations.
3071 SDOperand PPCTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
3072 switch (Op.getOpcode()) {
3073 default: assert(0 && "Wasn't expecting to be able to lower this!");
3074 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
3075 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
3076 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
3077 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
3078 case ISD::SETCC: return LowerSETCC(Op, DAG);
3080 return LowerVASTART(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3081 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3084 return LowerVAARG(Op, DAG, VarArgsFrameIndex, VarArgsStackOffset,
3085 VarArgsNumGPR, VarArgsNumFPR, PPCSubTarget);
3087 case ISD::FORMAL_ARGUMENTS:
3088 return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsFrameIndex,
3089 VarArgsStackOffset, VarArgsNumGPR,
3090 VarArgsNumFPR, PPCSubTarget);
3092 case ISD::CALL: return LowerCALL(Op, DAG, PPCSubTarget);
3093 case ISD::RET: return LowerRET(Op, DAG, getTargetMachine());
3094 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, PPCSubTarget);
3095 case ISD::DYNAMIC_STACKALLOC:
3096 return LowerDYNAMIC_STACKALLOC(Op, DAG, PPCSubTarget);
3098 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
3099 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
3100 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG);
3101 case ISD::FP_ROUND_INREG: return LowerFP_ROUND_INREG(Op, DAG);
3102 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
3104 // Lower 64-bit shifts.
3105 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
3106 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
3107 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
3109 // Vector-related lowering.
3110 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
3111 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
3112 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
3113 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
3114 case ISD::MUL: return LowerMUL(Op, DAG);
3116 // Frame & Return address.
3117 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
3118 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
3123 SDNode *PPCTargetLowering::ExpandOperationResult(SDNode *N, SelectionDAG &DAG) {
3124 switch (N->getOpcode()) {
3125 default: assert(0 && "Wasn't expecting to be able to lower this!");
3126 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(SDOperand(N, 0), DAG).Val;
3131 //===----------------------------------------------------------------------===//
3132 // Other Lowering Code
3133 //===----------------------------------------------------------------------===//
3136 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
3137 MachineBasicBlock *BB) {
3138 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
3139 assert((MI->getOpcode() == PPC::SELECT_CC_I4 ||
3140 MI->getOpcode() == PPC::SELECT_CC_I8 ||
3141 MI->getOpcode() == PPC::SELECT_CC_F4 ||
3142 MI->getOpcode() == PPC::SELECT_CC_F8 ||
3143 MI->getOpcode() == PPC::SELECT_CC_VRRC) &&
3144 "Unexpected instr type to insert");
3146 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
3147 // control-flow pattern. The incoming instruction knows the destination vreg
3148 // to set, the condition code register to branch on, the true/false values to
3149 // select between, and a branch opcode to use.
3150 const BasicBlock *LLVM_BB = BB->getBasicBlock();
3151 ilist<MachineBasicBlock>::iterator It = BB;
3157 // cmpTY ccX, r1, r2
3159 // fallthrough --> copy0MBB
3160 MachineBasicBlock *thisMBB = BB;
3161 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
3162 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
3163 unsigned SelectPred = MI->getOperand(4).getImm();
3164 BuildMI(BB, TII->get(PPC::BCC))
3165 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
3166 MachineFunction *F = BB->getParent();
3167 F->getBasicBlockList().insert(It, copy0MBB);
3168 F->getBasicBlockList().insert(It, sinkMBB);
3169 // Update machine-CFG edges by first adding all successors of the current
3170 // block to the new block which will contain the Phi node for the select.
3171 for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
3172 e = BB->succ_end(); i != e; ++i)
3173 sinkMBB->addSuccessor(*i);
3174 // Next, remove all successors of the current block, and add the true
3175 // and fallthrough blocks as its successors.
3176 while(!BB->succ_empty())
3177 BB->removeSuccessor(BB->succ_begin());
3178 BB->addSuccessor(copy0MBB);
3179 BB->addSuccessor(sinkMBB);
3182 // %FalseValue = ...
3183 // # fallthrough to sinkMBB
3186 // Update machine-CFG edges
3187 BB->addSuccessor(sinkMBB);
3190 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
3193 BuildMI(BB, TII->get(PPC::PHI), MI->getOperand(0).getReg())
3194 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
3195 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
3197 delete MI; // The pseudo instruction is gone now.
3201 //===----------------------------------------------------------------------===//
3202 // Target Optimization Hooks
3203 //===----------------------------------------------------------------------===//
3205 SDOperand PPCTargetLowering::PerformDAGCombine(SDNode *N,
3206 DAGCombinerInfo &DCI) const {
3207 TargetMachine &TM = getTargetMachine();
3208 SelectionDAG &DAG = DCI.DAG;
3209 switch (N->getOpcode()) {
3212 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3213 if (C->getValue() == 0) // 0 << V -> 0.
3214 return N->getOperand(0);
3218 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3219 if (C->getValue() == 0) // 0 >>u V -> 0.
3220 return N->getOperand(0);
3224 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
3225 if (C->getValue() == 0 || // 0 >>s V -> 0.
3226 C->isAllOnesValue()) // -1 >>s V -> -1.
3227 return N->getOperand(0);
3231 case ISD::SINT_TO_FP:
3232 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
3233 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
3234 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
3235 // We allow the src/dst to be either f32/f64, but the intermediate
3236 // type must be i64.
3237 if (N->getOperand(0).getValueType() == MVT::i64 &&
3238 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
3239 SDOperand Val = N->getOperand(0).getOperand(0);
3240 if (Val.getValueType() == MVT::f32) {
3241 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3242 DCI.AddToWorklist(Val.Val);
3245 Val = DAG.getNode(PPCISD::FCTIDZ, MVT::f64, Val);
3246 DCI.AddToWorklist(Val.Val);
3247 Val = DAG.getNode(PPCISD::FCFID, MVT::f64, Val);
3248 DCI.AddToWorklist(Val.Val);
3249 if (N->getValueType(0) == MVT::f32) {
3250 Val = DAG.getNode(ISD::FP_ROUND, MVT::f32, Val,
3251 DAG.getIntPtrConstant(0));
3252 DCI.AddToWorklist(Val.Val);
3255 } else if (N->getOperand(0).getValueType() == MVT::i32) {
3256 // If the intermediate type is i32, we can avoid the load/store here
3263 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
3264 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
3265 !cast<StoreSDNode>(N)->isTruncatingStore() &&
3266 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
3267 N->getOperand(1).getValueType() == MVT::i32 &&
3268 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
3269 SDOperand Val = N->getOperand(1).getOperand(0);
3270 if (Val.getValueType() == MVT::f32) {
3271 Val = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Val);
3272 DCI.AddToWorklist(Val.Val);
3274 Val = DAG.getNode(PPCISD::FCTIWZ, MVT::f64, Val);
3275 DCI.AddToWorklist(Val.Val);
3277 Val = DAG.getNode(PPCISD::STFIWX, MVT::Other, N->getOperand(0), Val,
3278 N->getOperand(2), N->getOperand(3));
3279 DCI.AddToWorklist(Val.Val);
3283 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
3284 if (N->getOperand(1).getOpcode() == ISD::BSWAP &&
3285 N->getOperand(1).Val->hasOneUse() &&
3286 (N->getOperand(1).getValueType() == MVT::i32 ||
3287 N->getOperand(1).getValueType() == MVT::i16)) {
3288 SDOperand BSwapOp = N->getOperand(1).getOperand(0);
3289 // Do an any-extend to 32-bits if this is a half-word input.
3290 if (BSwapOp.getValueType() == MVT::i16)
3291 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, MVT::i32, BSwapOp);
3293 return DAG.getNode(PPCISD::STBRX, MVT::Other, N->getOperand(0), BSwapOp,
3294 N->getOperand(2), N->getOperand(3),
3295 DAG.getValueType(N->getOperand(1).getValueType()));
3299 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
3300 if (ISD::isNON_EXTLoad(N->getOperand(0).Val) &&
3301 N->getOperand(0).hasOneUse() &&
3302 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16)) {
3303 SDOperand Load = N->getOperand(0);
3304 LoadSDNode *LD = cast<LoadSDNode>(Load);
3305 // Create the byte-swapping load.
3306 std::vector<MVT::ValueType> VTs;
3307 VTs.push_back(MVT::i32);
3308 VTs.push_back(MVT::Other);
3309 SDOperand MO = DAG.getMemOperand(LD->getMemOperand());
3311 LD->getChain(), // Chain
3312 LD->getBasePtr(), // Ptr
3314 DAG.getValueType(N->getValueType(0)) // VT
3316 SDOperand BSLoad = DAG.getNode(PPCISD::LBRX, VTs, Ops, 4);
3318 // If this is an i16 load, insert the truncate.
3319 SDOperand ResVal = BSLoad;
3320 if (N->getValueType(0) == MVT::i16)
3321 ResVal = DAG.getNode(ISD::TRUNCATE, MVT::i16, BSLoad);
3323 // First, combine the bswap away. This makes the value produced by the
3325 DCI.CombineTo(N, ResVal);
3327 // Next, combine the load away, we give it a bogus result value but a real
3328 // chain result. The result value is dead because the bswap is dead.
3329 DCI.CombineTo(Load.Val, ResVal, BSLoad.getValue(1));
3331 // Return N so it doesn't get rechecked!
3332 return SDOperand(N, 0);
3336 case PPCISD::VCMP: {
3337 // If a VCMPo node already exists with exactly the same operands as this
3338 // node, use its result instead of this node (VCMPo computes both a CR6 and
3339 // a normal output).
3341 if (!N->getOperand(0).hasOneUse() &&
3342 !N->getOperand(1).hasOneUse() &&
3343 !N->getOperand(2).hasOneUse()) {
3345 // Scan all of the users of the LHS, looking for VCMPo's that match.
3346 SDNode *VCMPoNode = 0;
3348 SDNode *LHSN = N->getOperand(0).Val;
3349 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
3351 if ((*UI)->getOpcode() == PPCISD::VCMPo &&
3352 (*UI)->getOperand(1) == N->getOperand(1) &&
3353 (*UI)->getOperand(2) == N->getOperand(2) &&
3354 (*UI)->getOperand(0) == N->getOperand(0)) {
3359 // If there is no VCMPo node, or if the flag value has a single use, don't
3361 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
3364 // Look at the (necessarily single) use of the flag value. If it has a
3365 // chain, this transformation is more complex. Note that multiple things
3366 // could use the value result, which we should ignore.
3367 SDNode *FlagUser = 0;
3368 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
3369 FlagUser == 0; ++UI) {
3370 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
3372 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
3373 if (User->getOperand(i) == SDOperand(VCMPoNode, 1)) {
3380 // If the user is a MFCR instruction, we know this is safe. Otherwise we
3381 // give up for right now.
3382 if (FlagUser->getOpcode() == PPCISD::MFCR)
3383 return SDOperand(VCMPoNode, 0);
3388 // If this is a branch on an altivec predicate comparison, lower this so
3389 // that we don't have to do a MFCR: instead, branch directly on CR6. This
3390 // lowering is done pre-legalize, because the legalizer lowers the predicate
3391 // compare down to code that is difficult to reassemble.
3392 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
3393 SDOperand LHS = N->getOperand(2), RHS = N->getOperand(3);
3397 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
3398 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
3399 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
3400 assert(isDot && "Can't compare against a vector result!");
3402 // If this is a comparison against something other than 0/1, then we know
3403 // that the condition is never/always true.
3404 unsigned Val = cast<ConstantSDNode>(RHS)->getValue();
3405 if (Val != 0 && Val != 1) {
3406 if (CC == ISD::SETEQ) // Cond never true, remove branch.
3407 return N->getOperand(0);
3408 // Always !=, turn it into an unconditional branch.
3409 return DAG.getNode(ISD::BR, MVT::Other,
3410 N->getOperand(0), N->getOperand(4));
3413 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
3415 // Create the PPCISD altivec 'dot' comparison node.
3416 std::vector<MVT::ValueType> VTs;
3418 LHS.getOperand(2), // LHS of compare
3419 LHS.getOperand(3), // RHS of compare
3420 DAG.getConstant(CompareOpc, MVT::i32)
3422 VTs.push_back(LHS.getOperand(2).getValueType());
3423 VTs.push_back(MVT::Flag);
3424 SDOperand CompNode = DAG.getNode(PPCISD::VCMPo, VTs, Ops, 3);
3426 // Unpack the result based on how the target uses it.
3427 PPC::Predicate CompOpc;
3428 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getValue()) {
3429 default: // Can't happen, don't crash on invalid number though.
3430 case 0: // Branch on the value of the EQ bit of CR6.
3431 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
3433 case 1: // Branch on the inverted value of the EQ bit of CR6.
3434 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
3436 case 2: // Branch on the value of the LT bit of CR6.
3437 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
3439 case 3: // Branch on the inverted value of the LT bit of CR6.
3440 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
3444 return DAG.getNode(PPCISD::COND_BRANCH, MVT::Other, N->getOperand(0),
3445 DAG.getConstant(CompOpc, MVT::i32),
3446 DAG.getRegister(PPC::CR6, MVT::i32),
3447 N->getOperand(4), CompNode.getValue(1));
3456 //===----------------------------------------------------------------------===//
3457 // Inline Assembly Support
3458 //===----------------------------------------------------------------------===//
3460 void PPCTargetLowering::computeMaskedBitsForTargetNode(const SDOperand Op,
3464 const SelectionDAG &DAG,
3465 unsigned Depth) const {
3466 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
3467 switch (Op.getOpcode()) {
3469 case PPCISD::LBRX: {
3470 // lhbrx is known to have the top bits cleared out.
3471 if (cast<VTSDNode>(Op.getOperand(3))->getVT() == MVT::i16)
3472 KnownZero = 0xFFFF0000;
3475 case ISD::INTRINSIC_WO_CHAIN: {
3476 switch (cast<ConstantSDNode>(Op.getOperand(0))->getValue()) {
3478 case Intrinsic::ppc_altivec_vcmpbfp_p:
3479 case Intrinsic::ppc_altivec_vcmpeqfp_p:
3480 case Intrinsic::ppc_altivec_vcmpequb_p:
3481 case Intrinsic::ppc_altivec_vcmpequh_p:
3482 case Intrinsic::ppc_altivec_vcmpequw_p:
3483 case Intrinsic::ppc_altivec_vcmpgefp_p:
3484 case Intrinsic::ppc_altivec_vcmpgtfp_p:
3485 case Intrinsic::ppc_altivec_vcmpgtsb_p:
3486 case Intrinsic::ppc_altivec_vcmpgtsh_p:
3487 case Intrinsic::ppc_altivec_vcmpgtsw_p:
3488 case Intrinsic::ppc_altivec_vcmpgtub_p:
3489 case Intrinsic::ppc_altivec_vcmpgtuh_p:
3490 case Intrinsic::ppc_altivec_vcmpgtuw_p:
3491 KnownZero = ~1U; // All bits but the low one are known to be zero.
3499 /// getConstraintType - Given a constraint, return the type of
3500 /// constraint it is for this target.
3501 PPCTargetLowering::ConstraintType
3502 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
3503 if (Constraint.size() == 1) {
3504 switch (Constraint[0]) {
3511 return C_RegisterClass;
3514 return TargetLowering::getConstraintType(Constraint);
3517 std::pair<unsigned, const TargetRegisterClass*>
3518 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
3519 MVT::ValueType VT) const {
3520 if (Constraint.size() == 1) {
3521 // GCC RS6000 Constraint Letters
3522 switch (Constraint[0]) {
3525 if (VT == MVT::i64 && PPCSubTarget.isPPC64())
3526 return std::make_pair(0U, PPC::G8RCRegisterClass);
3527 return std::make_pair(0U, PPC::GPRCRegisterClass);
3530 return std::make_pair(0U, PPC::F4RCRegisterClass);
3531 else if (VT == MVT::f64)
3532 return std::make_pair(0U, PPC::F8RCRegisterClass);
3535 return std::make_pair(0U, PPC::VRRCRegisterClass);
3537 return std::make_pair(0U, PPC::CRRCRegisterClass);
3541 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
3545 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
3546 /// vector. If it is invalid, don't add anything to Ops.
3547 void PPCTargetLowering::LowerAsmOperandForConstraint(SDOperand Op, char Letter,
3548 std::vector<SDOperand>&Ops,
3549 SelectionDAG &DAG) {
3550 SDOperand Result(0,0);
3561 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
3562 if (!CST) return; // Must be an immediate to match.
3563 unsigned Value = CST->getValue();
3565 default: assert(0 && "Unknown constraint letter!");
3566 case 'I': // "I" is a signed 16-bit constant.
3567 if ((short)Value == (int)Value)
3568 Result = DAG.getTargetConstant(Value, Op.getValueType());
3570 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
3571 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
3572 if ((short)Value == 0)
3573 Result = DAG.getTargetConstant(Value, Op.getValueType());
3575 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
3576 if ((Value >> 16) == 0)
3577 Result = DAG.getTargetConstant(Value, Op.getValueType());
3579 case 'M': // "M" is a constant that is greater than 31.
3581 Result = DAG.getTargetConstant(Value, Op.getValueType());
3583 case 'N': // "N" is a positive constant that is an exact power of two.
3584 if ((int)Value > 0 && isPowerOf2_32(Value))
3585 Result = DAG.getTargetConstant(Value, Op.getValueType());
3587 case 'O': // "O" is the constant zero.
3589 Result = DAG.getTargetConstant(Value, Op.getValueType());
3591 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
3592 if ((short)-Value == (int)-Value)
3593 Result = DAG.getTargetConstant(Value, Op.getValueType());
3601 Ops.push_back(Result);
3605 // Handle standard constraint letters.
3606 TargetLowering::LowerAsmOperandForConstraint(Op, Letter, Ops, DAG);
3609 // isLegalAddressingMode - Return true if the addressing mode represented
3610 // by AM is legal for this target, for a load/store of the specified type.
3611 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
3612 const Type *Ty) const {
3613 // FIXME: PPC does not allow r+i addressing modes for vectors!
3615 // PPC allows a sign-extended 16-bit immediate field.
3616 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
3619 // No global is ever allowed as a base.
3623 // PPC only support r+r,
3625 case 0: // "r+i" or just "i", depending on HasBaseReg.
3628 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
3630 // Otherwise we have r+r or r+i.
3633 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
3635 // Allow 2*r as r+r.
3638 // No other scales are supported.
3645 /// isLegalAddressImmediate - Return true if the integer value can be used
3646 /// as the offset of the target addressing mode for load / store of the
3648 bool PPCTargetLowering::isLegalAddressImmediate(int64_t V,const Type *Ty) const{
3649 // PPC allows a sign-extended 16-bit immediate field.
3650 return (V > -(1 << 16) && V < (1 << 16)-1);
3653 bool PPCTargetLowering::isLegalAddressImmediate(llvm::GlobalValue* GV) const {
3657 SDOperand PPCTargetLowering::LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG) {
3658 // Depths > 0 not supported yet!
3659 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3662 MachineFunction &MF = DAG.getMachineFunction();
3663 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
3664 int RAIdx = FuncInfo->getReturnAddrSaveIndex();
3666 bool isPPC64 = PPCSubTarget.isPPC64();
3668 PPCFrameInfo::getReturnSaveOffset(isPPC64, PPCSubTarget.isMachoABI());
3670 // Set up a frame object for the return address.
3671 RAIdx = MF.getFrameInfo()->CreateFixedObject(isPPC64 ? 8 : 4, Offset);
3673 // Remember it for next time.
3674 FuncInfo->setReturnAddrSaveIndex(RAIdx);
3676 // Make sure the function really does not optimize away the store of the RA
3678 FuncInfo->setLRStoreRequired();
3681 // Just load the return address off the stack.
3682 SDOperand RetAddrFI = DAG.getFrameIndex(RAIdx, getPointerTy());
3683 return DAG.getLoad(getPointerTy(), DAG.getEntryNode(), RetAddrFI, NULL, 0);
3686 SDOperand PPCTargetLowering::LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG) {
3687 // Depths > 0 not supported yet!
3688 if (cast<ConstantSDNode>(Op.getOperand(0))->getValue() > 0)
3691 MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3692 bool isPPC64 = PtrVT == MVT::i64;
3694 MachineFunction &MF = DAG.getMachineFunction();
3695 MachineFrameInfo *MFI = MF.getFrameInfo();
3696 bool is31 = (NoFramePointerElim || MFI->hasVarSizedObjects())
3697 && MFI->getStackSize();
3700 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::X31 : PPC::X1,
3703 return DAG.getCopyFromReg(DAG.getEntryNode(), is31 ? PPC::R31 : PPC::R1,