1 //===-- PPCISelLowering.cpp - PPC DAG Lowering Implementation -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the PPCISelLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "PPCISelLowering.h"
15 #include "MCTargetDesc/PPCPredicates.h"
16 #include "PPCMachineFunctionInfo.h"
17 #include "PPCPerfectShuffle.h"
18 #include "PPCTargetMachine.h"
19 #include "PPCTargetObjectFile.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/StringSwitch.h"
22 #include "llvm/ADT/Triple.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/SelectionDAG.h"
29 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
30 #include "llvm/IR/CallingConv.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DerivedTypes.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/MathExtras.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetOptions.h"
42 static cl::opt<bool> DisablePPCPreinc("disable-ppc-preinc",
43 cl::desc("disable preincrement load/store generation on PPC"), cl::Hidden);
45 static cl::opt<bool> DisableILPPref("disable-ppc-ilp-pref",
46 cl::desc("disable setting the node scheduling preference to ILP on PPC"), cl::Hidden);
48 static cl::opt<bool> DisablePPCUnaligned("disable-ppc-unaligned",
49 cl::desc("disable unaligned load/store generation on PPC"), cl::Hidden);
51 // FIXME: Remove this once the bug has been fixed!
52 extern cl::opt<bool> ANDIGlueBug;
54 static TargetLoweringObjectFile *createTLOF(const Triple &TT) {
55 // If it isn't a Mach-O file then it's going to be a linux ELF
58 return new TargetLoweringObjectFileMachO();
60 return new PPC64LinuxTargetObjectFile();
63 PPCTargetLowering::PPCTargetLowering(PPCTargetMachine &TM)
64 : TargetLowering(TM, createTLOF(Triple(TM.getTargetTriple()))),
65 Subtarget(*TM.getSubtargetImpl()) {
68 // Use _setjmp/_longjmp instead of setjmp/longjmp.
69 setUseUnderscoreSetJmp(true);
70 setUseUnderscoreLongJmp(true);
72 // On PPC32/64, arguments smaller than 4/8 bytes are extended, so all
73 // arguments are at least 4/8 bytes aligned.
74 bool isPPC64 = Subtarget.isPPC64();
75 setMinStackArgumentAlignment(isPPC64 ? 8:4);
77 // Set up the register classes.
78 addRegisterClass(MVT::i32, &PPC::GPRCRegClass);
79 addRegisterClass(MVT::f32, &PPC::F4RCRegClass);
80 addRegisterClass(MVT::f64, &PPC::F8RCRegClass);
82 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
83 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
84 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
86 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
88 // PowerPC has pre-inc load and store's.
89 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal);
90 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal);
91 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal);
92 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal);
93 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal);
94 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal);
95 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal);
96 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal);
97 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal);
98 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal);
100 if (Subtarget.useCRBits()) {
101 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
103 if (isPPC64 || Subtarget.hasFPCVT()) {
104 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Promote);
105 AddPromotedToType (ISD::SINT_TO_FP, MVT::i1,
106 isPPC64 ? MVT::i64 : MVT::i32);
107 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Promote);
108 AddPromotedToType (ISD::UINT_TO_FP, MVT::i1,
109 isPPC64 ? MVT::i64 : MVT::i32);
111 setOperationAction(ISD::SINT_TO_FP, MVT::i1, Custom);
112 setOperationAction(ISD::UINT_TO_FP, MVT::i1, Custom);
115 // PowerPC does not support direct load / store of condition registers
116 setOperationAction(ISD::LOAD, MVT::i1, Custom);
117 setOperationAction(ISD::STORE, MVT::i1, Custom);
119 // FIXME: Remove this once the ANDI glue bug is fixed:
121 setOperationAction(ISD::TRUNCATE, MVT::i1, Custom);
123 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
125 setTruncStoreAction(MVT::i64, MVT::i1, Expand);
126 setTruncStoreAction(MVT::i32, MVT::i1, Expand);
127 setTruncStoreAction(MVT::i16, MVT::i1, Expand);
128 setTruncStoreAction(MVT::i8, MVT::i1, Expand);
130 addRegisterClass(MVT::i1, &PPC::CRBITRCRegClass);
133 // This is used in the ppcf128->int sequence. Note it has different semantics
134 // from FP_ROUND: that rounds to nearest, this rounds to zero.
135 setOperationAction(ISD::FP_ROUND_INREG, MVT::ppcf128, Custom);
137 // We do not currently implement these libm ops for PowerPC.
138 setOperationAction(ISD::FFLOOR, MVT::ppcf128, Expand);
139 setOperationAction(ISD::FCEIL, MVT::ppcf128, Expand);
140 setOperationAction(ISD::FTRUNC, MVT::ppcf128, Expand);
141 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand);
142 setOperationAction(ISD::FNEARBYINT, MVT::ppcf128, Expand);
143 setOperationAction(ISD::FREM, MVT::ppcf128, Expand);
145 // PowerPC has no SREM/UREM instructions
146 setOperationAction(ISD::SREM, MVT::i32, Expand);
147 setOperationAction(ISD::UREM, MVT::i32, Expand);
148 setOperationAction(ISD::SREM, MVT::i64, Expand);
149 setOperationAction(ISD::UREM, MVT::i64, Expand);
151 // Don't use SMUL_LOHI/UMUL_LOHI or SDIVREM/UDIVREM to lower SREM/UREM.
152 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
153 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
154 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
155 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
156 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
157 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
158 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
159 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
161 // We don't support sin/cos/sqrt/fmod/pow
162 setOperationAction(ISD::FSIN , MVT::f64, Expand);
163 setOperationAction(ISD::FCOS , MVT::f64, Expand);
164 setOperationAction(ISD::FSINCOS, MVT::f64, Expand);
165 setOperationAction(ISD::FREM , MVT::f64, Expand);
166 setOperationAction(ISD::FPOW , MVT::f64, Expand);
167 setOperationAction(ISD::FMA , MVT::f64, Legal);
168 setOperationAction(ISD::FSIN , MVT::f32, Expand);
169 setOperationAction(ISD::FCOS , MVT::f32, Expand);
170 setOperationAction(ISD::FSINCOS, MVT::f32, Expand);
171 setOperationAction(ISD::FREM , MVT::f32, Expand);
172 setOperationAction(ISD::FPOW , MVT::f32, Expand);
173 setOperationAction(ISD::FMA , MVT::f32, Legal);
175 setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
177 // If we're enabling GP optimizations, use hardware square root
178 if (!Subtarget.hasFSQRT() &&
179 !(TM.Options.UnsafeFPMath &&
180 Subtarget.hasFRSQRTE() && Subtarget.hasFRE()))
181 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
183 if (!Subtarget.hasFSQRT() &&
184 !(TM.Options.UnsafeFPMath &&
185 Subtarget.hasFRSQRTES() && Subtarget.hasFRES()))
186 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
188 if (Subtarget.hasFCPSGN()) {
189 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Legal);
190 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Legal);
192 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
193 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
196 if (Subtarget.hasFPRND()) {
197 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
198 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
199 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
200 setOperationAction(ISD::FROUND, MVT::f64, Legal);
202 setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
203 setOperationAction(ISD::FCEIL, MVT::f32, Legal);
204 setOperationAction(ISD::FTRUNC, MVT::f32, Legal);
205 setOperationAction(ISD::FROUND, MVT::f32, Legal);
208 // PowerPC does not have BSWAP, CTPOP or CTTZ
209 setOperationAction(ISD::BSWAP, MVT::i32 , Expand);
210 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
211 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
212 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
213 setOperationAction(ISD::BSWAP, MVT::i64 , Expand);
214 setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
215 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
216 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Expand);
218 if (Subtarget.hasPOPCNTD()) {
219 setOperationAction(ISD::CTPOP, MVT::i32 , Legal);
220 setOperationAction(ISD::CTPOP, MVT::i64 , Legal);
222 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
223 setOperationAction(ISD::CTPOP, MVT::i64 , Expand);
226 // PowerPC does not have ROTR
227 setOperationAction(ISD::ROTR, MVT::i32 , Expand);
228 setOperationAction(ISD::ROTR, MVT::i64 , Expand);
230 if (!Subtarget.useCRBits()) {
231 // PowerPC does not have Select
232 setOperationAction(ISD::SELECT, MVT::i32, Expand);
233 setOperationAction(ISD::SELECT, MVT::i64, Expand);
234 setOperationAction(ISD::SELECT, MVT::f32, Expand);
235 setOperationAction(ISD::SELECT, MVT::f64, Expand);
238 // PowerPC wants to turn select_cc of FP into fsel when possible.
239 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
240 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
242 // PowerPC wants to optimize integer setcc a bit
243 if (!Subtarget.useCRBits())
244 setOperationAction(ISD::SETCC, MVT::i32, Custom);
246 // PowerPC does not have BRCOND which requires SetCC
247 if (!Subtarget.useCRBits())
248 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
250 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
252 // PowerPC turns FP_TO_SINT into FCTIWZ and some load/stores.
253 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
255 // PowerPC does not have [U|S]INT_TO_FP
256 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand);
257 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
259 setOperationAction(ISD::BITCAST, MVT::f32, Expand);
260 setOperationAction(ISD::BITCAST, MVT::i32, Expand);
261 setOperationAction(ISD::BITCAST, MVT::i64, Expand);
262 setOperationAction(ISD::BITCAST, MVT::f64, Expand);
264 // We cannot sextinreg(i1). Expand to shifts.
265 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
267 // NOTE: EH_SJLJ_SETJMP/_LONGJMP supported here is NOT intended to support
268 // SjLj exception handling but a light-weight setjmp/longjmp replacement to
269 // support continuation, user-level threading, and etc.. As a result, no
270 // other SjLj exception interfaces are implemented and please don't build
271 // your own exception handling based on them.
272 // LLVM/Clang supports zero-cost DWARF exception handling.
273 setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
274 setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
276 // We want to legalize GlobalAddress and ConstantPool nodes into the
277 // appropriate instructions to materialize the address.
278 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
279 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
280 setOperationAction(ISD::BlockAddress, MVT::i32, Custom);
281 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
282 setOperationAction(ISD::JumpTable, MVT::i32, Custom);
283 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
284 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom);
285 setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
286 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
287 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
290 setOperationAction(ISD::TRAP, MVT::Other, Legal);
292 // TRAMPOLINE is custom lowered.
293 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
294 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
296 // VASTART needs to be custom lowered to use the VarArgsFrameIndex
297 setOperationAction(ISD::VASTART , MVT::Other, Custom);
299 if (Subtarget.isSVR4ABI()) {
301 // VAARG always uses double-word chunks, so promote anything smaller.
302 setOperationAction(ISD::VAARG, MVT::i1, Promote);
303 AddPromotedToType (ISD::VAARG, MVT::i1, MVT::i64);
304 setOperationAction(ISD::VAARG, MVT::i8, Promote);
305 AddPromotedToType (ISD::VAARG, MVT::i8, MVT::i64);
306 setOperationAction(ISD::VAARG, MVT::i16, Promote);
307 AddPromotedToType (ISD::VAARG, MVT::i16, MVT::i64);
308 setOperationAction(ISD::VAARG, MVT::i32, Promote);
309 AddPromotedToType (ISD::VAARG, MVT::i32, MVT::i64);
310 setOperationAction(ISD::VAARG, MVT::Other, Expand);
312 // VAARG is custom lowered with the 32-bit SVR4 ABI.
313 setOperationAction(ISD::VAARG, MVT::Other, Custom);
314 setOperationAction(ISD::VAARG, MVT::i64, Custom);
317 setOperationAction(ISD::VAARG, MVT::Other, Expand);
319 if (Subtarget.isSVR4ABI() && !isPPC64)
320 // VACOPY is custom lowered with the 32-bit SVR4 ABI.
321 setOperationAction(ISD::VACOPY , MVT::Other, Custom);
323 setOperationAction(ISD::VACOPY , MVT::Other, Expand);
325 // Use the default implementation.
326 setOperationAction(ISD::VAEND , MVT::Other, Expand);
327 setOperationAction(ISD::STACKSAVE , MVT::Other, Expand);
328 setOperationAction(ISD::STACKRESTORE , MVT::Other, Custom);
329 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32 , Custom);
330 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64 , Custom);
332 // We want to custom lower some of our intrinsics.
333 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
335 // To handle counter-based loop conditions.
336 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
338 // Comparisons that require checking two conditions.
339 setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
340 setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
341 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
342 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
343 setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
344 setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
345 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
346 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
347 setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
348 setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
349 setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
350 setCondCodeAction(ISD::SETONE, MVT::f64, Expand);
352 if (Subtarget.has64BitSupport()) {
353 // They also have instructions for converting between i64 and fp.
354 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
355 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
356 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
357 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
358 // This is just the low 32 bits of a (signed) fp->i64 conversion.
359 // We cannot do this with Promote because i64 is not a legal type.
360 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
362 if (Subtarget.hasLFIWAX() || Subtarget.isPPC64())
363 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
365 // PowerPC does not have FP_TO_UINT on 32-bit implementations.
366 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
369 // With the instructions enabled under FPCVT, we can do everything.
370 if (Subtarget.hasFPCVT()) {
371 if (Subtarget.has64BitSupport()) {
372 setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
373 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Custom);
374 setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
375 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Custom);
378 setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
379 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Custom);
380 setOperationAction(ISD::SINT_TO_FP, MVT::i32, Custom);
381 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Custom);
384 if (Subtarget.use64BitRegs()) {
385 // 64-bit PowerPC implementations can support i64 types directly
386 addRegisterClass(MVT::i64, &PPC::G8RCRegClass);
387 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
388 setOperationAction(ISD::BUILD_PAIR, MVT::i64, Expand);
389 // 64-bit PowerPC wants to expand i128 shifts itself.
390 setOperationAction(ISD::SHL_PARTS, MVT::i64, Custom);
391 setOperationAction(ISD::SRA_PARTS, MVT::i64, Custom);
392 setOperationAction(ISD::SRL_PARTS, MVT::i64, Custom);
394 // 32-bit PowerPC wants to expand i64 shifts itself.
395 setOperationAction(ISD::SHL_PARTS, MVT::i32, Custom);
396 setOperationAction(ISD::SRA_PARTS, MVT::i32, Custom);
397 setOperationAction(ISD::SRL_PARTS, MVT::i32, Custom);
400 if (Subtarget.hasAltivec()) {
401 // First set operation action for all vector types to expand. Then we
402 // will selectively turn on ones that can be effectively codegen'd.
403 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
404 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
405 MVT::SimpleValueType VT = (MVT::SimpleValueType)i;
407 // add/sub are legal for all supported vector VT's.
408 setOperationAction(ISD::ADD , VT, Legal);
409 setOperationAction(ISD::SUB , VT, Legal);
411 // We promote all shuffles to v16i8.
412 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Promote);
413 AddPromotedToType (ISD::VECTOR_SHUFFLE, VT, MVT::v16i8);
415 // We promote all non-typed operations to v4i32.
416 setOperationAction(ISD::AND , VT, Promote);
417 AddPromotedToType (ISD::AND , VT, MVT::v4i32);
418 setOperationAction(ISD::OR , VT, Promote);
419 AddPromotedToType (ISD::OR , VT, MVT::v4i32);
420 setOperationAction(ISD::XOR , VT, Promote);
421 AddPromotedToType (ISD::XOR , VT, MVT::v4i32);
422 setOperationAction(ISD::LOAD , VT, Promote);
423 AddPromotedToType (ISD::LOAD , VT, MVT::v4i32);
424 setOperationAction(ISD::SELECT, VT, Promote);
425 AddPromotedToType (ISD::SELECT, VT, MVT::v4i32);
426 setOperationAction(ISD::STORE, VT, Promote);
427 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
429 // No other operations are legal.
430 setOperationAction(ISD::MUL , VT, Expand);
431 setOperationAction(ISD::SDIV, VT, Expand);
432 setOperationAction(ISD::SREM, VT, Expand);
433 setOperationAction(ISD::UDIV, VT, Expand);
434 setOperationAction(ISD::UREM, VT, Expand);
435 setOperationAction(ISD::FDIV, VT, Expand);
436 setOperationAction(ISD::FREM, VT, Expand);
437 setOperationAction(ISD::FNEG, VT, Expand);
438 setOperationAction(ISD::FSQRT, VT, Expand);
439 setOperationAction(ISD::FLOG, VT, Expand);
440 setOperationAction(ISD::FLOG10, VT, Expand);
441 setOperationAction(ISD::FLOG2, VT, Expand);
442 setOperationAction(ISD::FEXP, VT, Expand);
443 setOperationAction(ISD::FEXP2, VT, Expand);
444 setOperationAction(ISD::FSIN, VT, Expand);
445 setOperationAction(ISD::FCOS, VT, Expand);
446 setOperationAction(ISD::FABS, VT, Expand);
447 setOperationAction(ISD::FPOWI, VT, Expand);
448 setOperationAction(ISD::FFLOOR, VT, Expand);
449 setOperationAction(ISD::FCEIL, VT, Expand);
450 setOperationAction(ISD::FTRUNC, VT, Expand);
451 setOperationAction(ISD::FRINT, VT, Expand);
452 setOperationAction(ISD::FNEARBYINT, VT, Expand);
453 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Expand);
454 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Expand);
455 setOperationAction(ISD::BUILD_VECTOR, VT, Expand);
456 setOperationAction(ISD::UMUL_LOHI, VT, Expand);
457 setOperationAction(ISD::SMUL_LOHI, VT, Expand);
458 setOperationAction(ISD::UDIVREM, VT, Expand);
459 setOperationAction(ISD::SDIVREM, VT, Expand);
460 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Expand);
461 setOperationAction(ISD::FPOW, VT, Expand);
462 setOperationAction(ISD::BSWAP, VT, Expand);
463 setOperationAction(ISD::CTPOP, VT, Expand);
464 setOperationAction(ISD::CTLZ, VT, Expand);
465 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
466 setOperationAction(ISD::CTTZ, VT, Expand);
467 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
468 setOperationAction(ISD::VSELECT, VT, Expand);
469 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Expand);
471 for (unsigned j = (unsigned)MVT::FIRST_VECTOR_VALUETYPE;
472 j <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++j) {
473 MVT::SimpleValueType InnerVT = (MVT::SimpleValueType)j;
474 setTruncStoreAction(VT, InnerVT, Expand);
476 setLoadExtAction(ISD::SEXTLOAD, VT, Expand);
477 setLoadExtAction(ISD::ZEXTLOAD, VT, Expand);
478 setLoadExtAction(ISD::EXTLOAD, VT, Expand);
481 // We can custom expand all VECTOR_SHUFFLEs to VPERM, others we can handle
482 // with merges, splats, etc.
483 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i8, Custom);
485 setOperationAction(ISD::AND , MVT::v4i32, Legal);
486 setOperationAction(ISD::OR , MVT::v4i32, Legal);
487 setOperationAction(ISD::XOR , MVT::v4i32, Legal);
488 setOperationAction(ISD::LOAD , MVT::v4i32, Legal);
489 setOperationAction(ISD::SELECT, MVT::v4i32,
490 Subtarget.useCRBits() ? Legal : Expand);
491 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
492 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal);
493 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Legal);
494 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal);
495 setOperationAction(ISD::UINT_TO_FP, MVT::v4i32, Legal);
496 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
497 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
498 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
499 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
501 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
502 addRegisterClass(MVT::v4i32, &PPC::VRRCRegClass);
503 addRegisterClass(MVT::v8i16, &PPC::VRRCRegClass);
504 addRegisterClass(MVT::v16i8, &PPC::VRRCRegClass);
506 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
507 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
509 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) {
510 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
511 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
514 setOperationAction(ISD::MUL, MVT::v4i32, Custom);
515 setOperationAction(ISD::MUL, MVT::v8i16, Custom);
516 setOperationAction(ISD::MUL, MVT::v16i8, Custom);
518 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom);
519 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i32, Custom);
521 setOperationAction(ISD::BUILD_VECTOR, MVT::v16i8, Custom);
522 setOperationAction(ISD::BUILD_VECTOR, MVT::v8i16, Custom);
523 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i32, Custom);
524 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom);
526 // Altivec does not contain unordered floating-point compare instructions
527 setCondCodeAction(ISD::SETUO, MVT::v4f32, Expand);
528 setCondCodeAction(ISD::SETUEQ, MVT::v4f32, Expand);
529 setCondCodeAction(ISD::SETUGT, MVT::v4f32, Expand);
530 setCondCodeAction(ISD::SETUGE, MVT::v4f32, Expand);
531 setCondCodeAction(ISD::SETULT, MVT::v4f32, Expand);
532 setCondCodeAction(ISD::SETULE, MVT::v4f32, Expand);
534 setCondCodeAction(ISD::SETO, MVT::v4f32, Expand);
535 setCondCodeAction(ISD::SETONE, MVT::v4f32, Expand);
537 if (Subtarget.hasVSX()) {
538 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
539 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Legal);
541 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
542 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
543 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
544 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
545 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
547 setOperationAction(ISD::FROUND, MVT::v4f32, Legal);
549 setOperationAction(ISD::MUL, MVT::v2f64, Legal);
550 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
552 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
553 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
555 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
556 setOperationAction(ISD::VSELECT, MVT::v8i16, Legal);
557 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
558 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
559 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
561 // Share the Altivec comparison restrictions.
562 setCondCodeAction(ISD::SETUO, MVT::v2f64, Expand);
563 setCondCodeAction(ISD::SETUEQ, MVT::v2f64, Expand);
564 setCondCodeAction(ISD::SETUGT, MVT::v2f64, Expand);
565 setCondCodeAction(ISD::SETUGE, MVT::v2f64, Expand);
566 setCondCodeAction(ISD::SETULT, MVT::v2f64, Expand);
567 setCondCodeAction(ISD::SETULE, MVT::v2f64, Expand);
569 setCondCodeAction(ISD::SETO, MVT::v2f64, Expand);
570 setCondCodeAction(ISD::SETONE, MVT::v2f64, Expand);
572 setOperationAction(ISD::LOAD, MVT::v2f64, Legal);
573 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
575 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Legal);
577 addRegisterClass(MVT::f64, &PPC::VSFRCRegClass);
579 addRegisterClass(MVT::v4f32, &PPC::VSRCRegClass);
580 addRegisterClass(MVT::v2f64, &PPC::VSRCRegClass);
582 // VSX v2i64 only supports non-arithmetic operations.
583 setOperationAction(ISD::ADD, MVT::v2i64, Expand);
584 setOperationAction(ISD::SUB, MVT::v2i64, Expand);
586 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
587 setOperationAction(ISD::SRA, MVT::v2i64, Expand);
588 setOperationAction(ISD::SRL, MVT::v2i64, Expand);
590 setOperationAction(ISD::SETCC, MVT::v2i64, Custom);
592 setOperationAction(ISD::LOAD, MVT::v2i64, Promote);
593 AddPromotedToType (ISD::LOAD, MVT::v2i64, MVT::v2f64);
594 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
595 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
597 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Legal);
599 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
600 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
601 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
602 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
604 // Vector operation legalization checks the result type of
605 // SIGN_EXTEND_INREG, overall legalization checks the inner type.
606 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i64, Legal);
607 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i32, Legal);
608 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
609 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
611 addRegisterClass(MVT::v2i64, &PPC::VSRCRegClass);
615 if (Subtarget.has64BitSupport()) {
616 setOperationAction(ISD::PREFETCH, MVT::Other, Legal);
617 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
620 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand);
621 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand);
622 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Expand);
623 setOperationAction(ISD::ATOMIC_STORE, MVT::i64, Expand);
625 setBooleanContents(ZeroOrOneBooleanContent);
626 // Altivec instructions set fields to all zeros or all ones.
627 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
630 setStackPointerRegisterToSaveRestore(PPC::X1);
631 setExceptionPointerRegister(PPC::X3);
632 setExceptionSelectorRegister(PPC::X4);
634 setStackPointerRegisterToSaveRestore(PPC::R1);
635 setExceptionPointerRegister(PPC::R3);
636 setExceptionSelectorRegister(PPC::R4);
639 // We have target-specific dag combine patterns for the following nodes:
640 setTargetDAGCombine(ISD::SINT_TO_FP);
641 setTargetDAGCombine(ISD::LOAD);
642 setTargetDAGCombine(ISD::STORE);
643 setTargetDAGCombine(ISD::BR_CC);
644 if (Subtarget.useCRBits())
645 setTargetDAGCombine(ISD::BRCOND);
646 setTargetDAGCombine(ISD::BSWAP);
647 setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN);
649 setTargetDAGCombine(ISD::SIGN_EXTEND);
650 setTargetDAGCombine(ISD::ZERO_EXTEND);
651 setTargetDAGCombine(ISD::ANY_EXTEND);
653 if (Subtarget.useCRBits()) {
654 setTargetDAGCombine(ISD::TRUNCATE);
655 setTargetDAGCombine(ISD::SETCC);
656 setTargetDAGCombine(ISD::SELECT_CC);
659 // Use reciprocal estimates.
660 if (TM.Options.UnsafeFPMath) {
661 setTargetDAGCombine(ISD::FDIV);
662 setTargetDAGCombine(ISD::FSQRT);
665 // Darwin long double math library functions have $LDBL128 appended.
666 if (Subtarget.isDarwin()) {
667 setLibcallName(RTLIB::COS_PPCF128, "cosl$LDBL128");
668 setLibcallName(RTLIB::POW_PPCF128, "powl$LDBL128");
669 setLibcallName(RTLIB::REM_PPCF128, "fmodl$LDBL128");
670 setLibcallName(RTLIB::SIN_PPCF128, "sinl$LDBL128");
671 setLibcallName(RTLIB::SQRT_PPCF128, "sqrtl$LDBL128");
672 setLibcallName(RTLIB::LOG_PPCF128, "logl$LDBL128");
673 setLibcallName(RTLIB::LOG2_PPCF128, "log2l$LDBL128");
674 setLibcallName(RTLIB::LOG10_PPCF128, "log10l$LDBL128");
675 setLibcallName(RTLIB::EXP_PPCF128, "expl$LDBL128");
676 setLibcallName(RTLIB::EXP2_PPCF128, "exp2l$LDBL128");
679 // With 32 condition bits, we don't need to sink (and duplicate) compares
680 // aggressively in CodeGenPrep.
681 if (Subtarget.useCRBits())
682 setHasMultipleConditionRegisters();
684 setMinFunctionAlignment(2);
685 if (Subtarget.isDarwin())
686 setPrefFunctionAlignment(4);
688 if (isPPC64 && Subtarget.isJITCodeModel())
689 // Temporary workaround for the inability of PPC64 JIT to handle jump
691 setSupportJumpTables(false);
693 setInsertFencesForAtomic(true);
695 if (Subtarget.enableMachineScheduler())
696 setSchedulingPreference(Sched::Source);
698 setSchedulingPreference(Sched::Hybrid);
700 computeRegisterProperties();
702 // The Freescale cores does better with aggressive inlining of memcpy and
703 // friends. Gcc uses same threshold of 128 bytes (= 32 word stores).
704 if (Subtarget.getDarwinDirective() == PPC::DIR_E500mc ||
705 Subtarget.getDarwinDirective() == PPC::DIR_E5500) {
706 MaxStoresPerMemset = 32;
707 MaxStoresPerMemsetOptSize = 16;
708 MaxStoresPerMemcpy = 32;
709 MaxStoresPerMemcpyOptSize = 8;
710 MaxStoresPerMemmove = 32;
711 MaxStoresPerMemmoveOptSize = 8;
713 setPrefFunctionAlignment(4);
717 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
718 /// the desired ByVal argument alignment.
719 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign,
720 unsigned MaxMaxAlign) {
721 if (MaxAlign == MaxMaxAlign)
723 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) {
724 if (MaxMaxAlign >= 32 && VTy->getBitWidth() >= 256)
726 else if (VTy->getBitWidth() >= 128 && MaxAlign < 16)
728 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) {
729 unsigned EltAlign = 0;
730 getMaxByValAlign(ATy->getElementType(), EltAlign, MaxMaxAlign);
731 if (EltAlign > MaxAlign)
733 } else if (StructType *STy = dyn_cast<StructType>(Ty)) {
734 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) {
735 unsigned EltAlign = 0;
736 getMaxByValAlign(STy->getElementType(i), EltAlign, MaxMaxAlign);
737 if (EltAlign > MaxAlign)
739 if (MaxAlign == MaxMaxAlign)
745 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
746 /// function arguments in the caller parameter area.
747 unsigned PPCTargetLowering::getByValTypeAlignment(Type *Ty) const {
748 // Darwin passes everything on 4 byte boundary.
749 if (Subtarget.isDarwin())
752 // 16byte and wider vectors are passed on 16byte boundary.
753 // The rest is 8 on PPC64 and 4 on PPC32 boundary.
754 unsigned Align = Subtarget.isPPC64() ? 8 : 4;
755 if (Subtarget.hasAltivec() || Subtarget.hasQPX())
756 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16);
760 const char *PPCTargetLowering::getTargetNodeName(unsigned Opcode) const {
762 default: return nullptr;
763 case PPCISD::FSEL: return "PPCISD::FSEL";
764 case PPCISD::FCFID: return "PPCISD::FCFID";
765 case PPCISD::FCTIDZ: return "PPCISD::FCTIDZ";
766 case PPCISD::FCTIWZ: return "PPCISD::FCTIWZ";
767 case PPCISD::FRE: return "PPCISD::FRE";
768 case PPCISD::FRSQRTE: return "PPCISD::FRSQRTE";
769 case PPCISD::STFIWX: return "PPCISD::STFIWX";
770 case PPCISD::VMADDFP: return "PPCISD::VMADDFP";
771 case PPCISD::VNMSUBFP: return "PPCISD::VNMSUBFP";
772 case PPCISD::VPERM: return "PPCISD::VPERM";
773 case PPCISD::Hi: return "PPCISD::Hi";
774 case PPCISD::Lo: return "PPCISD::Lo";
775 case PPCISD::TOC_ENTRY: return "PPCISD::TOC_ENTRY";
776 case PPCISD::LOAD: return "PPCISD::LOAD";
777 case PPCISD::LOAD_TOC: return "PPCISD::LOAD_TOC";
778 case PPCISD::DYNALLOC: return "PPCISD::DYNALLOC";
779 case PPCISD::GlobalBaseReg: return "PPCISD::GlobalBaseReg";
780 case PPCISD::SRL: return "PPCISD::SRL";
781 case PPCISD::SRA: return "PPCISD::SRA";
782 case PPCISD::SHL: return "PPCISD::SHL";
783 case PPCISD::CALL: return "PPCISD::CALL";
784 case PPCISD::CALL_NOP: return "PPCISD::CALL_NOP";
785 case PPCISD::MTCTR: return "PPCISD::MTCTR";
786 case PPCISD::BCTRL: return "PPCISD::BCTRL";
787 case PPCISD::RET_FLAG: return "PPCISD::RET_FLAG";
788 case PPCISD::EH_SJLJ_SETJMP: return "PPCISD::EH_SJLJ_SETJMP";
789 case PPCISD::EH_SJLJ_LONGJMP: return "PPCISD::EH_SJLJ_LONGJMP";
790 case PPCISD::MFOCRF: return "PPCISD::MFOCRF";
791 case PPCISD::VCMP: return "PPCISD::VCMP";
792 case PPCISD::VCMPo: return "PPCISD::VCMPo";
793 case PPCISD::LBRX: return "PPCISD::LBRX";
794 case PPCISD::STBRX: return "PPCISD::STBRX";
795 case PPCISD::LARX: return "PPCISD::LARX";
796 case PPCISD::STCX: return "PPCISD::STCX";
797 case PPCISD::COND_BRANCH: return "PPCISD::COND_BRANCH";
798 case PPCISD::BDNZ: return "PPCISD::BDNZ";
799 case PPCISD::BDZ: return "PPCISD::BDZ";
800 case PPCISD::MFFS: return "PPCISD::MFFS";
801 case PPCISD::FADDRTZ: return "PPCISD::FADDRTZ";
802 case PPCISD::TC_RETURN: return "PPCISD::TC_RETURN";
803 case PPCISD::CR6SET: return "PPCISD::CR6SET";
804 case PPCISD::CR6UNSET: return "PPCISD::CR6UNSET";
805 case PPCISD::ADDIS_TOC_HA: return "PPCISD::ADDIS_TOC_HA";
806 case PPCISD::LD_TOC_L: return "PPCISD::LD_TOC_L";
807 case PPCISD::ADDI_TOC_L: return "PPCISD::ADDI_TOC_L";
808 case PPCISD::PPC32_GOT: return "PPCISD::PPC32_GOT";
809 case PPCISD::ADDIS_GOT_TPREL_HA: return "PPCISD::ADDIS_GOT_TPREL_HA";
810 case PPCISD::LD_GOT_TPREL_L: return "PPCISD::LD_GOT_TPREL_L";
811 case PPCISD::ADD_TLS: return "PPCISD::ADD_TLS";
812 case PPCISD::ADDIS_TLSGD_HA: return "PPCISD::ADDIS_TLSGD_HA";
813 case PPCISD::ADDI_TLSGD_L: return "PPCISD::ADDI_TLSGD_L";
814 case PPCISD::GET_TLS_ADDR: return "PPCISD::GET_TLS_ADDR";
815 case PPCISD::ADDIS_TLSLD_HA: return "PPCISD::ADDIS_TLSLD_HA";
816 case PPCISD::ADDI_TLSLD_L: return "PPCISD::ADDI_TLSLD_L";
817 case PPCISD::GET_TLSLD_ADDR: return "PPCISD::GET_TLSLD_ADDR";
818 case PPCISD::ADDIS_DTPREL_HA: return "PPCISD::ADDIS_DTPREL_HA";
819 case PPCISD::ADDI_DTPREL_L: return "PPCISD::ADDI_DTPREL_L";
820 case PPCISD::VADD_SPLAT: return "PPCISD::VADD_SPLAT";
821 case PPCISD::SC: return "PPCISD::SC";
825 EVT PPCTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
827 return Subtarget.useCRBits() ? MVT::i1 : MVT::i32;
828 return VT.changeVectorElementTypeToInteger();
831 //===----------------------------------------------------------------------===//
832 // Node matching predicates, for use by the tblgen matching code.
833 //===----------------------------------------------------------------------===//
835 /// isFloatingPointZero - Return true if this is 0.0 or -0.0.
836 static bool isFloatingPointZero(SDValue Op) {
837 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
838 return CFP->getValueAPF().isZero();
839 else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
840 // Maybe this has already been legalized into the constant pool?
841 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Op.getOperand(1)))
842 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CP->getConstVal()))
843 return CFP->getValueAPF().isZero();
848 /// isConstantOrUndef - Op is either an undef node or a ConstantSDNode. Return
849 /// true if Op is undef or if it matches the specified value.
850 static bool isConstantOrUndef(int Op, int Val) {
851 return Op < 0 || Op == Val;
854 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
855 /// VPKUHUM instruction.
856 bool PPC::isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
858 unsigned j = DAG.getTarget().getDataLayout()->isLittleEndian() ? 0 : 1;
860 for (unsigned i = 0; i != 16; ++i)
861 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j))
864 for (unsigned i = 0; i != 8; ++i)
865 if (!isConstantOrUndef(N->getMaskElt(i), i*2+j) ||
866 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j))
872 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
873 /// VPKUWUM instruction.
874 bool PPC::isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
877 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
885 for (unsigned i = 0; i != 16; i += 2)
886 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
887 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k))
890 for (unsigned i = 0; i != 8; i += 2)
891 if (!isConstantOrUndef(N->getMaskElt(i ), i*2+j) ||
892 !isConstantOrUndef(N->getMaskElt(i+1), i*2+k) ||
893 !isConstantOrUndef(N->getMaskElt(i+8), i*2+j) ||
894 !isConstantOrUndef(N->getMaskElt(i+9), i*2+k))
900 /// isVMerge - Common function, used to match vmrg* shuffles.
902 static bool isVMerge(ShuffleVectorSDNode *N, unsigned UnitSize,
903 unsigned LHSStart, unsigned RHSStart) {
904 if (N->getValueType(0) != MVT::v16i8)
906 assert((UnitSize == 1 || UnitSize == 2 || UnitSize == 4) &&
907 "Unsupported merge size!");
909 for (unsigned i = 0; i != 8/UnitSize; ++i) // Step over units
910 for (unsigned j = 0; j != UnitSize; ++j) { // Step over bytes within unit
911 if (!isConstantOrUndef(N->getMaskElt(i*UnitSize*2+j),
912 LHSStart+j+i*UnitSize) ||
913 !isConstantOrUndef(N->getMaskElt(i*UnitSize*2+UnitSize+j),
914 RHSStart+j+i*UnitSize))
920 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
921 /// a VMRGL* instruction with the specified unit size (1,2 or 4 bytes).
922 bool PPC::isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
923 bool isUnary, SelectionDAG &DAG) {
924 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
926 return isVMerge(N, UnitSize, 0, 16);
927 return isVMerge(N, UnitSize, 0, 0);
930 return isVMerge(N, UnitSize, 8, 24);
931 return isVMerge(N, UnitSize, 8, 8);
935 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
936 /// a VMRGH* instruction with the specified unit size (1,2 or 4 bytes).
937 bool PPC::isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
938 bool isUnary, SelectionDAG &DAG) {
939 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
941 return isVMerge(N, UnitSize, 8, 24);
942 return isVMerge(N, UnitSize, 8, 8);
945 return isVMerge(N, UnitSize, 0, 16);
946 return isVMerge(N, UnitSize, 0, 0);
951 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
952 /// amount, otherwise return -1.
953 int PPC::isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG) {
954 if (N->getValueType(0) != MVT::v16i8)
957 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
959 // Find the first non-undef value in the shuffle mask.
961 for (i = 0; i != 16 && SVOp->getMaskElt(i) < 0; ++i)
964 if (i == 16) return -1; // all undef.
966 // Otherwise, check to see if the rest of the elements are consecutively
967 // numbered from this value.
968 unsigned ShiftAmt = SVOp->getMaskElt(i);
969 if (ShiftAmt < i) return -1;
971 if (DAG.getTarget().getDataLayout()->isLittleEndian()) {
976 // Check the rest of the elements to see if they are consecutive.
977 for (++i; i != 16; ++i)
978 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt - i))
981 // Check the rest of the elements to see if they are consecutive.
982 for (++i; i != 16; ++i)
983 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt - i) & 15))
987 } else { // Big Endian
992 // Check the rest of the elements to see if they are consecutive.
993 for (++i; i != 16; ++i)
994 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i))
997 // Check the rest of the elements to see if they are consecutive.
998 for (++i; i != 16; ++i)
999 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15))
1006 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
1007 /// specifies a splat of a single element that is suitable for input to
1008 /// VSPLTB/VSPLTH/VSPLTW.
1009 bool PPC::isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize) {
1010 assert(N->getValueType(0) == MVT::v16i8 &&
1011 (EltSize == 1 || EltSize == 2 || EltSize == 4));
1013 // This is a splat operation if each element of the permute is the same, and
1014 // if the value doesn't reference the second vector.
1015 unsigned ElementBase = N->getMaskElt(0);
1017 // FIXME: Handle UNDEF elements too!
1018 if (ElementBase >= 16)
1021 // Check that the indices are consecutive, in the case of a multi-byte element
1022 // splatted with a v16i8 mask.
1023 for (unsigned i = 1; i != EltSize; ++i)
1024 if (N->getMaskElt(i) < 0 || N->getMaskElt(i) != (int)(i+ElementBase))
1027 for (unsigned i = EltSize, e = 16; i != e; i += EltSize) {
1028 if (N->getMaskElt(i) < 0) continue;
1029 for (unsigned j = 0; j != EltSize; ++j)
1030 if (N->getMaskElt(i+j) != N->getMaskElt(j))
1036 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
1038 bool PPC::isAllNegativeZeroVector(SDNode *N) {
1039 BuildVectorSDNode *BV = cast<BuildVectorSDNode>(N);
1041 APInt APVal, APUndef;
1045 if (BV->isConstantSplat(APVal, APUndef, BitSize, HasAnyUndefs, 32, true))
1046 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0)))
1047 return CFP->getValueAPF().isNegZero();
1052 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
1053 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
1054 unsigned PPC::getVSPLTImmediate(SDNode *N, unsigned EltSize,
1055 SelectionDAG &DAG) {
1056 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N);
1057 assert(isSplatShuffleMask(SVOp, EltSize));
1058 if (DAG.getTarget().getDataLayout()->isLittleEndian())
1059 return (16 / EltSize) - 1 - (SVOp->getMaskElt(0) / EltSize);
1061 return SVOp->getMaskElt(0) / EltSize;
1064 /// get_VSPLTI_elt - If this is a build_vector of constants which can be formed
1065 /// by using a vspltis[bhw] instruction of the specified element size, return
1066 /// the constant being splatted. The ByteSize field indicates the number of
1067 /// bytes of each element [124] -> [bhw].
1068 SDValue PPC::get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG) {
1069 SDValue OpVal(nullptr, 0);
1071 // If ByteSize of the splat is bigger than the element size of the
1072 // build_vector, then we have a case where we are checking for a splat where
1073 // multiple elements of the buildvector are folded together into a single
1074 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
1075 unsigned EltSize = 16/N->getNumOperands();
1076 if (EltSize < ByteSize) {
1077 unsigned Multiple = ByteSize/EltSize; // Number of BV entries per spltval.
1078 SDValue UniquedVals[4];
1079 assert(Multiple > 1 && Multiple <= 4 && "How can this happen?");
1081 // See if all of the elements in the buildvector agree across.
1082 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1083 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1084 // If the element isn't a constant, bail fully out.
1085 if (!isa<ConstantSDNode>(N->getOperand(i))) return SDValue();
1088 if (!UniquedVals[i&(Multiple-1)].getNode())
1089 UniquedVals[i&(Multiple-1)] = N->getOperand(i);
1090 else if (UniquedVals[i&(Multiple-1)] != N->getOperand(i))
1091 return SDValue(); // no match.
1094 // Okay, if we reached this point, UniquedVals[0..Multiple-1] contains
1095 // either constant or undef values that are identical for each chunk. See
1096 // if these chunks can form into a larger vspltis*.
1098 // Check to see if all of the leading entries are either 0 or -1. If
1099 // neither, then this won't fit into the immediate field.
1100 bool LeadingZero = true;
1101 bool LeadingOnes = true;
1102 for (unsigned i = 0; i != Multiple-1; ++i) {
1103 if (!UniquedVals[i].getNode()) continue; // Must have been undefs.
1105 LeadingZero &= cast<ConstantSDNode>(UniquedVals[i])->isNullValue();
1106 LeadingOnes &= cast<ConstantSDNode>(UniquedVals[i])->isAllOnesValue();
1108 // Finally, check the least significant entry.
1110 if (!UniquedVals[Multiple-1].getNode())
1111 return DAG.getTargetConstant(0, MVT::i32); // 0,0,0,undef
1112 int Val = cast<ConstantSDNode>(UniquedVals[Multiple-1])->getZExtValue();
1114 return DAG.getTargetConstant(Val, MVT::i32); // 0,0,0,4 -> vspltisw(4)
1117 if (!UniquedVals[Multiple-1].getNode())
1118 return DAG.getTargetConstant(~0U, MVT::i32); // -1,-1,-1,undef
1119 int Val =cast<ConstantSDNode>(UniquedVals[Multiple-1])->getSExtValue();
1120 if (Val >= -16) // -1,-1,-1,-2 -> vspltisw(-2)
1121 return DAG.getTargetConstant(Val, MVT::i32);
1127 // Check to see if this buildvec has a single non-undef value in its elements.
1128 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
1129 if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
1130 if (!OpVal.getNode())
1131 OpVal = N->getOperand(i);
1132 else if (OpVal != N->getOperand(i))
1136 if (!OpVal.getNode()) return SDValue(); // All UNDEF: use implicit def.
1138 unsigned ValSizeInBytes = EltSize;
1140 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
1141 Value = CN->getZExtValue();
1142 } else if (ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(OpVal)) {
1143 assert(CN->getValueType(0) == MVT::f32 && "Only one legal FP vector type!");
1144 Value = FloatToBits(CN->getValueAPF().convertToFloat());
1147 // If the splat value is larger than the element value, then we can never do
1148 // this splat. The only case that we could fit the replicated bits into our
1149 // immediate field for would be zero, and we prefer to use vxor for it.
1150 if (ValSizeInBytes < ByteSize) return SDValue();
1152 // If the element value is larger than the splat value, cut it in half and
1153 // check to see if the two halves are equal. Continue doing this until we
1154 // get to ByteSize. This allows us to handle 0x01010101 as 0x01.
1155 while (ValSizeInBytes > ByteSize) {
1156 ValSizeInBytes >>= 1;
1158 // If the top half equals the bottom half, we're still ok.
1159 if (((Value >> (ValSizeInBytes*8)) & ((1 << (8*ValSizeInBytes))-1)) !=
1160 (Value & ((1 << (8*ValSizeInBytes))-1)))
1164 // Properly sign extend the value.
1165 int MaskVal = SignExtend32(Value, ByteSize * 8);
1167 // If this is zero, don't match, zero matches ISD::isBuildVectorAllZeros.
1168 if (MaskVal == 0) return SDValue();
1170 // Finally, if this value fits in a 5 bit sext field, return it
1171 if (SignExtend32<5>(MaskVal) == MaskVal)
1172 return DAG.getTargetConstant(MaskVal, MVT::i32);
1176 //===----------------------------------------------------------------------===//
1177 // Addressing Mode Selection
1178 //===----------------------------------------------------------------------===//
1180 /// isIntS16Immediate - This method tests to see if the node is either a 32-bit
1181 /// or 64-bit immediate, and if the value can be accurately represented as a
1182 /// sign extension from a 16-bit value. If so, this returns true and the
1184 static bool isIntS16Immediate(SDNode *N, short &Imm) {
1185 if (!isa<ConstantSDNode>(N))
1188 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
1189 if (N->getValueType(0) == MVT::i32)
1190 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
1192 return Imm == (int64_t)cast<ConstantSDNode>(N)->getZExtValue();
1194 static bool isIntS16Immediate(SDValue Op, short &Imm) {
1195 return isIntS16Immediate(Op.getNode(), Imm);
1199 /// SelectAddressRegReg - Given the specified addressed, check to see if it
1200 /// can be represented as an indexed [r+r] operation. Returns false if it
1201 /// can be more efficiently represented with [r+imm].
1202 bool PPCTargetLowering::SelectAddressRegReg(SDValue N, SDValue &Base,
1204 SelectionDAG &DAG) const {
1206 if (N.getOpcode() == ISD::ADD) {
1207 if (isIntS16Immediate(N.getOperand(1), imm))
1208 return false; // r+i
1209 if (N.getOperand(1).getOpcode() == PPCISD::Lo)
1210 return false; // r+i
1212 Base = N.getOperand(0);
1213 Index = N.getOperand(1);
1215 } else if (N.getOpcode() == ISD::OR) {
1216 if (isIntS16Immediate(N.getOperand(1), imm))
1217 return false; // r+i can fold it if we can.
1219 // If this is an or of disjoint bitfields, we can codegen this as an add
1220 // (for better address arithmetic) if the LHS and RHS of the OR are provably
1222 APInt LHSKnownZero, LHSKnownOne;
1223 APInt RHSKnownZero, RHSKnownOne;
1224 DAG.computeKnownBits(N.getOperand(0),
1225 LHSKnownZero, LHSKnownOne);
1227 if (LHSKnownZero.getBoolValue()) {
1228 DAG.computeKnownBits(N.getOperand(1),
1229 RHSKnownZero, RHSKnownOne);
1230 // If all of the bits are known zero on the LHS or RHS, the add won't
1232 if (~(LHSKnownZero | RHSKnownZero) == 0) {
1233 Base = N.getOperand(0);
1234 Index = N.getOperand(1);
1243 // If we happen to be doing an i64 load or store into a stack slot that has
1244 // less than a 4-byte alignment, then the frame-index elimination may need to
1245 // use an indexed load or store instruction (because the offset may not be a
1246 // multiple of 4). The extra register needed to hold the offset comes from the
1247 // register scavenger, and it is possible that the scavenger will need to use
1248 // an emergency spill slot. As a result, we need to make sure that a spill slot
1249 // is allocated when doing an i64 load/store into a less-than-4-byte-aligned
1251 static void fixupFuncForFI(SelectionDAG &DAG, int FrameIdx, EVT VT) {
1252 // FIXME: This does not handle the LWA case.
1256 // NOTE: We'll exclude negative FIs here, which come from argument
1257 // lowering, because there are no known test cases triggering this problem
1258 // using packed structures (or similar). We can remove this exclusion if
1259 // we find such a test case. The reason why this is so test-case driven is
1260 // because this entire 'fixup' is only to prevent crashes (from the
1261 // register scavenger) on not-really-valid inputs. For example, if we have:
1263 // %b = bitcast i1* %a to i64*
1264 // store i64* a, i64 b
1265 // then the store should really be marked as 'align 1', but is not. If it
1266 // were marked as 'align 1' then the indexed form would have been
1267 // instruction-selected initially, and the problem this 'fixup' is preventing
1268 // won't happen regardless.
1272 MachineFunction &MF = DAG.getMachineFunction();
1273 MachineFrameInfo *MFI = MF.getFrameInfo();
1275 unsigned Align = MFI->getObjectAlignment(FrameIdx);
1279 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1280 FuncInfo->setHasNonRISpills();
1283 /// Returns true if the address N can be represented by a base register plus
1284 /// a signed 16-bit displacement [r+imm], and if it is not better
1285 /// represented as reg+reg. If Aligned is true, only accept displacements
1286 /// suitable for STD and friends, i.e. multiples of 4.
1287 bool PPCTargetLowering::SelectAddressRegImm(SDValue N, SDValue &Disp,
1290 bool Aligned) const {
1291 // FIXME dl should come from parent load or store, not from address
1293 // If this can be more profitably realized as r+r, fail.
1294 if (SelectAddressRegReg(N, Disp, Base, DAG))
1297 if (N.getOpcode() == ISD::ADD) {
1299 if (isIntS16Immediate(N.getOperand(1), imm) &&
1300 (!Aligned || (imm & 3) == 0)) {
1301 Disp = DAG.getTargetConstant(imm, N.getValueType());
1302 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N.getOperand(0))) {
1303 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1304 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1306 Base = N.getOperand(0);
1308 return true; // [r+i]
1309 } else if (N.getOperand(1).getOpcode() == PPCISD::Lo) {
1310 // Match LOAD (ADD (X, Lo(G))).
1311 assert(!cast<ConstantSDNode>(N.getOperand(1).getOperand(1))->getZExtValue()
1312 && "Cannot handle constant offsets yet!");
1313 Disp = N.getOperand(1).getOperand(0); // The global address.
1314 assert(Disp.getOpcode() == ISD::TargetGlobalAddress ||
1315 Disp.getOpcode() == ISD::TargetGlobalTLSAddress ||
1316 Disp.getOpcode() == ISD::TargetConstantPool ||
1317 Disp.getOpcode() == ISD::TargetJumpTable);
1318 Base = N.getOperand(0);
1319 return true; // [&g+r]
1321 } else if (N.getOpcode() == ISD::OR) {
1323 if (isIntS16Immediate(N.getOperand(1), imm) &&
1324 (!Aligned || (imm & 3) == 0)) {
1325 // If this is an or of disjoint bitfields, we can codegen this as an add
1326 // (for better address arithmetic) if the LHS and RHS of the OR are
1327 // provably disjoint.
1328 APInt LHSKnownZero, LHSKnownOne;
1329 DAG.computeKnownBits(N.getOperand(0), LHSKnownZero, LHSKnownOne);
1331 if ((LHSKnownZero.getZExtValue()|~(uint64_t)imm) == ~0ULL) {
1332 // If all of the bits are known zero on the LHS or RHS, the add won't
1334 Base = N.getOperand(0);
1335 Disp = DAG.getTargetConstant(imm, N.getValueType());
1339 } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {
1340 // Loading from a constant address.
1342 // If this address fits entirely in a 16-bit sext immediate field, codegen
1345 if (isIntS16Immediate(CN, Imm) && (!Aligned || (Imm & 3) == 0)) {
1346 Disp = DAG.getTargetConstant(Imm, CN->getValueType(0));
1347 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1348 CN->getValueType(0));
1352 // Handle 32-bit sext immediates with LIS + addr mode.
1353 if ((CN->getValueType(0) == MVT::i32 ||
1354 (int64_t)CN->getZExtValue() == (int)CN->getZExtValue()) &&
1355 (!Aligned || (CN->getZExtValue() & 3) == 0)) {
1356 int Addr = (int)CN->getZExtValue();
1358 // Otherwise, break this down into an LIS + disp.
1359 Disp = DAG.getTargetConstant((short)Addr, MVT::i32);
1361 Base = DAG.getTargetConstant((Addr - (signed short)Addr) >> 16, MVT::i32);
1362 unsigned Opc = CN->getValueType(0) == MVT::i32 ? PPC::LIS : PPC::LIS8;
1363 Base = SDValue(DAG.getMachineNode(Opc, dl, CN->getValueType(0), Base), 0);
1368 Disp = DAG.getTargetConstant(0, getPointerTy());
1369 if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
1370 Base = DAG.getTargetFrameIndex(FI->getIndex(), N.getValueType());
1371 fixupFuncForFI(DAG, FI->getIndex(), N.getValueType());
1374 return true; // [r+0]
1377 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
1378 /// represented as an indexed [r+r] operation.
1379 bool PPCTargetLowering::SelectAddressRegRegOnly(SDValue N, SDValue &Base,
1381 SelectionDAG &DAG) const {
1382 // Check to see if we can easily represent this as an [r+r] address. This
1383 // will fail if it thinks that the address is more profitably represented as
1384 // reg+imm, e.g. where imm = 0.
1385 if (SelectAddressRegReg(N, Base, Index, DAG))
1388 // If the operand is an addition, always emit this as [r+r], since this is
1389 // better (for code size, and execution, as the memop does the add for free)
1390 // than emitting an explicit add.
1391 if (N.getOpcode() == ISD::ADD) {
1392 Base = N.getOperand(0);
1393 Index = N.getOperand(1);
1397 // Otherwise, do it the hard way, using R0 as the base register.
1398 Base = DAG.getRegister(Subtarget.isPPC64() ? PPC::ZERO8 : PPC::ZERO,
1404 /// getPreIndexedAddressParts - returns true by value, base pointer and
1405 /// offset pointer and addressing mode by reference if the node's address
1406 /// can be legally represented as pre-indexed load / store address.
1407 bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1409 ISD::MemIndexedMode &AM,
1410 SelectionDAG &DAG) const {
1411 if (DisablePPCPreinc) return false;
1417 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1418 Ptr = LD->getBasePtr();
1419 VT = LD->getMemoryVT();
1420 Alignment = LD->getAlignment();
1421 } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1422 Ptr = ST->getBasePtr();
1423 VT = ST->getMemoryVT();
1424 Alignment = ST->getAlignment();
1429 // PowerPC doesn't have preinc load/store instructions for vectors.
1433 if (SelectAddressRegReg(Ptr, Base, Offset, DAG)) {
1435 // Common code will reject creating a pre-inc form if the base pointer
1436 // is a frame index, or if N is a store and the base pointer is either
1437 // the same as or a predecessor of the value being stored. Check for
1438 // those situations here, and try with swapped Base/Offset instead.
1441 if (isa<FrameIndexSDNode>(Base) || isa<RegisterSDNode>(Base))
1444 SDValue Val = cast<StoreSDNode>(N)->getValue();
1445 if (Val == Base || Base.getNode()->isPredecessorOf(Val.getNode()))
1450 std::swap(Base, Offset);
1456 // LDU/STU can only handle immediates that are a multiple of 4.
1457 if (VT != MVT::i64) {
1458 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, false))
1461 // LDU/STU need an address with at least 4-byte alignment.
1465 if (!SelectAddressRegImm(Ptr, Offset, Base, DAG, true))
1469 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1470 // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of
1471 // sext i32 to i64 when addr mode is r+i.
1472 if (LD->getValueType(0) == MVT::i64 && LD->getMemoryVT() == MVT::i32 &&
1473 LD->getExtensionType() == ISD::SEXTLOAD &&
1474 isa<ConstantSDNode>(Offset))
1482 //===----------------------------------------------------------------------===//
1483 // LowerOperation implementation
1484 //===----------------------------------------------------------------------===//
1486 /// GetLabelAccessInfo - Return true if we should reference labels using a
1487 /// PICBase, set the HiOpFlags and LoOpFlags to the target MO flags.
1488 static bool GetLabelAccessInfo(const TargetMachine &TM, unsigned &HiOpFlags,
1489 unsigned &LoOpFlags,
1490 const GlobalValue *GV = nullptr) {
1491 HiOpFlags = PPCII::MO_HA;
1492 LoOpFlags = PPCII::MO_LO;
1494 // Don't use the pic base if not in PIC relocation model. Or if we are on a
1495 // non-darwin platform. We don't support PIC on other platforms yet.
1496 bool isPIC = TM.getRelocationModel() == Reloc::PIC_ &&
1497 TM.getSubtarget<PPCSubtarget>().isDarwin();
1499 HiOpFlags |= PPCII::MO_PIC_FLAG;
1500 LoOpFlags |= PPCII::MO_PIC_FLAG;
1503 // If this is a reference to a global value that requires a non-lazy-ptr, make
1504 // sure that instruction lowering adds it.
1505 if (GV && TM.getSubtarget<PPCSubtarget>().hasLazyResolverStub(GV, TM)) {
1506 HiOpFlags |= PPCII::MO_NLP_FLAG;
1507 LoOpFlags |= PPCII::MO_NLP_FLAG;
1509 if (GV->hasHiddenVisibility()) {
1510 HiOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1511 LoOpFlags |= PPCII::MO_NLP_HIDDEN_FLAG;
1518 static SDValue LowerLabelRef(SDValue HiPart, SDValue LoPart, bool isPIC,
1519 SelectionDAG &DAG) {
1520 EVT PtrVT = HiPart.getValueType();
1521 SDValue Zero = DAG.getConstant(0, PtrVT);
1524 SDValue Hi = DAG.getNode(PPCISD::Hi, DL, PtrVT, HiPart, Zero);
1525 SDValue Lo = DAG.getNode(PPCISD::Lo, DL, PtrVT, LoPart, Zero);
1527 // With PIC, the first instruction is actually "GR+hi(&G)".
1529 Hi = DAG.getNode(ISD::ADD, DL, PtrVT,
1530 DAG.getNode(PPCISD::GlobalBaseReg, DL, PtrVT), Hi);
1532 // Generate non-pic code that has direct accesses to the constant pool.
1533 // The address of the global is just (hi(&g)+lo(&g)).
1534 return DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo);
1537 SDValue PPCTargetLowering::LowerConstantPool(SDValue Op,
1538 SelectionDAG &DAG) const {
1539 EVT PtrVT = Op.getValueType();
1540 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
1541 const Constant *C = CP->getConstVal();
1543 // 64-bit SVR4 ABI code is always position-independent.
1544 // The actual address of the GlobalValue is stored in the TOC.
1545 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1546 SDValue GA = DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0);
1547 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(CP), MVT::i64, GA,
1548 DAG.getRegister(PPC::X2, MVT::i64));
1551 unsigned MOHiFlag, MOLoFlag;
1552 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1554 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOHiFlag);
1556 DAG.getTargetConstantPool(C, PtrVT, CP->getAlignment(), 0, MOLoFlag);
1557 return LowerLabelRef(CPIHi, CPILo, isPIC, DAG);
1560 SDValue PPCTargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const {
1561 EVT PtrVT = Op.getValueType();
1562 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
1564 // 64-bit SVR4 ABI code is always position-independent.
1565 // The actual address of the GlobalValue is stored in the TOC.
1566 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1567 SDValue GA = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1568 return DAG.getNode(PPCISD::TOC_ENTRY, SDLoc(JT), MVT::i64, GA,
1569 DAG.getRegister(PPC::X2, MVT::i64));
1572 unsigned MOHiFlag, MOLoFlag;
1573 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1574 SDValue JTIHi = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOHiFlag);
1575 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MOLoFlag);
1576 return LowerLabelRef(JTIHi, JTILo, isPIC, DAG);
1579 SDValue PPCTargetLowering::LowerBlockAddress(SDValue Op,
1580 SelectionDAG &DAG) const {
1581 EVT PtrVT = Op.getValueType();
1583 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
1585 unsigned MOHiFlag, MOLoFlag;
1586 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag);
1587 SDValue TgtBAHi = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOHiFlag);
1588 SDValue TgtBALo = DAG.getTargetBlockAddress(BA, PtrVT, 0, MOLoFlag);
1589 return LowerLabelRef(TgtBAHi, TgtBALo, isPIC, DAG);
1592 SDValue PPCTargetLowering::LowerGlobalTLSAddress(SDValue Op,
1593 SelectionDAG &DAG) const {
1595 // FIXME: TLS addresses currently use medium model code sequences,
1596 // which is the most useful form. Eventually support for small and
1597 // large models could be added if users need it, at the cost of
1598 // additional complexity.
1599 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
1601 const GlobalValue *GV = GA->getGlobal();
1602 EVT PtrVT = getPointerTy();
1603 bool is64bit = Subtarget.isPPC64();
1605 TLSModel::Model Model = getTargetMachine().getTLSModel(GV);
1607 if (Model == TLSModel::LocalExec) {
1608 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1609 PPCII::MO_TPREL_HA);
1610 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1611 PPCII::MO_TPREL_LO);
1612 SDValue TLSReg = DAG.getRegister(is64bit ? PPC::X13 : PPC::R2,
1613 is64bit ? MVT::i64 : MVT::i32);
1614 SDValue Hi = DAG.getNode(PPCISD::Hi, dl, PtrVT, TGAHi, TLSReg);
1615 return DAG.getNode(PPCISD::Lo, dl, PtrVT, TGALo, Hi);
1618 if (Model == TLSModel::InitialExec) {
1619 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1620 SDValue TGATLS = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0,
1624 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1625 GOTPtr = DAG.getNode(PPCISD::ADDIS_GOT_TPREL_HA, dl,
1626 PtrVT, GOTReg, TGA);
1628 GOTPtr = DAG.getNode(PPCISD::PPC32_GOT, dl, PtrVT);
1629 SDValue TPOffset = DAG.getNode(PPCISD::LD_GOT_TPREL_L, dl,
1630 PtrVT, TGA, GOTPtr);
1631 return DAG.getNode(PPCISD::ADD_TLS, dl, PtrVT, TPOffset, TGATLS);
1634 if (Model == TLSModel::GeneralDynamic) {
1635 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1636 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1637 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSGD_HA, dl, PtrVT,
1639 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSGD_L, dl, PtrVT,
1642 // We need a chain node, and don't have one handy. The underlying
1643 // call has no side effects, so using the function entry node
1645 SDValue Chain = DAG.getEntryNode();
1646 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1647 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1648 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLS_ADDR, dl,
1649 PtrVT, ParmReg, TGA);
1650 // The return value from GET_TLS_ADDR really is in X3 already, but
1651 // some hacks are needed here to tie everything together. The extra
1652 // copies dissolve during subsequent transforms.
1653 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1654 return DAG.getCopyFromReg(Chain, dl, PPC::X3, PtrVT);
1657 if (Model == TLSModel::LocalDynamic) {
1658 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, PtrVT, 0, 0);
1659 SDValue GOTReg = DAG.getRegister(PPC::X2, MVT::i64);
1660 SDValue GOTEntryHi = DAG.getNode(PPCISD::ADDIS_TLSLD_HA, dl, PtrVT,
1662 SDValue GOTEntry = DAG.getNode(PPCISD::ADDI_TLSLD_L, dl, PtrVT,
1665 // We need a chain node, and don't have one handy. The underlying
1666 // call has no side effects, so using the function entry node
1668 SDValue Chain = DAG.getEntryNode();
1669 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, GOTEntry);
1670 SDValue ParmReg = DAG.getRegister(PPC::X3, MVT::i64);
1671 SDValue TLSAddr = DAG.getNode(PPCISD::GET_TLSLD_ADDR, dl,
1672 PtrVT, ParmReg, TGA);
1673 // The return value from GET_TLSLD_ADDR really is in X3 already, but
1674 // some hacks are needed here to tie everything together. The extra
1675 // copies dissolve during subsequent transforms.
1676 Chain = DAG.getCopyToReg(Chain, dl, PPC::X3, TLSAddr);
1677 SDValue DtvOffsetHi = DAG.getNode(PPCISD::ADDIS_DTPREL_HA, dl, PtrVT,
1678 Chain, ParmReg, TGA);
1679 return DAG.getNode(PPCISD::ADDI_DTPREL_L, dl, PtrVT, DtvOffsetHi, TGA);
1682 llvm_unreachable("Unknown TLS model!");
1685 SDValue PPCTargetLowering::LowerGlobalAddress(SDValue Op,
1686 SelectionDAG &DAG) const {
1687 EVT PtrVT = Op.getValueType();
1688 GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
1690 const GlobalValue *GV = GSDN->getGlobal();
1692 // 64-bit SVR4 ABI code is always position-independent.
1693 // The actual address of the GlobalValue is stored in the TOC.
1694 if (Subtarget.isSVR4ABI() && Subtarget.isPPC64()) {
1695 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset());
1696 return DAG.getNode(PPCISD::TOC_ENTRY, DL, MVT::i64, GA,
1697 DAG.getRegister(PPC::X2, MVT::i64));
1700 unsigned MOHiFlag, MOLoFlag;
1701 bool isPIC = GetLabelAccessInfo(DAG.getTarget(), MOHiFlag, MOLoFlag, GV);
1704 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOHiFlag);
1706 DAG.getTargetGlobalAddress(GV, DL, PtrVT, GSDN->getOffset(), MOLoFlag);
1708 SDValue Ptr = LowerLabelRef(GAHi, GALo, isPIC, DAG);
1710 // If the global reference is actually to a non-lazy-pointer, we have to do an
1711 // extra load to get the address of the global.
1712 if (MOHiFlag & PPCII::MO_NLP_FLAG)
1713 Ptr = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Ptr, MachinePointerInfo(),
1714 false, false, false, 0);
1718 SDValue PPCTargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const {
1719 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1722 if (Op.getValueType() == MVT::v2i64) {
1723 // When the operands themselves are v2i64 values, we need to do something
1724 // special because VSX has no underlying comparison operations for these.
1725 if (Op.getOperand(0).getValueType() == MVT::v2i64) {
1726 // Equality can be handled by casting to the legal type for Altivec
1727 // comparisons, everything else needs to be expanded.
1728 if (CC == ISD::SETEQ || CC == ISD::SETNE) {
1729 return DAG.getNode(ISD::BITCAST, dl, MVT::v2i64,
1730 DAG.getSetCC(dl, MVT::v4i32,
1731 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0)),
1732 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(1)),
1739 // We handle most of these in the usual way.
1743 // If we're comparing for equality to zero, expose the fact that this is
1744 // implented as a ctlz/srl pair on ppc, so that the dag combiner can
1745 // fold the new nodes.
1746 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
1747 if (C->isNullValue() && CC == ISD::SETEQ) {
1748 EVT VT = Op.getOperand(0).getValueType();
1749 SDValue Zext = Op.getOperand(0);
1750 if (VT.bitsLT(MVT::i32)) {
1752 Zext = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, Op.getOperand(0));
1754 unsigned Log2b = Log2_32(VT.getSizeInBits());
1755 SDValue Clz = DAG.getNode(ISD::CTLZ, dl, VT, Zext);
1756 SDValue Scc = DAG.getNode(ISD::SRL, dl, VT, Clz,
1757 DAG.getConstant(Log2b, MVT::i32));
1758 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Scc);
1760 // Leave comparisons against 0 and -1 alone for now, since they're usually
1761 // optimized. FIXME: revisit this when we can custom lower all setcc
1763 if (C->isAllOnesValue() || C->isNullValue())
1767 // If we have an integer seteq/setne, turn it into a compare against zero
1768 // by xor'ing the rhs with the lhs, which is faster than setting a
1769 // condition register, reading it back out, and masking the correct bit. The
1770 // normal approach here uses sub to do this instead of xor. Using xor exposes
1771 // the result to other bit-twiddling opportunities.
1772 EVT LHSVT = Op.getOperand(0).getValueType();
1773 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) {
1774 EVT VT = Op.getValueType();
1775 SDValue Sub = DAG.getNode(ISD::XOR, dl, LHSVT, Op.getOperand(0),
1777 return DAG.getSetCC(dl, VT, Sub, DAG.getConstant(0, LHSVT), CC);
1782 SDValue PPCTargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG,
1783 const PPCSubtarget &Subtarget) const {
1784 SDNode *Node = Op.getNode();
1785 EVT VT = Node->getValueType(0);
1786 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1787 SDValue InChain = Node->getOperand(0);
1788 SDValue VAListPtr = Node->getOperand(1);
1789 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
1792 assert(!Subtarget.isPPC64() && "LowerVAARG is PPC32 only");
1795 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1796 VAListPtr, MachinePointerInfo(SV), MVT::i8,
1798 InChain = GprIndex.getValue(1);
1800 if (VT == MVT::i64) {
1801 // Check if GprIndex is even
1802 SDValue GprAnd = DAG.getNode(ISD::AND, dl, MVT::i32, GprIndex,
1803 DAG.getConstant(1, MVT::i32));
1804 SDValue CC64 = DAG.getSetCC(dl, MVT::i32, GprAnd,
1805 DAG.getConstant(0, MVT::i32), ISD::SETNE);
1806 SDValue GprIndexPlusOne = DAG.getNode(ISD::ADD, dl, MVT::i32, GprIndex,
1807 DAG.getConstant(1, MVT::i32));
1808 // Align GprIndex to be even if it isn't
1809 GprIndex = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC64, GprIndexPlusOne,
1813 // fpr index is 1 byte after gpr
1814 SDValue FprPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1815 DAG.getConstant(1, MVT::i32));
1818 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
1819 FprPtr, MachinePointerInfo(SV), MVT::i8,
1821 InChain = FprIndex.getValue(1);
1823 SDValue RegSaveAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1824 DAG.getConstant(8, MVT::i32));
1826 SDValue OverflowAreaPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAListPtr,
1827 DAG.getConstant(4, MVT::i32));
1830 SDValue OverflowArea = DAG.getLoad(MVT::i32, dl, InChain, OverflowAreaPtr,
1831 MachinePointerInfo(), false, false,
1833 InChain = OverflowArea.getValue(1);
1835 SDValue RegSaveArea = DAG.getLoad(MVT::i32, dl, InChain, RegSaveAreaPtr,
1836 MachinePointerInfo(), false, false,
1838 InChain = RegSaveArea.getValue(1);
1840 // select overflow_area if index > 8
1841 SDValue CC = DAG.getSetCC(dl, MVT::i32, VT.isInteger() ? GprIndex : FprIndex,
1842 DAG.getConstant(8, MVT::i32), ISD::SETLT);
1844 // adjustment constant gpr_index * 4/8
1845 SDValue RegConstant = DAG.getNode(ISD::MUL, dl, MVT::i32,
1846 VT.isInteger() ? GprIndex : FprIndex,
1847 DAG.getConstant(VT.isInteger() ? 4 : 8,
1850 // OurReg = RegSaveArea + RegConstant
1851 SDValue OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, RegSaveArea,
1854 // Floating types are 32 bytes into RegSaveArea
1855 if (VT.isFloatingPoint())
1856 OurReg = DAG.getNode(ISD::ADD, dl, PtrVT, OurReg,
1857 DAG.getConstant(32, MVT::i32));
1859 // increase {f,g}pr_index by 1 (or 2 if VT is i64)
1860 SDValue IndexPlus1 = DAG.getNode(ISD::ADD, dl, MVT::i32,
1861 VT.isInteger() ? GprIndex : FprIndex,
1862 DAG.getConstant(VT == MVT::i64 ? 2 : 1,
1865 InChain = DAG.getTruncStore(InChain, dl, IndexPlus1,
1866 VT.isInteger() ? VAListPtr : FprPtr,
1867 MachinePointerInfo(SV),
1868 MVT::i8, false, false, 0);
1870 // determine if we should load from reg_save_area or overflow_area
1871 SDValue Result = DAG.getNode(ISD::SELECT, dl, PtrVT, CC, OurReg, OverflowArea);
1873 // increase overflow_area by 4/8 if gpr/fpr > 8
1874 SDValue OverflowAreaPlusN = DAG.getNode(ISD::ADD, dl, PtrVT, OverflowArea,
1875 DAG.getConstant(VT.isInteger() ? 4 : 8,
1878 OverflowArea = DAG.getNode(ISD::SELECT, dl, MVT::i32, CC, OverflowArea,
1881 InChain = DAG.getTruncStore(InChain, dl, OverflowArea,
1883 MachinePointerInfo(),
1884 MVT::i32, false, false, 0);
1886 return DAG.getLoad(VT, dl, InChain, Result, MachinePointerInfo(),
1887 false, false, false, 0);
1890 SDValue PPCTargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG,
1891 const PPCSubtarget &Subtarget) const {
1892 assert(!Subtarget.isPPC64() && "LowerVACOPY is PPC32 only");
1894 // We have to copy the entire va_list struct:
1895 // 2*sizeof(char) + 2 Byte alignment + 2*sizeof(char*) = 12 Byte
1896 return DAG.getMemcpy(Op.getOperand(0), Op,
1897 Op.getOperand(1), Op.getOperand(2),
1898 DAG.getConstant(12, MVT::i32), 8, false, true,
1899 MachinePointerInfo(), MachinePointerInfo());
1902 SDValue PPCTargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op,
1903 SelectionDAG &DAG) const {
1904 return Op.getOperand(0);
1907 SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 SDValue Chain = Op.getOperand(0);
1910 SDValue Trmp = Op.getOperand(1); // trampoline
1911 SDValue FPtr = Op.getOperand(2); // nested function
1912 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
1915 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1916 bool isPPC64 = (PtrVT == MVT::i64);
1918 DAG.getTargetLoweringInfo().getDataLayout()->getIntPtrType(
1921 TargetLowering::ArgListTy Args;
1922 TargetLowering::ArgListEntry Entry;
1924 Entry.Ty = IntPtrTy;
1925 Entry.Node = Trmp; Args.push_back(Entry);
1927 // TrampSize == (isPPC64 ? 48 : 40);
1928 Entry.Node = DAG.getConstant(isPPC64 ? 48 : 40,
1929 isPPC64 ? MVT::i64 : MVT::i32);
1930 Args.push_back(Entry);
1932 Entry.Node = FPtr; Args.push_back(Entry);
1933 Entry.Node = Nest; Args.push_back(Entry);
1935 // Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
1936 TargetLowering::CallLoweringInfo CLI(DAG);
1937 CLI.setDebugLoc(dl).setChain(Chain)
1938 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
1939 DAG.getExternalSymbol("__trampoline_setup", PtrVT), &Args, 0);
1941 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
1942 return CallResult.second;
1945 SDValue PPCTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG,
1946 const PPCSubtarget &Subtarget) const {
1947 MachineFunction &MF = DAG.getMachineFunction();
1948 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
1952 if (Subtarget.isDarwinABI() || Subtarget.isPPC64()) {
1953 // vastart just stores the address of the VarArgsFrameIndex slot into the
1954 // memory location argument.
1955 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1956 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
1957 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1958 return DAG.getStore(Op.getOperand(0), dl, FR, Op.getOperand(1),
1959 MachinePointerInfo(SV),
1963 // For the 32-bit SVR4 ABI we follow the layout of the va_list struct.
1964 // We suppose the given va_list is already allocated.
1967 // char gpr; /* index into the array of 8 GPRs
1968 // * stored in the register save area
1969 // * gpr=0 corresponds to r3,
1970 // * gpr=1 to r4, etc.
1972 // char fpr; /* index into the array of 8 FPRs
1973 // * stored in the register save area
1974 // * fpr=0 corresponds to f1,
1975 // * fpr=1 to f2, etc.
1977 // char *overflow_arg_area;
1978 // /* location on stack that holds
1979 // * the next overflow argument
1981 // char *reg_save_area;
1982 // /* where r3:r10 and f1:f8 (if saved)
1988 SDValue ArgGPR = DAG.getConstant(FuncInfo->getVarArgsNumGPR(), MVT::i32);
1989 SDValue ArgFPR = DAG.getConstant(FuncInfo->getVarArgsNumFPR(), MVT::i32);
1992 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
1994 SDValue StackOffsetFI = DAG.getFrameIndex(FuncInfo->getVarArgsStackOffset(),
1996 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
1999 uint64_t FrameOffset = PtrVT.getSizeInBits()/8;
2000 SDValue ConstFrameOffset = DAG.getConstant(FrameOffset, PtrVT);
2002 uint64_t StackOffset = PtrVT.getSizeInBits()/8 - 1;
2003 SDValue ConstStackOffset = DAG.getConstant(StackOffset, PtrVT);
2005 uint64_t FPROffset = 1;
2006 SDValue ConstFPROffset = DAG.getConstant(FPROffset, PtrVT);
2008 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2010 // Store first byte : number of int regs
2011 SDValue firstStore = DAG.getTruncStore(Op.getOperand(0), dl, ArgGPR,
2013 MachinePointerInfo(SV),
2014 MVT::i8, false, false, 0);
2015 uint64_t nextOffset = FPROffset;
2016 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, Op.getOperand(1),
2019 // Store second byte : number of float regs
2020 SDValue secondStore =
2021 DAG.getTruncStore(firstStore, dl, ArgFPR, nextPtr,
2022 MachinePointerInfo(SV, nextOffset), MVT::i8,
2024 nextOffset += StackOffset;
2025 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstStackOffset);
2027 // Store second word : arguments given on stack
2028 SDValue thirdStore =
2029 DAG.getStore(secondStore, dl, StackOffsetFI, nextPtr,
2030 MachinePointerInfo(SV, nextOffset),
2032 nextOffset += FrameOffset;
2033 nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, nextPtr, ConstFrameOffset);
2035 // Store third word : arguments given in registers
2036 return DAG.getStore(thirdStore, dl, FR, nextPtr,
2037 MachinePointerInfo(SV, nextOffset),
2042 #include "PPCGenCallingConv.inc"
2044 // Function whose sole purpose is to kill compiler warnings
2045 // stemming from unused functions included from PPCGenCallingConv.inc.
2046 CCAssignFn *PPCTargetLowering::useFastISelCCs(unsigned Flag) const {
2047 return Flag ? CC_PPC64_ELF_FIS : RetCC_PPC64_ELF_FIS;
2050 bool llvm::CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
2051 CCValAssign::LocInfo &LocInfo,
2052 ISD::ArgFlagsTy &ArgFlags,
2057 bool llvm::CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
2059 CCValAssign::LocInfo &LocInfo,
2060 ISD::ArgFlagsTy &ArgFlags,
2062 static const MCPhysReg ArgRegs[] = {
2063 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2064 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2066 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2068 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2070 // Skip one register if the first unallocated register has an even register
2071 // number and there are still argument registers available which have not been
2072 // allocated yet. RegNum is actually an index into ArgRegs, which means we
2073 // need to skip a register if RegNum is odd.
2074 if (RegNum != NumArgRegs && RegNum % 2 == 1) {
2075 State.AllocateReg(ArgRegs[RegNum]);
2078 // Always return false here, as this function only makes sure that the first
2079 // unallocated register has an odd register number and does not actually
2080 // allocate a register for the current argument.
2084 bool llvm::CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
2086 CCValAssign::LocInfo &LocInfo,
2087 ISD::ArgFlagsTy &ArgFlags,
2089 static const MCPhysReg ArgRegs[] = {
2090 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2094 const unsigned NumArgRegs = array_lengthof(ArgRegs);
2096 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs);
2098 // If there is only one Floating-point register left we need to put both f64
2099 // values of a split ppc_fp128 value on the stack.
2100 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) {
2101 State.AllocateReg(ArgRegs[RegNum]);
2104 // Always return false here, as this function only makes sure that the two f64
2105 // values a ppc_fp128 value is split into are both passed in registers or both
2106 // passed on the stack and does not actually allocate a register for the
2107 // current argument.
2111 /// GetFPR - Get the set of FP registers that should be allocated for arguments,
2113 static const MCPhysReg *GetFPR() {
2114 static const MCPhysReg FPR[] = {
2115 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2116 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
2122 /// CalculateStackSlotSize - Calculates the size reserved for this argument on
2124 static unsigned CalculateStackSlotSize(EVT ArgVT, ISD::ArgFlagsTy Flags,
2125 unsigned PtrByteSize) {
2126 unsigned ArgSize = ArgVT.getStoreSize();
2127 if (Flags.isByVal())
2128 ArgSize = Flags.getByValSize();
2129 ArgSize = ((ArgSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2135 PPCTargetLowering::LowerFormalArguments(SDValue Chain,
2136 CallingConv::ID CallConv, bool isVarArg,
2137 const SmallVectorImpl<ISD::InputArg>
2139 SDLoc dl, SelectionDAG &DAG,
2140 SmallVectorImpl<SDValue> &InVals)
2142 if (Subtarget.isSVR4ABI()) {
2143 if (Subtarget.isPPC64())
2144 return LowerFormalArguments_64SVR4(Chain, CallConv, isVarArg, Ins,
2147 return LowerFormalArguments_32SVR4(Chain, CallConv, isVarArg, Ins,
2150 return LowerFormalArguments_Darwin(Chain, CallConv, isVarArg, Ins,
2156 PPCTargetLowering::LowerFormalArguments_32SVR4(
2158 CallingConv::ID CallConv, bool isVarArg,
2159 const SmallVectorImpl<ISD::InputArg>
2161 SDLoc dl, SelectionDAG &DAG,
2162 SmallVectorImpl<SDValue> &InVals) const {
2164 // 32-bit SVR4 ABI Stack Frame Layout:
2165 // +-----------------------------------+
2166 // +--> | Back chain |
2167 // | +-----------------------------------+
2168 // | | Floating-point register save area |
2169 // | +-----------------------------------+
2170 // | | General register save area |
2171 // | +-----------------------------------+
2172 // | | CR save word |
2173 // | +-----------------------------------+
2174 // | | VRSAVE save word |
2175 // | +-----------------------------------+
2176 // | | Alignment padding |
2177 // | +-----------------------------------+
2178 // | | Vector register save area |
2179 // | +-----------------------------------+
2180 // | | Local variable space |
2181 // | +-----------------------------------+
2182 // | | Parameter list area |
2183 // | +-----------------------------------+
2184 // | | LR save word |
2185 // | +-----------------------------------+
2186 // SP--> +--- | Back chain |
2187 // +-----------------------------------+
2190 // System V Application Binary Interface PowerPC Processor Supplement
2191 // AltiVec Technology Programming Interface Manual
2193 MachineFunction &MF = DAG.getMachineFunction();
2194 MachineFrameInfo *MFI = MF.getFrameInfo();
2195 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2197 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2198 // Potential tail calls could cause overwriting of argument stack slots.
2199 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2200 (CallConv == CallingConv::Fast));
2201 unsigned PtrByteSize = 4;
2203 // Assign locations to all of the incoming arguments.
2204 SmallVector<CCValAssign, 16> ArgLocs;
2205 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2206 getTargetMachine(), ArgLocs, *DAG.getContext());
2208 // Reserve space for the linkage area on the stack.
2209 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
2211 CCInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4);
2213 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
2214 CCValAssign &VA = ArgLocs[i];
2216 // Arguments stored in registers.
2217 if (VA.isRegLoc()) {
2218 const TargetRegisterClass *RC;
2219 EVT ValVT = VA.getValVT();
2221 switch (ValVT.getSimpleVT().SimpleTy) {
2223 llvm_unreachable("ValVT not supported by formal arguments Lowering");
2226 RC = &PPC::GPRCRegClass;
2229 RC = &PPC::F4RCRegClass;
2232 if (Subtarget.hasVSX())
2233 RC = &PPC::VSFRCRegClass;
2235 RC = &PPC::F8RCRegClass;
2241 RC = &PPC::VRRCRegClass;
2245 RC = &PPC::VSHRCRegClass;
2249 // Transform the arguments stored in physical registers into virtual ones.
2250 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
2251 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg,
2252 ValVT == MVT::i1 ? MVT::i32 : ValVT);
2254 if (ValVT == MVT::i1)
2255 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgValue);
2257 InVals.push_back(ArgValue);
2259 // Argument stored in memory.
2260 assert(VA.isMemLoc());
2262 unsigned ArgSize = VA.getLocVT().getStoreSize();
2263 int FI = MFI->CreateFixedObject(ArgSize, VA.getLocMemOffset(),
2266 // Create load nodes to retrieve arguments from the stack.
2267 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2268 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
2269 MachinePointerInfo(),
2270 false, false, false, 0));
2274 // Assign locations to all of the incoming aggregate by value arguments.
2275 // Aggregates passed by value are stored in the local variable space of the
2276 // caller's stack frame, right above the parameter list area.
2277 SmallVector<CCValAssign, 16> ByValArgLocs;
2278 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
2279 getTargetMachine(), ByValArgLocs, *DAG.getContext());
2281 // Reserve stack space for the allocations in CCInfo.
2282 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
2284 CCByValInfo.AnalyzeFormalArguments(Ins, CC_PPC32_SVR4_ByVal);
2286 // Area that is at least reserved in the caller of this function.
2287 unsigned MinReservedArea = CCByValInfo.getNextStackOffset();
2289 // Set the size that is at least reserved in caller of this function. Tail
2290 // call optimized function's reserved stack space needs to be aligned so that
2291 // taking the difference between two stack areas will result in an aligned
2293 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2296 std::max(MinReservedArea,
2297 PPCFrameLowering::getMinCallFrameSize(false, false));
2299 unsigned TargetAlign = DAG.getMachineFunction().getTarget().getFrameLowering()->
2300 getStackAlignment();
2301 unsigned AlignMask = TargetAlign-1;
2302 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2304 FI->setMinReservedArea(MinReservedArea);
2306 SmallVector<SDValue, 8> MemOps;
2308 // If the function takes variable number of arguments, make a frame index for
2309 // the start of the first vararg value... for expansion of llvm.va_start.
2311 static const MCPhysReg GPArgRegs[] = {
2312 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2313 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2315 const unsigned NumGPArgRegs = array_lengthof(GPArgRegs);
2317 static const MCPhysReg FPArgRegs[] = {
2318 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
2321 const unsigned NumFPArgRegs = array_lengthof(FPArgRegs);
2323 FuncInfo->setVarArgsNumGPR(CCInfo.getFirstUnallocated(GPArgRegs,
2325 FuncInfo->setVarArgsNumFPR(CCInfo.getFirstUnallocated(FPArgRegs,
2328 // Make room for NumGPArgRegs and NumFPArgRegs.
2329 int Depth = NumGPArgRegs * PtrVT.getSizeInBits()/8 +
2330 NumFPArgRegs * EVT(MVT::f64).getSizeInBits()/8;
2332 FuncInfo->setVarArgsStackOffset(
2333 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
2334 CCInfo.getNextStackOffset(), true));
2336 FuncInfo->setVarArgsFrameIndex(MFI->CreateStackObject(Depth, 8, false));
2337 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2339 // The fixed integer arguments of a variadic function are stored to the
2340 // VarArgsFrameIndex on the stack so that they may be loaded by deferencing
2341 // the result of va_next.
2342 for (unsigned GPRIndex = 0; GPRIndex != NumGPArgRegs; ++GPRIndex) {
2343 // Get an existing live-in vreg, or add a new one.
2344 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
2346 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2348 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2349 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2350 MachinePointerInfo(), false, false, 0);
2351 MemOps.push_back(Store);
2352 // Increment the address by four for the next argument to store
2353 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
2354 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2357 // FIXME 32-bit SVR4: We only need to save FP argument registers if CR bit 6
2359 // The double arguments are stored to the VarArgsFrameIndex
2361 for (unsigned FPRIndex = 0; FPRIndex != NumFPArgRegs; ++FPRIndex) {
2362 // Get an existing live-in vreg, or add a new one.
2363 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
2365 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2367 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2368 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2369 MachinePointerInfo(), false, false, 0);
2370 MemOps.push_back(Store);
2371 // Increment the address by eight for the next argument to store
2372 SDValue PtrOff = DAG.getConstant(EVT(MVT::f64).getSizeInBits()/8,
2374 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2378 if (!MemOps.empty())
2379 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2384 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2385 // value to MVT::i64 and then truncate to the correct register size.
2387 PPCTargetLowering::extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT,
2388 SelectionDAG &DAG, SDValue ArgVal,
2391 ArgVal = DAG.getNode(ISD::AssertSext, dl, MVT::i64, ArgVal,
2392 DAG.getValueType(ObjectVT));
2393 else if (Flags.isZExt())
2394 ArgVal = DAG.getNode(ISD::AssertZext, dl, MVT::i64, ArgVal,
2395 DAG.getValueType(ObjectVT));
2397 return DAG.getNode(ISD::TRUNCATE, dl, ObjectVT, ArgVal);
2400 // Set the size that is at least reserved in caller of this function. Tail
2401 // call optimized functions' reserved stack space needs to be aligned so that
2402 // taking the difference between two stack areas will result in an aligned
2405 PPCTargetLowering::setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
2406 unsigned nAltivecParamsAtEnd,
2407 unsigned MinReservedArea,
2408 bool isPPC64) const {
2409 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
2410 // Add the Altivec parameters at the end, if needed.
2411 if (nAltivecParamsAtEnd) {
2412 MinReservedArea = ((MinReservedArea+15)/16)*16;
2413 MinReservedArea += 16*nAltivecParamsAtEnd;
2416 std::max(MinReservedArea,
2417 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
2418 unsigned TargetAlign
2419 = DAG.getMachineFunction().getTarget().getFrameLowering()->
2420 getStackAlignment();
2421 unsigned AlignMask = TargetAlign-1;
2422 MinReservedArea = (MinReservedArea + AlignMask) & ~AlignMask;
2423 FI->setMinReservedArea(MinReservedArea);
2427 PPCTargetLowering::LowerFormalArguments_64SVR4(
2429 CallingConv::ID CallConv, bool isVarArg,
2430 const SmallVectorImpl<ISD::InputArg>
2432 SDLoc dl, SelectionDAG &DAG,
2433 SmallVectorImpl<SDValue> &InVals) const {
2434 // TODO: add description of PPC stack frame format, or at least some docs.
2436 bool isLittleEndian = Subtarget.isLittleEndian();
2437 MachineFunction &MF = DAG.getMachineFunction();
2438 MachineFrameInfo *MFI = MF.getFrameInfo();
2439 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2441 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2442 // Potential tail calls could cause overwriting of argument stack slots.
2443 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2444 (CallConv == CallingConv::Fast));
2445 unsigned PtrByteSize = 8;
2447 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
2448 // Area that is at least reserved in caller of this function.
2449 unsigned MinReservedArea = ArgOffset;
2451 static const MCPhysReg GPR[] = {
2452 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2453 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2456 static const MCPhysReg *FPR = GetFPR();
2458 static const MCPhysReg VR[] = {
2459 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2460 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2462 static const MCPhysReg VSRH[] = {
2463 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
2464 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
2467 const unsigned Num_GPR_Regs = array_lengthof(GPR);
2468 const unsigned Num_FPR_Regs = 13;
2469 const unsigned Num_VR_Regs = array_lengthof(VR);
2471 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2473 // Add DAG nodes to load the arguments or copy them out of registers. On
2474 // entry to a function on PPC, the arguments start after the linkage area,
2475 // although the first ones are often in registers.
2477 SmallVector<SDValue, 8> MemOps;
2478 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2479 unsigned CurArgIdx = 0;
2480 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2482 bool needsLoad = false;
2483 EVT ObjectVT = Ins[ArgNo].VT;
2484 unsigned ObjSize = ObjectVT.getStoreSize();
2485 unsigned ArgSize = ObjSize;
2486 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2487 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2488 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2490 unsigned CurArgOffset = ArgOffset;
2492 // Altivec parameters are padded to a 16 byte boundary.
2493 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2494 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8 ||
2495 ObjectVT==MVT::v2f64 || ObjectVT==MVT::v2i64)
2496 MinReservedArea = ((MinReservedArea+15)/16)*16;
2498 // Calculate min reserved area.
2499 MinReservedArea += CalculateStackSlotSize(ObjectVT, Flags, PtrByteSize);
2501 // FIXME the codegen can be much improved in some cases.
2502 // We do not have to keep everything in memory.
2503 if (Flags.isByVal()) {
2504 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2505 ObjSize = Flags.getByValSize();
2506 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2507 // Empty aggregate parameters do not take up registers. Examples:
2511 // etc. However, we have to provide a place-holder in InVals, so
2512 // pretend we have an 8-byte item at the current address for that
2515 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2516 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2517 InVals.push_back(FIN);
2521 unsigned BVAlign = Flags.getByValAlign();
2523 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
2524 CurArgOffset = ArgOffset;
2527 // All aggregates smaller than 8 bytes must be passed right-justified.
2528 if (ObjSize < PtrByteSize && !isLittleEndian)
2529 CurArgOffset = CurArgOffset + (PtrByteSize - ObjSize);
2530 // The value of the object is its address.
2531 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2532 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2533 InVals.push_back(FIN);
2536 if (GPR_idx != Num_GPR_Regs) {
2537 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2538 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2541 if (ObjSize==1 || ObjSize==2 || ObjSize==4) {
2542 EVT ObjType = (ObjSize == 1 ? MVT::i8 :
2543 (ObjSize == 2 ? MVT::i16 : MVT::i32));
2544 Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2545 MachinePointerInfo(FuncArg),
2546 ObjType, false, false, 0);
2548 // For sizes that don't fit a truncating store (3, 5, 6, 7),
2549 // store the whole register as-is to the parameter save area
2550 // slot. The address of the parameter was already calculated
2551 // above (InVals.push_back(FIN)) to be the right-justified
2552 // offset within the slot. For this store, we need a new
2553 // frame index that points at the beginning of the slot.
2554 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2555 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2556 Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2557 MachinePointerInfo(FuncArg),
2561 MemOps.push_back(Store);
2564 // Whether we copied from a register or not, advance the offset
2565 // into the parameter save area by a full doubleword.
2566 ArgOffset += PtrByteSize;
2570 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2571 // Store whatever pieces of the object are in registers
2572 // to memory. ArgOffset will be the address of the beginning
2574 if (GPR_idx != Num_GPR_Regs) {
2576 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2577 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2578 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2579 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2580 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2581 MachinePointerInfo(FuncArg, j),
2583 MemOps.push_back(Store);
2585 ArgOffset += PtrByteSize;
2587 ArgOffset += ArgSize - j;
2594 switch (ObjectVT.getSimpleVT().SimpleTy) {
2595 default: llvm_unreachable("Unhandled argument type!");
2599 if (GPR_idx != Num_GPR_Regs) {
2600 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2601 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2603 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2604 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2605 // value to MVT::i64 and then truncate to the correct register size.
2606 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2611 ArgSize = PtrByteSize;
2618 // Every 8 bytes of argument space consumes one of the GPRs available for
2619 // argument passing.
2620 if (GPR_idx != Num_GPR_Regs) {
2623 if (FPR_idx != Num_FPR_Regs) {
2626 if (ObjectVT == MVT::f32)
2627 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2629 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() ?
2630 &PPC::VSFRCRegClass :
2631 &PPC::F8RCRegClass);
2633 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2637 ArgSize = PtrByteSize;
2648 // Vectors are aligned to a 16-byte boundary in the argument save area.
2649 while ((ArgOffset % 16) != 0) {
2650 ArgOffset += PtrByteSize;
2651 if (GPR_idx != Num_GPR_Regs)
2654 if (VR_idx != Num_VR_Regs) {
2655 unsigned VReg = (ObjectVT == MVT::v2f64 || ObjectVT == MVT::v2i64) ?
2656 MF.addLiveIn(VSRH[VR_idx], &PPC::VSHRCRegClass) :
2657 MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2658 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2661 CurArgOffset = ArgOffset;
2665 GPR_idx = std::min(GPR_idx + 2, Num_GPR_Regs);
2669 // We need to load the argument to a virtual register if we determined
2670 // above that we ran out of physical registers of the appropriate type.
2672 if (ObjSize < ArgSize && !isLittleEndian)
2673 CurArgOffset += ArgSize - ObjSize;
2674 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, isImmutable);
2675 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2676 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
2677 false, false, false, 0);
2680 InVals.push_back(ArgVal);
2683 // Set the size that is at least reserved in caller of this function. Tail
2684 // call optimized functions' reserved stack space needs to be aligned so that
2685 // taking the difference between two stack areas will result in an aligned
2687 setMinReservedArea(MF, DAG, 0, MinReservedArea, true);
2689 // If the function takes variable number of arguments, make a frame index for
2690 // the start of the first vararg value... for expansion of llvm.va_start.
2692 int Depth = ArgOffset;
2694 FuncInfo->setVarArgsFrameIndex(
2695 MFI->CreateFixedObject(PtrByteSize, Depth, true));
2696 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
2698 // If this function is vararg, store any remaining integer argument regs
2699 // to their spots on the stack so that they may be loaded by deferencing the
2700 // result of va_next.
2701 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
2702 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2703 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2704 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2705 MachinePointerInfo(), false, false, 0);
2706 MemOps.push_back(Store);
2707 // Increment the address by four for the next argument to store
2708 SDValue PtrOff = DAG.getConstant(PtrByteSize, PtrVT);
2709 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
2713 if (!MemOps.empty())
2714 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
2720 PPCTargetLowering::LowerFormalArguments_Darwin(
2722 CallingConv::ID CallConv, bool isVarArg,
2723 const SmallVectorImpl<ISD::InputArg>
2725 SDLoc dl, SelectionDAG &DAG,
2726 SmallVectorImpl<SDValue> &InVals) const {
2727 // TODO: add description of PPC stack frame format, or at least some docs.
2729 MachineFunction &MF = DAG.getMachineFunction();
2730 MachineFrameInfo *MFI = MF.getFrameInfo();
2731 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
2733 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
2734 bool isPPC64 = PtrVT == MVT::i64;
2735 // Potential tail calls could cause overwriting of argument stack slots.
2736 bool isImmutable = !(getTargetMachine().Options.GuaranteedTailCallOpt &&
2737 (CallConv == CallingConv::Fast));
2738 unsigned PtrByteSize = isPPC64 ? 8 : 4;
2740 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
2741 // Area that is at least reserved in caller of this function.
2742 unsigned MinReservedArea = ArgOffset;
2744 static const MCPhysReg GPR_32[] = { // 32-bit registers.
2745 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
2746 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
2748 static const MCPhysReg GPR_64[] = { // 64-bit registers.
2749 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
2750 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
2753 static const MCPhysReg *FPR = GetFPR();
2755 static const MCPhysReg VR[] = {
2756 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
2757 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
2760 const unsigned Num_GPR_Regs = array_lengthof(GPR_32);
2761 const unsigned Num_FPR_Regs = 13;
2762 const unsigned Num_VR_Regs = array_lengthof( VR);
2764 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
2766 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
2768 // In 32-bit non-varargs functions, the stack space for vectors is after the
2769 // stack space for non-vectors. We do not use this space unless we have
2770 // too many vectors to fit in registers, something that only occurs in
2771 // constructed examples:), but we have to walk the arglist to figure
2772 // that out...for the pathological case, compute VecArgOffset as the
2773 // start of the vector parameter area. Computing VecArgOffset is the
2774 // entire point of the following loop.
2775 unsigned VecArgOffset = ArgOffset;
2776 if (!isVarArg && !isPPC64) {
2777 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e;
2779 EVT ObjectVT = Ins[ArgNo].VT;
2780 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2782 if (Flags.isByVal()) {
2783 // ObjSize is the true size, ArgSize rounded up to multiple of regs.
2784 unsigned ObjSize = Flags.getByValSize();
2786 ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2787 VecArgOffset += ArgSize;
2791 switch(ObjectVT.getSimpleVT().SimpleTy) {
2792 default: llvm_unreachable("Unhandled argument type!");
2798 case MVT::i64: // PPC64
2800 // FIXME: We are guaranteed to be !isPPC64 at this point.
2801 // Does MVT::i64 apply?
2808 // Nothing to do, we're only looking at Nonvector args here.
2813 // We've found where the vector parameter area in memory is. Skip the
2814 // first 12 parameters; these don't use that memory.
2815 VecArgOffset = ((VecArgOffset+15)/16)*16;
2816 VecArgOffset += 12*16;
2818 // Add DAG nodes to load the arguments or copy them out of registers. On
2819 // entry to a function on PPC, the arguments start after the linkage area,
2820 // although the first ones are often in registers.
2822 SmallVector<SDValue, 8> MemOps;
2823 unsigned nAltivecParamsAtEnd = 0;
2824 Function::const_arg_iterator FuncArg = MF.getFunction()->arg_begin();
2825 unsigned CurArgIdx = 0;
2826 for (unsigned ArgNo = 0, e = Ins.size(); ArgNo != e; ++ArgNo) {
2828 bool needsLoad = false;
2829 EVT ObjectVT = Ins[ArgNo].VT;
2830 unsigned ObjSize = ObjectVT.getSizeInBits()/8;
2831 unsigned ArgSize = ObjSize;
2832 ISD::ArgFlagsTy Flags = Ins[ArgNo].Flags;
2833 std::advance(FuncArg, Ins[ArgNo].OrigArgIndex - CurArgIdx);
2834 CurArgIdx = Ins[ArgNo].OrigArgIndex;
2836 unsigned CurArgOffset = ArgOffset;
2838 // Varargs or 64 bit Altivec parameters are padded to a 16 byte boundary.
2839 if (ObjectVT==MVT::v4f32 || ObjectVT==MVT::v4i32 ||
2840 ObjectVT==MVT::v8i16 || ObjectVT==MVT::v16i8) {
2841 if (isVarArg || isPPC64) {
2842 MinReservedArea = ((MinReservedArea+15)/16)*16;
2843 MinReservedArea += CalculateStackSlotSize(ObjectVT,
2846 } else nAltivecParamsAtEnd++;
2848 // Calculate min reserved area.
2849 MinReservedArea += CalculateStackSlotSize(Ins[ArgNo].VT,
2853 // FIXME the codegen can be much improved in some cases.
2854 // We do not have to keep everything in memory.
2855 if (Flags.isByVal()) {
2856 // ObjSize is the true size, ArgSize rounded up to multiple of registers.
2857 ObjSize = Flags.getByValSize();
2858 ArgSize = ((ObjSize + PtrByteSize - 1)/PtrByteSize) * PtrByteSize;
2859 // Objects of size 1 and 2 are right justified, everything else is
2860 // left justified. This means the memory address is adjusted forwards.
2861 if (ObjSize==1 || ObjSize==2) {
2862 CurArgOffset = CurArgOffset + (4 - ObjSize);
2864 // The value of the object is its address.
2865 int FI = MFI->CreateFixedObject(ObjSize, CurArgOffset, true);
2866 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2867 InVals.push_back(FIN);
2868 if (ObjSize==1 || ObjSize==2) {
2869 if (GPR_idx != Num_GPR_Regs) {
2872 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2874 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2875 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2876 EVT ObjType = ObjSize == 1 ? MVT::i8 : MVT::i16;
2877 SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
2878 MachinePointerInfo(FuncArg),
2879 ObjType, false, false, 0);
2880 MemOps.push_back(Store);
2884 ArgOffset += PtrByteSize;
2888 for (unsigned j = 0; j < ArgSize; j += PtrByteSize) {
2889 // Store whatever pieces of the object are in registers
2890 // to memory. ArgOffset will be the address of the beginning
2892 if (GPR_idx != Num_GPR_Regs) {
2895 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2897 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2898 int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
2899 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
2900 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2901 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
2902 MachinePointerInfo(FuncArg, j),
2904 MemOps.push_back(Store);
2906 ArgOffset += PtrByteSize;
2908 ArgOffset += ArgSize - (ArgOffset-CurArgOffset);
2915 switch (ObjectVT.getSimpleVT().SimpleTy) {
2916 default: llvm_unreachable("Unhandled argument type!");
2920 if (GPR_idx != Num_GPR_Regs) {
2921 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
2922 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
2924 if (ObjectVT == MVT::i1)
2925 ArgVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, ArgVal);
2930 ArgSize = PtrByteSize;
2932 // All int arguments reserve stack space in the Darwin ABI.
2933 ArgOffset += PtrByteSize;
2937 case MVT::i64: // PPC64
2938 if (GPR_idx != Num_GPR_Regs) {
2939 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
2940 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2942 if (ObjectVT == MVT::i32 || ObjectVT == MVT::i1)
2943 // PPC64 passes i8, i16, and i32 values in i64 registers. Promote
2944 // value to MVT::i64 and then truncate to the correct register size.
2945 ArgVal = extendArgForPPC64(Flags, ObjectVT, DAG, ArgVal, dl);
2950 ArgSize = PtrByteSize;
2952 // All int arguments reserve stack space in the Darwin ABI.
2958 // Every 4 bytes of argument space consumes one of the GPRs available for
2959 // argument passing.
2960 if (GPR_idx != Num_GPR_Regs) {
2962 if (ObjSize == 8 && GPR_idx != Num_GPR_Regs && !isPPC64)
2965 if (FPR_idx != Num_FPR_Regs) {
2968 if (ObjectVT == MVT::f32)
2969 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
2971 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
2973 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2979 // All FP arguments reserve stack space in the Darwin ABI.
2980 ArgOffset += isPPC64 ? 8 : ObjSize;
2986 // Note that vector arguments in registers don't reserve stack space,
2987 // except in varargs functions.
2988 if (VR_idx != Num_VR_Regs) {
2989 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
2990 ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
2992 while ((ArgOffset % 16) != 0) {
2993 ArgOffset += PtrByteSize;
2994 if (GPR_idx != Num_GPR_Regs)
2998 GPR_idx = std::min(GPR_idx+4, Num_GPR_Regs); // FIXME correct for ppc64?
3002 if (!isVarArg && !isPPC64) {
3003 // Vectors go after all the nonvectors.
3004 CurArgOffset = VecArgOffset;
3007 // Vectors are aligned.
3008 ArgOffset = ((ArgOffset+15)/16)*16;
3009 CurArgOffset = ArgOffset;
3017 // We need to load the argument to a virtual register if we determined above
3018 // that we ran out of physical registers of the appropriate type.
3020 int FI = MFI->CreateFixedObject(ObjSize,
3021 CurArgOffset + (ArgSize - ObjSize),
3023 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
3024 ArgVal = DAG.getLoad(ObjectVT, dl, Chain, FIN, MachinePointerInfo(),
3025 false, false, false, 0);
3028 InVals.push_back(ArgVal);
3031 // Set the size that is at least reserved in caller of this function. Tail
3032 // call optimized functions' reserved stack space needs to be aligned so that
3033 // taking the difference between two stack areas will result in an aligned
3035 setMinReservedArea(MF, DAG, nAltivecParamsAtEnd, MinReservedArea, isPPC64);
3037 // If the function takes variable number of arguments, make a frame index for
3038 // the start of the first vararg value... for expansion of llvm.va_start.
3040 int Depth = ArgOffset;
3042 FuncInfo->setVarArgsFrameIndex(
3043 MFI->CreateFixedObject(PtrVT.getSizeInBits()/8,
3045 SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
3047 // If this function is vararg, store any remaining integer argument regs
3048 // to their spots on the stack so that they may be loaded by deferencing the
3049 // result of va_next.
3050 for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
3054 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
3056 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
3058 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
3059 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
3060 MachinePointerInfo(), false, false, 0);
3061 MemOps.push_back(Store);
3062 // Increment the address by four for the next argument to store
3063 SDValue PtrOff = DAG.getConstant(PtrVT.getSizeInBits()/8, PtrVT);
3064 FIN = DAG.getNode(ISD::ADD, dl, PtrOff.getValueType(), FIN, PtrOff);
3068 if (!MemOps.empty())
3069 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
3074 /// CalculateParameterAndLinkageAreaSize - Get the size of the parameter plus
3075 /// linkage area for the Darwin ABI, or the 64-bit SVR4 ABI.
3077 CalculateParameterAndLinkageAreaSize(SelectionDAG &DAG,
3081 const SmallVectorImpl<ISD::OutputArg>
3083 const SmallVectorImpl<SDValue> &OutVals,
3084 unsigned &nAltivecParamsAtEnd) {
3085 // Count how many bytes are to be pushed on the stack, including the linkage
3086 // area, and parameter passing area. We start with 24/48 bytes, which is
3087 // prereserved space for [SP][CR][LR][3 x unused].
3088 unsigned NumBytes = PPCFrameLowering::getLinkageSize(isPPC64, true);
3089 unsigned NumOps = Outs.size();
3090 unsigned PtrByteSize = isPPC64 ? 8 : 4;
3092 // Add up all the space actually used.
3093 // In 32-bit non-varargs calls, Altivec parameters all go at the end; usually
3094 // they all go in registers, but we must reserve stack space for them for
3095 // possible use by the caller. In varargs or 64-bit calls, parameters are
3096 // assigned stack space in order, with padding so Altivec parameters are
3098 nAltivecParamsAtEnd = 0;
3099 for (unsigned i = 0; i != NumOps; ++i) {
3100 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3101 EVT ArgVT = Outs[i].VT;
3102 // Varargs Altivec parameters are padded to a 16 byte boundary.
3103 if (ArgVT==MVT::v4f32 || ArgVT==MVT::v4i32 ||
3104 ArgVT==MVT::v8i16 || ArgVT==MVT::v16i8 ||
3105 ArgVT==MVT::v2f64 || ArgVT==MVT::v2i64) {
3106 if (!isVarArg && !isPPC64) {
3107 // Non-varargs Altivec parameters go after all the non-Altivec
3108 // parameters; handle those later so we know how much padding we need.
3109 nAltivecParamsAtEnd++;
3112 // Varargs and 64-bit Altivec parameters are padded to 16 byte boundary.
3113 NumBytes = ((NumBytes+15)/16)*16;
3115 NumBytes += CalculateStackSlotSize(ArgVT, Flags, PtrByteSize);
3118 // Allow for Altivec parameters at the end, if needed.
3119 if (nAltivecParamsAtEnd) {
3120 NumBytes = ((NumBytes+15)/16)*16;
3121 NumBytes += 16*nAltivecParamsAtEnd;
3124 // The prolog code of the callee may store up to 8 GPR argument registers to
3125 // the stack, allowing va_start to index over them in memory if its varargs.
3126 // Because we cannot tell if this is needed on the caller side, we have to
3127 // conservatively assume that it is needed. As such, make sure we have at
3128 // least enough stack space for the caller to store the 8 GPRs.
3129 NumBytes = std::max(NumBytes,
3130 PPCFrameLowering::getMinCallFrameSize(isPPC64, true));
3132 // Tail call needs the stack to be aligned.
3133 if (CC == CallingConv::Fast && DAG.getTarget().Options.GuaranteedTailCallOpt){
3134 unsigned TargetAlign = DAG.getMachineFunction().getTarget().
3135 getFrameLowering()->getStackAlignment();
3136 unsigned AlignMask = TargetAlign-1;
3137 NumBytes = (NumBytes + AlignMask) & ~AlignMask;
3143 /// CalculateTailCallSPDiff - Get the amount the stack pointer has to be
3144 /// adjusted to accommodate the arguments for the tailcall.
3145 static int CalculateTailCallSPDiff(SelectionDAG& DAG, bool isTailCall,
3146 unsigned ParamSize) {
3148 if (!isTailCall) return 0;
3150 PPCFunctionInfo *FI = DAG.getMachineFunction().getInfo<PPCFunctionInfo>();
3151 unsigned CallerMinReservedArea = FI->getMinReservedArea();
3152 int SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
3153 // Remember only if the new adjustement is bigger.
3154 if (SPDiff < FI->getTailCallSPDelta())
3155 FI->setTailCallSPDelta(SPDiff);
3160 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
3161 /// for tail call optimization. Targets which want to do tail call
3162 /// optimization should implement this function.
3164 PPCTargetLowering::IsEligibleForTailCallOptimization(SDValue Callee,
3165 CallingConv::ID CalleeCC,
3167 const SmallVectorImpl<ISD::InputArg> &Ins,
3168 SelectionDAG& DAG) const {
3169 if (!getTargetMachine().Options.GuaranteedTailCallOpt)
3172 // Variable argument functions are not supported.
3176 MachineFunction &MF = DAG.getMachineFunction();
3177 CallingConv::ID CallerCC = MF.getFunction()->getCallingConv();
3178 if (CalleeCC == CallingConv::Fast && CallerCC == CalleeCC) {
3179 // Functions containing by val parameters are not supported.
3180 for (unsigned i = 0; i != Ins.size(); i++) {
3181 ISD::ArgFlagsTy Flags = Ins[i].Flags;
3182 if (Flags.isByVal()) return false;
3185 // Non-PIC/GOT tail calls are supported.
3186 if (getTargetMachine().getRelocationModel() != Reloc::PIC_)
3189 // At the moment we can only do local tail calls (in same module, hidden
3190 // or protected) if we are generating PIC.
3191 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3192 return G->getGlobal()->hasHiddenVisibility()
3193 || G->getGlobal()->hasProtectedVisibility();
3199 /// isCallCompatibleAddress - Return the immediate to use if the specified
3200 /// 32-bit value is representable in the immediate field of a BxA instruction.
3201 static SDNode *isBLACompatibleAddress(SDValue Op, SelectionDAG &DAG) {
3202 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op);
3203 if (!C) return nullptr;
3205 int Addr = C->getZExtValue();
3206 if ((Addr & 3) != 0 || // Low 2 bits are implicitly zero.
3207 SignExtend32<26>(Addr) != Addr)
3208 return nullptr; // Top 6 bits have to be sext of immediate.
3210 return DAG.getConstant((int)C->getZExtValue() >> 2,
3211 DAG.getTargetLoweringInfo().getPointerTy()).getNode();
3216 struct TailCallArgumentInfo {
3221 TailCallArgumentInfo() : FrameIdx(0) {}
3226 /// StoreTailCallArgumentsToStackSlot - Stores arguments to their stack slot.
3228 StoreTailCallArgumentsToStackSlot(SelectionDAG &DAG,
3230 const SmallVectorImpl<TailCallArgumentInfo> &TailCallArgs,
3231 SmallVectorImpl<SDValue> &MemOpChains,
3233 for (unsigned i = 0, e = TailCallArgs.size(); i != e; ++i) {
3234 SDValue Arg = TailCallArgs[i].Arg;
3235 SDValue FIN = TailCallArgs[i].FrameIdxOp;
3236 int FI = TailCallArgs[i].FrameIdx;
3237 // Store relative to framepointer.
3238 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, FIN,
3239 MachinePointerInfo::getFixedStack(FI),
3244 /// EmitTailCallStoreFPAndRetAddr - Move the frame pointer and return address to
3245 /// the appropriate stack slot for the tail call optimized function call.
3246 static SDValue EmitTailCallStoreFPAndRetAddr(SelectionDAG &DAG,
3247 MachineFunction &MF,
3256 // Calculate the new stack slot for the return address.
3257 int SlotSize = isPPC64 ? 8 : 4;
3258 int NewRetAddrLoc = SPDiff + PPCFrameLowering::getReturnSaveOffset(isPPC64,
3260 int NewRetAddr = MF.getFrameInfo()->CreateFixedObject(SlotSize,
3261 NewRetAddrLoc, true);
3262 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3263 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewRetAddr, VT);
3264 Chain = DAG.getStore(Chain, dl, OldRetAddr, NewRetAddrFrIdx,
3265 MachinePointerInfo::getFixedStack(NewRetAddr),
3268 // When using the 32/64-bit SVR4 ABI there is no need to move the FP stack
3269 // slot as the FP is never overwritten.
3272 SPDiff + PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
3273 int NewFPIdx = MF.getFrameInfo()->CreateFixedObject(SlotSize, NewFPLoc,
3275 SDValue NewFramePtrIdx = DAG.getFrameIndex(NewFPIdx, VT);
3276 Chain = DAG.getStore(Chain, dl, OldFP, NewFramePtrIdx,
3277 MachinePointerInfo::getFixedStack(NewFPIdx),
3284 /// CalculateTailCallArgDest - Remember Argument for later processing. Calculate
3285 /// the position of the argument.
3287 CalculateTailCallArgDest(SelectionDAG &DAG, MachineFunction &MF, bool isPPC64,
3288 SDValue Arg, int SPDiff, unsigned ArgOffset,
3289 SmallVectorImpl<TailCallArgumentInfo>& TailCallArguments) {
3290 int Offset = ArgOffset + SPDiff;
3291 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8;
3292 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true);
3293 EVT VT = isPPC64 ? MVT::i64 : MVT::i32;
3294 SDValue FIN = DAG.getFrameIndex(FI, VT);
3295 TailCallArgumentInfo Info;
3297 Info.FrameIdxOp = FIN;
3299 TailCallArguments.push_back(Info);
3302 /// EmitTCFPAndRetAddrLoad - Emit load from frame pointer and return address
3303 /// stack slot. Returns the chain as result and the loaded frame pointers in
3304 /// LROpOut/FPOpout. Used when tail calling.
3305 SDValue PPCTargetLowering::EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
3313 // Load the LR and FP stack slot for later adjusting.
3314 EVT VT = Subtarget.isPPC64() ? MVT::i64 : MVT::i32;
3315 LROpOut = getReturnAddrFrameIndex(DAG);
3316 LROpOut = DAG.getLoad(VT, dl, Chain, LROpOut, MachinePointerInfo(),
3317 false, false, false, 0);
3318 Chain = SDValue(LROpOut.getNode(), 1);
3320 // When using the 32/64-bit SVR4 ABI there is no need to load the FP stack
3321 // slot as the FP is never overwritten.
3323 FPOpOut = getFramePointerFrameIndex(DAG);
3324 FPOpOut = DAG.getLoad(VT, dl, Chain, FPOpOut, MachinePointerInfo(),
3325 false, false, false, 0);
3326 Chain = SDValue(FPOpOut.getNode(), 1);
3332 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified
3333 /// by "Src" to address "Dst" of size "Size". Alignment information is
3334 /// specified by the specific parameter attribute. The copy will be passed as
3335 /// a byval function parameter.
3336 /// Sometimes what we are copying is the end of a larger object, the part that
3337 /// does not fit in registers.
3339 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
3340 ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
3342 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
3343 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
3344 false, false, MachinePointerInfo(),
3345 MachinePointerInfo());
3348 /// LowerMemOpCallTo - Store the argument to the stack or remember it in case of
3351 LowerMemOpCallTo(SelectionDAG &DAG, MachineFunction &MF, SDValue Chain,
3352 SDValue Arg, SDValue PtrOff, int SPDiff,
3353 unsigned ArgOffset, bool isPPC64, bool isTailCall,
3354 bool isVector, SmallVectorImpl<SDValue> &MemOpChains,
3355 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments,
3357 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3362 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
3364 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3365 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
3366 DAG.getConstant(ArgOffset, PtrVT));
3368 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3369 MachinePointerInfo(), false, false, 0));
3370 // Calculate and remember argument location.
3371 } else CalculateTailCallArgDest(DAG, MF, isPPC64, Arg, SPDiff, ArgOffset,
3376 void PrepareTailCall(SelectionDAG &DAG, SDValue &InFlag, SDValue &Chain,
3377 SDLoc dl, bool isPPC64, int SPDiff, unsigned NumBytes,
3378 SDValue LROp, SDValue FPOp, bool isDarwinABI,
3379 SmallVectorImpl<TailCallArgumentInfo> &TailCallArguments) {
3380 MachineFunction &MF = DAG.getMachineFunction();
3382 // Emit a sequence of copyto/copyfrom virtual registers for arguments that
3383 // might overwrite each other in case of tail call optimization.
3384 SmallVector<SDValue, 8> MemOpChains2;
3385 // Do not flag preceding copytoreg stuff together with the following stuff.
3387 StoreTailCallArgumentsToStackSlot(DAG, Chain, TailCallArguments,
3389 if (!MemOpChains2.empty())
3390 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains2);
3392 // Store the return address to the appropriate stack slot.
3393 Chain = EmitTailCallStoreFPAndRetAddr(DAG, MF, Chain, LROp, FPOp, SPDiff,
3394 isPPC64, isDarwinABI, dl);
3396 // Emit callseq_end just before tailcall node.
3397 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3398 DAG.getIntPtrConstant(0, true), InFlag, dl);
3399 InFlag = Chain.getValue(1);
3403 unsigned PrepareCall(SelectionDAG &DAG, SDValue &Callee, SDValue &InFlag,
3404 SDValue &Chain, SDLoc dl, int SPDiff, bool isTailCall,
3405 SmallVectorImpl<std::pair<unsigned, SDValue> > &RegsToPass,
3406 SmallVectorImpl<SDValue> &Ops, std::vector<EVT> &NodeTys,
3407 const PPCSubtarget &Subtarget) {
3409 bool isPPC64 = Subtarget.isPPC64();
3410 bool isSVR4ABI = Subtarget.isSVR4ABI();
3412 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3413 NodeTys.push_back(MVT::Other); // Returns a chain
3414 NodeTys.push_back(MVT::Glue); // Returns a flag for retval copy to use.
3416 unsigned CallOpc = PPCISD::CALL;
3418 bool needIndirectCall = true;
3419 if (!isSVR4ABI || !isPPC64)
3420 if (SDNode *Dest = isBLACompatibleAddress(Callee, DAG)) {
3421 // If this is an absolute destination address, use the munged value.
3422 Callee = SDValue(Dest, 0);
3423 needIndirectCall = false;
3426 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
3427 // XXX Work around for http://llvm.org/bugs/show_bug.cgi?id=5201
3428 // Use indirect calls for ALL functions calls in JIT mode, since the
3429 // far-call stubs may be outside relocation limits for a BL instruction.
3430 if (!DAG.getTarget().getSubtarget<PPCSubtarget>().isJITCodeModel()) {
3431 unsigned OpFlags = 0;
3432 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3433 (Subtarget.getTargetTriple().isMacOSX() &&
3434 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5)) &&
3435 (G->getGlobal()->isDeclaration() ||
3436 G->getGlobal()->isWeakForLinker())) {
3437 // PC-relative references to external symbols should go through $stub,
3438 // unless we're building with the leopard linker or later, which
3439 // automatically synthesizes these stubs.
3440 OpFlags = PPCII::MO_DARWIN_STUB;
3443 // If the callee is a GlobalAddress/ExternalSymbol node (quite common,
3444 // every direct call is) turn it into a TargetGlobalAddress /
3445 // TargetExternalSymbol node so that legalize doesn't hack it.
3446 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
3447 Callee.getValueType(),
3449 needIndirectCall = false;
3453 if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) {
3454 unsigned char OpFlags = 0;
3456 if (DAG.getTarget().getRelocationModel() != Reloc::Static &&
3457 (Subtarget.getTargetTriple().isMacOSX() &&
3458 Subtarget.getTargetTriple().isMacOSXVersionLT(10, 5))) {
3459 // PC-relative references to external symbols should go through $stub,
3460 // unless we're building with the leopard linker or later, which
3461 // automatically synthesizes these stubs.
3462 OpFlags = PPCII::MO_DARWIN_STUB;
3465 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), Callee.getValueType(),
3467 needIndirectCall = false;
3470 if (needIndirectCall) {
3471 // Otherwise, this is an indirect call. We have to use a MTCTR/BCTRL pair
3472 // to do the call, we can't use PPCISD::CALL.
3473 SDValue MTCTROps[] = {Chain, Callee, InFlag};
3475 if (isSVR4ABI && isPPC64) {
3476 // Function pointers in the 64-bit SVR4 ABI do not point to the function
3477 // entry point, but to the function descriptor (the function entry point
3478 // address is part of the function descriptor though).
3479 // The function descriptor is a three doubleword structure with the
3480 // following fields: function entry point, TOC base address and
3481 // environment pointer.
3482 // Thus for a call through a function pointer, the following actions need
3484 // 1. Save the TOC of the caller in the TOC save area of its stack
3485 // frame (this is done in LowerCall_Darwin() or LowerCall_64SVR4()).
3486 // 2. Load the address of the function entry point from the function
3488 // 3. Load the TOC of the callee from the function descriptor into r2.
3489 // 4. Load the environment pointer from the function descriptor into
3491 // 5. Branch to the function entry point address.
3492 // 6. On return of the callee, the TOC of the caller needs to be
3493 // restored (this is done in FinishCall()).
3495 // All those operations are flagged together to ensure that no other
3496 // operations can be scheduled in between. E.g. without flagging the
3497 // operations together, a TOC access in the caller could be scheduled
3498 // between the load of the callee TOC and the branch to the callee, which
3499 // results in the TOC access going through the TOC of the callee instead
3500 // of going through the TOC of the caller, which leads to incorrect code.
3502 // Load the address of the function entry point from the function
3504 SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other, MVT::Glue);
3505 SDValue LoadFuncPtr = DAG.getNode(PPCISD::LOAD, dl, VTs,
3506 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3507 Chain = LoadFuncPtr.getValue(1);
3508 InFlag = LoadFuncPtr.getValue(2);
3510 // Load environment pointer into r11.
3511 // Offset of the environment pointer within the function descriptor.
3512 SDValue PtrOff = DAG.getIntPtrConstant(16);
3514 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, PtrOff);
3515 SDValue LoadEnvPtr = DAG.getNode(PPCISD::LOAD, dl, VTs, Chain, AddPtr,
3517 Chain = LoadEnvPtr.getValue(1);
3518 InFlag = LoadEnvPtr.getValue(2);
3520 SDValue EnvVal = DAG.getCopyToReg(Chain, dl, PPC::X11, LoadEnvPtr,
3522 Chain = EnvVal.getValue(0);
3523 InFlag = EnvVal.getValue(1);
3525 // Load TOC of the callee into r2. We are using a target-specific load
3526 // with r2 hard coded, because the result of a target-independent load
3527 // would never go directly into r2, since r2 is a reserved register (which
3528 // prevents the register allocator from allocating it), resulting in an
3529 // additional register being allocated and an unnecessary move instruction
3531 VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3532 SDValue TOCOff = DAG.getIntPtrConstant(8);
3533 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, Callee, TOCOff);
3534 SDValue LoadTOCPtr = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain,
3536 Chain = LoadTOCPtr.getValue(0);
3537 InFlag = LoadTOCPtr.getValue(1);
3539 MTCTROps[0] = Chain;
3540 MTCTROps[1] = LoadFuncPtr;
3541 MTCTROps[2] = InFlag;
3544 Chain = DAG.getNode(PPCISD::MTCTR, dl, NodeTys,
3545 makeArrayRef(MTCTROps, InFlag.getNode() ? 3 : 2));
3546 InFlag = Chain.getValue(1);
3549 NodeTys.push_back(MVT::Other);
3550 NodeTys.push_back(MVT::Glue);
3551 Ops.push_back(Chain);
3552 CallOpc = PPCISD::BCTRL;
3553 Callee.setNode(nullptr);
3554 // Add use of X11 (holding environment pointer)
3555 if (isSVR4ABI && isPPC64)
3556 Ops.push_back(DAG.getRegister(PPC::X11, PtrVT));
3557 // Add CTR register as callee so a bctr can be emitted later.
3559 Ops.push_back(DAG.getRegister(isPPC64 ? PPC::CTR8 : PPC::CTR, PtrVT));
3562 // If this is a direct call, pass the chain and the callee.
3563 if (Callee.getNode()) {
3564 Ops.push_back(Chain);
3565 Ops.push_back(Callee);
3567 // If this is a tail call add stack pointer delta.
3569 Ops.push_back(DAG.getConstant(SPDiff, MVT::i32));
3571 // Add argument registers to the end of the list so that they are known live
3573 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
3574 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
3575 RegsToPass[i].second.getValueType()));
3581 bool isLocalCall(const SDValue &Callee)
3583 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
3584 return !G->getGlobal()->isDeclaration() &&
3585 !G->getGlobal()->isWeakForLinker();
3590 PPCTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
3591 CallingConv::ID CallConv, bool isVarArg,
3592 const SmallVectorImpl<ISD::InputArg> &Ins,
3593 SDLoc dl, SelectionDAG &DAG,
3594 SmallVectorImpl<SDValue> &InVals) const {
3596 SmallVector<CCValAssign, 16> RVLocs;
3597 CCState CCRetInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3598 getTargetMachine(), RVLocs, *DAG.getContext());
3599 CCRetInfo.AnalyzeCallResult(Ins, RetCC_PPC);
3601 // Copy all of the result registers out of their specified physreg.
3602 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
3603 CCValAssign &VA = RVLocs[i];
3604 assert(VA.isRegLoc() && "Can only return in registers!");
3606 SDValue Val = DAG.getCopyFromReg(Chain, dl,
3607 VA.getLocReg(), VA.getLocVT(), InFlag);
3608 Chain = Val.getValue(1);
3609 InFlag = Val.getValue(2);
3611 switch (VA.getLocInfo()) {
3612 default: llvm_unreachable("Unknown loc info!");
3613 case CCValAssign::Full: break;
3614 case CCValAssign::AExt:
3615 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3617 case CCValAssign::ZExt:
3618 Val = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), Val,
3619 DAG.getValueType(VA.getValVT()));
3620 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3622 case CCValAssign::SExt:
3623 Val = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), Val,
3624 DAG.getValueType(VA.getValVT()));
3625 Val = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), Val);
3629 InVals.push_back(Val);
3636 PPCTargetLowering::FinishCall(CallingConv::ID CallConv, SDLoc dl,
3637 bool isTailCall, bool isVarArg,
3639 SmallVector<std::pair<unsigned, SDValue>, 8>
3641 SDValue InFlag, SDValue Chain,
3643 int SPDiff, unsigned NumBytes,
3644 const SmallVectorImpl<ISD::InputArg> &Ins,
3645 SmallVectorImpl<SDValue> &InVals) const {
3646 std::vector<EVT> NodeTys;
3647 SmallVector<SDValue, 8> Ops;
3648 unsigned CallOpc = PrepareCall(DAG, Callee, InFlag, Chain, dl, SPDiff,
3649 isTailCall, RegsToPass, Ops, NodeTys,
3652 // Add implicit use of CR bit 6 for 32-bit SVR4 vararg calls
3653 if (isVarArg && Subtarget.isSVR4ABI() && !Subtarget.isPPC64())
3654 Ops.push_back(DAG.getRegister(PPC::CR1EQ, MVT::i32));
3656 // When performing tail call optimization the callee pops its arguments off
3657 // the stack. Account for this here so these bytes can be pushed back on in
3658 // PPCFrameLowering::eliminateCallFramePseudoInstr.
3659 int BytesCalleePops =
3660 (CallConv == CallingConv::Fast &&
3661 getTargetMachine().Options.GuaranteedTailCallOpt) ? NumBytes : 0;
3663 // Add a register mask operand representing the call-preserved registers.
3664 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
3665 const uint32_t *Mask = TRI->getCallPreservedMask(CallConv);
3666 assert(Mask && "Missing call preserved mask for calling convention");
3667 Ops.push_back(DAG.getRegisterMask(Mask));
3669 if (InFlag.getNode())
3670 Ops.push_back(InFlag);
3674 assert(((Callee.getOpcode() == ISD::Register &&
3675 cast<RegisterSDNode>(Callee)->getReg() == PPC::CTR) ||
3676 Callee.getOpcode() == ISD::TargetExternalSymbol ||
3677 Callee.getOpcode() == ISD::TargetGlobalAddress ||
3678 isa<ConstantSDNode>(Callee)) &&
3679 "Expecting an global address, external symbol, absolute value or register");
3681 return DAG.getNode(PPCISD::TC_RETURN, dl, MVT::Other, Ops);
3684 // Add a NOP immediately after the branch instruction when using the 64-bit
3685 // SVR4 ABI. At link time, if caller and callee are in a different module and
3686 // thus have a different TOC, the call will be replaced with a call to a stub
3687 // function which saves the current TOC, loads the TOC of the callee and
3688 // branches to the callee. The NOP will be replaced with a load instruction
3689 // which restores the TOC of the caller from the TOC save slot of the current
3690 // stack frame. If caller and callee belong to the same module (and have the
3691 // same TOC), the NOP will remain unchanged.
3693 bool needsTOCRestore = false;
3694 if (!isTailCall && Subtarget.isSVR4ABI()&& Subtarget.isPPC64()) {
3695 if (CallOpc == PPCISD::BCTRL) {
3696 // This is a call through a function pointer.
3697 // Restore the caller TOC from the save area into R2.
3698 // See PrepareCall() for more information about calls through function
3699 // pointers in the 64-bit SVR4 ABI.
3700 // We are using a target-specific load with r2 hard coded, because the
3701 // result of a target-independent load would never go directly into r2,
3702 // since r2 is a reserved register (which prevents the register allocator
3703 // from allocating it), resulting in an additional register being
3704 // allocated and an unnecessary move instruction being generated.
3705 needsTOCRestore = true;
3706 } else if ((CallOpc == PPCISD::CALL) &&
3707 (!isLocalCall(Callee) ||
3708 DAG.getTarget().getRelocationModel() == Reloc::PIC_)) {
3709 // Otherwise insert NOP for non-local calls.
3710 CallOpc = PPCISD::CALL_NOP;
3714 Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
3715 InFlag = Chain.getValue(1);
3717 if (needsTOCRestore) {
3718 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3719 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
3720 SDValue StackPtr = DAG.getRegister(PPC::X1, PtrVT);
3721 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
3722 SDValue TOCOff = DAG.getIntPtrConstant(TOCSaveOffset);
3723 SDValue AddTOC = DAG.getNode(ISD::ADD, dl, MVT::i64, StackPtr, TOCOff);
3724 Chain = DAG.getNode(PPCISD::LOAD_TOC, dl, VTs, Chain, AddTOC, InFlag);
3725 InFlag = Chain.getValue(1);
3728 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
3729 DAG.getIntPtrConstant(BytesCalleePops, true),
3732 InFlag = Chain.getValue(1);
3734 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
3735 Ins, dl, DAG, InVals);
3739 PPCTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
3740 SmallVectorImpl<SDValue> &InVals) const {
3741 SelectionDAG &DAG = CLI.DAG;
3743 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
3744 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
3745 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
3746 SDValue Chain = CLI.Chain;
3747 SDValue Callee = CLI.Callee;
3748 bool &isTailCall = CLI.IsTailCall;
3749 CallingConv::ID CallConv = CLI.CallConv;
3750 bool isVarArg = CLI.IsVarArg;
3753 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, isVarArg,
3756 if (!isTailCall && CLI.CS && CLI.CS->isMustTailCall())
3757 report_fatal_error("failed to perform tail call elimination on a call "
3758 "site marked musttail");
3760 if (Subtarget.isSVR4ABI()) {
3761 if (Subtarget.isPPC64())
3762 return LowerCall_64SVR4(Chain, Callee, CallConv, isVarArg,
3763 isTailCall, Outs, OutVals, Ins,
3766 return LowerCall_32SVR4(Chain, Callee, CallConv, isVarArg,
3767 isTailCall, Outs, OutVals, Ins,
3771 return LowerCall_Darwin(Chain, Callee, CallConv, isVarArg,
3772 isTailCall, Outs, OutVals, Ins,
3777 PPCTargetLowering::LowerCall_32SVR4(SDValue Chain, SDValue Callee,
3778 CallingConv::ID CallConv, bool isVarArg,
3780 const SmallVectorImpl<ISD::OutputArg> &Outs,
3781 const SmallVectorImpl<SDValue> &OutVals,
3782 const SmallVectorImpl<ISD::InputArg> &Ins,
3783 SDLoc dl, SelectionDAG &DAG,
3784 SmallVectorImpl<SDValue> &InVals) const {
3785 // See PPCTargetLowering::LowerFormalArguments_32SVR4() for a description
3786 // of the 32-bit SVR4 ABI stack frame layout.
3788 assert((CallConv == CallingConv::C ||
3789 CallConv == CallingConv::Fast) && "Unknown calling convention!");
3791 unsigned PtrByteSize = 4;
3793 MachineFunction &MF = DAG.getMachineFunction();
3795 // Mark this function as potentially containing a function that contains a
3796 // tail call. As a consequence the frame pointer will be used for dynamicalloc
3797 // and restoring the callers stack pointer in this functions epilog. This is
3798 // done because by tail calling the called function might overwrite the value
3799 // in this function's (MF) stack pointer stack slot 0(SP).
3800 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
3801 CallConv == CallingConv::Fast)
3802 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
3804 // Count how many bytes are to be pushed on the stack, including the linkage
3805 // area, parameter list area and the part of the local variable space which
3806 // contains copies of aggregates which are passed by value.
3808 // Assign locations to all of the outgoing arguments.
3809 SmallVector<CCValAssign, 16> ArgLocs;
3810 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3811 getTargetMachine(), ArgLocs, *DAG.getContext());
3813 // Reserve space for the linkage area on the stack.
3814 CCInfo.AllocateStack(PPCFrameLowering::getLinkageSize(false, false), PtrByteSize);
3817 // Handle fixed and variable vector arguments differently.
3818 // Fixed vector arguments go into registers as long as registers are
3819 // available. Variable vector arguments always go into memory.
3820 unsigned NumArgs = Outs.size();
3822 for (unsigned i = 0; i != NumArgs; ++i) {
3823 MVT ArgVT = Outs[i].VT;
3824 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
3827 if (Outs[i].IsFixed) {
3828 Result = CC_PPC32_SVR4(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags,
3831 Result = CC_PPC32_SVR4_VarArg(i, ArgVT, ArgVT, CCValAssign::Full,
3837 errs() << "Call operand #" << i << " has unhandled type "
3838 << EVT(ArgVT).getEVTString() << "\n";
3840 llvm_unreachable(nullptr);
3844 // All arguments are treated the same.
3845 CCInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4);
3848 // Assign locations to all of the outgoing aggregate by value arguments.
3849 SmallVector<CCValAssign, 16> ByValArgLocs;
3850 CCState CCByValInfo(CallConv, isVarArg, DAG.getMachineFunction(),
3851 getTargetMachine(), ByValArgLocs, *DAG.getContext());
3853 // Reserve stack space for the allocations in CCInfo.
3854 CCByValInfo.AllocateStack(CCInfo.getNextStackOffset(), PtrByteSize);
3856 CCByValInfo.AnalyzeCallOperands(Outs, CC_PPC32_SVR4_ByVal);
3858 // Size of the linkage area, parameter list area and the part of the local
3859 // space variable where copies of aggregates which are passed by value are
3861 unsigned NumBytes = CCByValInfo.getNextStackOffset();
3863 // Calculate by how many bytes the stack has to be adjusted in case of tail
3864 // call optimization.
3865 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
3867 // Adjust the stack pointer for the new arguments...
3868 // These operations are automatically eliminated by the prolog/epilog pass
3869 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
3871 SDValue CallSeqStart = Chain;
3873 // Load the return address and frame pointer so it can be moved somewhere else
3876 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, false,
3879 // Set up a copy of the stack pointer for use loading and storing any
3880 // arguments that may not fit in the registers available for argument
3882 SDValue StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
3884 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
3885 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
3886 SmallVector<SDValue, 8> MemOpChains;
3888 bool seenFloatArg = false;
3889 // Walk the register/memloc assignments, inserting copies/loads.
3890 for (unsigned i = 0, j = 0, e = ArgLocs.size();
3893 CCValAssign &VA = ArgLocs[i];
3894 SDValue Arg = OutVals[i];
3895 ISD::ArgFlagsTy Flags = Outs[i].Flags;
3897 if (Flags.isByVal()) {
3898 // Argument is an aggregate which is passed by value, thus we need to
3899 // create a copy of it in the local variable space of the current stack
3900 // frame (which is the stack frame of the caller) and pass the address of
3901 // this copy to the callee.
3902 assert((j < ByValArgLocs.size()) && "Index out of bounds!");
3903 CCValAssign &ByValVA = ByValArgLocs[j++];
3904 assert((VA.getValNo() == ByValVA.getValNo()) && "ValNo mismatch!");
3906 // Memory reserved in the local variable space of the callers stack frame.
3907 unsigned LocMemOffset = ByValVA.getLocMemOffset();
3909 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3910 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3912 // Create a copy of the argument in the local area of the current
3914 SDValue MemcpyCall =
3915 CreateCopyOfByValArgument(Arg, PtrOff,
3916 CallSeqStart.getNode()->getOperand(0),
3919 // This must go outside the CALLSEQ_START..END.
3920 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
3921 CallSeqStart.getNode()->getOperand(1),
3923 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
3924 NewCallSeqStart.getNode());
3925 Chain = CallSeqStart = NewCallSeqStart;
3927 // Pass the address of the aggregate copy on the stack either in a
3928 // physical register or in the parameter list area of the current stack
3929 // frame to the callee.
3933 if (VA.isRegLoc()) {
3934 if (Arg.getValueType() == MVT::i1)
3935 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Arg);
3937 seenFloatArg |= VA.getLocVT().isFloatingPoint();
3938 // Put argument in a physical register.
3939 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
3941 // Put argument in the parameter list area of the current stack frame.
3942 assert(VA.isMemLoc());
3943 unsigned LocMemOffset = VA.getLocMemOffset();
3946 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset);
3947 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff);
3949 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
3950 MachinePointerInfo(),
3953 // Calculate and remember argument location.
3954 CalculateTailCallArgDest(DAG, MF, false, Arg, SPDiff, LocMemOffset,
3960 if (!MemOpChains.empty())
3961 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
3963 // Build a sequence of copy-to-reg nodes chained together with token chain
3964 // and flag operands which copy the outgoing args into the appropriate regs.
3966 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
3967 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
3968 RegsToPass[i].second, InFlag);
3969 InFlag = Chain.getValue(1);
3972 // Set CR bit 6 to true if this is a vararg call with floating args passed in
3975 SDVTList VTs = DAG.getVTList(MVT::Other, MVT::Glue);
3976 SDValue Ops[] = { Chain, InFlag };
3978 Chain = DAG.getNode(seenFloatArg ? PPCISD::CR6SET : PPCISD::CR6UNSET,
3979 dl, VTs, makeArrayRef(Ops, InFlag.getNode() ? 2 : 1));
3981 InFlag = Chain.getValue(1);
3985 PrepareTailCall(DAG, InFlag, Chain, dl, false, SPDiff, NumBytes, LROp, FPOp,
3986 false, TailCallArguments);
3988 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
3989 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
3993 // Copy an argument into memory, being careful to do this outside the
3994 // call sequence for the call to which the argument belongs.
3996 PPCTargetLowering::createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
3997 SDValue CallSeqStart,
3998 ISD::ArgFlagsTy Flags,
4001 SDValue MemcpyCall = CreateCopyOfByValArgument(Arg, PtrOff,
4002 CallSeqStart.getNode()->getOperand(0),
4004 // The MEMCPY must go outside the CALLSEQ_START..END.
4005 SDValue NewCallSeqStart = DAG.getCALLSEQ_START(MemcpyCall,
4006 CallSeqStart.getNode()->getOperand(1),
4008 DAG.ReplaceAllUsesWith(CallSeqStart.getNode(),
4009 NewCallSeqStart.getNode());
4010 return NewCallSeqStart;
4014 PPCTargetLowering::LowerCall_64SVR4(SDValue Chain, SDValue Callee,
4015 CallingConv::ID CallConv, bool isVarArg,
4017 const SmallVectorImpl<ISD::OutputArg> &Outs,
4018 const SmallVectorImpl<SDValue> &OutVals,
4019 const SmallVectorImpl<ISD::InputArg> &Ins,
4020 SDLoc dl, SelectionDAG &DAG,
4021 SmallVectorImpl<SDValue> &InVals) const {
4023 bool isLittleEndian = Subtarget.isLittleEndian();
4024 unsigned NumOps = Outs.size();
4026 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4027 unsigned PtrByteSize = 8;
4029 MachineFunction &MF = DAG.getMachineFunction();
4031 // Mark this function as potentially containing a function that contains a
4032 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4033 // and restoring the callers stack pointer in this functions epilog. This is
4034 // done because by tail calling the called function might overwrite the value
4035 // in this function's (MF) stack pointer stack slot 0(SP).
4036 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4037 CallConv == CallingConv::Fast)
4038 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4040 unsigned nAltivecParamsAtEnd = 0;
4042 // Count how many bytes are to be pushed on the stack, including the linkage
4043 // area, and parameter passing area. We start with at least 48 bytes, which
4044 // is reserved space for [SP][CR][LR][3 x unused].
4045 // NOTE: For PPC64, nAltivecParamsAtEnd always remains zero as a result
4048 CalculateParameterAndLinkageAreaSize(DAG, true, isVarArg, CallConv,
4049 Outs, OutVals, nAltivecParamsAtEnd);
4051 // Calculate by how many bytes the stack has to be adjusted in case of tail
4052 // call optimization.
4053 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4055 // To protect arguments on the stack from being clobbered in a tail call,
4056 // force all the loads to happen before doing any other lowering.
4058 Chain = DAG.getStackArgumentTokenFactor(Chain);
4060 // Adjust the stack pointer for the new arguments...
4061 // These operations are automatically eliminated by the prolog/epilog pass
4062 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4064 SDValue CallSeqStart = Chain;
4066 // Load the return address and frame pointer so it can be move somewhere else
4069 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4072 // Set up a copy of the stack pointer for use loading and storing any
4073 // arguments that may not fit in the registers available for argument
4075 SDValue StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4077 // Figure out which arguments are going to go in registers, and which in
4078 // memory. Also, if this is a vararg function, floating point operations
4079 // must be stored to our stack, and loaded into integer regs as well, if
4080 // any integer regs are available for argument passing.
4081 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(true, true);
4082 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4084 static const MCPhysReg GPR[] = {
4085 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4086 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4088 static const MCPhysReg *FPR = GetFPR();
4090 static const MCPhysReg VR[] = {
4091 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4092 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4094 static const MCPhysReg VSRH[] = {
4095 PPC::VSH2, PPC::VSH3, PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, PPC::VSH8,
4096 PPC::VSH9, PPC::VSH10, PPC::VSH11, PPC::VSH12, PPC::VSH13
4099 const unsigned NumGPRs = array_lengthof(GPR);
4100 const unsigned NumFPRs = 13;
4101 const unsigned NumVRs = array_lengthof(VR);
4103 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4104 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4106 SmallVector<SDValue, 8> MemOpChains;
4107 for (unsigned i = 0; i != NumOps; ++i) {
4108 SDValue Arg = OutVals[i];
4109 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4111 // PtrOff will be used to store the current argument to the stack if a
4112 // register cannot be found for it.
4115 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4117 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4119 // Promote integers to 64-bit values.
4120 if (Arg.getValueType() == MVT::i32 || Arg.getValueType() == MVT::i1) {
4121 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4122 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4123 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4126 // FIXME memcpy is used way more than necessary. Correctness first.
4127 // Note: "by value" is code for passing a structure by value, not
4129 if (Flags.isByVal()) {
4130 // Note: Size includes alignment padding, so
4131 // struct x { short a; char b; }
4132 // will have Size = 4. With #pragma pack(1), it will have Size = 3.
4133 // These are the proper values we need for right-justifying the
4134 // aggregate in a parameter register.
4135 unsigned Size = Flags.getByValSize();
4137 // An empty aggregate parameter takes up no storage and no
4142 unsigned BVAlign = Flags.getByValAlign();
4144 if (BVAlign % PtrByteSize != 0)
4146 "ByVal alignment is not a multiple of the pointer size");
4148 ArgOffset = ((ArgOffset+BVAlign-1)/BVAlign)*BVAlign;
4151 // All aggregates smaller than 8 bytes must be passed right-justified.
4152 if (Size==1 || Size==2 || Size==4) {
4153 EVT VT = (Size==1) ? MVT::i8 : ((Size==2) ? MVT::i16 : MVT::i32);
4154 if (GPR_idx != NumGPRs) {
4155 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4156 MachinePointerInfo(), VT,
4158 MemOpChains.push_back(Load.getValue(1));
4159 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4161 ArgOffset += PtrByteSize;
4166 if (GPR_idx == NumGPRs && Size < 8) {
4167 SDValue AddPtr = PtrOff;
4168 if (!isLittleEndian) {
4169 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4170 PtrOff.getValueType());
4171 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4173 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4176 ArgOffset += PtrByteSize;
4179 // Copy entire object into memory. There are cases where gcc-generated
4180 // code assumes it is there, even if it could be put entirely into
4181 // registers. (This is not what the doc says.)
4183 // FIXME: The above statement is likely due to a misunderstanding of the
4184 // documents. All arguments must be copied into the parameter area BY
4185 // THE CALLEE in the event that the callee takes the address of any
4186 // formal argument. That has not yet been implemented. However, it is
4187 // reasonable to use the stack area as a staging area for the register
4190 // Skip this for small aggregates, as we will use the same slot for a
4191 // right-justified copy, below.
4193 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4197 // When a register is available, pass a small aggregate right-justified.
4198 if (Size < 8 && GPR_idx != NumGPRs) {
4199 // The easiest way to get this right-justified in a register
4200 // is to copy the structure into the rightmost portion of a
4201 // local variable slot, then load the whole slot into the
4203 // FIXME: The memcpy seems to produce pretty awful code for
4204 // small aggregates, particularly for packed ones.
4205 // FIXME: It would be preferable to use the slot in the
4206 // parameter save area instead of a new local variable.
4207 SDValue AddPtr = PtrOff;
4208 if (!isLittleEndian) {
4209 SDValue Const = DAG.getConstant(8 - Size, PtrOff.getValueType());
4210 AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4212 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4216 // Load the slot into the register.
4217 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, PtrOff,
4218 MachinePointerInfo(),
4219 false, false, false, 0);
4220 MemOpChains.push_back(Load.getValue(1));
4221 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4223 // Done with this argument.
4224 ArgOffset += PtrByteSize;
4228 // For aggregates larger than PtrByteSize, copy the pieces of the
4229 // object that fit into registers from the parameter save area.
4230 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4231 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4232 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4233 if (GPR_idx != NumGPRs) {
4234 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4235 MachinePointerInfo(),
4236 false, false, false, 0);
4237 MemOpChains.push_back(Load.getValue(1));
4238 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4239 ArgOffset += PtrByteSize;
4241 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4248 switch (Arg.getSimpleValueType().SimpleTy) {
4249 default: llvm_unreachable("Unexpected ValueType for argument!");
4253 if (GPR_idx != NumGPRs) {
4254 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4256 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4257 true, isTailCall, false, MemOpChains,
4258 TailCallArguments, dl);
4260 ArgOffset += PtrByteSize;
4264 if (FPR_idx != NumFPRs) {
4265 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4268 // A single float or an aggregate containing only a single float
4269 // must be passed right-justified in the stack doubleword, and
4270 // in the GPR, if one is available.
4272 if (Arg.getSimpleValueType().SimpleTy == MVT::f32 &&
4274 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4275 StoreOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4279 SDValue Store = DAG.getStore(Chain, dl, Arg, StoreOff,
4280 MachinePointerInfo(), false, false, 0);
4281 MemOpChains.push_back(Store);
4283 // Float varargs are always shadowed in available integer registers
4284 if (GPR_idx != NumGPRs) {
4285 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4286 MachinePointerInfo(), false, false,
4288 MemOpChains.push_back(Load.getValue(1));
4289 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4291 } else if (GPR_idx != NumGPRs)
4292 // If we have any FPRs remaining, we may also have GPRs remaining.
4295 // Single-precision floating-point values are mapped to the
4296 // second (rightmost) word of the stack doubleword.
4297 if (Arg.getValueType() == MVT::f32 && !isLittleEndian) {
4298 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4299 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4302 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4303 true, isTailCall, false, MemOpChains,
4304 TailCallArguments, dl);
4314 // Vectors are aligned to a 16-byte boundary in the argument save area.
4315 while (ArgOffset % 16 !=0) {
4316 ArgOffset += PtrByteSize;
4317 if (GPR_idx != NumGPRs)
4321 // For a varargs call, named arguments go into VRs or on the stack as
4322 // usual; unnamed arguments always go to the stack or the corresponding
4323 // GPRs when within range. For now, we always put the value in both
4324 // locations (or even all three).
4326 // We could elide this store in the case where the object fits
4327 // entirely in R registers. Maybe later.
4328 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4329 DAG.getConstant(ArgOffset, PtrVT));
4330 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4331 MachinePointerInfo(), false, false, 0);
4332 MemOpChains.push_back(Store);
4333 if (VR_idx != NumVRs) {
4334 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4335 MachinePointerInfo(),
4336 false, false, false, 0);
4337 MemOpChains.push_back(Load.getValue(1));
4339 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4340 Arg.getSimpleValueType() == MVT::v2i64) ?
4341 VSRH[VR_idx] : VR[VR_idx];
4344 RegsToPass.push_back(std::make_pair(VReg, Load));
4347 for (unsigned i=0; i<16; i+=PtrByteSize) {
4348 if (GPR_idx == NumGPRs)
4350 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4351 DAG.getConstant(i, PtrVT));
4352 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4353 false, false, false, 0);
4354 MemOpChains.push_back(Load.getValue(1));
4355 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4360 // Non-varargs Altivec params go into VRs or on the stack.
4361 if (VR_idx != NumVRs) {
4362 unsigned VReg = (Arg.getSimpleValueType() == MVT::v2f64 ||
4363 Arg.getSimpleValueType() == MVT::v2i64) ?
4364 VSRH[VR_idx] : VR[VR_idx];
4367 RegsToPass.push_back(std::make_pair(VReg, Arg));
4369 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4370 true, isTailCall, true, MemOpChains,
4371 TailCallArguments, dl);
4374 GPR_idx = std::min(GPR_idx + 2, NumGPRs);
4379 if (!MemOpChains.empty())
4380 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4382 // Check if this is an indirect call (MTCTR/BCTRL).
4383 // See PrepareCall() for more information about calls through function
4384 // pointers in the 64-bit SVR4 ABI.
4386 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4387 !dyn_cast<ExternalSymbolSDNode>(Callee)) {
4388 // Load r2 into a virtual register and store it to the TOC save area.
4389 SDValue Val = DAG.getCopyFromReg(Chain, dl, PPC::X2, MVT::i64);
4390 // TOC save area offset.
4391 unsigned TOCSaveOffset = PPCFrameLowering::getTOCSaveOffset();
4392 SDValue PtrOff = DAG.getIntPtrConstant(TOCSaveOffset);
4393 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4394 Chain = DAG.getStore(Val.getValue(1), dl, Val, AddPtr, MachinePointerInfo(),
4398 // Build a sequence of copy-to-reg nodes chained together with token chain
4399 // and flag operands which copy the outgoing args into the appropriate regs.
4401 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4402 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4403 RegsToPass[i].second, InFlag);
4404 InFlag = Chain.getValue(1);
4408 PrepareTailCall(DAG, InFlag, Chain, dl, true, SPDiff, NumBytes, LROp,
4409 FPOp, true, TailCallArguments);
4411 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4412 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4417 PPCTargetLowering::LowerCall_Darwin(SDValue Chain, SDValue Callee,
4418 CallingConv::ID CallConv, bool isVarArg,
4420 const SmallVectorImpl<ISD::OutputArg> &Outs,
4421 const SmallVectorImpl<SDValue> &OutVals,
4422 const SmallVectorImpl<ISD::InputArg> &Ins,
4423 SDLoc dl, SelectionDAG &DAG,
4424 SmallVectorImpl<SDValue> &InVals) const {
4426 unsigned NumOps = Outs.size();
4428 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4429 bool isPPC64 = PtrVT == MVT::i64;
4430 unsigned PtrByteSize = isPPC64 ? 8 : 4;
4432 MachineFunction &MF = DAG.getMachineFunction();
4434 // Mark this function as potentially containing a function that contains a
4435 // tail call. As a consequence the frame pointer will be used for dynamicalloc
4436 // and restoring the callers stack pointer in this functions epilog. This is
4437 // done because by tail calling the called function might overwrite the value
4438 // in this function's (MF) stack pointer stack slot 0(SP).
4439 if (getTargetMachine().Options.GuaranteedTailCallOpt &&
4440 CallConv == CallingConv::Fast)
4441 MF.getInfo<PPCFunctionInfo>()->setHasFastCall();
4443 unsigned nAltivecParamsAtEnd = 0;
4445 // Count how many bytes are to be pushed on the stack, including the linkage
4446 // area, and parameter passing area. We start with 24/48 bytes, which is
4447 // prereserved space for [SP][CR][LR][3 x unused].
4449 CalculateParameterAndLinkageAreaSize(DAG, isPPC64, isVarArg, CallConv,
4451 nAltivecParamsAtEnd);
4453 // Calculate by how many bytes the stack has to be adjusted in case of tail
4454 // call optimization.
4455 int SPDiff = CalculateTailCallSPDiff(DAG, isTailCall, NumBytes);
4457 // To protect arguments on the stack from being clobbered in a tail call,
4458 // force all the loads to happen before doing any other lowering.
4460 Chain = DAG.getStackArgumentTokenFactor(Chain);
4462 // Adjust the stack pointer for the new arguments...
4463 // These operations are automatically eliminated by the prolog/epilog pass
4464 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true),
4466 SDValue CallSeqStart = Chain;
4468 // Load the return address and frame pointer so it can be move somewhere else
4471 Chain = EmitTailCallLoadFPAndRetAddr(DAG, SPDiff, Chain, LROp, FPOp, true,
4474 // Set up a copy of the stack pointer for use loading and storing any
4475 // arguments that may not fit in the registers available for argument
4479 StackPtr = DAG.getRegister(PPC::X1, MVT::i64);
4481 StackPtr = DAG.getRegister(PPC::R1, MVT::i32);
4483 // Figure out which arguments are going to go in registers, and which in
4484 // memory. Also, if this is a vararg function, floating point operations
4485 // must be stored to our stack, and loaded into integer regs as well, if
4486 // any integer regs are available for argument passing.
4487 unsigned ArgOffset = PPCFrameLowering::getLinkageSize(isPPC64, true);
4488 unsigned GPR_idx = 0, FPR_idx = 0, VR_idx = 0;
4490 static const MCPhysReg GPR_32[] = { // 32-bit registers.
4491 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
4492 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
4494 static const MCPhysReg GPR_64[] = { // 64-bit registers.
4495 PPC::X3, PPC::X4, PPC::X5, PPC::X6,
4496 PPC::X7, PPC::X8, PPC::X9, PPC::X10,
4498 static const MCPhysReg *FPR = GetFPR();
4500 static const MCPhysReg VR[] = {
4501 PPC::V2, PPC::V3, PPC::V4, PPC::V5, PPC::V6, PPC::V7, PPC::V8,
4502 PPC::V9, PPC::V10, PPC::V11, PPC::V12, PPC::V13
4504 const unsigned NumGPRs = array_lengthof(GPR_32);
4505 const unsigned NumFPRs = 13;
4506 const unsigned NumVRs = array_lengthof(VR);
4508 const MCPhysReg *GPR = isPPC64 ? GPR_64 : GPR_32;
4510 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
4511 SmallVector<TailCallArgumentInfo, 8> TailCallArguments;
4513 SmallVector<SDValue, 8> MemOpChains;
4514 for (unsigned i = 0; i != NumOps; ++i) {
4515 SDValue Arg = OutVals[i];
4516 ISD::ArgFlagsTy Flags = Outs[i].Flags;
4518 // PtrOff will be used to store the current argument to the stack if a
4519 // register cannot be found for it.
4522 PtrOff = DAG.getConstant(ArgOffset, StackPtr.getValueType());
4524 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr, PtrOff);
4526 // On PPC64, promote integers to 64-bit values.
4527 if (isPPC64 && Arg.getValueType() == MVT::i32) {
4528 // FIXME: Should this use ANY_EXTEND if neither sext nor zext?
4529 unsigned ExtOp = Flags.isSExt() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
4530 Arg = DAG.getNode(ExtOp, dl, MVT::i64, Arg);
4533 // FIXME memcpy is used way more than necessary. Correctness first.
4534 // Note: "by value" is code for passing a structure by value, not
4536 if (Flags.isByVal()) {
4537 unsigned Size = Flags.getByValSize();
4538 // Very small objects are passed right-justified. Everything else is
4539 // passed left-justified.
4540 if (Size==1 || Size==2) {
4541 EVT VT = (Size==1) ? MVT::i8 : MVT::i16;
4542 if (GPR_idx != NumGPRs) {
4543 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, PtrVT, Chain, Arg,
4544 MachinePointerInfo(), VT,
4546 MemOpChains.push_back(Load.getValue(1));
4547 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4549 ArgOffset += PtrByteSize;
4551 SDValue Const = DAG.getConstant(PtrByteSize - Size,
4552 PtrOff.getValueType());
4553 SDValue AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
4554 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
4557 ArgOffset += PtrByteSize;
4561 // Copy entire object into memory. There are cases where gcc-generated
4562 // code assumes it is there, even if it could be put entirely into
4563 // registers. (This is not what the doc says.)
4564 Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
4568 // For small aggregates (Darwin only) and aggregates >= PtrByteSize,
4569 // copy the pieces of the object that fit into registers from the
4570 // parameter save area.
4571 for (unsigned j=0; j<Size; j+=PtrByteSize) {
4572 SDValue Const = DAG.getConstant(j, PtrOff.getValueType());
4573 SDValue AddArg = DAG.getNode(ISD::ADD, dl, PtrVT, Arg, Const);
4574 if (GPR_idx != NumGPRs) {
4575 SDValue Load = DAG.getLoad(PtrVT, dl, Chain, AddArg,
4576 MachinePointerInfo(),
4577 false, false, false, 0);
4578 MemOpChains.push_back(Load.getValue(1));
4579 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4580 ArgOffset += PtrByteSize;
4582 ArgOffset += ((Size - j + PtrByteSize-1)/PtrByteSize)*PtrByteSize;
4589 switch (Arg.getSimpleValueType().SimpleTy) {
4590 default: llvm_unreachable("Unexpected ValueType for argument!");
4594 if (GPR_idx != NumGPRs) {
4595 if (Arg.getValueType() == MVT::i1)
4596 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, PtrVT, Arg);
4598 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
4600 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4601 isPPC64, isTailCall, false, MemOpChains,
4602 TailCallArguments, dl);
4604 ArgOffset += PtrByteSize;
4608 if (FPR_idx != NumFPRs) {
4609 RegsToPass.push_back(std::make_pair(FPR[FPR_idx++], Arg));
4612 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4613 MachinePointerInfo(), false, false, 0);
4614 MemOpChains.push_back(Store);
4616 // Float varargs are always shadowed in available integer registers
4617 if (GPR_idx != NumGPRs) {
4618 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4619 MachinePointerInfo(), false, false,
4621 MemOpChains.push_back(Load.getValue(1));
4622 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4624 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 && !isPPC64){
4625 SDValue ConstFour = DAG.getConstant(4, PtrOff.getValueType());
4626 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, ConstFour);
4627 SDValue Load = DAG.getLoad(PtrVT, dl, Store, PtrOff,
4628 MachinePointerInfo(),
4629 false, false, false, 0);
4630 MemOpChains.push_back(Load.getValue(1));
4631 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4634 // If we have any FPRs remaining, we may also have GPRs remaining.
4635 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
4637 if (GPR_idx != NumGPRs)
4639 if (GPR_idx != NumGPRs && Arg.getValueType() == MVT::f64 &&
4640 !isPPC64) // PPC64 has 64-bit GPR's obviously :)
4644 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4645 isPPC64, isTailCall, false, MemOpChains,
4646 TailCallArguments, dl);
4650 ArgOffset += Arg.getValueType() == MVT::f32 ? 4 : 8;
4657 // These go aligned on the stack, or in the corresponding R registers
4658 // when within range. The Darwin PPC ABI doc claims they also go in
4659 // V registers; in fact gcc does this only for arguments that are
4660 // prototyped, not for those that match the ... We do it for all
4661 // arguments, seems to work.
4662 while (ArgOffset % 16 !=0) {
4663 ArgOffset += PtrByteSize;
4664 if (GPR_idx != NumGPRs)
4667 // We could elide this store in the case where the object fits
4668 // entirely in R registers. Maybe later.
4669 PtrOff = DAG.getNode(ISD::ADD, dl, PtrVT, StackPtr,
4670 DAG.getConstant(ArgOffset, PtrVT));
4671 SDValue Store = DAG.getStore(Chain, dl, Arg, PtrOff,
4672 MachinePointerInfo(), false, false, 0);
4673 MemOpChains.push_back(Store);
4674 if (VR_idx != NumVRs) {
4675 SDValue Load = DAG.getLoad(MVT::v4f32, dl, Store, PtrOff,
4676 MachinePointerInfo(),
4677 false, false, false, 0);
4678 MemOpChains.push_back(Load.getValue(1));
4679 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Load));
4682 for (unsigned i=0; i<16; i+=PtrByteSize) {
4683 if (GPR_idx == NumGPRs)
4685 SDValue Ix = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff,
4686 DAG.getConstant(i, PtrVT));
4687 SDValue Load = DAG.getLoad(PtrVT, dl, Store, Ix, MachinePointerInfo(),
4688 false, false, false, 0);
4689 MemOpChains.push_back(Load.getValue(1));
4690 RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Load));
4695 // Non-varargs Altivec params generally go in registers, but have
4696 // stack space allocated at the end.
4697 if (VR_idx != NumVRs) {
4698 // Doesn't have GPR space allocated.
4699 RegsToPass.push_back(std::make_pair(VR[VR_idx++], Arg));
4700 } else if (nAltivecParamsAtEnd==0) {
4701 // We are emitting Altivec params in order.
4702 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4703 isPPC64, isTailCall, true, MemOpChains,
4704 TailCallArguments, dl);
4710 // If all Altivec parameters fit in registers, as they usually do,
4711 // they get stack space following the non-Altivec parameters. We
4712 // don't track this here because nobody below needs it.
4713 // If there are more Altivec parameters than fit in registers emit
4715 if (!isVarArg && nAltivecParamsAtEnd > NumVRs) {
4717 // Offset is aligned; skip 1st 12 params which go in V registers.
4718 ArgOffset = ((ArgOffset+15)/16)*16;
4720 for (unsigned i = 0; i != NumOps; ++i) {
4721 SDValue Arg = OutVals[i];
4722 EVT ArgType = Outs[i].VT;
4723 if (ArgType==MVT::v4f32 || ArgType==MVT::v4i32 ||
4724 ArgType==MVT::v8i16 || ArgType==MVT::v16i8) {
4727 // We are emitting Altivec params in order.
4728 LowerMemOpCallTo(DAG, MF, Chain, Arg, PtrOff, SPDiff, ArgOffset,
4729 isPPC64, isTailCall, true, MemOpChains,
4730 TailCallArguments, dl);
4737 if (!MemOpChains.empty())
4738 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
4740 // On Darwin, R12 must contain the address of an indirect callee. This does
4741 // not mean the MTCTR instruction must use R12; it's easier to model this as
4742 // an extra parameter, so do that.
4744 !dyn_cast<GlobalAddressSDNode>(Callee) &&
4745 !dyn_cast<ExternalSymbolSDNode>(Callee) &&
4746 !isBLACompatibleAddress(Callee, DAG))
4747 RegsToPass.push_back(std::make_pair((unsigned)(isPPC64 ? PPC::X12 :
4748 PPC::R12), Callee));
4750 // Build a sequence of copy-to-reg nodes chained together with token chain
4751 // and flag operands which copy the outgoing args into the appropriate regs.
4753 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
4754 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
4755 RegsToPass[i].second, InFlag);
4756 InFlag = Chain.getValue(1);
4760 PrepareTailCall(DAG, InFlag, Chain, dl, isPPC64, SPDiff, NumBytes, LROp,
4761 FPOp, true, TailCallArguments);
4763 return FinishCall(CallConv, dl, isTailCall, isVarArg, DAG,
4764 RegsToPass, InFlag, Chain, Callee, SPDiff, NumBytes,
4769 PPCTargetLowering::CanLowerReturn(CallingConv::ID CallConv,
4770 MachineFunction &MF, bool isVarArg,
4771 const SmallVectorImpl<ISD::OutputArg> &Outs,
4772 LLVMContext &Context) const {
4773 SmallVector<CCValAssign, 16> RVLocs;
4774 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(),
4776 return CCInfo.CheckReturn(Outs, RetCC_PPC);
4780 PPCTargetLowering::LowerReturn(SDValue Chain,
4781 CallingConv::ID CallConv, bool isVarArg,
4782 const SmallVectorImpl<ISD::OutputArg> &Outs,
4783 const SmallVectorImpl<SDValue> &OutVals,
4784 SDLoc dl, SelectionDAG &DAG) const {
4786 SmallVector<CCValAssign, 16> RVLocs;
4787 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(),
4788 getTargetMachine(), RVLocs, *DAG.getContext());
4789 CCInfo.AnalyzeReturn(Outs, RetCC_PPC);
4792 SmallVector<SDValue, 4> RetOps(1, Chain);
4794 // Copy the result values into the output registers.
4795 for (unsigned i = 0; i != RVLocs.size(); ++i) {
4796 CCValAssign &VA = RVLocs[i];
4797 assert(VA.isRegLoc() && "Can only return in registers!");
4799 SDValue Arg = OutVals[i];
4801 switch (VA.getLocInfo()) {
4802 default: llvm_unreachable("Unknown loc info!");
4803 case CCValAssign::Full: break;
4804 case CCValAssign::AExt:
4805 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
4807 case CCValAssign::ZExt:
4808 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
4810 case CCValAssign::SExt:
4811 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
4815 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), Arg, Flag);
4816 Flag = Chain.getValue(1);
4817 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
4820 RetOps[0] = Chain; // Update chain.
4822 // Add the flag if we have it.
4824 RetOps.push_back(Flag);
4826 return DAG.getNode(PPCISD::RET_FLAG, dl, MVT::Other, RetOps);
4829 SDValue PPCTargetLowering::LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
4830 const PPCSubtarget &Subtarget) const {
4831 // When we pop the dynamic allocation we need to restore the SP link.
4834 // Get the corect type for pointers.
4835 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4837 // Construct the stack pointer operand.
4838 bool isPPC64 = Subtarget.isPPC64();
4839 unsigned SP = isPPC64 ? PPC::X1 : PPC::R1;
4840 SDValue StackPtr = DAG.getRegister(SP, PtrVT);
4842 // Get the operands for the STACKRESTORE.
4843 SDValue Chain = Op.getOperand(0);
4844 SDValue SaveSP = Op.getOperand(1);
4846 // Load the old link SP.
4847 SDValue LoadLinkSP = DAG.getLoad(PtrVT, dl, Chain, StackPtr,
4848 MachinePointerInfo(),
4849 false, false, false, 0);
4851 // Restore the stack pointer.
4852 Chain = DAG.getCopyToReg(LoadLinkSP.getValue(1), dl, SP, SaveSP);
4854 // Store the old link SP.
4855 return DAG.getStore(Chain, dl, LoadLinkSP, StackPtr, MachinePointerInfo(),
4862 PPCTargetLowering::getReturnAddrFrameIndex(SelectionDAG & DAG) const {
4863 MachineFunction &MF = DAG.getMachineFunction();
4864 bool isPPC64 = Subtarget.isPPC64();
4865 bool isDarwinABI = Subtarget.isDarwinABI();
4866 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4868 // Get current frame pointer save index. The users of this index will be
4869 // primarily DYNALLOC instructions.
4870 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4871 int RASI = FI->getReturnAddrSaveIndex();
4873 // If the frame pointer save index hasn't been defined yet.
4875 // Find out what the fix offset of the frame pointer save area.
4876 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
4877 // Allocate the frame index for frame pointer save area.
4878 RASI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, LROffset, true);
4880 FI->setReturnAddrSaveIndex(RASI);
4882 return DAG.getFrameIndex(RASI, PtrVT);
4886 PPCTargetLowering::getFramePointerFrameIndex(SelectionDAG & DAG) const {
4887 MachineFunction &MF = DAG.getMachineFunction();
4888 bool isPPC64 = Subtarget.isPPC64();
4889 bool isDarwinABI = Subtarget.isDarwinABI();
4890 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4892 // Get current frame pointer save index. The users of this index will be
4893 // primarily DYNALLOC instructions.
4894 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
4895 int FPSI = FI->getFramePointerSaveIndex();
4897 // If the frame pointer save index hasn't been defined yet.
4899 // Find out what the fix offset of the frame pointer save area.
4900 int FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64,
4903 // Allocate the frame index for frame pointer save area.
4904 FPSI = MF.getFrameInfo()->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
4906 FI->setFramePointerSaveIndex(FPSI);
4908 return DAG.getFrameIndex(FPSI, PtrVT);
4911 SDValue PPCTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
4913 const PPCSubtarget &Subtarget) const {
4915 SDValue Chain = Op.getOperand(0);
4916 SDValue Size = Op.getOperand(1);
4919 // Get the corect type for pointers.
4920 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
4922 SDValue NegSize = DAG.getNode(ISD::SUB, dl, PtrVT,
4923 DAG.getConstant(0, PtrVT), Size);
4924 // Construct a node for the frame pointer save index.
4925 SDValue FPSIdx = getFramePointerFrameIndex(DAG);
4926 // Build a DYNALLOC node.
4927 SDValue Ops[3] = { Chain, NegSize, FPSIdx };
4928 SDVTList VTs = DAG.getVTList(PtrVT, MVT::Other);
4929 return DAG.getNode(PPCISD::DYNALLOC, dl, VTs, Ops);
4932 SDValue PPCTargetLowering::lowerEH_SJLJ_SETJMP(SDValue Op,
4933 SelectionDAG &DAG) const {
4935 return DAG.getNode(PPCISD::EH_SJLJ_SETJMP, DL,
4936 DAG.getVTList(MVT::i32, MVT::Other),
4937 Op.getOperand(0), Op.getOperand(1));
4940 SDValue PPCTargetLowering::lowerEH_SJLJ_LONGJMP(SDValue Op,
4941 SelectionDAG &DAG) const {
4943 return DAG.getNode(PPCISD::EH_SJLJ_LONGJMP, DL, MVT::Other,
4944 Op.getOperand(0), Op.getOperand(1));
4947 SDValue PPCTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
4948 assert(Op.getValueType() == MVT::i1 &&
4949 "Custom lowering only for i1 loads");
4951 // First, load 8 bits into 32 bits, then truncate to 1 bit.
4954 LoadSDNode *LD = cast<LoadSDNode>(Op);
4956 SDValue Chain = LD->getChain();
4957 SDValue BasePtr = LD->getBasePtr();
4958 MachineMemOperand *MMO = LD->getMemOperand();
4960 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, dl, getPointerTy(), Chain,
4961 BasePtr, MVT::i8, MMO);
4962 SDValue Result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, NewLD);
4964 SDValue Ops[] = { Result, SDValue(NewLD.getNode(), 1) };
4965 return DAG.getMergeValues(Ops, dl);
4968 SDValue PPCTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
4969 assert(Op.getOperand(1).getValueType() == MVT::i1 &&
4970 "Custom lowering only for i1 stores");
4972 // First, zero extend to 32 bits, then use a truncating store to 8 bits.
4975 StoreSDNode *ST = cast<StoreSDNode>(Op);
4977 SDValue Chain = ST->getChain();
4978 SDValue BasePtr = ST->getBasePtr();
4979 SDValue Value = ST->getValue();
4980 MachineMemOperand *MMO = ST->getMemOperand();
4982 Value = DAG.getNode(ISD::ZERO_EXTEND, dl, getPointerTy(), Value);
4983 return DAG.getTruncStore(Chain, dl, Value, BasePtr, MVT::i8, MMO);
4986 // FIXME: Remove this once the ANDI glue bug is fixed:
4987 SDValue PPCTargetLowering::LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const {
4988 assert(Op.getValueType() == MVT::i1 &&
4989 "Custom lowering only for i1 results");
4992 return DAG.getNode(PPCISD::ANDIo_1_GT_BIT, DL, MVT::i1,
4996 /// LowerSELECT_CC - Lower floating point select_cc's into fsel instruction when
4998 SDValue PPCTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const {
4999 // Not FP? Not a fsel.
5000 if (!Op.getOperand(0).getValueType().isFloatingPoint() ||
5001 !Op.getOperand(2).getValueType().isFloatingPoint())
5004 // We might be able to do better than this under some circumstances, but in
5005 // general, fsel-based lowering of select is a finite-math-only optimization.
5006 // For more information, see section F.3 of the 2.06 ISA specification.
5007 if (!DAG.getTarget().Options.NoInfsFPMath ||
5008 !DAG.getTarget().Options.NoNaNsFPMath)
5011 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
5013 EVT ResVT = Op.getValueType();
5014 EVT CmpVT = Op.getOperand(0).getValueType();
5015 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
5016 SDValue TV = Op.getOperand(2), FV = Op.getOperand(3);
5019 // If the RHS of the comparison is a 0.0, we don't need to do the
5020 // subtraction at all.
5022 if (isFloatingPointZero(RHS))
5024 default: break; // SETUO etc aren't handled by fsel.
5028 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5029 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5030 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5031 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5032 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5033 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5034 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), Sel1, FV);
5037 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5040 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5041 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5042 return DAG.getNode(PPCISD::FSEL, dl, ResVT, LHS, TV, FV);
5045 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
5048 if (LHS.getValueType() == MVT::f32) // Comparison is always 64-bits
5049 LHS = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, LHS);
5050 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5051 DAG.getNode(ISD::FNEG, dl, MVT::f64, LHS), TV, FV);
5056 default: break; // SETUO etc aren't handled by fsel.
5060 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5061 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5062 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5063 Sel1 = DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5064 if (Sel1.getValueType() == MVT::f32) // Comparison is always 64-bits
5065 Sel1 = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Sel1);
5066 return DAG.getNode(PPCISD::FSEL, dl, ResVT,
5067 DAG.getNode(ISD::FNEG, dl, MVT::f64, Cmp), Sel1, FV);
5070 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5071 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5072 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5073 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5076 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, LHS, RHS);
5077 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5078 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5079 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5082 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5083 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5084 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5085 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, FV, TV);
5088 Cmp = DAG.getNode(ISD::FSUB, dl, CmpVT, RHS, LHS);
5089 if (Cmp.getValueType() == MVT::f32) // Comparison is always 64-bits
5090 Cmp = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Cmp);
5091 return DAG.getNode(PPCISD::FSEL, dl, ResVT, Cmp, TV, FV);
5096 // FIXME: Split this code up when LegalizeDAGTypes lands.
5097 SDValue PPCTargetLowering::LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG,
5099 assert(Op.getOperand(0).getValueType().isFloatingPoint());
5100 SDValue Src = Op.getOperand(0);
5101 if (Src.getValueType() == MVT::f32)
5102 Src = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Src);
5105 switch (Op.getSimpleValueType().SimpleTy) {
5106 default: llvm_unreachable("Unhandled FP_TO_INT type in custom expander!");
5108 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIWZ :
5109 (Subtarget.hasFPCVT() ? PPCISD::FCTIWUZ :
5114 assert((Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT()) &&
5115 "i64 FP_TO_UINT is supported only with FPCVT");
5116 Tmp = DAG.getNode(Op.getOpcode()==ISD::FP_TO_SINT ? PPCISD::FCTIDZ :
5122 // Convert the FP value to an int value through memory.
5123 bool i32Stack = Op.getValueType() == MVT::i32 && Subtarget.hasSTFIWX() &&
5124 (Op.getOpcode() == ISD::FP_TO_SINT || Subtarget.hasFPCVT());
5125 SDValue FIPtr = DAG.CreateStackTemporary(i32Stack ? MVT::i32 : MVT::f64);
5126 int FI = cast<FrameIndexSDNode>(FIPtr)->getIndex();
5127 MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(FI);
5129 // Emit a store to the stack slot.
5132 MachineFunction &MF = DAG.getMachineFunction();
5133 MachineMemOperand *MMO =
5134 MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, 4);
5135 SDValue Ops[] = { DAG.getEntryNode(), Tmp, FIPtr };
5136 Chain = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
5137 DAG.getVTList(MVT::Other), Ops, MVT::i32, MMO);
5139 Chain = DAG.getStore(DAG.getEntryNode(), dl, Tmp, FIPtr,
5140 MPI, false, false, 0);
5142 // Result is a load from the stack slot. If loading 4 bytes, make sure to
5144 if (Op.getValueType() == MVT::i32 && !i32Stack) {
5145 FIPtr = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr,
5146 DAG.getConstant(4, FIPtr.getValueType()));
5147 MPI = MachinePointerInfo();
5150 return DAG.getLoad(Op.getValueType(), dl, Chain, FIPtr, MPI,
5151 false, false, false, 0);
5154 SDValue PPCTargetLowering::LowerINT_TO_FP(SDValue Op,
5155 SelectionDAG &DAG) const {
5157 // Don't handle ppc_fp128 here; let it be lowered to a libcall.
5158 if (Op.getValueType() != MVT::f32 && Op.getValueType() != MVT::f64)
5161 if (Op.getOperand(0).getValueType() == MVT::i1)
5162 return DAG.getNode(ISD::SELECT, dl, Op.getValueType(), Op.getOperand(0),
5163 DAG.getConstantFP(1.0, Op.getValueType()),
5164 DAG.getConstantFP(0.0, Op.getValueType()));
5166 assert((Op.getOpcode() == ISD::SINT_TO_FP || Subtarget.hasFPCVT()) &&
5167 "UINT_TO_FP is supported only with FPCVT");
5169 // If we have FCFIDS, then use it when converting to single-precision.
5170 // Otherwise, convert to double-precision and then round.
5171 unsigned FCFOp = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5172 (Op.getOpcode() == ISD::UINT_TO_FP ?
5173 PPCISD::FCFIDUS : PPCISD::FCFIDS) :
5174 (Op.getOpcode() == ISD::UINT_TO_FP ?
5175 PPCISD::FCFIDU : PPCISD::FCFID);
5176 MVT FCFTy = (Subtarget.hasFPCVT() && Op.getValueType() == MVT::f32) ?
5177 MVT::f32 : MVT::f64;
5179 if (Op.getOperand(0).getValueType() == MVT::i64) {
5180 SDValue SINT = Op.getOperand(0);
5181 // When converting to single-precision, we actually need to convert
5182 // to double-precision first and then round to single-precision.
5183 // To avoid double-rounding effects during that operation, we have
5184 // to prepare the input operand. Bits that might be truncated when
5185 // converting to double-precision are replaced by a bit that won't
5186 // be lost at this stage, but is below the single-precision rounding
5189 // However, if -enable-unsafe-fp-math is in effect, accept double
5190 // rounding to avoid the extra overhead.
5191 if (Op.getValueType() == MVT::f32 &&
5192 !Subtarget.hasFPCVT() &&
5193 !DAG.getTarget().Options.UnsafeFPMath) {
5195 // Twiddle input to make sure the low 11 bits are zero. (If this
5196 // is the case, we are guaranteed the value will fit into the 53 bit
5197 // mantissa of an IEEE double-precision value without rounding.)
5198 // If any of those low 11 bits were not zero originally, make sure
5199 // bit 12 (value 2048) is set instead, so that the final rounding
5200 // to single-precision gets the correct result.
5201 SDValue Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5202 SINT, DAG.getConstant(2047, MVT::i64));
5203 Round = DAG.getNode(ISD::ADD, dl, MVT::i64,
5204 Round, DAG.getConstant(2047, MVT::i64));
5205 Round = DAG.getNode(ISD::OR, dl, MVT::i64, Round, SINT);
5206 Round = DAG.getNode(ISD::AND, dl, MVT::i64,
5207 Round, DAG.getConstant(-2048, MVT::i64));
5209 // However, we cannot use that value unconditionally: if the magnitude
5210 // of the input value is small, the bit-twiddling we did above might
5211 // end up visibly changing the output. Fortunately, in that case, we
5212 // don't need to twiddle bits since the original input will convert
5213 // exactly to double-precision floating-point already. Therefore,
5214 // construct a conditional to use the original value if the top 11
5215 // bits are all sign-bit copies, and use the rounded value computed
5217 SDValue Cond = DAG.getNode(ISD::SRA, dl, MVT::i64,
5218 SINT, DAG.getConstant(53, MVT::i32));
5219 Cond = DAG.getNode(ISD::ADD, dl, MVT::i64,
5220 Cond, DAG.getConstant(1, MVT::i64));
5221 Cond = DAG.getSetCC(dl, MVT::i32,
5222 Cond, DAG.getConstant(1, MVT::i64), ISD::SETUGT);
5224 SINT = DAG.getNode(ISD::SELECT, dl, MVT::i64, Cond, Round, SINT);
5227 SDValue Bits = DAG.getNode(ISD::BITCAST, dl, MVT::f64, SINT);
5228 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Bits);
5230 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5231 FP = DAG.getNode(ISD::FP_ROUND, dl,
5232 MVT::f32, FP, DAG.getIntPtrConstant(0));
5236 assert(Op.getOperand(0).getValueType() == MVT::i32 &&
5237 "Unhandled INT_TO_FP type in custom expander!");
5238 // Since we only generate this in 64-bit mode, we can take advantage of
5239 // 64-bit registers. In particular, sign extend the input value into the
5240 // 64-bit register with extsw, store the WHOLE 64-bit value into the stack
5241 // then lfd it and fcfid it.
5242 MachineFunction &MF = DAG.getMachineFunction();
5243 MachineFrameInfo *FrameInfo = MF.getFrameInfo();
5244 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5247 if (Subtarget.hasLFIWAX() || Subtarget.hasFPCVT()) {
5248 int FrameIdx = FrameInfo->CreateStackObject(4, 4, false);
5249 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5251 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), FIdx,
5252 MachinePointerInfo::getFixedStack(FrameIdx),
5255 assert(cast<StoreSDNode>(Store)->getMemoryVT() == MVT::i32 &&
5256 "Expected an i32 store");
5257 MachineMemOperand *MMO =
5258 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
5259 MachineMemOperand::MOLoad, 4, 4);
5260 SDValue Ops[] = { Store, FIdx };
5261 Ld = DAG.getMemIntrinsicNode(Op.getOpcode() == ISD::UINT_TO_FP ?
5262 PPCISD::LFIWZX : PPCISD::LFIWAX,
5263 dl, DAG.getVTList(MVT::f64, MVT::Other),
5264 Ops, MVT::i32, MMO);
5266 assert(Subtarget.isPPC64() &&
5267 "i32->FP without LFIWAX supported only on PPC64");
5269 int FrameIdx = FrameInfo->CreateStackObject(8, 8, false);
5270 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
5272 SDValue Ext64 = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i64,
5275 // STD the extended value into the stack slot.
5276 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Ext64, FIdx,
5277 MachinePointerInfo::getFixedStack(FrameIdx),
5280 // Load the value as a double.
5281 Ld = DAG.getLoad(MVT::f64, dl, Store, FIdx,
5282 MachinePointerInfo::getFixedStack(FrameIdx),
5283 false, false, false, 0);
5286 // FCFID it and return it.
5287 SDValue FP = DAG.getNode(FCFOp, dl, FCFTy, Ld);
5288 if (Op.getValueType() == MVT::f32 && !Subtarget.hasFPCVT())
5289 FP = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, FP, DAG.getIntPtrConstant(0));
5293 SDValue PPCTargetLowering::LowerFLT_ROUNDS_(SDValue Op,
5294 SelectionDAG &DAG) const {
5297 The rounding mode is in bits 30:31 of FPSR, and has the following
5304 FLT_ROUNDS, on the other hand, expects the following:
5311 To perform the conversion, we do:
5312 ((FPSCR & 0x3) ^ ((~FPSCR & 0x3) >> 1))
5315 MachineFunction &MF = DAG.getMachineFunction();
5316 EVT VT = Op.getValueType();
5317 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
5319 // Save FP Control Word to register
5321 MVT::f64, // return register
5322 MVT::Glue // unused in this context
5324 SDValue Chain = DAG.getNode(PPCISD::MFFS, dl, NodeTys, None);
5326 // Save FP register to stack slot
5327 int SSFI = MF.getFrameInfo()->CreateStackObject(8, 8, false);
5328 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
5329 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Chain,
5330 StackSlot, MachinePointerInfo(), false, false,0);
5332 // Load FP Control Word from low 32 bits of stack slot.
5333 SDValue Four = DAG.getConstant(4, PtrVT);
5334 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);
5335 SDValue CWD = DAG.getLoad(MVT::i32, dl, Store, Addr, MachinePointerInfo(),
5336 false, false, false, 0);
5338 // Transform as necessary
5340 DAG.getNode(ISD::AND, dl, MVT::i32,
5341 CWD, DAG.getConstant(3, MVT::i32));
5343 DAG.getNode(ISD::SRL, dl, MVT::i32,
5344 DAG.getNode(ISD::AND, dl, MVT::i32,
5345 DAG.getNode(ISD::XOR, dl, MVT::i32,
5346 CWD, DAG.getConstant(3, MVT::i32)),
5347 DAG.getConstant(3, MVT::i32)),
5348 DAG.getConstant(1, MVT::i32));
5351 DAG.getNode(ISD::XOR, dl, MVT::i32, CWD1, CWD2);
5353 return DAG.getNode((VT.getSizeInBits() < 16 ?
5354 ISD::TRUNCATE : ISD::ZERO_EXTEND), dl, VT, RetVal);
5357 SDValue PPCTargetLowering::LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5358 EVT VT = Op.getValueType();
5359 unsigned BitWidth = VT.getSizeInBits();
5361 assert(Op.getNumOperands() == 3 &&
5362 VT == Op.getOperand(1).getValueType() &&
5365 // Expand into a bunch of logical ops. Note that these ops
5366 // depend on the PPC behavior for oversized shift amounts.
5367 SDValue Lo = Op.getOperand(0);
5368 SDValue Hi = Op.getOperand(1);
5369 SDValue Amt = Op.getOperand(2);
5370 EVT AmtVT = Amt.getValueType();
5372 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5373 DAG.getConstant(BitWidth, AmtVT), Amt);
5374 SDValue Tmp2 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Amt);
5375 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5376 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
5377 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5378 DAG.getConstant(-BitWidth, AmtVT));
5379 SDValue Tmp6 = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Tmp5);
5380 SDValue OutHi = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5381 SDValue OutLo = DAG.getNode(PPCISD::SHL, dl, VT, Lo, Amt);
5382 SDValue OutOps[] = { OutLo, OutHi };
5383 return DAG.getMergeValues(OutOps, dl);
5386 SDValue PPCTargetLowering::LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const {
5387 EVT VT = Op.getValueType();
5389 unsigned BitWidth = VT.getSizeInBits();
5390 assert(Op.getNumOperands() == 3 &&
5391 VT == Op.getOperand(1).getValueType() &&
5394 // Expand into a bunch of logical ops. Note that these ops
5395 // depend on the PPC behavior for oversized shift amounts.
5396 SDValue Lo = Op.getOperand(0);
5397 SDValue Hi = Op.getOperand(1);
5398 SDValue Amt = Op.getOperand(2);
5399 EVT AmtVT = Amt.getValueType();
5401 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5402 DAG.getConstant(BitWidth, AmtVT), Amt);
5403 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5404 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5405 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5406 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5407 DAG.getConstant(-BitWidth, AmtVT));
5408 SDValue Tmp6 = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Tmp5);
5409 SDValue OutLo = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp6);
5410 SDValue OutHi = DAG.getNode(PPCISD::SRL, dl, VT, Hi, Amt);
5411 SDValue OutOps[] = { OutLo, OutHi };
5412 return DAG.getMergeValues(OutOps, dl);
5415 SDValue PPCTargetLowering::LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const {
5417 EVT VT = Op.getValueType();
5418 unsigned BitWidth = VT.getSizeInBits();
5419 assert(Op.getNumOperands() == 3 &&
5420 VT == Op.getOperand(1).getValueType() &&
5423 // Expand into a bunch of logical ops, followed by a select_cc.
5424 SDValue Lo = Op.getOperand(0);
5425 SDValue Hi = Op.getOperand(1);
5426 SDValue Amt = Op.getOperand(2);
5427 EVT AmtVT = Amt.getValueType();
5429 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT,
5430 DAG.getConstant(BitWidth, AmtVT), Amt);
5431 SDValue Tmp2 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Amt);
5432 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5433 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
5434 SDValue Tmp5 = DAG.getNode(ISD::ADD, dl, AmtVT, Amt,
5435 DAG.getConstant(-BitWidth, AmtVT));
5436 SDValue Tmp6 = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Tmp5);
5437 SDValue OutHi = DAG.getNode(PPCISD::SRA, dl, VT, Hi, Amt);
5438 SDValue OutLo = DAG.getSelectCC(dl, Tmp5, DAG.getConstant(0, AmtVT),
5439 Tmp4, Tmp6, ISD::SETLE);
5440 SDValue OutOps[] = { OutLo, OutHi };
5441 return DAG.getMergeValues(OutOps, dl);
5444 //===----------------------------------------------------------------------===//
5445 // Vector related lowering.
5448 /// BuildSplatI - Build a canonical splati of Val with an element size of
5449 /// SplatSize. Cast the result to VT.
5450 static SDValue BuildSplatI(int Val, unsigned SplatSize, EVT VT,
5451 SelectionDAG &DAG, SDLoc dl) {
5452 assert(Val >= -16 && Val <= 15 && "vsplti is out of range!");
5454 static const EVT VTys[] = { // canonical VT to use for each size.
5455 MVT::v16i8, MVT::v8i16, MVT::Other, MVT::v4i32
5458 EVT ReqVT = VT != MVT::Other ? VT : VTys[SplatSize-1];
5460 // Force vspltis[hw] -1 to vspltisb -1 to canonicalize.
5464 EVT CanonicalVT = VTys[SplatSize-1];
5466 // Build a canonical splat for this value.
5467 SDValue Elt = DAG.getConstant(Val, MVT::i32);
5468 SmallVector<SDValue, 8> Ops;
5469 Ops.assign(CanonicalVT.getVectorNumElements(), Elt);
5470 SDValue Res = DAG.getNode(ISD::BUILD_VECTOR, dl, CanonicalVT, Ops);
5471 return DAG.getNode(ISD::BITCAST, dl, ReqVT, Res);
5474 /// BuildIntrinsicOp - Return a unary operator intrinsic node with the
5475 /// specified intrinsic ID.
5476 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op,
5477 SelectionDAG &DAG, SDLoc dl,
5478 EVT DestVT = MVT::Other) {
5479 if (DestVT == MVT::Other) DestVT = Op.getValueType();
5480 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5481 DAG.getConstant(IID, MVT::i32), Op);
5484 /// BuildIntrinsicOp - Return a binary operator intrinsic node with the
5485 /// specified intrinsic ID.
5486 static SDValue BuildIntrinsicOp(unsigned IID, SDValue LHS, SDValue RHS,
5487 SelectionDAG &DAG, SDLoc dl,
5488 EVT DestVT = MVT::Other) {
5489 if (DestVT == MVT::Other) DestVT = LHS.getValueType();
5490 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5491 DAG.getConstant(IID, MVT::i32), LHS, RHS);
5494 /// BuildIntrinsicOp - Return a ternary operator intrinsic node with the
5495 /// specified intrinsic ID.
5496 static SDValue BuildIntrinsicOp(unsigned IID, SDValue Op0, SDValue Op1,
5497 SDValue Op2, SelectionDAG &DAG,
5498 SDLoc dl, EVT DestVT = MVT::Other) {
5499 if (DestVT == MVT::Other) DestVT = Op0.getValueType();
5500 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT,
5501 DAG.getConstant(IID, MVT::i32), Op0, Op1, Op2);
5505 /// BuildVSLDOI - Return a VECTOR_SHUFFLE that is a vsldoi of the specified
5506 /// amount. The result has the specified value type.
5507 static SDValue BuildVSLDOI(SDValue LHS, SDValue RHS, unsigned Amt,
5508 EVT VT, SelectionDAG &DAG, SDLoc dl) {
5509 // Force LHS/RHS to be the right type.
5510 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, LHS);
5511 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, RHS);
5514 for (unsigned i = 0; i != 16; ++i)
5516 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, LHS, RHS, Ops);
5517 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5520 // If this is a case we can't handle, return null and let the default
5521 // expansion code take care of it. If we CAN select this case, and if it
5522 // selects to a single instruction, return Op. Otherwise, if we can codegen
5523 // this case more efficiently than a constant pool load, lower it to the
5524 // sequence of ops that should be used.
5525 SDValue PPCTargetLowering::LowerBUILD_VECTOR(SDValue Op,
5526 SelectionDAG &DAG) const {
5528 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(Op.getNode());
5529 assert(BVN && "Expected a BuildVectorSDNode in LowerBUILD_VECTOR");
5531 // Check if this is a splat of a constant value.
5532 APInt APSplatBits, APSplatUndef;
5533 unsigned SplatBitSize;
5535 if (! BVN->isConstantSplat(APSplatBits, APSplatUndef, SplatBitSize,
5536 HasAnyUndefs, 0, true) || SplatBitSize > 32)
5539 unsigned SplatBits = APSplatBits.getZExtValue();
5540 unsigned SplatUndef = APSplatUndef.getZExtValue();
5541 unsigned SplatSize = SplatBitSize / 8;
5543 // First, handle single instruction cases.
5546 if (SplatBits == 0) {
5547 // Canonicalize all zero vectors to be v4i32.
5548 if (Op.getValueType() != MVT::v4i32 || HasAnyUndefs) {
5549 SDValue Z = DAG.getConstant(0, MVT::i32);
5550 Z = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Z, Z, Z, Z);
5551 Op = DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Z);
5556 // If the sign extended value is in the range [-16,15], use VSPLTI[bhw].
5557 int32_t SextVal= (int32_t(SplatBits << (32-SplatBitSize)) >>
5559 if (SextVal >= -16 && SextVal <= 15)
5560 return BuildSplatI(SextVal, SplatSize, Op.getValueType(), DAG, dl);
5563 // Two instruction sequences.
5565 // If this value is in the range [-32,30] and is even, use:
5566 // VSPLTI[bhw](val/2) + VSPLTI[bhw](val/2)
5567 // If this value is in the range [17,31] and is odd, use:
5568 // VSPLTI[bhw](val-16) - VSPLTI[bhw](-16)
5569 // If this value is in the range [-31,-17] and is odd, use:
5570 // VSPLTI[bhw](val+16) + VSPLTI[bhw](-16)
5571 // Note the last two are three-instruction sequences.
5572 if (SextVal >= -32 && SextVal <= 31) {
5573 // To avoid having these optimizations undone by constant folding,
5574 // we convert to a pseudo that will be expanded later into one of
5576 SDValue Elt = DAG.getConstant(SextVal, MVT::i32);
5577 EVT VT = (SplatSize == 1 ? MVT::v16i8 :
5578 (SplatSize == 2 ? MVT::v8i16 : MVT::v4i32));
5579 SDValue EltSize = DAG.getConstant(SplatSize, MVT::i32);
5580 SDValue RetVal = DAG.getNode(PPCISD::VADD_SPLAT, dl, VT, Elt, EltSize);
5581 if (VT == Op.getValueType())
5584 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), RetVal);
5587 // If this is 0x8000_0000 x 4, turn into vspltisw + vslw. If it is
5588 // 0x7FFF_FFFF x 4, turn it into not(0x8000_0000). This is important
5590 if (SplatSize == 4 && SplatBits == (0x7FFFFFFF&~SplatUndef)) {
5591 // Make -1 and vspltisw -1:
5592 SDValue OnesV = BuildSplatI(-1, 4, MVT::v4i32, DAG, dl);
5594 // Make the VSLW intrinsic, computing 0x8000_0000.
5595 SDValue Res = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, OnesV,
5598 // xor by OnesV to invert it.
5599 Res = DAG.getNode(ISD::XOR, dl, MVT::v4i32, Res, OnesV);
5600 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5603 // The remaining cases assume either big endian element order or
5604 // a splat-size that equates to the element size of the vector
5605 // to be built. An example that doesn't work for little endian is
5606 // {0, -1, 0, -1, 0, -1, 0, -1} which has a splat size of 32 bits
5607 // and a vector element size of 16 bits. The code below will
5608 // produce the vector in big endian element order, which for little
5609 // endian is {-1, 0, -1, 0, -1, 0, -1, 0}.
5611 // For now, just avoid these optimizations in that case.
5612 // FIXME: Develop correct optimizations for LE with mismatched
5613 // splat and element sizes.
5615 if (Subtarget.isLittleEndian() &&
5616 SplatSize != Op.getValueType().getVectorElementType().getSizeInBits())
5619 // Check to see if this is a wide variety of vsplti*, binop self cases.
5620 static const signed char SplatCsts[] = {
5621 -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7,
5622 -8, 8, -9, 9, -10, 10, -11, 11, -12, 12, -13, 13, 14, -14, 15, -15, -16
5625 for (unsigned idx = 0; idx < array_lengthof(SplatCsts); ++idx) {
5626 // Indirect through the SplatCsts array so that we favor 'vsplti -1' for
5627 // cases which are ambiguous (e.g. formation of 0x8000_0000). 'vsplti -1'
5628 int i = SplatCsts[idx];
5630 // Figure out what shift amount will be used by altivec if shifted by i in
5632 unsigned TypeShiftAmt = i & (SplatBitSize-1);
5634 // vsplti + shl self.
5635 if (SextVal == (int)((unsigned)i << TypeShiftAmt)) {
5636 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5637 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5638 Intrinsic::ppc_altivec_vslb, Intrinsic::ppc_altivec_vslh, 0,
5639 Intrinsic::ppc_altivec_vslw
5641 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5642 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5645 // vsplti + srl self.
5646 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5647 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5648 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5649 Intrinsic::ppc_altivec_vsrb, Intrinsic::ppc_altivec_vsrh, 0,
5650 Intrinsic::ppc_altivec_vsrw
5652 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5653 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5656 // vsplti + sra self.
5657 if (SextVal == (int)((unsigned)i >> TypeShiftAmt)) {
5658 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5659 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5660 Intrinsic::ppc_altivec_vsrab, Intrinsic::ppc_altivec_vsrah, 0,
5661 Intrinsic::ppc_altivec_vsraw
5663 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5664 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5667 // vsplti + rol self.
5668 if (SextVal == (int)(((unsigned)i << TypeShiftAmt) |
5669 ((unsigned)i >> (SplatBitSize-TypeShiftAmt)))) {
5670 SDValue Res = BuildSplatI(i, SplatSize, MVT::Other, DAG, dl);
5671 static const unsigned IIDs[] = { // Intrinsic to use for each size.
5672 Intrinsic::ppc_altivec_vrlb, Intrinsic::ppc_altivec_vrlh, 0,
5673 Intrinsic::ppc_altivec_vrlw
5675 Res = BuildIntrinsicOp(IIDs[SplatSize-1], Res, Res, DAG, dl);
5676 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Res);
5679 // t = vsplti c, result = vsldoi t, t, 1
5680 if (SextVal == (int)(((unsigned)i << 8) | (i < 0 ? 0xFF : 0))) {
5681 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5682 return BuildVSLDOI(T, T, 1, Op.getValueType(), DAG, dl);
5684 // t = vsplti c, result = vsldoi t, t, 2
5685 if (SextVal == (int)(((unsigned)i << 16) | (i < 0 ? 0xFFFF : 0))) {
5686 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5687 return BuildVSLDOI(T, T, 2, Op.getValueType(), DAG, dl);
5689 // t = vsplti c, result = vsldoi t, t, 3
5690 if (SextVal == (int)(((unsigned)i << 24) | (i < 0 ? 0xFFFFFF : 0))) {
5691 SDValue T = BuildSplatI(i, SplatSize, MVT::v16i8, DAG, dl);
5692 return BuildVSLDOI(T, T, 3, Op.getValueType(), DAG, dl);
5699 /// GeneratePerfectShuffle - Given an entry in the perfect-shuffle table, emit
5700 /// the specified operations to build the shuffle.
5701 static SDValue GeneratePerfectShuffle(unsigned PFEntry, SDValue LHS,
5702 SDValue RHS, SelectionDAG &DAG,
5704 unsigned OpNum = (PFEntry >> 26) & 0x0F;
5705 unsigned LHSID = (PFEntry >> 13) & ((1 << 13)-1);
5706 unsigned RHSID = (PFEntry >> 0) & ((1 << 13)-1);
5709 OP_COPY = 0, // Copy, used for things like <u,u,u,3> to say it is <0,1,2,3>
5721 if (OpNum == OP_COPY) {
5722 if (LHSID == (1*9+2)*9+3) return LHS;
5723 assert(LHSID == ((4*9+5)*9+6)*9+7 && "Illegal OP_COPY!");
5727 SDValue OpLHS, OpRHS;
5728 OpLHS = GeneratePerfectShuffle(PerfectShuffleTable[LHSID], LHS, RHS, DAG, dl);
5729 OpRHS = GeneratePerfectShuffle(PerfectShuffleTable[RHSID], LHS, RHS, DAG, dl);
5733 default: llvm_unreachable("Unknown i32 permute!");
5735 ShufIdxs[ 0] = 0; ShufIdxs[ 1] = 1; ShufIdxs[ 2] = 2; ShufIdxs[ 3] = 3;
5736 ShufIdxs[ 4] = 16; ShufIdxs[ 5] = 17; ShufIdxs[ 6] = 18; ShufIdxs[ 7] = 19;
5737 ShufIdxs[ 8] = 4; ShufIdxs[ 9] = 5; ShufIdxs[10] = 6; ShufIdxs[11] = 7;
5738 ShufIdxs[12] = 20; ShufIdxs[13] = 21; ShufIdxs[14] = 22; ShufIdxs[15] = 23;
5741 ShufIdxs[ 0] = 8; ShufIdxs[ 1] = 9; ShufIdxs[ 2] = 10; ShufIdxs[ 3] = 11;
5742 ShufIdxs[ 4] = 24; ShufIdxs[ 5] = 25; ShufIdxs[ 6] = 26; ShufIdxs[ 7] = 27;
5743 ShufIdxs[ 8] = 12; ShufIdxs[ 9] = 13; ShufIdxs[10] = 14; ShufIdxs[11] = 15;
5744 ShufIdxs[12] = 28; ShufIdxs[13] = 29; ShufIdxs[14] = 30; ShufIdxs[15] = 31;
5747 for (unsigned i = 0; i != 16; ++i)
5748 ShufIdxs[i] = (i&3)+0;
5751 for (unsigned i = 0; i != 16; ++i)
5752 ShufIdxs[i] = (i&3)+4;
5755 for (unsigned i = 0; i != 16; ++i)
5756 ShufIdxs[i] = (i&3)+8;
5759 for (unsigned i = 0; i != 16; ++i)
5760 ShufIdxs[i] = (i&3)+12;
5763 return BuildVSLDOI(OpLHS, OpRHS, 4, OpLHS.getValueType(), DAG, dl);
5765 return BuildVSLDOI(OpLHS, OpRHS, 8, OpLHS.getValueType(), DAG, dl);
5767 return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG, dl);
5769 EVT VT = OpLHS.getValueType();
5770 OpLHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpLHS);
5771 OpRHS = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OpRHS);
5772 SDValue T = DAG.getVectorShuffle(MVT::v16i8, dl, OpLHS, OpRHS, ShufIdxs);
5773 return DAG.getNode(ISD::BITCAST, dl, VT, T);
5776 /// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
5777 /// is a shuffle we can handle in a single instruction, return it. Otherwise,
5778 /// return the code it can be lowered into. Worst case, it can always be
5779 /// lowered into a vperm.
5780 SDValue PPCTargetLowering::LowerVECTOR_SHUFFLE(SDValue Op,
5781 SelectionDAG &DAG) const {
5783 SDValue V1 = Op.getOperand(0);
5784 SDValue V2 = Op.getOperand(1);
5785 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op);
5786 EVT VT = Op.getValueType();
5787 bool isLittleEndian = Subtarget.isLittleEndian();
5789 // Cases that are handled by instructions that take permute immediates
5790 // (such as vsplt*) should be left as VECTOR_SHUFFLE nodes so they can be
5791 // selected by the instruction selector.
5792 if (V2.getOpcode() == ISD::UNDEF) {
5793 if (PPC::isSplatShuffleMask(SVOp, 1) ||
5794 PPC::isSplatShuffleMask(SVOp, 2) ||
5795 PPC::isSplatShuffleMask(SVOp, 4) ||
5796 PPC::isVPKUWUMShuffleMask(SVOp, true, DAG) ||
5797 PPC::isVPKUHUMShuffleMask(SVOp, true, DAG) ||
5798 PPC::isVSLDOIShuffleMask(SVOp, true, DAG) != -1 ||
5799 PPC::isVMRGLShuffleMask(SVOp, 1, true, DAG) ||
5800 PPC::isVMRGLShuffleMask(SVOp, 2, true, DAG) ||
5801 PPC::isVMRGLShuffleMask(SVOp, 4, true, DAG) ||
5802 PPC::isVMRGHShuffleMask(SVOp, 1, true, DAG) ||
5803 PPC::isVMRGHShuffleMask(SVOp, 2, true, DAG) ||
5804 PPC::isVMRGHShuffleMask(SVOp, 4, true, DAG)) {
5809 // Altivec has a variety of "shuffle immediates" that take two vector inputs
5810 // and produce a fixed permutation. If any of these match, do not lower to
5812 if (PPC::isVPKUWUMShuffleMask(SVOp, false, DAG) ||
5813 PPC::isVPKUHUMShuffleMask(SVOp, false, DAG) ||
5814 PPC::isVSLDOIShuffleMask(SVOp, false, DAG) != -1 ||
5815 PPC::isVMRGLShuffleMask(SVOp, 1, false, DAG) ||
5816 PPC::isVMRGLShuffleMask(SVOp, 2, false, DAG) ||
5817 PPC::isVMRGLShuffleMask(SVOp, 4, false, DAG) ||
5818 PPC::isVMRGHShuffleMask(SVOp, 1, false, DAG) ||
5819 PPC::isVMRGHShuffleMask(SVOp, 2, false, DAG) ||
5820 PPC::isVMRGHShuffleMask(SVOp, 4, false, DAG))
5823 // Check to see if this is a shuffle of 4-byte values. If so, we can use our
5824 // perfect shuffle table to emit an optimal matching sequence.
5825 ArrayRef<int> PermMask = SVOp->getMask();
5827 unsigned PFIndexes[4];
5828 bool isFourElementShuffle = true;
5829 for (unsigned i = 0; i != 4 && isFourElementShuffle; ++i) { // Element number
5830 unsigned EltNo = 8; // Start out undef.
5831 for (unsigned j = 0; j != 4; ++j) { // Intra-element byte.
5832 if (PermMask[i*4+j] < 0)
5833 continue; // Undef, ignore it.
5835 unsigned ByteSource = PermMask[i*4+j];
5836 if ((ByteSource & 3) != j) {
5837 isFourElementShuffle = false;
5842 EltNo = ByteSource/4;
5843 } else if (EltNo != ByteSource/4) {
5844 isFourElementShuffle = false;
5848 PFIndexes[i] = EltNo;
5851 // If this shuffle can be expressed as a shuffle of 4-byte elements, use the
5852 // perfect shuffle vector to determine if it is cost effective to do this as
5853 // discrete instructions, or whether we should use a vperm.
5854 // For now, we skip this for little endian until such time as we have a
5855 // little-endian perfect shuffle table.
5856 if (isFourElementShuffle && !isLittleEndian) {
5857 // Compute the index in the perfect shuffle table.
5858 unsigned PFTableIndex =
5859 PFIndexes[0]*9*9*9+PFIndexes[1]*9*9+PFIndexes[2]*9+PFIndexes[3];
5861 unsigned PFEntry = PerfectShuffleTable[PFTableIndex];
5862 unsigned Cost = (PFEntry >> 30);
5864 // Determining when to avoid vperm is tricky. Many things affect the cost
5865 // of vperm, particularly how many times the perm mask needs to be computed.
5866 // For example, if the perm mask can be hoisted out of a loop or is already
5867 // used (perhaps because there are multiple permutes with the same shuffle
5868 // mask?) the vperm has a cost of 1. OTOH, hoisting the permute mask out of
5869 // the loop requires an extra register.
5871 // As a compromise, we only emit discrete instructions if the shuffle can be
5872 // generated in 3 or fewer operations. When we have loop information
5873 // available, if this block is within a loop, we should avoid using vperm
5874 // for 3-operation perms and use a constant pool load instead.
5876 return GeneratePerfectShuffle(PFEntry, V1, V2, DAG, dl);
5879 // Lower this to a VPERM(V1, V2, V3) expression, where V3 is a constant
5880 // vector that will get spilled to the constant pool.
5881 if (V2.getOpcode() == ISD::UNDEF) V2 = V1;
5883 // The SHUFFLE_VECTOR mask is almost exactly what we want for vperm, except
5884 // that it is in input element units, not in bytes. Convert now.
5886 // For little endian, the order of the input vectors is reversed, and
5887 // the permutation mask is complemented with respect to 31. This is
5888 // necessary to produce proper semantics with the big-endian-biased vperm
5890 EVT EltVT = V1.getValueType().getVectorElementType();
5891 unsigned BytesPerElement = EltVT.getSizeInBits()/8;
5893 SmallVector<SDValue, 16> ResultMask;
5894 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) {
5895 unsigned SrcElt = PermMask[i] < 0 ? 0 : PermMask[i];
5897 for (unsigned j = 0; j != BytesPerElement; ++j)
5899 ResultMask.push_back(DAG.getConstant(31 - (SrcElt*BytesPerElement+j),
5902 ResultMask.push_back(DAG.getConstant(SrcElt*BytesPerElement+j,
5906 SDValue VPermMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v16i8,
5909 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5912 return DAG.getNode(PPCISD::VPERM, dl, V1.getValueType(),
5916 /// getAltivecCompareInfo - Given an intrinsic, return false if it is not an
5917 /// altivec comparison. If it is, return true and fill in Opc/isDot with
5918 /// information about the intrinsic.
5919 static bool getAltivecCompareInfo(SDValue Intrin, int &CompareOpc,
5921 unsigned IntrinsicID =
5922 cast<ConstantSDNode>(Intrin.getOperand(0))->getZExtValue();
5925 switch (IntrinsicID) {
5926 default: return false;
5927 // Comparison predicates.
5928 case Intrinsic::ppc_altivec_vcmpbfp_p: CompareOpc = 966; isDot = 1; break;
5929 case Intrinsic::ppc_altivec_vcmpeqfp_p: CompareOpc = 198; isDot = 1; break;
5930 case Intrinsic::ppc_altivec_vcmpequb_p: CompareOpc = 6; isDot = 1; break;
5931 case Intrinsic::ppc_altivec_vcmpequh_p: CompareOpc = 70; isDot = 1; break;
5932 case Intrinsic::ppc_altivec_vcmpequw_p: CompareOpc = 134; isDot = 1; break;
5933 case Intrinsic::ppc_altivec_vcmpgefp_p: CompareOpc = 454; isDot = 1; break;
5934 case Intrinsic::ppc_altivec_vcmpgtfp_p: CompareOpc = 710; isDot = 1; break;
5935 case Intrinsic::ppc_altivec_vcmpgtsb_p: CompareOpc = 774; isDot = 1; break;
5936 case Intrinsic::ppc_altivec_vcmpgtsh_p: CompareOpc = 838; isDot = 1; break;
5937 case Intrinsic::ppc_altivec_vcmpgtsw_p: CompareOpc = 902; isDot = 1; break;
5938 case Intrinsic::ppc_altivec_vcmpgtub_p: CompareOpc = 518; isDot = 1; break;
5939 case Intrinsic::ppc_altivec_vcmpgtuh_p: CompareOpc = 582; isDot = 1; break;
5940 case Intrinsic::ppc_altivec_vcmpgtuw_p: CompareOpc = 646; isDot = 1; break;
5942 // Normal Comparisons.
5943 case Intrinsic::ppc_altivec_vcmpbfp: CompareOpc = 966; isDot = 0; break;
5944 case Intrinsic::ppc_altivec_vcmpeqfp: CompareOpc = 198; isDot = 0; break;
5945 case Intrinsic::ppc_altivec_vcmpequb: CompareOpc = 6; isDot = 0; break;
5946 case Intrinsic::ppc_altivec_vcmpequh: CompareOpc = 70; isDot = 0; break;
5947 case Intrinsic::ppc_altivec_vcmpequw: CompareOpc = 134; isDot = 0; break;
5948 case Intrinsic::ppc_altivec_vcmpgefp: CompareOpc = 454; isDot = 0; break;
5949 case Intrinsic::ppc_altivec_vcmpgtfp: CompareOpc = 710; isDot = 0; break;
5950 case Intrinsic::ppc_altivec_vcmpgtsb: CompareOpc = 774; isDot = 0; break;
5951 case Intrinsic::ppc_altivec_vcmpgtsh: CompareOpc = 838; isDot = 0; break;
5952 case Intrinsic::ppc_altivec_vcmpgtsw: CompareOpc = 902; isDot = 0; break;
5953 case Intrinsic::ppc_altivec_vcmpgtub: CompareOpc = 518; isDot = 0; break;
5954 case Intrinsic::ppc_altivec_vcmpgtuh: CompareOpc = 582; isDot = 0; break;
5955 case Intrinsic::ppc_altivec_vcmpgtuw: CompareOpc = 646; isDot = 0; break;
5960 /// LowerINTRINSIC_WO_CHAIN - If this is an intrinsic that we want to custom
5961 /// lower, do it, otherwise return null.
5962 SDValue PPCTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
5963 SelectionDAG &DAG) const {
5964 // If this is a lowered altivec predicate compare, CompareOpc is set to the
5965 // opcode number of the comparison.
5969 if (!getAltivecCompareInfo(Op, CompareOpc, isDot))
5970 return SDValue(); // Don't custom lower most intrinsics.
5972 // If this is a non-dot comparison, make the VCMP node and we are done.
5974 SDValue Tmp = DAG.getNode(PPCISD::VCMP, dl, Op.getOperand(2).getValueType(),
5975 Op.getOperand(1), Op.getOperand(2),
5976 DAG.getConstant(CompareOpc, MVT::i32));
5977 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Tmp);
5980 // Create the PPCISD altivec 'dot' comparison node.
5982 Op.getOperand(2), // LHS
5983 Op.getOperand(3), // RHS
5984 DAG.getConstant(CompareOpc, MVT::i32)
5986 EVT VTs[] = { Op.getOperand(2).getValueType(), MVT::Glue };
5987 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
5989 // Now that we have the comparison, emit a copy from the CR to a GPR.
5990 // This is flagged to the above dot comparison.
5991 SDValue Flags = DAG.getNode(PPCISD::MFOCRF, dl, MVT::i32,
5992 DAG.getRegister(PPC::CR6, MVT::i32),
5993 CompNode.getValue(1));
5995 // Unpack the result based on how the target uses it.
5996 unsigned BitNo; // Bit # of CR6.
5997 bool InvertBit; // Invert result?
5998 switch (cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()) {
5999 default: // Can't happen, don't crash on invalid number though.
6000 case 0: // Return the value of the EQ bit of CR6.
6001 BitNo = 0; InvertBit = false;
6003 case 1: // Return the inverted value of the EQ bit of CR6.
6004 BitNo = 0; InvertBit = true;
6006 case 2: // Return the value of the LT bit of CR6.
6007 BitNo = 2; InvertBit = false;
6009 case 3: // Return the inverted value of the LT bit of CR6.
6010 BitNo = 2; InvertBit = true;
6014 // Shift the bit into the low position.
6015 Flags = DAG.getNode(ISD::SRL, dl, MVT::i32, Flags,
6016 DAG.getConstant(8-(3-BitNo), MVT::i32));
6018 Flags = DAG.getNode(ISD::AND, dl, MVT::i32, Flags,
6019 DAG.getConstant(1, MVT::i32));
6021 // If we are supposed to, toggle the bit.
6023 Flags = DAG.getNode(ISD::XOR, dl, MVT::i32, Flags,
6024 DAG.getConstant(1, MVT::i32));
6028 SDValue PPCTargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op,
6029 SelectionDAG &DAG) const {
6031 // For v2i64 (VSX), we can pattern patch the v2i32 case (using fp <-> int
6032 // instructions), but for smaller types, we need to first extend up to v2i32
6033 // before doing going farther.
6034 if (Op.getValueType() == MVT::v2i64) {
6035 EVT ExtVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
6036 if (ExtVT != MVT::v2i32) {
6037 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, Op.getOperand(0));
6038 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v4i32, Op,
6039 DAG.getValueType(EVT::getVectorVT(*DAG.getContext(),
6040 ExtVT.getVectorElementType(), 4)));
6041 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Op);
6042 Op = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, MVT::v2i64, Op,
6043 DAG.getValueType(MVT::v2i32));
6052 SDValue PPCTargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op,
6053 SelectionDAG &DAG) const {
6055 // Create a stack slot that is 16-byte aligned.
6056 MachineFrameInfo *FrameInfo = DAG.getMachineFunction().getFrameInfo();
6057 int FrameIdx = FrameInfo->CreateStackObject(16, 16, false);
6058 EVT PtrVT = getPointerTy();
6059 SDValue FIdx = DAG.getFrameIndex(FrameIdx, PtrVT);
6061 // Store the input value into Value#0 of the stack slot.
6062 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl,
6063 Op.getOperand(0), FIdx, MachinePointerInfo(),
6066 return DAG.getLoad(Op.getValueType(), dl, Store, FIdx, MachinePointerInfo(),
6067 false, false, false, 0);
6070 SDValue PPCTargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const {
6072 if (Op.getValueType() == MVT::v4i32) {
6073 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6075 SDValue Zero = BuildSplatI( 0, 1, MVT::v4i32, DAG, dl);
6076 SDValue Neg16 = BuildSplatI(-16, 4, MVT::v4i32, DAG, dl);//+16 as shift amt.
6078 SDValue RHSSwap = // = vrlw RHS, 16
6079 BuildIntrinsicOp(Intrinsic::ppc_altivec_vrlw, RHS, Neg16, DAG, dl);
6081 // Shrinkify inputs to v8i16.
6082 LHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, LHS);
6083 RHS = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHS);
6084 RHSSwap = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, RHSSwap);
6086 // Low parts multiplied together, generating 32-bit results (we ignore the
6088 SDValue LoProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmulouh,
6089 LHS, RHS, DAG, dl, MVT::v4i32);
6091 SDValue HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmsumuhm,
6092 LHS, RHSSwap, Zero, DAG, dl, MVT::v4i32);
6093 // Shift the high parts up 16 bits.
6094 HiProd = BuildIntrinsicOp(Intrinsic::ppc_altivec_vslw, HiProd,
6096 return DAG.getNode(ISD::ADD, dl, MVT::v4i32, LoProd, HiProd);
6097 } else if (Op.getValueType() == MVT::v8i16) {
6098 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6100 SDValue Zero = BuildSplatI(0, 1, MVT::v8i16, DAG, dl);
6102 return BuildIntrinsicOp(Intrinsic::ppc_altivec_vmladduhm,
6103 LHS, RHS, Zero, DAG, dl);
6104 } else if (Op.getValueType() == MVT::v16i8) {
6105 SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1);
6106 bool isLittleEndian = Subtarget.isLittleEndian();
6108 // Multiply the even 8-bit parts, producing 16-bit sums.
6109 SDValue EvenParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuleub,
6110 LHS, RHS, DAG, dl, MVT::v8i16);
6111 EvenParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, EvenParts);
6113 // Multiply the odd 8-bit parts, producing 16-bit sums.
6114 SDValue OddParts = BuildIntrinsicOp(Intrinsic::ppc_altivec_vmuloub,
6115 LHS, RHS, DAG, dl, MVT::v8i16);
6116 OddParts = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, OddParts);
6118 // Merge the results together. Because vmuleub and vmuloub are
6119 // instructions with a big-endian bias, we must reverse the
6120 // element numbering and reverse the meaning of "odd" and "even"
6121 // when generating little endian code.
6123 for (unsigned i = 0; i != 8; ++i) {
6124 if (isLittleEndian) {
6126 Ops[i*2+1] = 2*i+16;
6129 Ops[i*2+1] = 2*i+1+16;
6133 return DAG.getVectorShuffle(MVT::v16i8, dl, OddParts, EvenParts, Ops);
6135 return DAG.getVectorShuffle(MVT::v16i8, dl, EvenParts, OddParts, Ops);
6137 llvm_unreachable("Unknown mul to lower!");
6141 /// LowerOperation - Provide custom lowering hooks for some operations.
6143 SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
6144 switch (Op.getOpcode()) {
6145 default: llvm_unreachable("Wasn't expecting to be able to lower this!");
6146 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
6147 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
6148 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
6149 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
6150 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
6151 case ISD::SETCC: return LowerSETCC(Op, DAG);
6152 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
6153 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
6155 return LowerVASTART(Op, DAG, Subtarget);
6158 return LowerVAARG(Op, DAG, Subtarget);
6161 return LowerVACOPY(Op, DAG, Subtarget);
6163 case ISD::STACKRESTORE: return LowerSTACKRESTORE(Op, DAG, Subtarget);
6164 case ISD::DYNAMIC_STACKALLOC:
6165 return LowerDYNAMIC_STACKALLOC(Op, DAG, Subtarget);
6167 case ISD::EH_SJLJ_SETJMP: return lowerEH_SJLJ_SETJMP(Op, DAG);
6168 case ISD::EH_SJLJ_LONGJMP: return lowerEH_SJLJ_LONGJMP(Op, DAG);
6170 case ISD::LOAD: return LowerLOAD(Op, DAG);
6171 case ISD::STORE: return LowerSTORE(Op, DAG);
6172 case ISD::TRUNCATE: return LowerTRUNCATE(Op, DAG);
6173 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
6174 case ISD::FP_TO_UINT:
6175 case ISD::FP_TO_SINT: return LowerFP_TO_INT(Op, DAG,
6177 case ISD::UINT_TO_FP:
6178 case ISD::SINT_TO_FP: return LowerINT_TO_FP(Op, DAG);
6179 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG);
6181 // Lower 64-bit shifts.
6182 case ISD::SHL_PARTS: return LowerSHL_PARTS(Op, DAG);
6183 case ISD::SRL_PARTS: return LowerSRL_PARTS(Op, DAG);
6184 case ISD::SRA_PARTS: return LowerSRA_PARTS(Op, DAG);
6186 // Vector-related lowering.
6187 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG);
6188 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG);
6189 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
6190 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG);
6191 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op, DAG);
6192 case ISD::MUL: return LowerMUL(Op, DAG);
6194 // For counter-based loop handling.
6195 case ISD::INTRINSIC_W_CHAIN: return SDValue();
6197 // Frame & Return address.
6198 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
6199 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
6203 void PPCTargetLowering::ReplaceNodeResults(SDNode *N,
6204 SmallVectorImpl<SDValue>&Results,
6205 SelectionDAG &DAG) const {
6206 const TargetMachine &TM = getTargetMachine();
6208 switch (N->getOpcode()) {
6210 llvm_unreachable("Do not know how to custom type legalize this operation!");
6211 case ISD::INTRINSIC_W_CHAIN: {
6212 if (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() !=
6213 Intrinsic::ppc_is_decremented_ctr_nonzero)
6216 assert(N->getValueType(0) == MVT::i1 &&
6217 "Unexpected result type for CTR decrement intrinsic");
6218 EVT SVT = getSetCCResultType(*DAG.getContext(), N->getValueType(0));
6219 SDVTList VTs = DAG.getVTList(SVT, MVT::Other);
6220 SDValue NewInt = DAG.getNode(N->getOpcode(), dl, VTs, N->getOperand(0),
6223 Results.push_back(NewInt);
6224 Results.push_back(NewInt.getValue(1));
6228 if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()
6229 || TM.getSubtarget<PPCSubtarget>().isPPC64())
6232 EVT VT = N->getValueType(0);
6234 if (VT == MVT::i64) {
6235 SDValue NewNode = LowerVAARG(SDValue(N, 1), DAG, Subtarget);
6237 Results.push_back(NewNode);
6238 Results.push_back(NewNode.getValue(1));
6242 case ISD::FP_ROUND_INREG: {
6243 assert(N->getValueType(0) == MVT::ppcf128);
6244 assert(N->getOperand(0).getValueType() == MVT::ppcf128);
6245 SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6246 MVT::f64, N->getOperand(0),
6247 DAG.getIntPtrConstant(0));
6248 SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl,
6249 MVT::f64, N->getOperand(0),
6250 DAG.getIntPtrConstant(1));
6252 // Add the two halves of the long double in round-to-zero mode.
6253 SDValue FPreg = DAG.getNode(PPCISD::FADDRTZ, dl, MVT::f64, Lo, Hi);
6255 // We know the low half is about to be thrown away, so just use something
6257 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::ppcf128,
6261 case ISD::FP_TO_SINT:
6262 // LowerFP_TO_INT() can only handle f32 and f64.
6263 if (N->getOperand(0).getValueType() == MVT::ppcf128)
6265 Results.push_back(LowerFP_TO_INT(SDValue(N, 0), DAG, dl));
6271 //===----------------------------------------------------------------------===//
6272 // Other Lowering Code
6273 //===----------------------------------------------------------------------===//
6276 PPCTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
6277 bool is64bit, unsigned BinOpcode) const {
6278 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6279 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6281 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6282 MachineFunction *F = BB->getParent();
6283 MachineFunction::iterator It = BB;
6286 unsigned dest = MI->getOperand(0).getReg();
6287 unsigned ptrA = MI->getOperand(1).getReg();
6288 unsigned ptrB = MI->getOperand(2).getReg();
6289 unsigned incr = MI->getOperand(3).getReg();
6290 DebugLoc dl = MI->getDebugLoc();
6292 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6293 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6294 F->insert(It, loopMBB);
6295 F->insert(It, exitMBB);
6296 exitMBB->splice(exitMBB->begin(), BB,
6297 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6298 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6300 MachineRegisterInfo &RegInfo = F->getRegInfo();
6301 unsigned TmpReg = (!BinOpcode) ? incr :
6302 RegInfo.createVirtualRegister(
6303 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6304 (const TargetRegisterClass *) &PPC::GPRCRegClass);
6308 // fallthrough --> loopMBB
6309 BB->addSuccessor(loopMBB);
6312 // l[wd]arx dest, ptr
6313 // add r0, dest, incr
6314 // st[wd]cx. r0, ptr
6316 // fallthrough --> exitMBB
6318 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6319 .addReg(ptrA).addReg(ptrB);
6321 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
6322 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6323 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
6324 BuildMI(BB, dl, TII->get(PPC::BCC))
6325 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6326 BB->addSuccessor(loopMBB);
6327 BB->addSuccessor(exitMBB);
6336 PPCTargetLowering::EmitPartwordAtomicBinary(MachineInstr *MI,
6337 MachineBasicBlock *BB,
6338 bool is8bit, // operation
6339 unsigned BinOpcode) const {
6340 // This also handles ATOMIC_SWAP, indicated by BinOpcode==0.
6341 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6342 // In 64 bit mode we have to use 64 bits for addresses, even though the
6343 // lwarx/stwcx are 32 bits. With the 32-bit atomics we can use address
6344 // registers without caring whether they're 32 or 64, but here we're
6345 // doing actual arithmetic on the addresses.
6346 bool is64bit = Subtarget.isPPC64();
6347 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6349 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6350 MachineFunction *F = BB->getParent();
6351 MachineFunction::iterator It = BB;
6354 unsigned dest = MI->getOperand(0).getReg();
6355 unsigned ptrA = MI->getOperand(1).getReg();
6356 unsigned ptrB = MI->getOperand(2).getReg();
6357 unsigned incr = MI->getOperand(3).getReg();
6358 DebugLoc dl = MI->getDebugLoc();
6360 MachineBasicBlock *loopMBB = F->CreateMachineBasicBlock(LLVM_BB);
6361 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6362 F->insert(It, loopMBB);
6363 F->insert(It, exitMBB);
6364 exitMBB->splice(exitMBB->begin(), BB,
6365 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6366 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6368 MachineRegisterInfo &RegInfo = F->getRegInfo();
6369 const TargetRegisterClass *RC =
6370 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6371 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6372 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6373 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6374 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6375 unsigned Incr2Reg = RegInfo.createVirtualRegister(RC);
6376 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6377 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6378 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6379 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6380 unsigned Tmp3Reg = RegInfo.createVirtualRegister(RC);
6381 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6382 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6384 unsigned TmpReg = (!BinOpcode) ? Incr2Reg : RegInfo.createVirtualRegister(RC);
6388 // fallthrough --> loopMBB
6389 BB->addSuccessor(loopMBB);
6391 // The 4-byte load must be aligned, while a char or short may be
6392 // anywhere in the word. Hence all this nasty bookkeeping code.
6393 // add ptr1, ptrA, ptrB [copy if ptrA==0]
6394 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
6395 // xori shift, shift1, 24 [16]
6396 // rlwinm ptr, ptr1, 0, 0, 29
6397 // slw incr2, incr, shift
6398 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
6399 // slw mask, mask2, shift
6401 // lwarx tmpDest, ptr
6402 // add tmp, tmpDest, incr2
6403 // andc tmp2, tmpDest, mask
6404 // and tmp3, tmp, mask
6405 // or tmp4, tmp3, tmp2
6408 // fallthrough --> exitMBB
6409 // srw dest, tmpDest, shift
6410 if (ptrA != ZeroReg) {
6411 Ptr1Reg = RegInfo.createVirtualRegister(RC);
6412 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
6413 .addReg(ptrA).addReg(ptrB);
6417 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
6418 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
6419 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
6420 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
6422 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
6423 .addReg(Ptr1Reg).addImm(0).addImm(61);
6425 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
6426 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
6427 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg)
6428 .addReg(incr).addReg(ShiftReg);
6430 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
6432 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
6433 BuildMI(BB, dl, TII->get(PPC::ORI),Mask2Reg).addReg(Mask3Reg).addImm(65535);
6435 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
6436 .addReg(Mask2Reg).addReg(ShiftReg);
6439 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
6440 .addReg(ZeroReg).addReg(PtrReg);
6442 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg)
6443 .addReg(Incr2Reg).addReg(TmpDestReg);
6444 BuildMI(BB, dl, TII->get(is64bit ? PPC::ANDC8 : PPC::ANDC), Tmp2Reg)
6445 .addReg(TmpDestReg).addReg(MaskReg);
6446 BuildMI(BB, dl, TII->get(is64bit ? PPC::AND8 : PPC::AND), Tmp3Reg)
6447 .addReg(TmpReg).addReg(MaskReg);
6448 BuildMI(BB, dl, TII->get(is64bit ? PPC::OR8 : PPC::OR), Tmp4Reg)
6449 .addReg(Tmp3Reg).addReg(Tmp2Reg);
6450 BuildMI(BB, dl, TII->get(PPC::STWCX))
6451 .addReg(Tmp4Reg).addReg(ZeroReg).addReg(PtrReg);
6452 BuildMI(BB, dl, TII->get(PPC::BCC))
6453 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
6454 BB->addSuccessor(loopMBB);
6455 BB->addSuccessor(exitMBB);
6460 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest).addReg(TmpDestReg)
6465 llvm::MachineBasicBlock*
6466 PPCTargetLowering::emitEHSjLjSetJmp(MachineInstr *MI,
6467 MachineBasicBlock *MBB) const {
6468 DebugLoc DL = MI->getDebugLoc();
6469 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6471 MachineFunction *MF = MBB->getParent();
6472 MachineRegisterInfo &MRI = MF->getRegInfo();
6474 const BasicBlock *BB = MBB->getBasicBlock();
6475 MachineFunction::iterator I = MBB;
6479 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6480 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6482 unsigned DstReg = MI->getOperand(0).getReg();
6483 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
6484 assert(RC->hasType(MVT::i32) && "Invalid destination!");
6485 unsigned mainDstReg = MRI.createVirtualRegister(RC);
6486 unsigned restoreDstReg = MRI.createVirtualRegister(RC);
6488 MVT PVT = getPointerTy();
6489 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6490 "Invalid Pointer Size!");
6491 // For v = setjmp(buf), we generate
6494 // SjLjSetup mainMBB
6500 // buf[LabelOffset] = LR
6504 // v = phi(main, restore)
6507 MachineBasicBlock *thisMBB = MBB;
6508 MachineBasicBlock *mainMBB = MF->CreateMachineBasicBlock(BB);
6509 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(BB);
6510 MF->insert(I, mainMBB);
6511 MF->insert(I, sinkMBB);
6513 MachineInstrBuilder MIB;
6515 // Transfer the remainder of BB and its successor edges to sinkMBB.
6516 sinkMBB->splice(sinkMBB->begin(), MBB,
6517 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
6518 sinkMBB->transferSuccessorsAndUpdatePHIs(MBB);
6520 // Note that the structure of the jmp_buf used here is not compatible
6521 // with that used by libc, and is not designed to be. Specifically, it
6522 // stores only those 'reserved' registers that LLVM does not otherwise
6523 // understand how to spill. Also, by convention, by the time this
6524 // intrinsic is called, Clang has already stored the frame address in the
6525 // first slot of the buffer and stack address in the third. Following the
6526 // X86 target code, we'll store the jump address in the second slot. We also
6527 // need to save the TOC pointer (R2) to handle jumps between shared
6528 // libraries, and that will be stored in the fourth slot. The thread
6529 // identifier (R13) is not affected.
6532 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6533 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6534 const int64_t BPOffset = 4 * PVT.getStoreSize();
6536 // Prepare IP either in reg.
6537 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
6538 unsigned LabelReg = MRI.createVirtualRegister(PtrRC);
6539 unsigned BufReg = MI->getOperand(1).getReg();
6541 if (Subtarget.isPPC64() && Subtarget.isSVR4ABI()) {
6542 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::STD))
6546 MIB.setMemRefs(MMOBegin, MMOEnd);
6549 // Naked functions never have a base pointer, and so we use r1. For all
6550 // other functions, this decision must be delayed until during PEI.
6552 if (MF->getFunction()->getAttributes().hasAttribute(
6553 AttributeSet::FunctionIndex, Attribute::Naked))
6554 BaseReg = Subtarget.isPPC64() ? PPC::X1 : PPC::R1;
6556 BaseReg = Subtarget.isPPC64() ? PPC::BP8 : PPC::BP;
6558 MIB = BuildMI(*thisMBB, MI, DL,
6559 TII->get(Subtarget.isPPC64() ? PPC::STD : PPC::STW))
6563 MIB.setMemRefs(MMOBegin, MMOEnd);
6566 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
6567 const PPCRegisterInfo *TRI =
6568 static_cast<const PPCRegisterInfo*>(getTargetMachine().getRegisterInfo());
6569 MIB.addRegMask(TRI->getNoPreservedMask());
6571 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
6573 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::EH_SjLj_Setup))
6575 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
6577 thisMBB->addSuccessor(mainMBB, /* weight */ 0);
6578 thisMBB->addSuccessor(sinkMBB, /* weight */ 1);
6582 MIB = BuildMI(mainMBB, DL,
6583 TII->get(Subtarget.isPPC64() ? PPC::MFLR8 : PPC::MFLR), LabelReg);
6586 if (Subtarget.isPPC64()) {
6587 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STD))
6589 .addImm(LabelOffset)
6592 MIB = BuildMI(mainMBB, DL, TII->get(PPC::STW))
6594 .addImm(LabelOffset)
6598 MIB.setMemRefs(MMOBegin, MMOEnd);
6600 BuildMI(mainMBB, DL, TII->get(PPC::LI), mainDstReg).addImm(0);
6601 mainMBB->addSuccessor(sinkMBB);
6604 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
6605 TII->get(PPC::PHI), DstReg)
6606 .addReg(mainDstReg).addMBB(mainMBB)
6607 .addReg(restoreDstReg).addMBB(thisMBB);
6609 MI->eraseFromParent();
6614 PPCTargetLowering::emitEHSjLjLongJmp(MachineInstr *MI,
6615 MachineBasicBlock *MBB) const {
6616 DebugLoc DL = MI->getDebugLoc();
6617 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6619 MachineFunction *MF = MBB->getParent();
6620 MachineRegisterInfo &MRI = MF->getRegInfo();
6623 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin();
6624 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end();
6626 MVT PVT = getPointerTy();
6627 assert((PVT == MVT::i64 || PVT == MVT::i32) &&
6628 "Invalid Pointer Size!");
6630 const TargetRegisterClass *RC =
6631 (PVT == MVT::i64) ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
6632 unsigned Tmp = MRI.createVirtualRegister(RC);
6633 // Since FP is only updated here but NOT referenced, it's treated as GPR.
6634 unsigned FP = (PVT == MVT::i64) ? PPC::X31 : PPC::R31;
6635 unsigned SP = (PVT == MVT::i64) ? PPC::X1 : PPC::R1;
6636 unsigned BP = (PVT == MVT::i64) ? PPC::X30 : PPC::R30;
6638 MachineInstrBuilder MIB;
6640 const int64_t LabelOffset = 1 * PVT.getStoreSize();
6641 const int64_t SPOffset = 2 * PVT.getStoreSize();
6642 const int64_t TOCOffset = 3 * PVT.getStoreSize();
6643 const int64_t BPOffset = 4 * PVT.getStoreSize();
6645 unsigned BufReg = MI->getOperand(0).getReg();
6647 // Reload FP (the jumped-to function may not have had a
6648 // frame pointer, and if so, then its r31 will be restored
6650 if (PVT == MVT::i64) {
6651 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
6655 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
6659 MIB.setMemRefs(MMOBegin, MMOEnd);
6662 if (PVT == MVT::i64) {
6663 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
6664 .addImm(LabelOffset)
6667 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
6668 .addImm(LabelOffset)
6671 MIB.setMemRefs(MMOBegin, MMOEnd);
6674 if (PVT == MVT::i64) {
6675 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
6679 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
6683 MIB.setMemRefs(MMOBegin, MMOEnd);
6686 if (PVT == MVT::i64) {
6687 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
6691 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
6695 MIB.setMemRefs(MMOBegin, MMOEnd);
6698 if (PVT == MVT::i64 && Subtarget.isSVR4ABI()) {
6699 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
6703 MIB.setMemRefs(MMOBegin, MMOEnd);
6707 BuildMI(*MBB, MI, DL,
6708 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
6709 BuildMI(*MBB, MI, DL, TII->get(PVT == MVT::i64 ? PPC::BCTR8 : PPC::BCTR));
6711 MI->eraseFromParent();
6716 PPCTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
6717 MachineBasicBlock *BB) const {
6718 if (MI->getOpcode() == PPC::EH_SjLj_SetJmp32 ||
6719 MI->getOpcode() == PPC::EH_SjLj_SetJmp64) {
6720 return emitEHSjLjSetJmp(MI, BB);
6721 } else if (MI->getOpcode() == PPC::EH_SjLj_LongJmp32 ||
6722 MI->getOpcode() == PPC::EH_SjLj_LongJmp64) {
6723 return emitEHSjLjLongJmp(MI, BB);
6726 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6728 // To "insert" these instructions we actually have to insert their
6729 // control-flow patterns.
6730 const BasicBlock *LLVM_BB = BB->getBasicBlock();
6731 MachineFunction::iterator It = BB;
6734 MachineFunction *F = BB->getParent();
6736 if (Subtarget.hasISEL() && (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6737 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6738 MI->getOpcode() == PPC::SELECT_I4 ||
6739 MI->getOpcode() == PPC::SELECT_I8)) {
6740 SmallVector<MachineOperand, 2> Cond;
6741 if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6742 MI->getOpcode() == PPC::SELECT_CC_I8)
6743 Cond.push_back(MI->getOperand(4));
6745 Cond.push_back(MachineOperand::CreateImm(PPC::PRED_BIT_SET));
6746 Cond.push_back(MI->getOperand(1));
6748 DebugLoc dl = MI->getDebugLoc();
6749 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
6750 TII->insertSelect(*BB, MI, dl, MI->getOperand(0).getReg(),
6751 Cond, MI->getOperand(2).getReg(),
6752 MI->getOperand(3).getReg());
6753 } else if (MI->getOpcode() == PPC::SELECT_CC_I4 ||
6754 MI->getOpcode() == PPC::SELECT_CC_I8 ||
6755 MI->getOpcode() == PPC::SELECT_CC_F4 ||
6756 MI->getOpcode() == PPC::SELECT_CC_F8 ||
6757 MI->getOpcode() == PPC::SELECT_CC_VRRC ||
6758 MI->getOpcode() == PPC::SELECT_I4 ||
6759 MI->getOpcode() == PPC::SELECT_I8 ||
6760 MI->getOpcode() == PPC::SELECT_F4 ||
6761 MI->getOpcode() == PPC::SELECT_F8 ||
6762 MI->getOpcode() == PPC::SELECT_VRRC) {
6763 // The incoming instruction knows the destination vreg to set, the
6764 // condition code register to branch on, the true/false values to
6765 // select between, and a branch opcode to use.
6770 // cmpTY ccX, r1, r2
6772 // fallthrough --> copy0MBB
6773 MachineBasicBlock *thisMBB = BB;
6774 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
6775 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
6776 DebugLoc dl = MI->getDebugLoc();
6777 F->insert(It, copy0MBB);
6778 F->insert(It, sinkMBB);
6780 // Transfer the remainder of BB and its successor edges to sinkMBB.
6781 sinkMBB->splice(sinkMBB->begin(), BB,
6782 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6783 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
6785 // Next, add the true and fallthrough blocks as its successors.
6786 BB->addSuccessor(copy0MBB);
6787 BB->addSuccessor(sinkMBB);
6789 if (MI->getOpcode() == PPC::SELECT_I4 ||
6790 MI->getOpcode() == PPC::SELECT_I8 ||
6791 MI->getOpcode() == PPC::SELECT_F4 ||
6792 MI->getOpcode() == PPC::SELECT_F8 ||
6793 MI->getOpcode() == PPC::SELECT_VRRC) {
6794 BuildMI(BB, dl, TII->get(PPC::BC))
6795 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6797 unsigned SelectPred = MI->getOperand(4).getImm();
6798 BuildMI(BB, dl, TII->get(PPC::BCC))
6799 .addImm(SelectPred).addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
6803 // %FalseValue = ...
6804 // # fallthrough to sinkMBB
6807 // Update machine-CFG edges
6808 BB->addSuccessor(sinkMBB);
6811 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
6814 BuildMI(*BB, BB->begin(), dl,
6815 TII->get(PPC::PHI), MI->getOperand(0).getReg())
6816 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
6817 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
6819 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I8)
6820 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ADD4);
6821 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I16)
6822 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ADD4);
6823 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I32)
6824 BB = EmitAtomicBinary(MI, BB, false, PPC::ADD4);
6825 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_ADD_I64)
6826 BB = EmitAtomicBinary(MI, BB, true, PPC::ADD8);
6828 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I8)
6829 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::AND);
6830 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I16)
6831 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::AND);
6832 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I32)
6833 BB = EmitAtomicBinary(MI, BB, false, PPC::AND);
6834 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_AND_I64)
6835 BB = EmitAtomicBinary(MI, BB, true, PPC::AND8);
6837 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I8)
6838 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::OR);
6839 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I16)
6840 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::OR);
6841 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I32)
6842 BB = EmitAtomicBinary(MI, BB, false, PPC::OR);
6843 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_OR_I64)
6844 BB = EmitAtomicBinary(MI, BB, true, PPC::OR8);
6846 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I8)
6847 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::XOR);
6848 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I16)
6849 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::XOR);
6850 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I32)
6851 BB = EmitAtomicBinary(MI, BB, false, PPC::XOR);
6852 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_XOR_I64)
6853 BB = EmitAtomicBinary(MI, BB, true, PPC::XOR8);
6855 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I8)
6856 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::ANDC);
6857 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I16)
6858 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::ANDC);
6859 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I32)
6860 BB = EmitAtomicBinary(MI, BB, false, PPC::ANDC);
6861 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_NAND_I64)
6862 BB = EmitAtomicBinary(MI, BB, true, PPC::ANDC8);
6864 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I8)
6865 BB = EmitPartwordAtomicBinary(MI, BB, true, PPC::SUBF);
6866 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I16)
6867 BB = EmitPartwordAtomicBinary(MI, BB, false, PPC::SUBF);
6868 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I32)
6869 BB = EmitAtomicBinary(MI, BB, false, PPC::SUBF);
6870 else if (MI->getOpcode() == PPC::ATOMIC_LOAD_SUB_I64)
6871 BB = EmitAtomicBinary(MI, BB, true, PPC::SUBF8);
6873 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I8)
6874 BB = EmitPartwordAtomicBinary(MI, BB, true, 0);
6875 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I16)
6876 BB = EmitPartwordAtomicBinary(MI, BB, false, 0);
6877 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I32)
6878 BB = EmitAtomicBinary(MI, BB, false, 0);
6879 else if (MI->getOpcode() == PPC::ATOMIC_SWAP_I64)
6880 BB = EmitAtomicBinary(MI, BB, true, 0);
6882 else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I32 ||
6883 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64) {
6884 bool is64bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I64;
6886 unsigned dest = MI->getOperand(0).getReg();
6887 unsigned ptrA = MI->getOperand(1).getReg();
6888 unsigned ptrB = MI->getOperand(2).getReg();
6889 unsigned oldval = MI->getOperand(3).getReg();
6890 unsigned newval = MI->getOperand(4).getReg();
6891 DebugLoc dl = MI->getDebugLoc();
6893 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6894 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6895 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6896 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6897 F->insert(It, loop1MBB);
6898 F->insert(It, loop2MBB);
6899 F->insert(It, midMBB);
6900 F->insert(It, exitMBB);
6901 exitMBB->splice(exitMBB->begin(), BB,
6902 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6903 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6907 // fallthrough --> loopMBB
6908 BB->addSuccessor(loop1MBB);
6911 // l[wd]arx dest, ptr
6912 // cmp[wd] dest, oldval
6915 // st[wd]cx. newval, ptr
6919 // st[wd]cx. dest, ptr
6922 BuildMI(BB, dl, TII->get(is64bit ? PPC::LDARX : PPC::LWARX), dest)
6923 .addReg(ptrA).addReg(ptrB);
6924 BuildMI(BB, dl, TII->get(is64bit ? PPC::CMPD : PPC::CMPW), PPC::CR0)
6925 .addReg(oldval).addReg(dest);
6926 BuildMI(BB, dl, TII->get(PPC::BCC))
6927 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
6928 BB->addSuccessor(loop2MBB);
6929 BB->addSuccessor(midMBB);
6932 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6933 .addReg(newval).addReg(ptrA).addReg(ptrB);
6934 BuildMI(BB, dl, TII->get(PPC::BCC))
6935 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
6936 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
6937 BB->addSuccessor(loop1MBB);
6938 BB->addSuccessor(exitMBB);
6941 BuildMI(BB, dl, TII->get(is64bit ? PPC::STDCX : PPC::STWCX))
6942 .addReg(dest).addReg(ptrA).addReg(ptrB);
6943 BB->addSuccessor(exitMBB);
6948 } else if (MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8 ||
6949 MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I16) {
6950 // We must use 64-bit registers for addresses when targeting 64-bit,
6951 // since we're actually doing arithmetic on them. Other registers
6953 bool is64bit = Subtarget.isPPC64();
6954 bool is8bit = MI->getOpcode() == PPC::ATOMIC_CMP_SWAP_I8;
6956 unsigned dest = MI->getOperand(0).getReg();
6957 unsigned ptrA = MI->getOperand(1).getReg();
6958 unsigned ptrB = MI->getOperand(2).getReg();
6959 unsigned oldval = MI->getOperand(3).getReg();
6960 unsigned newval = MI->getOperand(4).getReg();
6961 DebugLoc dl = MI->getDebugLoc();
6963 MachineBasicBlock *loop1MBB = F->CreateMachineBasicBlock(LLVM_BB);
6964 MachineBasicBlock *loop2MBB = F->CreateMachineBasicBlock(LLVM_BB);
6965 MachineBasicBlock *midMBB = F->CreateMachineBasicBlock(LLVM_BB);
6966 MachineBasicBlock *exitMBB = F->CreateMachineBasicBlock(LLVM_BB);
6967 F->insert(It, loop1MBB);
6968 F->insert(It, loop2MBB);
6969 F->insert(It, midMBB);
6970 F->insert(It, exitMBB);
6971 exitMBB->splice(exitMBB->begin(), BB,
6972 std::next(MachineBasicBlock::iterator(MI)), BB->end());
6973 exitMBB->transferSuccessorsAndUpdatePHIs(BB);
6975 MachineRegisterInfo &RegInfo = F->getRegInfo();
6976 const TargetRegisterClass *RC =
6977 is64bit ? (const TargetRegisterClass *) &PPC::G8RCRegClass :
6978 (const TargetRegisterClass *) &PPC::GPRCRegClass;
6979 unsigned PtrReg = RegInfo.createVirtualRegister(RC);
6980 unsigned Shift1Reg = RegInfo.createVirtualRegister(RC);
6981 unsigned ShiftReg = RegInfo.createVirtualRegister(RC);
6982 unsigned NewVal2Reg = RegInfo.createVirtualRegister(RC);
6983 unsigned NewVal3Reg = RegInfo.createVirtualRegister(RC);
6984 unsigned OldVal2Reg = RegInfo.createVirtualRegister(RC);
6985 unsigned OldVal3Reg = RegInfo.createVirtualRegister(RC);
6986 unsigned MaskReg = RegInfo.createVirtualRegister(RC);
6987 unsigned Mask2Reg = RegInfo.createVirtualRegister(RC);
6988 unsigned Mask3Reg = RegInfo.createVirtualRegister(RC);
6989 unsigned Tmp2Reg = RegInfo.createVirtualRegister(RC);
6990 unsigned Tmp4Reg = RegInfo.createVirtualRegister(RC);
6991 unsigned TmpDestReg = RegInfo.createVirtualRegister(RC);
6993 unsigned TmpReg = RegInfo.createVirtualRegister(RC);
6994 unsigned ZeroReg = is64bit ? PPC::ZERO8 : PPC::ZERO;
6997 // fallthrough --> loopMBB
6998 BB->addSuccessor(loop1MBB);
7000 // The 4-byte load must be aligned, while a char or short may be
7001 // anywhere in the word. Hence all this nasty bookkeeping code.
7002 // add ptr1, ptrA, ptrB [copy if ptrA==0]
7003 // rlwinm shift1, ptr1, 3, 27, 28 [3, 27, 27]
7004 // xori shift, shift1, 24 [16]
7005 // rlwinm ptr, ptr1, 0, 0, 29
7006 // slw newval2, newval, shift
7007 // slw oldval2, oldval,shift
7008 // li mask2, 255 [li mask3, 0; ori mask2, mask3, 65535]
7009 // slw mask, mask2, shift
7010 // and newval3, newval2, mask
7011 // and oldval3, oldval2, mask
7013 // lwarx tmpDest, ptr
7014 // and tmp, tmpDest, mask
7015 // cmpw tmp, oldval3
7018 // andc tmp2, tmpDest, mask
7019 // or tmp4, tmp2, newval3
7024 // stwcx. tmpDest, ptr
7026 // srw dest, tmpDest, shift
7027 if (ptrA != ZeroReg) {
7028 Ptr1Reg = RegInfo.createVirtualRegister(RC);
7029 BuildMI(BB, dl, TII->get(is64bit ? PPC::ADD8 : PPC::ADD4), Ptr1Reg)
7030 .addReg(ptrA).addReg(ptrB);
7034 BuildMI(BB, dl, TII->get(PPC::RLWINM), Shift1Reg).addReg(Ptr1Reg)
7035 .addImm(3).addImm(27).addImm(is8bit ? 28 : 27);
7036 BuildMI(BB, dl, TII->get(is64bit ? PPC::XORI8 : PPC::XORI), ShiftReg)
7037 .addReg(Shift1Reg).addImm(is8bit ? 24 : 16);
7039 BuildMI(BB, dl, TII->get(PPC::RLDICR), PtrReg)
7040 .addReg(Ptr1Reg).addImm(0).addImm(61);
7042 BuildMI(BB, dl, TII->get(PPC::RLWINM), PtrReg)
7043 .addReg(Ptr1Reg).addImm(0).addImm(0).addImm(29);
7044 BuildMI(BB, dl, TII->get(PPC::SLW), NewVal2Reg)
7045 .addReg(newval).addReg(ShiftReg);
7046 BuildMI(BB, dl, TII->get(PPC::SLW), OldVal2Reg)
7047 .addReg(oldval).addReg(ShiftReg);
7049 BuildMI(BB, dl, TII->get(PPC::LI), Mask2Reg).addImm(255);
7051 BuildMI(BB, dl, TII->get(PPC::LI), Mask3Reg).addImm(0);
7052 BuildMI(BB, dl, TII->get(PPC::ORI), Mask2Reg)
7053 .addReg(Mask3Reg).addImm(65535);
7055 BuildMI(BB, dl, TII->get(PPC::SLW), MaskReg)
7056 .addReg(Mask2Reg).addReg(ShiftReg);
7057 BuildMI(BB, dl, TII->get(PPC::AND), NewVal3Reg)
7058 .addReg(NewVal2Reg).addReg(MaskReg);
7059 BuildMI(BB, dl, TII->get(PPC::AND), OldVal3Reg)
7060 .addReg(OldVal2Reg).addReg(MaskReg);
7063 BuildMI(BB, dl, TII->get(PPC::LWARX), TmpDestReg)
7064 .addReg(ZeroReg).addReg(PtrReg);
7065 BuildMI(BB, dl, TII->get(PPC::AND),TmpReg)
7066 .addReg(TmpDestReg).addReg(MaskReg);
7067 BuildMI(BB, dl, TII->get(PPC::CMPW), PPC::CR0)
7068 .addReg(TmpReg).addReg(OldVal3Reg);
7069 BuildMI(BB, dl, TII->get(PPC::BCC))
7070 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(midMBB);
7071 BB->addSuccessor(loop2MBB);
7072 BB->addSuccessor(midMBB);
7075 BuildMI(BB, dl, TII->get(PPC::ANDC),Tmp2Reg)
7076 .addReg(TmpDestReg).addReg(MaskReg);
7077 BuildMI(BB, dl, TII->get(PPC::OR),Tmp4Reg)
7078 .addReg(Tmp2Reg).addReg(NewVal3Reg);
7079 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(Tmp4Reg)
7080 .addReg(ZeroReg).addReg(PtrReg);
7081 BuildMI(BB, dl, TII->get(PPC::BCC))
7082 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loop1MBB);
7083 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
7084 BB->addSuccessor(loop1MBB);
7085 BB->addSuccessor(exitMBB);
7088 BuildMI(BB, dl, TII->get(PPC::STWCX)).addReg(TmpDestReg)
7089 .addReg(ZeroReg).addReg(PtrReg);
7090 BB->addSuccessor(exitMBB);
7095 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW),dest).addReg(TmpReg)
7097 } else if (MI->getOpcode() == PPC::FADDrtz) {
7098 // This pseudo performs an FADD with rounding mode temporarily forced
7099 // to round-to-zero. We emit this via custom inserter since the FPSCR
7100 // is not modeled at the SelectionDAG level.
7101 unsigned Dest = MI->getOperand(0).getReg();
7102 unsigned Src1 = MI->getOperand(1).getReg();
7103 unsigned Src2 = MI->getOperand(2).getReg();
7104 DebugLoc dl = MI->getDebugLoc();
7106 MachineRegisterInfo &RegInfo = F->getRegInfo();
7107 unsigned MFFSReg = RegInfo.createVirtualRegister(&PPC::F8RCRegClass);
7109 // Save FPSCR value.
7110 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
7112 // Set rounding mode to round-to-zero.
7113 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB1)).addImm(31);
7114 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSB0)).addImm(30);
7116 // Perform addition.
7117 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
7119 // Restore FPSCR value.
7120 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSF)).addImm(1).addReg(MFFSReg);
7121 } else if (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7122 MI->getOpcode() == PPC::ANDIo_1_GT_BIT ||
7123 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7124 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) {
7125 unsigned Opcode = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8 ||
7126 MI->getOpcode() == PPC::ANDIo_1_GT_BIT8) ?
7127 PPC::ANDIo8 : PPC::ANDIo;
7128 bool isEQ = (MI->getOpcode() == PPC::ANDIo_1_EQ_BIT ||
7129 MI->getOpcode() == PPC::ANDIo_1_EQ_BIT8);
7131 MachineRegisterInfo &RegInfo = F->getRegInfo();
7132 unsigned Dest = RegInfo.createVirtualRegister(Opcode == PPC::ANDIo ?
7133 &PPC::GPRCRegClass :
7134 &PPC::G8RCRegClass);
7136 DebugLoc dl = MI->getDebugLoc();
7137 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
7138 .addReg(MI->getOperand(1).getReg()).addImm(1);
7139 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
7140 MI->getOperand(0).getReg())
7141 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
7143 llvm_unreachable("Unexpected instr type to insert");
7146 MI->eraseFromParent(); // The pseudo instruction is gone now.
7150 //===----------------------------------------------------------------------===//
7151 // Target Optimization Hooks
7152 //===----------------------------------------------------------------------===//
7154 SDValue PPCTargetLowering::DAGCombineFastRecip(SDValue Op,
7155 DAGCombinerInfo &DCI) const {
7156 if (DCI.isAfterLegalizeVectorOps())
7159 EVT VT = Op.getValueType();
7161 if ((VT == MVT::f32 && Subtarget.hasFRES()) ||
7162 (VT == MVT::f64 && Subtarget.hasFRE()) ||
7163 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7164 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7166 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7167 // For the reciprocal, we need to find the zero of the function:
7168 // F(X) = A X - 1 [which has a zero at X = 1/A]
7170 // X_{i+1} = X_i (2 - A X_i) = X_i + X_i (1 - A X_i) [this second form
7171 // does not require additional intermediate precision]
7173 // Convergence is quadratic, so we essentially double the number of digits
7174 // correct after every iteration. The minimum architected relative
7175 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7176 // 23 digits and double has 52 digits.
7177 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7178 if (VT.getScalarType() == MVT::f64)
7181 SelectionDAG &DAG = DCI.DAG;
7185 DAG.getConstantFP(1.0, VT.getScalarType());
7186 if (VT.isVector()) {
7187 assert(VT.getVectorNumElements() == 4 &&
7188 "Unknown vector type");
7189 FPOne = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7190 FPOne, FPOne, FPOne, FPOne);
7193 SDValue Est = DAG.getNode(PPCISD::FRE, dl, VT, Op);
7194 DCI.AddToWorklist(Est.getNode());
7196 // Newton iterations: Est = Est + Est (1 - Arg * Est)
7197 for (int i = 0; i < Iterations; ++i) {
7198 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Op, Est);
7199 DCI.AddToWorklist(NewEst.getNode());
7201 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPOne, NewEst);
7202 DCI.AddToWorklist(NewEst.getNode());
7204 NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7205 DCI.AddToWorklist(NewEst.getNode());
7207 Est = DAG.getNode(ISD::FADD, dl, VT, Est, NewEst);
7208 DCI.AddToWorklist(Est.getNode());
7217 SDValue PPCTargetLowering::DAGCombineFastRecipFSQRT(SDValue Op,
7218 DAGCombinerInfo &DCI) const {
7219 if (DCI.isAfterLegalizeVectorOps())
7222 EVT VT = Op.getValueType();
7224 if ((VT == MVT::f32 && Subtarget.hasFRSQRTES()) ||
7225 (VT == MVT::f64 && Subtarget.hasFRSQRTE()) ||
7226 (VT == MVT::v4f32 && Subtarget.hasAltivec()) ||
7227 (VT == MVT::v2f64 && Subtarget.hasVSX())) {
7229 // Newton iteration for a function: F(X) is X_{i+1} = X_i - F(X_i)/F'(X_i)
7230 // For the reciprocal sqrt, we need to find the zero of the function:
7231 // F(X) = 1/X^2 - A [which has a zero at X = 1/sqrt(A)]
7233 // X_{i+1} = X_i (1.5 - A X_i^2 / 2)
7234 // As a result, we precompute A/2 prior to the iteration loop.
7236 // Convergence is quadratic, so we essentially double the number of digits
7237 // correct after every iteration. The minimum architected relative
7238 // accuracy is 2^-5. When hasRecipPrec(), this is 2^-14. IEEE float has
7239 // 23 digits and double has 52 digits.
7240 int Iterations = Subtarget.hasRecipPrec() ? 1 : 3;
7241 if (VT.getScalarType() == MVT::f64)
7244 SelectionDAG &DAG = DCI.DAG;
7247 SDValue FPThreeHalves =
7248 DAG.getConstantFP(1.5, VT.getScalarType());
7249 if (VT.isVector()) {
7250 assert(VT.getVectorNumElements() == 4 &&
7251 "Unknown vector type");
7252 FPThreeHalves = DAG.getNode(ISD::BUILD_VECTOR, dl, VT,
7253 FPThreeHalves, FPThreeHalves,
7254 FPThreeHalves, FPThreeHalves);
7257 SDValue Est = DAG.getNode(PPCISD::FRSQRTE, dl, VT, Op);
7258 DCI.AddToWorklist(Est.getNode());
7260 // We now need 0.5*Arg which we can write as (1.5*Arg - Arg) so that
7261 // this entire sequence requires only one FP constant.
7262 SDValue HalfArg = DAG.getNode(ISD::FMUL, dl, VT, FPThreeHalves, Op);
7263 DCI.AddToWorklist(HalfArg.getNode());
7265 HalfArg = DAG.getNode(ISD::FSUB, dl, VT, HalfArg, Op);
7266 DCI.AddToWorklist(HalfArg.getNode());
7268 // Newton iterations: Est = Est * (1.5 - HalfArg * Est * Est)
7269 for (int i = 0; i < Iterations; ++i) {
7270 SDValue NewEst = DAG.getNode(ISD::FMUL, dl, VT, Est, Est);
7271 DCI.AddToWorklist(NewEst.getNode());
7273 NewEst = DAG.getNode(ISD::FMUL, dl, VT, HalfArg, NewEst);
7274 DCI.AddToWorklist(NewEst.getNode());
7276 NewEst = DAG.getNode(ISD::FSUB, dl, VT, FPThreeHalves, NewEst);
7277 DCI.AddToWorklist(NewEst.getNode());
7279 Est = DAG.getNode(ISD::FMUL, dl, VT, Est, NewEst);
7280 DCI.AddToWorklist(Est.getNode());
7289 // Like SelectionDAG::isConsecutiveLoad, but also works for stores, and does
7290 // not enforce equality of the chain operands.
7291 static bool isConsecutiveLS(LSBaseSDNode *LS, LSBaseSDNode *Base,
7292 unsigned Bytes, int Dist,
7293 SelectionDAG &DAG) {
7294 EVT VT = LS->getMemoryVT();
7295 if (VT.getSizeInBits() / 8 != Bytes)
7298 SDValue Loc = LS->getBasePtr();
7299 SDValue BaseLoc = Base->getBasePtr();
7300 if (Loc.getOpcode() == ISD::FrameIndex) {
7301 if (BaseLoc.getOpcode() != ISD::FrameIndex)
7303 const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
7304 int FI = cast<FrameIndexSDNode>(Loc)->getIndex();
7305 int BFI = cast<FrameIndexSDNode>(BaseLoc)->getIndex();
7306 int FS = MFI->getObjectSize(FI);
7307 int BFS = MFI->getObjectSize(BFI);
7308 if (FS != BFS || FS != (int)Bytes) return false;
7309 return MFI->getObjectOffset(FI) == (MFI->getObjectOffset(BFI) + Dist*Bytes);
7313 if (DAG.isBaseWithConstantOffset(Loc) && Loc.getOperand(0) == BaseLoc &&
7314 cast<ConstantSDNode>(Loc.getOperand(1))->getSExtValue() == Dist*Bytes)
7317 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
7318 const GlobalValue *GV1 = nullptr;
7319 const GlobalValue *GV2 = nullptr;
7320 int64_t Offset1 = 0;
7321 int64_t Offset2 = 0;
7322 bool isGA1 = TLI.isGAPlusOffset(Loc.getNode(), GV1, Offset1);
7323 bool isGA2 = TLI.isGAPlusOffset(BaseLoc.getNode(), GV2, Offset2);
7324 if (isGA1 && isGA2 && GV1 == GV2)
7325 return Offset1 == (Offset2 + Dist*Bytes);
7329 // Return true is there is a nearyby consecutive load to the one provided
7330 // (regardless of alignment). We search up and down the chain, looking though
7331 // token factors and other loads (but nothing else). As a result, a true
7332 // results indicates that it is safe to create a new consecutive load adjacent
7333 // to the load provided.
7334 static bool findConsecutiveLoad(LoadSDNode *LD, SelectionDAG &DAG) {
7335 SDValue Chain = LD->getChain();
7336 EVT VT = LD->getMemoryVT();
7338 SmallSet<SDNode *, 16> LoadRoots;
7339 SmallVector<SDNode *, 8> Queue(1, Chain.getNode());
7340 SmallSet<SDNode *, 16> Visited;
7342 // First, search up the chain, branching to follow all token-factor operands.
7343 // If we find a consecutive load, then we're done, otherwise, record all
7344 // nodes just above the top-level loads and token factors.
7345 while (!Queue.empty()) {
7346 SDNode *ChainNext = Queue.pop_back_val();
7347 if (!Visited.insert(ChainNext))
7350 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(ChainNext)) {
7351 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7354 if (!Visited.count(ChainLD->getChain().getNode()))
7355 Queue.push_back(ChainLD->getChain().getNode());
7356 } else if (ChainNext->getOpcode() == ISD::TokenFactor) {
7357 for (SDNode::op_iterator O = ChainNext->op_begin(),
7358 OE = ChainNext->op_end(); O != OE; ++O)
7359 if (!Visited.count(O->getNode()))
7360 Queue.push_back(O->getNode());
7362 LoadRoots.insert(ChainNext);
7365 // Second, search down the chain, starting from the top-level nodes recorded
7366 // in the first phase. These top-level nodes are the nodes just above all
7367 // loads and token factors. Starting with their uses, recursively look though
7368 // all loads (just the chain uses) and token factors to find a consecutive
7373 for (SmallSet<SDNode *, 16>::iterator I = LoadRoots.begin(),
7374 IE = LoadRoots.end(); I != IE; ++I) {
7375 Queue.push_back(*I);
7377 while (!Queue.empty()) {
7378 SDNode *LoadRoot = Queue.pop_back_val();
7379 if (!Visited.insert(LoadRoot))
7382 if (LoadSDNode *ChainLD = dyn_cast<LoadSDNode>(LoadRoot))
7383 if (isConsecutiveLS(ChainLD, LD, VT.getStoreSize(), 1, DAG))
7386 for (SDNode::use_iterator UI = LoadRoot->use_begin(),
7387 UE = LoadRoot->use_end(); UI != UE; ++UI)
7388 if (((isa<LoadSDNode>(*UI) &&
7389 cast<LoadSDNode>(*UI)->getChain().getNode() == LoadRoot) ||
7390 UI->getOpcode() == ISD::TokenFactor) && !Visited.count(*UI))
7391 Queue.push_back(*UI);
7398 SDValue PPCTargetLowering::DAGCombineTruncBoolExt(SDNode *N,
7399 DAGCombinerInfo &DCI) const {
7400 SelectionDAG &DAG = DCI.DAG;
7403 assert(Subtarget.useCRBits() &&
7404 "Expecting to be tracking CR bits");
7405 // If we're tracking CR bits, we need to be careful that we don't have:
7406 // trunc(binary-ops(zext(x), zext(y)))
7408 // trunc(binary-ops(binary-ops(zext(x), zext(y)), ...)
7409 // such that we're unnecessarily moving things into GPRs when it would be
7410 // better to keep them in CR bits.
7412 // Note that trunc here can be an actual i1 trunc, or can be the effective
7413 // truncation that comes from a setcc or select_cc.
7414 if (N->getOpcode() == ISD::TRUNCATE &&
7415 N->getValueType(0) != MVT::i1)
7418 if (N->getOperand(0).getValueType() != MVT::i32 &&
7419 N->getOperand(0).getValueType() != MVT::i64)
7422 if (N->getOpcode() == ISD::SETCC ||
7423 N->getOpcode() == ISD::SELECT_CC) {
7424 // If we're looking at a comparison, then we need to make sure that the
7425 // high bits (all except for the first) don't matter the result.
7427 cast<CondCodeSDNode>(N->getOperand(
7428 N->getOpcode() == ISD::SETCC ? 2 : 4))->get();
7429 unsigned OpBits = N->getOperand(0).getValueSizeInBits();
7431 if (ISD::isSignedIntSetCC(CC)) {
7432 if (DAG.ComputeNumSignBits(N->getOperand(0)) != OpBits ||
7433 DAG.ComputeNumSignBits(N->getOperand(1)) != OpBits)
7435 } else if (ISD::isUnsignedIntSetCC(CC)) {
7436 if (!DAG.MaskedValueIsZero(N->getOperand(0),
7437 APInt::getHighBitsSet(OpBits, OpBits-1)) ||
7438 !DAG.MaskedValueIsZero(N->getOperand(1),
7439 APInt::getHighBitsSet(OpBits, OpBits-1)))
7442 // This is neither a signed nor an unsigned comparison, just make sure
7443 // that the high bits are equal.
7444 APInt Op1Zero, Op1One;
7445 APInt Op2Zero, Op2One;
7446 DAG.computeKnownBits(N->getOperand(0), Op1Zero, Op1One);
7447 DAG.computeKnownBits(N->getOperand(1), Op2Zero, Op2One);
7449 // We don't really care about what is known about the first bit (if
7450 // anything), so clear it in all masks prior to comparing them.
7451 Op1Zero.clearBit(0); Op1One.clearBit(0);
7452 Op2Zero.clearBit(0); Op2One.clearBit(0);
7454 if (Op1Zero != Op2Zero || Op1One != Op2One)
7459 // We now know that the higher-order bits are irrelevant, we just need to
7460 // make sure that all of the intermediate operations are bit operations, and
7461 // all inputs are extensions.
7462 if (N->getOperand(0).getOpcode() != ISD::AND &&
7463 N->getOperand(0).getOpcode() != ISD::OR &&
7464 N->getOperand(0).getOpcode() != ISD::XOR &&
7465 N->getOperand(0).getOpcode() != ISD::SELECT &&
7466 N->getOperand(0).getOpcode() != ISD::SELECT_CC &&
7467 N->getOperand(0).getOpcode() != ISD::TRUNCATE &&
7468 N->getOperand(0).getOpcode() != ISD::SIGN_EXTEND &&
7469 N->getOperand(0).getOpcode() != ISD::ZERO_EXTEND &&
7470 N->getOperand(0).getOpcode() != ISD::ANY_EXTEND)
7473 if ((N->getOpcode() == ISD::SETCC || N->getOpcode() == ISD::SELECT_CC) &&
7474 N->getOperand(1).getOpcode() != ISD::AND &&
7475 N->getOperand(1).getOpcode() != ISD::OR &&
7476 N->getOperand(1).getOpcode() != ISD::XOR &&
7477 N->getOperand(1).getOpcode() != ISD::SELECT &&
7478 N->getOperand(1).getOpcode() != ISD::SELECT_CC &&
7479 N->getOperand(1).getOpcode() != ISD::TRUNCATE &&
7480 N->getOperand(1).getOpcode() != ISD::SIGN_EXTEND &&
7481 N->getOperand(1).getOpcode() != ISD::ZERO_EXTEND &&
7482 N->getOperand(1).getOpcode() != ISD::ANY_EXTEND)
7485 SmallVector<SDValue, 4> Inputs;
7486 SmallVector<SDValue, 8> BinOps, PromOps;
7487 SmallPtrSet<SDNode *, 16> Visited;
7489 for (unsigned i = 0; i < 2; ++i) {
7490 if (((N->getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7491 N->getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7492 N->getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7493 N->getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7494 isa<ConstantSDNode>(N->getOperand(i)))
7495 Inputs.push_back(N->getOperand(i));
7497 BinOps.push_back(N->getOperand(i));
7499 if (N->getOpcode() == ISD::TRUNCATE)
7503 // Visit all inputs, collect all binary operations (and, or, xor and
7504 // select) that are all fed by extensions.
7505 while (!BinOps.empty()) {
7506 SDValue BinOp = BinOps.back();
7509 if (!Visited.insert(BinOp.getNode()))
7512 PromOps.push_back(BinOp);
7514 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7515 // The condition of the select is not promoted.
7516 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7518 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7521 if (((BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7522 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7523 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) &&
7524 BinOp.getOperand(i).getOperand(0).getValueType() == MVT::i1) ||
7525 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7526 Inputs.push_back(BinOp.getOperand(i));
7527 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7528 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7529 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7530 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7531 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC ||
7532 BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7533 BinOp.getOperand(i).getOpcode() == ISD::SIGN_EXTEND ||
7534 BinOp.getOperand(i).getOpcode() == ISD::ZERO_EXTEND ||
7535 BinOp.getOperand(i).getOpcode() == ISD::ANY_EXTEND) {
7536 BinOps.push_back(BinOp.getOperand(i));
7538 // We have an input that is not an extension or another binary
7539 // operation; we'll abort this transformation.
7545 // Make sure that this is a self-contained cluster of operations (which
7546 // is not quite the same thing as saying that everything has only one
7548 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7549 if (isa<ConstantSDNode>(Inputs[i]))
7552 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7553 UE = Inputs[i].getNode()->use_end();
7556 if (User != N && !Visited.count(User))
7559 // Make sure that we're not going to promote the non-output-value
7560 // operand(s) or SELECT or SELECT_CC.
7561 // FIXME: Although we could sometimes handle this, and it does occur in
7562 // practice that one of the condition inputs to the select is also one of
7563 // the outputs, we currently can't deal with this.
7564 if (User->getOpcode() == ISD::SELECT) {
7565 if (User->getOperand(0) == Inputs[i])
7567 } else if (User->getOpcode() == ISD::SELECT_CC) {
7568 if (User->getOperand(0) == Inputs[i] ||
7569 User->getOperand(1) == Inputs[i])
7575 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7576 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7577 UE = PromOps[i].getNode()->use_end();
7580 if (User != N && !Visited.count(User))
7583 // Make sure that we're not going to promote the non-output-value
7584 // operand(s) or SELECT or SELECT_CC.
7585 // FIXME: Although we could sometimes handle this, and it does occur in
7586 // practice that one of the condition inputs to the select is also one of
7587 // the outputs, we currently can't deal with this.
7588 if (User->getOpcode() == ISD::SELECT) {
7589 if (User->getOperand(0) == PromOps[i])
7591 } else if (User->getOpcode() == ISD::SELECT_CC) {
7592 if (User->getOperand(0) == PromOps[i] ||
7593 User->getOperand(1) == PromOps[i])
7599 // Replace all inputs with the extension operand.
7600 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7601 // Constants may have users outside the cluster of to-be-promoted nodes,
7602 // and so we need to replace those as we do the promotions.
7603 if (isa<ConstantSDNode>(Inputs[i]))
7606 DAG.ReplaceAllUsesOfValueWith(Inputs[i], Inputs[i].getOperand(0));
7609 // Replace all operations (these are all the same, but have a different
7610 // (i1) return type). DAG.getNode will validate that the types of
7611 // a binary operator match, so go through the list in reverse so that
7612 // we've likely promoted both operands first. Any intermediate truncations or
7613 // extensions disappear.
7614 while (!PromOps.empty()) {
7615 SDValue PromOp = PromOps.back();
7618 if (PromOp.getOpcode() == ISD::TRUNCATE ||
7619 PromOp.getOpcode() == ISD::SIGN_EXTEND ||
7620 PromOp.getOpcode() == ISD::ZERO_EXTEND ||
7621 PromOp.getOpcode() == ISD::ANY_EXTEND) {
7622 if (!isa<ConstantSDNode>(PromOp.getOperand(0)) &&
7623 PromOp.getOperand(0).getValueType() != MVT::i1) {
7624 // The operand is not yet ready (see comment below).
7625 PromOps.insert(PromOps.begin(), PromOp);
7629 SDValue RepValue = PromOp.getOperand(0);
7630 if (isa<ConstantSDNode>(RepValue))
7631 RepValue = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, RepValue);
7633 DAG.ReplaceAllUsesOfValueWith(PromOp, RepValue);
7638 switch (PromOp.getOpcode()) {
7639 default: C = 0; break;
7640 case ISD::SELECT: C = 1; break;
7641 case ISD::SELECT_CC: C = 2; break;
7644 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7645 PromOp.getOperand(C).getValueType() != MVT::i1) ||
7646 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7647 PromOp.getOperand(C+1).getValueType() != MVT::i1)) {
7648 // The to-be-promoted operands of this node have not yet been
7649 // promoted (this should be rare because we're going through the
7650 // list backward, but if one of the operands has several users in
7651 // this cluster of to-be-promoted nodes, it is possible).
7652 PromOps.insert(PromOps.begin(), PromOp);
7656 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7657 PromOp.getNode()->op_end());
7659 // If there are any constant inputs, make sure they're replaced now.
7660 for (unsigned i = 0; i < 2; ++i)
7661 if (isa<ConstantSDNode>(Ops[C+i]))
7662 Ops[C+i] = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ops[C+i]);
7664 DAG.ReplaceAllUsesOfValueWith(PromOp,
7665 DAG.getNode(PromOp.getOpcode(), dl, MVT::i1, Ops));
7668 // Now we're left with the initial truncation itself.
7669 if (N->getOpcode() == ISD::TRUNCATE)
7670 return N->getOperand(0);
7672 // Otherwise, this is a comparison. The operands to be compared have just
7673 // changed type (to i1), but everything else is the same.
7674 return SDValue(N, 0);
7677 SDValue PPCTargetLowering::DAGCombineExtBoolTrunc(SDNode *N,
7678 DAGCombinerInfo &DCI) const {
7679 SelectionDAG &DAG = DCI.DAG;
7682 // If we're tracking CR bits, we need to be careful that we don't have:
7683 // zext(binary-ops(trunc(x), trunc(y)))
7685 // zext(binary-ops(binary-ops(trunc(x), trunc(y)), ...)
7686 // such that we're unnecessarily moving things into CR bits that can more
7687 // efficiently stay in GPRs. Note that if we're not certain that the high
7688 // bits are set as required by the final extension, we still may need to do
7689 // some masking to get the proper behavior.
7691 // This same functionality is important on PPC64 when dealing with
7692 // 32-to-64-bit extensions; these occur often when 32-bit values are used as
7693 // the return values of functions. Because it is so similar, it is handled
7696 if (N->getValueType(0) != MVT::i32 &&
7697 N->getValueType(0) != MVT::i64)
7700 if (!((N->getOperand(0).getValueType() == MVT::i1 &&
7701 Subtarget.useCRBits()) ||
7702 (N->getOperand(0).getValueType() == MVT::i32 &&
7703 Subtarget.isPPC64())))
7706 if (N->getOperand(0).getOpcode() != ISD::AND &&
7707 N->getOperand(0).getOpcode() != ISD::OR &&
7708 N->getOperand(0).getOpcode() != ISD::XOR &&
7709 N->getOperand(0).getOpcode() != ISD::SELECT &&
7710 N->getOperand(0).getOpcode() != ISD::SELECT_CC)
7713 SmallVector<SDValue, 4> Inputs;
7714 SmallVector<SDValue, 8> BinOps(1, N->getOperand(0)), PromOps;
7715 SmallPtrSet<SDNode *, 16> Visited;
7717 // Visit all inputs, collect all binary operations (and, or, xor and
7718 // select) that are all fed by truncations.
7719 while (!BinOps.empty()) {
7720 SDValue BinOp = BinOps.back();
7723 if (!Visited.insert(BinOp.getNode()))
7726 PromOps.push_back(BinOp);
7728 for (unsigned i = 0, ie = BinOp.getNumOperands(); i != ie; ++i) {
7729 // The condition of the select is not promoted.
7730 if (BinOp.getOpcode() == ISD::SELECT && i == 0)
7732 if (BinOp.getOpcode() == ISD::SELECT_CC && i != 2 && i != 3)
7735 if (BinOp.getOperand(i).getOpcode() == ISD::TRUNCATE ||
7736 isa<ConstantSDNode>(BinOp.getOperand(i))) {
7737 Inputs.push_back(BinOp.getOperand(i));
7738 } else if (BinOp.getOperand(i).getOpcode() == ISD::AND ||
7739 BinOp.getOperand(i).getOpcode() == ISD::OR ||
7740 BinOp.getOperand(i).getOpcode() == ISD::XOR ||
7741 BinOp.getOperand(i).getOpcode() == ISD::SELECT ||
7742 BinOp.getOperand(i).getOpcode() == ISD::SELECT_CC) {
7743 BinOps.push_back(BinOp.getOperand(i));
7745 // We have an input that is not a truncation or another binary
7746 // operation; we'll abort this transformation.
7752 // Make sure that this is a self-contained cluster of operations (which
7753 // is not quite the same thing as saying that everything has only one
7755 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7756 if (isa<ConstantSDNode>(Inputs[i]))
7759 for (SDNode::use_iterator UI = Inputs[i].getNode()->use_begin(),
7760 UE = Inputs[i].getNode()->use_end();
7763 if (User != N && !Visited.count(User))
7766 // Make sure that we're not going to promote the non-output-value
7767 // operand(s) or SELECT or SELECT_CC.
7768 // FIXME: Although we could sometimes handle this, and it does occur in
7769 // practice that one of the condition inputs to the select is also one of
7770 // the outputs, we currently can't deal with this.
7771 if (User->getOpcode() == ISD::SELECT) {
7772 if (User->getOperand(0) == Inputs[i])
7774 } else if (User->getOpcode() == ISD::SELECT_CC) {
7775 if (User->getOperand(0) == Inputs[i] ||
7776 User->getOperand(1) == Inputs[i])
7782 for (unsigned i = 0, ie = PromOps.size(); i != ie; ++i) {
7783 for (SDNode::use_iterator UI = PromOps[i].getNode()->use_begin(),
7784 UE = PromOps[i].getNode()->use_end();
7787 if (User != N && !Visited.count(User))
7790 // Make sure that we're not going to promote the non-output-value
7791 // operand(s) or SELECT or SELECT_CC.
7792 // FIXME: Although we could sometimes handle this, and it does occur in
7793 // practice that one of the condition inputs to the select is also one of
7794 // the outputs, we currently can't deal with this.
7795 if (User->getOpcode() == ISD::SELECT) {
7796 if (User->getOperand(0) == PromOps[i])
7798 } else if (User->getOpcode() == ISD::SELECT_CC) {
7799 if (User->getOperand(0) == PromOps[i] ||
7800 User->getOperand(1) == PromOps[i])
7806 unsigned PromBits = N->getOperand(0).getValueSizeInBits();
7807 bool ReallyNeedsExt = false;
7808 if (N->getOpcode() != ISD::ANY_EXTEND) {
7809 // If all of the inputs are not already sign/zero extended, then
7810 // we'll still need to do that at the end.
7811 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7812 if (isa<ConstantSDNode>(Inputs[i]))
7816 Inputs[i].getOperand(0).getValueSizeInBits();
7817 assert(PromBits < OpBits && "Truncation not to a smaller bit count?");
7819 if ((N->getOpcode() == ISD::ZERO_EXTEND &&
7820 !DAG.MaskedValueIsZero(Inputs[i].getOperand(0),
7821 APInt::getHighBitsSet(OpBits,
7822 OpBits-PromBits))) ||
7823 (N->getOpcode() == ISD::SIGN_EXTEND &&
7824 DAG.ComputeNumSignBits(Inputs[i].getOperand(0)) <
7825 (OpBits-(PromBits-1)))) {
7826 ReallyNeedsExt = true;
7832 // Replace all inputs, either with the truncation operand, or a
7833 // truncation or extension to the final output type.
7834 for (unsigned i = 0, ie = Inputs.size(); i != ie; ++i) {
7835 // Constant inputs need to be replaced with the to-be-promoted nodes that
7836 // use them because they might have users outside of the cluster of
7838 if (isa<ConstantSDNode>(Inputs[i]))
7841 SDValue InSrc = Inputs[i].getOperand(0);
7842 if (Inputs[i].getValueType() == N->getValueType(0))
7843 DAG.ReplaceAllUsesOfValueWith(Inputs[i], InSrc);
7844 else if (N->getOpcode() == ISD::SIGN_EXTEND)
7845 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7846 DAG.getSExtOrTrunc(InSrc, dl, N->getValueType(0)));
7847 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7848 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7849 DAG.getZExtOrTrunc(InSrc, dl, N->getValueType(0)));
7851 DAG.ReplaceAllUsesOfValueWith(Inputs[i],
7852 DAG.getAnyExtOrTrunc(InSrc, dl, N->getValueType(0)));
7855 // Replace all operations (these are all the same, but have a different
7856 // (promoted) return type). DAG.getNode will validate that the types of
7857 // a binary operator match, so go through the list in reverse so that
7858 // we've likely promoted both operands first.
7859 while (!PromOps.empty()) {
7860 SDValue PromOp = PromOps.back();
7864 switch (PromOp.getOpcode()) {
7865 default: C = 0; break;
7866 case ISD::SELECT: C = 1; break;
7867 case ISD::SELECT_CC: C = 2; break;
7870 if ((!isa<ConstantSDNode>(PromOp.getOperand(C)) &&
7871 PromOp.getOperand(C).getValueType() != N->getValueType(0)) ||
7872 (!isa<ConstantSDNode>(PromOp.getOperand(C+1)) &&
7873 PromOp.getOperand(C+1).getValueType() != N->getValueType(0))) {
7874 // The to-be-promoted operands of this node have not yet been
7875 // promoted (this should be rare because we're going through the
7876 // list backward, but if one of the operands has several users in
7877 // this cluster of to-be-promoted nodes, it is possible).
7878 PromOps.insert(PromOps.begin(), PromOp);
7882 SmallVector<SDValue, 3> Ops(PromOp.getNode()->op_begin(),
7883 PromOp.getNode()->op_end());
7885 // If this node has constant inputs, then they'll need to be promoted here.
7886 for (unsigned i = 0; i < 2; ++i) {
7887 if (!isa<ConstantSDNode>(Ops[C+i]))
7889 if (Ops[C+i].getValueType() == N->getValueType(0))
7892 if (N->getOpcode() == ISD::SIGN_EXTEND)
7893 Ops[C+i] = DAG.getSExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7894 else if (N->getOpcode() == ISD::ZERO_EXTEND)
7895 Ops[C+i] = DAG.getZExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7897 Ops[C+i] = DAG.getAnyExtOrTrunc(Ops[C+i], dl, N->getValueType(0));
7900 DAG.ReplaceAllUsesOfValueWith(PromOp,
7901 DAG.getNode(PromOp.getOpcode(), dl, N->getValueType(0), Ops));
7904 // Now we're left with the initial extension itself.
7905 if (!ReallyNeedsExt)
7906 return N->getOperand(0);
7908 // To zero extend, just mask off everything except for the first bit (in the
7910 if (N->getOpcode() == ISD::ZERO_EXTEND)
7911 return DAG.getNode(ISD::AND, dl, N->getValueType(0), N->getOperand(0),
7912 DAG.getConstant(APInt::getLowBitsSet(
7913 N->getValueSizeInBits(0), PromBits),
7914 N->getValueType(0)));
7916 assert(N->getOpcode() == ISD::SIGN_EXTEND &&
7917 "Invalid extension type");
7918 EVT ShiftAmountTy = getShiftAmountTy(N->getValueType(0));
7920 DAG.getConstant(N->getValueSizeInBits(0)-PromBits, ShiftAmountTy);
7921 return DAG.getNode(ISD::SRA, dl, N->getValueType(0),
7922 DAG.getNode(ISD::SHL, dl, N->getValueType(0),
7923 N->getOperand(0), ShiftCst), ShiftCst);
7926 SDValue PPCTargetLowering::PerformDAGCombine(SDNode *N,
7927 DAGCombinerInfo &DCI) const {
7928 const TargetMachine &TM = getTargetMachine();
7929 SelectionDAG &DAG = DCI.DAG;
7931 switch (N->getOpcode()) {
7934 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7935 if (C->isNullValue()) // 0 << V -> 0.
7936 return N->getOperand(0);
7940 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7941 if (C->isNullValue()) // 0 >>u V -> 0.
7942 return N->getOperand(0);
7946 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(0))) {
7947 if (C->isNullValue() || // 0 >>s V -> 0.
7948 C->isAllOnesValue()) // -1 >>s V -> -1.
7949 return N->getOperand(0);
7952 case ISD::SIGN_EXTEND:
7953 case ISD::ZERO_EXTEND:
7954 case ISD::ANY_EXTEND:
7955 return DAGCombineExtBoolTrunc(N, DCI);
7958 case ISD::SELECT_CC:
7959 return DAGCombineTruncBoolExt(N, DCI);
7961 assert(TM.Options.UnsafeFPMath &&
7962 "Reciprocal estimates require UnsafeFPMath");
7964 if (N->getOperand(1).getOpcode() == ISD::FSQRT) {
7966 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0), DCI);
7968 DCI.AddToWorklist(RV.getNode());
7969 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7970 N->getOperand(0), RV);
7972 } else if (N->getOperand(1).getOpcode() == ISD::FP_EXTEND &&
7973 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7975 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7978 DCI.AddToWorklist(RV.getNode());
7979 RV = DAG.getNode(ISD::FP_EXTEND, SDLoc(N->getOperand(1)),
7980 N->getValueType(0), RV);
7981 DCI.AddToWorklist(RV.getNode());
7982 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7983 N->getOperand(0), RV);
7985 } else if (N->getOperand(1).getOpcode() == ISD::FP_ROUND &&
7986 N->getOperand(1).getOperand(0).getOpcode() == ISD::FSQRT) {
7988 DAGCombineFastRecipFSQRT(N->getOperand(1).getOperand(0).getOperand(0),
7991 DCI.AddToWorklist(RV.getNode());
7992 RV = DAG.getNode(ISD::FP_ROUND, SDLoc(N->getOperand(1)),
7993 N->getValueType(0), RV,
7994 N->getOperand(1).getOperand(1));
7995 DCI.AddToWorklist(RV.getNode());
7996 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
7997 N->getOperand(0), RV);
8001 SDValue RV = DAGCombineFastRecip(N->getOperand(1), DCI);
8003 DCI.AddToWorklist(RV.getNode());
8004 return DAG.getNode(ISD::FMUL, dl, N->getValueType(0),
8005 N->getOperand(0), RV);
8011 assert(TM.Options.UnsafeFPMath &&
8012 "Reciprocal estimates require UnsafeFPMath");
8014 // Compute this as 1/(1/sqrt(X)), which is the reciprocal of the
8016 SDValue RV = DAGCombineFastRecipFSQRT(N->getOperand(0), DCI);
8018 DCI.AddToWorklist(RV.getNode());
8019 RV = DAGCombineFastRecip(RV, DCI);
8021 // Unfortunately, RV is now NaN if the input was exactly 0. Select out
8022 // this case and force the answer to 0.
8024 EVT VT = RV.getValueType();
8026 SDValue Zero = DAG.getConstantFP(0.0, VT.getScalarType());
8027 if (VT.isVector()) {
8028 assert(VT.getVectorNumElements() == 4 && "Unknown vector type");
8029 Zero = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, Zero, Zero, Zero, Zero);
8033 DAG.getSetCC(dl, getSetCCResultType(*DAG.getContext(), VT),
8034 N->getOperand(0), Zero, ISD::SETEQ);
8035 DCI.AddToWorklist(ZeroCmp.getNode());
8036 DCI.AddToWorklist(RV.getNode());
8038 RV = DAG.getNode(VT.isVector() ? ISD::VSELECT : ISD::SELECT, dl, VT,
8046 case ISD::SINT_TO_FP:
8047 if (TM.getSubtarget<PPCSubtarget>().has64BitSupport()) {
8048 if (N->getOperand(0).getOpcode() == ISD::FP_TO_SINT) {
8049 // Turn (sint_to_fp (fp_to_sint X)) -> fctidz/fcfid without load/stores.
8050 // We allow the src/dst to be either f32/f64, but the intermediate
8051 // type must be i64.
8052 if (N->getOperand(0).getValueType() == MVT::i64 &&
8053 N->getOperand(0).getOperand(0).getValueType() != MVT::ppcf128) {
8054 SDValue Val = N->getOperand(0).getOperand(0);
8055 if (Val.getValueType() == MVT::f32) {
8056 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8057 DCI.AddToWorklist(Val.getNode());
8060 Val = DAG.getNode(PPCISD::FCTIDZ, dl, MVT::f64, Val);
8061 DCI.AddToWorklist(Val.getNode());
8062 Val = DAG.getNode(PPCISD::FCFID, dl, MVT::f64, Val);
8063 DCI.AddToWorklist(Val.getNode());
8064 if (N->getValueType(0) == MVT::f32) {
8065 Val = DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Val,
8066 DAG.getIntPtrConstant(0));
8067 DCI.AddToWorklist(Val.getNode());
8070 } else if (N->getOperand(0).getValueType() == MVT::i32) {
8071 // If the intermediate type is i32, we can avoid the load/store here
8078 // Turn STORE (FP_TO_SINT F) -> STFIWX(FCTIWZ(F)).
8079 if (TM.getSubtarget<PPCSubtarget>().hasSTFIWX() &&
8080 !cast<StoreSDNode>(N)->isTruncatingStore() &&
8081 N->getOperand(1).getOpcode() == ISD::FP_TO_SINT &&
8082 N->getOperand(1).getValueType() == MVT::i32 &&
8083 N->getOperand(1).getOperand(0).getValueType() != MVT::ppcf128) {
8084 SDValue Val = N->getOperand(1).getOperand(0);
8085 if (Val.getValueType() == MVT::f32) {
8086 Val = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f64, Val);
8087 DCI.AddToWorklist(Val.getNode());
8089 Val = DAG.getNode(PPCISD::FCTIWZ, dl, MVT::f64, Val);
8090 DCI.AddToWorklist(Val.getNode());
8093 N->getOperand(0), Val, N->getOperand(2),
8094 DAG.getValueType(N->getOperand(1).getValueType())
8097 Val = DAG.getMemIntrinsicNode(PPCISD::STFIWX, dl,
8098 DAG.getVTList(MVT::Other), Ops,
8099 cast<StoreSDNode>(N)->getMemoryVT(),
8100 cast<StoreSDNode>(N)->getMemOperand());
8101 DCI.AddToWorklist(Val.getNode());
8105 // Turn STORE (BSWAP) -> sthbrx/stwbrx.
8106 if (cast<StoreSDNode>(N)->isUnindexed() &&
8107 N->getOperand(1).getOpcode() == ISD::BSWAP &&
8108 N->getOperand(1).getNode()->hasOneUse() &&
8109 (N->getOperand(1).getValueType() == MVT::i32 ||
8110 N->getOperand(1).getValueType() == MVT::i16 ||
8111 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8112 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8113 N->getOperand(1).getValueType() == MVT::i64))) {
8114 SDValue BSwapOp = N->getOperand(1).getOperand(0);
8115 // Do an any-extend to 32-bits if this is a half-word input.
8116 if (BSwapOp.getValueType() == MVT::i16)
8117 BSwapOp = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, BSwapOp);
8120 N->getOperand(0), BSwapOp, N->getOperand(2),
8121 DAG.getValueType(N->getOperand(1).getValueType())
8124 DAG.getMemIntrinsicNode(PPCISD::STBRX, dl, DAG.getVTList(MVT::Other),
8125 Ops, cast<StoreSDNode>(N)->getMemoryVT(),
8126 cast<StoreSDNode>(N)->getMemOperand());
8130 LoadSDNode *LD = cast<LoadSDNode>(N);
8131 EVT VT = LD->getValueType(0);
8132 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext());
8133 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(Ty);
8134 if (ISD::isNON_EXTLoad(N) && VT.isVector() &&
8135 TM.getSubtarget<PPCSubtarget>().hasAltivec() &&
8136 (VT == MVT::v16i8 || VT == MVT::v8i16 ||
8137 VT == MVT::v4i32 || VT == MVT::v4f32) &&
8138 LD->getAlignment() < ABIAlignment) {
8139 // This is a type-legal unaligned Altivec load.
8140 SDValue Chain = LD->getChain();
8141 SDValue Ptr = LD->getBasePtr();
8142 bool isLittleEndian = Subtarget.isLittleEndian();
8144 // This implements the loading of unaligned vectors as described in
8145 // the venerable Apple Velocity Engine overview. Specifically:
8146 // https://developer.apple.com/hardwaredrivers/ve/alignment.html
8147 // https://developer.apple.com/hardwaredrivers/ve/code_optimization.html
8149 // The general idea is to expand a sequence of one or more unaligned
8150 // loads into an alignment-based permutation-control instruction (lvsl
8151 // or lvsr), a series of regular vector loads (which always truncate
8152 // their input address to an aligned address), and a series of
8153 // permutations. The results of these permutations are the requested
8154 // loaded values. The trick is that the last "extra" load is not taken
8155 // from the address you might suspect (sizeof(vector) bytes after the
8156 // last requested load), but rather sizeof(vector) - 1 bytes after the
8157 // last requested vector. The point of this is to avoid a page fault if
8158 // the base address happened to be aligned. This works because if the
8159 // base address is aligned, then adding less than a full vector length
8160 // will cause the last vector in the sequence to be (re)loaded.
8161 // Otherwise, the next vector will be fetched as you might suspect was
8164 // We might be able to reuse the permutation generation from
8165 // a different base address offset from this one by an aligned amount.
8166 // The INTRINSIC_WO_CHAIN DAG combine will attempt to perform this
8167 // optimization later.
8168 Intrinsic::ID Intr = (isLittleEndian ?
8169 Intrinsic::ppc_altivec_lvsr :
8170 Intrinsic::ppc_altivec_lvsl);
8171 SDValue PermCntl = BuildIntrinsicOp(Intr, Ptr, DAG, dl, MVT::v16i8);
8173 // Refine the alignment of the original load (a "new" load created here
8174 // which was identical to the first except for the alignment would be
8175 // merged with the existing node regardless).
8176 MachineFunction &MF = DAG.getMachineFunction();
8177 MachineMemOperand *MMO =
8178 MF.getMachineMemOperand(LD->getPointerInfo(),
8179 LD->getMemOperand()->getFlags(),
8180 LD->getMemoryVT().getStoreSize(),
8182 LD->refineAlignment(MMO);
8183 SDValue BaseLoad = SDValue(LD, 0);
8185 // Note that the value of IncOffset (which is provided to the next
8186 // load's pointer info offset value, and thus used to calculate the
8187 // alignment), and the value of IncValue (which is actually used to
8188 // increment the pointer value) are different! This is because we
8189 // require the next load to appear to be aligned, even though it
8190 // is actually offset from the base pointer by a lesser amount.
8191 int IncOffset = VT.getSizeInBits() / 8;
8192 int IncValue = IncOffset;
8194 // Walk (both up and down) the chain looking for another load at the real
8195 // (aligned) offset (the alignment of the other load does not matter in
8196 // this case). If found, then do not use the offset reduction trick, as
8197 // that will prevent the loads from being later combined (as they would
8198 // otherwise be duplicates).
8199 if (!findConsecutiveLoad(LD, DAG))
8202 SDValue Increment = DAG.getConstant(IncValue, getPointerTy());
8203 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment);
8206 DAG.getLoad(VT, dl, Chain, Ptr,
8207 LD->getPointerInfo().getWithOffset(IncOffset),
8208 LD->isVolatile(), LD->isNonTemporal(),
8209 LD->isInvariant(), ABIAlignment);
8211 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
8212 BaseLoad.getValue(1), ExtraLoad.getValue(1));
8214 if (BaseLoad.getValueType() != MVT::v4i32)
8215 BaseLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, BaseLoad);
8217 if (ExtraLoad.getValueType() != MVT::v4i32)
8218 ExtraLoad = DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, ExtraLoad);
8220 // Because vperm has a big-endian bias, we must reverse the order
8221 // of the input vectors and complement the permute control vector
8222 // when generating little endian code. We have already handled the
8223 // latter by using lvsr instead of lvsl, so just reverse BaseLoad
8224 // and ExtraLoad here.
8227 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8228 ExtraLoad, BaseLoad, PermCntl, DAG, dl);
8230 Perm = BuildIntrinsicOp(Intrinsic::ppc_altivec_vperm,
8231 BaseLoad, ExtraLoad, PermCntl, DAG, dl);
8233 if (VT != MVT::v4i32)
8234 Perm = DAG.getNode(ISD::BITCAST, dl, VT, Perm);
8236 // Now we need to be really careful about how we update the users of the
8237 // original load. We cannot just call DCI.CombineTo (or
8238 // DAG.ReplaceAllUsesWith for that matter), because the load still has
8239 // uses created here (the permutation for example) that need to stay.
8240 SDNode::use_iterator UI = N->use_begin(), UE = N->use_end();
8242 SDUse &Use = UI.getUse();
8244 // Note: BaseLoad is checked here because it might not be N, but a
8246 if (User == Perm.getNode() || User == BaseLoad.getNode() ||
8247 User == TF.getNode() || Use.getResNo() > 1) {
8252 SDValue To = Use.getResNo() ? TF : Perm;
8255 SmallVector<SDValue, 8> Ops;
8256 for (SDNode::op_iterator O = User->op_begin(),
8257 OE = User->op_end(); O != OE; ++O) {
8264 DAG.UpdateNodeOperands(User, Ops);
8267 return SDValue(N, 0);
8271 case ISD::INTRINSIC_WO_CHAIN: {
8272 bool isLittleEndian = Subtarget.isLittleEndian();
8273 Intrinsic::ID Intr = (isLittleEndian ?
8274 Intrinsic::ppc_altivec_lvsr :
8275 Intrinsic::ppc_altivec_lvsl);
8276 if (cast<ConstantSDNode>(N->getOperand(0))->getZExtValue() == Intr &&
8277 N->getOperand(1)->getOpcode() == ISD::ADD) {
8278 SDValue Add = N->getOperand(1);
8280 if (DAG.MaskedValueIsZero(Add->getOperand(1),
8281 APInt::getAllOnesValue(4 /* 16 byte alignment */).zext(
8282 Add.getValueType().getScalarType().getSizeInBits()))) {
8283 SDNode *BasePtr = Add->getOperand(0).getNode();
8284 for (SDNode::use_iterator UI = BasePtr->use_begin(),
8285 UE = BasePtr->use_end(); UI != UE; ++UI) {
8286 if (UI->getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8287 cast<ConstantSDNode>(UI->getOperand(0))->getZExtValue() ==
8289 // We've found another LVSL/LVSR, and this address is an aligned
8290 // multiple of that one. The results will be the same, so use the
8291 // one we've just found instead.
8293 return SDValue(*UI, 0);
8302 // Turn BSWAP (LOAD) -> lhbrx/lwbrx.
8303 if (ISD::isNON_EXTLoad(N->getOperand(0).getNode()) &&
8304 N->getOperand(0).hasOneUse() &&
8305 (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i16 ||
8306 (TM.getSubtarget<PPCSubtarget>().hasLDBRX() &&
8307 TM.getSubtarget<PPCSubtarget>().isPPC64() &&
8308 N->getValueType(0) == MVT::i64))) {
8309 SDValue Load = N->getOperand(0);
8310 LoadSDNode *LD = cast<LoadSDNode>(Load);
8311 // Create the byte-swapping load.
8313 LD->getChain(), // Chain
8314 LD->getBasePtr(), // Ptr
8315 DAG.getValueType(N->getValueType(0)) // VT
8318 DAG.getMemIntrinsicNode(PPCISD::LBRX, dl,
8319 DAG.getVTList(N->getValueType(0) == MVT::i64 ?
8320 MVT::i64 : MVT::i32, MVT::Other),
8321 Ops, LD->getMemoryVT(), LD->getMemOperand());
8323 // If this is an i16 load, insert the truncate.
8324 SDValue ResVal = BSLoad;
8325 if (N->getValueType(0) == MVT::i16)
8326 ResVal = DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, BSLoad);
8328 // First, combine the bswap away. This makes the value produced by the
8330 DCI.CombineTo(N, ResVal);
8332 // Next, combine the load away, we give it a bogus result value but a real
8333 // chain result. The result value is dead because the bswap is dead.
8334 DCI.CombineTo(Load.getNode(), ResVal, BSLoad.getValue(1));
8336 // Return N so it doesn't get rechecked!
8337 return SDValue(N, 0);
8341 case PPCISD::VCMP: {
8342 // If a VCMPo node already exists with exactly the same operands as this
8343 // node, use its result instead of this node (VCMPo computes both a CR6 and
8344 // a normal output).
8346 if (!N->getOperand(0).hasOneUse() &&
8347 !N->getOperand(1).hasOneUse() &&
8348 !N->getOperand(2).hasOneUse()) {
8350 // Scan all of the users of the LHS, looking for VCMPo's that match.
8351 SDNode *VCMPoNode = nullptr;
8353 SDNode *LHSN = N->getOperand(0).getNode();
8354 for (SDNode::use_iterator UI = LHSN->use_begin(), E = LHSN->use_end();
8356 if (UI->getOpcode() == PPCISD::VCMPo &&
8357 UI->getOperand(1) == N->getOperand(1) &&
8358 UI->getOperand(2) == N->getOperand(2) &&
8359 UI->getOperand(0) == N->getOperand(0)) {
8364 // If there is no VCMPo node, or if the flag value has a single use, don't
8366 if (!VCMPoNode || VCMPoNode->hasNUsesOfValue(0, 1))
8369 // Look at the (necessarily single) use of the flag value. If it has a
8370 // chain, this transformation is more complex. Note that multiple things
8371 // could use the value result, which we should ignore.
8372 SDNode *FlagUser = nullptr;
8373 for (SDNode::use_iterator UI = VCMPoNode->use_begin();
8374 FlagUser == nullptr; ++UI) {
8375 assert(UI != VCMPoNode->use_end() && "Didn't find user!");
8377 for (unsigned i = 0, e = User->getNumOperands(); i != e; ++i) {
8378 if (User->getOperand(i) == SDValue(VCMPoNode, 1)) {
8385 // If the user is a MFOCRF instruction, we know this is safe.
8386 // Otherwise we give up for right now.
8387 if (FlagUser->getOpcode() == PPCISD::MFOCRF)
8388 return SDValue(VCMPoNode, 0);
8393 SDValue Cond = N->getOperand(1);
8394 SDValue Target = N->getOperand(2);
8396 if (Cond.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8397 cast<ConstantSDNode>(Cond.getOperand(1))->getZExtValue() ==
8398 Intrinsic::ppc_is_decremented_ctr_nonzero) {
8400 // We now need to make the intrinsic dead (it cannot be instruction
8402 DAG.ReplaceAllUsesOfValueWith(Cond.getValue(1), Cond.getOperand(0));
8403 assert(Cond.getNode()->hasOneUse() &&
8404 "Counter decrement has more than one use");
8406 return DAG.getNode(PPCISD::BDNZ, dl, MVT::Other,
8407 N->getOperand(0), Target);
8412 // If this is a branch on an altivec predicate comparison, lower this so
8413 // that we don't have to do a MFOCRF: instead, branch directly on CR6. This
8414 // lowering is done pre-legalize, because the legalizer lowers the predicate
8415 // compare down to code that is difficult to reassemble.
8416 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get();
8417 SDValue LHS = N->getOperand(2), RHS = N->getOperand(3);
8419 // Sometimes the promoted value of the intrinsic is ANDed by some non-zero
8420 // value. If so, pass-through the AND to get to the intrinsic.
8421 if (LHS.getOpcode() == ISD::AND &&
8422 LHS.getOperand(0).getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8423 cast<ConstantSDNode>(LHS.getOperand(0).getOperand(1))->getZExtValue() ==
8424 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8425 isa<ConstantSDNode>(LHS.getOperand(1)) &&
8426 !cast<ConstantSDNode>(LHS.getOperand(1))->getConstantIntValue()->
8428 LHS = LHS.getOperand(0);
8430 if (LHS.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
8431 cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue() ==
8432 Intrinsic::ppc_is_decremented_ctr_nonzero &&
8433 isa<ConstantSDNode>(RHS)) {
8434 assert((CC == ISD::SETEQ || CC == ISD::SETNE) &&
8435 "Counter decrement comparison is not EQ or NE");
8437 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8438 bool isBDNZ = (CC == ISD::SETEQ && Val) ||
8439 (CC == ISD::SETNE && !Val);
8441 // We now need to make the intrinsic dead (it cannot be instruction
8443 DAG.ReplaceAllUsesOfValueWith(LHS.getValue(1), LHS.getOperand(0));
8444 assert(LHS.getNode()->hasOneUse() &&
8445 "Counter decrement has more than one use");
8447 return DAG.getNode(isBDNZ ? PPCISD::BDNZ : PPCISD::BDZ, dl, MVT::Other,
8448 N->getOperand(0), N->getOperand(4));
8454 if (LHS.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
8455 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) &&
8456 getAltivecCompareInfo(LHS, CompareOpc, isDot)) {
8457 assert(isDot && "Can't compare against a vector result!");
8459 // If this is a comparison against something other than 0/1, then we know
8460 // that the condition is never/always true.
8461 unsigned Val = cast<ConstantSDNode>(RHS)->getZExtValue();
8462 if (Val != 0 && Val != 1) {
8463 if (CC == ISD::SETEQ) // Cond never true, remove branch.
8464 return N->getOperand(0);
8465 // Always !=, turn it into an unconditional branch.
8466 return DAG.getNode(ISD::BR, dl, MVT::Other,
8467 N->getOperand(0), N->getOperand(4));
8470 bool BranchOnWhenPredTrue = (CC == ISD::SETEQ) ^ (Val == 0);
8472 // Create the PPCISD altivec 'dot' comparison node.
8474 LHS.getOperand(2), // LHS of compare
8475 LHS.getOperand(3), // RHS of compare
8476 DAG.getConstant(CompareOpc, MVT::i32)
8478 EVT VTs[] = { LHS.getOperand(2).getValueType(), MVT::Glue };
8479 SDValue CompNode = DAG.getNode(PPCISD::VCMPo, dl, VTs, Ops);
8481 // Unpack the result based on how the target uses it.
8482 PPC::Predicate CompOpc;
8483 switch (cast<ConstantSDNode>(LHS.getOperand(1))->getZExtValue()) {
8484 default: // Can't happen, don't crash on invalid number though.
8485 case 0: // Branch on the value of the EQ bit of CR6.
8486 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_EQ : PPC::PRED_NE;
8488 case 1: // Branch on the inverted value of the EQ bit of CR6.
8489 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_NE : PPC::PRED_EQ;
8491 case 2: // Branch on the value of the LT bit of CR6.
8492 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_LT : PPC::PRED_GE;
8494 case 3: // Branch on the inverted value of the LT bit of CR6.
8495 CompOpc = BranchOnWhenPredTrue ? PPC::PRED_GE : PPC::PRED_LT;
8499 return DAG.getNode(PPCISD::COND_BRANCH, dl, MVT::Other, N->getOperand(0),
8500 DAG.getConstant(CompOpc, MVT::i32),
8501 DAG.getRegister(PPC::CR6, MVT::i32),
8502 N->getOperand(4), CompNode.getValue(1));
8511 //===----------------------------------------------------------------------===//
8512 // Inline Assembly Support
8513 //===----------------------------------------------------------------------===//
8515 void PPCTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
8518 const SelectionDAG &DAG,
8519 unsigned Depth) const {
8520 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
8521 switch (Op.getOpcode()) {
8523 case PPCISD::LBRX: {
8524 // lhbrx is known to have the top bits cleared out.
8525 if (cast<VTSDNode>(Op.getOperand(2))->getVT() == MVT::i16)
8526 KnownZero = 0xFFFF0000;
8529 case ISD::INTRINSIC_WO_CHAIN: {
8530 switch (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue()) {
8532 case Intrinsic::ppc_altivec_vcmpbfp_p:
8533 case Intrinsic::ppc_altivec_vcmpeqfp_p:
8534 case Intrinsic::ppc_altivec_vcmpequb_p:
8535 case Intrinsic::ppc_altivec_vcmpequh_p:
8536 case Intrinsic::ppc_altivec_vcmpequw_p:
8537 case Intrinsic::ppc_altivec_vcmpgefp_p:
8538 case Intrinsic::ppc_altivec_vcmpgtfp_p:
8539 case Intrinsic::ppc_altivec_vcmpgtsb_p:
8540 case Intrinsic::ppc_altivec_vcmpgtsh_p:
8541 case Intrinsic::ppc_altivec_vcmpgtsw_p:
8542 case Intrinsic::ppc_altivec_vcmpgtub_p:
8543 case Intrinsic::ppc_altivec_vcmpgtuh_p:
8544 case Intrinsic::ppc_altivec_vcmpgtuw_p:
8545 KnownZero = ~1U; // All bits but the low one are known to be zero.
8553 /// getConstraintType - Given a constraint, return the type of
8554 /// constraint it is for this target.
8555 PPCTargetLowering::ConstraintType
8556 PPCTargetLowering::getConstraintType(const std::string &Constraint) const {
8557 if (Constraint.size() == 1) {
8558 switch (Constraint[0]) {
8565 return C_RegisterClass;
8567 // FIXME: While Z does indicate a memory constraint, it specifically
8568 // indicates an r+r address (used in conjunction with the 'y' modifier
8569 // in the replacement string). Currently, we're forcing the base
8570 // register to be r0 in the asm printer (which is interpreted as zero)
8571 // and forming the complete address in the second register. This is
8575 } else if (Constraint == "wc") { // individual CR bits.
8576 return C_RegisterClass;
8577 } else if (Constraint == "wa" || Constraint == "wd" ||
8578 Constraint == "wf" || Constraint == "ws") {
8579 return C_RegisterClass; // VSX registers.
8581 return TargetLowering::getConstraintType(Constraint);
8584 /// Examine constraint type and operand type and determine a weight value.
8585 /// This object must already have been set up with the operand type
8586 /// and the current alternative constraint selected.
8587 TargetLowering::ConstraintWeight
8588 PPCTargetLowering::getSingleConstraintMatchWeight(
8589 AsmOperandInfo &info, const char *constraint) const {
8590 ConstraintWeight weight = CW_Invalid;
8591 Value *CallOperandVal = info.CallOperandVal;
8592 // If we don't have a value, we can't do a match,
8593 // but allow it at the lowest weight.
8594 if (!CallOperandVal)
8596 Type *type = CallOperandVal->getType();
8598 // Look at the constraint type.
8599 if (StringRef(constraint) == "wc" && type->isIntegerTy(1))
8600 return CW_Register; // an individual CR bit.
8601 else if ((StringRef(constraint) == "wa" ||
8602 StringRef(constraint) == "wd" ||
8603 StringRef(constraint) == "wf") &&
8606 else if (StringRef(constraint) == "ws" && type->isDoubleTy())
8609 switch (*constraint) {
8611 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
8614 if (type->isIntegerTy())
8615 weight = CW_Register;
8618 if (type->isFloatTy())
8619 weight = CW_Register;
8622 if (type->isDoubleTy())
8623 weight = CW_Register;
8626 if (type->isVectorTy())
8627 weight = CW_Register;
8630 weight = CW_Register;
8639 std::pair<unsigned, const TargetRegisterClass*>
8640 PPCTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
8642 if (Constraint.size() == 1) {
8643 // GCC RS6000 Constraint Letters
8644 switch (Constraint[0]) {
8646 if (VT == MVT::i64 && Subtarget.isPPC64())
8647 return std::make_pair(0U, &PPC::G8RC_NOX0RegClass);
8648 return std::make_pair(0U, &PPC::GPRC_NOR0RegClass);
8650 if (VT == MVT::i64 && Subtarget.isPPC64())
8651 return std::make_pair(0U, &PPC::G8RCRegClass);
8652 return std::make_pair(0U, &PPC::GPRCRegClass);
8654 if (VT == MVT::f32 || VT == MVT::i32)
8655 return std::make_pair(0U, &PPC::F4RCRegClass);
8656 if (VT == MVT::f64 || VT == MVT::i64)
8657 return std::make_pair(0U, &PPC::F8RCRegClass);
8660 return std::make_pair(0U, &PPC::VRRCRegClass);
8662 return std::make_pair(0U, &PPC::CRRCRegClass);
8664 } else if (Constraint == "wc") { // an individual CR bit.
8665 return std::make_pair(0U, &PPC::CRBITRCRegClass);
8666 } else if (Constraint == "wa" || Constraint == "wd" ||
8667 Constraint == "wf") {
8668 return std::make_pair(0U, &PPC::VSRCRegClass);
8669 } else if (Constraint == "ws") {
8670 return std::make_pair(0U, &PPC::VSFRCRegClass);
8673 std::pair<unsigned, const TargetRegisterClass*> R =
8674 TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
8676 // r[0-9]+ are used, on PPC64, to refer to the corresponding 64-bit registers
8677 // (which we call X[0-9]+). If a 64-bit value has been requested, and a
8678 // 32-bit GPR has been selected, then 'upgrade' it to the 64-bit parent
8680 // FIXME: If TargetLowering::getRegForInlineAsmConstraint could somehow use
8681 // the AsmName field from *RegisterInfo.td, then this would not be necessary.
8682 if (R.first && VT == MVT::i64 && Subtarget.isPPC64() &&
8683 PPC::GPRCRegClass.contains(R.first)) {
8684 const TargetRegisterInfo *TRI = getTargetMachine().getRegisterInfo();
8685 return std::make_pair(TRI->getMatchingSuperReg(R.first,
8686 PPC::sub_32, &PPC::G8RCRegClass),
8687 &PPC::G8RCRegClass);
8694 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
8695 /// vector. If it is invalid, don't add anything to Ops.
8696 void PPCTargetLowering::LowerAsmOperandForConstraint(SDValue Op,
8697 std::string &Constraint,
8698 std::vector<SDValue>&Ops,
8699 SelectionDAG &DAG) const {
8702 // Only support length 1 constraints.
8703 if (Constraint.length() > 1) return;
8705 char Letter = Constraint[0];
8716 ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op);
8717 if (!CST) return; // Must be an immediate to match.
8718 unsigned Value = CST->getZExtValue();
8720 default: llvm_unreachable("Unknown constraint letter!");
8721 case 'I': // "I" is a signed 16-bit constant.
8722 if ((short)Value == (int)Value)
8723 Result = DAG.getTargetConstant(Value, Op.getValueType());
8725 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
8726 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
8727 if ((short)Value == 0)
8728 Result = DAG.getTargetConstant(Value, Op.getValueType());
8730 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
8731 if ((Value >> 16) == 0)
8732 Result = DAG.getTargetConstant(Value, Op.getValueType());
8734 case 'M': // "M" is a constant that is greater than 31.
8736 Result = DAG.getTargetConstant(Value, Op.getValueType());
8738 case 'N': // "N" is a positive constant that is an exact power of two.
8739 if ((int)Value > 0 && isPowerOf2_32(Value))
8740 Result = DAG.getTargetConstant(Value, Op.getValueType());
8742 case 'O': // "O" is the constant zero.
8744 Result = DAG.getTargetConstant(Value, Op.getValueType());
8746 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
8747 if ((short)-Value == (int)-Value)
8748 Result = DAG.getTargetConstant(Value, Op.getValueType());
8755 if (Result.getNode()) {
8756 Ops.push_back(Result);
8760 // Handle standard constraint letters.
8761 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
8764 // isLegalAddressingMode - Return true if the addressing mode represented
8765 // by AM is legal for this target, for a load/store of the specified type.
8766 bool PPCTargetLowering::isLegalAddressingMode(const AddrMode &AM,
8768 // FIXME: PPC does not allow r+i addressing modes for vectors!
8770 // PPC allows a sign-extended 16-bit immediate field.
8771 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
8774 // No global is ever allowed as a base.
8778 // PPC only support r+r,
8780 case 0: // "r+i" or just "i", depending on HasBaseReg.
8783 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
8785 // Otherwise we have r+r or r+i.
8788 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
8790 // Allow 2*r as r+r.
8793 // No other scales are supported.
8800 SDValue PPCTargetLowering::LowerRETURNADDR(SDValue Op,
8801 SelectionDAG &DAG) const {
8802 MachineFunction &MF = DAG.getMachineFunction();
8803 MachineFrameInfo *MFI = MF.getFrameInfo();
8804 MFI->setReturnAddressIsTaken(true);
8806 if (verifyReturnAddressArgumentIsConstant(Op, DAG))
8810 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8812 // Make sure the function does not optimize away the store of the RA to
8814 PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
8815 FuncInfo->setLRStoreRequired();
8816 bool isPPC64 = Subtarget.isPPC64();
8817 bool isDarwinABI = Subtarget.isDarwinABI();
8820 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG);
8823 DAG.getConstant(PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI),
8824 isPPC64? MVT::i64 : MVT::i32);
8825 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8826 DAG.getNode(ISD::ADD, dl, getPointerTy(),
8828 MachinePointerInfo(), false, false, false, 0);
8831 // Just load the return address off the stack.
8832 SDValue RetAddrFI = getReturnAddrFrameIndex(DAG);
8833 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(),
8834 RetAddrFI, MachinePointerInfo(), false, false, false, 0);
8837 SDValue PPCTargetLowering::LowerFRAMEADDR(SDValue Op,
8838 SelectionDAG &DAG) const {
8840 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
8842 EVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
8843 bool isPPC64 = PtrVT == MVT::i64;
8845 MachineFunction &MF = DAG.getMachineFunction();
8846 MachineFrameInfo *MFI = MF.getFrameInfo();
8847 MFI->setFrameAddressIsTaken(true);
8849 // Naked functions never have a frame pointer, and so we use r1. For all
8850 // other functions, this decision must be delayed until during PEI.
8852 if (MF.getFunction()->getAttributes().hasAttribute(
8853 AttributeSet::FunctionIndex, Attribute::Naked))
8854 FrameReg = isPPC64 ? PPC::X1 : PPC::R1;
8856 FrameReg = isPPC64 ? PPC::FP8 : PPC::FP;
8858 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg,
8861 FrameAddr = DAG.getLoad(Op.getValueType(), dl, DAG.getEntryNode(),
8862 FrameAddr, MachinePointerInfo(), false, false,
8867 // FIXME? Maybe this could be a TableGen attribute on some registers and
8868 // this table could be generated automatically from RegInfo.
8869 unsigned PPCTargetLowering::getRegisterByName(const char* RegName,
8871 bool isPPC64 = Subtarget.isPPC64();
8872 bool isDarwinABI = Subtarget.isDarwinABI();
8874 if ((isPPC64 && VT != MVT::i64 && VT != MVT::i32) ||
8875 (!isPPC64 && VT != MVT::i32))
8876 report_fatal_error("Invalid register global variable type");
8878 bool is64Bit = isPPC64 && VT == MVT::i64;
8879 unsigned Reg = StringSwitch<unsigned>(RegName)
8880 .Case("r1", is64Bit ? PPC::X1 : PPC::R1)
8881 .Case("r2", isDarwinABI ? 0 : (is64Bit ? PPC::X2 : PPC::R2))
8882 .Case("r13", (!isPPC64 && isDarwinABI) ? 0 :
8883 (is64Bit ? PPC::X13 : PPC::R13))
8888 report_fatal_error("Invalid register name global variable");
8892 PPCTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
8893 // The PowerPC target isn't yet aware of offsets.
8897 /// getOptimalMemOpType - Returns the target specific optimal type for load
8898 /// and store operations as a result of memset, memcpy, and memmove
8899 /// lowering. If DstAlign is zero that means it's safe to destination
8900 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
8901 /// means there isn't a need to check it against alignment requirement,
8902 /// probably because the source does not need to be loaded. If 'IsMemset' is
8903 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
8904 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
8905 /// source is constant so it does not need to be loaded.
8906 /// It returns EVT::Other if the type should be determined using generic
8907 /// target-independent logic.
8908 EVT PPCTargetLowering::getOptimalMemOpType(uint64_t Size,
8909 unsigned DstAlign, unsigned SrcAlign,
8910 bool IsMemset, bool ZeroMemset,
8912 MachineFunction &MF) const {
8913 if (Subtarget.isPPC64()) {
8920 /// \brief Returns true if it is beneficial to convert a load of a constant
8921 /// to just the constant itself.
8922 bool PPCTargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
8924 assert(Ty->isIntegerTy());
8926 unsigned BitSize = Ty->getPrimitiveSizeInBits();
8927 if (BitSize == 0 || BitSize > 64)
8932 bool PPCTargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
8933 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
8935 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits();
8936 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits();
8937 return NumBits1 == 64 && NumBits2 == 32;
8940 bool PPCTargetLowering::isTruncateFree(EVT VT1, EVT VT2) const {
8941 if (!VT1.isInteger() || !VT2.isInteger())
8943 unsigned NumBits1 = VT1.getSizeInBits();
8944 unsigned NumBits2 = VT2.getSizeInBits();
8945 return NumBits1 == 64 && NumBits2 == 32;
8948 bool PPCTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
8949 return isInt<16>(Imm) || isUInt<16>(Imm);
8952 bool PPCTargetLowering::isLegalAddImmediate(int64_t Imm) const {
8953 return isInt<16>(Imm) || isUInt<16>(Imm);
8956 bool PPCTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
8959 if (DisablePPCUnaligned)
8962 // PowerPC supports unaligned memory access for simple non-vector types.
8963 // Although accessing unaligned addresses is not as efficient as accessing
8964 // aligned addresses, it is generally more efficient than manual expansion,
8965 // and generally only traps for software emulation when crossing page
8971 if (VT.getSimpleVT().isVector()) {
8972 if (Subtarget.hasVSX()) {
8973 if (VT != MVT::v2f64 && VT != MVT::v2i64)
8980 if (VT == MVT::ppcf128)
8989 bool PPCTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
8990 VT = VT.getScalarType();
8995 switch (VT.getSimpleVT().SimpleTy) {
9007 PPCTargetLowering::shouldExpandBuildVectorWithShuffles(
9008 EVT VT , unsigned DefinedValues) const {
9009 if (VT == MVT::v2i64)
9012 return TargetLowering::shouldExpandBuildVectorWithShuffles(VT, DefinedValues);
9015 Sched::Preference PPCTargetLowering::getSchedulingPreference(SDNode *N) const {
9016 if (DisableILPPref || Subtarget.enableMachineScheduler())
9017 return TargetLowering::getSchedulingPreference(N);
9022 // Create a fast isel object.
9024 PPCTargetLowering::createFastISel(FunctionLoweringInfo &FuncInfo,
9025 const TargetLibraryInfo *LibInfo) const {
9026 return PPC::createFastISel(FuncInfo, LibInfo);