1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
74 /// The following two target-specific nodes are used for calls through
75 /// function pointers in the 64-bit SVR4 ABI.
77 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
78 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
79 /// compute an allocation on the stack.
82 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
83 /// at function entry, used for PIC code.
86 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
87 /// shift amounts. These nodes are generated by the multi-precision shift
91 /// The combination of sra[wd]i and addze used to implemented signed
92 /// integer division by a power of 2. The first operand is the dividend,
93 /// and the second is the constant shift amount (representing the
97 /// CALL - A direct function call.
98 /// CALL_NOP is a call with the special NOP which follows 64-bit
102 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
103 /// MTCTR instruction.
106 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
107 /// BCTRL instruction.
110 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
111 /// instruction and the TOC reload required on SVR4 PPC64.
114 /// Return with a flag operand, matched by 'blr'
117 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
118 /// This copies the bits corresponding to the specified CRREG into the
119 /// resultant GPR. Bits corresponding to other CR regs are undefined.
122 // FIXME: Remove these once the ANDI glue bug is fixed:
123 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
124 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
125 /// implement truncation of i32 or i64 to i1.
126 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
128 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
129 // target (returns (Lo, Hi)). It takes a chain operand.
132 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
135 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
138 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
139 /// instructions. For lack of better number, we use the opcode number
140 /// encoding for the OPC field to identify the compare. For example, 838
144 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
145 /// altivec VCMP*o instructions. For lack of better number, we use the
146 /// opcode number encoding for the OPC field to identify the compare. For
147 /// example, 838 is VCMPGTSH.
150 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
151 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
152 /// condition register to branch on, OPC is the branch opcode to use (e.g.
153 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
154 /// an optional input flag argument.
157 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
161 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
162 /// towards zero. Used only as part of the long double-to-int
163 /// conversion sequence.
166 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
169 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
170 /// reserve indexed. This is used to implement atomic operations.
173 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
174 /// indexed. This is used to implement atomic operations.
177 /// TC_RETURN - A tail call return.
179 /// operand #1 callee (register or absolute)
180 /// operand #2 stack adjustment
181 /// operand #3 optional in flag
184 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
188 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
192 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
193 /// local dynamic TLS on PPC32.
196 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
197 /// TLS model, produces an ADDIS8 instruction that adds the GOT
198 /// base to sym\@got\@tprel\@ha.
201 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
202 /// TLS model, produces a LD instruction with base register G8RReg
203 /// and offset sym\@got\@tprel\@l. This completes the addition that
204 /// finds the offset of "sym" relative to the thread pointer.
207 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
208 /// model, produces an ADD instruction that adds the contents of
209 /// G8RReg to the thread pointer. Symbol contains a relocation
210 /// sym\@tls which is to be replaced by the thread pointer and
211 /// identifies to the linker that the instruction is part of a
215 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
216 /// model, produces an ADDIS8 instruction that adds the GOT base
217 /// register to sym\@got\@tlsgd\@ha.
220 /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
221 /// model, produces an ADDI8 instruction that adds G8RReg to
222 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
223 /// ADDIS_TLSGD_L_ADDR until after register assignment.
226 /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
227 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
228 /// ADDIS_TLSGD_L_ADDR until after register assignment.
231 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
232 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
233 /// register assignment.
236 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
237 /// model, produces an ADDIS8 instruction that adds the GOT base
238 /// register to sym\@got\@tlsld\@ha.
241 /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
242 /// model, produces an ADDI8 instruction that adds G8RReg to
243 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
244 /// ADDIS_TLSLD_L_ADDR until after register assignment.
247 /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
248 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
249 /// ADDIS_TLSLD_L_ADDR until after register assignment.
252 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
253 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
254 /// following register assignment.
257 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
258 /// model, produces an ADDIS8 instruction that adds X3 to
262 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
263 /// model, produces an ADDI8 instruction that adds G8RReg to
264 /// sym\@got\@dtprel\@l.
267 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
268 /// during instruction selection to optimize a BUILD_VECTOR into
269 /// operations on splats. This is necessary to avoid losing these
270 /// optimizations due to constant folding.
273 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
274 /// operand identifies the operating system entry point.
277 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
278 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
279 /// or stxvd2x instruction. The chain is necessary because the
280 /// sequence replaces a load and needs to provide the same number
284 /// QVFPERM = This corresponds to the QPX qvfperm instruction.
287 /// QVGPCI = This corresponds to the QPX qvgpci instruction.
290 /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
293 /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
296 /// QBFLT = Access the underlying QPX floating-point boolean
300 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
301 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
302 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
304 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
306 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
307 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
308 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
312 /// STFIWX - The STFIWX instruction. The first operand is an input token
313 /// chain, then an f64 value to store, then an address to store it to.
316 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
317 /// load which sign-extends from a 32-bit integer value into the
318 /// destination 64-bit register.
321 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
322 /// load which zero-extends from a 32-bit integer value into the
323 /// destination 64-bit register.
326 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
327 /// Maps directly to an lxvd2x instruction that will be followed by
331 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
332 /// Maps directly to an stxvd2x instruction that will be preceded by
336 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
337 /// The 4xf32 load used for v4i1 constants.
340 /// GPRC = TOC_ENTRY GA, TOC
341 /// Loads the entry for GA from the TOC, where the TOC base is given by
342 /// the last operand.
347 /// Define some predicates that are used for node matching.
349 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
350 /// VPKUHUM instruction.
351 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
354 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
355 /// VPKUWUM instruction.
356 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
359 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
360 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
361 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
362 unsigned ShuffleKind, SelectionDAG &DAG);
364 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
365 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
366 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
367 unsigned ShuffleKind, SelectionDAG &DAG);
369 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
370 /// shift amount, otherwise return -1.
371 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
374 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
375 /// specifies a splat of a single element that is suitable for input to
376 /// VSPLTB/VSPLTH/VSPLTW.
377 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
379 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
381 bool isAllNegativeZeroVector(SDNode *N);
383 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
384 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
385 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
387 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
388 /// formed by using a vspltis[bhw] instruction of the specified element
389 /// size, return the constant being splatted. The ByteSize field indicates
390 /// the number of bytes of each element [124] -> [bhw].
391 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
393 /// If this is a qvaligni shuffle mask, return the shift
394 /// amount, otherwise return -1.
395 int isQVALIGNIShuffleMask(SDNode *N);
398 class PPCTargetLowering : public TargetLowering {
399 const PPCSubtarget &Subtarget;
402 explicit PPCTargetLowering(const PPCTargetMachine &TM,
403 const PPCSubtarget &STI);
405 /// getTargetNodeName() - This method returns the name of a target specific
407 const char *getTargetNodeName(unsigned Opcode) const override;
409 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
411 bool isCheapToSpeculateCttz() const override {
415 bool isCheapToSpeculateCtlz() const override {
419 /// getSetCCResultType - Return the ISD::SETCC ValueType
420 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
422 /// Return true if target always beneficiates from combining into FMA for a
423 /// given value type. This must typically return false on targets where FMA
424 /// takes more cycles to execute than FADD.
425 bool enableAggressiveFMAFusion(EVT VT) const override;
427 /// getPreIndexedAddressParts - returns true by value, base pointer and
428 /// offset pointer and addressing mode by reference if the node's address
429 /// can be legally represented as pre-indexed load / store address.
430 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
432 ISD::MemIndexedMode &AM,
433 SelectionDAG &DAG) const override;
435 /// SelectAddressRegReg - Given the specified addressed, check to see if it
436 /// can be represented as an indexed [r+r] operation. Returns false if it
437 /// can be more efficiently represented with [r+imm].
438 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
439 SelectionDAG &DAG) const;
441 /// SelectAddressRegImm - Returns true if the address N can be represented
442 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
443 /// is not better represented as reg+reg. If Aligned is true, only accept
444 /// displacements suitable for STD and friends, i.e. multiples of 4.
445 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
446 SelectionDAG &DAG, bool Aligned) const;
448 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
449 /// represented as an indexed [r+r] operation.
450 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
451 SelectionDAG &DAG) const;
453 Sched::Preference getSchedulingPreference(SDNode *N) const override;
455 /// LowerOperation - Provide custom lowering hooks for some operations.
457 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
459 /// ReplaceNodeResults - Replace the results of node with an illegal result
460 /// type with new values built out of custom code.
462 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
463 SelectionDAG &DAG) const override;
465 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
466 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
468 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
470 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
471 std::vector<SDNode *> *Created) const override;
473 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
475 void computeKnownBitsForTargetNode(const SDValue Op,
478 const SelectionDAG &DAG,
479 unsigned Depth = 0) const override;
481 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
483 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
484 bool IsStore, bool IsLoad) const override;
485 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
486 bool IsStore, bool IsLoad) const override;
489 EmitInstrWithCustomInserter(MachineInstr *MI,
490 MachineBasicBlock *MBB) const override;
491 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
492 MachineBasicBlock *MBB, bool is64Bit,
493 unsigned BinOpcode) const;
494 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
495 MachineBasicBlock *MBB,
496 bool is8bit, unsigned Opcode) const;
498 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
499 MachineBasicBlock *MBB) const;
501 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
502 MachineBasicBlock *MBB) const;
505 getConstraintType(const std::string &Constraint) const override;
507 /// Examine constraint string and operand type and determine a weight value.
508 /// The operand object must already have been set up with the operand type.
509 ConstraintWeight getSingleConstraintMatchWeight(
510 AsmOperandInfo &info, const char *constraint) const override;
512 std::pair<unsigned, const TargetRegisterClass *>
513 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
514 const std::string &Constraint,
515 MVT VT) const override;
517 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
518 /// function arguments in the caller parameter area. This is the actual
519 /// alignment, not its logarithm.
520 unsigned getByValTypeAlignment(Type *Ty) const override;
522 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
523 /// vector. If it is invalid, don't add anything to Ops.
524 void LowerAsmOperandForConstraint(SDValue Op,
525 std::string &Constraint,
526 std::vector<SDValue> &Ops,
527 SelectionDAG &DAG) const override;
529 /// isLegalAddressingMode - Return true if the addressing mode represented
530 /// by AM is legal for this target, for a load/store of the specified type.
531 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
533 /// isLegalICmpImmediate - Return true if the specified immediate is legal
534 /// icmp immediate, that is the target has icmp instructions which can
535 /// compare a register against the immediate without having to materialize
536 /// the immediate into a register.
537 bool isLegalICmpImmediate(int64_t Imm) const override;
539 /// isLegalAddImmediate - Return true if the specified immediate is legal
540 /// add immediate, that is the target has add instructions which can
541 /// add a register and the immediate without having to materialize
542 /// the immediate into a register.
543 bool isLegalAddImmediate(int64_t Imm) const override;
545 /// isTruncateFree - Return true if it's free to truncate a value of
546 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
547 /// register X1 to i32 by referencing its sub-register R1.
548 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
549 bool isTruncateFree(EVT VT1, EVT VT2) const override;
551 bool isZExtFree(SDValue Val, EVT VT2) const override;
553 bool isFPExtFree(EVT VT) const override;
555 /// \brief Returns true if it is beneficial to convert a load of a constant
556 /// to just the constant itself.
557 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
558 Type *Ty) const override;
560 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
562 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
564 unsigned Intrinsic) const override;
566 /// getOptimalMemOpType - Returns the target specific optimal type for load
567 /// and store operations as a result of memset, memcpy, and memmove
568 /// lowering. If DstAlign is zero that means it's safe to destination
569 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
570 /// means there isn't a need to check it against alignment requirement,
571 /// probably because the source does not need to be loaded. If 'IsMemset' is
572 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
573 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
574 /// source is constant so it does not need to be loaded.
575 /// It returns EVT::Other if the type should be determined using generic
576 /// target-independent logic.
578 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
579 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
580 MachineFunction &MF) const override;
582 /// Is unaligned memory access allowed for the given type, and is it fast
583 /// relative to software emulation.
584 bool allowsMisalignedMemoryAccesses(EVT VT,
587 bool *Fast = nullptr) const override;
589 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
590 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
591 /// expanded to FMAs when this method returns true, otherwise fmuladd is
592 /// expanded to fmul + fadd.
593 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
595 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
597 // Should we expand the build vector with shuffles?
599 shouldExpandBuildVectorWithShuffles(EVT VT,
600 unsigned DefinedValues) const override;
602 /// createFastISel - This method returns a target-specific FastISel object,
603 /// or null if the target does not support "fast" instruction selection.
604 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
605 const TargetLibraryInfo *LibInfo) const override;
607 /// \brief Returns true if an argument of type Ty needs to be passed in a
608 /// contiguous block of registers in calling convention CallConv.
609 bool functionArgumentNeedsConsecutiveRegisters(
610 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
611 // We support any array type as "consecutive" block in the parameter
612 // save area. The element type defines the alignment requirement and
613 // whether the argument should go in GPRs, FPRs, or VRs if available.
615 // Note that clang uses this capability both to implement the ELFv2
616 // homogeneous float/vector aggregate ABI, and to avoid having to use
617 // "byval" when passing aggregates that might fully fit in registers.
618 return Ty->isArrayTy();
623 struct ReuseLoadInfo {
627 MachinePointerInfo MPI;
631 const MDNode *Ranges;
633 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {}
636 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
638 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
639 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
640 SelectionDAG &DAG) const;
642 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
643 SelectionDAG &DAG, SDLoc dl) const;
645 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
646 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
649 IsEligibleForTailCallOptimization(SDValue Callee,
650 CallingConv::ID CalleeCC,
652 const SmallVectorImpl<ISD::InputArg> &Ins,
653 SelectionDAG& DAG) const;
655 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
663 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
664 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
665 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
666 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
667 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
668 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
669 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
670 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
671 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
672 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
673 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
674 const PPCSubtarget &Subtarget) const;
675 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
676 const PPCSubtarget &Subtarget) const;
677 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
678 const PPCSubtarget &Subtarget) const;
679 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
680 const PPCSubtarget &Subtarget) const;
681 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
682 const PPCSubtarget &Subtarget) const;
683 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
684 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
685 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
686 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
687 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
688 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
689 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
690 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
691 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
692 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
693 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
694 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
695 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
696 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
697 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
698 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
699 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
701 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
702 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
704 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
705 CallingConv::ID CallConv, bool isVarArg,
706 const SmallVectorImpl<ISD::InputArg> &Ins,
707 SDLoc dl, SelectionDAG &DAG,
708 SmallVectorImpl<SDValue> &InVals) const;
709 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
710 bool isVarArg, bool IsPatchPoint,
712 SmallVector<std::pair<unsigned, SDValue>, 8>
714 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
716 int SPDiff, unsigned NumBytes,
717 const SmallVectorImpl<ISD::InputArg> &Ins,
718 SmallVectorImpl<SDValue> &InVals,
719 ImmutableCallSite *CS) const;
722 LowerFormalArguments(SDValue Chain,
723 CallingConv::ID CallConv, bool isVarArg,
724 const SmallVectorImpl<ISD::InputArg> &Ins,
725 SDLoc dl, SelectionDAG &DAG,
726 SmallVectorImpl<SDValue> &InVals) const override;
729 LowerCall(TargetLowering::CallLoweringInfo &CLI,
730 SmallVectorImpl<SDValue> &InVals) const override;
733 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
735 const SmallVectorImpl<ISD::OutputArg> &Outs,
736 LLVMContext &Context) const override;
739 LowerReturn(SDValue Chain,
740 CallingConv::ID CallConv, bool isVarArg,
741 const SmallVectorImpl<ISD::OutputArg> &Outs,
742 const SmallVectorImpl<SDValue> &OutVals,
743 SDLoc dl, SelectionDAG &DAG) const override;
746 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
747 SDValue ArgVal, SDLoc dl) const;
750 LowerFormalArguments_Darwin(SDValue Chain,
751 CallingConv::ID CallConv, bool isVarArg,
752 const SmallVectorImpl<ISD::InputArg> &Ins,
753 SDLoc dl, SelectionDAG &DAG,
754 SmallVectorImpl<SDValue> &InVals) const;
756 LowerFormalArguments_64SVR4(SDValue Chain,
757 CallingConv::ID CallConv, bool isVarArg,
758 const SmallVectorImpl<ISD::InputArg> &Ins,
759 SDLoc dl, SelectionDAG &DAG,
760 SmallVectorImpl<SDValue> &InVals) const;
762 LowerFormalArguments_32SVR4(SDValue Chain,
763 CallingConv::ID CallConv, bool isVarArg,
764 const SmallVectorImpl<ISD::InputArg> &Ins,
765 SDLoc dl, SelectionDAG &DAG,
766 SmallVectorImpl<SDValue> &InVals) const;
769 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
770 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
771 SelectionDAG &DAG, SDLoc dl) const;
774 LowerCall_Darwin(SDValue Chain, SDValue Callee,
775 CallingConv::ID CallConv,
776 bool isVarArg, bool isTailCall, bool IsPatchPoint,
777 const SmallVectorImpl<ISD::OutputArg> &Outs,
778 const SmallVectorImpl<SDValue> &OutVals,
779 const SmallVectorImpl<ISD::InputArg> &Ins,
780 SDLoc dl, SelectionDAG &DAG,
781 SmallVectorImpl<SDValue> &InVals,
782 ImmutableCallSite *CS) const;
784 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
785 CallingConv::ID CallConv,
786 bool isVarArg, bool isTailCall, bool IsPatchPoint,
787 const SmallVectorImpl<ISD::OutputArg> &Outs,
788 const SmallVectorImpl<SDValue> &OutVals,
789 const SmallVectorImpl<ISD::InputArg> &Ins,
790 SDLoc dl, SelectionDAG &DAG,
791 SmallVectorImpl<SDValue> &InVals,
792 ImmutableCallSite *CS) const;
794 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
795 bool isVarArg, bool isTailCall, bool IsPatchPoint,
796 const SmallVectorImpl<ISD::OutputArg> &Outs,
797 const SmallVectorImpl<SDValue> &OutVals,
798 const SmallVectorImpl<ISD::InputArg> &Ins,
799 SDLoc dl, SelectionDAG &DAG,
800 SmallVectorImpl<SDValue> &InVals,
801 ImmutableCallSite *CS) const;
803 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
804 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
806 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
807 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
808 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
810 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
811 unsigned &RefinementSteps,
812 bool &UseOneConstNR) const override;
813 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
814 unsigned &RefinementSteps) const override;
815 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
817 CCAssignFn *useFastISelCCs(unsigned Flag) const;
821 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
822 const TargetLibraryInfo *LibInfo);
825 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
826 CCValAssign::LocInfo &LocInfo,
827 ISD::ArgFlagsTy &ArgFlags,
830 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
832 CCValAssign::LocInfo &LocInfo,
833 ISD::ArgFlagsTy &ArgFlags,
836 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
838 CCValAssign::LocInfo &LocInfo,
839 ISD::ArgFlagsTy &ArgFlags,
843 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H