1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
25 // Start the numbering where the builting ops and target ops leave off.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
28 /// FSEL - Traditional three-operand fsel node.
32 /// FCFID - The FCFID instruction, taking an f64 operand and producing
33 /// and f64 value containing the FP representation of the integer that
34 /// was temporarily in the f64 operand.
37 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
38 /// operand, producing an f64 value containing the integer representation
42 /// STFIWX - The STFIWX instruction. The first operand is an input token
43 /// chain, then an f64 value to store, then an address to store it to,
44 /// then a SRCVALUE for the address.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
62 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
63 /// at function entry, used for PIC code.
66 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
67 /// shift amounts. These nodes are generated by the multi-precision shift
71 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
75 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
78 /// CALL - A direct function call.
81 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
82 /// MTCTR instruction.
85 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
86 /// BCTRL instruction.
89 /// Return with a flag operand, matched by 'blr'
92 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
93 /// This copies the bits corresponding to the specified CRREG into the
94 /// resultant GPR. Bits corresponding to other CR regs are undefined.
97 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
98 /// instructions. For lack of better number, we use the opcode number
99 /// encoding for the OPC field to identify the compare. For example, 838
103 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
104 /// altivec VCMP*o instructions. For lack of better number, we use the
105 /// opcode number encoding for the OPC field to identify the compare. For
106 /// example, 838 is VCMPGTSH.
109 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
110 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
111 /// condition register to branch on, OPC is the branch opcode to use (e.g.
112 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
113 /// an optional input flag argument.
116 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a
117 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
118 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
122 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a
123 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
124 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
130 /// Define some predicates that are used for node matching.
132 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
133 /// VPKUHUM instruction.
134 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary);
136 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
137 /// VPKUWUM instruction.
138 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary);
140 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
141 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
142 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
144 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
145 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
146 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
148 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
149 /// amount, otherwise return -1.
150 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
152 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
153 /// specifies a splat of a single element that is suitable for input to
154 /// VSPLTB/VSPLTH/VSPLTW.
155 bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
157 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
158 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
159 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
161 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
162 /// formed by using a vspltis[bhw] instruction of the specified element
163 /// size, return the constant being splatted. The ByteSize field indicates
164 /// the number of bytes of each element [124] -> [bhw].
165 SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
168 class PPCTargetLowering : public TargetLowering {
169 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
170 int ReturnAddrIndex; // FrameIndex for return slot.
172 PPCTargetLowering(TargetMachine &TM);
174 /// getTargetNodeName() - This method returns the name of a target specific
176 virtual const char *getTargetNodeName(unsigned Opcode) const;
178 /// LowerOperation - Provide custom lowering hooks for some operations.
180 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
182 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
184 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
188 unsigned Depth = 0) const;
190 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
191 MachineBasicBlock *MBB);
193 ConstraintType getConstraintType(char ConstraintLetter) const;
194 std::vector<unsigned>
195 getRegClassForInlineAsmConstraint(const std::string &Constraint,
196 MVT::ValueType VT) const;
197 SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
200 /// isLegalAddressImmediate - Return true if the integer value can be used
201 /// as the offset of the target addressing mode.
202 virtual bool isLegalAddressImmediate(int64_t V) const;
203 virtual bool isLegalAddressImmediate(llvm::GlobalValue*) const;
207 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H