1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/CodeGen/CallingConvLower.h"
24 #include "llvm/Target/TargetLowering.h"
29 // Start the numbering where the builtin ops and target ops leave off.
30 FIRST_NUMBER = ISD::BUILTIN_OP_END,
32 /// FSEL - Traditional three-operand fsel node.
36 /// FCFID - The FCFID instruction, taking an f64 operand and producing
37 /// and f64 value containing the FP representation of the integer that
38 /// was temporarily in the f64 operand.
41 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
42 /// unsigned integers and single-precision outputs.
43 FCFIDU, FCFIDS, FCFIDUS,
45 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
46 /// operand, producing an f64 value containing the integer representation
50 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
51 /// unsigned integers.
54 /// Reciprocal estimate instructions (unary FP ops).
57 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
58 // three v4f32 operands and producing a v4f32 result.
61 /// VPERM - The PPC VPERM Instruction.
65 /// Hi/Lo - These represent the high and low 16-bit parts of a global
66 /// address respectively. These nodes have two operands, the first of
67 /// which must be a TargetGlobalAddress, and the second of which must be a
68 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
69 /// though these are usually folded into other nodes.
74 /// The following three target-specific nodes are used for calls through
75 /// function pointers in the 64-bit SVR4 ABI.
77 /// Restore the TOC from the TOC save area of the current stack frame.
78 /// This is basically a hard coded load instruction which additionally
79 /// takes/produces a flag.
82 /// Like a regular LOAD but additionally taking/producing a flag.
85 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
86 /// a hard coded load instruction.
89 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
90 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
91 /// compute an allocation on the stack.
94 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
95 /// at function entry, used for PIC code.
98 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
99 /// shift amounts. These nodes are generated by the multi-precision shift
103 /// CALL - A direct function call.
104 /// CALL_NOP is a call with the special NOP which follows 64-bit
108 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
109 /// MTCTR instruction.
112 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
113 /// BCTRL instruction.
116 /// Return with a flag operand, matched by 'blr'
119 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
120 /// instructions. This copies the bits corresponding to the specified
121 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
125 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
128 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
131 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
132 /// instructions. For lack of better number, we use the opcode number
133 /// encoding for the OPC field to identify the compare. For example, 838
137 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
138 /// altivec VCMP*o instructions. For lack of better number, we use the
139 /// opcode number encoding for the OPC field to identify the compare. For
140 /// example, 838 is VCMPGTSH.
143 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
144 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
145 /// condition register to branch on, OPC is the branch opcode to use (e.g.
146 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
147 /// an optional input flag argument.
150 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
154 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
155 /// towards zero. Used only as part of the long double-to-int
156 /// conversion sequence.
159 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
162 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
163 /// reserve indexed. This is used to implement atomic operations.
166 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
167 /// indexed. This is used to implement atomic operations.
170 /// TC_RETURN - A tail call return.
172 /// operand #1 callee (register or absolute)
173 /// operand #2 stack adjustment
174 /// operand #3 optional in flag
177 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
181 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
182 /// TLS model, produces an ADDIS8 instruction that adds the GOT
183 /// base to sym\@got\@tprel\@ha.
186 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
187 /// TLS model, produces a LD instruction with base register G8RReg
188 /// and offset sym\@got\@tprel\@l. This completes the addition that
189 /// finds the offset of "sym" relative to the thread pointer.
192 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
193 /// model, produces an ADD instruction that adds the contents of
194 /// G8RReg to the thread pointer. Symbol contains a relocation
195 /// sym\@tls which is to be replaced by the thread pointer and
196 /// identifies to the linker that the instruction is part of a
200 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
201 /// model, produces an ADDIS8 instruction that adds the GOT base
202 /// register to sym\@got\@tlsgd\@ha.
205 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
206 /// model, produces an ADDI8 instruction that adds G8RReg to
207 /// sym\@got\@tlsgd\@l.
210 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
211 /// model, produces a call to __tls_get_addr(sym\@tlsgd).
214 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
215 /// model, produces an ADDIS8 instruction that adds the GOT base
216 /// register to sym\@got\@tlsld\@ha.
219 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
220 /// model, produces an ADDI8 instruction that adds G8RReg to
221 /// sym\@got\@tlsld\@l.
224 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
225 /// model, produces a call to __tls_get_addr(sym\@tlsld).
228 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
229 /// local-dynamic TLS model, produces an ADDIS8 instruction
230 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
231 /// to tie this in place following a copy to %X3 from the result
232 /// of a GET_TLSLD_ADDR.
235 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
236 /// model, produces an ADDI8 instruction that adds G8RReg to
237 /// sym\@got\@dtprel\@l.
240 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
241 /// during instruction selection to optimize a BUILD_VECTOR into
242 /// operations on splats. This is necessary to avoid losing these
243 /// optimizations due to constant folding.
246 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
247 /// operand identifies the operating system entry point.
250 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
251 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
252 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
254 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
256 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
257 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
258 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
262 /// STFIWX - The STFIWX instruction. The first operand is an input token
263 /// chain, then an f64 value to store, then an address to store it to.
266 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
267 /// load which sign-extends from a 32-bit integer value into the
268 /// destination 64-bit register.
271 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
272 /// load which zero-extends from a 32-bit integer value into the
273 /// destination 64-bit register.
276 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
277 /// produces an ADDIS8 instruction that adds the TOC base register to
281 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
282 /// produces a LD instruction with base register G8RReg and offset
283 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
286 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
287 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
288 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
293 /// Define some predicates that are used for node matching.
295 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
296 /// VPKUHUM instruction.
297 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
299 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
300 /// VPKUWUM instruction.
301 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
303 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
304 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
305 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
308 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
309 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
310 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
313 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
314 /// amount, otherwise return -1.
315 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
317 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
318 /// specifies a splat of a single element that is suitable for input to
319 /// VSPLTB/VSPLTH/VSPLTW.
320 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
322 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
324 bool isAllNegativeZeroVector(SDNode *N);
326 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
327 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
328 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
330 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
331 /// formed by using a vspltis[bhw] instruction of the specified element
332 /// size, return the constant being splatted. The ByteSize field indicates
333 /// the number of bytes of each element [124] -> [bhw].
334 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
337 class PPCTargetLowering : public TargetLowering {
338 const PPCSubtarget &PPCSubTarget;
341 explicit PPCTargetLowering(PPCTargetMachine &TM);
343 /// getTargetNodeName() - This method returns the name of a target specific
345 virtual const char *getTargetNodeName(unsigned Opcode) const;
347 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
349 /// getSetCCResultType - Return the ISD::SETCC ValueType
350 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
352 /// getPreIndexedAddressParts - returns true by value, base pointer and
353 /// offset pointer and addressing mode by reference if the node's address
354 /// can be legally represented as pre-indexed load / store address.
355 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
357 ISD::MemIndexedMode &AM,
358 SelectionDAG &DAG) const;
360 /// SelectAddressRegReg - Given the specified addressed, check to see if it
361 /// can be represented as an indexed [r+r] operation. Returns false if it
362 /// can be more efficiently represented with [r+imm].
363 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
364 SelectionDAG &DAG) const;
366 /// SelectAddressRegImm - Returns true if the address N can be represented
367 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
368 /// is not better represented as reg+reg. If Aligned is true, only accept
369 /// displacements suitable for STD and friends, i.e. multiples of 4.
370 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
371 SelectionDAG &DAG, bool Aligned) const;
373 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
374 /// represented as an indexed [r+r] operation.
375 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
376 SelectionDAG &DAG) const;
378 Sched::Preference getSchedulingPreference(SDNode *N) const;
380 /// LowerOperation - Provide custom lowering hooks for some operations.
382 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
384 /// ReplaceNodeResults - Replace the results of node with an illegal result
385 /// type with new values built out of custom code.
387 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
388 SelectionDAG &DAG) const;
390 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
392 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
395 const SelectionDAG &DAG,
396 unsigned Depth = 0) const;
398 virtual MachineBasicBlock *
399 EmitInstrWithCustomInserter(MachineInstr *MI,
400 MachineBasicBlock *MBB) const;
401 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
402 MachineBasicBlock *MBB, bool is64Bit,
403 unsigned BinOpcode) const;
404 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
405 MachineBasicBlock *MBB,
406 bool is8bit, unsigned Opcode) const;
408 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
409 MachineBasicBlock *MBB) const;
411 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
412 MachineBasicBlock *MBB) const;
414 ConstraintType getConstraintType(const std::string &Constraint) const;
416 /// Examine constraint string and operand type and determine a weight value.
417 /// The operand object must already have been set up with the operand type.
418 ConstraintWeight getSingleConstraintMatchWeight(
419 AsmOperandInfo &info, const char *constraint) const;
421 std::pair<unsigned, const TargetRegisterClass*>
422 getRegForInlineAsmConstraint(const std::string &Constraint,
425 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
426 /// function arguments in the caller parameter area. This is the actual
427 /// alignment, not its logarithm.
428 unsigned getByValTypeAlignment(Type *Ty) const;
430 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
431 /// vector. If it is invalid, don't add anything to Ops.
432 virtual void LowerAsmOperandForConstraint(SDValue Op,
433 std::string &Constraint,
434 std::vector<SDValue> &Ops,
435 SelectionDAG &DAG) const;
437 /// isLegalAddressingMode - Return true if the addressing mode represented
438 /// by AM is legal for this target, for a load/store of the specified type.
439 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
441 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
443 /// getOptimalMemOpType - Returns the target specific optimal type for load
444 /// and store operations as a result of memset, memcpy, and memmove
445 /// lowering. If DstAlign is zero that means it's safe to destination
446 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
447 /// means there isn't a need to check it against alignment requirement,
448 /// probably because the source does not need to be loaded. If 'IsMemset' is
449 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
450 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
451 /// source is constant so it does not need to be loaded.
452 /// It returns EVT::Other if the type should be determined using generic
453 /// target-independent logic.
455 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
456 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
457 MachineFunction &MF) const;
459 /// Is unaligned memory access allowed for the given type, and is it fast
460 /// relative to software emulation.
461 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const;
463 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
464 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
465 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
466 /// is expanded to mul + add.
467 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
470 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
471 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
474 IsEligibleForTailCallOptimization(SDValue Callee,
475 CallingConv::ID CalleeCC,
477 const SmallVectorImpl<ISD::InputArg> &Ins,
478 SelectionDAG& DAG) const;
480 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
488 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
489 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
499 const PPCSubtarget &Subtarget) const;
500 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
501 const PPCSubtarget &Subtarget) const;
502 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
503 const PPCSubtarget &Subtarget) const;
504 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
505 const PPCSubtarget &Subtarget) const;
506 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
508 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
509 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
510 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
511 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
512 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
513 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
514 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
519 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
520 CallingConv::ID CallConv, bool isVarArg,
521 const SmallVectorImpl<ISD::InputArg> &Ins,
522 SDLoc dl, SelectionDAG &DAG,
523 SmallVectorImpl<SDValue> &InVals) const;
524 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
527 SmallVector<std::pair<unsigned, SDValue>, 8>
529 SDValue InFlag, SDValue Chain,
531 int SPDiff, unsigned NumBytes,
532 const SmallVectorImpl<ISD::InputArg> &Ins,
533 SmallVectorImpl<SDValue> &InVals) const;
536 LowerFormalArguments(SDValue Chain,
537 CallingConv::ID CallConv, bool isVarArg,
538 const SmallVectorImpl<ISD::InputArg> &Ins,
539 SDLoc dl, SelectionDAG &DAG,
540 SmallVectorImpl<SDValue> &InVals) const;
543 LowerCall(TargetLowering::CallLoweringInfo &CLI,
544 SmallVectorImpl<SDValue> &InVals) const;
547 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
549 const SmallVectorImpl<ISD::OutputArg> &Outs,
550 LLVMContext &Context) const;
553 LowerReturn(SDValue Chain,
554 CallingConv::ID CallConv, bool isVarArg,
555 const SmallVectorImpl<ISD::OutputArg> &Outs,
556 const SmallVectorImpl<SDValue> &OutVals,
557 SDLoc dl, SelectionDAG &DAG) const;
560 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
561 SDValue ArgVal, SDLoc dl) const;
564 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
565 unsigned nAltivecParamsAtEnd,
566 unsigned MinReservedArea, bool isPPC64) const;
569 LowerFormalArguments_Darwin(SDValue Chain,
570 CallingConv::ID CallConv, bool isVarArg,
571 const SmallVectorImpl<ISD::InputArg> &Ins,
572 SDLoc dl, SelectionDAG &DAG,
573 SmallVectorImpl<SDValue> &InVals) const;
575 LowerFormalArguments_64SVR4(SDValue Chain,
576 CallingConv::ID CallConv, bool isVarArg,
577 const SmallVectorImpl<ISD::InputArg> &Ins,
578 SDLoc dl, SelectionDAG &DAG,
579 SmallVectorImpl<SDValue> &InVals) const;
581 LowerFormalArguments_32SVR4(SDValue Chain,
582 CallingConv::ID CallConv, bool isVarArg,
583 const SmallVectorImpl<ISD::InputArg> &Ins,
584 SDLoc dl, SelectionDAG &DAG,
585 SmallVectorImpl<SDValue> &InVals) const;
588 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
589 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
590 SelectionDAG &DAG, SDLoc dl) const;
593 LowerCall_Darwin(SDValue Chain, SDValue Callee,
594 CallingConv::ID CallConv,
595 bool isVarArg, bool isTailCall,
596 const SmallVectorImpl<ISD::OutputArg> &Outs,
597 const SmallVectorImpl<SDValue> &OutVals,
598 const SmallVectorImpl<ISD::InputArg> &Ins,
599 SDLoc dl, SelectionDAG &DAG,
600 SmallVectorImpl<SDValue> &InVals) const;
602 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
603 CallingConv::ID CallConv,
604 bool isVarArg, bool isTailCall,
605 const SmallVectorImpl<ISD::OutputArg> &Outs,
606 const SmallVectorImpl<SDValue> &OutVals,
607 const SmallVectorImpl<ISD::InputArg> &Ins,
608 SDLoc dl, SelectionDAG &DAG,
609 SmallVectorImpl<SDValue> &InVals) const;
611 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
612 bool isVarArg, bool isTailCall,
613 const SmallVectorImpl<ISD::OutputArg> &Outs,
614 const SmallVectorImpl<SDValue> &OutVals,
615 const SmallVectorImpl<ISD::InputArg> &Ins,
616 SDLoc dl, SelectionDAG &DAG,
617 SmallVectorImpl<SDValue> &InVals) const;
619 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
620 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
622 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
623 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
626 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
627 CCValAssign::LocInfo &LocInfo,
628 ISD::ArgFlagsTy &ArgFlags,
631 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
633 CCValAssign::LocInfo &LocInfo,
634 ISD::ArgFlagsTy &ArgFlags,
637 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
639 CCValAssign::LocInfo &LocInfo,
640 ISD::ArgFlagsTy &ArgFlags,
644 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H