1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
64 /// The following three target-specific nodes are used for calls through
65 /// function pointers in the 64-bit SVR4 ABI.
67 /// Restore the TOC from the TOC save area of the current stack frame.
68 /// This is basically a hard coded load instruction which additionally
69 /// takes/produces a flag.
72 /// Like a regular LOAD but additionally taking/producing a flag.
75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76 /// a hard coded load instruction.
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
97 /// CALL - A direct function call.
98 /// CALL_NOP_SVR4 is a call with the special NOP which follows 64-bit
100 CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4,
102 /// NOP - Special NOP which follows 64-bit SVR4 calls.
105 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
106 /// MTCTR instruction.
109 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
110 /// BCTRL instruction.
111 BCTRL_Darwin, BCTRL_SVR4,
113 /// Return with a flag operand, matched by 'blr'
116 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
117 /// instructions. This copies the bits corresponding to the specified
118 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
122 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
123 /// instructions. For lack of better number, we use the opcode number
124 /// encoding for the OPC field to identify the compare. For example, 838
128 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
129 /// altivec VCMP*o instructions. For lack of better number, we use the
130 /// opcode number encoding for the OPC field to identify the compare. For
131 /// example, 838 is VCMPGTSH.
134 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
135 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
136 /// condition register to branch on, OPC is the branch opcode to use (e.g.
137 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
138 /// an optional input flag argument.
141 // The following 5 instructions are used only as part of the
142 // long double-to-int conversion sequence.
144 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
148 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
151 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
154 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
155 /// rounding towards zero. It has flags added so it won't move past the
156 /// FPSCR-setting instructions.
159 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
162 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
163 /// reserve indexed. This is used to implement atomic operations.
166 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
167 /// indexed. This is used to implement atomic operations.
170 /// TC_RETURN - A tail call return.
172 /// operand #1 callee (register or absolute)
173 /// operand #2 stack adjustment
174 /// operand #3 optional in flag
177 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
181 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
182 /// TLS model, produces an ADDIS8 instruction that adds the GOT
183 /// base to sym@got@tprel@ha.
186 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
187 /// TLS model, produces a LD instruction with base register G8RReg
188 /// and offset sym@got@tprel@l. This completes the addition that
189 /// finds the offset of "sym" relative to the thread pointer.
192 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
193 /// model, produces an ADD instruction that adds the contents of
194 /// G8RReg to the thread pointer. Symbol contains a relocation
195 /// sym@tls which is to be replaced by the thread pointer and
196 /// identifies to the linker that the instruction is part of a
200 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
201 /// model, produces an ADDIS8 instruction that adds the GOT base
202 /// register to sym@got@tlsgd@ha.
205 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
206 /// model, produces an ADDI8 instruction that adds G8RReg to
210 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
211 /// model, produces a call to __tls_get_addr(sym@tlsgd).
214 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
215 /// model, produces an ADDIS8 instruction that adds the GOT base
216 /// register to sym@got@tlsld@ha.
219 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
220 /// model, produces an ADDI8 instruction that adds G8RReg to
224 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
225 /// model, produces a call to __tls_get_addr(sym@tlsld).
228 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
229 /// local-dynamic TLS model, produces an ADDIS8 instruction
230 /// that adds X3 to sym@dtprel@ha. The Chain operand is needed
231 /// to tie this in place following a copy to %X3 from the result
232 /// of a GET_TLSLD_ADDR.
235 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
236 /// model, produces an ADDI8 instruction that adds G8RReg to
237 /// sym@got@dtprel@l.
240 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
241 /// during instruction selection to optimize a BUILD_VECTOR into
242 /// operations on splats. This is necessary to avoid losing these
243 /// optimizations due to constant folding.
246 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
247 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
249 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
250 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
251 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
255 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
256 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
257 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
261 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
262 /// produces an ADDIS8 instruction that adds the TOC base register to
266 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
267 /// produces a LD instruction with base register G8RReg and offset
268 /// sym@toc@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
271 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
272 /// an ADDI8 instruction that adds G8RReg to sym@toc@l.
273 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
278 /// Define some predicates that are used for node matching.
280 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
281 /// VPKUHUM instruction.
282 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
284 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
285 /// VPKUWUM instruction.
286 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
288 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
289 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
290 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
293 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
294 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
295 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
298 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
299 /// amount, otherwise return -1.
300 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
302 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
303 /// specifies a splat of a single element that is suitable for input to
304 /// VSPLTB/VSPLTH/VSPLTW.
305 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
307 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
309 bool isAllNegativeZeroVector(SDNode *N);
311 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
312 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
313 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
315 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
316 /// formed by using a vspltis[bhw] instruction of the specified element
317 /// size, return the constant being splatted. The ByteSize field indicates
318 /// the number of bytes of each element [124] -> [bhw].
319 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
322 class PPCTargetLowering : public TargetLowering {
323 const PPCSubtarget &PPCSubTarget;
326 explicit PPCTargetLowering(PPCTargetMachine &TM);
328 /// getTargetNodeName() - This method returns the name of a target specific
330 virtual const char *getTargetNodeName(unsigned Opcode) const;
332 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
334 /// getSetCCResultType - Return the ISD::SETCC ValueType
335 virtual EVT getSetCCResultType(EVT VT) const;
337 /// getPreIndexedAddressParts - returns true by value, base pointer and
338 /// offset pointer and addressing mode by reference if the node's address
339 /// can be legally represented as pre-indexed load / store address.
340 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
342 ISD::MemIndexedMode &AM,
343 SelectionDAG &DAG) const;
345 /// SelectAddressRegReg - Given the specified addressed, check to see if it
346 /// can be represented as an indexed [r+r] operation. Returns false if it
347 /// can be more efficiently represented with [r+imm].
348 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
349 SelectionDAG &DAG) const;
351 /// SelectAddressRegImm - Returns true if the address N can be represented
352 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
353 /// is not better represented as reg+reg.
354 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
355 SelectionDAG &DAG) const;
357 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
358 /// represented as an indexed [r+r] operation.
359 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
360 SelectionDAG &DAG) const;
362 /// SelectAddressRegImmShift - Returns true if the address N can be
363 /// represented by a base register plus a signed 14-bit displacement
364 /// [r+imm*4]. Suitable for use by STD and friends.
365 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
366 SelectionDAG &DAG) const;
368 Sched::Preference getSchedulingPreference(SDNode *N) const;
370 /// LowerOperation - Provide custom lowering hooks for some operations.
372 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
374 /// ReplaceNodeResults - Replace the results of node with an illegal result
375 /// type with new values built out of custom code.
377 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
378 SelectionDAG &DAG) const;
380 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
382 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
385 const SelectionDAG &DAG,
386 unsigned Depth = 0) const;
388 virtual MachineBasicBlock *
389 EmitInstrWithCustomInserter(MachineInstr *MI,
390 MachineBasicBlock *MBB) const;
391 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
392 MachineBasicBlock *MBB, bool is64Bit,
393 unsigned BinOpcode) const;
394 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
395 MachineBasicBlock *MBB,
396 bool is8bit, unsigned Opcode) const;
398 ConstraintType getConstraintType(const std::string &Constraint) const;
400 /// Examine constraint string and operand type and determine a weight value.
401 /// The operand object must already have been set up with the operand type.
402 ConstraintWeight getSingleConstraintMatchWeight(
403 AsmOperandInfo &info, const char *constraint) const;
405 std::pair<unsigned, const TargetRegisterClass*>
406 getRegForInlineAsmConstraint(const std::string &Constraint,
409 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
410 /// function arguments in the caller parameter area. This is the actual
411 /// alignment, not its logarithm.
412 unsigned getByValTypeAlignment(Type *Ty) const;
414 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
415 /// vector. If it is invalid, don't add anything to Ops.
416 virtual void LowerAsmOperandForConstraint(SDValue Op,
417 std::string &Constraint,
418 std::vector<SDValue> &Ops,
419 SelectionDAG &DAG) const;
421 /// isLegalAddressingMode - Return true if the addressing mode represented
422 /// by AM is legal for this target, for a load/store of the specified type.
423 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
425 /// isLegalAddressImmediate - Return true if the integer value can be used
426 /// as the offset of the target addressing mode for load / store of the
428 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
430 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
431 /// the offset of the target addressing mode.
432 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
434 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
436 /// getOptimalMemOpType - Returns the target specific optimal type for load
437 /// and store operations as a result of memset, memcpy, and memmove
438 /// lowering. If DstAlign is zero that means it's safe to destination
439 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
440 /// means there isn't a need to check it against alignment requirement,
441 /// probably because the source does not need to be loaded. If 'IsMemset' is
442 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
443 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
444 /// source is constant so it does not need to be loaded.
445 /// It returns EVT::Other if the type should be determined using generic
446 /// target-independent logic.
448 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
449 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
450 MachineFunction &MF) const;
452 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
453 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
454 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
455 /// is expanded to mul + add.
456 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
459 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
460 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
463 IsEligibleForTailCallOptimization(SDValue Callee,
464 CallingConv::ID CalleeCC,
466 const SmallVectorImpl<ISD::InputArg> &Ins,
467 SelectionDAG& DAG) const;
469 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
477 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
487 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
488 const PPCSubtarget &Subtarget) const;
489 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
490 const PPCSubtarget &Subtarget) const;
491 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
492 const PPCSubtarget &Subtarget) const;
493 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
494 const PPCSubtarget &Subtarget) const;
495 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
497 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
506 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
508 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
509 CallingConv::ID CallConv, bool isVarArg,
510 const SmallVectorImpl<ISD::InputArg> &Ins,
511 DebugLoc dl, SelectionDAG &DAG,
512 SmallVectorImpl<SDValue> &InVals) const;
513 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
516 SmallVector<std::pair<unsigned, SDValue>, 8>
518 SDValue InFlag, SDValue Chain,
520 int SPDiff, unsigned NumBytes,
521 const SmallVectorImpl<ISD::InputArg> &Ins,
522 SmallVectorImpl<SDValue> &InVals) const;
525 LowerFormalArguments(SDValue Chain,
526 CallingConv::ID CallConv, bool isVarArg,
527 const SmallVectorImpl<ISD::InputArg> &Ins,
528 DebugLoc dl, SelectionDAG &DAG,
529 SmallVectorImpl<SDValue> &InVals) const;
532 LowerCall(TargetLowering::CallLoweringInfo &CLI,
533 SmallVectorImpl<SDValue> &InVals) const;
536 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
538 const SmallVectorImpl<ISD::OutputArg> &Outs,
539 LLVMContext &Context) const;
542 LowerReturn(SDValue Chain,
543 CallingConv::ID CallConv, bool isVarArg,
544 const SmallVectorImpl<ISD::OutputArg> &Outs,
545 const SmallVectorImpl<SDValue> &OutVals,
546 DebugLoc dl, SelectionDAG &DAG) const;
549 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
550 SDValue ArgVal, DebugLoc dl) const;
553 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
554 unsigned nAltivecParamsAtEnd,
555 unsigned MinReservedArea, bool isPPC64) const;
558 LowerFormalArguments_Darwin(SDValue Chain,
559 CallingConv::ID CallConv, bool isVarArg,
560 const SmallVectorImpl<ISD::InputArg> &Ins,
561 DebugLoc dl, SelectionDAG &DAG,
562 SmallVectorImpl<SDValue> &InVals) const;
564 LowerFormalArguments_64SVR4(SDValue Chain,
565 CallingConv::ID CallConv, bool isVarArg,
566 const SmallVectorImpl<ISD::InputArg> &Ins,
567 DebugLoc dl, SelectionDAG &DAG,
568 SmallVectorImpl<SDValue> &InVals) const;
570 LowerFormalArguments_32SVR4(SDValue Chain,
571 CallingConv::ID CallConv, bool isVarArg,
572 const SmallVectorImpl<ISD::InputArg> &Ins,
573 DebugLoc dl, SelectionDAG &DAG,
574 SmallVectorImpl<SDValue> &InVals) const;
577 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
578 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
579 SelectionDAG &DAG, DebugLoc dl) const;
582 LowerCall_Darwin(SDValue Chain, SDValue Callee,
583 CallingConv::ID CallConv,
584 bool isVarArg, bool isTailCall,
585 const SmallVectorImpl<ISD::OutputArg> &Outs,
586 const SmallVectorImpl<SDValue> &OutVals,
587 const SmallVectorImpl<ISD::InputArg> &Ins,
588 DebugLoc dl, SelectionDAG &DAG,
589 SmallVectorImpl<SDValue> &InVals) const;
591 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
592 CallingConv::ID CallConv,
593 bool isVarArg, bool isTailCall,
594 const SmallVectorImpl<ISD::OutputArg> &Outs,
595 const SmallVectorImpl<SDValue> &OutVals,
596 const SmallVectorImpl<ISD::InputArg> &Ins,
597 DebugLoc dl, SelectionDAG &DAG,
598 SmallVectorImpl<SDValue> &InVals) const;
600 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
601 bool isVarArg, bool isTailCall,
602 const SmallVectorImpl<ISD::OutputArg> &Outs,
603 const SmallVectorImpl<SDValue> &OutVals,
604 const SmallVectorImpl<ISD::InputArg> &Ins,
605 DebugLoc dl, SelectionDAG &DAG,
606 SmallVectorImpl<SDValue> &InVals) const;
610 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H