1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "PPCSubtarget.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// Hi/Lo - These represent the high and low 16-bit parts of a global
65 /// address respectively. These nodes have two operands, the first of
66 /// which must be a TargetGlobalAddress, and the second of which must be a
67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
68 /// though these are usually folded into other nodes.
73 /// The following three target-specific nodes are used for calls through
74 /// function pointers in the 64-bit SVR4 ABI.
76 /// Restore the TOC from the TOC save area of the current stack frame.
77 /// This is basically a hard coded load instruction which additionally
78 /// takes/produces a flag.
81 /// Like a regular LOAD but additionally taking/producing a flag.
84 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
85 /// a hard coded load instruction.
88 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
89 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
90 /// compute an allocation on the stack.
93 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
94 /// at function entry, used for PIC code.
97 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
98 /// shift amounts. These nodes are generated by the multi-precision shift
102 /// CALL - A direct function call.
103 /// CALL_NOP is a call with the special NOP which follows 64-bit
107 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
108 /// MTCTR instruction.
111 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
112 /// BCTRL instruction.
115 /// Return with a flag operand, matched by 'blr'
118 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
119 /// instructions. This copies the bits corresponding to the specified
120 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
124 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
127 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
130 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
131 /// instructions. For lack of better number, we use the opcode number
132 /// encoding for the OPC field to identify the compare. For example, 838
136 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
137 /// altivec VCMP*o instructions. For lack of better number, we use the
138 /// opcode number encoding for the OPC field to identify the compare. For
139 /// example, 838 is VCMPGTSH.
142 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
144 /// condition register to branch on, OPC is the branch opcode to use (e.g.
145 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
146 /// an optional input flag argument.
149 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
153 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
154 /// towards zero. Used only as part of the long double-to-int
155 /// conversion sequence.
158 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
161 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
162 /// reserve indexed. This is used to implement atomic operations.
165 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
166 /// indexed. This is used to implement atomic operations.
169 /// TC_RETURN - A tail call return.
171 /// operand #1 callee (register or absolute)
172 /// operand #2 stack adjustment
173 /// operand #3 optional in flag
176 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
180 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
181 /// TLS model, produces an ADDIS8 instruction that adds the GOT
182 /// base to sym\@got\@tprel\@ha.
185 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
186 /// TLS model, produces a LD instruction with base register G8RReg
187 /// and offset sym\@got\@tprel\@l. This completes the addition that
188 /// finds the offset of "sym" relative to the thread pointer.
191 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
192 /// model, produces an ADD instruction that adds the contents of
193 /// G8RReg to the thread pointer. Symbol contains a relocation
194 /// sym\@tls which is to be replaced by the thread pointer and
195 /// identifies to the linker that the instruction is part of a
199 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
200 /// model, produces an ADDIS8 instruction that adds the GOT base
201 /// register to sym\@got\@tlsgd\@ha.
204 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
205 /// model, produces an ADDI8 instruction that adds G8RReg to
206 /// sym\@got\@tlsgd\@l.
209 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
210 /// model, produces a call to __tls_get_addr(sym\@tlsgd).
213 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
214 /// model, produces an ADDIS8 instruction that adds the GOT base
215 /// register to sym\@got\@tlsld\@ha.
218 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
219 /// model, produces an ADDI8 instruction that adds G8RReg to
220 /// sym\@got\@tlsld\@l.
223 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
224 /// model, produces a call to __tls_get_addr(sym\@tlsld).
227 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
228 /// local-dynamic TLS model, produces an ADDIS8 instruction
229 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
230 /// to tie this in place following a copy to %X3 from the result
231 /// of a GET_TLSLD_ADDR.
234 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
235 /// model, produces an ADDI8 instruction that adds G8RReg to
236 /// sym\@got\@dtprel\@l.
239 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
240 /// during instruction selection to optimize a BUILD_VECTOR into
241 /// operations on splats. This is necessary to avoid losing these
242 /// optimizations due to constant folding.
245 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
246 /// operand identifies the operating system entry point.
249 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
250 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
251 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
253 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
255 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
256 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
257 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
261 /// STFIWX - The STFIWX instruction. The first operand is an input token
262 /// chain, then an f64 value to store, then an address to store it to.
265 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
266 /// load which sign-extends from a 32-bit integer value into the
267 /// destination 64-bit register.
270 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
271 /// load which zero-extends from a 32-bit integer value into the
272 /// destination 64-bit register.
275 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
276 /// produces an ADDIS8 instruction that adds the TOC base register to
280 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
281 /// produces a LD instruction with base register G8RReg and offset
282 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
285 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
286 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
287 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
292 /// Define some predicates that are used for node matching.
294 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
295 /// VPKUHUM instruction.
296 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
298 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
299 /// VPKUWUM instruction.
300 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
302 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
303 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
304 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
307 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
308 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
309 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
312 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
313 /// amount, otherwise return -1.
314 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
316 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
317 /// specifies a splat of a single element that is suitable for input to
318 /// VSPLTB/VSPLTH/VSPLTW.
319 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
321 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
323 bool isAllNegativeZeroVector(SDNode *N);
325 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
326 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
327 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
329 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
330 /// formed by using a vspltis[bhw] instruction of the specified element
331 /// size, return the constant being splatted. The ByteSize field indicates
332 /// the number of bytes of each element [124] -> [bhw].
333 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
336 class PPCTargetLowering : public TargetLowering {
337 const PPCSubtarget &PPCSubTarget;
338 const PPCRegisterInfo *PPCRegInfo;
339 const PPCInstrInfo *PPCII;
342 explicit PPCTargetLowering(PPCTargetMachine &TM);
344 /// getTargetNodeName() - This method returns the name of a target specific
346 virtual const char *getTargetNodeName(unsigned Opcode) const;
348 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
350 /// getSetCCResultType - Return the ISD::SETCC ValueType
351 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
353 /// getPreIndexedAddressParts - returns true by value, base pointer and
354 /// offset pointer and addressing mode by reference if the node's address
355 /// can be legally represented as pre-indexed load / store address.
356 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
358 ISD::MemIndexedMode &AM,
359 SelectionDAG &DAG) const;
361 /// SelectAddressRegReg - Given the specified addressed, check to see if it
362 /// can be represented as an indexed [r+r] operation. Returns false if it
363 /// can be more efficiently represented with [r+imm].
364 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
365 SelectionDAG &DAG) const;
367 /// SelectAddressRegImm - Returns true if the address N can be represented
368 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
369 /// is not better represented as reg+reg. If Aligned is true, only accept
370 /// displacements suitable for STD and friends, i.e. multiples of 4.
371 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
372 SelectionDAG &DAG, bool Aligned) const;
374 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
375 /// represented as an indexed [r+r] operation.
376 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
377 SelectionDAG &DAG) const;
379 Sched::Preference getSchedulingPreference(SDNode *N) const;
381 /// LowerOperation - Provide custom lowering hooks for some operations.
383 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
385 /// ReplaceNodeResults - Replace the results of node with an illegal result
386 /// type with new values built out of custom code.
388 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
389 SelectionDAG &DAG) const;
391 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
393 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
396 const SelectionDAG &DAG,
397 unsigned Depth = 0) const;
399 virtual MachineBasicBlock *
400 EmitInstrWithCustomInserter(MachineInstr *MI,
401 MachineBasicBlock *MBB) const;
402 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
403 MachineBasicBlock *MBB, bool is64Bit,
404 unsigned BinOpcode) const;
405 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
406 MachineBasicBlock *MBB,
407 bool is8bit, unsigned Opcode) const;
409 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
410 MachineBasicBlock *MBB) const;
412 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
413 MachineBasicBlock *MBB) const;
415 ConstraintType getConstraintType(const std::string &Constraint) const;
417 /// Examine constraint string and operand type and determine a weight value.
418 /// The operand object must already have been set up with the operand type.
419 ConstraintWeight getSingleConstraintMatchWeight(
420 AsmOperandInfo &info, const char *constraint) const;
422 std::pair<unsigned, const TargetRegisterClass*>
423 getRegForInlineAsmConstraint(const std::string &Constraint,
426 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
427 /// function arguments in the caller parameter area. This is the actual
428 /// alignment, not its logarithm.
429 unsigned getByValTypeAlignment(Type *Ty) const;
431 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
432 /// vector. If it is invalid, don't add anything to Ops.
433 virtual void LowerAsmOperandForConstraint(SDValue Op,
434 std::string &Constraint,
435 std::vector<SDValue> &Ops,
436 SelectionDAG &DAG) const;
438 /// isLegalAddressingMode - Return true if the addressing mode represented
439 /// by AM is legal for this target, for a load/store of the specified type.
440 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
442 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
444 /// getOptimalMemOpType - Returns the target specific optimal type for load
445 /// and store operations as a result of memset, memcpy, and memmove
446 /// lowering. If DstAlign is zero that means it's safe to destination
447 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
448 /// means there isn't a need to check it against alignment requirement,
449 /// probably because the source does not need to be loaded. If 'IsMemset' is
450 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
451 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
452 /// source is constant so it does not need to be loaded.
453 /// It returns EVT::Other if the type should be determined using generic
454 /// target-independent logic.
456 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
457 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
458 MachineFunction &MF) const;
460 /// Is unaligned memory access allowed for the given type, and is it fast
461 /// relative to software emulation.
462 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast = 0) const;
464 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
465 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
466 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
467 /// is expanded to mul + add.
468 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
471 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
472 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
475 IsEligibleForTailCallOptimization(SDValue Callee,
476 CallingConv::ID CalleeCC,
478 const SmallVectorImpl<ISD::InputArg> &Ins,
479 SelectionDAG& DAG) const;
481 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
489 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
490 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
491 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
492 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
493 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
494 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
496 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
500 const PPCSubtarget &Subtarget) const;
501 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
502 const PPCSubtarget &Subtarget) const;
503 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
504 const PPCSubtarget &Subtarget) const;
505 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
506 const PPCSubtarget &Subtarget) const;
507 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
508 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
509 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
510 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
511 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
512 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
513 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
514 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
516 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
517 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
518 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
520 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
521 CallingConv::ID CallConv, bool isVarArg,
522 const SmallVectorImpl<ISD::InputArg> &Ins,
523 SDLoc dl, SelectionDAG &DAG,
524 SmallVectorImpl<SDValue> &InVals) const;
525 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
528 SmallVector<std::pair<unsigned, SDValue>, 8>
530 SDValue InFlag, SDValue Chain,
532 int SPDiff, unsigned NumBytes,
533 const SmallVectorImpl<ISD::InputArg> &Ins,
534 SmallVectorImpl<SDValue> &InVals) const;
537 LowerFormalArguments(SDValue Chain,
538 CallingConv::ID CallConv, bool isVarArg,
539 const SmallVectorImpl<ISD::InputArg> &Ins,
540 SDLoc dl, SelectionDAG &DAG,
541 SmallVectorImpl<SDValue> &InVals) const;
544 LowerCall(TargetLowering::CallLoweringInfo &CLI,
545 SmallVectorImpl<SDValue> &InVals) const;
548 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
550 const SmallVectorImpl<ISD::OutputArg> &Outs,
551 LLVMContext &Context) const;
554 LowerReturn(SDValue Chain,
555 CallingConv::ID CallConv, bool isVarArg,
556 const SmallVectorImpl<ISD::OutputArg> &Outs,
557 const SmallVectorImpl<SDValue> &OutVals,
558 SDLoc dl, SelectionDAG &DAG) const;
561 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
562 SDValue ArgVal, SDLoc dl) const;
565 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
566 unsigned nAltivecParamsAtEnd,
567 unsigned MinReservedArea, bool isPPC64) const;
570 LowerFormalArguments_Darwin(SDValue Chain,
571 CallingConv::ID CallConv, bool isVarArg,
572 const SmallVectorImpl<ISD::InputArg> &Ins,
573 SDLoc dl, SelectionDAG &DAG,
574 SmallVectorImpl<SDValue> &InVals) const;
576 LowerFormalArguments_64SVR4(SDValue Chain,
577 CallingConv::ID CallConv, bool isVarArg,
578 const SmallVectorImpl<ISD::InputArg> &Ins,
579 SDLoc dl, SelectionDAG &DAG,
580 SmallVectorImpl<SDValue> &InVals) const;
582 LowerFormalArguments_32SVR4(SDValue Chain,
583 CallingConv::ID CallConv, bool isVarArg,
584 const SmallVectorImpl<ISD::InputArg> &Ins,
585 SDLoc dl, SelectionDAG &DAG,
586 SmallVectorImpl<SDValue> &InVals) const;
589 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
590 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
591 SelectionDAG &DAG, SDLoc dl) const;
594 LowerCall_Darwin(SDValue Chain, SDValue Callee,
595 CallingConv::ID CallConv,
596 bool isVarArg, bool isTailCall,
597 const SmallVectorImpl<ISD::OutputArg> &Outs,
598 const SmallVectorImpl<SDValue> &OutVals,
599 const SmallVectorImpl<ISD::InputArg> &Ins,
600 SDLoc dl, SelectionDAG &DAG,
601 SmallVectorImpl<SDValue> &InVals) const;
603 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
604 CallingConv::ID CallConv,
605 bool isVarArg, bool isTailCall,
606 const SmallVectorImpl<ISD::OutputArg> &Outs,
607 const SmallVectorImpl<SDValue> &OutVals,
608 const SmallVectorImpl<ISD::InputArg> &Ins,
609 SDLoc dl, SelectionDAG &DAG,
610 SmallVectorImpl<SDValue> &InVals) const;
612 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
613 bool isVarArg, bool isTailCall,
614 const SmallVectorImpl<ISD::OutputArg> &Outs,
615 const SmallVectorImpl<SDValue> &OutVals,
616 const SmallVectorImpl<ISD::InputArg> &Ins,
617 SDLoc dl, SelectionDAG &DAG,
618 SmallVectorImpl<SDValue> &InVals) const;
620 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
621 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
623 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
624 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
628 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H