1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to,
45 /// then a SRCVALUE for the address.
48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
49 // three v4f32 operands and producing a v4f32 result.
52 /// VPERM - The PPC VPERM Instruction.
56 /// Hi/Lo - These represent the high and low 16-bit parts of a global
57 /// address respectively. These nodes have two operands, the first of
58 /// which must be a TargetGlobalAddress, and the second of which must be a
59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
60 /// though these are usually folded into other nodes.
63 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
64 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
65 /// compute an allocation on the stack.
68 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
69 /// at function entry, used for PIC code.
72 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
73 /// shift amounts. These nodes are generated by the multi-precision shift
77 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
81 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
84 /// CALL - A direct function call.
87 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
88 /// MTCTR instruction.
91 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
92 /// BCTRL instruction.
93 BCTRL_Macho, BCTRL_ELF,
95 /// Return with a flag operand, matched by 'blr'
98 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
99 /// This copies the bits corresponding to the specified CRREG into the
100 /// resultant GPR. Bits corresponding to other CR regs are undefined.
103 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
104 /// instructions. For lack of better number, we use the opcode number
105 /// encoding for the OPC field to identify the compare. For example, 838
109 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
110 /// altivec VCMP*o instructions. For lack of better number, we use the
111 /// opcode number encoding for the OPC field to identify the compare. For
112 /// example, 838 is VCMPGTSH.
115 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
116 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
117 /// condition register to branch on, OPC is the branch opcode to use (e.g.
118 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
119 /// an optional input flag argument.
122 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a
123 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
124 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
128 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a
129 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
130 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
134 // The following 5 instructions are used only as part of the
135 // long double-to-int conversion sequence.
137 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
141 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
144 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
147 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
148 /// rounding towards zero. It has flags added so it won't move past the
149 /// FPSCR-setting instructions.
152 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
157 /// Define some predicates that are used for node matching.
159 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
160 /// VPKUHUM instruction.
161 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary);
163 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
164 /// VPKUWUM instruction.
165 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary);
167 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
168 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
169 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
171 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
172 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
173 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
175 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
176 /// amount, otherwise return -1.
177 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
179 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
180 /// specifies a splat of a single element that is suitable for input to
181 /// VSPLTB/VSPLTH/VSPLTW.
182 bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
184 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
186 bool isAllNegativeZeroVector(SDNode *N);
188 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
189 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
190 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
192 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
193 /// formed by using a vspltis[bhw] instruction of the specified element
194 /// size, return the constant being splatted. The ByteSize field indicates
195 /// the number of bytes of each element [124] -> [bhw].
196 SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
199 class PPCTargetLowering : public TargetLowering {
200 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
201 int VarArgsStackOffset; // StackOffset for start of stack
203 unsigned VarArgsNumGPR; // Index of the first unused integer
204 // register for parameter passing.
205 unsigned VarArgsNumFPR; // Index of the first unused double
206 // register for parameter passing.
207 int ReturnAddrIndex; // FrameIndex for return slot.
208 const PPCSubtarget &PPCSubTarget;
210 explicit PPCTargetLowering(PPCTargetMachine &TM);
212 /// getTargetNodeName() - This method returns the name of a target specific
214 virtual const char *getTargetNodeName(unsigned Opcode) const;
216 /// getSetCCResultType - Return the ISD::SETCC ValueType
217 virtual MVT::ValueType getSetCCResultType(const SDOperand &) const;
219 /// getPreIndexedAddressParts - returns true by value, base pointer and
220 /// offset pointer and addressing mode by reference if the node's address
221 /// can be legally represented as pre-indexed load / store address.
222 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
224 ISD::MemIndexedMode &AM,
227 /// SelectAddressRegReg - Given the specified addressed, check to see if it
228 /// can be represented as an indexed [r+r] operation. Returns false if it
229 /// can be more efficiently represented with [r+imm].
230 bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index,
233 /// SelectAddressRegImm - Returns true if the address N can be represented
234 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
235 /// is not better represented as reg+reg.
236 bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base,
239 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
240 /// represented as an indexed [r+r] operation.
241 bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index,
244 /// SelectAddressRegImmShift - Returns true if the address N can be
245 /// represented by a base register plus a signed 14-bit displacement
246 /// [r+imm*4]. Suitable for use by STD and friends.
247 bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base,
251 /// LowerOperation - Provide custom lowering hooks for some operations.
253 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
255 virtual SDNode *ExpandOperationResult(SDNode *N, SelectionDAG &DAG);
257 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
259 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
263 const SelectionDAG &DAG,
264 unsigned Depth = 0) const;
266 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
267 MachineBasicBlock *MBB);
269 ConstraintType getConstraintType(const std::string &Constraint) const;
270 std::pair<unsigned, const TargetRegisterClass*>
271 getRegForInlineAsmConstraint(const std::string &Constraint,
272 MVT::ValueType VT) const;
274 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
275 /// function arguments in the caller parameter area. This is the actual
276 /// alignment, not its logarithm.
277 unsigned getByValTypeAlignment(const Type *Ty) const;
279 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
280 /// vector. If it is invalid, don't add anything to Ops.
281 virtual void LowerAsmOperandForConstraint(SDOperand Op,
282 char ConstraintLetter,
283 std::vector<SDOperand> &Ops,
286 /// isLegalAddressingMode - Return true if the addressing mode represented
287 /// by AM is legal for this target, for a load/store of the specified type.
288 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
290 /// isLegalAddressImmediate - Return true if the integer value can be used
291 /// as the offset of the target addressing mode for load / store of the
293 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
295 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
296 /// the offset of the target addressing mode.
297 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
299 SDOperand LowerRETURNADDR(SDOperand Op, SelectionDAG &DAG);
300 SDOperand LowerFRAMEADDR(SDOperand Op, SelectionDAG &DAG);
301 SDOperand LowerConstantPool(SDOperand Op, SelectionDAG &DAG);
302 SDOperand LowerGlobalAddress(SDOperand Op, SelectionDAG &DAG);
303 SDOperand LowerGlobalTLSAddress(SDOperand Op, SelectionDAG &DAG);
304 SDOperand LowerJumpTable(SDOperand Op, SelectionDAG &DAG);
305 SDOperand LowerSETCC(SDOperand Op, SelectionDAG &DAG);
306 SDOperand LowerVASTART(SDOperand Op, SelectionDAG &DAG,
307 int VarArgsFrameIndex, int VarArgsStackOffset,
308 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
309 const PPCSubtarget &Subtarget);
310 SDOperand LowerVAARG(SDOperand Op, SelectionDAG &DAG, int VarArgsFrameIndex,
311 int VarArgsStackOffset, unsigned VarArgsNumGPR,
312 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
313 SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
314 int &VarArgsFrameIndex,
315 int &VarArgsStackOffset,
316 unsigned &VarArgsNumGPR,
317 unsigned &VarArgsNumFPR,
318 const PPCSubtarget &Subtarget);
319 SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG,
320 const PPCSubtarget &Subtarget, TargetMachine &TM);
321 SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, TargetMachine &TM);
322 SDOperand LowerSTACKRESTORE(SDOperand Op, SelectionDAG &DAG,
323 const PPCSubtarget &Subtarget);
324 SDOperand LowerDYNAMIC_STACKALLOC(SDOperand Op, SelectionDAG &DAG,
325 const PPCSubtarget &Subtarget);
326 SDOperand LowerSELECT_CC(SDOperand Op, SelectionDAG &DAG);
327 SDOperand LowerFP_TO_SINT(SDOperand Op, SelectionDAG &DAG);
328 SDOperand LowerSINT_TO_FP(SDOperand Op, SelectionDAG &DAG);
329 SDOperand LowerFP_ROUND_INREG(SDOperand Op, SelectionDAG &DAG);
330 SDOperand LowerFLT_ROUNDS_(SDOperand Op, SelectionDAG &DAG);
331 SDOperand LowerSHL_PARTS(SDOperand Op, SelectionDAG &DAG);
332 SDOperand LowerSRL_PARTS(SDOperand Op, SelectionDAG &DAG);
333 SDOperand LowerSRA_PARTS(SDOperand Op, SelectionDAG &DAG);
334 SDOperand LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG);
335 SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG);
336 SDOperand LowerINTRINSIC_WO_CHAIN(SDOperand Op, SelectionDAG &DAG);
337 SDOperand LowerSCALAR_TO_VECTOR(SDOperand Op, SelectionDAG &DAG);
338 SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG);
342 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H