1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
27 enum NodeType : unsigned {
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
74 /// The following two target-specific nodes are used for calls through
75 /// function pointers in the 64-bit SVR4 ABI.
77 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
78 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
79 /// compute an allocation on the stack.
82 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
83 /// at function entry, used for PIC code.
86 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
87 /// shift amounts. These nodes are generated by the multi-precision shift
91 /// The combination of sra[wd]i and addze used to implemented signed
92 /// integer division by a power of 2. The first operand is the dividend,
93 /// and the second is the constant shift amount (representing the
97 /// CALL - A direct function call.
98 /// CALL_NOP is a call with the special NOP which follows 64-bit
102 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
103 /// MTCTR instruction.
106 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
107 /// BCTRL instruction.
110 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
111 /// instruction and the TOC reload required on SVR4 PPC64.
114 /// Return with a flag operand, matched by 'blr'
117 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
118 /// This copies the bits corresponding to the specified CRREG into the
119 /// resultant GPR. Bits corresponding to other CR regs are undefined.
122 /// Direct move from a VSX register to a GPR
125 /// Direct move from a GPR to a VSX register (algebraic)
128 /// Direct move from a GPR to a VSX register (zero)
131 // FIXME: Remove these once the ANDI glue bug is fixed:
132 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
133 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
134 /// implement truncation of i32 or i64 to i1.
135 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
137 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
138 // target (returns (Lo, Hi)). It takes a chain operand.
141 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
144 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
147 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
148 /// instructions. For lack of better number, we use the opcode number
149 /// encoding for the OPC field to identify the compare. For example, 838
153 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
154 /// altivec VCMP*o instructions. For lack of better number, we use the
155 /// opcode number encoding for the OPC field to identify the compare. For
156 /// example, 838 is VCMPGTSH.
159 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
160 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
161 /// condition register to branch on, OPC is the branch opcode to use (e.g.
162 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
163 /// an optional input flag argument.
166 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
170 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
171 /// towards zero. Used only as part of the long double-to-int
172 /// conversion sequence.
175 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
178 /// TC_RETURN - A tail call return.
180 /// operand #1 callee (register or absolute)
181 /// operand #2 stack adjustment
182 /// operand #3 optional in flag
185 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
189 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
193 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
194 /// local dynamic TLS on PPC32.
197 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
198 /// TLS model, produces an ADDIS8 instruction that adds the GOT
199 /// base to sym\@got\@tprel\@ha.
202 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
203 /// TLS model, produces a LD instruction with base register G8RReg
204 /// and offset sym\@got\@tprel\@l. This completes the addition that
205 /// finds the offset of "sym" relative to the thread pointer.
208 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
209 /// model, produces an ADD instruction that adds the contents of
210 /// G8RReg to the thread pointer. Symbol contains a relocation
211 /// sym\@tls which is to be replaced by the thread pointer and
212 /// identifies to the linker that the instruction is part of a
216 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
217 /// model, produces an ADDIS8 instruction that adds the GOT base
218 /// register to sym\@got\@tlsgd\@ha.
221 /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
222 /// model, produces an ADDI8 instruction that adds G8RReg to
223 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
224 /// ADDIS_TLSGD_L_ADDR until after register assignment.
227 /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
228 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
229 /// ADDIS_TLSGD_L_ADDR until after register assignment.
232 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
233 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
234 /// register assignment.
237 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
238 /// model, produces an ADDIS8 instruction that adds the GOT base
239 /// register to sym\@got\@tlsld\@ha.
242 /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
243 /// model, produces an ADDI8 instruction that adds G8RReg to
244 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
245 /// ADDIS_TLSLD_L_ADDR until after register assignment.
248 /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
249 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
250 /// ADDIS_TLSLD_L_ADDR until after register assignment.
253 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
254 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
255 /// following register assignment.
258 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
259 /// model, produces an ADDIS8 instruction that adds X3 to
263 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
264 /// model, produces an ADDI8 instruction that adds G8RReg to
265 /// sym\@got\@dtprel\@l.
268 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
269 /// during instruction selection to optimize a BUILD_VECTOR into
270 /// operations on splats. This is necessary to avoid losing these
271 /// optimizations due to constant folding.
274 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
275 /// operand identifies the operating system entry point.
278 /// CHAIN = CLRBHRB CHAIN - Clear branch history rolling buffer.
281 /// GPRC, CHAIN = MFBHRBE CHAIN, Entry, Dummy - Move from branch
282 /// history rolling buffer entry.
285 /// CHAIN = RFEBB CHAIN, State - Return from event-based branch.
288 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
289 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
290 /// or stxvd2x instruction. The chain is necessary because the
291 /// sequence replaces a load and needs to provide the same number
295 /// QVFPERM = This corresponds to the QPX qvfperm instruction.
298 /// QVGPCI = This corresponds to the QPX qvgpci instruction.
301 /// QVALIGNI = This corresponds to the QPX qvaligni instruction.
304 /// QVESPLATI = This corresponds to the QPX qvesplati instruction.
307 /// QBFLT = Access the underlying QPX floating-point boolean
311 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
312 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
313 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
315 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
317 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
318 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
319 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
323 /// STFIWX - The STFIWX instruction. The first operand is an input token
324 /// chain, then an f64 value to store, then an address to store it to.
327 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
328 /// load which sign-extends from a 32-bit integer value into the
329 /// destination 64-bit register.
332 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
333 /// load which zero-extends from a 32-bit integer value into the
334 /// destination 64-bit register.
337 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
338 /// Maps directly to an lxvd2x instruction that will be followed by
342 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
343 /// Maps directly to an stxvd2x instruction that will be preceded by
347 /// QBRC, CHAIN = QVLFSb CHAIN, Ptr
348 /// The 4xf32 load used for v4i1 constants.
351 /// GPRC = TOC_ENTRY GA, TOC
352 /// Loads the entry for GA from the TOC, where the TOC base is given by
353 /// the last operand.
358 /// Define some predicates that are used for node matching.
360 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
361 /// VPKUHUM instruction.
362 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
365 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
366 /// VPKUWUM instruction.
367 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
370 /// isVPKUDUMShuffleMask - Return true if this is the shuffle mask for a
371 /// VPKUDUM instruction.
372 bool isVPKUDUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
375 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
376 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
377 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
378 unsigned ShuffleKind, SelectionDAG &DAG);
380 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
381 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
382 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
383 unsigned ShuffleKind, SelectionDAG &DAG);
385 /// isVMRGEOShuffleMask - Return true if this is a shuffle mask suitable for
386 /// a VMRGEW or VMRGOW instruction
387 bool isVMRGEOShuffleMask(ShuffleVectorSDNode *N, bool CheckEven,
388 unsigned ShuffleKind, SelectionDAG &DAG);
390 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
391 /// shift amount, otherwise return -1.
392 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
395 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
396 /// specifies a splat of a single element that is suitable for input to
397 /// VSPLTB/VSPLTH/VSPLTW.
398 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
400 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
401 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
402 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
404 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
405 /// formed by using a vspltis[bhw] instruction of the specified element
406 /// size, return the constant being splatted. The ByteSize field indicates
407 /// the number of bytes of each element [124] -> [bhw].
408 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
410 /// If this is a qvaligni shuffle mask, return the shift
411 /// amount, otherwise return -1.
412 int isQVALIGNIShuffleMask(SDNode *N);
415 class PPCTargetLowering : public TargetLowering {
416 const PPCSubtarget &Subtarget;
419 explicit PPCTargetLowering(const PPCTargetMachine &TM,
420 const PPCSubtarget &STI);
422 /// getTargetNodeName() - This method returns the name of a target specific
424 const char *getTargetNodeName(unsigned Opcode) const override;
426 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override {
430 bool isCheapToSpeculateCttz() const override {
434 bool isCheapToSpeculateCtlz() const override {
438 /// getSetCCResultType - Return the ISD::SETCC ValueType
439 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
440 EVT VT) const override;
442 /// Return true if target always beneficiates from combining into FMA for a
443 /// given value type. This must typically return false on targets where FMA
444 /// takes more cycles to execute than FADD.
445 bool enableAggressiveFMAFusion(EVT VT) const override;
447 /// getPreIndexedAddressParts - returns true by value, base pointer and
448 /// offset pointer and addressing mode by reference if the node's address
449 /// can be legally represented as pre-indexed load / store address.
450 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
452 ISD::MemIndexedMode &AM,
453 SelectionDAG &DAG) const override;
455 /// SelectAddressRegReg - Given the specified addressed, check to see if it
456 /// can be represented as an indexed [r+r] operation. Returns false if it
457 /// can be more efficiently represented with [r+imm].
458 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
459 SelectionDAG &DAG) const;
461 /// SelectAddressRegImm - Returns true if the address N can be represented
462 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
463 /// is not better represented as reg+reg. If Aligned is true, only accept
464 /// displacements suitable for STD and friends, i.e. multiples of 4.
465 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
466 SelectionDAG &DAG, bool Aligned) const;
468 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
469 /// represented as an indexed [r+r] operation.
470 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
471 SelectionDAG &DAG) const;
473 Sched::Preference getSchedulingPreference(SDNode *N) const override;
475 /// LowerOperation - Provide custom lowering hooks for some operations.
477 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
479 /// ReplaceNodeResults - Replace the results of node with an illegal result
480 /// type with new values built out of custom code.
482 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
483 SelectionDAG &DAG) const override;
485 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
486 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
488 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
490 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
491 std::vector<SDNode *> *Created) const override;
493 unsigned getRegisterByName(const char* RegName, EVT VT,
494 SelectionDAG &DAG) const override;
496 void computeKnownBitsForTargetNode(const SDValue Op,
499 const SelectionDAG &DAG,
500 unsigned Depth = 0) const override;
502 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
504 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
505 bool IsStore, bool IsLoad) const override;
506 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
507 bool IsStore, bool IsLoad) const override;
510 EmitInstrWithCustomInserter(MachineInstr *MI,
511 MachineBasicBlock *MBB) const override;
512 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
513 MachineBasicBlock *MBB,
515 unsigned BinOpcode) const;
516 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
517 MachineBasicBlock *MBB,
518 bool is8bit, unsigned Opcode) const;
520 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
521 MachineBasicBlock *MBB) const;
523 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
524 MachineBasicBlock *MBB) const;
526 ConstraintType getConstraintType(StringRef Constraint) const override;
528 /// Examine constraint string and operand type and determine a weight value.
529 /// The operand object must already have been set up with the operand type.
530 ConstraintWeight getSingleConstraintMatchWeight(
531 AsmOperandInfo &info, const char *constraint) const override;
533 std::pair<unsigned, const TargetRegisterClass *>
534 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
535 StringRef Constraint, MVT VT) const override;
537 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
538 /// function arguments in the caller parameter area. This is the actual
539 /// alignment, not its logarithm.
540 unsigned getByValTypeAlignment(Type *Ty,
541 const DataLayout &DL) const override;
543 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
544 /// vector. If it is invalid, don't add anything to Ops.
545 void LowerAsmOperandForConstraint(SDValue Op,
546 std::string &Constraint,
547 std::vector<SDValue> &Ops,
548 SelectionDAG &DAG) const override;
551 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
552 if (ConstraintCode == "es")
553 return InlineAsm::Constraint_es;
554 else if (ConstraintCode == "o")
555 return InlineAsm::Constraint_o;
556 else if (ConstraintCode == "Q")
557 return InlineAsm::Constraint_Q;
558 else if (ConstraintCode == "Z")
559 return InlineAsm::Constraint_Z;
560 else if (ConstraintCode == "Zy")
561 return InlineAsm::Constraint_Zy;
562 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
565 /// isLegalAddressingMode - Return true if the addressing mode represented
566 /// by AM is legal for this target, for a load/store of the specified type.
567 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
568 Type *Ty, unsigned AS) const override;
570 /// isLegalICmpImmediate - Return true if the specified immediate is legal
571 /// icmp immediate, that is the target has icmp instructions which can
572 /// compare a register against the immediate without having to materialize
573 /// the immediate into a register.
574 bool isLegalICmpImmediate(int64_t Imm) const override;
576 /// isLegalAddImmediate - Return true if the specified immediate is legal
577 /// add immediate, that is the target has add instructions which can
578 /// add a register and the immediate without having to materialize
579 /// the immediate into a register.
580 bool isLegalAddImmediate(int64_t Imm) const override;
582 /// isTruncateFree - Return true if it's free to truncate a value of
583 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
584 /// register X1 to i32 by referencing its sub-register R1.
585 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
586 bool isTruncateFree(EVT VT1, EVT VT2) const override;
588 bool isZExtFree(SDValue Val, EVT VT2) const override;
590 bool isFPExtFree(EVT VT) const override;
592 /// \brief Returns true if it is beneficial to convert a load of a constant
593 /// to just the constant itself.
594 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
595 Type *Ty) const override;
597 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
599 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
601 unsigned Intrinsic) const override;
603 /// getOptimalMemOpType - Returns the target specific optimal type for load
604 /// and store operations as a result of memset, memcpy, and memmove
605 /// lowering. If DstAlign is zero that means it's safe to destination
606 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
607 /// means there isn't a need to check it against alignment requirement,
608 /// probably because the source does not need to be loaded. If 'IsMemset' is
609 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
610 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
611 /// source is constant so it does not need to be loaded.
612 /// It returns EVT::Other if the type should be determined using generic
613 /// target-independent logic.
615 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
616 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
617 MachineFunction &MF) const override;
619 /// Is unaligned memory access allowed for the given type, and is it fast
620 /// relative to software emulation.
621 bool allowsMisalignedMemoryAccesses(EVT VT,
624 bool *Fast = nullptr) const override;
626 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
627 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
628 /// expanded to FMAs when this method returns true, otherwise fmuladd is
629 /// expanded to fmul + fadd.
630 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
632 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
634 // Should we expand the build vector with shuffles?
636 shouldExpandBuildVectorWithShuffles(EVT VT,
637 unsigned DefinedValues) const override;
639 /// createFastISel - This method returns a target-specific FastISel object,
640 /// or null if the target does not support "fast" instruction selection.
641 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
642 const TargetLibraryInfo *LibInfo) const override;
644 /// \brief Returns true if an argument of type Ty needs to be passed in a
645 /// contiguous block of registers in calling convention CallConv.
646 bool functionArgumentNeedsConsecutiveRegisters(
647 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
648 // We support any array type as "consecutive" block in the parameter
649 // save area. The element type defines the alignment requirement and
650 // whether the argument should go in GPRs, FPRs, or VRs if available.
652 // Note that clang uses this capability both to implement the ELFv2
653 // homogeneous float/vector aggregate ABI, and to avoid having to use
654 // "byval" when passing aggregates that might fully fit in registers.
655 return Ty->isArrayTy();
660 struct ReuseLoadInfo {
664 MachinePointerInfo MPI;
668 const MDNode *Ranges;
670 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {}
673 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
675 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
676 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
677 SelectionDAG &DAG) const;
679 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
680 SelectionDAG &DAG, SDLoc dl) const;
681 SDValue LowerFP_TO_INTDirectMove(SDValue Op, SelectionDAG &DAG,
683 SDValue LowerINT_TO_FPDirectMove(SDValue Op, SelectionDAG &DAG,
686 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
687 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
690 IsEligibleForTailCallOptimization(SDValue Callee,
691 CallingConv::ID CalleeCC,
693 const SmallVectorImpl<ISD::InputArg> &Ins,
694 SelectionDAG& DAG) const;
696 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
704 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
705 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
706 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
707 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
708 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
709 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
710 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
711 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
712 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
713 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
714 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
715 const PPCSubtarget &Subtarget) const;
716 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
717 const PPCSubtarget &Subtarget) const;
718 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
719 const PPCSubtarget &Subtarget) const;
720 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
721 const PPCSubtarget &Subtarget) const;
722 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
723 const PPCSubtarget &Subtarget) const;
724 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
725 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
726 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
727 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
728 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
729 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
730 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
731 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
732 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
733 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
734 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
735 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
736 SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
737 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
738 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
739 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
740 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
742 SDValue LowerVectorLoad(SDValue Op, SelectionDAG &DAG) const;
743 SDValue LowerVectorStore(SDValue Op, SelectionDAG &DAG) const;
745 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
746 CallingConv::ID CallConv, bool isVarArg,
747 const SmallVectorImpl<ISD::InputArg> &Ins,
748 SDLoc dl, SelectionDAG &DAG,
749 SmallVectorImpl<SDValue> &InVals) const;
750 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
751 bool isVarArg, bool IsPatchPoint, bool hasNest,
753 SmallVector<std::pair<unsigned, SDValue>, 8>
755 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
757 int SPDiff, unsigned NumBytes,
758 const SmallVectorImpl<ISD::InputArg> &Ins,
759 SmallVectorImpl<SDValue> &InVals,
760 ImmutableCallSite *CS) const;
763 LowerFormalArguments(SDValue Chain,
764 CallingConv::ID CallConv, bool isVarArg,
765 const SmallVectorImpl<ISD::InputArg> &Ins,
766 SDLoc dl, SelectionDAG &DAG,
767 SmallVectorImpl<SDValue> &InVals) const override;
770 LowerCall(TargetLowering::CallLoweringInfo &CLI,
771 SmallVectorImpl<SDValue> &InVals) const override;
774 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
776 const SmallVectorImpl<ISD::OutputArg> &Outs,
777 LLVMContext &Context) const override;
780 LowerReturn(SDValue Chain,
781 CallingConv::ID CallConv, bool isVarArg,
782 const SmallVectorImpl<ISD::OutputArg> &Outs,
783 const SmallVectorImpl<SDValue> &OutVals,
784 SDLoc dl, SelectionDAG &DAG) const override;
787 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
788 SDValue ArgVal, SDLoc dl) const;
791 LowerFormalArguments_Darwin(SDValue Chain,
792 CallingConv::ID CallConv, bool isVarArg,
793 const SmallVectorImpl<ISD::InputArg> &Ins,
794 SDLoc dl, SelectionDAG &DAG,
795 SmallVectorImpl<SDValue> &InVals) const;
797 LowerFormalArguments_64SVR4(SDValue Chain,
798 CallingConv::ID CallConv, bool isVarArg,
799 const SmallVectorImpl<ISD::InputArg> &Ins,
800 SDLoc dl, SelectionDAG &DAG,
801 SmallVectorImpl<SDValue> &InVals) const;
803 LowerFormalArguments_32SVR4(SDValue Chain,
804 CallingConv::ID CallConv, bool isVarArg,
805 const SmallVectorImpl<ISD::InputArg> &Ins,
806 SDLoc dl, SelectionDAG &DAG,
807 SmallVectorImpl<SDValue> &InVals) const;
810 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
811 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
812 SelectionDAG &DAG, SDLoc dl) const;
815 LowerCall_Darwin(SDValue Chain, SDValue Callee,
816 CallingConv::ID CallConv,
817 bool isVarArg, bool isTailCall, bool IsPatchPoint,
818 const SmallVectorImpl<ISD::OutputArg> &Outs,
819 const SmallVectorImpl<SDValue> &OutVals,
820 const SmallVectorImpl<ISD::InputArg> &Ins,
821 SDLoc dl, SelectionDAG &DAG,
822 SmallVectorImpl<SDValue> &InVals,
823 ImmutableCallSite *CS) const;
825 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
826 CallingConv::ID CallConv,
827 bool isVarArg, bool isTailCall, bool IsPatchPoint,
828 const SmallVectorImpl<ISD::OutputArg> &Outs,
829 const SmallVectorImpl<SDValue> &OutVals,
830 const SmallVectorImpl<ISD::InputArg> &Ins,
831 SDLoc dl, SelectionDAG &DAG,
832 SmallVectorImpl<SDValue> &InVals,
833 ImmutableCallSite *CS) const;
835 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
836 bool isVarArg, bool isTailCall, bool IsPatchPoint,
837 const SmallVectorImpl<ISD::OutputArg> &Outs,
838 const SmallVectorImpl<SDValue> &OutVals,
839 const SmallVectorImpl<ISD::InputArg> &Ins,
840 SDLoc dl, SelectionDAG &DAG,
841 SmallVectorImpl<SDValue> &InVals,
842 ImmutableCallSite *CS) const;
844 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
845 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
847 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
848 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
849 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
851 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
852 unsigned &RefinementSteps,
853 bool &UseOneConstNR) const override;
854 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
855 unsigned &RefinementSteps) const override;
856 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
858 CCAssignFn *useFastISelCCs(unsigned Flag) const;
862 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
863 const TargetLibraryInfo *LibInfo);
866 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
867 CCValAssign::LocInfo &LocInfo,
868 ISD::ArgFlagsTy &ArgFlags,
871 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
873 CCValAssign::LocInfo &LocInfo,
874 ISD::ArgFlagsTy &ArgFlags,
877 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
879 CCValAssign::LocInfo &LocInfo,
880 ISD::ArgFlagsTy &ArgFlags,
884 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H