1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to,
45 /// then a SRCVALUE for the address.
48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
49 // three v4f32 operands and producing a v4f32 result.
52 /// VPERM - The PPC VPERM Instruction.
56 /// Hi/Lo - These represent the high and low 16-bit parts of a global
57 /// address respectively. These nodes have two operands, the first of
58 /// which must be a TargetGlobalAddress, and the second of which must be a
59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
60 /// though these are usually folded into other nodes.
65 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
66 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
67 /// compute an allocation on the stack.
70 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
71 /// at function entry, used for PIC code.
74 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
75 /// shift amounts. These nodes are generated by the multi-precision shift
79 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
83 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
86 /// CALL - A direct function call.
87 CALL_Darwin, CALL_SVR4,
89 /// NOP - Special NOP which follows 64-bit SVR4 calls.
92 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
93 /// MTCTR instruction.
96 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
97 /// BCTRL instruction.
98 BCTRL_Darwin, BCTRL_SVR4,
100 /// Return with a flag operand, matched by 'blr'
103 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
104 /// This copies the bits corresponding to the specified CRREG into the
105 /// resultant GPR. Bits corresponding to other CR regs are undefined.
108 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
109 /// instructions. For lack of better number, we use the opcode number
110 /// encoding for the OPC field to identify the compare. For example, 838
114 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
115 /// altivec VCMP*o instructions. For lack of better number, we use the
116 /// opcode number encoding for the OPC field to identify the compare. For
117 /// example, 838 is VCMPGTSH.
120 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
121 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
122 /// condition register to branch on, OPC is the branch opcode to use (e.g.
123 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
124 /// an optional input flag argument.
127 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a
128 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
129 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
133 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a
134 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
135 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
139 // The following 5 instructions are used only as part of the
140 // long double-to-int conversion sequence.
142 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
146 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
149 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
152 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
153 /// rounding towards zero. It has flags added so it won't move past the
154 /// FPSCR-setting instructions.
157 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
160 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
161 /// reserve indexed. This is used to implement atomic operations.
164 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
165 /// indexed. This is used to implement atomic operations.
168 /// TC_RETURN - A tail call return.
170 /// operand #1 callee (register or absolute)
171 /// operand #2 stack adjustment
172 /// operand #3 optional in flag
177 /// Define some predicates that are used for node matching.
179 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
180 /// VPKUHUM instruction.
181 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
183 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
184 /// VPKUWUM instruction.
185 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
187 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
188 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
189 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
192 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
193 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
194 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
197 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
198 /// amount, otherwise return -1.
199 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
201 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
202 /// specifies a splat of a single element that is suitable for input to
203 /// VSPLTB/VSPLTH/VSPLTW.
204 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
206 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
208 bool isAllNegativeZeroVector(SDNode *N);
210 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
211 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
212 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
214 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
215 /// formed by using a vspltis[bhw] instruction of the specified element
216 /// size, return the constant being splatted. The ByteSize field indicates
217 /// the number of bytes of each element [124] -> [bhw].
218 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
221 class PPCTargetLowering : public TargetLowering {
222 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
223 int VarArgsStackOffset; // StackOffset for start of stack
225 unsigned VarArgsNumGPR; // Index of the first unused integer
226 // register for parameter passing.
227 unsigned VarArgsNumFPR; // Index of the first unused double
228 // register for parameter passing.
229 const PPCSubtarget &PPCSubTarget;
231 explicit PPCTargetLowering(PPCTargetMachine &TM);
233 /// getTargetNodeName() - This method returns the name of a target specific
235 virtual const char *getTargetNodeName(unsigned Opcode) const;
237 /// getSetCCResultType - Return the ISD::SETCC ValueType
238 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
240 /// getPreIndexedAddressParts - returns true by value, base pointer and
241 /// offset pointer and addressing mode by reference if the node's address
242 /// can be legally represented as pre-indexed load / store address.
243 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
245 ISD::MemIndexedMode &AM,
246 SelectionDAG &DAG) const;
248 /// SelectAddressRegReg - Given the specified addressed, check to see if it
249 /// can be represented as an indexed [r+r] operation. Returns false if it
250 /// can be more efficiently represented with [r+imm].
251 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
252 SelectionDAG &DAG) const;
254 /// SelectAddressRegImm - Returns true if the address N can be represented
255 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
256 /// is not better represented as reg+reg.
257 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
258 SelectionDAG &DAG) const;
260 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
261 /// represented as an indexed [r+r] operation.
262 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
263 SelectionDAG &DAG) const;
265 /// SelectAddressRegImmShift - Returns true if the address N can be
266 /// represented by a base register plus a signed 14-bit displacement
267 /// [r+imm*4]. Suitable for use by STD and friends.
268 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
269 SelectionDAG &DAG) const;
272 /// LowerOperation - Provide custom lowering hooks for some operations.
274 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
276 /// ReplaceNodeResults - Replace the results of node with an illegal result
277 /// type with new values built out of custom code.
279 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
282 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
284 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
288 const SelectionDAG &DAG,
289 unsigned Depth = 0) const;
291 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
292 MachineBasicBlock *MBB) const;
293 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
294 MachineBasicBlock *MBB, bool is64Bit,
295 unsigned BinOpcode) const;
296 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
297 MachineBasicBlock *MBB,
298 bool is8bit, unsigned Opcode) const;
300 ConstraintType getConstraintType(const std::string &Constraint) const;
301 std::pair<unsigned, const TargetRegisterClass*>
302 getRegForInlineAsmConstraint(const std::string &Constraint,
305 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
306 /// function arguments in the caller parameter area. This is the actual
307 /// alignment, not its logarithm.
308 unsigned getByValTypeAlignment(const Type *Ty) const;
310 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
311 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
312 /// true it means one of the asm constraint of the inline asm instruction
313 /// being processed is 'm'.
314 virtual void LowerAsmOperandForConstraint(SDValue Op,
315 char ConstraintLetter,
317 std::vector<SDValue> &Ops,
318 SelectionDAG &DAG) const;
320 /// isLegalAddressingMode - Return true if the addressing mode represented
321 /// by AM is legal for this target, for a load/store of the specified type.
322 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
324 /// isLegalAddressImmediate - Return true if the integer value can be used
325 /// as the offset of the target addressing mode for load / store of the
327 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
329 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
330 /// the offset of the target addressing mode.
331 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
334 IsEligibleForTailCallOptimization(SDValue Callee,
337 const SmallVectorImpl<ISD::InputArg> &Ins,
338 SelectionDAG& DAG) const;
340 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
342 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
343 bool isSrcConst, bool isSrcStr,
344 SelectionDAG &DAG) const;
346 /// getFunctionAlignment - Return the Log2 alignment of this function.
347 virtual unsigned getFunctionAlignment(const Function *F) const;
349 /// getPreferredLSDADataFormat - Return the preferred exception handling data
350 /// format for the LSDA.
351 virtual unsigned getPreferredLSDADataFormat() const;
353 /// getPreferredFDEDataFormat - Return the preferred exception handling data
354 /// format for the FDE.
355 virtual unsigned getPreferredFDEDataFormat() const;
358 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
359 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
361 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
369 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
370 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
371 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
372 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
373 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
374 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
375 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
376 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
377 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
378 int VarArgsFrameIndex, int VarArgsStackOffset,
379 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
380 const PPCSubtarget &Subtarget);
381 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
382 int VarArgsStackOffset, unsigned VarArgsNumGPR,
383 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
384 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
385 const PPCSubtarget &Subtarget);
386 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
387 const PPCSubtarget &Subtarget);
388 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
389 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
390 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
391 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
392 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
393 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
394 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
395 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
396 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
397 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
398 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
399 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
401 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
402 unsigned CallConv, bool isVarArg,
403 const SmallVectorImpl<ISD::InputArg> &Ins,
404 DebugLoc dl, SelectionDAG &DAG,
405 SmallVectorImpl<SDValue> &InVals);
406 SDValue FinishCall(unsigned CallConv, DebugLoc dl, bool isTailCall,
409 SmallVector<std::pair<unsigned, SDValue>, 8>
411 SDValue InFlag, SDValue Chain,
413 int SPDiff, unsigned NumBytes,
414 const SmallVectorImpl<ISD::InputArg> &Ins,
415 SmallVectorImpl<SDValue> &InVals);
418 LowerFormalArguments(SDValue Chain,
419 unsigned CallConv, bool isVarArg,
420 const SmallVectorImpl<ISD::InputArg> &Ins,
421 DebugLoc dl, SelectionDAG &DAG,
422 SmallVectorImpl<SDValue> &InVals);
425 LowerCall(SDValue Chain, SDValue Callee,
426 unsigned CallConv, bool isVarArg, bool isTailCall,
427 const SmallVectorImpl<ISD::OutputArg> &Outs,
428 const SmallVectorImpl<ISD::InputArg> &Ins,
429 DebugLoc dl, SelectionDAG &DAG,
430 SmallVectorImpl<SDValue> &InVals);
433 LowerReturn(SDValue Chain,
434 unsigned CallConv, bool isVarArg,
435 const SmallVectorImpl<ISD::OutputArg> &Outs,
436 DebugLoc dl, SelectionDAG &DAG);
439 LowerFormalArguments_Darwin(SDValue Chain,
440 unsigned CallConv, bool isVarArg,
441 const SmallVectorImpl<ISD::InputArg> &Ins,
442 DebugLoc dl, SelectionDAG &DAG,
443 SmallVectorImpl<SDValue> &InVals);
445 LowerFormalArguments_SVR4(SDValue Chain,
446 unsigned CallConv, bool isVarArg,
447 const SmallVectorImpl<ISD::InputArg> &Ins,
448 DebugLoc dl, SelectionDAG &DAG,
449 SmallVectorImpl<SDValue> &InVals);
452 LowerCall_Darwin(SDValue Chain, SDValue Callee,
453 unsigned CallConv, bool isVarArg, bool isTailCall,
454 const SmallVectorImpl<ISD::OutputArg> &Outs,
455 const SmallVectorImpl<ISD::InputArg> &Ins,
456 DebugLoc dl, SelectionDAG &DAG,
457 SmallVectorImpl<SDValue> &InVals);
459 LowerCall_SVR4(SDValue Chain, SDValue Callee,
460 unsigned CallConv, bool isVarArg, bool isTailCall,
461 const SmallVectorImpl<ISD::OutputArg> &Outs,
462 const SmallVectorImpl<ISD::InputArg> &Ins,
463 DebugLoc dl, SelectionDAG &DAG,
464 SmallVectorImpl<SDValue> &InVals);
468 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H