1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
76 /// The following two target-specific nodes are used for calls through
77 /// function pointers in the 64-bit SVR4 ABI.
79 /// Like a regular LOAD but additionally taking/producing a flag.
82 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded
86 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
87 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
88 /// compute an allocation on the stack.
91 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
92 /// at function entry, used for PIC code.
95 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
96 /// shift amounts. These nodes are generated by the multi-precision shift
100 /// The combination of sra[wd]i and addze used to implemented signed
101 /// integer division by a power of 2. The first operand is the dividend,
102 /// and the second is the constant shift amount (representing the
106 /// CALL - A direct function call.
107 /// CALL_NOP is a call with the special NOP which follows 64-bit
111 /// CALL_TLS and CALL_NOP_TLS - Versions of CALL and CALL_NOP used
112 /// to access TLS variables.
113 CALL_TLS, CALL_NOP_TLS,
115 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
116 /// MTCTR instruction.
119 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
120 /// BCTRL instruction.
123 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
124 /// instruction and the TOC reload required on SVR4 PPC64.
127 /// Return with a flag operand, matched by 'blr'
130 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
131 /// This copies the bits corresponding to the specified CRREG into the
132 /// resultant GPR. Bits corresponding to other CR regs are undefined.
135 // FIXME: Remove these once the ANDI glue bug is fixed:
136 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
137 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
138 /// implement truncation of i32 or i64 to i1.
139 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
141 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
142 // target (returns (Lo, Hi)). It takes a chain operand.
145 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
148 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
151 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
152 /// instructions. For lack of better number, we use the opcode number
153 /// encoding for the OPC field to identify the compare. For example, 838
157 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
158 /// altivec VCMP*o instructions. For lack of better number, we use the
159 /// opcode number encoding for the OPC field to identify the compare. For
160 /// example, 838 is VCMPGTSH.
163 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
164 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
165 /// condition register to branch on, OPC is the branch opcode to use (e.g.
166 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
167 /// an optional input flag argument.
170 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
174 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
175 /// towards zero. Used only as part of the long double-to-int
176 /// conversion sequence.
179 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
182 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
183 /// reserve indexed. This is used to implement atomic operations.
186 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
187 /// indexed. This is used to implement atomic operations.
190 /// TC_RETURN - A tail call return.
192 /// operand #1 callee (register or absolute)
193 /// operand #2 stack adjustment
194 /// operand #3 optional in flag
197 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
201 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
205 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
206 /// local dynamic TLS on PPC32.
209 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
210 /// TLS model, produces an ADDIS8 instruction that adds the GOT
211 /// base to sym\@got\@tprel\@ha.
214 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
215 /// TLS model, produces a LD instruction with base register G8RReg
216 /// and offset sym\@got\@tprel\@l. This completes the addition that
217 /// finds the offset of "sym" relative to the thread pointer.
220 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
221 /// model, produces an ADD instruction that adds the contents of
222 /// G8RReg to the thread pointer. Symbol contains a relocation
223 /// sym\@tls which is to be replaced by the thread pointer and
224 /// identifies to the linker that the instruction is part of a
228 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
229 /// model, produces an ADDIS8 instruction that adds the GOT base
230 /// register to sym\@got\@tlsgd\@ha.
233 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
234 /// model, produces an ADDI8 instruction that adds G8RReg to
235 /// sym\@got\@tlsgd\@l.
238 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
239 /// model, produces an ADDIS8 instruction that adds the GOT base
240 /// register to sym\@got\@tlsld\@ha.
243 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
244 /// model, produces an ADDI8 instruction that adds G8RReg to
245 /// sym\@got\@tlsld\@l.
248 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
249 /// local-dynamic TLS model, produces an ADDIS8 instruction
250 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
251 /// to tie this in place following a copy to %X3 from the result
252 /// of a GET_TLSLD_ADDR.
255 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
256 /// model, produces an ADDI8 instruction that adds G8RReg to
257 /// sym\@got\@dtprel\@l.
260 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
261 /// during instruction selection to optimize a BUILD_VECTOR into
262 /// operations on splats. This is necessary to avoid losing these
263 /// optimizations due to constant folding.
266 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
267 /// operand identifies the operating system entry point.
270 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
271 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
272 /// or stxvd2x instruction. The chain is necessary because the
273 /// sequence replaces a load and needs to provide the same number
277 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
278 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
279 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
281 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
283 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
284 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
285 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
289 /// STFIWX - The STFIWX instruction. The first operand is an input token
290 /// chain, then an f64 value to store, then an address to store it to.
293 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
294 /// load which sign-extends from a 32-bit integer value into the
295 /// destination 64-bit register.
298 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
299 /// load which zero-extends from a 32-bit integer value into the
300 /// destination 64-bit register.
303 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
304 /// produces an ADDIS8 instruction that adds the TOC base register to
308 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
309 /// produces a LD instruction with base register G8RReg and offset
310 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
313 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
314 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
315 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
318 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
319 /// Maps directly to an lxvd2x instruction that will be followed by
323 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
324 /// Maps directly to an stxvd2x instruction that will be preceded by
330 /// Define some predicates that are used for node matching.
332 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
333 /// VPKUHUM instruction.
334 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
337 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
338 /// VPKUWUM instruction.
339 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
342 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
343 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
344 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
345 unsigned ShuffleKind, SelectionDAG &DAG);
347 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
348 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
349 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
350 unsigned ShuffleKind, SelectionDAG &DAG);
352 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
353 /// shift amount, otherwise return -1.
354 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
357 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
358 /// specifies a splat of a single element that is suitable for input to
359 /// VSPLTB/VSPLTH/VSPLTW.
360 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
362 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
364 bool isAllNegativeZeroVector(SDNode *N);
366 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
367 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
368 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
370 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
371 /// formed by using a vspltis[bhw] instruction of the specified element
372 /// size, return the constant being splatted. The ByteSize field indicates
373 /// the number of bytes of each element [124] -> [bhw].
374 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
378 class PPCTargetLowering : public TargetLowering {
379 const PPCSubtarget &Subtarget;
382 explicit PPCTargetLowering(const PPCTargetMachine &TM);
384 /// getTargetNodeName() - This method returns the name of a target specific
386 const char *getTargetNodeName(unsigned Opcode) const override;
388 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
390 /// getSetCCResultType - Return the ISD::SETCC ValueType
391 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
393 /// Return true if target always beneficiates from combining into FMA for a
394 /// given value type. This must typically return false on targets where FMA
395 /// takes more cycles to execute than FADD.
396 bool enableAggressiveFMAFusion(EVT VT) const override;
398 /// getPreIndexedAddressParts - returns true by value, base pointer and
399 /// offset pointer and addressing mode by reference if the node's address
400 /// can be legally represented as pre-indexed load / store address.
401 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
403 ISD::MemIndexedMode &AM,
404 SelectionDAG &DAG) const override;
406 /// SelectAddressRegReg - Given the specified addressed, check to see if it
407 /// can be represented as an indexed [r+r] operation. Returns false if it
408 /// can be more efficiently represented with [r+imm].
409 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
410 SelectionDAG &DAG) const;
412 /// SelectAddressRegImm - Returns true if the address N can be represented
413 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
414 /// is not better represented as reg+reg. If Aligned is true, only accept
415 /// displacements suitable for STD and friends, i.e. multiples of 4.
416 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
417 SelectionDAG &DAG, bool Aligned) const;
419 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
420 /// represented as an indexed [r+r] operation.
421 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
422 SelectionDAG &DAG) const;
424 Sched::Preference getSchedulingPreference(SDNode *N) const override;
426 /// LowerOperation - Provide custom lowering hooks for some operations.
428 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
430 /// ReplaceNodeResults - Replace the results of node with an illegal result
431 /// type with new values built out of custom code.
433 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
434 SelectionDAG &DAG) const override;
436 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
437 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
439 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
441 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
442 std::vector<SDNode *> *Created) const override;
444 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
446 void computeKnownBitsForTargetNode(const SDValue Op,
449 const SelectionDAG &DAG,
450 unsigned Depth = 0) const override;
452 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
453 bool IsStore, bool IsLoad) const override;
454 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
455 bool IsStore, bool IsLoad) const override;
458 EmitInstrWithCustomInserter(MachineInstr *MI,
459 MachineBasicBlock *MBB) const override;
460 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
461 MachineBasicBlock *MBB, bool is64Bit,
462 unsigned BinOpcode) const;
463 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
464 MachineBasicBlock *MBB,
465 bool is8bit, unsigned Opcode) const;
467 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
468 MachineBasicBlock *MBB) const;
470 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
471 MachineBasicBlock *MBB) const;
474 getConstraintType(const std::string &Constraint) const override;
476 /// Examine constraint string and operand type and determine a weight value.
477 /// The operand object must already have been set up with the operand type.
478 ConstraintWeight getSingleConstraintMatchWeight(
479 AsmOperandInfo &info, const char *constraint) const override;
481 std::pair<unsigned, const TargetRegisterClass*>
482 getRegForInlineAsmConstraint(const std::string &Constraint,
483 MVT VT) const override;
485 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
486 /// function arguments in the caller parameter area. This is the actual
487 /// alignment, not its logarithm.
488 unsigned getByValTypeAlignment(Type *Ty) const override;
490 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
491 /// vector. If it is invalid, don't add anything to Ops.
492 void LowerAsmOperandForConstraint(SDValue Op,
493 std::string &Constraint,
494 std::vector<SDValue> &Ops,
495 SelectionDAG &DAG) const override;
497 /// isLegalAddressingMode - Return true if the addressing mode represented
498 /// by AM is legal for this target, for a load/store of the specified type.
499 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
501 /// isLegalICmpImmediate - Return true if the specified immediate is legal
502 /// icmp immediate, that is the target has icmp instructions which can
503 /// compare a register against the immediate without having to materialize
504 /// the immediate into a register.
505 bool isLegalICmpImmediate(int64_t Imm) const override;
507 /// isLegalAddImmediate - Return true if the specified immediate is legal
508 /// add immediate, that is the target has add instructions which can
509 /// add a register and the immediate without having to materialize
510 /// the immediate into a register.
511 bool isLegalAddImmediate(int64_t Imm) const override;
513 /// isTruncateFree - Return true if it's free to truncate a value of
514 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
515 /// register X1 to i32 by referencing its sub-register R1.
516 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
517 bool isTruncateFree(EVT VT1, EVT VT2) const override;
519 /// \brief Returns true if it is beneficial to convert a load of a constant
520 /// to just the constant itself.
521 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
522 Type *Ty) const override;
524 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
526 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
528 unsigned Intrinsic) const override;
530 /// getOptimalMemOpType - Returns the target specific optimal type for load
531 /// and store operations as a result of memset, memcpy, and memmove
532 /// lowering. If DstAlign is zero that means it's safe to destination
533 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
534 /// means there isn't a need to check it against alignment requirement,
535 /// probably because the source does not need to be loaded. If 'IsMemset' is
536 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
537 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
538 /// source is constant so it does not need to be loaded.
539 /// It returns EVT::Other if the type should be determined using generic
540 /// target-independent logic.
542 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
543 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
544 MachineFunction &MF) const override;
546 /// Is unaligned memory access allowed for the given type, and is it fast
547 /// relative to software emulation.
548 bool allowsMisalignedMemoryAccesses(EVT VT,
551 bool *Fast = nullptr) const override;
553 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
554 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
555 /// expanded to FMAs when this method returns true, otherwise fmuladd is
556 /// expanded to fmul + fadd.
557 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
559 // Should we expand the build vector with shuffles?
561 shouldExpandBuildVectorWithShuffles(EVT VT,
562 unsigned DefinedValues) const override;
564 /// createFastISel - This method returns a target-specific FastISel object,
565 /// or null if the target does not support "fast" instruction selection.
566 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
567 const TargetLibraryInfo *LibInfo) const override;
569 /// \brief Returns true if an argument of type Ty needs to be passed in a
570 /// contiguous block of registers in calling convention CallConv.
571 bool functionArgumentNeedsConsecutiveRegisters(
572 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
573 // We support any array type as "consecutive" block in the parameter
574 // save area. The element type defines the alignment requirement and
575 // whether the argument should go in GPRs, FPRs, or VRs if available.
577 // Note that clang uses this capability both to implement the ELFv2
578 // homogeneous float/vector aggregate ABI, and to avoid having to use
579 // "byval" when passing aggregates that might fully fit in registers.
580 return Ty->isArrayTy();
584 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
585 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
588 IsEligibleForTailCallOptimization(SDValue Callee,
589 CallingConv::ID CalleeCC,
591 const SmallVectorImpl<ISD::InputArg> &Ins,
592 SelectionDAG& DAG) const;
594 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
602 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
603 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
604 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
605 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
606 std::pair<SDValue,SDValue> lowerTLSCall(SDValue Op, SDLoc dl,
607 SelectionDAG &DAG) const;
608 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
609 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
610 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
611 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
612 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
613 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
614 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
615 const PPCSubtarget &Subtarget) const;
616 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
617 const PPCSubtarget &Subtarget) const;
618 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
619 const PPCSubtarget &Subtarget) const;
620 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
621 const PPCSubtarget &Subtarget) const;
622 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
623 const PPCSubtarget &Subtarget) const;
624 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
625 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
626 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
627 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
628 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
629 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
630 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
631 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
632 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
633 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
634 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
635 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
636 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
637 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
638 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
639 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
641 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
642 CallingConv::ID CallConv, bool isVarArg,
643 const SmallVectorImpl<ISD::InputArg> &Ins,
644 SDLoc dl, SelectionDAG &DAG,
645 SmallVectorImpl<SDValue> &InVals) const;
646 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
649 SmallVector<std::pair<unsigned, SDValue>, 8>
651 SDValue InFlag, SDValue Chain,
653 int SPDiff, unsigned NumBytes,
654 const SmallVectorImpl<ISD::InputArg> &Ins,
655 SmallVectorImpl<SDValue> &InVals) const;
658 LowerFormalArguments(SDValue Chain,
659 CallingConv::ID CallConv, bool isVarArg,
660 const SmallVectorImpl<ISD::InputArg> &Ins,
661 SDLoc dl, SelectionDAG &DAG,
662 SmallVectorImpl<SDValue> &InVals) const override;
665 LowerCall(TargetLowering::CallLoweringInfo &CLI,
666 SmallVectorImpl<SDValue> &InVals) const override;
669 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
671 const SmallVectorImpl<ISD::OutputArg> &Outs,
672 LLVMContext &Context) const override;
675 LowerReturn(SDValue Chain,
676 CallingConv::ID CallConv, bool isVarArg,
677 const SmallVectorImpl<ISD::OutputArg> &Outs,
678 const SmallVectorImpl<SDValue> &OutVals,
679 SDLoc dl, SelectionDAG &DAG) const override;
682 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
683 SDValue ArgVal, SDLoc dl) const;
686 LowerFormalArguments_Darwin(SDValue Chain,
687 CallingConv::ID CallConv, bool isVarArg,
688 const SmallVectorImpl<ISD::InputArg> &Ins,
689 SDLoc dl, SelectionDAG &DAG,
690 SmallVectorImpl<SDValue> &InVals) const;
692 LowerFormalArguments_64SVR4(SDValue Chain,
693 CallingConv::ID CallConv, bool isVarArg,
694 const SmallVectorImpl<ISD::InputArg> &Ins,
695 SDLoc dl, SelectionDAG &DAG,
696 SmallVectorImpl<SDValue> &InVals) const;
698 LowerFormalArguments_32SVR4(SDValue Chain,
699 CallingConv::ID CallConv, bool isVarArg,
700 const SmallVectorImpl<ISD::InputArg> &Ins,
701 SDLoc dl, SelectionDAG &DAG,
702 SmallVectorImpl<SDValue> &InVals) const;
705 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
706 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
707 SelectionDAG &DAG, SDLoc dl) const;
710 LowerCall_Darwin(SDValue Chain, SDValue Callee,
711 CallingConv::ID CallConv,
712 bool isVarArg, bool isTailCall,
713 const SmallVectorImpl<ISD::OutputArg> &Outs,
714 const SmallVectorImpl<SDValue> &OutVals,
715 const SmallVectorImpl<ISD::InputArg> &Ins,
716 SDLoc dl, SelectionDAG &DAG,
717 SmallVectorImpl<SDValue> &InVals) const;
719 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
720 CallingConv::ID CallConv,
721 bool isVarArg, bool isTailCall,
722 const SmallVectorImpl<ISD::OutputArg> &Outs,
723 const SmallVectorImpl<SDValue> &OutVals,
724 const SmallVectorImpl<ISD::InputArg> &Ins,
725 SDLoc dl, SelectionDAG &DAG,
726 SmallVectorImpl<SDValue> &InVals) const;
728 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
729 bool isVarArg, bool isTailCall,
730 const SmallVectorImpl<ISD::OutputArg> &Outs,
731 const SmallVectorImpl<SDValue> &OutVals,
732 const SmallVectorImpl<ISD::InputArg> &Ins,
733 SDLoc dl, SelectionDAG &DAG,
734 SmallVectorImpl<SDValue> &InVals) const;
736 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
737 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
739 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
740 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
742 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
743 unsigned &RefinementSteps,
744 bool &UseOneConstNR) const override;
745 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
746 unsigned &RefinementSteps) const override;
747 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
749 CCAssignFn *useFastISelCCs(unsigned Flag) const;
753 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
754 const TargetLibraryInfo *LibInfo);
757 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
758 CCValAssign::LocInfo &LocInfo,
759 ISD::ArgFlagsTy &ArgFlags,
762 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
764 CCValAssign::LocInfo &LocInfo,
765 ISD::ArgFlagsTy &ArgFlags,
768 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
770 CCValAssign::LocInfo &LocInfo,
771 ISD::ArgFlagsTy &ArgFlags,
775 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H