1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builting ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to,
45 /// then a SRCVALUE for the address.
48 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
49 // three v4f32 operands and producing a v4f32 result.
52 /// VPERM - The PPC VPERM Instruction.
56 /// Hi/Lo - These represent the high and low 16-bit parts of a global
57 /// address respectively. These nodes have two operands, the first of
58 /// which must be a TargetGlobalAddress, and the second of which must be a
59 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
60 /// though these are usually folded into other nodes.
63 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
64 /// at function entry, used for PIC code.
67 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
68 /// shift amounts. These nodes are generated by the multi-precision shift
72 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
76 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
79 /// CALL - A direct function call.
82 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
83 /// MTCTR instruction.
86 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
87 /// BCTRL instruction.
90 /// Return with a flag operand, matched by 'blr'
93 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
94 /// This copies the bits corresponding to the specified CRREG into the
95 /// resultant GPR. Bits corresponding to other CR regs are undefined.
98 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
99 /// instructions. For lack of better number, we use the opcode number
100 /// encoding for the OPC field to identify the compare. For example, 838
104 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
105 /// altivec VCMP*o instructions. For lack of better number, we use the
106 /// opcode number encoding for the OPC field to identify the compare. For
107 /// example, 838 is VCMPGTSH.
110 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
111 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
112 /// condition register to branch on, OPC is the branch opcode to use (e.g.
113 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
114 /// an optional input flag argument.
117 /// CHAIN = STBRX CHAIN, GPRC, Ptr, SRCVALUE, Type - This is a
118 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
119 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
123 /// GPRC, CHAIN = LBRX CHAIN, Ptr, SRCVALUE, Type - This is a
124 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
125 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
131 /// Define some predicates that are used for node matching.
133 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
134 /// VPKUHUM instruction.
135 bool isVPKUHUMShuffleMask(SDNode *N, bool isUnary);
137 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
138 /// VPKUWUM instruction.
139 bool isVPKUWUMShuffleMask(SDNode *N, bool isUnary);
141 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
142 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
143 bool isVMRGLShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
145 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
146 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
147 bool isVMRGHShuffleMask(SDNode *N, unsigned UnitSize, bool isUnary);
149 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
150 /// amount, otherwise return -1.
151 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
153 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
154 /// specifies a splat of a single element that is suitable for input to
155 /// VSPLTB/VSPLTH/VSPLTW.
156 bool isSplatShuffleMask(SDNode *N, unsigned EltSize);
158 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
159 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
160 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
162 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
163 /// formed by using a vspltis[bhw] instruction of the specified element
164 /// size, return the constant being splatted. The ByteSize field indicates
165 /// the number of bytes of each element [124] -> [bhw].
166 SDOperand get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
169 class PPCTargetLowering : public TargetLowering {
170 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
171 int ReturnAddrIndex; // FrameIndex for return slot.
172 const PPCSubtarget &PPCSubTarget;
174 PPCTargetLowering(PPCTargetMachine &TM);
176 /// getTargetNodeName() - This method returns the name of a target specific
178 virtual const char *getTargetNodeName(unsigned Opcode) const;
180 /// getPreIndexedAddressParts - returns true by value, base pointer and
181 /// offset pointer and addressing mode by reference if the node's address
182 /// can be legally represented as pre-indexed load / store address.
183 virtual bool getPreIndexedAddressParts(SDNode *N, SDOperand &Base,
185 ISD::MemIndexedMode &AM,
188 /// SelectAddressRegReg - Given the specified addressed, check to see if it
189 /// can be represented as an indexed [r+r] operation. Returns false if it
190 /// can be more efficiently represented with [r+imm].
191 bool SelectAddressRegReg(SDOperand N, SDOperand &Base, SDOperand &Index,
194 /// SelectAddressRegImm - Returns true if the address N can be represented
195 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
196 /// is not better represented as reg+reg.
197 bool SelectAddressRegImm(SDOperand N, SDOperand &Disp, SDOperand &Base,
200 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
201 /// represented as an indexed [r+r] operation.
202 bool SelectAddressRegRegOnly(SDOperand N, SDOperand &Base, SDOperand &Index,
205 /// SelectAddressRegImmShift - Returns true if the address N can be
206 /// represented by a base register plus a signed 14-bit displacement
207 /// [r+imm*4]. Suitable for use by STD and friends.
208 bool SelectAddressRegImmShift(SDOperand N, SDOperand &Disp, SDOperand &Base,
212 /// LowerOperation - Provide custom lowering hooks for some operations.
214 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
216 virtual SDOperand PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
218 virtual void computeMaskedBitsForTargetNode(const SDOperand Op,
222 unsigned Depth = 0) const;
224 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
225 MachineBasicBlock *MBB);
227 ConstraintType getConstraintType(char ConstraintLetter) const;
228 std::pair<unsigned, const TargetRegisterClass*>
229 getRegForInlineAsmConstraint(const std::string &Constraint,
230 MVT::ValueType VT) const;
231 SDOperand isOperandValidForConstraint(SDOperand Op, char ConstraintLetter,
234 /// isLegalAddressImmediate - Return true if the integer value can be used
235 /// as the offset of the target addressing mode.
236 virtual bool isLegalAddressImmediate(int64_t V) const;
237 virtual bool isLegalAddressImmediate(llvm::GlobalValue*) const;
241 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H