1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
64 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
65 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
66 /// compute an allocation on the stack.
69 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
70 /// at function entry, used for PIC code.
73 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
74 /// shift amounts. These nodes are generated by the multi-precision shift
78 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
82 /// CALL - A direct function call.
83 CALL_Darwin, CALL_SVR4,
85 /// NOP - Special NOP which follows 64-bit SVR4 calls.
88 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
89 /// MTCTR instruction.
92 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
93 /// BCTRL instruction.
94 BCTRL_Darwin, BCTRL_SVR4,
96 /// Return with a flag operand, matched by 'blr'
99 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
100 /// This copies the bits corresponding to the specified CRREG into the
101 /// resultant GPR. Bits corresponding to other CR regs are undefined.
104 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
105 /// instructions. For lack of better number, we use the opcode number
106 /// encoding for the OPC field to identify the compare. For example, 838
110 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
111 /// altivec VCMP*o instructions. For lack of better number, we use the
112 /// opcode number encoding for the OPC field to identify the compare. For
113 /// example, 838 is VCMPGTSH.
116 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
117 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
118 /// condition register to branch on, OPC is the branch opcode to use (e.g.
119 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
120 /// an optional input flag argument.
123 // The following 5 instructions are used only as part of the
124 // long double-to-int conversion sequence.
126 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
130 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
133 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
136 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
137 /// rounding towards zero. It has flags added so it won't move past the
138 /// FPSCR-setting instructions.
141 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
144 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
145 /// reserve indexed. This is used to implement atomic operations.
148 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
149 /// indexed. This is used to implement atomic operations.
152 /// TC_RETURN - A tail call return.
154 /// operand #1 callee (register or absolute)
155 /// operand #2 stack adjustment
156 /// operand #3 optional in flag
159 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
160 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
162 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
163 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
164 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
168 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
169 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
170 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
176 /// Define some predicates that are used for node matching.
178 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
179 /// VPKUHUM instruction.
180 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
182 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
183 /// VPKUWUM instruction.
184 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
186 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
187 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
188 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
191 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
192 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
193 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
196 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
197 /// amount, otherwise return -1.
198 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
200 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
201 /// specifies a splat of a single element that is suitable for input to
202 /// VSPLTB/VSPLTH/VSPLTW.
203 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
205 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
207 bool isAllNegativeZeroVector(SDNode *N);
209 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
210 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
211 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
213 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
214 /// formed by using a vspltis[bhw] instruction of the specified element
215 /// size, return the constant being splatted. The ByteSize field indicates
216 /// the number of bytes of each element [124] -> [bhw].
217 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
220 class PPCTargetLowering : public TargetLowering {
221 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
222 int VarArgsStackOffset; // StackOffset for start of stack
224 unsigned VarArgsNumGPR; // Index of the first unused integer
225 // register for parameter passing.
226 unsigned VarArgsNumFPR; // Index of the first unused double
227 // register for parameter passing.
228 const PPCSubtarget &PPCSubTarget;
230 explicit PPCTargetLowering(PPCTargetMachine &TM);
232 /// getTargetNodeName() - This method returns the name of a target specific
234 virtual const char *getTargetNodeName(unsigned Opcode) const;
236 /// getSetCCResultType - Return the ISD::SETCC ValueType
237 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
239 /// getPreIndexedAddressParts - returns true by value, base pointer and
240 /// offset pointer and addressing mode by reference if the node's address
241 /// can be legally represented as pre-indexed load / store address.
242 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
244 ISD::MemIndexedMode &AM,
245 SelectionDAG &DAG) const;
247 /// SelectAddressRegReg - Given the specified addressed, check to see if it
248 /// can be represented as an indexed [r+r] operation. Returns false if it
249 /// can be more efficiently represented with [r+imm].
250 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
251 SelectionDAG &DAG) const;
253 /// SelectAddressRegImm - Returns true if the address N can be represented
254 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
255 /// is not better represented as reg+reg.
256 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
257 SelectionDAG &DAG) const;
259 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
260 /// represented as an indexed [r+r] operation.
261 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
262 SelectionDAG &DAG) const;
264 /// SelectAddressRegImmShift - Returns true if the address N can be
265 /// represented by a base register plus a signed 14-bit displacement
266 /// [r+imm*4]. Suitable for use by STD and friends.
267 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
268 SelectionDAG &DAG) const;
271 /// LowerOperation - Provide custom lowering hooks for some operations.
273 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
275 /// ReplaceNodeResults - Replace the results of node with an illegal result
276 /// type with new values built out of custom code.
278 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
281 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
283 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
287 const SelectionDAG &DAG,
288 unsigned Depth = 0) const;
290 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
291 MachineBasicBlock *MBB,
292 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
293 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
294 MachineBasicBlock *MBB, bool is64Bit,
295 unsigned BinOpcode) const;
296 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
297 MachineBasicBlock *MBB,
298 bool is8bit, unsigned Opcode) const;
300 ConstraintType getConstraintType(const std::string &Constraint) const;
301 std::pair<unsigned, const TargetRegisterClass*>
302 getRegForInlineAsmConstraint(const std::string &Constraint,
305 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
306 /// function arguments in the caller parameter area. This is the actual
307 /// alignment, not its logarithm.
308 unsigned getByValTypeAlignment(const Type *Ty) const;
310 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
311 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
312 /// true it means one of the asm constraint of the inline asm instruction
313 /// being processed is 'm'.
314 virtual void LowerAsmOperandForConstraint(SDValue Op,
315 char ConstraintLetter,
317 std::vector<SDValue> &Ops,
318 SelectionDAG &DAG) const;
320 /// isLegalAddressingMode - Return true if the addressing mode represented
321 /// by AM is legal for this target, for a load/store of the specified type.
322 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
324 /// isLegalAddressImmediate - Return true if the integer value can be used
325 /// as the offset of the target addressing mode for load / store of the
327 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
329 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
330 /// the offset of the target addressing mode.
331 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
334 IsEligibleForTailCallOptimization(SDValue Callee,
335 CallingConv::ID CalleeCC,
337 const SmallVectorImpl<ISD::InputArg> &Ins,
338 SelectionDAG& DAG) const;
340 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
342 virtual EVT getOptimalMemOpType(uint64_t Size, unsigned Align,
343 bool isSrcConst, bool isSrcStr,
344 SelectionDAG &DAG) const;
346 /// getFunctionAlignment - Return the Log2 alignment of this function.
347 virtual unsigned getFunctionAlignment(const Function *F) const;
350 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
351 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
353 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
361 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
362 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
363 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
364 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
365 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
366 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
367 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
368 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
369 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
370 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
371 int VarArgsFrameIndex, int VarArgsStackOffset,
372 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
373 const PPCSubtarget &Subtarget);
374 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
375 int VarArgsStackOffset, unsigned VarArgsNumGPR,
376 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
377 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
378 const PPCSubtarget &Subtarget);
379 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
380 const PPCSubtarget &Subtarget);
381 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
382 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
383 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
384 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
385 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
386 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
387 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
388 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
389 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
390 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
391 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
392 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
394 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
395 CallingConv::ID CallConv, bool isVarArg,
396 const SmallVectorImpl<ISD::InputArg> &Ins,
397 DebugLoc dl, SelectionDAG &DAG,
398 SmallVectorImpl<SDValue> &InVals);
399 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
402 SmallVector<std::pair<unsigned, SDValue>, 8>
404 SDValue InFlag, SDValue Chain,
406 int SPDiff, unsigned NumBytes,
407 const SmallVectorImpl<ISD::InputArg> &Ins,
408 SmallVectorImpl<SDValue> &InVals);
411 LowerFormalArguments(SDValue Chain,
412 CallingConv::ID CallConv, bool isVarArg,
413 const SmallVectorImpl<ISD::InputArg> &Ins,
414 DebugLoc dl, SelectionDAG &DAG,
415 SmallVectorImpl<SDValue> &InVals);
418 LowerCall(SDValue Chain, SDValue Callee,
419 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
420 const SmallVectorImpl<ISD::OutputArg> &Outs,
421 const SmallVectorImpl<ISD::InputArg> &Ins,
422 DebugLoc dl, SelectionDAG &DAG,
423 SmallVectorImpl<SDValue> &InVals);
426 LowerReturn(SDValue Chain,
427 CallingConv::ID CallConv, bool isVarArg,
428 const SmallVectorImpl<ISD::OutputArg> &Outs,
429 DebugLoc dl, SelectionDAG &DAG);
432 LowerFormalArguments_Darwin(SDValue Chain,
433 CallingConv::ID CallConv, bool isVarArg,
434 const SmallVectorImpl<ISD::InputArg> &Ins,
435 DebugLoc dl, SelectionDAG &DAG,
436 SmallVectorImpl<SDValue> &InVals);
438 LowerFormalArguments_SVR4(SDValue Chain,
439 CallingConv::ID CallConv, bool isVarArg,
440 const SmallVectorImpl<ISD::InputArg> &Ins,
441 DebugLoc dl, SelectionDAG &DAG,
442 SmallVectorImpl<SDValue> &InVals);
445 LowerCall_Darwin(SDValue Chain, SDValue Callee,
446 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
447 const SmallVectorImpl<ISD::OutputArg> &Outs,
448 const SmallVectorImpl<ISD::InputArg> &Ins,
449 DebugLoc dl, SelectionDAG &DAG,
450 SmallVectorImpl<SDValue> &InVals);
452 LowerCall_SVR4(SDValue Chain, SDValue Callee,
453 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
454 const SmallVectorImpl<ISD::OutputArg> &Outs,
455 const SmallVectorImpl<ISD::InputArg> &Ins,
456 DebugLoc dl, SelectionDAG &DAG,
457 SmallVectorImpl<SDValue> &InVals);
461 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H