1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "PPCSubtarget.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
64 /// The following three target-specific nodes are used for calls through
65 /// function pointers in the 64-bit SVR4 ABI.
67 /// Restore the TOC from the TOC save area of the current stack frame.
68 /// This is basically a hard coded load instruction which additionally
69 /// takes/produces a flag.
72 /// Like a regular LOAD but additionally taking/producing a flag.
75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76 /// a hard coded load instruction.
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
97 /// CALL - A direct function call.
98 CALL_Darwin, CALL_SVR4,
100 /// NOP - Special NOP which follows 64-bit SVR4 calls.
103 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
104 /// MTCTR instruction.
107 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
108 /// BCTRL instruction.
109 BCTRL_Darwin, BCTRL_SVR4,
111 /// Return with a flag operand, matched by 'blr'
114 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCR/MFOCRF instructions.
115 /// This copies the bits corresponding to the specified CRREG into the
116 /// resultant GPR. Bits corresponding to other CR regs are undefined.
119 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
120 /// instructions. For lack of better number, we use the opcode number
121 /// encoding for the OPC field to identify the compare. For example, 838
125 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
126 /// altivec VCMP*o instructions. For lack of better number, we use the
127 /// opcode number encoding for the OPC field to identify the compare. For
128 /// example, 838 is VCMPGTSH.
131 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
132 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
133 /// condition register to branch on, OPC is the branch opcode to use (e.g.
134 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
135 /// an optional input flag argument.
138 // The following 5 instructions are used only as part of the
139 // long double-to-int conversion sequence.
141 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
145 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
148 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
151 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
152 /// rounding towards zero. It has flags added so it won't move past the
153 /// FPSCR-setting instructions.
156 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
159 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
160 /// reserve indexed. This is used to implement atomic operations.
163 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
164 /// indexed. This is used to implement atomic operations.
167 /// TC_RETURN - A tail call return.
169 /// operand #1 callee (register or absolute)
170 /// operand #2 stack adjustment
171 /// operand #3 optional in flag
174 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
175 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
177 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
178 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
179 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
183 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
184 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
185 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
191 /// Define some predicates that are used for node matching.
193 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
194 /// VPKUHUM instruction.
195 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
197 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
198 /// VPKUWUM instruction.
199 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
201 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
202 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
203 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
206 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
207 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
208 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
211 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
212 /// amount, otherwise return -1.
213 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
215 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
216 /// specifies a splat of a single element that is suitable for input to
217 /// VSPLTB/VSPLTH/VSPLTW.
218 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
220 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
222 bool isAllNegativeZeroVector(SDNode *N);
224 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
225 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
226 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
228 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
229 /// formed by using a vspltis[bhw] instruction of the specified element
230 /// size, return the constant being splatted. The ByteSize field indicates
231 /// the number of bytes of each element [124] -> [bhw].
232 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
235 class PPCTargetLowering : public TargetLowering {
236 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
237 int VarArgsStackOffset; // StackOffset for start of stack
239 unsigned VarArgsNumGPR; // Index of the first unused integer
240 // register for parameter passing.
241 unsigned VarArgsNumFPR; // Index of the first unused double
242 // register for parameter passing.
243 const PPCSubtarget &PPCSubTarget;
245 explicit PPCTargetLowering(PPCTargetMachine &TM);
247 /// getTargetNodeName() - This method returns the name of a target specific
249 virtual const char *getTargetNodeName(unsigned Opcode) const;
251 /// getSetCCResultType - Return the ISD::SETCC ValueType
252 virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const;
254 /// getPreIndexedAddressParts - returns true by value, base pointer and
255 /// offset pointer and addressing mode by reference if the node's address
256 /// can be legally represented as pre-indexed load / store address.
257 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
259 ISD::MemIndexedMode &AM,
260 SelectionDAG &DAG) const;
262 /// SelectAddressRegReg - Given the specified addressed, check to see if it
263 /// can be represented as an indexed [r+r] operation. Returns false if it
264 /// can be more efficiently represented with [r+imm].
265 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
266 SelectionDAG &DAG) const;
268 /// SelectAddressRegImm - Returns true if the address N can be represented
269 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
270 /// is not better represented as reg+reg.
271 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
272 SelectionDAG &DAG) const;
274 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
275 /// represented as an indexed [r+r] operation.
276 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
277 SelectionDAG &DAG) const;
279 /// SelectAddressRegImmShift - Returns true if the address N can be
280 /// represented by a base register plus a signed 14-bit displacement
281 /// [r+imm*4]. Suitable for use by STD and friends.
282 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
283 SelectionDAG &DAG) const;
286 /// LowerOperation - Provide custom lowering hooks for some operations.
288 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
290 /// ReplaceNodeResults - Replace the results of node with an illegal result
291 /// type with new values built out of custom code.
293 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
296 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
298 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
302 const SelectionDAG &DAG,
303 unsigned Depth = 0) const;
305 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
306 MachineBasicBlock *MBB,
307 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
308 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
309 MachineBasicBlock *MBB, bool is64Bit,
310 unsigned BinOpcode) const;
311 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
312 MachineBasicBlock *MBB,
313 bool is8bit, unsigned Opcode) const;
315 ConstraintType getConstraintType(const std::string &Constraint) const;
316 std::pair<unsigned, const TargetRegisterClass*>
317 getRegForInlineAsmConstraint(const std::string &Constraint,
320 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
321 /// function arguments in the caller parameter area. This is the actual
322 /// alignment, not its logarithm.
323 unsigned getByValTypeAlignment(const Type *Ty) const;
325 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
326 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
327 /// true it means one of the asm constraint of the inline asm instruction
328 /// being processed is 'm'.
329 virtual void LowerAsmOperandForConstraint(SDValue Op,
330 char ConstraintLetter,
332 std::vector<SDValue> &Ops,
333 SelectionDAG &DAG) const;
335 /// isLegalAddressingMode - Return true if the addressing mode represented
336 /// by AM is legal for this target, for a load/store of the specified type.
337 virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const;
339 /// isLegalAddressImmediate - Return true if the integer value can be used
340 /// as the offset of the target addressing mode for load / store of the
342 virtual bool isLegalAddressImmediate(int64_t V, const Type *Ty) const;
344 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
345 /// the offset of the target addressing mode.
346 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
348 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
350 /// getOptimalMemOpType - Returns the target specific optimal type for load
351 /// and store operations as a result of memset, memcpy, and memmove
352 /// lowering. If DstAlign is zero that means it's safe to destination
353 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
354 /// means there isn't a need to check it against alignment requirement,
355 /// probably because the source does not need to be loaded. If
356 /// 'NonScalarIntSafe' is true, that means it's safe to return a
357 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
358 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
359 /// constant so it does not need to be loaded.
360 /// It returns EVT::Other if SelectionDAG should be responsible for
361 /// determining the type.
363 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
364 bool NonScalarIntSafe, bool MemcpyStrSrc,
365 SelectionDAG &DAG) const;
367 /// getFunctionAlignment - Return the Log2 alignment of this function.
368 virtual unsigned getFunctionAlignment(const Function *F) const;
371 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
372 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
375 IsEligibleForTailCallOptimization(SDValue Callee,
376 CallingConv::ID CalleeCC,
378 const SmallVectorImpl<ISD::InputArg> &Ins,
379 SelectionDAG& DAG) const;
381 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
389 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG);
390 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
391 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
392 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
393 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
394 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
395 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG);
396 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG);
397 SDValue LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG);
398 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
399 int VarArgsFrameIndex, int VarArgsStackOffset,
400 unsigned VarArgsNumGPR, unsigned VarArgsNumFPR,
401 const PPCSubtarget &Subtarget);
402 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG, int VarArgsFrameIndex,
403 int VarArgsStackOffset, unsigned VarArgsNumGPR,
404 unsigned VarArgsNumFPR, const PPCSubtarget &Subtarget);
405 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
406 const PPCSubtarget &Subtarget);
407 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
408 const PPCSubtarget &Subtarget);
409 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
410 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl);
411 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG);
412 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG);
413 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG);
414 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG);
415 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG);
416 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG);
417 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG);
418 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG);
419 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG);
420 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG);
422 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
423 CallingConv::ID CallConv, bool isVarArg,
424 const SmallVectorImpl<ISD::InputArg> &Ins,
425 DebugLoc dl, SelectionDAG &DAG,
426 SmallVectorImpl<SDValue> &InVals);
427 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
430 SmallVector<std::pair<unsigned, SDValue>, 8>
432 SDValue InFlag, SDValue Chain,
434 int SPDiff, unsigned NumBytes,
435 const SmallVectorImpl<ISD::InputArg> &Ins,
436 SmallVectorImpl<SDValue> &InVals);
439 LowerFormalArguments(SDValue Chain,
440 CallingConv::ID CallConv, bool isVarArg,
441 const SmallVectorImpl<ISD::InputArg> &Ins,
442 DebugLoc dl, SelectionDAG &DAG,
443 SmallVectorImpl<SDValue> &InVals);
446 LowerCall(SDValue Chain, SDValue Callee,
447 CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
448 const SmallVectorImpl<ISD::OutputArg> &Outs,
449 const SmallVectorImpl<ISD::InputArg> &Ins,
450 DebugLoc dl, SelectionDAG &DAG,
451 SmallVectorImpl<SDValue> &InVals);
454 LowerReturn(SDValue Chain,
455 CallingConv::ID CallConv, bool isVarArg,
456 const SmallVectorImpl<ISD::OutputArg> &Outs,
457 DebugLoc dl, SelectionDAG &DAG);
460 LowerFormalArguments_Darwin(SDValue Chain,
461 CallingConv::ID CallConv, bool isVarArg,
462 const SmallVectorImpl<ISD::InputArg> &Ins,
463 DebugLoc dl, SelectionDAG &DAG,
464 SmallVectorImpl<SDValue> &InVals);
466 LowerFormalArguments_SVR4(SDValue Chain,
467 CallingConv::ID CallConv, bool isVarArg,
468 const SmallVectorImpl<ISD::InputArg> &Ins,
469 DebugLoc dl, SelectionDAG &DAG,
470 SmallVectorImpl<SDValue> &InVals);
473 LowerCall_Darwin(SDValue Chain, SDValue Callee,
474 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
475 const SmallVectorImpl<ISD::OutputArg> &Outs,
476 const SmallVectorImpl<ISD::InputArg> &Ins,
477 DebugLoc dl, SelectionDAG &DAG,
478 SmallVectorImpl<SDValue> &InVals);
480 LowerCall_SVR4(SDValue Chain, SDValue Callee,
481 CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
482 const SmallVectorImpl<ISD::OutputArg> &Outs,
483 const SmallVectorImpl<ISD::InputArg> &Ins,
484 DebugLoc dl, SelectionDAG &DAG,
485 SmallVectorImpl<SDValue> &InVals);
489 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H