1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCSubtarget.h"
20 #include "llvm/Target/TargetLowering.h"
21 #include "llvm/CodeGen/SelectionDAG.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
64 /// The following three target-specific nodes are used for calls through
65 /// function pointers in the 64-bit SVR4 ABI.
67 /// Restore the TOC from the TOC save area of the current stack frame.
68 /// This is basically a hard coded load instruction which additionally
69 /// takes/produces a flag.
72 /// Like a regular LOAD but additionally taking/producing a flag.
75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76 /// a hard coded load instruction.
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
97 /// CALL - A direct function call.
98 /// CALL_NOP_SVR4 is a call with the special NOP which follows 64-bit
100 CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4,
102 /// NOP - Special NOP which follows 64-bit SVR4 calls.
105 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
106 /// MTCTR instruction.
109 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
110 /// BCTRL instruction.
111 BCTRL_Darwin, BCTRL_SVR4,
113 /// Return with a flag operand, matched by 'blr'
116 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
117 /// instructions. This copies the bits corresponding to the specified
118 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
122 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
123 /// instructions. For lack of better number, we use the opcode number
124 /// encoding for the OPC field to identify the compare. For example, 838
128 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
129 /// altivec VCMP*o instructions. For lack of better number, we use the
130 /// opcode number encoding for the OPC field to identify the compare. For
131 /// example, 838 is VCMPGTSH.
134 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
135 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
136 /// condition register to branch on, OPC is the branch opcode to use (e.g.
137 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
138 /// an optional input flag argument.
141 // The following 5 instructions are used only as part of the
142 // long double-to-int conversion sequence.
144 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
148 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
151 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
154 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
155 /// rounding towards zero. It has flags added so it won't move past the
156 /// FPSCR-setting instructions.
159 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
162 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
163 /// reserve indexed. This is used to implement atomic operations.
166 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
167 /// indexed. This is used to implement atomic operations.
170 /// TC_RETURN - A tail call return.
172 /// operand #1 callee (register or absolute)
173 /// operand #2 stack adjustment
174 /// operand #3 optional in flag
177 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
178 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
180 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
181 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
182 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
186 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
187 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
188 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
194 /// Define some predicates that are used for node matching.
196 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
197 /// VPKUHUM instruction.
198 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
200 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
201 /// VPKUWUM instruction.
202 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
204 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
205 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
206 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
209 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
210 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
211 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
214 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
215 /// amount, otherwise return -1.
216 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
218 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
219 /// specifies a splat of a single element that is suitable for input to
220 /// VSPLTB/VSPLTH/VSPLTW.
221 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
223 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
225 bool isAllNegativeZeroVector(SDNode *N);
227 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
228 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
229 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
231 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
232 /// formed by using a vspltis[bhw] instruction of the specified element
233 /// size, return the constant being splatted. The ByteSize field indicates
234 /// the number of bytes of each element [124] -> [bhw].
235 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
238 class PPCTargetLowering : public TargetLowering {
239 const PPCSubtarget &PPCSubTarget;
242 explicit PPCTargetLowering(PPCTargetMachine &TM);
244 /// getTargetNodeName() - This method returns the name of a target specific
246 virtual const char *getTargetNodeName(unsigned Opcode) const;
248 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
250 /// getSetCCResultType - Return the ISD::SETCC ValueType
251 virtual EVT getSetCCResultType(EVT VT) const;
253 /// getPreIndexedAddressParts - returns true by value, base pointer and
254 /// offset pointer and addressing mode by reference if the node's address
255 /// can be legally represented as pre-indexed load / store address.
256 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
258 ISD::MemIndexedMode &AM,
259 SelectionDAG &DAG) const;
261 /// SelectAddressRegReg - Given the specified addressed, check to see if it
262 /// can be represented as an indexed [r+r] operation. Returns false if it
263 /// can be more efficiently represented with [r+imm].
264 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
265 SelectionDAG &DAG) const;
267 /// SelectAddressRegImm - Returns true if the address N can be represented
268 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
269 /// is not better represented as reg+reg.
270 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
271 SelectionDAG &DAG) const;
273 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
274 /// represented as an indexed [r+r] operation.
275 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
276 SelectionDAG &DAG) const;
278 /// SelectAddressRegImmShift - Returns true if the address N can be
279 /// represented by a base register plus a signed 14-bit displacement
280 /// [r+imm*4]. Suitable for use by STD and friends.
281 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
282 SelectionDAG &DAG) const;
284 Sched::Preference getSchedulingPreference(SDNode *N) const;
286 /// LowerOperation - Provide custom lowering hooks for some operations.
288 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
290 /// ReplaceNodeResults - Replace the results of node with an illegal result
291 /// type with new values built out of custom code.
293 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
294 SelectionDAG &DAG) const;
296 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
298 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
301 const SelectionDAG &DAG,
302 unsigned Depth = 0) const;
304 virtual MachineBasicBlock *
305 EmitInstrWithCustomInserter(MachineInstr *MI,
306 MachineBasicBlock *MBB) const;
307 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
308 MachineBasicBlock *MBB, bool is64Bit,
309 unsigned BinOpcode) const;
310 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
311 MachineBasicBlock *MBB,
312 bool is8bit, unsigned Opcode) const;
314 ConstraintType getConstraintType(const std::string &Constraint) const;
316 /// Examine constraint string and operand type and determine a weight value.
317 /// The operand object must already have been set up with the operand type.
318 ConstraintWeight getSingleConstraintMatchWeight(
319 AsmOperandInfo &info, const char *constraint) const;
321 std::pair<unsigned, const TargetRegisterClass*>
322 getRegForInlineAsmConstraint(const std::string &Constraint,
325 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
326 /// function arguments in the caller parameter area. This is the actual
327 /// alignment, not its logarithm.
328 unsigned getByValTypeAlignment(Type *Ty) const;
330 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
331 /// vector. If it is invalid, don't add anything to Ops.
332 virtual void LowerAsmOperandForConstraint(SDValue Op,
333 std::string &Constraint,
334 std::vector<SDValue> &Ops,
335 SelectionDAG &DAG) const;
337 /// isLegalAddressingMode - Return true if the addressing mode represented
338 /// by AM is legal for this target, for a load/store of the specified type.
339 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
341 /// isLegalAddressImmediate - Return true if the integer value can be used
342 /// as the offset of the target addressing mode for load / store of the
344 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
346 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
347 /// the offset of the target addressing mode.
348 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
350 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
352 /// getOptimalMemOpType - Returns the target specific optimal type for load
353 /// and store operations as a result of memset, memcpy, and memmove
354 /// lowering. If DstAlign is zero that means it's safe to destination
355 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
356 /// means there isn't a need to check it against alignment requirement,
357 /// probably because the source does not need to be loaded. If
358 /// 'IsZeroVal' is true, that means it's safe to return a
359 /// non-scalar-integer type, e.g. empty string source, constant, or loaded
360 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is
361 /// constant so it does not need to be loaded.
362 /// It returns EVT::Other if the type should be determined using generic
363 /// target-independent logic.
365 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
366 bool IsZeroVal, bool MemcpyStrSrc,
367 MachineFunction &MF) const;
369 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
370 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
371 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
372 /// is expanded to mul + add.
373 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
376 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
377 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
380 IsEligibleForTailCallOptimization(SDValue Callee,
381 CallingConv::ID CalleeCC,
383 const SmallVectorImpl<ISD::InputArg> &Ins,
384 SelectionDAG& DAG) const;
386 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
394 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
395 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
396 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
397 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
398 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
399 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
400 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
401 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
402 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
403 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
404 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
405 const PPCSubtarget &Subtarget) const;
406 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
407 const PPCSubtarget &Subtarget) const;
408 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
409 const PPCSubtarget &Subtarget) const;
410 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
411 const PPCSubtarget &Subtarget) const;
412 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
413 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
414 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
415 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
416 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
417 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
418 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
419 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
420 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
421 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
422 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
423 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
425 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
426 CallingConv::ID CallConv, bool isVarArg,
427 const SmallVectorImpl<ISD::InputArg> &Ins,
428 DebugLoc dl, SelectionDAG &DAG,
429 SmallVectorImpl<SDValue> &InVals) const;
430 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
433 SmallVector<std::pair<unsigned, SDValue>, 8>
435 SDValue InFlag, SDValue Chain,
437 int SPDiff, unsigned NumBytes,
438 const SmallVectorImpl<ISD::InputArg> &Ins,
439 SmallVectorImpl<SDValue> &InVals) const;
442 LowerFormalArguments(SDValue Chain,
443 CallingConv::ID CallConv, bool isVarArg,
444 const SmallVectorImpl<ISD::InputArg> &Ins,
445 DebugLoc dl, SelectionDAG &DAG,
446 SmallVectorImpl<SDValue> &InVals) const;
449 LowerCall(TargetLowering::CallLoweringInfo &CLI,
450 SmallVectorImpl<SDValue> &InVals) const;
453 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
455 const SmallVectorImpl<ISD::OutputArg> &Outs,
456 LLVMContext &Context) const;
459 LowerReturn(SDValue Chain,
460 CallingConv::ID CallConv, bool isVarArg,
461 const SmallVectorImpl<ISD::OutputArg> &Outs,
462 const SmallVectorImpl<SDValue> &OutVals,
463 DebugLoc dl, SelectionDAG &DAG) const;
466 LowerFormalArguments_Darwin(SDValue Chain,
467 CallingConv::ID CallConv, bool isVarArg,
468 const SmallVectorImpl<ISD::InputArg> &Ins,
469 DebugLoc dl, SelectionDAG &DAG,
470 SmallVectorImpl<SDValue> &InVals) const;
472 LowerFormalArguments_SVR4(SDValue Chain,
473 CallingConv::ID CallConv, bool isVarArg,
474 const SmallVectorImpl<ISD::InputArg> &Ins,
475 DebugLoc dl, SelectionDAG &DAG,
476 SmallVectorImpl<SDValue> &InVals) const;
479 LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
480 bool isVarArg, bool isTailCall,
481 const SmallVectorImpl<ISD::OutputArg> &Outs,
482 const SmallVectorImpl<SDValue> &OutVals,
483 const SmallVectorImpl<ISD::InputArg> &Ins,
484 DebugLoc dl, SelectionDAG &DAG,
485 SmallVectorImpl<SDValue> &InVals) const;
487 LowerCall_SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
488 bool isVarArg, bool isTailCall,
489 const SmallVectorImpl<ISD::OutputArg> &Outs,
490 const SmallVectorImpl<SDValue> &OutVals,
491 const SmallVectorImpl<ISD::InputArg> &Ins,
492 DebugLoc dl, SelectionDAG &DAG,
493 SmallVectorImpl<SDValue> &InVals) const;
497 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H