1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
76 /// The following two target-specific nodes are used for calls through
77 /// function pointers in the 64-bit SVR4 ABI.
79 /// Like a regular LOAD but additionally taking/producing a flag.
82 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded
86 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
87 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
88 /// compute an allocation on the stack.
91 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
92 /// at function entry, used for PIC code.
95 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
96 /// shift amounts. These nodes are generated by the multi-precision shift
100 /// The combination of sra[wd]i and addze used to implemented signed
101 /// integer division by a power of 2. The first operand is the dividend,
102 /// and the second is the constant shift amount (representing the
106 /// CALL - A direct function call.
107 /// CALL_NOP is a call with the special NOP which follows 64-bit
111 /// CALL_TLS and CALL_NOP_TLS - Versions of CALL and CALL_NOP used
112 /// to access TLS variables.
113 CALL_TLS, CALL_NOP_TLS,
115 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
116 /// MTCTR instruction.
119 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
120 /// BCTRL instruction.
123 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
124 /// instruction and the TOC reload required on SVR4 PPC64.
127 /// Return with a flag operand, matched by 'blr'
130 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
131 /// This copies the bits corresponding to the specified CRREG into the
132 /// resultant GPR. Bits corresponding to other CR regs are undefined.
135 // FIXME: Remove these once the ANDI glue bug is fixed:
136 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
137 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
138 /// implement truncation of i32 or i64 to i1.
139 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
141 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
142 // target (returns (Lo, Hi)). It takes a chain operand.
145 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
148 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
151 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
152 /// instructions. For lack of better number, we use the opcode number
153 /// encoding for the OPC field to identify the compare. For example, 838
157 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
158 /// altivec VCMP*o instructions. For lack of better number, we use the
159 /// opcode number encoding for the OPC field to identify the compare. For
160 /// example, 838 is VCMPGTSH.
163 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
164 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
165 /// condition register to branch on, OPC is the branch opcode to use (e.g.
166 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
167 /// an optional input flag argument.
170 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
174 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
175 /// towards zero. Used only as part of the long double-to-int
176 /// conversion sequence.
179 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
182 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
183 /// reserve indexed. This is used to implement atomic operations.
186 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
187 /// indexed. This is used to implement atomic operations.
190 /// TC_RETURN - A tail call return.
192 /// operand #1 callee (register or absolute)
193 /// operand #2 stack adjustment
194 /// operand #3 optional in flag
197 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
201 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
205 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
206 /// local dynamic TLS on PPC32.
209 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
210 /// TLS model, produces an ADDIS8 instruction that adds the GOT
211 /// base to sym\@got\@tprel\@ha.
214 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
215 /// TLS model, produces a LD instruction with base register G8RReg
216 /// and offset sym\@got\@tprel\@l. This completes the addition that
217 /// finds the offset of "sym" relative to the thread pointer.
220 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
221 /// model, produces an ADD instruction that adds the contents of
222 /// G8RReg to the thread pointer. Symbol contains a relocation
223 /// sym\@tls which is to be replaced by the thread pointer and
224 /// identifies to the linker that the instruction is part of a
228 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
229 /// model, produces an ADDIS8 instruction that adds the GOT base
230 /// register to sym\@got\@tlsgd\@ha.
233 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
234 /// model, produces an ADDI8 instruction that adds G8RReg to
235 /// sym\@got\@tlsgd\@l.
238 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
239 /// model, produces an ADDIS8 instruction that adds the GOT base
240 /// register to sym\@got\@tlsld\@ha.
243 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
244 /// model, produces an ADDI8 instruction that adds G8RReg to
245 /// sym\@got\@tlsld\@l.
248 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
249 /// local-dynamic TLS model, produces an ADDIS8 instruction
250 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
251 /// to tie this in place following a copy to %X3 from the result
252 /// of a GET_TLSLD_ADDR.
255 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
256 /// model, produces an ADDI8 instruction that adds G8RReg to
257 /// sym\@got\@dtprel\@l.
260 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
261 /// during instruction selection to optimize a BUILD_VECTOR into
262 /// operations on splats. This is necessary to avoid losing these
263 /// optimizations due to constant folding.
266 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
267 /// operand identifies the operating system entry point.
270 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
271 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
272 /// or stxvd2x instruction. The chain is necessary because the
273 /// sequence replaces a load and needs to provide the same number
277 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
278 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
279 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
281 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
283 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
284 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
285 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
289 /// STFIWX - The STFIWX instruction. The first operand is an input token
290 /// chain, then an f64 value to store, then an address to store it to.
293 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
294 /// load which sign-extends from a 32-bit integer value into the
295 /// destination 64-bit register.
298 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
299 /// load which zero-extends from a 32-bit integer value into the
300 /// destination 64-bit register.
303 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
304 /// produces an ADDIS8 instruction that adds the TOC base register to
308 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
309 /// produces a LD instruction with base register G8RReg and offset
310 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
313 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
314 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
315 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
318 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
319 /// Maps directly to an lxvd2x instruction that will be followed by
323 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
324 /// Maps directly to an stxvd2x instruction that will be preceded by
330 /// Define some predicates that are used for node matching.
332 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
333 /// VPKUHUM instruction.
334 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
337 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
338 /// VPKUWUM instruction.
339 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
342 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
343 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
344 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
345 unsigned ShuffleKind, SelectionDAG &DAG);
347 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
348 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
349 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
350 unsigned ShuffleKind, SelectionDAG &DAG);
352 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
353 /// shift amount, otherwise return -1.
354 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
357 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
358 /// specifies a splat of a single element that is suitable for input to
359 /// VSPLTB/VSPLTH/VSPLTW.
360 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
362 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
364 bool isAllNegativeZeroVector(SDNode *N);
366 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
367 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
368 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
370 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
371 /// formed by using a vspltis[bhw] instruction of the specified element
372 /// size, return the constant being splatted. The ByteSize field indicates
373 /// the number of bytes of each element [124] -> [bhw].
374 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
378 class PPCTargetLowering : public TargetLowering {
379 const PPCSubtarget &Subtarget;
382 explicit PPCTargetLowering(const PPCTargetMachine &TM);
384 /// getTargetNodeName() - This method returns the name of a target specific
386 const char *getTargetNodeName(unsigned Opcode) const override;
388 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
390 bool isCheapToSpeculateCttz() const override {
394 bool isCheapToSpeculateCtlz() const override {
398 /// getSetCCResultType - Return the ISD::SETCC ValueType
399 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
401 /// Return true if target always beneficiates from combining into FMA for a
402 /// given value type. This must typically return false on targets where FMA
403 /// takes more cycles to execute than FADD.
404 bool enableAggressiveFMAFusion(EVT VT) const override;
406 /// getPreIndexedAddressParts - returns true by value, base pointer and
407 /// offset pointer and addressing mode by reference if the node's address
408 /// can be legally represented as pre-indexed load / store address.
409 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
411 ISD::MemIndexedMode &AM,
412 SelectionDAG &DAG) const override;
414 /// SelectAddressRegReg - Given the specified addressed, check to see if it
415 /// can be represented as an indexed [r+r] operation. Returns false if it
416 /// can be more efficiently represented with [r+imm].
417 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
418 SelectionDAG &DAG) const;
420 /// SelectAddressRegImm - Returns true if the address N can be represented
421 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
422 /// is not better represented as reg+reg. If Aligned is true, only accept
423 /// displacements suitable for STD and friends, i.e. multiples of 4.
424 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
425 SelectionDAG &DAG, bool Aligned) const;
427 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
428 /// represented as an indexed [r+r] operation.
429 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
430 SelectionDAG &DAG) const;
432 Sched::Preference getSchedulingPreference(SDNode *N) const override;
434 /// LowerOperation - Provide custom lowering hooks for some operations.
436 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
438 /// ReplaceNodeResults - Replace the results of node with an illegal result
439 /// type with new values built out of custom code.
441 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
442 SelectionDAG &DAG) const override;
444 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
445 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
447 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
449 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
450 std::vector<SDNode *> *Created) const override;
452 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
454 void computeKnownBitsForTargetNode(const SDValue Op,
457 const SelectionDAG &DAG,
458 unsigned Depth = 0) const override;
460 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
462 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
463 bool IsStore, bool IsLoad) const override;
464 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
465 bool IsStore, bool IsLoad) const override;
468 EmitInstrWithCustomInserter(MachineInstr *MI,
469 MachineBasicBlock *MBB) const override;
470 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
471 MachineBasicBlock *MBB, bool is64Bit,
472 unsigned BinOpcode) const;
473 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
474 MachineBasicBlock *MBB,
475 bool is8bit, unsigned Opcode) const;
477 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
478 MachineBasicBlock *MBB) const;
480 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
481 MachineBasicBlock *MBB) const;
484 getConstraintType(const std::string &Constraint) const override;
486 /// Examine constraint string and operand type and determine a weight value.
487 /// The operand object must already have been set up with the operand type.
488 ConstraintWeight getSingleConstraintMatchWeight(
489 AsmOperandInfo &info, const char *constraint) const override;
491 std::pair<unsigned, const TargetRegisterClass*>
492 getRegForInlineAsmConstraint(const std::string &Constraint,
493 MVT VT) const override;
495 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
496 /// function arguments in the caller parameter area. This is the actual
497 /// alignment, not its logarithm.
498 unsigned getByValTypeAlignment(Type *Ty) const override;
500 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
501 /// vector. If it is invalid, don't add anything to Ops.
502 void LowerAsmOperandForConstraint(SDValue Op,
503 std::string &Constraint,
504 std::vector<SDValue> &Ops,
505 SelectionDAG &DAG) const override;
507 /// isLegalAddressingMode - Return true if the addressing mode represented
508 /// by AM is legal for this target, for a load/store of the specified type.
509 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
511 /// isLegalICmpImmediate - Return true if the specified immediate is legal
512 /// icmp immediate, that is the target has icmp instructions which can
513 /// compare a register against the immediate without having to materialize
514 /// the immediate into a register.
515 bool isLegalICmpImmediate(int64_t Imm) const override;
517 /// isLegalAddImmediate - Return true if the specified immediate is legal
518 /// add immediate, that is the target has add instructions which can
519 /// add a register and the immediate without having to materialize
520 /// the immediate into a register.
521 bool isLegalAddImmediate(int64_t Imm) const override;
523 /// isTruncateFree - Return true if it's free to truncate a value of
524 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
525 /// register X1 to i32 by referencing its sub-register R1.
526 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
527 bool isTruncateFree(EVT VT1, EVT VT2) const override;
529 /// \brief Returns true if it is beneficial to convert a load of a constant
530 /// to just the constant itself.
531 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
532 Type *Ty) const override;
534 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
536 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
538 unsigned Intrinsic) const override;
540 /// getOptimalMemOpType - Returns the target specific optimal type for load
541 /// and store operations as a result of memset, memcpy, and memmove
542 /// lowering. If DstAlign is zero that means it's safe to destination
543 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
544 /// means there isn't a need to check it against alignment requirement,
545 /// probably because the source does not need to be loaded. If 'IsMemset' is
546 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
547 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
548 /// source is constant so it does not need to be loaded.
549 /// It returns EVT::Other if the type should be determined using generic
550 /// target-independent logic.
552 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
553 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
554 MachineFunction &MF) const override;
556 /// Is unaligned memory access allowed for the given type, and is it fast
557 /// relative to software emulation.
558 bool allowsMisalignedMemoryAccesses(EVT VT,
561 bool *Fast = nullptr) const override;
563 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
564 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
565 /// expanded to FMAs when this method returns true, otherwise fmuladd is
566 /// expanded to fmul + fadd.
567 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
569 // Should we expand the build vector with shuffles?
571 shouldExpandBuildVectorWithShuffles(EVT VT,
572 unsigned DefinedValues) const override;
574 /// createFastISel - This method returns a target-specific FastISel object,
575 /// or null if the target does not support "fast" instruction selection.
576 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
577 const TargetLibraryInfo *LibInfo) const override;
579 /// \brief Returns true if an argument of type Ty needs to be passed in a
580 /// contiguous block of registers in calling convention CallConv.
581 bool functionArgumentNeedsConsecutiveRegisters(
582 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
583 // We support any array type as "consecutive" block in the parameter
584 // save area. The element type defines the alignment requirement and
585 // whether the argument should go in GPRs, FPRs, or VRs if available.
587 // Note that clang uses this capability both to implement the ELFv2
588 // homogeneous float/vector aggregate ABI, and to avoid having to use
589 // "byval" when passing aggregates that might fully fit in registers.
590 return Ty->isArrayTy();
594 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
595 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
598 IsEligibleForTailCallOptimization(SDValue Callee,
599 CallingConv::ID CalleeCC,
601 const SmallVectorImpl<ISD::InputArg> &Ins,
602 SelectionDAG& DAG) const;
604 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
612 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
613 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
614 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
615 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
616 std::pair<SDValue,SDValue> lowerTLSCall(SDValue Op, SDLoc dl,
617 SelectionDAG &DAG) const;
618 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
619 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
620 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
621 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
622 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
623 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
624 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
625 const PPCSubtarget &Subtarget) const;
626 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
627 const PPCSubtarget &Subtarget) const;
628 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
629 const PPCSubtarget &Subtarget) const;
630 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
631 const PPCSubtarget &Subtarget) const;
632 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
633 const PPCSubtarget &Subtarget) const;
634 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
635 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
636 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
637 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
638 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
639 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
640 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
641 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
642 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
643 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
644 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
645 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
646 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
647 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
648 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
649 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
651 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
652 CallingConv::ID CallConv, bool isVarArg,
653 const SmallVectorImpl<ISD::InputArg> &Ins,
654 SDLoc dl, SelectionDAG &DAG,
655 SmallVectorImpl<SDValue> &InVals) const;
656 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
659 SmallVector<std::pair<unsigned, SDValue>, 8>
661 SDValue InFlag, SDValue Chain,
663 int SPDiff, unsigned NumBytes,
664 const SmallVectorImpl<ISD::InputArg> &Ins,
665 SmallVectorImpl<SDValue> &InVals) const;
668 LowerFormalArguments(SDValue Chain,
669 CallingConv::ID CallConv, bool isVarArg,
670 const SmallVectorImpl<ISD::InputArg> &Ins,
671 SDLoc dl, SelectionDAG &DAG,
672 SmallVectorImpl<SDValue> &InVals) const override;
675 LowerCall(TargetLowering::CallLoweringInfo &CLI,
676 SmallVectorImpl<SDValue> &InVals) const override;
679 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
681 const SmallVectorImpl<ISD::OutputArg> &Outs,
682 LLVMContext &Context) const override;
685 LowerReturn(SDValue Chain,
686 CallingConv::ID CallConv, bool isVarArg,
687 const SmallVectorImpl<ISD::OutputArg> &Outs,
688 const SmallVectorImpl<SDValue> &OutVals,
689 SDLoc dl, SelectionDAG &DAG) const override;
692 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
693 SDValue ArgVal, SDLoc dl) const;
696 LowerFormalArguments_Darwin(SDValue Chain,
697 CallingConv::ID CallConv, bool isVarArg,
698 const SmallVectorImpl<ISD::InputArg> &Ins,
699 SDLoc dl, SelectionDAG &DAG,
700 SmallVectorImpl<SDValue> &InVals) const;
702 LowerFormalArguments_64SVR4(SDValue Chain,
703 CallingConv::ID CallConv, bool isVarArg,
704 const SmallVectorImpl<ISD::InputArg> &Ins,
705 SDLoc dl, SelectionDAG &DAG,
706 SmallVectorImpl<SDValue> &InVals) const;
708 LowerFormalArguments_32SVR4(SDValue Chain,
709 CallingConv::ID CallConv, bool isVarArg,
710 const SmallVectorImpl<ISD::InputArg> &Ins,
711 SDLoc dl, SelectionDAG &DAG,
712 SmallVectorImpl<SDValue> &InVals) const;
715 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
716 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
717 SelectionDAG &DAG, SDLoc dl) const;
720 LowerCall_Darwin(SDValue Chain, SDValue Callee,
721 CallingConv::ID CallConv,
722 bool isVarArg, bool isTailCall,
723 const SmallVectorImpl<ISD::OutputArg> &Outs,
724 const SmallVectorImpl<SDValue> &OutVals,
725 const SmallVectorImpl<ISD::InputArg> &Ins,
726 SDLoc dl, SelectionDAG &DAG,
727 SmallVectorImpl<SDValue> &InVals) const;
729 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
730 CallingConv::ID CallConv,
731 bool isVarArg, bool isTailCall,
732 const SmallVectorImpl<ISD::OutputArg> &Outs,
733 const SmallVectorImpl<SDValue> &OutVals,
734 const SmallVectorImpl<ISD::InputArg> &Ins,
735 SDLoc dl, SelectionDAG &DAG,
736 SmallVectorImpl<SDValue> &InVals) const;
738 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
739 bool isVarArg, bool isTailCall,
740 const SmallVectorImpl<ISD::OutputArg> &Outs,
741 const SmallVectorImpl<SDValue> &OutVals,
742 const SmallVectorImpl<ISD::InputArg> &Ins,
743 SDLoc dl, SelectionDAG &DAG,
744 SmallVectorImpl<SDValue> &InVals) const;
746 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
747 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
749 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
750 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
752 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
753 unsigned &RefinementSteps,
754 bool &UseOneConstNR) const override;
755 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
756 unsigned &RefinementSteps) const override;
757 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
759 CCAssignFn *useFastISelCCs(unsigned Flag) const;
763 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
764 const TargetLibraryInfo *LibInfo);
767 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
768 CCValAssign::LocInfo &LocInfo,
769 ISD::ArgFlagsTy &ArgFlags,
772 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
774 CCValAssign::LocInfo &LocInfo,
775 ISD::ArgFlagsTy &ArgFlags,
778 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
780 CCValAssign::LocInfo &LocInfo,
781 ISD::ArgFlagsTy &ArgFlags,
785 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H