1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
16 #define LLVM_LIB_TARGET_POWERPC_PPCISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// The CMPB instruction (takes two operands of i32 or i64).
67 /// Hi/Lo - These represent the high and low 16-bit parts of a global
68 /// address respectively. These nodes have two operands, the first of
69 /// which must be a TargetGlobalAddress, and the second of which must be a
70 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
71 /// though these are usually folded into other nodes.
76 /// The following two target-specific nodes are used for calls through
77 /// function pointers in the 64-bit SVR4 ABI.
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
93 /// The combination of sra[wd]i and addze used to implemented signed
94 /// integer division by a power of 2. The first operand is the dividend,
95 /// and the second is the constant shift amount (representing the
99 /// CALL - A direct function call.
100 /// CALL_NOP is a call with the special NOP which follows 64-bit
104 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
105 /// MTCTR instruction.
108 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
109 /// BCTRL instruction.
112 /// CHAIN,FLAG = BCTRL(CHAIN, ADDR, INFLAG) - The combination of a bctrl
113 /// instruction and the TOC reload required on SVR4 PPC64.
116 /// Return with a flag operand, matched by 'blr'
119 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
120 /// This copies the bits corresponding to the specified CRREG into the
121 /// resultant GPR. Bits corresponding to other CR regs are undefined.
124 // FIXME: Remove these once the ANDI glue bug is fixed:
125 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
126 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
127 /// implement truncation of i32 or i64 to i1.
128 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
130 // READ_TIME_BASE - A read of the 64-bit time-base register on a 32-bit
131 // target (returns (Lo, Hi)). It takes a chain operand.
134 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
137 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
140 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
141 /// instructions. For lack of better number, we use the opcode number
142 /// encoding for the OPC field to identify the compare. For example, 838
146 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
147 /// altivec VCMP*o instructions. For lack of better number, we use the
148 /// opcode number encoding for the OPC field to identify the compare. For
149 /// example, 838 is VCMPGTSH.
152 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
153 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
154 /// condition register to branch on, OPC is the branch opcode to use (e.g.
155 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
156 /// an optional input flag argument.
159 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
163 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
164 /// towards zero. Used only as part of the long double-to-int
165 /// conversion sequence.
168 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
171 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
172 /// reserve indexed. This is used to implement atomic operations.
175 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
176 /// indexed. This is used to implement atomic operations.
179 /// TC_RETURN - A tail call return.
181 /// operand #1 callee (register or absolute)
182 /// operand #2 stack adjustment
183 /// operand #3 optional in flag
186 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
190 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
194 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
195 /// local dynamic TLS on PPC32.
198 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
199 /// TLS model, produces an ADDIS8 instruction that adds the GOT
200 /// base to sym\@got\@tprel\@ha.
203 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
204 /// TLS model, produces a LD instruction with base register G8RReg
205 /// and offset sym\@got\@tprel\@l. This completes the addition that
206 /// finds the offset of "sym" relative to the thread pointer.
209 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
210 /// model, produces an ADD instruction that adds the contents of
211 /// G8RReg to the thread pointer. Symbol contains a relocation
212 /// sym\@tls which is to be replaced by the thread pointer and
213 /// identifies to the linker that the instruction is part of a
217 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
218 /// model, produces an ADDIS8 instruction that adds the GOT base
219 /// register to sym\@got\@tlsgd\@ha.
222 /// %X3 = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
223 /// model, produces an ADDI8 instruction that adds G8RReg to
224 /// sym\@got\@tlsgd\@l and stores the result in X3. Hidden by
225 /// ADDIS_TLSGD_L_ADDR until after register assignment.
228 /// %X3 = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
229 /// model, produces a call to __tls_get_addr(sym\@tlsgd). Hidden by
230 /// ADDIS_TLSGD_L_ADDR until after register assignment.
233 /// G8RC = ADDI_TLSGD_L_ADDR G8RReg, Symbol, Symbol - Op that
234 /// combines ADDI_TLSGD_L and GET_TLS_ADDR until expansion following
235 /// register assignment.
238 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
239 /// model, produces an ADDIS8 instruction that adds the GOT base
240 /// register to sym\@got\@tlsld\@ha.
243 /// %X3 = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
244 /// model, produces an ADDI8 instruction that adds G8RReg to
245 /// sym\@got\@tlsld\@l and stores the result in X3. Hidden by
246 /// ADDIS_TLSLD_L_ADDR until after register assignment.
249 /// %X3 = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
250 /// model, produces a call to __tls_get_addr(sym\@tlsld). Hidden by
251 /// ADDIS_TLSLD_L_ADDR until after register assignment.
254 /// G8RC = ADDI_TLSLD_L_ADDR G8RReg, Symbol, Symbol - Op that
255 /// combines ADDI_TLSLD_L and GET_TLSLD_ADDR until expansion
256 /// following register assignment.
259 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol - For the local-dynamic TLS
260 /// model, produces an ADDIS8 instruction that adds X3 to
264 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
265 /// model, produces an ADDI8 instruction that adds G8RReg to
266 /// sym\@got\@dtprel\@l.
269 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
270 /// during instruction selection to optimize a BUILD_VECTOR into
271 /// operations on splats. This is necessary to avoid losing these
272 /// optimizations due to constant folding.
275 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
276 /// operand identifies the operating system entry point.
279 /// VSRC, CHAIN = XXSWAPD CHAIN, VSRC - Occurs only for little
280 /// endian. Maps to an xxswapd instruction that corrects an lxvd2x
281 /// or stxvd2x instruction. The chain is necessary because the
282 /// sequence replaces a load and needs to provide the same number
286 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
287 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
288 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
290 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
292 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
293 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
294 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
298 /// STFIWX - The STFIWX instruction. The first operand is an input token
299 /// chain, then an f64 value to store, then an address to store it to.
302 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
303 /// load which sign-extends from a 32-bit integer value into the
304 /// destination 64-bit register.
307 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
308 /// load which zero-extends from a 32-bit integer value into the
309 /// destination 64-bit register.
312 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
313 /// produces an ADDIS8 instruction that adds the TOC base register to
317 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
318 /// produces a LD instruction with base register G8RReg and offset
319 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
322 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
323 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
324 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
327 /// VSRC, CHAIN = LXVD2X_LE CHAIN, Ptr - Occurs only for little endian.
328 /// Maps directly to an lxvd2x instruction that will be followed by
332 /// CHAIN = STXVD2X CHAIN, VSRC, Ptr - Occurs only for little endian.
333 /// Maps directly to an stxvd2x instruction that will be preceded by
339 /// Define some predicates that are used for node matching.
341 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
342 /// VPKUHUM instruction.
343 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
346 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
347 /// VPKUWUM instruction.
348 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, unsigned ShuffleKind,
351 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
352 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
353 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
354 unsigned ShuffleKind, SelectionDAG &DAG);
356 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
357 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
358 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
359 unsigned ShuffleKind, SelectionDAG &DAG);
361 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the
362 /// shift amount, otherwise return -1.
363 int isVSLDOIShuffleMask(SDNode *N, unsigned ShuffleKind,
366 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
367 /// specifies a splat of a single element that is suitable for input to
368 /// VSPLTB/VSPLTH/VSPLTW.
369 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
371 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
373 bool isAllNegativeZeroVector(SDNode *N);
375 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
376 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
377 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
379 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
380 /// formed by using a vspltis[bhw] instruction of the specified element
381 /// size, return the constant being splatted. The ByteSize field indicates
382 /// the number of bytes of each element [124] -> [bhw].
383 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
386 class PPCTargetLowering : public TargetLowering {
387 const PPCSubtarget &Subtarget;
390 explicit PPCTargetLowering(const PPCTargetMachine &TM,
391 const PPCSubtarget &STI);
393 /// getTargetNodeName() - This method returns the name of a target specific
395 const char *getTargetNodeName(unsigned Opcode) const override;
397 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
399 bool isCheapToSpeculateCttz() const override {
403 bool isCheapToSpeculateCtlz() const override {
407 /// getSetCCResultType - Return the ISD::SETCC ValueType
408 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
410 /// Return true if target always beneficiates from combining into FMA for a
411 /// given value type. This must typically return false on targets where FMA
412 /// takes more cycles to execute than FADD.
413 bool enableAggressiveFMAFusion(EVT VT) const override;
415 /// getPreIndexedAddressParts - returns true by value, base pointer and
416 /// offset pointer and addressing mode by reference if the node's address
417 /// can be legally represented as pre-indexed load / store address.
418 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
420 ISD::MemIndexedMode &AM,
421 SelectionDAG &DAG) const override;
423 /// SelectAddressRegReg - Given the specified addressed, check to see if it
424 /// can be represented as an indexed [r+r] operation. Returns false if it
425 /// can be more efficiently represented with [r+imm].
426 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
427 SelectionDAG &DAG) const;
429 /// SelectAddressRegImm - Returns true if the address N can be represented
430 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
431 /// is not better represented as reg+reg. If Aligned is true, only accept
432 /// displacements suitable for STD and friends, i.e. multiples of 4.
433 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
434 SelectionDAG &DAG, bool Aligned) const;
436 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
437 /// represented as an indexed [r+r] operation.
438 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
439 SelectionDAG &DAG) const;
441 Sched::Preference getSchedulingPreference(SDNode *N) const override;
443 /// LowerOperation - Provide custom lowering hooks for some operations.
445 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
447 /// ReplaceNodeResults - Replace the results of node with an illegal result
448 /// type with new values built out of custom code.
450 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
451 SelectionDAG &DAG) const override;
453 SDValue expandVSXLoadForLE(SDNode *N, DAGCombinerInfo &DCI) const;
454 SDValue expandVSXStoreForLE(SDNode *N, DAGCombinerInfo &DCI) const;
456 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
458 SDValue BuildSDIVPow2(SDNode *N, const APInt &Divisor, SelectionDAG &DAG,
459 std::vector<SDNode *> *Created) const override;
461 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
463 void computeKnownBitsForTargetNode(const SDValue Op,
466 const SelectionDAG &DAG,
467 unsigned Depth = 0) const override;
469 unsigned getPrefLoopAlignment(MachineLoop *ML) const override;
471 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
472 bool IsStore, bool IsLoad) const override;
473 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
474 bool IsStore, bool IsLoad) const override;
477 EmitInstrWithCustomInserter(MachineInstr *MI,
478 MachineBasicBlock *MBB) const override;
479 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
480 MachineBasicBlock *MBB, bool is64Bit,
481 unsigned BinOpcode) const;
482 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
483 MachineBasicBlock *MBB,
484 bool is8bit, unsigned Opcode) const;
486 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
487 MachineBasicBlock *MBB) const;
489 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
490 MachineBasicBlock *MBB) const;
493 getConstraintType(const std::string &Constraint) const override;
495 /// Examine constraint string and operand type and determine a weight value.
496 /// The operand object must already have been set up with the operand type.
497 ConstraintWeight getSingleConstraintMatchWeight(
498 AsmOperandInfo &info, const char *constraint) const override;
500 std::pair<unsigned, const TargetRegisterClass*>
501 getRegForInlineAsmConstraint(const std::string &Constraint,
502 MVT VT) const override;
504 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
505 /// function arguments in the caller parameter area. This is the actual
506 /// alignment, not its logarithm.
507 unsigned getByValTypeAlignment(Type *Ty) const override;
509 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
510 /// vector. If it is invalid, don't add anything to Ops.
511 void LowerAsmOperandForConstraint(SDValue Op,
512 std::string &Constraint,
513 std::vector<SDValue> &Ops,
514 SelectionDAG &DAG) const override;
516 /// isLegalAddressingMode - Return true if the addressing mode represented
517 /// by AM is legal for this target, for a load/store of the specified type.
518 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
520 /// isLegalICmpImmediate - Return true if the specified immediate is legal
521 /// icmp immediate, that is the target has icmp instructions which can
522 /// compare a register against the immediate without having to materialize
523 /// the immediate into a register.
524 bool isLegalICmpImmediate(int64_t Imm) const override;
526 /// isLegalAddImmediate - Return true if the specified immediate is legal
527 /// add immediate, that is the target has add instructions which can
528 /// add a register and the immediate without having to materialize
529 /// the immediate into a register.
530 bool isLegalAddImmediate(int64_t Imm) const override;
532 /// isTruncateFree - Return true if it's free to truncate a value of
533 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
534 /// register X1 to i32 by referencing its sub-register R1.
535 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
536 bool isTruncateFree(EVT VT1, EVT VT2) const override;
538 bool isZExtFree(SDValue Val, EVT VT2) const override;
540 bool isFPExtFree(EVT VT) const override;
542 /// \brief Returns true if it is beneficial to convert a load of a constant
543 /// to just the constant itself.
544 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
545 Type *Ty) const override;
547 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
549 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
551 unsigned Intrinsic) const override;
553 /// getOptimalMemOpType - Returns the target specific optimal type for load
554 /// and store operations as a result of memset, memcpy, and memmove
555 /// lowering. If DstAlign is zero that means it's safe to destination
556 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
557 /// means there isn't a need to check it against alignment requirement,
558 /// probably because the source does not need to be loaded. If 'IsMemset' is
559 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
560 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
561 /// source is constant so it does not need to be loaded.
562 /// It returns EVT::Other if the type should be determined using generic
563 /// target-independent logic.
565 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
566 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
567 MachineFunction &MF) const override;
569 /// Is unaligned memory access allowed for the given type, and is it fast
570 /// relative to software emulation.
571 bool allowsMisalignedMemoryAccesses(EVT VT,
574 bool *Fast = nullptr) const override;
576 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
577 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
578 /// expanded to FMAs when this method returns true, otherwise fmuladd is
579 /// expanded to fmul + fadd.
580 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
582 const MCPhysReg *getScratchRegisters(CallingConv::ID CC) const override;
584 // Should we expand the build vector with shuffles?
586 shouldExpandBuildVectorWithShuffles(EVT VT,
587 unsigned DefinedValues) const override;
589 /// createFastISel - This method returns a target-specific FastISel object,
590 /// or null if the target does not support "fast" instruction selection.
591 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
592 const TargetLibraryInfo *LibInfo) const override;
594 /// \brief Returns true if an argument of type Ty needs to be passed in a
595 /// contiguous block of registers in calling convention CallConv.
596 bool functionArgumentNeedsConsecutiveRegisters(
597 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
598 // We support any array type as "consecutive" block in the parameter
599 // save area. The element type defines the alignment requirement and
600 // whether the argument should go in GPRs, FPRs, or VRs if available.
602 // Note that clang uses this capability both to implement the ELFv2
603 // homogeneous float/vector aggregate ABI, and to avoid having to use
604 // "byval" when passing aggregates that might fully fit in registers.
605 return Ty->isArrayTy();
610 struct ReuseLoadInfo {
614 MachinePointerInfo MPI;
618 const MDNode *Ranges;
620 ReuseLoadInfo() : IsInvariant(false), Alignment(0), Ranges(nullptr) {}
623 bool canReuseLoadAddress(SDValue Op, EVT MemVT, ReuseLoadInfo &RLI,
625 ISD::LoadExtType ET = ISD::NON_EXTLOAD) const;
626 void spliceIntoChain(SDValue ResChain, SDValue NewResChain,
627 SelectionDAG &DAG) const;
629 void LowerFP_TO_INTForReuse(SDValue Op, ReuseLoadInfo &RLI,
630 SelectionDAG &DAG, SDLoc dl) const;
632 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
633 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
636 IsEligibleForTailCallOptimization(SDValue Callee,
637 CallingConv::ID CalleeCC,
639 const SmallVectorImpl<ISD::InputArg> &Ins,
640 SelectionDAG& DAG) const;
642 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
650 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
651 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
652 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
653 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
654 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
655 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
656 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
657 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
658 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
659 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
660 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
661 const PPCSubtarget &Subtarget) const;
662 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
663 const PPCSubtarget &Subtarget) const;
664 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
665 const PPCSubtarget &Subtarget) const;
666 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
667 const PPCSubtarget &Subtarget) const;
668 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
669 const PPCSubtarget &Subtarget) const;
670 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
671 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
672 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
673 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
674 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
675 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
676 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
677 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
678 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
679 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
680 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
681 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
682 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
683 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
684 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
685 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
687 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
688 CallingConv::ID CallConv, bool isVarArg,
689 const SmallVectorImpl<ISD::InputArg> &Ins,
690 SDLoc dl, SelectionDAG &DAG,
691 SmallVectorImpl<SDValue> &InVals) const;
692 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
693 bool isVarArg, bool IsPatchPoint,
695 SmallVector<std::pair<unsigned, SDValue>, 8>
697 SDValue InFlag, SDValue Chain, SDValue CallSeqStart,
699 int SPDiff, unsigned NumBytes,
700 const SmallVectorImpl<ISD::InputArg> &Ins,
701 SmallVectorImpl<SDValue> &InVals,
702 ImmutableCallSite *CS) const;
705 LowerFormalArguments(SDValue Chain,
706 CallingConv::ID CallConv, bool isVarArg,
707 const SmallVectorImpl<ISD::InputArg> &Ins,
708 SDLoc dl, SelectionDAG &DAG,
709 SmallVectorImpl<SDValue> &InVals) const override;
712 LowerCall(TargetLowering::CallLoweringInfo &CLI,
713 SmallVectorImpl<SDValue> &InVals) const override;
716 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
718 const SmallVectorImpl<ISD::OutputArg> &Outs,
719 LLVMContext &Context) const override;
722 LowerReturn(SDValue Chain,
723 CallingConv::ID CallConv, bool isVarArg,
724 const SmallVectorImpl<ISD::OutputArg> &Outs,
725 const SmallVectorImpl<SDValue> &OutVals,
726 SDLoc dl, SelectionDAG &DAG) const override;
729 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
730 SDValue ArgVal, SDLoc dl) const;
733 LowerFormalArguments_Darwin(SDValue Chain,
734 CallingConv::ID CallConv, bool isVarArg,
735 const SmallVectorImpl<ISD::InputArg> &Ins,
736 SDLoc dl, SelectionDAG &DAG,
737 SmallVectorImpl<SDValue> &InVals) const;
739 LowerFormalArguments_64SVR4(SDValue Chain,
740 CallingConv::ID CallConv, bool isVarArg,
741 const SmallVectorImpl<ISD::InputArg> &Ins,
742 SDLoc dl, SelectionDAG &DAG,
743 SmallVectorImpl<SDValue> &InVals) const;
745 LowerFormalArguments_32SVR4(SDValue Chain,
746 CallingConv::ID CallConv, bool isVarArg,
747 const SmallVectorImpl<ISD::InputArg> &Ins,
748 SDLoc dl, SelectionDAG &DAG,
749 SmallVectorImpl<SDValue> &InVals) const;
752 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
753 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
754 SelectionDAG &DAG, SDLoc dl) const;
757 LowerCall_Darwin(SDValue Chain, SDValue Callee,
758 CallingConv::ID CallConv,
759 bool isVarArg, bool isTailCall, bool IsPatchPoint,
760 const SmallVectorImpl<ISD::OutputArg> &Outs,
761 const SmallVectorImpl<SDValue> &OutVals,
762 const SmallVectorImpl<ISD::InputArg> &Ins,
763 SDLoc dl, SelectionDAG &DAG,
764 SmallVectorImpl<SDValue> &InVals,
765 ImmutableCallSite *CS) const;
767 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
768 CallingConv::ID CallConv,
769 bool isVarArg, bool isTailCall, bool IsPatchPoint,
770 const SmallVectorImpl<ISD::OutputArg> &Outs,
771 const SmallVectorImpl<SDValue> &OutVals,
772 const SmallVectorImpl<ISD::InputArg> &Ins,
773 SDLoc dl, SelectionDAG &DAG,
774 SmallVectorImpl<SDValue> &InVals,
775 ImmutableCallSite *CS) const;
777 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
778 bool isVarArg, bool isTailCall, bool IsPatchPoint,
779 const SmallVectorImpl<ISD::OutputArg> &Outs,
780 const SmallVectorImpl<SDValue> &OutVals,
781 const SmallVectorImpl<ISD::InputArg> &Ins,
782 SDLoc dl, SelectionDAG &DAG,
783 SmallVectorImpl<SDValue> &InVals,
784 ImmutableCallSite *CS) const;
786 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
787 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
789 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
790 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
791 SDValue combineFPToIntToFP(SDNode *N, DAGCombinerInfo &DCI) const;
793 SDValue getRsqrtEstimate(SDValue Operand, DAGCombinerInfo &DCI,
794 unsigned &RefinementSteps,
795 bool &UseOneConstNR) const override;
796 SDValue getRecipEstimate(SDValue Operand, DAGCombinerInfo &DCI,
797 unsigned &RefinementSteps) const override;
798 bool combineRepeatedFPDivisors(unsigned NumUsers) const override;
800 CCAssignFn *useFastISelCCs(unsigned Flag) const;
804 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
805 const TargetLibraryInfo *LibInfo);
808 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
809 CCValAssign::LocInfo &LocInfo,
810 ISD::ArgFlagsTy &ArgFlags,
813 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
815 CCValAssign::LocInfo &LocInfo,
816 ISD::ArgFlagsTy &ArgFlags,
819 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
821 CCValAssign::LocInfo &LocInfo,
822 ISD::ArgFlagsTy &ArgFlags,
826 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H