1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// Hi/Lo - These represent the high and low 16-bit parts of a global
65 /// address respectively. These nodes have two operands, the first of
66 /// which must be a TargetGlobalAddress, and the second of which must be a
67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
68 /// though these are usually folded into other nodes.
73 /// The following three target-specific nodes are used for calls through
74 /// function pointers in the 64-bit SVR4 ABI.
76 /// Restore the TOC from the TOC save area of the current stack frame.
77 /// This is basically a hard coded load instruction which additionally
78 /// takes/produces a flag.
81 /// Like a regular LOAD but additionally taking/producing a flag.
84 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
85 /// a hard coded load instruction.
88 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
89 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
90 /// compute an allocation on the stack.
93 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
94 /// at function entry, used for PIC code.
97 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
98 /// shift amounts. These nodes are generated by the multi-precision shift
102 /// CALL - A direct function call.
103 /// CALL_NOP is a call with the special NOP which follows 64-bit
107 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
108 /// MTCTR instruction.
111 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
112 /// BCTRL instruction.
115 /// Return with a flag operand, matched by 'blr'
118 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
119 /// This copies the bits corresponding to the specified CRREG into the
120 /// resultant GPR. Bits corresponding to other CR regs are undefined.
123 // FIXME: Remove these once the ANDI glue bug is fixed:
124 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
125 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
126 /// implement truncation of i32 or i64 to i1.
127 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
129 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
132 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
135 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
136 /// instructions. For lack of better number, we use the opcode number
137 /// encoding for the OPC field to identify the compare. For example, 838
141 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
142 /// altivec VCMP*o instructions. For lack of better number, we use the
143 /// opcode number encoding for the OPC field to identify the compare. For
144 /// example, 838 is VCMPGTSH.
147 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
148 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
149 /// condition register to branch on, OPC is the branch opcode to use (e.g.
150 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
151 /// an optional input flag argument.
154 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
158 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
159 /// towards zero. Used only as part of the long double-to-int
160 /// conversion sequence.
163 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
166 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
167 /// reserve indexed. This is used to implement atomic operations.
170 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
171 /// indexed. This is used to implement atomic operations.
174 /// TC_RETURN - A tail call return.
176 /// operand #1 callee (register or absolute)
177 /// operand #2 stack adjustment
178 /// operand #3 optional in flag
181 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
185 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
189 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
190 /// TLS model, produces an ADDIS8 instruction that adds the GOT
191 /// base to sym\@got\@tprel\@ha.
194 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
195 /// TLS model, produces a LD instruction with base register G8RReg
196 /// and offset sym\@got\@tprel\@l. This completes the addition that
197 /// finds the offset of "sym" relative to the thread pointer.
200 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
201 /// model, produces an ADD instruction that adds the contents of
202 /// G8RReg to the thread pointer. Symbol contains a relocation
203 /// sym\@tls which is to be replaced by the thread pointer and
204 /// identifies to the linker that the instruction is part of a
208 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
209 /// model, produces an ADDIS8 instruction that adds the GOT base
210 /// register to sym\@got\@tlsgd\@ha.
213 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
214 /// model, produces an ADDI8 instruction that adds G8RReg to
215 /// sym\@got\@tlsgd\@l.
218 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
219 /// model, produces a call to __tls_get_addr(sym\@tlsgd).
222 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
223 /// model, produces an ADDIS8 instruction that adds the GOT base
224 /// register to sym\@got\@tlsld\@ha.
227 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
228 /// model, produces an ADDI8 instruction that adds G8RReg to
229 /// sym\@got\@tlsld\@l.
232 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
233 /// model, produces a call to __tls_get_addr(sym\@tlsld).
236 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
237 /// local-dynamic TLS model, produces an ADDIS8 instruction
238 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
239 /// to tie this in place following a copy to %X3 from the result
240 /// of a GET_TLSLD_ADDR.
243 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
244 /// model, produces an ADDI8 instruction that adds G8RReg to
245 /// sym\@got\@dtprel\@l.
248 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
249 /// during instruction selection to optimize a BUILD_VECTOR into
250 /// operations on splats. This is necessary to avoid losing these
251 /// optimizations due to constant folding.
254 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
255 /// operand identifies the operating system entry point.
258 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
259 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
260 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
262 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
264 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
265 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
266 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
270 /// STFIWX - The STFIWX instruction. The first operand is an input token
271 /// chain, then an f64 value to store, then an address to store it to.
274 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
275 /// load which sign-extends from a 32-bit integer value into the
276 /// destination 64-bit register.
279 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
280 /// load which zero-extends from a 32-bit integer value into the
281 /// destination 64-bit register.
284 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
285 /// produces an ADDIS8 instruction that adds the TOC base register to
289 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
290 /// produces a LD instruction with base register G8RReg and offset
291 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
294 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
295 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
296 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
301 /// Define some predicates that are used for node matching.
303 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
304 /// VPKUHUM instruction.
305 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
308 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
309 /// VPKUWUM instruction.
310 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
313 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
314 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
315 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
316 bool isUnary, SelectionDAG &DAG);
318 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
319 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
320 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
321 bool isUnary, SelectionDAG &DAG);
323 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
324 /// amount, otherwise return -1.
325 int isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG);
327 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
328 /// specifies a splat of a single element that is suitable for input to
329 /// VSPLTB/VSPLTH/VSPLTW.
330 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
332 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
334 bool isAllNegativeZeroVector(SDNode *N);
336 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
337 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
338 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
340 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
341 /// formed by using a vspltis[bhw] instruction of the specified element
342 /// size, return the constant being splatted. The ByteSize field indicates
343 /// the number of bytes of each element [124] -> [bhw].
344 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
348 class PPCTargetLowering : public TargetLowering {
349 const PPCSubtarget &Subtarget;
352 explicit PPCTargetLowering(PPCTargetMachine &TM);
354 /// getTargetNodeName() - This method returns the name of a target specific
356 const char *getTargetNodeName(unsigned Opcode) const override;
358 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
360 /// getSetCCResultType - Return the ISD::SETCC ValueType
361 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
363 /// getPreIndexedAddressParts - returns true by value, base pointer and
364 /// offset pointer and addressing mode by reference if the node's address
365 /// can be legally represented as pre-indexed load / store address.
366 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
368 ISD::MemIndexedMode &AM,
369 SelectionDAG &DAG) const override;
371 /// SelectAddressRegReg - Given the specified addressed, check to see if it
372 /// can be represented as an indexed [r+r] operation. Returns false if it
373 /// can be more efficiently represented with [r+imm].
374 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
375 SelectionDAG &DAG) const;
377 /// SelectAddressRegImm - Returns true if the address N can be represented
378 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
379 /// is not better represented as reg+reg. If Aligned is true, only accept
380 /// displacements suitable for STD and friends, i.e. multiples of 4.
381 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
382 SelectionDAG &DAG, bool Aligned) const;
384 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
385 /// represented as an indexed [r+r] operation.
386 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
387 SelectionDAG &DAG) const;
389 Sched::Preference getSchedulingPreference(SDNode *N) const override;
391 /// LowerOperation - Provide custom lowering hooks for some operations.
393 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
395 /// ReplaceNodeResults - Replace the results of node with an illegal result
396 /// type with new values built out of custom code.
398 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
399 SelectionDAG &DAG) const override;
401 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
403 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
405 void computeKnownBitsForTargetNode(const SDValue Op,
408 const SelectionDAG &DAG,
409 unsigned Depth = 0) const override;
412 EmitInstrWithCustomInserter(MachineInstr *MI,
413 MachineBasicBlock *MBB) const override;
414 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
415 MachineBasicBlock *MBB, bool is64Bit,
416 unsigned BinOpcode) const;
417 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
418 MachineBasicBlock *MBB,
419 bool is8bit, unsigned Opcode) const;
421 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
422 MachineBasicBlock *MBB) const;
424 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
425 MachineBasicBlock *MBB) const;
428 getConstraintType(const std::string &Constraint) const override;
430 /// Examine constraint string and operand type and determine a weight value.
431 /// The operand object must already have been set up with the operand type.
432 ConstraintWeight getSingleConstraintMatchWeight(
433 AsmOperandInfo &info, const char *constraint) const override;
435 std::pair<unsigned, const TargetRegisterClass*>
436 getRegForInlineAsmConstraint(const std::string &Constraint,
437 MVT VT) const override;
439 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
440 /// function arguments in the caller parameter area. This is the actual
441 /// alignment, not its logarithm.
442 unsigned getByValTypeAlignment(Type *Ty) const override;
444 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
445 /// vector. If it is invalid, don't add anything to Ops.
446 void LowerAsmOperandForConstraint(SDValue Op,
447 std::string &Constraint,
448 std::vector<SDValue> &Ops,
449 SelectionDAG &DAG) const override;
451 /// isLegalAddressingMode - Return true if the addressing mode represented
452 /// by AM is legal for this target, for a load/store of the specified type.
453 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
455 /// isLegalICmpImmediate - Return true if the specified immediate is legal
456 /// icmp immediate, that is the target has icmp instructions which can
457 /// compare a register against the immediate without having to materialize
458 /// the immediate into a register.
459 bool isLegalICmpImmediate(int64_t Imm) const override;
461 /// isLegalAddImmediate - Return true if the specified immediate is legal
462 /// add immediate, that is the target has add instructions which can
463 /// add a register and the immediate without having to materialize
464 /// the immediate into a register.
465 bool isLegalAddImmediate(int64_t Imm) const override;
467 /// isTruncateFree - Return true if it's free to truncate a value of
468 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
469 /// register X1 to i32 by referencing its sub-register R1.
470 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
471 bool isTruncateFree(EVT VT1, EVT VT2) const override;
473 /// \brief Returns true if it is beneficial to convert a load of a constant
474 /// to just the constant itself.
475 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
476 Type *Ty) const override;
478 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
480 /// getOptimalMemOpType - Returns the target specific optimal type for load
481 /// and store operations as a result of memset, memcpy, and memmove
482 /// lowering. If DstAlign is zero that means it's safe to destination
483 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
484 /// means there isn't a need to check it against alignment requirement,
485 /// probably because the source does not need to be loaded. If 'IsMemset' is
486 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
487 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
488 /// source is constant so it does not need to be loaded.
489 /// It returns EVT::Other if the type should be determined using generic
490 /// target-independent logic.
492 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
493 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
494 MachineFunction &MF) const override;
496 /// Is unaligned memory access allowed for the given type, and is it fast
497 /// relative to software emulation.
498 bool allowsUnalignedMemoryAccesses(EVT VT,
500 bool *Fast = nullptr) const override;
502 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
503 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
504 /// expanded to FMAs when this method returns true, otherwise fmuladd is
505 /// expanded to fmul + fadd.
506 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
508 // Should we expand the build vector with shuffles?
510 shouldExpandBuildVectorWithShuffles(EVT VT,
511 unsigned DefinedValues) const override;
513 /// createFastISel - This method returns a target-specific FastISel object,
514 /// or null if the target does not support "fast" instruction selection.
515 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
516 const TargetLibraryInfo *LibInfo) const override;
519 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
520 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
523 IsEligibleForTailCallOptimization(SDValue Callee,
524 CallingConv::ID CalleeCC,
526 const SmallVectorImpl<ISD::InputArg> &Ins,
527 SelectionDAG& DAG) const;
529 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
537 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
538 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
539 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
540 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
541 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
542 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
543 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
544 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
545 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
546 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
547 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
548 const PPCSubtarget &Subtarget) const;
549 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
550 const PPCSubtarget &Subtarget) const;
551 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
552 const PPCSubtarget &Subtarget) const;
553 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
554 const PPCSubtarget &Subtarget) const;
555 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
556 const PPCSubtarget &Subtarget) const;
557 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
558 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
559 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
560 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
561 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
562 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
563 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
564 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
565 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
566 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
567 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
568 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
569 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
570 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
571 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
572 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
574 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
575 CallingConv::ID CallConv, bool isVarArg,
576 const SmallVectorImpl<ISD::InputArg> &Ins,
577 SDLoc dl, SelectionDAG &DAG,
578 SmallVectorImpl<SDValue> &InVals) const;
579 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
582 SmallVector<std::pair<unsigned, SDValue>, 8>
584 SDValue InFlag, SDValue Chain,
586 int SPDiff, unsigned NumBytes,
587 const SmallVectorImpl<ISD::InputArg> &Ins,
588 SmallVectorImpl<SDValue> &InVals) const;
591 LowerFormalArguments(SDValue Chain,
592 CallingConv::ID CallConv, bool isVarArg,
593 const SmallVectorImpl<ISD::InputArg> &Ins,
594 SDLoc dl, SelectionDAG &DAG,
595 SmallVectorImpl<SDValue> &InVals) const override;
598 LowerCall(TargetLowering::CallLoweringInfo &CLI,
599 SmallVectorImpl<SDValue> &InVals) const override;
602 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
604 const SmallVectorImpl<ISD::OutputArg> &Outs,
605 LLVMContext &Context) const override;
608 LowerReturn(SDValue Chain,
609 CallingConv::ID CallConv, bool isVarArg,
610 const SmallVectorImpl<ISD::OutputArg> &Outs,
611 const SmallVectorImpl<SDValue> &OutVals,
612 SDLoc dl, SelectionDAG &DAG) const override;
615 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
616 SDValue ArgVal, SDLoc dl) const;
619 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
620 unsigned nAltivecParamsAtEnd,
621 unsigned MinReservedArea, bool isPPC64) const;
624 LowerFormalArguments_Darwin(SDValue Chain,
625 CallingConv::ID CallConv, bool isVarArg,
626 const SmallVectorImpl<ISD::InputArg> &Ins,
627 SDLoc dl, SelectionDAG &DAG,
628 SmallVectorImpl<SDValue> &InVals) const;
630 LowerFormalArguments_64SVR4(SDValue Chain,
631 CallingConv::ID CallConv, bool isVarArg,
632 const SmallVectorImpl<ISD::InputArg> &Ins,
633 SDLoc dl, SelectionDAG &DAG,
634 SmallVectorImpl<SDValue> &InVals) const;
636 LowerFormalArguments_32SVR4(SDValue Chain,
637 CallingConv::ID CallConv, bool isVarArg,
638 const SmallVectorImpl<ISD::InputArg> &Ins,
639 SDLoc dl, SelectionDAG &DAG,
640 SmallVectorImpl<SDValue> &InVals) const;
643 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
644 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
645 SelectionDAG &DAG, SDLoc dl) const;
648 LowerCall_Darwin(SDValue Chain, SDValue Callee,
649 CallingConv::ID CallConv,
650 bool isVarArg, bool isTailCall,
651 const SmallVectorImpl<ISD::OutputArg> &Outs,
652 const SmallVectorImpl<SDValue> &OutVals,
653 const SmallVectorImpl<ISD::InputArg> &Ins,
654 SDLoc dl, SelectionDAG &DAG,
655 SmallVectorImpl<SDValue> &InVals) const;
657 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
658 CallingConv::ID CallConv,
659 bool isVarArg, bool isTailCall,
660 const SmallVectorImpl<ISD::OutputArg> &Outs,
661 const SmallVectorImpl<SDValue> &OutVals,
662 const SmallVectorImpl<ISD::InputArg> &Ins,
663 SDLoc dl, SelectionDAG &DAG,
664 SmallVectorImpl<SDValue> &InVals) const;
666 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
667 bool isVarArg, bool isTailCall,
668 const SmallVectorImpl<ISD::OutputArg> &Outs,
669 const SmallVectorImpl<SDValue> &OutVals,
670 const SmallVectorImpl<ISD::InputArg> &Ins,
671 SDLoc dl, SelectionDAG &DAG,
672 SmallVectorImpl<SDValue> &InVals) const;
674 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
675 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
677 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
678 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
679 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
680 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
682 CCAssignFn *useFastISelCCs(unsigned Flag) const;
686 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
687 const TargetLibraryInfo *LibInfo);
690 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
691 CCValAssign::LocInfo &LocInfo,
692 ISD::ArgFlagsTy &ArgFlags,
695 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
697 CCValAssign::LocInfo &LocInfo,
698 ISD::ArgFlagsTy &ArgFlags,
701 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
703 CCValAssign::LocInfo &LocInfo,
704 ISD::ArgFlagsTy &ArgFlags,
708 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H