1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCSubtarget.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
26 // Start the numbering where the builtin ops and target ops leave off.
27 FIRST_NUMBER = ISD::BUILTIN_OP_END,
29 /// FSEL - Traditional three-operand fsel node.
33 /// FCFID - The FCFID instruction, taking an f64 operand and producing
34 /// and f64 value containing the FP representation of the integer that
35 /// was temporarily in the f64 operand.
38 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
39 /// operand, producing an f64 value containing the integer representation
43 /// STFIWX - The STFIWX instruction. The first operand is an input token
44 /// chain, then an f64 value to store, then an address to store it to.
47 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
48 // three v4f32 operands and producing a v4f32 result.
51 /// VPERM - The PPC VPERM Instruction.
55 /// Hi/Lo - These represent the high and low 16-bit parts of a global
56 /// address respectively. These nodes have two operands, the first of
57 /// which must be a TargetGlobalAddress, and the second of which must be a
58 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
59 /// though these are usually folded into other nodes.
64 /// The following three target-specific nodes are used for calls through
65 /// function pointers in the 64-bit SVR4 ABI.
67 /// Restore the TOC from the TOC save area of the current stack frame.
68 /// This is basically a hard coded load instruction which additionally
69 /// takes/produces a flag.
72 /// Like a regular LOAD but additionally taking/producing a flag.
75 /// LOAD into r2 (also taking/producing a flag). Like TOC_RESTORE, this is
76 /// a hard coded load instruction.
79 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
80 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
81 /// compute an allocation on the stack.
84 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
85 /// at function entry, used for PIC code.
88 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
89 /// shift amounts. These nodes are generated by the multi-precision shift
93 /// EXTSW_32 - This is the EXTSW instruction for use with "32-bit"
97 /// CALL - A direct function call.
98 /// CALL_NOP_SVR4 is a call with the special NOP which follows 64-bit
100 CALL_Darwin, CALL_SVR4, CALL_NOP_SVR4,
102 /// NOP - Special NOP which follows 64-bit SVR4 calls.
105 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
106 /// MTCTR instruction.
109 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
110 /// BCTRL instruction.
111 BCTRL_Darwin, BCTRL_SVR4,
113 /// Return with a flag operand, matched by 'blr'
116 /// R32 = MFCR(CRREG, INFLAG) - Represents the MFCRpseud/MFOCRF
117 /// instructions. This copies the bits corresponding to the specified
118 /// CRREG into the resultant GPR. Bits corresponding to other CR regs
122 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
123 /// instructions. For lack of better number, we use the opcode number
124 /// encoding for the OPC field to identify the compare. For example, 838
128 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
129 /// altivec VCMP*o instructions. For lack of better number, we use the
130 /// opcode number encoding for the OPC field to identify the compare. For
131 /// example, 838 is VCMPGTSH.
134 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
135 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
136 /// condition register to branch on, OPC is the branch opcode to use (e.g.
137 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
138 /// an optional input flag argument.
141 // The following 5 instructions are used only as part of the
142 // long double-to-int conversion sequence.
144 /// OUTFLAG = MFFS F8RC - This moves the FPSCR (not modelled) into the
148 /// OUTFLAG = MTFSB0 INFLAG - This clears a bit in the FPSCR.
151 /// OUTFLAG = MTFSB1 INFLAG - This sets a bit in the FPSCR.
154 /// F8RC, OUTFLAG = FADDRTZ F8RC, F8RC, INFLAG - This is an FADD done with
155 /// rounding towards zero. It has flags added so it won't move past the
156 /// FPSCR-setting instructions.
159 /// MTFSF = F8RC, INFLAG - This moves the register into the FPSCR.
162 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
163 /// reserve indexed. This is used to implement atomic operations.
166 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
167 /// indexed. This is used to implement atomic operations.
170 /// TC_RETURN - A tail call return.
172 /// operand #1 callee (register or absolute)
173 /// operand #2 stack adjustment
174 /// operand #3 optional in flag
177 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
181 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
182 /// TLS model, produces an ADDIS8 instruction that adds the GOT
183 /// base to sym@got@tprel@ha.
186 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
187 /// TLS model, produces a LD instruction with base register G8RReg
188 /// and offset sym@got@tprel@l. This completes the addition that
189 /// finds the offset of "sym" relative to the thread pointer.
192 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
193 /// model, produces an ADD instruction that adds the contents of
194 /// G8RReg to the thread pointer. Symbol contains a relocation
195 /// sym@tls which is to be replaced by the thread pointer and
196 /// identifies to the linker that the instruction is part of a
200 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
201 /// model, produces an ADDIS8 instruction that adds the GOT base
202 /// register to sym@got@tlsgd@ha.
205 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
206 /// model, produces an ADDI8 instruction that adds G8RReg to
210 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
211 /// model, produces a call to __tls_get_addr(sym@tlsgd).
214 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
215 /// model, produces an ADDIS8 instruction that adds the GOT base
216 /// register to sym@got@tlsld@ha.
219 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
220 /// model, produces an ADDI8 instruction that adds G8RReg to
224 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
225 /// model, produces a call to __tls_get_addr(sym@tlsld).
228 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
229 /// local-dynamic TLS model, produces an ADDIS8 instruction
230 /// that adds X3 to sym@dtprel@ha. The Chain operand is needed
231 /// to tie this in place following a copy to %X3 from the result
232 /// of a GET_TLSLD_ADDR.
235 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
236 /// model, produces an ADDI8 instruction that adds G8RReg to
237 /// sym@got@dtprel@l.
240 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
241 /// during instruction selection to optimize a BUILD_VECTOR into
242 /// operations on splats. This is necessary to avoid losing these
243 /// optimizations due to constant folding.
246 /// STD_32 - This is the STD instruction for use with "32-bit" registers.
247 STD_32 = ISD::FIRST_TARGET_MEMORY_OPCODE,
249 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
250 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
251 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
255 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
256 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
257 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
261 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium code model, produces
262 /// an ADDIS8 instruction that adds the TOC base register to sym@toc@ha.
265 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium code model, produces a
266 /// LD instruction with base register G8RReg and offset sym@toc@l.
267 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
270 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
271 /// an ADDI8 instruction that adds G8RReg to sym@toc@l.
272 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
277 /// Define some predicates that are used for node matching.
279 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
280 /// VPKUHUM instruction.
281 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
283 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
284 /// VPKUWUM instruction.
285 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary);
287 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
288 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
289 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
292 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
293 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
294 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
297 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
298 /// amount, otherwise return -1.
299 int isVSLDOIShuffleMask(SDNode *N, bool isUnary);
301 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
302 /// specifies a splat of a single element that is suitable for input to
303 /// VSPLTB/VSPLTH/VSPLTW.
304 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
306 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
308 bool isAllNegativeZeroVector(SDNode *N);
310 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
311 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
312 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize);
314 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
315 /// formed by using a vspltis[bhw] instruction of the specified element
316 /// size, return the constant being splatted. The ByteSize field indicates
317 /// the number of bytes of each element [124] -> [bhw].
318 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
321 class PPCTargetLowering : public TargetLowering {
322 const PPCSubtarget &PPCSubTarget;
325 explicit PPCTargetLowering(PPCTargetMachine &TM);
327 /// getTargetNodeName() - This method returns the name of a target specific
329 virtual const char *getTargetNodeName(unsigned Opcode) const;
331 virtual MVT getShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
333 /// getSetCCResultType - Return the ISD::SETCC ValueType
334 virtual EVT getSetCCResultType(EVT VT) const;
336 /// getPreIndexedAddressParts - returns true by value, base pointer and
337 /// offset pointer and addressing mode by reference if the node's address
338 /// can be legally represented as pre-indexed load / store address.
339 virtual bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
341 ISD::MemIndexedMode &AM,
342 SelectionDAG &DAG) const;
344 /// SelectAddressRegReg - Given the specified addressed, check to see if it
345 /// can be represented as an indexed [r+r] operation. Returns false if it
346 /// can be more efficiently represented with [r+imm].
347 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
348 SelectionDAG &DAG) const;
350 /// SelectAddressRegImm - Returns true if the address N can be represented
351 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
352 /// is not better represented as reg+reg.
353 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
354 SelectionDAG &DAG) const;
356 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
357 /// represented as an indexed [r+r] operation.
358 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
359 SelectionDAG &DAG) const;
361 /// SelectAddressRegImmShift - Returns true if the address N can be
362 /// represented by a base register plus a signed 14-bit displacement
363 /// [r+imm*4]. Suitable for use by STD and friends.
364 bool SelectAddressRegImmShift(SDValue N, SDValue &Disp, SDValue &Base,
365 SelectionDAG &DAG) const;
367 Sched::Preference getSchedulingPreference(SDNode *N) const;
369 /// LowerOperation - Provide custom lowering hooks for some operations.
371 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
373 /// ReplaceNodeResults - Replace the results of node with an illegal result
374 /// type with new values built out of custom code.
376 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
377 SelectionDAG &DAG) const;
379 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
381 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
384 const SelectionDAG &DAG,
385 unsigned Depth = 0) const;
387 virtual MachineBasicBlock *
388 EmitInstrWithCustomInserter(MachineInstr *MI,
389 MachineBasicBlock *MBB) const;
390 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
391 MachineBasicBlock *MBB, bool is64Bit,
392 unsigned BinOpcode) const;
393 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
394 MachineBasicBlock *MBB,
395 bool is8bit, unsigned Opcode) const;
397 ConstraintType getConstraintType(const std::string &Constraint) const;
399 /// Examine constraint string and operand type and determine a weight value.
400 /// The operand object must already have been set up with the operand type.
401 ConstraintWeight getSingleConstraintMatchWeight(
402 AsmOperandInfo &info, const char *constraint) const;
404 std::pair<unsigned, const TargetRegisterClass*>
405 getRegForInlineAsmConstraint(const std::string &Constraint,
408 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
409 /// function arguments in the caller parameter area. This is the actual
410 /// alignment, not its logarithm.
411 unsigned getByValTypeAlignment(Type *Ty) const;
413 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
414 /// vector. If it is invalid, don't add anything to Ops.
415 virtual void LowerAsmOperandForConstraint(SDValue Op,
416 std::string &Constraint,
417 std::vector<SDValue> &Ops,
418 SelectionDAG &DAG) const;
420 /// isLegalAddressingMode - Return true if the addressing mode represented
421 /// by AM is legal for this target, for a load/store of the specified type.
422 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
424 /// isLegalAddressImmediate - Return true if the integer value can be used
425 /// as the offset of the target addressing mode for load / store of the
427 virtual bool isLegalAddressImmediate(int64_t V, Type *Ty) const;
429 /// isLegalAddressImmediate - Return true if the GlobalValue can be used as
430 /// the offset of the target addressing mode.
431 virtual bool isLegalAddressImmediate(GlobalValue *GV) const;
433 virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const;
435 /// getOptimalMemOpType - Returns the target specific optimal type for load
436 /// and store operations as a result of memset, memcpy, and memmove
437 /// lowering. If DstAlign is zero that means it's safe to destination
438 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
439 /// means there isn't a need to check it against alignment requirement,
440 /// probably because the source does not need to be loaded. If 'IsMemset' is
441 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
442 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
443 /// source is constant so it does not need to be loaded.
444 /// It returns EVT::Other if the type should be determined using generic
445 /// target-independent logic.
447 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
448 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
449 MachineFunction &MF) const;
451 /// isFMAFasterThanMulAndAdd - Return true if an FMA operation is faster than
452 /// a pair of mul and add instructions. fmuladd intrinsics will be expanded to
453 /// FMAs when this method returns true (and FMAs are legal), otherwise fmuladd
454 /// is expanded to mul + add.
455 virtual bool isFMAFasterThanMulAndAdd(EVT VT) const;
458 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
459 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
462 IsEligibleForTailCallOptimization(SDValue Callee,
463 CallingConv::ID CalleeCC,
465 const SmallVectorImpl<ISD::InputArg> &Ins,
466 SelectionDAG& DAG) const;
468 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
476 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
477 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
478 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
479 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
480 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
481 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
482 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
483 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
484 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
485 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
486 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
487 const PPCSubtarget &Subtarget) const;
488 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
489 const PPCSubtarget &Subtarget) const;
490 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
491 const PPCSubtarget &Subtarget) const;
492 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
493 const PPCSubtarget &Subtarget) const;
494 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
495 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, DebugLoc dl) const;
496 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
497 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
498 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
499 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
500 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
503 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
504 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
505 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
507 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
508 CallingConv::ID CallConv, bool isVarArg,
509 const SmallVectorImpl<ISD::InputArg> &Ins,
510 DebugLoc dl, SelectionDAG &DAG,
511 SmallVectorImpl<SDValue> &InVals) const;
512 SDValue FinishCall(CallingConv::ID CallConv, DebugLoc dl, bool isTailCall,
515 SmallVector<std::pair<unsigned, SDValue>, 8>
517 SDValue InFlag, SDValue Chain,
519 int SPDiff, unsigned NumBytes,
520 const SmallVectorImpl<ISD::InputArg> &Ins,
521 SmallVectorImpl<SDValue> &InVals) const;
524 LowerFormalArguments(SDValue Chain,
525 CallingConv::ID CallConv, bool isVarArg,
526 const SmallVectorImpl<ISD::InputArg> &Ins,
527 DebugLoc dl, SelectionDAG &DAG,
528 SmallVectorImpl<SDValue> &InVals) const;
531 LowerCall(TargetLowering::CallLoweringInfo &CLI,
532 SmallVectorImpl<SDValue> &InVals) const;
535 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
537 const SmallVectorImpl<ISD::OutputArg> &Outs,
538 LLVMContext &Context) const;
541 LowerReturn(SDValue Chain,
542 CallingConv::ID CallConv, bool isVarArg,
543 const SmallVectorImpl<ISD::OutputArg> &Outs,
544 const SmallVectorImpl<SDValue> &OutVals,
545 DebugLoc dl, SelectionDAG &DAG) const;
548 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
549 SDValue ArgVal, DebugLoc dl) const;
552 setMinReservedArea(MachineFunction &MF, SelectionDAG &DAG,
553 unsigned nAltivecParamsAtEnd,
554 unsigned MinReservedArea, bool isPPC64) const;
557 LowerFormalArguments_Darwin(SDValue Chain,
558 CallingConv::ID CallConv, bool isVarArg,
559 const SmallVectorImpl<ISD::InputArg> &Ins,
560 DebugLoc dl, SelectionDAG &DAG,
561 SmallVectorImpl<SDValue> &InVals) const;
563 LowerFormalArguments_64SVR4(SDValue Chain,
564 CallingConv::ID CallConv, bool isVarArg,
565 const SmallVectorImpl<ISD::InputArg> &Ins,
566 DebugLoc dl, SelectionDAG &DAG,
567 SmallVectorImpl<SDValue> &InVals) const;
569 LowerFormalArguments_32SVR4(SDValue Chain,
570 CallingConv::ID CallConv, bool isVarArg,
571 const SmallVectorImpl<ISD::InputArg> &Ins,
572 DebugLoc dl, SelectionDAG &DAG,
573 SmallVectorImpl<SDValue> &InVals) const;
576 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
577 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
578 SelectionDAG &DAG, DebugLoc dl) const;
581 LowerCall_Darwin(SDValue Chain, SDValue Callee,
582 CallingConv::ID CallConv,
583 bool isVarArg, bool isTailCall,
584 const SmallVectorImpl<ISD::OutputArg> &Outs,
585 const SmallVectorImpl<SDValue> &OutVals,
586 const SmallVectorImpl<ISD::InputArg> &Ins,
587 DebugLoc dl, SelectionDAG &DAG,
588 SmallVectorImpl<SDValue> &InVals) const;
590 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
591 CallingConv::ID CallConv,
592 bool isVarArg, bool isTailCall,
593 const SmallVectorImpl<ISD::OutputArg> &Outs,
594 const SmallVectorImpl<SDValue> &OutVals,
595 const SmallVectorImpl<ISD::InputArg> &Ins,
596 DebugLoc dl, SelectionDAG &DAG,
597 SmallVectorImpl<SDValue> &InVals) const;
599 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
600 bool isVarArg, bool isTailCall,
601 const SmallVectorImpl<ISD::OutputArg> &Outs,
602 const SmallVectorImpl<SDValue> &OutVals,
603 const SmallVectorImpl<ISD::InputArg> &Ins,
604 DebugLoc dl, SelectionDAG &DAG,
605 SmallVectorImpl<SDValue> &InVals) const;
609 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H