1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
18 #include "llvm/Target/TargetLowering.h"
19 #include "llvm/CodeGen/SelectionDAG.h"
25 // Start the numbering where the builting ops and target ops leave off.
26 FIRST_NUMBER = ISD::BUILTIN_OP_END+PPC::INSTRUCTION_LIST_END,
28 /// FSEL - Traditional three-operand fsel node.
32 /// FCFID - The FCFID instruction, taking an f64 operand and producing
33 /// and f64 value containing the FP representation of the integer that
34 /// was temporarily in the f64 operand.
37 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
38 /// operand, producing an f64 value containing the integer representation
42 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
43 // three v4f32 operands and producing a v4f32 result.
46 /// Hi/Lo - These represent the high and low 16-bit parts of a global
47 /// address respectively. These nodes have two operands, the first of
48 /// which must be a TargetGlobalAddress, and the second of which must be a
49 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
50 /// though these are usually folded into other nodes.
53 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
54 /// at function entry, used for PIC code.
57 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
58 /// shift amounts. These nodes are generated by the multi-precision shift
62 /// CALL - A function call.
65 /// Return with a flag operand, matched by 'blr'
70 class PPCTargetLowering : public TargetLowering {
71 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
72 int ReturnAddrIndex; // FrameIndex for return slot.
74 PPCTargetLowering(TargetMachine &TM);
76 /// getTargetNodeName() - This method returns the name of a target specific
78 virtual const char *getTargetNodeName(unsigned Opcode) const;
80 /// LowerOperation - Provide custom lowering hooks for some operations.
82 virtual SDOperand LowerOperation(SDOperand Op, SelectionDAG &DAG);
84 /// LowerArguments - This hook must be implemented to indicate how we should
85 /// lower the arguments for the specified function, into the specified DAG.
86 virtual std::vector<SDOperand>
87 LowerArguments(Function &F, SelectionDAG &DAG);
89 /// LowerCallTo - This hook lowers an abstract call to a function into an
91 virtual std::pair<SDOperand, SDOperand>
92 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
94 bool isTailCall, SDOperand Callee, ArgListTy &Args,
97 virtual MachineBasicBlock *InsertAtEndOfBasicBlock(MachineInstr *MI,
98 MachineBasicBlock *MBB);
100 std::vector<unsigned>
101 getRegForInlineAsmConstraint(const std::string &Constraint) const;
106 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H