1 //===-- PPCISelLowering.h - PPC32 DAG Lowering Interface --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that PPC uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
16 #define LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H
19 #include "PPCInstrInfo.h"
20 #include "PPCRegisterInfo.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/SelectionDAG.h"
23 #include "llvm/Target/TargetLowering.h"
28 // Start the numbering where the builtin ops and target ops leave off.
29 FIRST_NUMBER = ISD::BUILTIN_OP_END,
31 /// FSEL - Traditional three-operand fsel node.
35 /// FCFID - The FCFID instruction, taking an f64 operand and producing
36 /// and f64 value containing the FP representation of the integer that
37 /// was temporarily in the f64 operand.
40 /// Newer FCFID[US] integer-to-floating-point conversion instructions for
41 /// unsigned integers and single-precision outputs.
42 FCFIDU, FCFIDS, FCFIDUS,
44 /// FCTI[D,W]Z - The FCTIDZ and FCTIWZ instructions, taking an f32 or f64
45 /// operand, producing an f64 value containing the integer representation
49 /// Newer FCTI[D,W]UZ floating-point-to-integer conversion instructions for
50 /// unsigned integers.
53 /// Reciprocal estimate instructions (unary FP ops).
56 // VMADDFP, VNMSUBFP - The VMADDFP and VNMSUBFP instructions, taking
57 // three v4f32 operands and producing a v4f32 result.
60 /// VPERM - The PPC VPERM Instruction.
64 /// Hi/Lo - These represent the high and low 16-bit parts of a global
65 /// address respectively. These nodes have two operands, the first of
66 /// which must be a TargetGlobalAddress, and the second of which must be a
67 /// Constant. Selected naively, these turn into 'lis G+C' and 'li G+C',
68 /// though these are usually folded into other nodes.
73 /// The following two target-specific nodes are used for calls through
74 /// function pointers in the 64-bit SVR4 ABI.
76 /// Like a regular LOAD but additionally taking/producing a flag.
79 /// Like LOAD (taking/producing a flag), but using r2 as hard-coded
83 /// OPRC, CHAIN = DYNALLOC(CHAIN, NEGSIZE, FRAME_INDEX)
84 /// This instruction is lowered in PPCRegisterInfo::eliminateFrameIndex to
85 /// compute an allocation on the stack.
88 /// GlobalBaseReg - On Darwin, this node represents the result of the mflr
89 /// at function entry, used for PIC code.
92 /// These nodes represent the 32-bit PPC shifts that operate on 6-bit
93 /// shift amounts. These nodes are generated by the multi-precision shift
97 /// CALL - A direct function call.
98 /// CALL_NOP is a call with the special NOP which follows 64-bit
102 /// CHAIN,FLAG = MTCTR(VAL, CHAIN[, INFLAG]) - Directly corresponds to a
103 /// MTCTR instruction.
106 /// CHAIN,FLAG = BCTRL(CHAIN, INFLAG) - Directly corresponds to a
107 /// BCTRL instruction.
110 /// Return with a flag operand, matched by 'blr'
113 /// R32 = MFOCRF(CRREG, INFLAG) - Represents the MFOCRF instruction.
114 /// This copies the bits corresponding to the specified CRREG into the
115 /// resultant GPR. Bits corresponding to other CR regs are undefined.
118 // FIXME: Remove these once the ANDI glue bug is fixed:
119 /// i1 = ANDIo_1_[EQ|GT]_BIT(i32 or i64 x) - Represents the result of the
120 /// eq or gt bit of CR0 after executing andi. x, 1. This is used to
121 /// implement truncation of i32 or i64 to i1.
122 ANDIo_1_EQ_BIT, ANDIo_1_GT_BIT,
124 // EH_SJLJ_SETJMP - SjLj exception handling setjmp.
127 // EH_SJLJ_LONGJMP - SjLj exception handling longjmp.
130 /// RESVEC = VCMP(LHS, RHS, OPC) - Represents one of the altivec VCMP*
131 /// instructions. For lack of better number, we use the opcode number
132 /// encoding for the OPC field to identify the compare. For example, 838
136 /// RESVEC, OUTFLAG = VCMPo(LHS, RHS, OPC) - Represents one of the
137 /// altivec VCMP*o instructions. For lack of better number, we use the
138 /// opcode number encoding for the OPC field to identify the compare. For
139 /// example, 838 is VCMPGTSH.
142 /// CHAIN = COND_BRANCH CHAIN, CRRC, OPC, DESTBB [, INFLAG] - This
143 /// corresponds to the COND_BRANCH pseudo instruction. CRRC is the
144 /// condition register to branch on, OPC is the branch opcode to use (e.g.
145 /// PPC::BLE), DESTBB is the destination block to branch to, and INFLAG is
146 /// an optional input flag argument.
149 /// CHAIN = BDNZ CHAIN, DESTBB - These are used to create counter-based
153 /// F8RC = FADDRTZ F8RC, F8RC - This is an FADD done with rounding
154 /// towards zero. Used only as part of the long double-to-int
155 /// conversion sequence.
158 /// F8RC = MFFS - This moves the FPSCR (not modeled) into the register.
161 /// LARX = This corresponds to PPC l{w|d}arx instrcution: load and
162 /// reserve indexed. This is used to implement atomic operations.
165 /// STCX = This corresponds to PPC stcx. instrcution: store conditional
166 /// indexed. This is used to implement atomic operations.
169 /// TC_RETURN - A tail call return.
171 /// operand #1 callee (register or absolute)
172 /// operand #2 stack adjustment
173 /// operand #3 optional in flag
176 /// ch, gl = CR6[UN]SET ch, inglue - Toggle CR bit 6 for SVR4 vararg calls
180 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by initial-exec TLS
184 /// GPRC = address of _GLOBAL_OFFSET_TABLE_. Used by general dynamic and
185 /// local dynamic TLS on PPC32.
188 /// G8RC = ADDIS_GOT_TPREL_HA %X2, Symbol - Used by the initial-exec
189 /// TLS model, produces an ADDIS8 instruction that adds the GOT
190 /// base to sym\@got\@tprel\@ha.
193 /// G8RC = LD_GOT_TPREL_L Symbol, G8RReg - Used by the initial-exec
194 /// TLS model, produces a LD instruction with base register G8RReg
195 /// and offset sym\@got\@tprel\@l. This completes the addition that
196 /// finds the offset of "sym" relative to the thread pointer.
199 /// G8RC = ADD_TLS G8RReg, Symbol - Used by the initial-exec TLS
200 /// model, produces an ADD instruction that adds the contents of
201 /// G8RReg to the thread pointer. Symbol contains a relocation
202 /// sym\@tls which is to be replaced by the thread pointer and
203 /// identifies to the linker that the instruction is part of a
207 /// G8RC = ADDIS_TLSGD_HA %X2, Symbol - For the general-dynamic TLS
208 /// model, produces an ADDIS8 instruction that adds the GOT base
209 /// register to sym\@got\@tlsgd\@ha.
212 /// G8RC = ADDI_TLSGD_L G8RReg, Symbol - For the general-dynamic TLS
213 /// model, produces an ADDI8 instruction that adds G8RReg to
214 /// sym\@got\@tlsgd\@l.
217 /// G8RC = GET_TLS_ADDR %X3, Symbol - For the general-dynamic TLS
218 /// model, produces a call to __tls_get_addr(sym\@tlsgd).
221 /// G8RC = ADDIS_TLSLD_HA %X2, Symbol - For the local-dynamic TLS
222 /// model, produces an ADDIS8 instruction that adds the GOT base
223 /// register to sym\@got\@tlsld\@ha.
226 /// G8RC = ADDI_TLSLD_L G8RReg, Symbol - For the local-dynamic TLS
227 /// model, produces an ADDI8 instruction that adds G8RReg to
228 /// sym\@got\@tlsld\@l.
231 /// G8RC = GET_TLSLD_ADDR %X3, Symbol - For the local-dynamic TLS
232 /// model, produces a call to __tls_get_addr(sym\@tlsld).
235 /// G8RC = ADDIS_DTPREL_HA %X3, Symbol, Chain - For the
236 /// local-dynamic TLS model, produces an ADDIS8 instruction
237 /// that adds X3 to sym\@dtprel\@ha. The Chain operand is needed
238 /// to tie this in place following a copy to %X3 from the result
239 /// of a GET_TLSLD_ADDR.
242 /// G8RC = ADDI_DTPREL_L G8RReg, Symbol - For the local-dynamic TLS
243 /// model, produces an ADDI8 instruction that adds G8RReg to
244 /// sym\@got\@dtprel\@l.
247 /// VRRC = VADD_SPLAT Elt, EltSize - Temporary node to be expanded
248 /// during instruction selection to optimize a BUILD_VECTOR into
249 /// operations on splats. This is necessary to avoid losing these
250 /// optimizations due to constant folding.
253 /// CHAIN = SC CHAIN, Imm128 - System call. The 7-bit unsigned
254 /// operand identifies the operating system entry point.
257 /// CHAIN = STBRX CHAIN, GPRC, Ptr, Type - This is a
258 /// byte-swapping store instruction. It byte-swaps the low "Type" bits of
259 /// the GPRC input, then stores it through Ptr. Type can be either i16 or
261 STBRX = ISD::FIRST_TARGET_MEMORY_OPCODE,
263 /// GPRC, CHAIN = LBRX CHAIN, Ptr, Type - This is a
264 /// byte-swapping load instruction. It loads "Type" bits, byte swaps it,
265 /// then puts it in the bottom bits of the GPRC. TYPE can be either i16
269 /// STFIWX - The STFIWX instruction. The first operand is an input token
270 /// chain, then an f64 value to store, then an address to store it to.
273 /// GPRC, CHAIN = LFIWAX CHAIN, Ptr - This is a floating-point
274 /// load which sign-extends from a 32-bit integer value into the
275 /// destination 64-bit register.
278 /// GPRC, CHAIN = LFIWZX CHAIN, Ptr - This is a floating-point
279 /// load which zero-extends from a 32-bit integer value into the
280 /// destination 64-bit register.
283 /// G8RC = ADDIS_TOC_HA %X2, Symbol - For medium and large code model,
284 /// produces an ADDIS8 instruction that adds the TOC base register to
288 /// G8RC = LD_TOC_L Symbol, G8RReg - For medium and large code model,
289 /// produces a LD instruction with base register G8RReg and offset
290 /// sym\@toc\@l. Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
293 /// G8RC = ADDI_TOC_L G8RReg, Symbol - For medium code model, produces
294 /// an ADDI8 instruction that adds G8RReg to sym\@toc\@l.
295 /// Preceded by an ADDIS_TOC_HA to form a full 32-bit offset.
300 /// Define some predicates that are used for node matching.
302 /// isVPKUHUMShuffleMask - Return true if this is the shuffle mask for a
303 /// VPKUHUM instruction.
304 bool isVPKUHUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
307 /// isVPKUWUMShuffleMask - Return true if this is the shuffle mask for a
308 /// VPKUWUM instruction.
309 bool isVPKUWUMShuffleMask(ShuffleVectorSDNode *N, bool isUnary,
312 /// isVMRGLShuffleMask - Return true if this is a shuffle mask suitable for
313 /// a VRGL* instruction with the specified unit size (1,2 or 4 bytes).
314 bool isVMRGLShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
315 unsigned ShuffleKind, SelectionDAG &DAG);
317 /// isVMRGHShuffleMask - Return true if this is a shuffle mask suitable for
318 /// a VRGH* instruction with the specified unit size (1,2 or 4 bytes).
319 bool isVMRGHShuffleMask(ShuffleVectorSDNode *N, unsigned UnitSize,
320 unsigned ShuffleKind, SelectionDAG &DAG);
322 /// isVSLDOIShuffleMask - If this is a vsldoi shuffle mask, return the shift
323 /// amount, otherwise return -1.
324 int isVSLDOIShuffleMask(SDNode *N, bool isUnary, SelectionDAG &DAG);
326 /// isSplatShuffleMask - Return true if the specified VECTOR_SHUFFLE operand
327 /// specifies a splat of a single element that is suitable for input to
328 /// VSPLTB/VSPLTH/VSPLTW.
329 bool isSplatShuffleMask(ShuffleVectorSDNode *N, unsigned EltSize);
331 /// isAllNegativeZeroVector - Returns true if all elements of build_vector
333 bool isAllNegativeZeroVector(SDNode *N);
335 /// getVSPLTImmediate - Return the appropriate VSPLT* immediate to splat the
336 /// specified isSplatShuffleMask VECTOR_SHUFFLE mask.
337 unsigned getVSPLTImmediate(SDNode *N, unsigned EltSize, SelectionDAG &DAG);
339 /// get_VSPLTI_elt - If this is a build_vector of constants which can be
340 /// formed by using a vspltis[bhw] instruction of the specified element
341 /// size, return the constant being splatted. The ByteSize field indicates
342 /// the number of bytes of each element [124] -> [bhw].
343 SDValue get_VSPLTI_elt(SDNode *N, unsigned ByteSize, SelectionDAG &DAG);
347 class PPCTargetLowering : public TargetLowering {
348 const PPCSubtarget &Subtarget;
351 explicit PPCTargetLowering(PPCTargetMachine &TM);
353 /// getTargetNodeName() - This method returns the name of a target specific
355 const char *getTargetNodeName(unsigned Opcode) const override;
357 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i32; }
359 /// getSetCCResultType - Return the ISD::SETCC ValueType
360 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
362 /// getPreIndexedAddressParts - returns true by value, base pointer and
363 /// offset pointer and addressing mode by reference if the node's address
364 /// can be legally represented as pre-indexed load / store address.
365 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base,
367 ISD::MemIndexedMode &AM,
368 SelectionDAG &DAG) const override;
370 /// SelectAddressRegReg - Given the specified addressed, check to see if it
371 /// can be represented as an indexed [r+r] operation. Returns false if it
372 /// can be more efficiently represented with [r+imm].
373 bool SelectAddressRegReg(SDValue N, SDValue &Base, SDValue &Index,
374 SelectionDAG &DAG) const;
376 /// SelectAddressRegImm - Returns true if the address N can be represented
377 /// by a base register plus a signed 16-bit displacement [r+imm], and if it
378 /// is not better represented as reg+reg. If Aligned is true, only accept
379 /// displacements suitable for STD and friends, i.e. multiples of 4.
380 bool SelectAddressRegImm(SDValue N, SDValue &Disp, SDValue &Base,
381 SelectionDAG &DAG, bool Aligned) const;
383 /// SelectAddressRegRegOnly - Given the specified addressed, force it to be
384 /// represented as an indexed [r+r] operation.
385 bool SelectAddressRegRegOnly(SDValue N, SDValue &Base, SDValue &Index,
386 SelectionDAG &DAG) const;
388 Sched::Preference getSchedulingPreference(SDNode *N) const override;
390 /// LowerOperation - Provide custom lowering hooks for some operations.
392 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
394 /// ReplaceNodeResults - Replace the results of node with an illegal result
395 /// type with new values built out of custom code.
397 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
398 SelectionDAG &DAG) const override;
400 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
402 unsigned getRegisterByName(const char* RegName, EVT VT) const override;
404 void computeKnownBitsForTargetNode(const SDValue Op,
407 const SelectionDAG &DAG,
408 unsigned Depth = 0) const override;
411 EmitInstrWithCustomInserter(MachineInstr *MI,
412 MachineBasicBlock *MBB) const override;
413 MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
414 MachineBasicBlock *MBB, bool is64Bit,
415 unsigned BinOpcode) const;
416 MachineBasicBlock *EmitPartwordAtomicBinary(MachineInstr *MI,
417 MachineBasicBlock *MBB,
418 bool is8bit, unsigned Opcode) const;
420 MachineBasicBlock *emitEHSjLjSetJmp(MachineInstr *MI,
421 MachineBasicBlock *MBB) const;
423 MachineBasicBlock *emitEHSjLjLongJmp(MachineInstr *MI,
424 MachineBasicBlock *MBB) const;
427 getConstraintType(const std::string &Constraint) const override;
429 /// Examine constraint string and operand type and determine a weight value.
430 /// The operand object must already have been set up with the operand type.
431 ConstraintWeight getSingleConstraintMatchWeight(
432 AsmOperandInfo &info, const char *constraint) const override;
434 std::pair<unsigned, const TargetRegisterClass*>
435 getRegForInlineAsmConstraint(const std::string &Constraint,
436 MVT VT) const override;
438 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
439 /// function arguments in the caller parameter area. This is the actual
440 /// alignment, not its logarithm.
441 unsigned getByValTypeAlignment(Type *Ty) const override;
443 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
444 /// vector. If it is invalid, don't add anything to Ops.
445 void LowerAsmOperandForConstraint(SDValue Op,
446 std::string &Constraint,
447 std::vector<SDValue> &Ops,
448 SelectionDAG &DAG) const override;
450 /// isLegalAddressingMode - Return true if the addressing mode represented
451 /// by AM is legal for this target, for a load/store of the specified type.
452 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
454 /// isLegalICmpImmediate - Return true if the specified immediate is legal
455 /// icmp immediate, that is the target has icmp instructions which can
456 /// compare a register against the immediate without having to materialize
457 /// the immediate into a register.
458 bool isLegalICmpImmediate(int64_t Imm) const override;
460 /// isLegalAddImmediate - Return true if the specified immediate is legal
461 /// add immediate, that is the target has add instructions which can
462 /// add a register and the immediate without having to materialize
463 /// the immediate into a register.
464 bool isLegalAddImmediate(int64_t Imm) const override;
466 /// isTruncateFree - Return true if it's free to truncate a value of
467 /// type Ty1 to type Ty2. e.g. On PPC it's free to truncate a i64 value in
468 /// register X1 to i32 by referencing its sub-register R1.
469 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
470 bool isTruncateFree(EVT VT1, EVT VT2) const override;
472 /// \brief Returns true if it is beneficial to convert a load of a constant
473 /// to just the constant itself.
474 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
475 Type *Ty) const override;
477 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
479 /// getOptimalMemOpType - Returns the target specific optimal type for load
480 /// and store operations as a result of memset, memcpy, and memmove
481 /// lowering. If DstAlign is zero that means it's safe to destination
482 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it
483 /// means there isn't a need to check it against alignment requirement,
484 /// probably because the source does not need to be loaded. If 'IsMemset' is
485 /// true, that means it's expanding a memset. If 'ZeroMemset' is true, that
486 /// means it's a memset of zero. 'MemcpyStrSrc' indicates whether the memcpy
487 /// source is constant so it does not need to be loaded.
488 /// It returns EVT::Other if the type should be determined using generic
489 /// target-independent logic.
491 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
492 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
493 MachineFunction &MF) const override;
495 /// Is unaligned memory access allowed for the given type, and is it fast
496 /// relative to software emulation.
497 bool allowsUnalignedMemoryAccesses(EVT VT,
499 bool *Fast = nullptr) const override;
501 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
502 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
503 /// expanded to FMAs when this method returns true, otherwise fmuladd is
504 /// expanded to fmul + fadd.
505 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
507 // Should we expand the build vector with shuffles?
509 shouldExpandBuildVectorWithShuffles(EVT VT,
510 unsigned DefinedValues) const override;
512 /// createFastISel - This method returns a target-specific FastISel object,
513 /// or null if the target does not support "fast" instruction selection.
514 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
515 const TargetLibraryInfo *LibInfo) const override;
517 /// \brief Returns true if an argument of type Ty needs to be passed in a
518 /// contiguous block of registers in calling convention CallConv.
519 bool functionArgumentNeedsConsecutiveRegisters(
520 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override {
521 // We support any array type as "consecutive" block in the parameter
522 // save area. The element type defines the alignment requirement and
523 // whether the argument should go in GPRs, FPRs, or VRs if available.
525 // Note that clang uses this capability both to implement the ELFv2
526 // homogeneous float/vector aggregate ABI, and to avoid having to use
527 // "byval" when passing aggregates that might fully fit in registers.
528 return Ty->isArrayTy();
532 SDValue getFramePointerFrameIndex(SelectionDAG & DAG) const;
533 SDValue getReturnAddrFrameIndex(SelectionDAG & DAG) const;
536 IsEligibleForTailCallOptimization(SDValue Callee,
537 CallingConv::ID CalleeCC,
539 const SmallVectorImpl<ISD::InputArg> &Ins,
540 SelectionDAG& DAG) const;
542 SDValue EmitTailCallLoadFPAndRetAddr(SelectionDAG & DAG,
550 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
551 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
552 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
553 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
554 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
555 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
556 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
557 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
558 SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
559 SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
560 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG,
561 const PPCSubtarget &Subtarget) const;
562 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG,
563 const PPCSubtarget &Subtarget) const;
564 SDValue LowerVACOPY(SDValue Op, SelectionDAG &DAG,
565 const PPCSubtarget &Subtarget) const;
566 SDValue LowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG,
567 const PPCSubtarget &Subtarget) const;
568 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG,
569 const PPCSubtarget &Subtarget) const;
570 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
571 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
572 SDValue LowerTRUNCATE(SDValue Op, SelectionDAG &DAG) const;
573 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
574 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG, SDLoc dl) const;
575 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
576 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
577 SDValue LowerSHL_PARTS(SDValue Op, SelectionDAG &DAG) const;
578 SDValue LowerSRL_PARTS(SDValue Op, SelectionDAG &DAG) const;
579 SDValue LowerSRA_PARTS(SDValue Op, SelectionDAG &DAG) const;
580 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
581 SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
582 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
583 SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
584 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
585 SDValue LowerMUL(SDValue Op, SelectionDAG &DAG) const;
587 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
588 CallingConv::ID CallConv, bool isVarArg,
589 const SmallVectorImpl<ISD::InputArg> &Ins,
590 SDLoc dl, SelectionDAG &DAG,
591 SmallVectorImpl<SDValue> &InVals) const;
592 SDValue FinishCall(CallingConv::ID CallConv, SDLoc dl, bool isTailCall,
595 SmallVector<std::pair<unsigned, SDValue>, 8>
597 SDValue InFlag, SDValue Chain,
599 int SPDiff, unsigned NumBytes,
600 const SmallVectorImpl<ISD::InputArg> &Ins,
601 SmallVectorImpl<SDValue> &InVals) const;
604 LowerFormalArguments(SDValue Chain,
605 CallingConv::ID CallConv, bool isVarArg,
606 const SmallVectorImpl<ISD::InputArg> &Ins,
607 SDLoc dl, SelectionDAG &DAG,
608 SmallVectorImpl<SDValue> &InVals) const override;
611 LowerCall(TargetLowering::CallLoweringInfo &CLI,
612 SmallVectorImpl<SDValue> &InVals) const override;
615 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
617 const SmallVectorImpl<ISD::OutputArg> &Outs,
618 LLVMContext &Context) const override;
621 LowerReturn(SDValue Chain,
622 CallingConv::ID CallConv, bool isVarArg,
623 const SmallVectorImpl<ISD::OutputArg> &Outs,
624 const SmallVectorImpl<SDValue> &OutVals,
625 SDLoc dl, SelectionDAG &DAG) const override;
628 extendArgForPPC64(ISD::ArgFlagsTy Flags, EVT ObjectVT, SelectionDAG &DAG,
629 SDValue ArgVal, SDLoc dl) const;
632 LowerFormalArguments_Darwin(SDValue Chain,
633 CallingConv::ID CallConv, bool isVarArg,
634 const SmallVectorImpl<ISD::InputArg> &Ins,
635 SDLoc dl, SelectionDAG &DAG,
636 SmallVectorImpl<SDValue> &InVals) const;
638 LowerFormalArguments_64SVR4(SDValue Chain,
639 CallingConv::ID CallConv, bool isVarArg,
640 const SmallVectorImpl<ISD::InputArg> &Ins,
641 SDLoc dl, SelectionDAG &DAG,
642 SmallVectorImpl<SDValue> &InVals) const;
644 LowerFormalArguments_32SVR4(SDValue Chain,
645 CallingConv::ID CallConv, bool isVarArg,
646 const SmallVectorImpl<ISD::InputArg> &Ins,
647 SDLoc dl, SelectionDAG &DAG,
648 SmallVectorImpl<SDValue> &InVals) const;
651 createMemcpyOutsideCallSeq(SDValue Arg, SDValue PtrOff,
652 SDValue CallSeqStart, ISD::ArgFlagsTy Flags,
653 SelectionDAG &DAG, SDLoc dl) const;
656 LowerCall_Darwin(SDValue Chain, SDValue Callee,
657 CallingConv::ID CallConv,
658 bool isVarArg, bool isTailCall,
659 const SmallVectorImpl<ISD::OutputArg> &Outs,
660 const SmallVectorImpl<SDValue> &OutVals,
661 const SmallVectorImpl<ISD::InputArg> &Ins,
662 SDLoc dl, SelectionDAG &DAG,
663 SmallVectorImpl<SDValue> &InVals) const;
665 LowerCall_64SVR4(SDValue Chain, SDValue Callee,
666 CallingConv::ID CallConv,
667 bool isVarArg, bool isTailCall,
668 const SmallVectorImpl<ISD::OutputArg> &Outs,
669 const SmallVectorImpl<SDValue> &OutVals,
670 const SmallVectorImpl<ISD::InputArg> &Ins,
671 SDLoc dl, SelectionDAG &DAG,
672 SmallVectorImpl<SDValue> &InVals) const;
674 LowerCall_32SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
675 bool isVarArg, bool isTailCall,
676 const SmallVectorImpl<ISD::OutputArg> &Outs,
677 const SmallVectorImpl<SDValue> &OutVals,
678 const SmallVectorImpl<ISD::InputArg> &Ins,
679 SDLoc dl, SelectionDAG &DAG,
680 SmallVectorImpl<SDValue> &InVals) const;
682 SDValue lowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
683 SDValue lowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
685 SDValue DAGCombineExtBoolTrunc(SDNode *N, DAGCombinerInfo &DCI) const;
686 SDValue DAGCombineTruncBoolExt(SDNode *N, DAGCombinerInfo &DCI) const;
687 SDValue DAGCombineFastRecip(SDValue Op, DAGCombinerInfo &DCI) const;
688 SDValue DAGCombineFastRecipFSQRT(SDValue Op, DAGCombinerInfo &DCI) const;
690 CCAssignFn *useFastISelCCs(unsigned Flag) const;
694 FastISel *createFastISel(FunctionLoweringInfo &FuncInfo,
695 const TargetLibraryInfo *LibInfo);
698 bool CC_PPC32_SVR4_Custom_Dummy(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
699 CCValAssign::LocInfo &LocInfo,
700 ISD::ArgFlagsTy &ArgFlags,
703 bool CC_PPC32_SVR4_Custom_AlignArgRegs(unsigned &ValNo, MVT &ValVT,
705 CCValAssign::LocInfo &LocInfo,
706 ISD::ArgFlagsTy &ArgFlags,
709 bool CC_PPC32_SVR4_Custom_AlignFPArgRegs(unsigned &ValNo, MVT &ValVT,
711 CCValAssign::LocInfo &LocInfo,
712 ISD::ArgFlagsTy &ArgFlags,
716 #endif // LLVM_TARGET_POWERPC_PPC32ISELLOWERING_H