1 //===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
11 // Magic number generation for integer divide from the PowerPC Compiler Writer's
12 // Guide, section 3.2.3.5
14 //===----------------------------------------------------------------------===//
17 #include "PowerPCInstrBuilder.h"
18 #include "PowerPCInstrInfo.h"
19 #include "PPC32RegisterInfo.h"
20 #include "llvm/Constants.h" // FIXME: REMOVE
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/ADT/Statistic.h"
38 //===----------------------------------------------------------------------===//
39 // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
41 class PPC32TargetLowering : public TargetLowering {
42 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
43 int ReturnAddrIndex; // FrameIndex for return slot.
45 PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Set up the register classes.
47 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
48 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
49 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
51 // PowerPC has no intrinsics for these particular operations
52 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
53 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
54 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
56 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
57 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
58 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
60 // PowerPC has no SREM/UREM instructions
61 setOperationAction(ISD::SREM, MVT::i32, Expand);
62 setOperationAction(ISD::UREM, MVT::i32, Expand);
64 setShiftAmountFlavor(Extend); // shl X, 32 == 0
65 addLegalFPImmediate(+0.0); // Necessary for FSEL
66 addLegalFPImmediate(-0.0); //
68 computeRegisterProperties();
71 /// LowerArguments - This hook must be implemented to indicate how we should
72 /// lower the arguments for the specified function, into the specified DAG.
73 virtual std::vector<SDOperand>
74 LowerArguments(Function &F, SelectionDAG &DAG);
76 /// LowerCallTo - This hook lowers an abstract call to a function into an
78 virtual std::pair<SDOperand, SDOperand>
79 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
80 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
82 virtual std::pair<SDOperand, SDOperand>
83 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
85 virtual std::pair<SDOperand,SDOperand>
86 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
87 const Type *ArgTy, SelectionDAG &DAG);
89 virtual std::pair<SDOperand, SDOperand>
90 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
96 std::vector<SDOperand>
97 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
99 // add beautiful description of PPC stack frame format, or at least some docs
101 MachineFunction &MF = DAG.getMachineFunction();
102 MachineFrameInfo *MFI = MF.getFrameInfo();
103 MachineBasicBlock& BB = MF.front();
104 std::vector<SDOperand> ArgValues;
106 // Due to the rather complicated nature of the PowerPC ABI, rather than a
107 // fixed size array of physical args, for the sake of simplicity let the STL
108 // handle tracking them for us.
109 std::vector<unsigned> argVR, argPR, argOp;
110 unsigned ArgOffset = 24;
111 unsigned GPR_remaining = 8;
112 unsigned FPR_remaining = 13;
113 unsigned GPR_idx = 0, FPR_idx = 0;
114 static const unsigned GPR[] = {
115 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
116 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
118 static const unsigned FPR[] = {
119 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
120 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
123 // Add DAG nodes to load the arguments... On entry to a function on PPC,
124 // the arguments start at offset 24, although they are likely to be passed
126 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
127 SDOperand newroot, argt;
129 bool needsLoad = false;
130 MVT::ValueType ObjectVT = getValueType(I->getType());
133 default: assert(0 && "Unhandled argument type!");
139 if (GPR_remaining > 0) {
140 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
141 argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
143 if (ObjectVT != MVT::i32)
144 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
149 case MVT::i64: ObjSize = 8;
150 // FIXME: can split 64b load between reg/mem if it is last arg in regs
151 if (GPR_remaining > 1) {
152 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
153 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
154 // Copy the extracted halves into the virtual registers
155 SDOperand argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
157 SDOperand argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
158 // Build the outgoing arg thingy
159 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
165 case MVT::f32: ObjSize = 4;
166 case MVT::f64: ObjSize = 8;
167 if (FPR_remaining > 0) {
168 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
169 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
179 // We need to load the argument to a virtual register if we determined above
180 // that we ran out of physical registers of the appropriate type
182 unsigned SubregOffset = 0;
183 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
184 if (ObjectVT == MVT::i16) SubregOffset = 2;
185 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
186 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
187 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
188 DAG.getConstant(SubregOffset, MVT::i32));
189 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
192 // Every 4 bytes of argument space consumes one of the GPRs available for
194 if (GPR_remaining > 0) {
195 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
196 GPR_remaining -= delta;
199 ArgOffset += ObjSize;
201 DAG.setRoot(newroot.getValue(1));
202 ArgValues.push_back(argt);
205 // If the function takes variable number of arguments, make a frame index for
206 // the start of the first vararg value... for expansion of llvm.va_start.
208 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
209 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
210 // If this function is vararg, store any remaining integer argument regs
211 // to their spots on the stack so that they may be loaded by deferencing the
212 // result of va_next.
213 std::vector<SDOperand> MemOps;
214 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
215 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
216 SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
217 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
219 MemOps.push_back(Store);
220 // Increment the address by four for the next argument to store
221 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
222 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
224 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
230 std::pair<SDOperand, SDOperand>
231 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
232 const Type *RetTy, bool isVarArg,
233 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
234 // args_to_use will accumulate outgoing args for the ISD::CALL case in
235 // SelectExpr to use to put the arguments in the appropriate registers.
236 std::vector<SDOperand> args_to_use;
238 // Count how many bytes are to be pushed on the stack, including the linkage
239 // area, and parameter passing area.
240 unsigned NumBytes = 24;
243 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
244 DAG.getConstant(NumBytes, getPointerTy()));
246 for (unsigned i = 0, e = Args.size(); i != e; ++i)
247 switch (getValueType(Args[i].second)) {
248 default: assert(0 && "Unknown value type!");
262 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
263 // plus 32 bytes of argument space in case any called code gets funky on us.
264 if (NumBytes < 56) NumBytes = 56;
266 // Adjust the stack pointer for the new arguments...
267 // These operations are automatically eliminated by the prolog/epilog pass
268 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
269 DAG.getConstant(NumBytes, getPointerTy()));
271 // Set up a copy of the stack pointer for use loading and storing any
272 // arguments that may not fit in the registers available for argument
274 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
277 // Figure out which arguments are going to go in registers, and which in
278 // memory. Also, if this is a vararg function, floating point operations
279 // must be stored to our stack, and loaded into integer regs as well, if
280 // any integer regs are available for argument passing.
281 unsigned ArgOffset = 24;
282 unsigned GPR_remaining = 8;
283 unsigned FPR_remaining = 13;
285 std::vector<SDOperand> MemOps;
286 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
287 // PtrOff will be used to store the current argument to the stack if a
288 // register cannot be found for it.
289 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
290 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
291 MVT::ValueType ArgVT = getValueType(Args[i].second);
294 default: assert(0 && "Unexpected ValueType for argument!");
298 // Promote the integer to 32 bits. If the input type is signed use a
299 // sign extend, otherwise use a zero extend.
300 if (Args[i].second->isSigned())
301 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
303 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
306 if (GPR_remaining > 0) {
307 args_to_use.push_back(Args[i].first);
310 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
311 Args[i].first, PtrOff));
316 // If we have one free GPR left, we can place the upper half of the i64
317 // in it, and store the other half to the stack. If we have two or more
318 // free GPRs, then we can pass both halves of the i64 in registers.
319 if (GPR_remaining > 0) {
320 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
321 Args[i].first, DAG.getConstant(1, MVT::i32));
322 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
323 Args[i].first, DAG.getConstant(0, MVT::i32));
324 args_to_use.push_back(Hi);
326 if (GPR_remaining > 0) {
327 args_to_use.push_back(Lo);
330 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
331 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
332 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
336 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
337 Args[i].first, PtrOff));
343 if (FPR_remaining > 0) {
344 args_to_use.push_back(Args[i].first);
347 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
348 Args[i].first, PtrOff);
349 MemOps.push_back(Store);
350 // Float varargs are always shadowed in available integer registers
351 if (GPR_remaining > 0) {
352 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
353 MemOps.push_back(Load);
354 args_to_use.push_back(Load);
357 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
358 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
359 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
360 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
361 MemOps.push_back(Load);
362 args_to_use.push_back(Load);
366 // If we have any FPRs remaining, we may also have GPRs remaining.
367 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
369 if (GPR_remaining > 0) {
370 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
373 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
374 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
379 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
380 Args[i].first, PtrOff));
382 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
387 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
390 std::vector<MVT::ValueType> RetVals;
391 MVT::ValueType RetTyVT = getValueType(RetTy);
392 if (RetTyVT != MVT::isVoid)
393 RetVals.push_back(RetTyVT);
394 RetVals.push_back(MVT::Other);
396 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
397 Chain, Callee, args_to_use), 0);
398 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
399 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
400 DAG.getConstant(NumBytes, getPointerTy()));
401 return std::make_pair(TheCall, Chain);
404 std::pair<SDOperand, SDOperand>
405 PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
406 //vastart just returns the address of the VarArgsFrameIndex slot.
407 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
410 std::pair<SDOperand,SDOperand> PPC32TargetLowering::
411 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
412 const Type *ArgTy, SelectionDAG &DAG) {
413 MVT::ValueType ArgVT = getValueType(ArgTy);
416 Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
419 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
422 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
423 "Other types should have been promoted for varargs!");
426 Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
427 DAG.getConstant(Amt, VAList.getValueType()));
429 return std::make_pair(Result, Chain);
433 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
434 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
436 assert(0 && "LowerFrameReturnAddress unimplemented");
441 Statistic<>NotLogic("ppc-codegen", "Number of inverted logical ops");
442 Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
443 //===--------------------------------------------------------------------===//
444 /// ISel - PPC32 specific code to select PPC32 machine instructions for
445 /// SelectionDAG operations.
446 //===--------------------------------------------------------------------===//
447 class ISel : public SelectionDAGISel {
448 PPC32TargetLowering PPC32Lowering;
449 SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
450 // for sdiv and udiv until it is put into the future
453 /// ExprMap - As shared expressions are codegen'd, we keep track of which
454 /// vreg the value is produced in, so we only emit one copy of each compiled
456 std::map<SDOperand, unsigned> ExprMap;
458 unsigned GlobalBaseReg;
459 bool GlobalBaseInitialized;
462 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
465 /// runOnFunction - Override this function in order to reset our per-function
467 virtual bool runOnFunction(Function &Fn) {
468 // Make sure we re-emit a set of the global base reg if necessary
469 GlobalBaseInitialized = false;
470 return SelectionDAGISel::runOnFunction(Fn);
473 /// InstructionSelectBasicBlock - This callback is invoked by
474 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
475 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
477 // Codegen the basic block.
479 Select(DAG.getRoot());
481 // Clear state used for selection.
486 // dag -> dag expanders for integer divide by constant
487 SDOperand BuildSDIVSequence(SDOperand N);
488 SDOperand BuildUDIVSequence(SDOperand N);
490 unsigned getGlobalBaseReg();
491 unsigned getConstDouble(double floatVal, unsigned Result);
492 unsigned SelectSetCR0(SDOperand CC);
493 unsigned SelectExpr(SDOperand N);
494 unsigned SelectExprFP(SDOperand N, unsigned Result);
495 void Select(SDOperand N);
497 bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
498 void SelectBranchCC(SDOperand N);
501 /// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
502 /// returns zero when the input is not exactly a power of two.
503 static unsigned ExactLog2(unsigned Val) {
504 if (Val == 0 || (Val & (Val-1))) return 0;
513 /// getImmediateForOpcode - This method returns a value indicating whether
514 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
515 /// values are either 0, 1 or 2. 0 indicates that either N is not a
516 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
517 /// of 1 indicates that the constant may be used in normal immediate form. A
518 /// return value of 2 indicates that the constant may be used in shifted
519 /// immediate form. A return value of 3 indicates that log base 2 of the
520 /// constant may be used. A return value of 4 indicates that the constant is
521 /// suitable for conversion into a magic number for integer division.
523 static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
524 unsigned& Imm, bool U = false) {
525 if (N.getOpcode() != ISD::Constant) return 0;
527 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
532 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
533 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
538 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
539 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
543 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
546 if (U && (v >= 0 && v <= 65535)) { Imm = v & 0xFFFF; return 1; }
547 if (!U && (v <= 32767 && v >= -32768)) { Imm = v & 0xFFFF; return 1; }
550 if ((Imm = ExactLog2(v))) { return 3; }
551 if (v <= -2 || v >= 2) { return 4; }
554 if (v > 1) { return 4; }
560 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
561 /// to Condition. If the Condition is unordered or unsigned, the bool argument
562 /// U is set to true, otherwise it is set to false.
563 static unsigned getBCCForSetCC(unsigned Condition, bool& U) {
566 default: assert(0 && "Unknown condition!"); abort();
567 case ISD::SETEQ: return PPC::BEQ;
568 case ISD::SETNE: return PPC::BNE;
569 case ISD::SETULT: U = true;
570 case ISD::SETLT: return PPC::BLT;
571 case ISD::SETULE: U = true;
572 case ISD::SETLE: return PPC::BLE;
573 case ISD::SETUGT: U = true;
574 case ISD::SETGT: return PPC::BGT;
575 case ISD::SETUGE: U = true;
576 case ISD::SETGE: return PPC::BGE;
581 /// IndexedOpForOp - Return the indexed variant for each of the PowerPC load
582 /// and store immediate instructions.
583 static unsigned IndexedOpForOp(unsigned Opcode) {
585 default: assert(0 && "Unknown opcode!"); abort();
586 case PPC::LBZ: return PPC::LBZX; case PPC::STB: return PPC::STBX;
587 case PPC::LHZ: return PPC::LHZX; case PPC::STH: return PPC::STHX;
588 case PPC::LHA: return PPC::LHAX; case PPC::STW: return PPC::STWX;
589 case PPC::LWZ: return PPC::LWZX; case PPC::STFS: return PPC::STFSX;
590 case PPC::LFS: return PPC::LFSX; case PPC::STFD: return PPC::STFDX;
591 case PPC::LFD: return PPC::LFDX;
596 // Structure used to return the necessary information to codegen an SDIV as
599 int m; // magic number
600 int s; // shift amount
604 unsigned int m; // magic number
605 int a; // add indicator
606 int s; // shift amount
609 /// magic - calculate the magic numbers required to codegen an integer sdiv as
610 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
612 static struct ms magic(int d) {
614 unsigned int ad, anc, delta, q1, r1, q2, r2, t;
615 const unsigned int two31 = 2147483648U; // 2^31
619 t = two31 + ((unsigned int)d >> 31);
620 anc = t - 1 - t%ad; // absolute value of nc
621 p = 31; // initialize p
622 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
623 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
624 q2 = two31/ad; // initialize q2 = 2p/abs(d)
625 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
628 q1 = 2*q1; // update q1 = 2p/abs(nc)
629 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
630 if (r1 >= anc) { // must be unsigned comparison
634 q2 = 2*q2; // update q2 = 2p/abs(d)
635 r2 = 2*r2; // update r2 = rem(2p/abs(d))
636 if (r2 >= ad) { // must be unsigned comparison
641 } while (q1 < delta || (q1 == delta && r1 == 0));
644 if (d < 0) mag.m = -mag.m; // resulting magic number
645 mag.s = p - 32; // resulting shift
649 /// magicu - calculate the magic numbers required to codegen an integer udiv as
650 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
651 static struct mu magicu(unsigned d)
654 unsigned int nc, delta, q1, r1, q2, r2;
656 magu.a = 0; // initialize "add" indicator
658 p = 31; // initialize p
659 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
660 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
661 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
662 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
665 if (r1 >= nc - r1 ) {
666 q1 = 2*q1 + 1; // update q1
667 r1 = 2*r1 - nc; // update r1
670 q1 = 2*q1; // update q1
671 r1 = 2*r1; // update r1
673 if (r2 + 1 >= d - r2) {
674 if (q2 >= 0x7FFFFFFF) magu.a = 1;
675 q2 = 2*q2 + 1; // update q2
676 r2 = 2*r2 + 1 - d; // update r2
679 if (q2 >= 0x80000000) magu.a = 1;
680 q2 = 2*q2; // update q2
681 r2 = 2*r2 + 1; // update r2
684 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
685 magu.m = q2 + 1; // resulting magic number
686 magu.s = p - 32; // resulting shift
691 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
692 /// return a DAG expression to select that will generate the same value by
693 /// multiplying by a magic number. See:
694 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
695 SDOperand ISel::BuildSDIVSequence(SDOperand N) {
696 int d = (int)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
697 ms magics = magic(d);
698 // Multiply the numerator (operand 0) by the magic value
699 SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
700 ISelDAG->getConstant(magics.m, MVT::i32));
701 // If d > 0 and m < 0, add the numerator
702 if (d > 0 && magics.m < 0)
703 Q = ISelDAG->getNode(ISD::ADD, MVT::i32, Q, N.getOperand(0));
704 // If d < 0 and m > 0, subtract the numerator.
705 if (d < 0 && magics.m > 0)
706 Q = ISelDAG->getNode(ISD::SUB, MVT::i32, Q, N.getOperand(0));
707 // Shift right algebraic if shift value is nonzero
709 Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
710 ISelDAG->getConstant(magics.s, MVT::i32));
711 // Extract the sign bit and add it to the quotient
713 ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
714 return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
717 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
718 /// return a DAG expression to select that will generate the same value by
719 /// multiplying by a magic number. See:
720 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
721 SDOperand ISel::BuildUDIVSequence(SDOperand N) {
723 (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
724 mu magics = magicu(d);
725 // Multiply the numerator (operand 0) by the magic value
726 SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
727 ISelDAG->getConstant(magics.m, MVT::i32));
729 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
730 ISelDAG->getConstant(magics.s, MVT::i32));
732 SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), Q);
733 NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
734 ISelDAG->getConstant(1, MVT::i32));
735 NPQ = ISelDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
736 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
737 ISelDAG->getConstant(magics.s-1, MVT::i32));
742 /// getGlobalBaseReg - Output the instructions required to put the
743 /// base address to use for accessing globals into a register.
745 unsigned ISel::getGlobalBaseReg() {
746 if (!GlobalBaseInitialized) {
747 // Insert the set of GlobalBaseReg into the first MBB of the function
748 MachineBasicBlock &FirstMBB = BB->getParent()->front();
749 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
750 GlobalBaseReg = MakeReg(MVT::i32);
751 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
752 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
753 GlobalBaseInitialized = true;
755 return GlobalBaseReg;
758 /// getConstDouble - Loads a floating point value into a register, via the
759 /// Constant Pool. Optionally takes a register in which to load the value.
760 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
761 unsigned Tmp1 = MakeReg(MVT::i32);
762 if (0 == Result) Result = MakeReg(MVT::f64);
763 MachineConstantPool *CP = BB->getParent()->getConstantPool();
764 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
765 unsigned CPI = CP->getConstantPoolIndex(CFP);
766 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
767 .addConstantPoolIndex(CPI);
768 BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
772 unsigned ISel::SelectSetCR0(SDOperand CC) {
773 unsigned Opc, Tmp1, Tmp2;
774 static const unsigned CompareOpcodes[] =
775 { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
777 // If the first operand to the select is a SETCC node, then we can fold it
778 // into the branch that selects which value to return.
779 SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
780 if (SetCC && CC.getOpcode() == ISD::SETCC) {
782 Opc = getBCCForSetCC(SetCC->getCondition(), U);
783 Tmp1 = SelectExpr(SetCC->getOperand(0));
785 // Pass the optional argument U to getImmediateForOpcode for SETCC,
786 // so that it knows whether the SETCC immediate range is signed or not.
787 if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
790 BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
792 BuildMI(BB, PPC::CMPWI, 2, PPC::CR0).addReg(Tmp1).addSImm(Tmp2);
794 bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
795 unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
796 Tmp2 = SelectExpr(SetCC->getOperand(1));
797 BuildMI(BB, CompareOpc, 2, PPC::CR0).addReg(Tmp1).addReg(Tmp2);
800 Tmp1 = SelectExpr(CC);
801 BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(0);
807 /// Check to see if the load is a constant offset from a base register
808 bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
810 unsigned imm = 0, opcode = N.getOpcode();
811 if (N.getOpcode() == ISD::ADD) {
812 Reg = SelectExpr(N.getOperand(0));
813 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
817 offset = SelectExpr(N.getOperand(1));
825 void ISel::SelectBranchCC(SDOperand N)
827 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
828 MachineBasicBlock *Dest =
829 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
831 // Get the MBB we will fall through to so that we can hand it off to the
832 // branch selection pass as an argument to the PPC::COND_BRANCH pseudo op.
833 //ilist<MachineBasicBlock>::iterator It = BB;
834 //MachineBasicBlock *Fallthrough = ++It;
836 Select(N.getOperand(0)); //chain
837 unsigned Opc = SelectSetCR0(N.getOperand(1));
838 // FIXME: Use this once we have something approximating two-way branches
839 // We cannot currently use this in case the ISel hands us something like
842 // since the fallthrough basic block for the conditional branch does not start
843 // with the unconditional branch (it is skipped over).
844 //BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
845 // .addMBB(Dest).addMBB(Fallthrough);
846 BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(Dest);
850 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
852 unsigned Tmp1, Tmp2, Tmp3;
854 SDNode *Node = N.Val;
855 MVT::ValueType DestType = N.getValueType();
856 unsigned opcode = N.getOpcode();
861 assert(0 && "Node not handled!\n");
864 // Attempt to generate FSEL. We can do this whenever we have an FP result,
865 // and an FP comparison in the SetCC node.
866 SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
867 if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
868 !MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
869 SetCC->getCondition() != ISD::SETEQ &&
870 SetCC->getCondition() != ISD::SETNE) {
871 MVT::ValueType VT = SetCC->getOperand(0).getValueType();
872 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
873 unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
874 unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
876 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
877 if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
878 switch(SetCC->getCondition()) {
879 default: assert(0 && "Invalid FSEL condition"); abort();
882 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(FV).addReg(TV);
886 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
891 BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
892 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(FV).addReg(TV);
898 BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
899 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
904 Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
905 Tmp2 = SelectExpr(SetCC->getOperand(1));
907 switch(SetCC->getCondition()) {
908 default: assert(0 && "Invalid FSEL condition"); abort();
911 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
912 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
916 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
917 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
921 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
922 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
926 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
927 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
931 assert(0 && "Should never get here");
935 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
936 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
937 Opc = SelectSetCR0(N.getOperand(0));
939 // Create an iterator with which to insert the MBB for copying the false
940 // value and the MBB to hold the PHI instruction for this SetCC.
941 MachineBasicBlock *thisMBB = BB;
942 const BasicBlock *LLVM_BB = BB->getBasicBlock();
943 ilist<MachineBasicBlock>::iterator It = BB;
951 // fallthrough --> copy0MBB
952 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
953 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
954 BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
955 MachineFunction *F = BB->getParent();
956 F->getBasicBlockList().insert(It, copy0MBB);
957 F->getBasicBlockList().insert(It, sinkMBB);
958 // Update machine-CFG edges
959 BB->addSuccessor(copy0MBB);
960 BB->addSuccessor(sinkMBB);
964 // # fallthrough to sinkMBB
966 // Update machine-CFG edges
967 BB->addSuccessor(sinkMBB);
970 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
973 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
974 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
979 if (!NoExcessFPPrecision &&
980 ISD::ADD == N.getOperand(0).getOpcode() &&
981 N.getOperand(0).Val->hasOneUse() &&
982 ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
983 N.getOperand(0).getOperand(0).Val->hasOneUse()) {
984 ++FusedFP; // Statistic
985 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
986 Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
987 Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
988 Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
989 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
990 } else if (!NoExcessFPPrecision &&
991 ISD::SUB == N.getOperand(0).getOpcode() &&
992 N.getOperand(0).Val->hasOneUse() &&
993 ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
994 N.getOperand(0).getOperand(0).Val->hasOneUse()) {
995 ++FusedFP; // Statistic
996 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
997 Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
998 Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
999 Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
1000 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1001 } else if (ISD::FABS == N.getOperand(0).getOpcode()) {
1002 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1003 BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
1005 Tmp1 = SelectExpr(N.getOperand(0));
1006 BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
1011 Tmp1 = SelectExpr(N.getOperand(0));
1012 BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
1016 assert (DestType == MVT::f32 &&
1017 N.getOperand(0).getValueType() == MVT::f64 &&
1018 "only f64 to f32 conversion supported here");
1019 Tmp1 = SelectExpr(N.getOperand(0));
1020 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
1023 case ISD::FP_EXTEND:
1024 assert (DestType == MVT::f64 &&
1025 N.getOperand(0).getValueType() == MVT::f32 &&
1026 "only f32 to f64 conversion supported here");
1027 Tmp1 = SelectExpr(N.getOperand(0));
1028 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
1031 case ISD::CopyFromReg:
1033 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1034 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
1035 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
1038 case ISD::ConstantFP: {
1039 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
1040 Result = getConstDouble(CN->getValue(), Result);
1045 if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
1046 N.getOperand(0).Val->hasOneUse()) {
1047 ++FusedFP; // Statistic
1048 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1049 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1050 Tmp3 = SelectExpr(N.getOperand(1));
1051 Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
1052 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1055 Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
1056 Tmp1 = SelectExpr(N.getOperand(0));
1057 Tmp2 = SelectExpr(N.getOperand(1));
1058 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1062 if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
1063 N.getOperand(0).Val->hasOneUse()) {
1064 ++FusedFP; // Statistic
1065 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1066 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1067 Tmp3 = SelectExpr(N.getOperand(1));
1068 Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
1069 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1072 Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
1073 Tmp1 = SelectExpr(N.getOperand(0));
1074 Tmp2 = SelectExpr(N.getOperand(1));
1075 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1081 case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
1082 case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
1084 Tmp1 = SelectExpr(N.getOperand(0));
1085 Tmp2 = SelectExpr(N.getOperand(1));
1086 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1089 case ISD::UINT_TO_FP:
1090 case ISD::SINT_TO_FP: {
1091 assert (N.getOperand(0).getValueType() == MVT::i32
1092 && "int to float must operate on i32");
1093 bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
1094 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1095 Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
1096 Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
1097 unsigned ConstF = MakeReg(MVT::f64); // temp reg to hold the fp constant
1099 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
1100 MachineConstantPool *CP = BB->getParent()->getConstantPool();
1102 // FIXME: pull this FP constant generation stuff out into something like
1103 // the simple ISel's getReg.
1105 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
1106 unsigned CPI = CP->getConstantPoolIndex(CFP);
1107 // Load constant fp value
1108 unsigned Tmp4 = MakeReg(MVT::i32);
1109 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp4).addReg(getGlobalBaseReg())
1110 .addConstantPoolIndex(CPI);
1111 BuildMI(BB, PPC::LFD, 2, ConstF).addConstantPoolIndex(CPI).addReg(Tmp4);
1112 // Store the hi & low halves of the fp value, currently in int regs
1113 BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
1114 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
1115 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
1116 addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
1117 // Generate the return value with a subtract
1118 BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
1120 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000008p52);
1121 unsigned CPI = CP->getConstantPoolIndex(CFP);
1122 // Load constant fp value
1123 unsigned Tmp4 = MakeReg(MVT::i32);
1124 unsigned TmpL = MakeReg(MVT::i32);
1125 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp4).addReg(getGlobalBaseReg())
1126 .addConstantPoolIndex(CPI);
1127 BuildMI(BB, PPC::LFD, 2, ConstF).addConstantPoolIndex(CPI).addReg(Tmp4);
1128 // Store the hi & low halves of the fp value, currently in int regs
1129 BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
1130 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
1131 BuildMI(BB, PPC::XORIS, 2, TmpL).addReg(Tmp1).addImm(0x8000);
1132 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
1133 addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
1134 // Generate the return value with a subtract
1135 BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
1140 assert(0 && "Should never get here");
1144 unsigned ISel::SelectExpr(SDOperand N) {
1146 unsigned Tmp1, Tmp2, Tmp3;
1148 unsigned opcode = N.getOpcode();
1150 SDNode *Node = N.Val;
1151 MVT::ValueType DestType = N.getValueType();
1153 unsigned &Reg = ExprMap[N];
1154 if (Reg) return Reg;
1156 switch (N.getOpcode()) {
1158 Reg = Result = (N.getValueType() != MVT::Other) ?
1159 MakeReg(N.getValueType()) : 1;
1162 // If this is a call instruction, make sure to prepare ALL of the result
1163 // values as well as the chain.
1164 if (Node->getNumValues() == 1)
1165 Reg = Result = 1; // Void call, just a chain.
1167 Result = MakeReg(Node->getValueType(0));
1168 ExprMap[N.getValue(0)] = Result;
1169 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
1170 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1171 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
1174 case ISD::ADD_PARTS:
1175 case ISD::SUB_PARTS:
1176 case ISD::SHL_PARTS:
1177 case ISD::SRL_PARTS:
1178 case ISD::SRA_PARTS:
1179 Result = MakeReg(Node->getValueType(0));
1180 ExprMap[N.getValue(0)] = Result;
1181 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
1182 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1186 if (ISD::CopyFromReg == opcode)
1187 DestType = N.getValue(0).getValueType();
1189 if (DestType == MVT::f64 || DestType == MVT::f32)
1190 if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode)
1191 return SelectExprFP(N, Result);
1196 assert(0 && "Node not handled!\n");
1198 BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
1200 case ISD::DYNAMIC_STACKALLOC:
1201 // Generate both result values. FIXME: Need a better commment here?
1203 ExprMap[N.getValue(1)] = 1;
1205 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1207 // FIXME: We are currently ignoring the requested alignment for handling
1208 // greater than the stack alignment. This will need to be revisited at some
1209 // point. Align = N.getOperand(2);
1210 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
1211 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
1212 std::cerr << "Cannot allocate stack object with greater alignment than"
1213 << " the stack alignment yet!";
1216 Select(N.getOperand(0));
1217 Tmp1 = SelectExpr(N.getOperand(1));
1218 // Subtract size from stack pointer, thereby allocating some space.
1219 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
1220 // Put a pointer to the space into the result register by copying the SP
1221 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
1224 case ISD::ConstantPool:
1225 Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
1226 Tmp2 = MakeReg(MVT::i32);
1227 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
1228 .addConstantPoolIndex(Tmp1);
1229 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
1232 case ISD::FrameIndex:
1233 Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
1234 addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
1237 case ISD::GlobalAddress: {
1238 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
1239 Tmp1 = MakeReg(MVT::i32);
1240 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
1241 .addGlobalAddress(GV);
1242 if (GV->hasWeakLinkage() || GV->isExternal()) {
1243 BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
1245 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp1).addGlobalAddress(GV);
1253 case ISD::SEXTLOAD: {
1254 MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
1255 Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
1256 bool sext = (ISD::SEXTLOAD == opcode);
1258 // Make sure we generate both values.
1260 ExprMap[N.getValue(1)] = 1; // Generate the token
1262 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1264 SDOperand Chain = N.getOperand(0);
1265 SDOperand Address = N.getOperand(1);
1268 switch (TypeBeingLoaded) {
1269 default: Node->dump(); assert(0 && "Cannot load this type!");
1270 case MVT::i1: Opc = PPC::LBZ; break;
1271 case MVT::i8: Opc = PPC::LBZ; break;
1272 case MVT::i16: Opc = sext ? PPC::LHA : PPC::LHZ; break;
1273 case MVT::i32: Opc = PPC::LWZ; break;
1274 case MVT::f32: Opc = PPC::LFS; break;
1275 case MVT::f64: Opc = PPC::LFD; break;
1278 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
1279 Tmp1 = MakeReg(MVT::i32);
1280 int CPI = CP->getIndex();
1281 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
1282 .addConstantPoolIndex(CPI);
1283 BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
1285 else if(Address.getOpcode() == ISD::FrameIndex) {
1286 Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
1287 addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
1290 bool idx = SelectAddr(Address, Tmp1, offset);
1292 Opc = IndexedOpForOp(Opc);
1293 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(offset);
1295 BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
1302 unsigned GPR_idx = 0, FPR_idx = 0;
1303 static const unsigned GPR[] = {
1304 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1305 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1307 static const unsigned FPR[] = {
1308 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1309 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1312 // Lower the chain for this call.
1313 Select(N.getOperand(0));
1314 ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
1316 MachineInstr *CallMI;
1317 // Emit the correct call instruction based on the type of symbol called.
1318 if (GlobalAddressSDNode *GASD =
1319 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
1320 CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
1322 } else if (ExternalSymbolSDNode *ESSDN =
1323 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
1324 CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
1327 Tmp1 = SelectExpr(N.getOperand(1));
1328 BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
1329 BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
1330 CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
1334 // Load the register args to virtual regs
1335 std::vector<unsigned> ArgVR;
1336 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
1337 ArgVR.push_back(SelectExpr(N.getOperand(i)));
1339 // Copy the virtual registers into the appropriate argument register
1340 for(int i = 0, e = ArgVR.size(); i < e; ++i) {
1341 switch(N.getOperand(i+2).getValueType()) {
1342 default: Node->dump(); assert(0 && "Unknown value type for call");
1347 assert(GPR_idx < 8 && "Too many int args");
1348 if (N.getOperand(i+2).getOpcode() != ISD::UNDEF) {
1349 BuildMI(BB, PPC::OR,2,GPR[GPR_idx]).addReg(ArgVR[i]).addReg(ArgVR[i]);
1350 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1356 assert(FPR_idx < 13 && "Too many fp args");
1357 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgVR[i]);
1358 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1364 // Put the call instruction in the correct place in the MachineBasicBlock
1365 BB->push_back(CallMI);
1367 switch (Node->getValueType(0)) {
1368 default: assert(0 && "Unknown value type for call result!");
1369 case MVT::Other: return 1;
1374 if (Node->getValueType(1) == MVT::i32) {
1375 BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3);
1376 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R4).addReg(PPC::R4);
1378 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
1383 BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
1386 return Result+N.ResNo;
1389 case ISD::SIGN_EXTEND:
1390 case ISD::SIGN_EXTEND_INREG:
1391 Tmp1 = SelectExpr(N.getOperand(0));
1392 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1393 default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
1395 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
1398 BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
1401 BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
1406 case ISD::ZERO_EXTEND_INREG:
1407 Tmp1 = SelectExpr(N.getOperand(0));
1408 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1409 default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break;
1410 case MVT::i16: Tmp2 = 16; break;
1411 case MVT::i8: Tmp2 = 24; break;
1412 case MVT::i1: Tmp2 = 31; break;
1414 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2)
1418 case ISD::CopyFromReg:
1420 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1421 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
1422 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
1426 Tmp1 = SelectExpr(N.getOperand(0));
1427 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1428 Tmp2 = CN->getValue() & 0x1F;
1429 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
1432 Tmp2 = SelectExpr(N.getOperand(1));
1433 BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1438 Tmp1 = SelectExpr(N.getOperand(0));
1439 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1440 Tmp2 = CN->getValue() & 0x1F;
1441 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(32-Tmp2)
1442 .addImm(Tmp2).addImm(31);
1444 Tmp2 = SelectExpr(N.getOperand(1));
1445 BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1450 Tmp1 = SelectExpr(N.getOperand(0));
1451 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1452 Tmp2 = CN->getValue() & 0x1F;
1453 BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1455 Tmp2 = SelectExpr(N.getOperand(1));
1456 BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1461 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
1462 Tmp1 = SelectExpr(N.getOperand(0));
1463 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1464 default: assert(0 && "unhandled result code");
1465 case 0: // No immediate
1466 Tmp2 = SelectExpr(N.getOperand(1));
1467 BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
1469 case 1: // Low immediate
1470 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1472 case 2: // Shifted immediate
1473 BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1480 Tmp1 = SelectExpr(N.getOperand(0));
1481 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1482 default: assert(0 && "unhandled result code");
1483 case 0: // No immediate
1484 Tmp2 = SelectExpr(N.getOperand(1));
1486 case ISD::AND: Opc = PPC::AND; break;
1487 case ISD::OR: Opc = PPC::OR; break;
1489 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1491 case 1: // Low immediate
1493 case ISD::AND: Opc = PPC::ANDIo; break;
1494 case ISD::OR: Opc = PPC::ORI; break;
1496 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
1498 case 2: // Shifted immediate
1500 case ISD::AND: Opc = PPC::ANDISo; break;
1501 case ISD::OR: Opc = PPC::ORIS; break;
1503 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
1509 // Check for EQV: xor, (xor a, -1), b
1510 if (N.getOperand(0).getOpcode() == ISD::XOR &&
1511 N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
1512 cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->isAllOnesValue()) {
1514 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1515 Tmp2 = SelectExpr(N.getOperand(1));
1516 BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
1519 // Check for NOT, NOR, and NAND: xor (copy, or, and), -1
1520 if (N.getOperand(1).getOpcode() == ISD::Constant &&
1521 cast<ConstantSDNode>(N.getOperand(1))->isAllOnesValue()) {
1523 switch(N.getOperand(0).getOpcode()) {
1525 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1526 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1527 BuildMI(BB, PPC::NOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
1530 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1531 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1532 BuildMI(BB, PPC::NAND, 2, Result).addReg(Tmp1).addReg(Tmp2);
1535 Tmp1 = SelectExpr(N.getOperand(0));
1536 BuildMI(BB, PPC::NOR, 2, Result).addReg(Tmp1).addReg(Tmp1);
1541 Tmp1 = SelectExpr(N.getOperand(0));
1542 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1543 default: assert(0 && "unhandled result code");
1544 case 0: // No immediate
1545 Tmp2 = SelectExpr(N.getOperand(1));
1546 BuildMI(BB, PPC::XOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
1548 case 1: // Low immediate
1549 BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1551 case 2: // Shifted immediate
1552 BuildMI(BB, PPC::XORIS, 2, Result).addReg(Tmp1).addImm(Tmp2);
1559 Tmp2 = SelectExpr(N.getOperand(1));
1560 if (1 == getImmediateForOpcode(N.getOperand(0), opcode, Tmp1))
1561 BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
1563 Tmp1 = SelectExpr(N.getOperand(0));
1564 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
1569 Tmp1 = SelectExpr(N.getOperand(0));
1570 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
1571 BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1573 Tmp2 = SelectExpr(N.getOperand(1));
1574 BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1580 Tmp1 = SelectExpr(N.getOperand(0));
1581 Tmp2 = SelectExpr(N.getOperand(1));
1582 Opc = (ISD::MULHU == opcode) ? PPC::MULHWU : PPC::MULHW;
1583 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1588 switch (getImmediateForOpcode(N.getOperand(1), opcode, Tmp3)) {
1590 // If this is an sdiv by a power of two, we can use an srawi/addze pair.
1592 Tmp1 = MakeReg(MVT::i32);
1593 Tmp2 = SelectExpr(N.getOperand(0));
1594 BuildMI(BB, PPC::SRAWI, 2, Tmp1).addReg(Tmp2).addImm(Tmp3);
1595 BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp1);
1597 // If this is a divide by constant, we can emit code using some magic
1598 // constants to implement it as a multiply instead.
1601 if (opcode == ISD::SDIV)
1602 return SelectExpr(BuildSDIVSequence(N));
1604 return SelectExpr(BuildUDIVSequence(N));
1606 Tmp1 = SelectExpr(N.getOperand(0));
1607 Tmp2 = SelectExpr(N.getOperand(1));
1608 Opc = (ISD::UDIV == opcode) ? PPC::DIVWU : PPC::DIVW;
1609 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1612 case ISD::ADD_PARTS:
1613 case ISD::SUB_PARTS: {
1614 assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
1615 "Not an i64 add/sub!");
1616 // Emit all of the operands.
1617 std::vector<unsigned> InVals;
1618 for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
1619 InVals.push_back(SelectExpr(N.getOperand(i)));
1620 if (N.getOpcode() == ISD::ADD_PARTS) {
1621 BuildMI(BB, PPC::ADDC, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
1622 BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
1624 BuildMI(BB, PPC::SUBFC, 2, Result).addReg(InVals[2]).addReg(InVals[0]);
1625 BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(InVals[3]).addReg(InVals[1]);
1627 return Result+N.ResNo;
1630 case ISD::SHL_PARTS:
1631 case ISD::SRA_PARTS:
1632 case ISD::SRL_PARTS: {
1633 assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
1634 "Not an i64 shift!");
1635 unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
1636 unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
1637 unsigned SHReg = SelectExpr(N.getOperand(2));
1638 Tmp1 = MakeReg(MVT::i32);
1639 Tmp2 = MakeReg(MVT::i32);
1640 Tmp3 = MakeReg(MVT::i32);
1641 unsigned Tmp4 = MakeReg(MVT::i32);
1642 unsigned Tmp5 = MakeReg(MVT::i32);
1643 unsigned Tmp6 = MakeReg(MVT::i32);
1644 BuildMI(BB, PPC::SUBFIC, 2, Tmp1).addReg(SHReg).addSImm(32);
1645 if (ISD::SHL_PARTS == opcode) {
1646 BuildMI(BB, PPC::SLW, 2, Tmp2).addReg(ShiftOpHi).addReg(SHReg);
1647 BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1);
1648 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
1649 BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
1650 BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpLo).addReg(Tmp5);
1651 BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6);
1652 BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg);
1653 } else if (ISD::SRL_PARTS == opcode) {
1654 BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
1655 BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
1656 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
1657 BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
1658 BuildMI(BB, PPC::SRW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
1659 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp4).addReg(Tmp6);
1660 BuildMI(BB, PPC::SRW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
1662 MachineBasicBlock *TmpMBB = new MachineBasicBlock(BB->getBasicBlock());
1663 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
1664 MachineBasicBlock *OldMBB = BB;
1665 MachineFunction *F = BB->getParent();
1666 ilist<MachineBasicBlock>::iterator It = BB; ++It;
1667 F->getBasicBlockList().insert(It, TmpMBB);
1668 F->getBasicBlockList().insert(It, PhiMBB);
1669 BB->addSuccessor(TmpMBB);
1670 BB->addSuccessor(PhiMBB);
1671 BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
1672 BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
1673 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
1674 BuildMI(BB, PPC::ADDICo, 2, Tmp5).addReg(SHReg).addSImm(-32);
1675 BuildMI(BB, PPC::SRAW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
1676 BuildMI(BB, PPC::SRAW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
1677 BuildMI(BB, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
1678 // Select correct least significant half if the shift amount > 32
1680 unsigned Tmp7 = MakeReg(MVT::i32);
1681 BuildMI(BB, PPC::OR, 2, Tmp7).addReg(Tmp6).addReg(Tmp6);
1682 TmpMBB->addSuccessor(PhiMBB);
1684 BuildMI(BB, PPC::PHI, 4, Result).addReg(Tmp4).addMBB(OldMBB)
1685 .addReg(Tmp7).addMBB(TmpMBB);
1687 return Result+N.ResNo;
1690 case ISD::FP_TO_UINT:
1691 case ISD::FP_TO_SINT: {
1692 bool U = (ISD::FP_TO_UINT == opcode);
1693 Tmp1 = SelectExpr(N.getOperand(0));
1695 Tmp2 = MakeReg(MVT::f64);
1696 BuildMI(BB, PPC::FCTIWZ, 1, Tmp2).addReg(Tmp1);
1697 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
1698 addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(Tmp2), FrameIdx);
1699 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Result), FrameIdx, 4);
1702 unsigned Zero = getConstDouble(0.0);
1703 unsigned MaxInt = getConstDouble((1LL << 32) - 1);
1704 unsigned Border = getConstDouble(1LL << 31);
1705 unsigned UseZero = MakeReg(MVT::f64);
1706 unsigned UseMaxInt = MakeReg(MVT::f64);
1707 unsigned UseChoice = MakeReg(MVT::f64);
1708 unsigned TmpReg = MakeReg(MVT::f64);
1709 unsigned TmpReg2 = MakeReg(MVT::f64);
1710 unsigned ConvReg = MakeReg(MVT::f64);
1711 unsigned IntTmp = MakeReg(MVT::i32);
1712 unsigned XorReg = MakeReg(MVT::i32);
1713 MachineFunction *F = BB->getParent();
1714 int FrameIdx = F->getFrameInfo()->CreateStackObject(8, 8);
1715 // Update machine-CFG edges
1716 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
1717 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
1718 MachineBasicBlock *OldMBB = BB;
1719 ilist<MachineBasicBlock>::iterator It = BB; ++It;
1720 F->getBasicBlockList().insert(It, XorMBB);
1721 F->getBasicBlockList().insert(It, PhiMBB);
1722 BB->addSuccessor(XorMBB);
1723 BB->addSuccessor(PhiMBB);
1724 // Convert from floating point to unsigned 32-bit value
1725 // Use 0 if incoming value is < 0.0
1726 BuildMI(BB, PPC::FSEL, 3, UseZero).addReg(Tmp1).addReg(Tmp1).addReg(Zero);
1727 // Use 2**32 - 1 if incoming value is >= 2**32
1728 BuildMI(BB, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(Tmp1);
1729 BuildMI(BB, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt).addReg(UseZero)
1732 BuildMI(BB, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
1733 // Use difference if >= 2**31
1734 BuildMI(BB, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice).addReg(Border);
1735 BuildMI(BB, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
1737 // Convert to integer
1738 BuildMI(BB, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
1739 addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(ConvReg), FrameIdx);
1740 addFrameReference(BuildMI(BB, PPC::LWZ, 2, IntTmp), FrameIdx, 4);
1741 BuildMI(BB, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
1742 BuildMI(BB, PPC::B, 1).addMBB(XorMBB);
1745 // add 2**31 if input was >= 2**31
1747 BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
1748 XorMBB->addSuccessor(PhiMBB);
1751 // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
1753 BuildMI(BB, PPC::PHI, 4, Result).addReg(IntTmp).addMBB(OldMBB)
1754 .addReg(XorReg).addMBB(XorMBB);
1757 assert(0 && "Should never get here");
1762 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
1763 Opc = SelectSetCR0(N);
1765 unsigned TrueValue = MakeReg(MVT::i32);
1766 BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
1767 unsigned FalseValue = MakeReg(MVT::i32);
1768 BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
1770 // Create an iterator with which to insert the MBB for copying the false
1771 // value and the MBB to hold the PHI instruction for this SetCC.
1772 MachineBasicBlock *thisMBB = BB;
1773 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1774 ilist<MachineBasicBlock>::iterator It = BB;
1779 // cmpTY cr0, r1, r2
1780 // %TrueValue = li 1
1782 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1783 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1784 BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
1785 MachineFunction *F = BB->getParent();
1786 F->getBasicBlockList().insert(It, copy0MBB);
1787 F->getBasicBlockList().insert(It, sinkMBB);
1788 // Update machine-CFG edges
1789 BB->addSuccessor(copy0MBB);
1790 BB->addSuccessor(sinkMBB);
1793 // %FalseValue = li 0
1796 // Update machine-CFG edges
1797 BB->addSuccessor(sinkMBB);
1800 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1803 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
1804 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
1807 assert(0 && "Is this legal?");
1811 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
1812 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
1813 Opc = SelectSetCR0(N.getOperand(0));
1815 // Create an iterator with which to insert the MBB for copying the false
1816 // value and the MBB to hold the PHI instruction for this SetCC.
1817 MachineBasicBlock *thisMBB = BB;
1818 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1819 ilist<MachineBasicBlock>::iterator It = BB;
1825 // cmpTY cr0, r1, r2
1827 // fallthrough --> copy0MBB
1828 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1829 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1830 BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
1831 MachineFunction *F = BB->getParent();
1832 F->getBasicBlockList().insert(It, copy0MBB);
1833 F->getBasicBlockList().insert(It, sinkMBB);
1834 // Update machine-CFG edges
1835 BB->addSuccessor(copy0MBB);
1836 BB->addSuccessor(sinkMBB);
1839 // %FalseValue = ...
1840 // # fallthrough to sinkMBB
1842 // Update machine-CFG edges
1843 BB->addSuccessor(sinkMBB);
1846 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1849 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
1850 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
1852 // FIXME: Select i64?
1857 switch (N.getValueType()) {
1858 default: assert(0 && "Cannot use constants of this type!");
1860 BuildMI(BB, PPC::LI, 1, Result)
1861 .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
1865 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
1866 if (v < 32768 && v >= -32768) {
1867 BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
1869 Tmp1 = MakeReg(MVT::i32);
1870 BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
1871 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
1881 void ISel::Select(SDOperand N) {
1882 unsigned Tmp1, Tmp2, Opc;
1883 unsigned opcode = N.getOpcode();
1885 if (!ExprMap.insert(std::make_pair(N, 1)).second)
1886 return; // Already selected.
1888 SDNode *Node = N.Val;
1890 switch (Node->getOpcode()) {
1892 Node->dump(); std::cerr << "\n";
1893 assert(0 && "Node not handled yet!");
1894 case ISD::EntryToken: return; // Noop
1895 case ISD::TokenFactor:
1896 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1897 Select(Node->getOperand(i));
1899 case ISD::ADJCALLSTACKDOWN:
1900 case ISD::ADJCALLSTACKUP:
1901 Select(N.getOperand(0));
1902 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1903 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? PPC::ADJCALLSTACKDOWN :
1904 PPC::ADJCALLSTACKUP;
1905 BuildMI(BB, Opc, 1).addImm(Tmp1);
1908 MachineBasicBlock *Dest =
1909 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
1910 Select(N.getOperand(0));
1911 BuildMI(BB, PPC::B, 1).addMBB(Dest);
1917 case ISD::CopyToReg:
1918 Select(N.getOperand(0));
1919 Tmp1 = SelectExpr(N.getOperand(1));
1920 Tmp2 = cast<RegSDNode>(N)->getReg();
1923 if (N.getOperand(1).getValueType() == MVT::f64 ||
1924 N.getOperand(1).getValueType() == MVT::f32)
1925 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
1927 BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1930 case ISD::ImplicitDef:
1931 Select(N.getOperand(0));
1932 BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
1935 switch (N.getNumOperands()) {
1937 assert(0 && "Unknown return instruction!");
1939 assert(N.getOperand(1).getValueType() == MVT::i32 &&
1940 N.getOperand(2).getValueType() == MVT::i32 &&
1941 "Unknown two-register value!");
1942 Select(N.getOperand(0));
1943 Tmp1 = SelectExpr(N.getOperand(1));
1944 Tmp2 = SelectExpr(N.getOperand(2));
1945 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp2).addReg(Tmp2);
1946 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp1).addReg(Tmp1);
1949 Select(N.getOperand(0));
1950 Tmp1 = SelectExpr(N.getOperand(1));
1951 switch (N.getOperand(1).getValueType()) {
1953 assert(0 && "Unknown return type!");
1956 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
1959 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
1963 Select(N.getOperand(0));
1966 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
1968 case ISD::TRUNCSTORE:
1971 SDOperand Chain = N.getOperand(0);
1972 SDOperand Value = N.getOperand(1);
1973 SDOperand Address = N.getOperand(2);
1976 Tmp1 = SelectExpr(Value); //value
1978 if (opcode == ISD::STORE) {
1979 switch(Value.getValueType()) {
1980 default: assert(0 && "unknown Type in store");
1981 case MVT::i32: Opc = PPC::STW; break;
1982 case MVT::f64: Opc = PPC::STFD; break;
1983 case MVT::f32: Opc = PPC::STFS; break;
1985 } else { //ISD::TRUNCSTORE
1986 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1987 default: assert(0 && "unknown Type in store");
1988 case MVT::i1: //FIXME: DAG does not promote this load
1989 case MVT::i8: Opc = PPC::STB; break;
1990 case MVT::i16: Opc = PPC::STH; break;
1994 if(Address.getOpcode() == ISD::FrameIndex)
1996 Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
1997 addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
2002 bool idx = SelectAddr(Address, Tmp2, offset);
2004 Opc = IndexedOpForOp(Opc);
2005 BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
2007 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
2016 case ISD::CopyFromReg:
2018 case ISD::DYNAMIC_STACKALLOC:
2023 assert(0 && "Should not be reached!");
2027 /// createPPC32PatternInstructionSelector - This pass converts an LLVM function
2028 /// into a machine code representation using pattern matching and a machine
2029 /// description file.
2031 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
2032 return new ISel(TM);