1 //===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
11 // Magic number generation for integer divide from the PowerPC Compiler Writer's
12 // Guide, section 3.2.3.5
14 //===----------------------------------------------------------------------===//
17 #include "PowerPCInstrBuilder.h"
18 #include "PowerPCInstrInfo.h"
19 #include "PPC32TargetMachine.h"
20 #include "llvm/Constants.h" // FIXME: REMOVE
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/ADT/Statistic.h"
38 //===----------------------------------------------------------------------===//
39 // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
41 class PPC32TargetLowering : public TargetLowering {
42 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
43 int ReturnAddrIndex; // FrameIndex for return slot.
45 PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Set up the register classes.
47 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
48 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
49 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
51 // PowerPC has no intrinsics for these particular operations
52 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
53 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
54 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
56 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
57 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
58 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
60 // PowerPC has no SREM/UREM instructions
61 setOperationAction(ISD::SREM, MVT::i32, Expand);
62 setOperationAction(ISD::UREM, MVT::i32, Expand);
64 setShiftAmountFlavor(Extend); // shl X, 32 == 0
65 setSetCCResultContents(ZeroOrOneSetCCResult);
66 addLegalFPImmediate(+0.0); // Necessary for FSEL
67 addLegalFPImmediate(-0.0); //
69 computeRegisterProperties();
72 /// LowerArguments - This hook must be implemented to indicate how we should
73 /// lower the arguments for the specified function, into the specified DAG.
74 virtual std::vector<SDOperand>
75 LowerArguments(Function &F, SelectionDAG &DAG);
77 /// LowerCallTo - This hook lowers an abstract call to a function into an
79 virtual std::pair<SDOperand, SDOperand>
80 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
81 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
83 virtual std::pair<SDOperand, SDOperand>
84 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
86 virtual std::pair<SDOperand,SDOperand>
87 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
88 const Type *ArgTy, SelectionDAG &DAG);
90 virtual std::pair<SDOperand, SDOperand>
91 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
97 std::vector<SDOperand>
98 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
100 // add beautiful description of PPC stack frame format, or at least some docs
102 MachineFunction &MF = DAG.getMachineFunction();
103 MachineFrameInfo *MFI = MF.getFrameInfo();
104 MachineBasicBlock& BB = MF.front();
105 std::vector<SDOperand> ArgValues;
107 // Due to the rather complicated nature of the PowerPC ABI, rather than a
108 // fixed size array of physical args, for the sake of simplicity let the STL
109 // handle tracking them for us.
110 std::vector<unsigned> argVR, argPR, argOp;
111 unsigned ArgOffset = 24;
112 unsigned GPR_remaining = 8;
113 unsigned FPR_remaining = 13;
114 unsigned GPR_idx = 0, FPR_idx = 0;
115 static const unsigned GPR[] = {
116 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
117 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
119 static const unsigned FPR[] = {
120 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
121 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
124 // Add DAG nodes to load the arguments... On entry to a function on PPC,
125 // the arguments start at offset 24, although they are likely to be passed
127 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
128 SDOperand newroot, argt;
130 bool needsLoad = false;
131 bool ArgLive = !I->use_empty();
132 MVT::ValueType ObjectVT = getValueType(I->getType());
135 default: assert(0 && "Unhandled argument type!");
142 if (GPR_remaining > 0) {
143 MF.addLiveIn(GPR[GPR_idx]);
144 argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
146 if (ObjectVT != MVT::i32)
147 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
152 case MVT::i64: ObjSize = 8;
154 // FIXME: can split 64b load between reg/mem if it is last arg in regs
155 if (GPR_remaining > 1) {
156 MF.addLiveIn(GPR[GPR_idx]);
157 MF.addLiveIn(GPR[GPR_idx+1]);
158 // Copy the extracted halves into the virtual registers
159 SDOperand argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
161 SDOperand argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
162 // Build the outgoing arg thingy
163 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
171 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
173 if (FPR_remaining > 0) {
174 MF.addLiveIn(FPR[FPR_idx]);
175 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
185 // We need to load the argument to a virtual register if we determined above
186 // that we ran out of physical registers of the appropriate type
188 unsigned SubregOffset = 0;
189 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
190 if (ObjectVT == MVT::i16) SubregOffset = 2;
191 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
192 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
193 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
194 DAG.getConstant(SubregOffset, MVT::i32));
195 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
198 // Every 4 bytes of argument space consumes one of the GPRs available for
200 if (GPR_remaining > 0) {
201 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
202 GPR_remaining -= delta;
205 ArgOffset += ObjSize;
207 DAG.setRoot(newroot.getValue(1));
209 ArgValues.push_back(argt);
212 // If the function takes variable number of arguments, make a frame index for
213 // the start of the first vararg value... for expansion of llvm.va_start.
215 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
216 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
217 // If this function is vararg, store any remaining integer argument regs
218 // to their spots on the stack so that they may be loaded by deferencing the
219 // result of va_next.
220 std::vector<SDOperand> MemOps;
221 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
222 MF.addLiveIn(GPR[GPR_idx]);
223 SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
224 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
226 MemOps.push_back(Store);
227 // Increment the address by four for the next argument to store
228 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
229 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
231 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
234 // Finally, inform the code generator which regs we return values in.
235 switch (getValueType(F.getReturnType())) {
236 default: assert(0 && "Unknown type!");
237 case MVT::isVoid: break;
242 MF.addLiveOut(PPC::R3);
245 MF.addLiveOut(PPC::R3);
246 MF.addLiveOut(PPC::R4);
250 MF.addLiveOut(PPC::F1);
257 std::pair<SDOperand, SDOperand>
258 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
259 const Type *RetTy, bool isVarArg,
260 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
261 // args_to_use will accumulate outgoing args for the ISD::CALL case in
262 // SelectExpr to use to put the arguments in the appropriate registers.
263 std::vector<SDOperand> args_to_use;
265 // Count how many bytes are to be pushed on the stack, including the linkage
266 // area, and parameter passing area.
267 unsigned NumBytes = 24;
270 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
271 DAG.getConstant(NumBytes, getPointerTy()));
273 for (unsigned i = 0, e = Args.size(); i != e; ++i)
274 switch (getValueType(Args[i].second)) {
275 default: assert(0 && "Unknown value type!");
289 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
290 // plus 32 bytes of argument space in case any called code gets funky on us.
291 if (NumBytes < 56) NumBytes = 56;
293 // Adjust the stack pointer for the new arguments...
294 // These operations are automatically eliminated by the prolog/epilog pass
295 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
296 DAG.getConstant(NumBytes, getPointerTy()));
298 // Set up a copy of the stack pointer for use loading and storing any
299 // arguments that may not fit in the registers available for argument
301 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
304 // Figure out which arguments are going to go in registers, and which in
305 // memory. Also, if this is a vararg function, floating point operations
306 // must be stored to our stack, and loaded into integer regs as well, if
307 // any integer regs are available for argument passing.
308 unsigned ArgOffset = 24;
309 unsigned GPR_remaining = 8;
310 unsigned FPR_remaining = 13;
312 std::vector<SDOperand> MemOps;
313 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
314 // PtrOff will be used to store the current argument to the stack if a
315 // register cannot be found for it.
316 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
317 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
318 MVT::ValueType ArgVT = getValueType(Args[i].second);
321 default: assert(0 && "Unexpected ValueType for argument!");
325 // Promote the integer to 32 bits. If the input type is signed use a
326 // sign extend, otherwise use a zero extend.
327 if (Args[i].second->isSigned())
328 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
330 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
333 if (GPR_remaining > 0) {
334 args_to_use.push_back(Args[i].first);
337 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
338 Args[i].first, PtrOff));
343 // If we have one free GPR left, we can place the upper half of the i64
344 // in it, and store the other half to the stack. If we have two or more
345 // free GPRs, then we can pass both halves of the i64 in registers.
346 if (GPR_remaining > 0) {
347 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
348 Args[i].first, DAG.getConstant(1, MVT::i32));
349 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
350 Args[i].first, DAG.getConstant(0, MVT::i32));
351 args_to_use.push_back(Hi);
353 if (GPR_remaining > 0) {
354 args_to_use.push_back(Lo);
357 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
358 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
359 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
363 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
364 Args[i].first, PtrOff));
370 if (FPR_remaining > 0) {
371 args_to_use.push_back(Args[i].first);
374 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
375 Args[i].first, PtrOff);
376 MemOps.push_back(Store);
377 // Float varargs are always shadowed in available integer registers
378 if (GPR_remaining > 0) {
379 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
380 MemOps.push_back(Load);
381 args_to_use.push_back(Load);
384 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
385 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
386 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
387 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff);
388 MemOps.push_back(Load);
389 args_to_use.push_back(Load);
393 // If we have any FPRs remaining, we may also have GPRs remaining.
394 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
396 if (GPR_remaining > 0) {
397 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
400 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
401 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
406 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
407 Args[i].first, PtrOff));
409 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
414 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
417 std::vector<MVT::ValueType> RetVals;
418 MVT::ValueType RetTyVT = getValueType(RetTy);
419 if (RetTyVT != MVT::isVoid)
420 RetVals.push_back(RetTyVT);
421 RetVals.push_back(MVT::Other);
423 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
424 Chain, Callee, args_to_use), 0);
425 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
426 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
427 DAG.getConstant(NumBytes, getPointerTy()));
428 return std::make_pair(TheCall, Chain);
431 std::pair<SDOperand, SDOperand>
432 PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
433 //vastart just returns the address of the VarArgsFrameIndex slot.
434 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
437 std::pair<SDOperand,SDOperand> PPC32TargetLowering::
438 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
439 const Type *ArgTy, SelectionDAG &DAG) {
440 MVT::ValueType ArgVT = getValueType(ArgTy);
443 Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
446 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
449 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
450 "Other types should have been promoted for varargs!");
453 Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
454 DAG.getConstant(Amt, VAList.getValueType()));
456 return std::make_pair(Result, Chain);
460 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
461 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
463 assert(0 && "LowerFrameReturnAddress unimplemented");
468 Statistic<>Rotates("ppc-codegen", "Number of rotates emitted");
469 Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
470 //===--------------------------------------------------------------------===//
471 /// ISel - PPC32 specific code to select PPC32 machine instructions for
472 /// SelectionDAG operations.
473 //===--------------------------------------------------------------------===//
474 class ISel : public SelectionDAGISel {
475 PPC32TargetLowering PPC32Lowering;
476 SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
477 // for sdiv and udiv until it is put into the future
480 /// ExprMap - As shared expressions are codegen'd, we keep track of which
481 /// vreg the value is produced in, so we only emit one copy of each compiled
483 std::map<SDOperand, unsigned> ExprMap;
485 unsigned GlobalBaseReg;
486 bool GlobalBaseInitialized;
489 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
492 /// runOnFunction - Override this function in order to reset our per-function
494 virtual bool runOnFunction(Function &Fn) {
495 // Make sure we re-emit a set of the global base reg if necessary
496 GlobalBaseInitialized = false;
497 return SelectionDAGISel::runOnFunction(Fn);
500 /// InstructionSelectBasicBlock - This callback is invoked by
501 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
502 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
504 // Codegen the basic block.
506 Select(DAG.getRoot());
508 // Clear state used for selection.
513 // dag -> dag expanders for integer divide by constant
514 SDOperand BuildSDIVSequence(SDOperand N);
515 SDOperand BuildUDIVSequence(SDOperand N);
517 unsigned getGlobalBaseReg();
518 unsigned getConstDouble(double floatVal, unsigned Result);
519 bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
520 unsigned SelectSetCR0(SDOperand CC);
521 unsigned SelectExpr(SDOperand N);
522 unsigned SelectExprFP(SDOperand N, unsigned Result);
523 void Select(SDOperand N);
525 bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
526 void SelectBranchCC(SDOperand N);
529 /// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
530 /// returns zero when the input is not exactly a power of two.
531 static unsigned ExactLog2(unsigned Val) {
532 if (Val == 0 || (Val & (Val-1))) return 0;
541 // IsRunOfOnes - returns true if Val consists of one contiguous run of 1's with
542 // any number of 0's on either side. the 1's are allowed to wrap from LSB to
543 // MSB. so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
544 // not, since all 1's are not contiguous.
545 static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
550 // look for first set bit
552 for (; i < 32; i++) {
553 if ((Val & (1 << (31 - i))) != 0) {
560 // look for last set bit
561 for (; i < 32; i++) {
562 if ((Val & (1 << (31 - i))) == 0)
567 // look for next set bit
568 for (; i < 32; i++) {
569 if ((Val & (1 << (31 - i))) != 0)
573 // if we exhausted all the bits, we found a match at this point for 0*1*0*
577 // since we just encountered more 1's, if it doesn't wrap around to the
578 // most significant bit of the word, then we did not find a match to 1*0*1* so
583 // look for last set bit
584 for (MB = i; i < 32; i++) {
585 if ((Val & (1 << (31 - i))) == 0)
589 // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
590 // the value is not a run of ones.
596 /// getImmediateForOpcode - This method returns a value indicating whether
597 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
598 /// values are either 0, 1 or 2. 0 indicates that either N is not a
599 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
600 /// of 1 indicates that the constant may be used in normal immediate form. A
601 /// return value of 2 indicates that the constant may be used in shifted
602 /// immediate form. A return value of 3 indicates that log base 2 of the
603 /// constant may be used. A return value of 4 indicates that the constant is
604 /// suitable for conversion into a magic number for integer division.
606 static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
607 unsigned& Imm, bool U = false) {
608 if (N.getOpcode() != ISD::Constant) return 0;
610 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
615 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
616 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
621 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
622 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
626 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
629 if (U && (v >= 0 && v <= 65535)) { Imm = v & 0xFFFF; return 1; }
630 if (!U && (v <= 32767 && v >= -32768)) { Imm = v & 0xFFFF; return 1; }
633 if ((Imm = ExactLog2(v))) { return 3; }
634 if (v <= -2 || v >= 2) { return 4; }
637 if (v > 1) { return 4; }
643 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
644 /// to Condition. If the Condition is unordered or unsigned, the bool argument
645 /// U is set to true, otherwise it is set to false.
646 static unsigned getBCCForSetCC(unsigned Condition, bool& U) {
649 default: assert(0 && "Unknown condition!"); abort();
650 case ISD::SETEQ: return PPC::BEQ;
651 case ISD::SETNE: return PPC::BNE;
652 case ISD::SETULT: U = true;
653 case ISD::SETLT: return PPC::BLT;
654 case ISD::SETULE: U = true;
655 case ISD::SETLE: return PPC::BLE;
656 case ISD::SETUGT: U = true;
657 case ISD::SETGT: return PPC::BGT;
658 case ISD::SETUGE: U = true;
659 case ISD::SETGE: return PPC::BGE;
664 /// IndexedOpForOp - Return the indexed variant for each of the PowerPC load
665 /// and store immediate instructions.
666 static unsigned IndexedOpForOp(unsigned Opcode) {
668 default: assert(0 && "Unknown opcode!"); abort();
669 case PPC::LBZ: return PPC::LBZX; case PPC::STB: return PPC::STBX;
670 case PPC::LHZ: return PPC::LHZX; case PPC::STH: return PPC::STHX;
671 case PPC::LHA: return PPC::LHAX; case PPC::STW: return PPC::STWX;
672 case PPC::LWZ: return PPC::LWZX; case PPC::STFS: return PPC::STFSX;
673 case PPC::LFS: return PPC::LFSX; case PPC::STFD: return PPC::STFDX;
674 case PPC::LFD: return PPC::LFDX;
679 // Structure used to return the necessary information to codegen an SDIV as
682 int m; // magic number
683 int s; // shift amount
687 unsigned int m; // magic number
688 int a; // add indicator
689 int s; // shift amount
692 /// magic - calculate the magic numbers required to codegen an integer sdiv as
693 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
695 static struct ms magic(int d) {
697 unsigned int ad, anc, delta, q1, r1, q2, r2, t;
698 const unsigned int two31 = 2147483648U; // 2^31
702 t = two31 + ((unsigned int)d >> 31);
703 anc = t - 1 - t%ad; // absolute value of nc
704 p = 31; // initialize p
705 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
706 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
707 q2 = two31/ad; // initialize q2 = 2p/abs(d)
708 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
711 q1 = 2*q1; // update q1 = 2p/abs(nc)
712 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
713 if (r1 >= anc) { // must be unsigned comparison
717 q2 = 2*q2; // update q2 = 2p/abs(d)
718 r2 = 2*r2; // update r2 = rem(2p/abs(d))
719 if (r2 >= ad) { // must be unsigned comparison
724 } while (q1 < delta || (q1 == delta && r1 == 0));
727 if (d < 0) mag.m = -mag.m; // resulting magic number
728 mag.s = p - 32; // resulting shift
732 /// magicu - calculate the magic numbers required to codegen an integer udiv as
733 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
734 static struct mu magicu(unsigned d)
737 unsigned int nc, delta, q1, r1, q2, r2;
739 magu.a = 0; // initialize "add" indicator
741 p = 31; // initialize p
742 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
743 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
744 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
745 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
748 if (r1 >= nc - r1 ) {
749 q1 = 2*q1 + 1; // update q1
750 r1 = 2*r1 - nc; // update r1
753 q1 = 2*q1; // update q1
754 r1 = 2*r1; // update r1
756 if (r2 + 1 >= d - r2) {
757 if (q2 >= 0x7FFFFFFF) magu.a = 1;
758 q2 = 2*q2 + 1; // update q2
759 r2 = 2*r2 + 1 - d; // update r2
762 if (q2 >= 0x80000000) magu.a = 1;
763 q2 = 2*q2; // update q2
764 r2 = 2*r2 + 1; // update r2
767 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
768 magu.m = q2 + 1; // resulting magic number
769 magu.s = p - 32; // resulting shift
774 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
775 /// return a DAG expression to select that will generate the same value by
776 /// multiplying by a magic number. See:
777 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
778 SDOperand ISel::BuildSDIVSequence(SDOperand N) {
779 int d = (int)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
780 ms magics = magic(d);
781 // Multiply the numerator (operand 0) by the magic value
782 SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
783 ISelDAG->getConstant(magics.m, MVT::i32));
784 // If d > 0 and m < 0, add the numerator
785 if (d > 0 && magics.m < 0)
786 Q = ISelDAG->getNode(ISD::ADD, MVT::i32, Q, N.getOperand(0));
787 // If d < 0 and m > 0, subtract the numerator.
788 if (d < 0 && magics.m > 0)
789 Q = ISelDAG->getNode(ISD::SUB, MVT::i32, Q, N.getOperand(0));
790 // Shift right algebraic if shift value is nonzero
792 Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
793 ISelDAG->getConstant(magics.s, MVT::i32));
794 // Extract the sign bit and add it to the quotient
796 ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
797 return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
800 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
801 /// return a DAG expression to select that will generate the same value by
802 /// multiplying by a magic number. See:
803 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
804 SDOperand ISel::BuildUDIVSequence(SDOperand N) {
806 (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
807 mu magics = magicu(d);
808 // Multiply the numerator (operand 0) by the magic value
809 SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
810 ISelDAG->getConstant(magics.m, MVT::i32));
812 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
813 ISelDAG->getConstant(magics.s, MVT::i32));
815 SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), Q);
816 NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
817 ISelDAG->getConstant(1, MVT::i32));
818 NPQ = ISelDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
819 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
820 ISelDAG->getConstant(magics.s-1, MVT::i32));
825 /// getGlobalBaseReg - Output the instructions required to put the
826 /// base address to use for accessing globals into a register.
828 unsigned ISel::getGlobalBaseReg() {
829 if (!GlobalBaseInitialized) {
830 // Insert the set of GlobalBaseReg into the first MBB of the function
831 MachineBasicBlock &FirstMBB = BB->getParent()->front();
832 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
833 GlobalBaseReg = MakeReg(MVT::i32);
834 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
835 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
836 GlobalBaseInitialized = true;
838 return GlobalBaseReg;
841 /// getConstDouble - Loads a floating point value into a register, via the
842 /// Constant Pool. Optionally takes a register in which to load the value.
843 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
844 unsigned Tmp1 = MakeReg(MVT::i32);
845 if (0 == Result) Result = MakeReg(MVT::f64);
846 MachineConstantPool *CP = BB->getParent()->getConstantPool();
847 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
848 unsigned CPI = CP->getConstantPoolIndex(CFP);
849 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
850 .addConstantPoolIndex(CPI);
851 BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
855 /// SelectBitfieldInsert - turn an or of two masked values into
856 /// the rotate left word immediate then mask insert (rlwimi) instruction.
857 /// Returns true on success, false if the caller still needs to select OR.
859 /// Patterns matched:
860 /// 1. or shl, and 5. or and, and
861 /// 2. or and, shl 6. or shl, shr
862 /// 3. or shr, and 7. or shr, shl
864 bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
865 bool IsRotate = false;
866 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
867 unsigned Op0Opc = OR.getOperand(0).getOpcode();
868 unsigned Op1Opc = OR.getOperand(1).getOpcode();
870 // Verify that we have the correct opcodes
871 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
873 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
876 // Generate Mask value for Target
877 if (ConstantSDNode *CN =
878 dyn_cast<ConstantSDNode>(OR.getOperand(0).getOperand(1).Val)) {
880 case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
881 case ISD::SRL: TgtMask >>= (unsigned)CN->getValue(); break;
882 case ISD::AND: TgtMask &= (unsigned)CN->getValue(); break;
888 // Generate Mask value for Insert
889 if (ConstantSDNode *CN =
890 dyn_cast<ConstantSDNode>(OR.getOperand(1).getOperand(1).Val)) {
893 Amount = CN->getValue();
895 if (Op0Opc == ISD::SRL) IsRotate = true;
898 Amount = CN->getValue();
901 if (Op0Opc == ISD::SHL) IsRotate = true;
904 InsMask &= (unsigned)CN->getValue();
911 // Verify that the Target mask and Insert mask together form a full word mask
912 // and that the Insert mask is a run of set bits (which implies both are runs
913 // of set bits). Given that, Select the arguments and generate the rlwimi
916 if (((TgtMask ^ InsMask) == 0xFFFFFFFF) && IsRunOfOnes(InsMask, MB, ME)) {
918 // Check for rotlwi / rotrwi here, a special case of bitfield insert
919 // where both bitfield halves are sourced from the same value.
921 OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
922 ++Rotates; // Statistic
923 Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
924 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
925 .addImm(0).addImm(31);
928 if (Op0Opc == ISD::AND)
929 Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
931 Tmp1 = SelectExpr(OR.getOperand(0));
932 Tmp2 = SelectExpr(OR.getOperand(1).getOperand(0));
933 BuildMI(BB, PPC::RLWIMI, 5, Result).addReg(Tmp1).addReg(Tmp2)
934 .addImm(Amount).addImm(MB).addImm(ME);
940 unsigned ISel::SelectSetCR0(SDOperand CC) {
941 unsigned Opc, Tmp1, Tmp2;
942 static const unsigned CompareOpcodes[] =
943 { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
945 // If the first operand to the select is a SETCC node, then we can fold it
946 // into the branch that selects which value to return.
947 SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val);
948 if (SetCC && CC.getOpcode() == ISD::SETCC) {
950 Opc = getBCCForSetCC(SetCC->getCondition(), U);
951 Tmp1 = SelectExpr(SetCC->getOperand(0));
953 // Pass the optional argument U to getImmediateForOpcode for SETCC,
954 // so that it knows whether the SETCC immediate range is signed or not.
955 if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
958 BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(Tmp2);
960 BuildMI(BB, PPC::CMPWI, 2, PPC::CR0).addReg(Tmp1).addSImm(Tmp2);
962 bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
963 unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
964 Tmp2 = SelectExpr(SetCC->getOperand(1));
965 BuildMI(BB, CompareOpc, 2, PPC::CR0).addReg(Tmp1).addReg(Tmp2);
968 Tmp1 = SelectExpr(CC);
969 BuildMI(BB, PPC::CMPLWI, 2, PPC::CR0).addReg(Tmp1).addImm(0);
975 /// Check to see if the load is a constant offset from a base register
976 bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
978 unsigned imm = 0, opcode = N.getOpcode();
979 if (N.getOpcode() == ISD::ADD) {
980 Reg = SelectExpr(N.getOperand(0));
981 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
985 offset = SelectExpr(N.getOperand(1));
993 void ISel::SelectBranchCC(SDOperand N)
995 MachineBasicBlock *Dest =
996 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
998 Select(N.getOperand(0)); //chain
999 unsigned Opc = SelectSetCR0(N.getOperand(1));
1001 // Iterate to the next basic block, unless we're already at the end of the
1002 ilist<MachineBasicBlock>::iterator It = BB, E = BB->getParent()->end();
1003 if (++It == E) It = BB;
1005 // If this is a two way branch, then grab the fallthrough basic block argument
1006 // and build a PowerPC branch pseudo-op, suitable for long branch conversion
1007 // if necessary by the branch selection pass. Otherwise, emit a standard
1008 // conditional branch.
1009 if (N.getOpcode() == ISD::BRCONDTWOWAY) {
1010 MachineBasicBlock *Fallthrough =
1011 cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
1013 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
1014 .addMBB(Dest).addMBB(Fallthrough);
1015 if (Fallthrough != It)
1016 BuildMI(BB, PPC::B, 1).addMBB(Fallthrough);
1018 if (Fallthrough != It) {
1019 Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
1020 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
1021 .addMBB(Fallthrough).addMBB(Dest);
1025 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(PPC::CR0).addImm(Opc)
1026 .addMBB(Dest).addMBB(It);
1027 //BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(Dest);
1032 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
1034 unsigned Tmp1, Tmp2, Tmp3;
1036 SDNode *Node = N.Val;
1037 MVT::ValueType DestType = N.getValueType();
1038 unsigned opcode = N.getOpcode();
1043 assert(0 && "Node not handled!\n");
1046 // Attempt to generate FSEL. We can do this whenever we have an FP result,
1047 // and an FP comparison in the SetCC node.
1048 SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
1049 if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
1050 !MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
1051 SetCC->getCondition() != ISD::SETEQ &&
1052 SetCC->getCondition() != ISD::SETNE) {
1053 MVT::ValueType VT = SetCC->getOperand(0).getValueType();
1054 unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
1055 unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
1057 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
1058 if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
1059 switch(SetCC->getCondition()) {
1060 default: assert(0 && "Invalid FSEL condition"); abort();
1063 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1066 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
1067 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
1071 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1074 if (SetCC->getOperand(0).getOpcode() == ISD::FNEG) {
1075 Tmp2 = SelectExpr(SetCC->getOperand(0).getOperand(0));
1078 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
1079 BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
1081 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
1086 Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
1087 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
1088 Tmp2 = SelectExpr(SetCC->getOperand(1));
1090 switch(SetCC->getCondition()) {
1091 default: assert(0 && "Invalid FSEL condition"); abort();
1094 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
1095 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
1099 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
1100 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
1104 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
1105 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
1109 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
1110 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
1114 assert(0 && "Should never get here");
1118 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
1119 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
1120 Opc = SelectSetCR0(N.getOperand(0));
1122 // Create an iterator with which to insert the MBB for copying the false
1123 // value and the MBB to hold the PHI instruction for this SetCC.
1124 MachineBasicBlock *thisMBB = BB;
1125 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1126 ilist<MachineBasicBlock>::iterator It = BB;
1132 // cmpTY cr0, r1, r2
1134 // fallthrough --> copy0MBB
1135 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1136 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1137 BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
1138 MachineFunction *F = BB->getParent();
1139 F->getBasicBlockList().insert(It, copy0MBB);
1140 F->getBasicBlockList().insert(It, sinkMBB);
1141 // Update machine-CFG edges
1142 BB->addSuccessor(copy0MBB);
1143 BB->addSuccessor(sinkMBB);
1146 // %FalseValue = ...
1147 // # fallthrough to sinkMBB
1149 // Update machine-CFG edges
1150 BB->addSuccessor(sinkMBB);
1153 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1156 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
1157 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
1162 if (!NoExcessFPPrecision &&
1163 ISD::ADD == N.getOperand(0).getOpcode() &&
1164 N.getOperand(0).Val->hasOneUse() &&
1165 ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
1166 N.getOperand(0).getOperand(0).Val->hasOneUse()) {
1167 ++FusedFP; // Statistic
1168 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
1169 Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
1170 Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
1171 Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
1172 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1173 } else if (!NoExcessFPPrecision &&
1174 ISD::ADD == N.getOperand(0).getOpcode() &&
1175 N.getOperand(0).Val->hasOneUse() &&
1176 ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
1177 N.getOperand(0).getOperand(1).Val->hasOneUse()) {
1178 ++FusedFP; // Statistic
1179 Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
1180 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(1));
1181 Tmp3 = SelectExpr(N.getOperand(0).getOperand(0));
1182 Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
1183 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1184 } else if (ISD::FABS == N.getOperand(0).getOpcode()) {
1185 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1186 BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
1188 Tmp1 = SelectExpr(N.getOperand(0));
1189 BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
1194 Tmp1 = SelectExpr(N.getOperand(0));
1195 BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
1199 assert (DestType == MVT::f32 &&
1200 N.getOperand(0).getValueType() == MVT::f64 &&
1201 "only f64 to f32 conversion supported here");
1202 Tmp1 = SelectExpr(N.getOperand(0));
1203 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
1206 case ISD::FP_EXTEND:
1207 assert (DestType == MVT::f64 &&
1208 N.getOperand(0).getValueType() == MVT::f32 &&
1209 "only f32 to f64 conversion supported here");
1210 Tmp1 = SelectExpr(N.getOperand(0));
1211 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
1214 case ISD::CopyFromReg:
1216 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1217 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
1218 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
1221 case ISD::ConstantFP: {
1222 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
1223 Result = getConstDouble(CN->getValue(), Result);
1228 if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
1229 N.getOperand(0).Val->hasOneUse()) {
1230 ++FusedFP; // Statistic
1231 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1232 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1233 Tmp3 = SelectExpr(N.getOperand(1));
1234 Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
1235 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1238 if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
1239 N.getOperand(1).Val->hasOneUse()) {
1240 ++FusedFP; // Statistic
1241 Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
1242 Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
1243 Tmp3 = SelectExpr(N.getOperand(0));
1244 Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
1245 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1248 Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
1249 Tmp1 = SelectExpr(N.getOperand(0));
1250 Tmp2 = SelectExpr(N.getOperand(1));
1251 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1255 if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
1256 N.getOperand(0).Val->hasOneUse()) {
1257 ++FusedFP; // Statistic
1258 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1259 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1260 Tmp3 = SelectExpr(N.getOperand(1));
1261 Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
1262 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1265 if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
1266 N.getOperand(1).Val->hasOneUse()) {
1267 ++FusedFP; // Statistic
1268 Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
1269 Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
1270 Tmp3 = SelectExpr(N.getOperand(0));
1271 Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
1272 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1275 Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
1276 Tmp1 = SelectExpr(N.getOperand(0));
1277 Tmp2 = SelectExpr(N.getOperand(1));
1278 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1284 case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
1285 case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
1287 Tmp1 = SelectExpr(N.getOperand(0));
1288 Tmp2 = SelectExpr(N.getOperand(1));
1289 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1292 case ISD::UINT_TO_FP:
1293 case ISD::SINT_TO_FP: {
1294 assert (N.getOperand(0).getValueType() == MVT::i32
1295 && "int to float must operate on i32");
1296 bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
1297 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1298 Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
1299 Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
1300 unsigned ConstF = MakeReg(MVT::f64); // temp reg to hold the fp constant
1302 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
1303 MachineConstantPool *CP = BB->getParent()->getConstantPool();
1305 // FIXME: pull this FP constant generation stuff out into something like
1306 // the simple ISel's getReg.
1308 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000000p52);
1309 unsigned CPI = CP->getConstantPoolIndex(CFP);
1310 // Load constant fp value
1311 unsigned Tmp4 = MakeReg(MVT::i32);
1312 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp4).addReg(getGlobalBaseReg())
1313 .addConstantPoolIndex(CPI);
1314 BuildMI(BB, PPC::LFD, 2, ConstF).addConstantPoolIndex(CPI).addReg(Tmp4);
1315 // Store the hi & low halves of the fp value, currently in int regs
1316 BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
1317 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
1318 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
1319 addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
1320 // Generate the return value with a subtract
1321 BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
1323 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, 0x1.000008p52);
1324 unsigned CPI = CP->getConstantPoolIndex(CFP);
1325 // Load constant fp value
1326 unsigned Tmp4 = MakeReg(MVT::i32);
1327 unsigned TmpL = MakeReg(MVT::i32);
1328 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp4).addReg(getGlobalBaseReg())
1329 .addConstantPoolIndex(CPI);
1330 BuildMI(BB, PPC::LFD, 2, ConstF).addConstantPoolIndex(CPI).addReg(Tmp4);
1331 // Store the hi & low halves of the fp value, currently in int regs
1332 BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
1333 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
1334 BuildMI(BB, PPC::XORIS, 2, TmpL).addReg(Tmp1).addImm(0x8000);
1335 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
1336 addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
1337 // Generate the return value with a subtract
1338 BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
1343 assert(0 && "Should never get here");
1347 unsigned ISel::SelectExpr(SDOperand N) {
1349 unsigned Tmp1, Tmp2, Tmp3;
1351 unsigned opcode = N.getOpcode();
1353 SDNode *Node = N.Val;
1354 MVT::ValueType DestType = N.getValueType();
1356 unsigned &Reg = ExprMap[N];
1357 if (Reg) return Reg;
1359 switch (N.getOpcode()) {
1361 Reg = Result = (N.getValueType() != MVT::Other) ?
1362 MakeReg(N.getValueType()) : 1;
1365 // If this is a call instruction, make sure to prepare ALL of the result
1366 // values as well as the chain.
1367 if (Node->getNumValues() == 1)
1368 Reg = Result = 1; // Void call, just a chain.
1370 Result = MakeReg(Node->getValueType(0));
1371 ExprMap[N.getValue(0)] = Result;
1372 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
1373 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1374 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
1377 case ISD::ADD_PARTS:
1378 case ISD::SUB_PARTS:
1379 case ISD::SHL_PARTS:
1380 case ISD::SRL_PARTS:
1381 case ISD::SRA_PARTS:
1382 Result = MakeReg(Node->getValueType(0));
1383 ExprMap[N.getValue(0)] = Result;
1384 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
1385 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1389 if (ISD::CopyFromReg == opcode)
1390 DestType = N.getValue(0).getValueType();
1392 if (DestType == MVT::f64 || DestType == MVT::f32)
1393 if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
1394 ISD::UNDEF != opcode && ISD::CALL != opcode)
1395 return SelectExprFP(N, Result);
1400 assert(0 && "Node not handled!\n");
1402 BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
1404 case ISD::DYNAMIC_STACKALLOC:
1405 // Generate both result values. FIXME: Need a better commment here?
1407 ExprMap[N.getValue(1)] = 1;
1409 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1411 // FIXME: We are currently ignoring the requested alignment for handling
1412 // greater than the stack alignment. This will need to be revisited at some
1413 // point. Align = N.getOperand(2);
1414 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
1415 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
1416 std::cerr << "Cannot allocate stack object with greater alignment than"
1417 << " the stack alignment yet!";
1420 Select(N.getOperand(0));
1421 Tmp1 = SelectExpr(N.getOperand(1));
1422 // Subtract size from stack pointer, thereby allocating some space.
1423 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
1424 // Put a pointer to the space into the result register by copying the SP
1425 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
1428 case ISD::ConstantPool:
1429 Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
1430 Tmp2 = MakeReg(MVT::i32);
1431 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
1432 .addConstantPoolIndex(Tmp1);
1433 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
1436 case ISD::FrameIndex:
1437 Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
1438 addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
1441 case ISD::GlobalAddress: {
1442 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
1443 Tmp1 = MakeReg(MVT::i32);
1444 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
1445 .addGlobalAddress(GV);
1446 if (GV->hasWeakLinkage() || GV->isExternal()) {
1447 BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
1449 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp1).addGlobalAddress(GV);
1457 case ISD::SEXTLOAD: {
1458 MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
1459 Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
1460 bool sext = (ISD::SEXTLOAD == opcode);
1462 // Make sure we generate both values.
1464 ExprMap[N.getValue(1)] = 1; // Generate the token
1466 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1468 SDOperand Chain = N.getOperand(0);
1469 SDOperand Address = N.getOperand(1);
1472 switch (TypeBeingLoaded) {
1473 default: Node->dump(); assert(0 && "Cannot load this type!");
1474 case MVT::i1: Opc = PPC::LBZ; break;
1475 case MVT::i8: Opc = PPC::LBZ; break;
1476 case MVT::i16: Opc = sext ? PPC::LHA : PPC::LHZ; break;
1477 case MVT::i32: Opc = PPC::LWZ; break;
1478 case MVT::f32: Opc = PPC::LFS; break;
1479 case MVT::f64: Opc = PPC::LFD; break;
1482 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
1483 Tmp1 = MakeReg(MVT::i32);
1484 int CPI = CP->getIndex();
1485 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
1486 .addConstantPoolIndex(CPI);
1487 BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
1489 else if(Address.getOpcode() == ISD::FrameIndex) {
1490 Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
1491 addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
1494 bool idx = SelectAddr(Address, Tmp1, offset);
1496 Opc = IndexedOpForOp(Opc);
1497 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(offset);
1499 BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
1506 unsigned GPR_idx = 0, FPR_idx = 0;
1507 static const unsigned GPR[] = {
1508 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1509 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1511 static const unsigned FPR[] = {
1512 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1513 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1516 // Lower the chain for this call.
1517 Select(N.getOperand(0));
1518 ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
1520 MachineInstr *CallMI;
1521 // Emit the correct call instruction based on the type of symbol called.
1522 if (GlobalAddressSDNode *GASD =
1523 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
1524 CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
1526 } else if (ExternalSymbolSDNode *ESSDN =
1527 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
1528 CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
1531 Tmp1 = SelectExpr(N.getOperand(1));
1532 BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
1533 BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
1534 CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
1538 // Load the register args to virtual regs
1539 std::vector<unsigned> ArgVR;
1540 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
1541 ArgVR.push_back(SelectExpr(N.getOperand(i)));
1543 // Copy the virtual registers into the appropriate argument register
1544 for(int i = 0, e = ArgVR.size(); i < e; ++i) {
1545 switch(N.getOperand(i+2).getValueType()) {
1546 default: Node->dump(); assert(0 && "Unknown value type for call");
1551 assert(GPR_idx < 8 && "Too many int args");
1552 if (N.getOperand(i+2).getOpcode() != ISD::UNDEF) {
1553 BuildMI(BB, PPC::OR,2,GPR[GPR_idx]).addReg(ArgVR[i]).addReg(ArgVR[i]);
1554 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1560 assert(FPR_idx < 13 && "Too many fp args");
1561 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgVR[i]);
1562 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1568 // Put the call instruction in the correct place in the MachineBasicBlock
1569 BB->push_back(CallMI);
1571 switch (Node->getValueType(0)) {
1572 default: assert(0 && "Unknown value type for call result!");
1573 case MVT::Other: return 1;
1578 if (Node->getValueType(1) == MVT::i32) {
1579 BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3);
1580 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R4).addReg(PPC::R4);
1582 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
1587 BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
1590 return Result+N.ResNo;
1593 case ISD::SIGN_EXTEND:
1594 case ISD::SIGN_EXTEND_INREG:
1595 Tmp1 = SelectExpr(N.getOperand(0));
1596 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1597 default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
1599 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
1602 BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
1605 BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
1610 case ISD::ZERO_EXTEND_INREG:
1611 Tmp1 = SelectExpr(N.getOperand(0));
1612 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1613 default: Node->dump(); assert(0 && "Unhandled ZERO_EXTEND type"); break;
1614 case MVT::i16: Tmp2 = 16; break;
1615 case MVT::i8: Tmp2 = 24; break;
1616 case MVT::i1: Tmp2 = 31; break;
1618 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(0).addImm(Tmp2)
1622 case ISD::CopyFromReg:
1624 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1625 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
1626 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
1630 Tmp1 = SelectExpr(N.getOperand(0));
1631 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1632 Tmp2 = CN->getValue() & 0x1F;
1633 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
1636 Tmp2 = SelectExpr(N.getOperand(1));
1637 BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1642 Tmp1 = SelectExpr(N.getOperand(0));
1643 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1644 Tmp2 = CN->getValue() & 0x1F;
1645 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(32-Tmp2)
1646 .addImm(Tmp2).addImm(31);
1648 Tmp2 = SelectExpr(N.getOperand(1));
1649 BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1654 Tmp1 = SelectExpr(N.getOperand(0));
1655 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1656 Tmp2 = CN->getValue() & 0x1F;
1657 BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1659 Tmp2 = SelectExpr(N.getOperand(1));
1660 BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1665 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
1666 Tmp1 = SelectExpr(N.getOperand(0));
1667 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1668 default: assert(0 && "unhandled result code");
1669 case 0: // No immediate
1670 Tmp2 = SelectExpr(N.getOperand(1));
1671 BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
1673 case 1: // Low immediate
1674 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1676 case 2: // Shifted immediate
1677 BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1683 Tmp1 = SelectExpr(N.getOperand(0));
1684 // FIXME: should add check in getImmediateForOpcode to return a value
1685 // indicating the immediate is a run of set bits so we can emit a bitfield
1686 // clear with RLWINM instead.
1687 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1688 default: assert(0 && "unhandled result code");
1689 case 0: // No immediate
1690 Tmp2 = SelectExpr(N.getOperand(1));
1691 BuildMI(BB, PPC::AND, 2, Result).addReg(Tmp1).addReg(Tmp2);
1693 case 1: // Low immediate
1694 BuildMI(BB, PPC::ANDIo, 2, Result).addReg(Tmp1).addImm(Tmp2);
1696 case 2: // Shifted immediate
1697 BuildMI(BB, PPC::ANDISo, 2, Result).addReg(Tmp1).addImm(Tmp2);
1703 if (SelectBitfieldInsert(N, Result))
1705 Tmp1 = SelectExpr(N.getOperand(0));
1706 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1707 default: assert(0 && "unhandled result code");
1708 case 0: // No immediate
1709 Tmp2 = SelectExpr(N.getOperand(1));
1710 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp2);
1712 case 1: // Low immediate
1713 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1715 case 2: // Shifted immediate
1716 BuildMI(BB, PPC::ORIS, 2, Result).addReg(Tmp1).addImm(Tmp2);
1722 // Check for EQV: xor, (xor a, -1), b
1723 if (N.getOperand(0).getOpcode() == ISD::XOR &&
1724 N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
1725 cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->isAllOnesValue()) {
1726 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1727 Tmp2 = SelectExpr(N.getOperand(1));
1728 BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
1731 // Check for NOT, NOR, and NAND: xor (copy, or, and), -1
1732 if (N.getOperand(1).getOpcode() == ISD::Constant &&
1733 cast<ConstantSDNode>(N.getOperand(1))->isAllOnesValue()) {
1734 switch(N.getOperand(0).getOpcode()) {
1736 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1737 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1738 BuildMI(BB, PPC::NOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
1741 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1742 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1743 BuildMI(BB, PPC::NAND, 2, Result).addReg(Tmp1).addReg(Tmp2);
1746 Tmp1 = SelectExpr(N.getOperand(0));
1747 BuildMI(BB, PPC::NOR, 2, Result).addReg(Tmp1).addReg(Tmp1);
1752 Tmp1 = SelectExpr(N.getOperand(0));
1753 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1754 default: assert(0 && "unhandled result code");
1755 case 0: // No immediate
1756 Tmp2 = SelectExpr(N.getOperand(1));
1757 BuildMI(BB, PPC::XOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
1759 case 1: // Low immediate
1760 BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1762 case 2: // Shifted immediate
1763 BuildMI(BB, PPC::XORIS, 2, Result).addReg(Tmp1).addImm(Tmp2);
1770 Tmp2 = SelectExpr(N.getOperand(1));
1771 if (1 == getImmediateForOpcode(N.getOperand(0), opcode, Tmp1))
1772 BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
1774 Tmp1 = SelectExpr(N.getOperand(0));
1775 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
1780 Tmp1 = SelectExpr(N.getOperand(0));
1781 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
1782 BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1784 Tmp2 = SelectExpr(N.getOperand(1));
1785 BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1791 Tmp1 = SelectExpr(N.getOperand(0));
1792 Tmp2 = SelectExpr(N.getOperand(1));
1793 Opc = (ISD::MULHU == opcode) ? PPC::MULHWU : PPC::MULHW;
1794 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1799 switch (getImmediateForOpcode(N.getOperand(1), opcode, Tmp3)) {
1801 // If this is an sdiv by a power of two, we can use an srawi/addze pair.
1803 Tmp1 = MakeReg(MVT::i32);
1804 Tmp2 = SelectExpr(N.getOperand(0));
1805 BuildMI(BB, PPC::SRAWI, 2, Tmp1).addReg(Tmp2).addImm(Tmp3);
1806 BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp1);
1808 // If this is a divide by constant, we can emit code using some magic
1809 // constants to implement it as a multiply instead.
1812 if (opcode == ISD::SDIV)
1813 return SelectExpr(BuildSDIVSequence(N));
1815 return SelectExpr(BuildUDIVSequence(N));
1817 Tmp1 = SelectExpr(N.getOperand(0));
1818 Tmp2 = SelectExpr(N.getOperand(1));
1819 Opc = (ISD::UDIV == opcode) ? PPC::DIVWU : PPC::DIVW;
1820 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1823 case ISD::ADD_PARTS:
1824 case ISD::SUB_PARTS: {
1825 assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
1826 "Not an i64 add/sub!");
1827 // Emit all of the operands.
1828 std::vector<unsigned> InVals;
1829 for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
1830 InVals.push_back(SelectExpr(N.getOperand(i)));
1831 if (N.getOpcode() == ISD::ADD_PARTS) {
1832 BuildMI(BB, PPC::ADDC, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
1833 BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
1835 BuildMI(BB, PPC::SUBFC, 2, Result).addReg(InVals[2]).addReg(InVals[0]);
1836 BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(InVals[3]).addReg(InVals[1]);
1838 return Result+N.ResNo;
1841 case ISD::SHL_PARTS:
1842 case ISD::SRA_PARTS:
1843 case ISD::SRL_PARTS: {
1844 assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
1845 "Not an i64 shift!");
1846 unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
1847 unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
1848 unsigned SHReg = SelectExpr(N.getOperand(2));
1849 Tmp1 = MakeReg(MVT::i32);
1850 Tmp2 = MakeReg(MVT::i32);
1851 Tmp3 = MakeReg(MVT::i32);
1852 unsigned Tmp4 = MakeReg(MVT::i32);
1853 unsigned Tmp5 = MakeReg(MVT::i32);
1854 unsigned Tmp6 = MakeReg(MVT::i32);
1855 BuildMI(BB, PPC::SUBFIC, 2, Tmp1).addReg(SHReg).addSImm(32);
1856 if (ISD::SHL_PARTS == opcode) {
1857 BuildMI(BB, PPC::SLW, 2, Tmp2).addReg(ShiftOpHi).addReg(SHReg);
1858 BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1);
1859 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
1860 BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
1861 BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpLo).addReg(Tmp5);
1862 BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6);
1863 BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg);
1864 } else if (ISD::SRL_PARTS == opcode) {
1865 BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
1866 BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
1867 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
1868 BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
1869 BuildMI(BB, PPC::SRW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
1870 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp4).addReg(Tmp6);
1871 BuildMI(BB, PPC::SRW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
1873 MachineBasicBlock *TmpMBB = new MachineBasicBlock(BB->getBasicBlock());
1874 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
1875 MachineBasicBlock *OldMBB = BB;
1876 MachineFunction *F = BB->getParent();
1877 ilist<MachineBasicBlock>::iterator It = BB; ++It;
1878 F->getBasicBlockList().insert(It, TmpMBB);
1879 F->getBasicBlockList().insert(It, PhiMBB);
1880 BB->addSuccessor(TmpMBB);
1881 BB->addSuccessor(PhiMBB);
1882 BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
1883 BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
1884 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
1885 BuildMI(BB, PPC::ADDICo, 2, Tmp5).addReg(SHReg).addSImm(-32);
1886 BuildMI(BB, PPC::SRAW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
1887 BuildMI(BB, PPC::SRAW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
1888 BuildMI(BB, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
1889 // Select correct least significant half if the shift amount > 32
1891 unsigned Tmp7 = MakeReg(MVT::i32);
1892 BuildMI(BB, PPC::OR, 2, Tmp7).addReg(Tmp6).addReg(Tmp6);
1893 TmpMBB->addSuccessor(PhiMBB);
1895 BuildMI(BB, PPC::PHI, 4, Result).addReg(Tmp4).addMBB(OldMBB)
1896 .addReg(Tmp7).addMBB(TmpMBB);
1898 return Result+N.ResNo;
1901 case ISD::FP_TO_UINT:
1902 case ISD::FP_TO_SINT: {
1903 bool U = (ISD::FP_TO_UINT == opcode);
1904 Tmp1 = SelectExpr(N.getOperand(0));
1906 Tmp2 = MakeReg(MVT::f64);
1907 BuildMI(BB, PPC::FCTIWZ, 1, Tmp2).addReg(Tmp1);
1908 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
1909 addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(Tmp2), FrameIdx);
1910 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Result), FrameIdx, 4);
1913 unsigned Zero = getConstDouble(0.0);
1914 unsigned MaxInt = getConstDouble((1LL << 32) - 1);
1915 unsigned Border = getConstDouble(1LL << 31);
1916 unsigned UseZero = MakeReg(MVT::f64);
1917 unsigned UseMaxInt = MakeReg(MVT::f64);
1918 unsigned UseChoice = MakeReg(MVT::f64);
1919 unsigned TmpReg = MakeReg(MVT::f64);
1920 unsigned TmpReg2 = MakeReg(MVT::f64);
1921 unsigned ConvReg = MakeReg(MVT::f64);
1922 unsigned IntTmp = MakeReg(MVT::i32);
1923 unsigned XorReg = MakeReg(MVT::i32);
1924 MachineFunction *F = BB->getParent();
1925 int FrameIdx = F->getFrameInfo()->CreateStackObject(8, 8);
1926 // Update machine-CFG edges
1927 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
1928 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
1929 MachineBasicBlock *OldMBB = BB;
1930 ilist<MachineBasicBlock>::iterator It = BB; ++It;
1931 F->getBasicBlockList().insert(It, XorMBB);
1932 F->getBasicBlockList().insert(It, PhiMBB);
1933 BB->addSuccessor(XorMBB);
1934 BB->addSuccessor(PhiMBB);
1935 // Convert from floating point to unsigned 32-bit value
1936 // Use 0 if incoming value is < 0.0
1937 BuildMI(BB, PPC::FSEL, 3, UseZero).addReg(Tmp1).addReg(Tmp1).addReg(Zero);
1938 // Use 2**32 - 1 if incoming value is >= 2**32
1939 BuildMI(BB, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(Tmp1);
1940 BuildMI(BB, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt).addReg(UseZero)
1943 BuildMI(BB, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
1944 // Use difference if >= 2**31
1945 BuildMI(BB, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice).addReg(Border);
1946 BuildMI(BB, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
1948 // Convert to integer
1949 BuildMI(BB, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
1950 addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(ConvReg), FrameIdx);
1951 addFrameReference(BuildMI(BB, PPC::LWZ, 2, IntTmp), FrameIdx, 4);
1952 BuildMI(BB, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
1953 BuildMI(BB, PPC::B, 1).addMBB(XorMBB);
1956 // add 2**31 if input was >= 2**31
1958 BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
1959 XorMBB->addSuccessor(PhiMBB);
1962 // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
1964 BuildMI(BB, PPC::PHI, 4, Result).addReg(IntTmp).addMBB(OldMBB)
1965 .addReg(XorReg).addMBB(XorMBB);
1968 assert(0 && "Should never get here");
1973 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
1974 // We can codegen setcc op, 0 very efficiently compared to a conditional
1975 // branch. Check for that here.
1976 if (ConstantSDNode *CN =
1977 dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
1978 if (CN->getValue() == 0) {
1979 Tmp1 = SelectExpr(SetCC->getOperand(0));
1980 switch (SetCC->getCondition()) {
1981 default: assert(0 && "Unhandled SetCC condition"); abort();
1984 Tmp2 = MakeReg(MVT::i32);
1985 BuildMI(BB, PPC::CNTLZW, 1, Tmp2).addReg(Tmp1);
1986 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp2).addImm(27)
1987 .addImm(5).addImm(31);
1991 Tmp2 = MakeReg(MVT::i32);
1992 BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(-1);
1993 BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp2).addReg(Tmp1);
1996 BuildMI(BB, PPC::LI, 1, Result).addSImm(0);
1999 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(1)
2000 .addImm(31).addImm(31);
2003 Tmp2 = MakeReg(MVT::i32);
2004 Tmp3 = MakeReg(MVT::i32);
2005 BuildMI(BB, PPC::NEG, 2, Tmp2).addReg(Tmp1);
2006 BuildMI(BB, PPC::ORC, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
2007 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
2008 .addImm(31).addImm(31);
2011 Tmp2 = MakeReg(MVT::i32);
2012 Tmp3 = MakeReg(MVT::i32);
2013 BuildMI(BB, PPC::NEG, 2, Tmp2).addReg(Tmp1);
2014 BuildMI(BB, PPC::ANDC, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
2015 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
2016 .addImm(31).addImm(31);
2019 BuildMI(BB, PPC::LI, 1, Result).addSImm(1);
2022 BuildMI(BB, PPC::RLWINM, 4, Tmp2).addReg(Tmp1).addImm(1)
2023 .addImm(31).addImm(31);
2024 BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp2).addImm(1);
2031 Opc = SelectSetCR0(N);
2032 unsigned TrueValue = MakeReg(MVT::i32);
2033 BuildMI(BB, PPC::LI, 1, TrueValue).addSImm(1);
2034 unsigned FalseValue = MakeReg(MVT::i32);
2035 BuildMI(BB, PPC::LI, 1, FalseValue).addSImm(0);
2037 // Create an iterator with which to insert the MBB for copying the false
2038 // value and the MBB to hold the PHI instruction for this SetCC.
2039 MachineBasicBlock *thisMBB = BB;
2040 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2041 ilist<MachineBasicBlock>::iterator It = BB;
2046 // cmpTY cr0, r1, r2
2047 // %TrueValue = li 1
2049 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2050 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2051 BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
2052 MachineFunction *F = BB->getParent();
2053 F->getBasicBlockList().insert(It, copy0MBB);
2054 F->getBasicBlockList().insert(It, sinkMBB);
2055 // Update machine-CFG edges
2056 BB->addSuccessor(copy0MBB);
2057 BB->addSuccessor(sinkMBB);
2060 // %FalseValue = li 0
2063 // Update machine-CFG edges
2064 BB->addSuccessor(sinkMBB);
2067 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2070 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
2071 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
2074 assert(0 && "Is this legal?");
2078 // We can codegen select (a < 0) ? b : 0 very efficiently compared to a
2079 // conditional branch. Check for that here.
2080 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val)) {
2081 if (ConstantSDNode *CN =
2082 dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
2083 if (ConstantSDNode *CNF =
2084 dyn_cast<ConstantSDNode>(N.getOperand(2).Val)) {
2085 if (CN->getValue() == 0 && CNF->getValue() == 0 &&
2086 SetCC->getCondition() == ISD::SETLT) {
2087 Tmp1 = SelectExpr(N.getOperand(1)); // TRUE value
2088 Tmp2 = SelectExpr(SetCC->getOperand(0));
2089 Tmp3 = MakeReg(MVT::i32);
2090 BuildMI(BB, PPC::SRAWI, 2, Tmp3).addReg(Tmp2).addImm(31);
2091 BuildMI(BB, PPC::AND, 2, Result).addReg(Tmp1).addReg(Tmp3);
2097 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
2098 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
2099 Opc = SelectSetCR0(N.getOperand(0));
2101 // Create an iterator with which to insert the MBB for copying the false
2102 // value and the MBB to hold the PHI instruction for this SetCC.
2103 MachineBasicBlock *thisMBB = BB;
2104 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2105 ilist<MachineBasicBlock>::iterator It = BB;
2111 // cmpTY cr0, r1, r2
2113 // fallthrough --> copy0MBB
2114 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2115 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2116 BuildMI(BB, Opc, 2).addReg(PPC::CR0).addMBB(sinkMBB);
2117 MachineFunction *F = BB->getParent();
2118 F->getBasicBlockList().insert(It, copy0MBB);
2119 F->getBasicBlockList().insert(It, sinkMBB);
2120 // Update machine-CFG edges
2121 BB->addSuccessor(copy0MBB);
2122 BB->addSuccessor(sinkMBB);
2125 // %FalseValue = ...
2126 // # fallthrough to sinkMBB
2128 // Update machine-CFG edges
2129 BB->addSuccessor(sinkMBB);
2132 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2135 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
2136 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
2141 switch (N.getValueType()) {
2142 default: assert(0 && "Cannot use constants of this type!");
2144 BuildMI(BB, PPC::LI, 1, Result)
2145 .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
2149 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
2150 if (v < 32768 && v >= -32768) {
2151 BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
2153 Tmp1 = MakeReg(MVT::i32);
2154 BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
2155 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
2165 void ISel::Select(SDOperand N) {
2166 unsigned Tmp1, Tmp2, Opc;
2167 unsigned opcode = N.getOpcode();
2169 if (!ExprMap.insert(std::make_pair(N, 1)).second)
2170 return; // Already selected.
2172 SDNode *Node = N.Val;
2174 switch (Node->getOpcode()) {
2176 Node->dump(); std::cerr << "\n";
2177 assert(0 && "Node not handled yet!");
2178 case ISD::EntryToken: return; // Noop
2179 case ISD::TokenFactor:
2180 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
2181 Select(Node->getOperand(i));
2183 case ISD::ADJCALLSTACKDOWN:
2184 case ISD::ADJCALLSTACKUP:
2185 Select(N.getOperand(0));
2186 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
2187 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? PPC::ADJCALLSTACKDOWN :
2188 PPC::ADJCALLSTACKUP;
2189 BuildMI(BB, Opc, 1).addImm(Tmp1);
2192 MachineBasicBlock *Dest =
2193 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
2194 Select(N.getOperand(0));
2195 BuildMI(BB, PPC::B, 1).addMBB(Dest);
2199 case ISD::BRCONDTWOWAY:
2202 case ISD::CopyToReg:
2203 Select(N.getOperand(0));
2204 Tmp1 = SelectExpr(N.getOperand(1));
2205 Tmp2 = cast<RegSDNode>(N)->getReg();
2208 if (N.getOperand(1).getValueType() == MVT::f64 ||
2209 N.getOperand(1).getValueType() == MVT::f32)
2210 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
2212 BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
2215 case ISD::ImplicitDef:
2216 Select(N.getOperand(0));
2217 BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
2220 switch (N.getNumOperands()) {
2222 assert(0 && "Unknown return instruction!");
2224 assert(N.getOperand(1).getValueType() == MVT::i32 &&
2225 N.getOperand(2).getValueType() == MVT::i32 &&
2226 "Unknown two-register value!");
2227 Select(N.getOperand(0));
2228 Tmp1 = SelectExpr(N.getOperand(1));
2229 Tmp2 = SelectExpr(N.getOperand(2));
2230 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp2).addReg(Tmp2);
2231 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp1).addReg(Tmp1);
2234 Select(N.getOperand(0));
2235 Tmp1 = SelectExpr(N.getOperand(1));
2236 switch (N.getOperand(1).getValueType()) {
2238 assert(0 && "Unknown return type!");
2241 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
2244 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
2248 Select(N.getOperand(0));
2251 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
2253 case ISD::TRUNCSTORE:
2256 SDOperand Chain = N.getOperand(0);
2257 SDOperand Value = N.getOperand(1);
2258 SDOperand Address = N.getOperand(2);
2261 Tmp1 = SelectExpr(Value); //value
2263 if (opcode == ISD::STORE) {
2264 switch(Value.getValueType()) {
2265 default: assert(0 && "unknown Type in store");
2266 case MVT::i32: Opc = PPC::STW; break;
2267 case MVT::f64: Opc = PPC::STFD; break;
2268 case MVT::f32: Opc = PPC::STFS; break;
2270 } else { //ISD::TRUNCSTORE
2271 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
2272 default: assert(0 && "unknown Type in store");
2274 case MVT::i8: Opc = PPC::STB; break;
2275 case MVT::i16: Opc = PPC::STH; break;
2279 if(Address.getOpcode() == ISD::FrameIndex)
2281 Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
2282 addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
2287 bool idx = SelectAddr(Address, Tmp2, offset);
2289 Opc = IndexedOpForOp(Opc);
2290 BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
2292 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
2301 case ISD::CopyFromReg:
2303 case ISD::DYNAMIC_STACKALLOC:
2308 assert(0 && "Should not be reached!");
2312 /// createPPC32PatternInstructionSelector - This pass converts an LLVM function
2313 /// into a machine code representation using pattern matching and a machine
2314 /// description file.
2316 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
2317 return new ISel(TM);