1 //===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
11 // Magic number generation for integer divide from the PowerPC Compiler Writer's
12 // Guide, section 3.2.3.5
14 //===----------------------------------------------------------------------===//
17 #include "PowerPCInstrBuilder.h"
18 #include "PowerPCInstrInfo.h"
19 #include "PPC32TargetMachine.h"
20 #include "llvm/Constants.h" // FIXME: REMOVE
21 #include "llvm/Function.h"
22 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
23 #include "llvm/CodeGen/MachineFunction.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/SelectionDAG.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/SSARegMap.h"
28 #include "llvm/Target/TargetData.h"
29 #include "llvm/Target/TargetLowering.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/MathExtras.h"
33 #include "llvm/ADT/Statistic.h"
38 //===----------------------------------------------------------------------===//
39 // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
41 class PPC32TargetLowering : public TargetLowering {
42 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
43 int ReturnAddrIndex; // FrameIndex for return slot.
45 PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
46 // Fold away setcc operations if possible.
47 setSetCCIsExpensive();
49 // Set up the register classes.
50 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
51 addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);
52 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
54 // PowerPC has no intrinsics for these particular operations
55 setOperationAction(ISD::MEMMOVE, MVT::Other, Expand);
56 setOperationAction(ISD::MEMSET, MVT::Other, Expand);
57 setOperationAction(ISD::MEMCPY, MVT::Other, Expand);
59 // PowerPC has an i16 but no i8 (or i1) SEXTLOAD
60 setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
61 setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
63 // PowerPC has no SREM/UREM instructions
64 setOperationAction(ISD::SREM, MVT::i32, Expand);
65 setOperationAction(ISD::UREM, MVT::i32, Expand);
67 // We don't support sin/cos/sqrt/fmod
68 setOperationAction(ISD::FSIN , MVT::f64, Expand);
69 setOperationAction(ISD::FCOS , MVT::f64, Expand);
70 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
71 setOperationAction(ISD::SREM , MVT::f64, Expand);
72 setOperationAction(ISD::FSIN , MVT::f32, Expand);
73 setOperationAction(ISD::FCOS , MVT::f32, Expand);
74 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
75 setOperationAction(ISD::SREM , MVT::f32, Expand);
77 //PowerPC does not have CTPOP or CTTZ
78 setOperationAction(ISD::CTPOP, MVT::i32 , Expand);
79 setOperationAction(ISD::CTTZ , MVT::i32 , Expand);
81 setSetCCResultContents(ZeroOrOneSetCCResult);
82 addLegalFPImmediate(+0.0); // Necessary for FSEL
83 addLegalFPImmediate(-0.0); //
85 computeRegisterProperties();
88 /// LowerArguments - This hook must be implemented to indicate how we should
89 /// lower the arguments for the specified function, into the specified DAG.
90 virtual std::vector<SDOperand>
91 LowerArguments(Function &F, SelectionDAG &DAG);
93 /// LowerCallTo - This hook lowers an abstract call to a function into an
95 virtual std::pair<SDOperand, SDOperand>
96 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg, unsigned CC,
97 bool isTailCall, SDOperand Callee, ArgListTy &Args,
100 virtual SDOperand LowerVAStart(SDOperand Chain, SDOperand VAListP,
101 Value *VAListV, SelectionDAG &DAG);
103 virtual std::pair<SDOperand,SDOperand>
104 LowerVAArg(SDOperand Chain, SDOperand VAListP, Value *VAListV,
105 const Type *ArgTy, SelectionDAG &DAG);
107 virtual std::pair<SDOperand, SDOperand>
108 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
114 std::vector<SDOperand>
115 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
117 // add beautiful description of PPC stack frame format, or at least some docs
119 MachineFunction &MF = DAG.getMachineFunction();
120 MachineFrameInfo *MFI = MF.getFrameInfo();
121 MachineBasicBlock& BB = MF.front();
122 std::vector<SDOperand> ArgValues;
124 // Due to the rather complicated nature of the PowerPC ABI, rather than a
125 // fixed size array of physical args, for the sake of simplicity let the STL
126 // handle tracking them for us.
127 std::vector<unsigned> argVR, argPR, argOp;
128 unsigned ArgOffset = 24;
129 unsigned GPR_remaining = 8;
130 unsigned FPR_remaining = 13;
131 unsigned GPR_idx = 0, FPR_idx = 0;
132 static const unsigned GPR[] = {
133 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
134 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
136 static const unsigned FPR[] = {
137 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
138 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
141 // Add DAG nodes to load the arguments... On entry to a function on PPC,
142 // the arguments start at offset 24, although they are likely to be passed
144 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
145 SDOperand newroot, argt;
147 bool needsLoad = false;
148 bool ArgLive = !I->use_empty();
149 MVT::ValueType ObjectVT = getValueType(I->getType());
152 default: assert(0 && "Unhandled argument type!");
159 if (GPR_remaining > 0) {
160 MF.addLiveIn(GPR[GPR_idx]);
161 argt = newroot = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32,
163 if (ObjectVT != MVT::i32)
164 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
169 case MVT::i64: ObjSize = 8;
171 if (GPR_remaining > 0) {
172 SDOperand argHi, argLo;
173 MF.addLiveIn(GPR[GPR_idx]);
174 argHi = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
175 // If we have two or more remaining argument registers, then both halves
176 // of the i64 can be sourced from there. Otherwise, the lower half will
177 // have to come off the stack. This can happen when an i64 is preceded
178 // by 28 bytes of arguments.
179 if (GPR_remaining > 1) {
180 MF.addLiveIn(GPR[GPR_idx+1]);
181 argLo = DAG.getCopyFromReg(GPR[GPR_idx+1], MVT::i32, argHi);
183 int FI = MFI->CreateFixedObject(4, ArgOffset+4);
184 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
185 argLo = DAG.getLoad(MVT::i32, DAG.getEntryNode(), FIN,
186 DAG.getSrcValue(NULL));
188 // Build the outgoing arg thingy
189 argt = DAG.getNode(ISD::BUILD_PAIR, MVT::i64, argLo, argHi);
197 ObjSize = (ObjectVT == MVT::f64) ? 8 : 4;
199 if (FPR_remaining > 0) {
200 MF.addLiveIn(FPR[FPR_idx]);
201 argt = newroot = DAG.getCopyFromReg(FPR[FPR_idx], ObjectVT,
211 // We need to load the argument to a virtual register if we determined above
212 // that we ran out of physical registers of the appropriate type
214 unsigned SubregOffset = 0;
215 if (ObjectVT == MVT::i8 || ObjectVT == MVT::i1) SubregOffset = 3;
216 if (ObjectVT == MVT::i16) SubregOffset = 2;
217 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
218 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
219 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
220 DAG.getConstant(SubregOffset, MVT::i32));
221 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN,
222 DAG.getSrcValue(NULL));
225 // Every 4 bytes of argument space consumes one of the GPRs available for
227 if (GPR_remaining > 0) {
228 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
229 GPR_remaining -= delta;
232 ArgOffset += ObjSize;
234 DAG.setRoot(newroot.getValue(1));
236 ArgValues.push_back(argt);
239 // If the function takes variable number of arguments, make a frame index for
240 // the start of the first vararg value... for expansion of llvm.va_start.
242 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
243 SDOperand FIN = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
244 // If this function is vararg, store any remaining integer argument regs
245 // to their spots on the stack so that they may be loaded by deferencing the
246 // result of va_next.
247 std::vector<SDOperand> MemOps;
248 for (; GPR_remaining > 0; --GPR_remaining, ++GPR_idx) {
249 MF.addLiveIn(GPR[GPR_idx]);
250 SDOperand Val = DAG.getCopyFromReg(GPR[GPR_idx], MVT::i32, DAG.getRoot());
251 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1),
252 Val, FIN, DAG.getSrcValue(NULL));
253 MemOps.push_back(Store);
254 // Increment the address by four for the next argument to store
255 SDOperand PtrOff = DAG.getConstant(4, getPointerTy());
256 FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN, PtrOff);
258 DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps));
261 // Finally, inform the code generator which regs we return values in.
262 switch (getValueType(F.getReturnType())) {
263 default: assert(0 && "Unknown type!");
264 case MVT::isVoid: break;
269 MF.addLiveOut(PPC::R3);
272 MF.addLiveOut(PPC::R3);
273 MF.addLiveOut(PPC::R4);
277 MF.addLiveOut(PPC::F1);
284 std::pair<SDOperand, SDOperand>
285 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
286 const Type *RetTy, bool isVarArg,
287 unsigned CallingConv, bool isTailCall,
288 SDOperand Callee, ArgListTy &Args,
290 // args_to_use will accumulate outgoing args for the ISD::CALL case in
291 // SelectExpr to use to put the arguments in the appropriate registers.
292 std::vector<SDOperand> args_to_use;
294 // Count how many bytes are to be pushed on the stack, including the linkage
295 // area, and parameter passing area.
296 unsigned NumBytes = 24;
299 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
300 DAG.getConstant(NumBytes, getPointerTy()));
302 for (unsigned i = 0, e = Args.size(); i != e; ++i)
303 switch (getValueType(Args[i].second)) {
304 default: assert(0 && "Unknown value type!");
318 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
319 // plus 32 bytes of argument space in case any called code gets funky on us.
320 if (NumBytes < 56) NumBytes = 56;
322 // Adjust the stack pointer for the new arguments...
323 // These operations are automatically eliminated by the prolog/epilog pass
324 Chain = DAG.getNode(ISD::CALLSEQ_START, MVT::Other, Chain,
325 DAG.getConstant(NumBytes, getPointerTy()));
327 // Set up a copy of the stack pointer for use loading and storing any
328 // arguments that may not fit in the registers available for argument
330 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
333 // Figure out which arguments are going to go in registers, and which in
334 // memory. Also, if this is a vararg function, floating point operations
335 // must be stored to our stack, and loaded into integer regs as well, if
336 // any integer regs are available for argument passing.
337 unsigned ArgOffset = 24;
338 unsigned GPR_remaining = 8;
339 unsigned FPR_remaining = 13;
341 std::vector<SDOperand> MemOps;
342 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
343 // PtrOff will be used to store the current argument to the stack if a
344 // register cannot be found for it.
345 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
346 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
347 MVT::ValueType ArgVT = getValueType(Args[i].second);
350 default: assert(0 && "Unexpected ValueType for argument!");
354 // Promote the integer to 32 bits. If the input type is signed use a
355 // sign extend, otherwise use a zero extend.
356 if (Args[i].second->isSigned())
357 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
359 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
362 if (GPR_remaining > 0) {
363 args_to_use.push_back(Args[i].first);
366 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
367 Args[i].first, PtrOff,
368 DAG.getSrcValue(NULL)));
373 // If we have one free GPR left, we can place the upper half of the i64
374 // in it, and store the other half to the stack. If we have two or more
375 // free GPRs, then we can pass both halves of the i64 in registers.
376 if (GPR_remaining > 0) {
377 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
378 Args[i].first, DAG.getConstant(1, MVT::i32));
379 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
380 Args[i].first, DAG.getConstant(0, MVT::i32));
381 args_to_use.push_back(Hi);
383 if (GPR_remaining > 0) {
384 args_to_use.push_back(Lo);
387 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
388 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
389 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
390 Lo, PtrOff, DAG.getSrcValue(NULL)));
393 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
394 Args[i].first, PtrOff,
395 DAG.getSrcValue(NULL)));
401 if (FPR_remaining > 0) {
402 args_to_use.push_back(Args[i].first);
405 SDOperand Store = DAG.getNode(ISD::STORE, MVT::Other, Chain,
406 Args[i].first, PtrOff,
407 DAG.getSrcValue(NULL));
408 MemOps.push_back(Store);
409 // Float varargs are always shadowed in available integer registers
410 if (GPR_remaining > 0) {
411 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
412 DAG.getSrcValue(NULL));
413 MemOps.push_back(Load);
414 args_to_use.push_back(Load);
417 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
418 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
419 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
420 SDOperand Load = DAG.getLoad(MVT::i32, Store, PtrOff,
421 DAG.getSrcValue(NULL));
422 MemOps.push_back(Load);
423 args_to_use.push_back(Load);
427 // If we have any FPRs remaining, we may also have GPRs remaining.
428 // Args passed in FPRs consume either 1 (f32) or 2 (f64) available
430 if (GPR_remaining > 0) {
431 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
434 if (GPR_remaining > 0 && MVT::f64 == ArgVT) {
435 args_to_use.push_back(DAG.getNode(ISD::UNDEF, MVT::i32));
440 MemOps.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
441 Args[i].first, PtrOff,
442 DAG.getSrcValue(NULL)));
444 ArgOffset += (ArgVT == MVT::f32) ? 4 : 8;
449 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
452 std::vector<MVT::ValueType> RetVals;
453 MVT::ValueType RetTyVT = getValueType(RetTy);
454 if (RetTyVT != MVT::isVoid)
455 RetVals.push_back(RetTyVT);
456 RetVals.push_back(MVT::Other);
458 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
459 Chain, Callee, args_to_use), 0);
460 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
461 Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
462 DAG.getConstant(NumBytes, getPointerTy()));
463 return std::make_pair(TheCall, Chain);
466 SDOperand PPC32TargetLowering::LowerVAStart(SDOperand Chain, SDOperand VAListP,
467 Value *VAListV, SelectionDAG &DAG) {
468 // vastart just stores the address of the VarArgsFrameIndex slot into the
469 // memory location argument.
470 SDOperand FR = DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32);
471 return DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
472 DAG.getSrcValue(VAListV));
475 std::pair<SDOperand,SDOperand>
476 PPC32TargetLowering::LowerVAArg(SDOperand Chain,
477 SDOperand VAListP, Value *VAListV,
478 const Type *ArgTy, SelectionDAG &DAG) {
479 MVT::ValueType ArgVT = getValueType(ArgTy);
482 DAG.getLoad(MVT::i32, Chain, VAListP, DAG.getSrcValue(VAListV));
483 SDOperand Result = DAG.getLoad(ArgVT, Chain, VAList, DAG.getSrcValue(NULL));
485 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
488 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
489 "Other types should have been promoted for varargs!");
492 VAList = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
493 DAG.getConstant(Amt, VAList.getValueType()));
494 Chain = DAG.getNode(ISD::STORE, MVT::Other, Chain,
495 VAList, VAListP, DAG.getSrcValue(VAListV));
496 return std::make_pair(Result, Chain);
500 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
501 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
503 assert(0 && "LowerFrameReturnAddress unimplemented");
508 Statistic<>Recorded("ppc-codegen", "Number of recording ops emitted");
509 Statistic<>FusedFP("ppc-codegen", "Number of fused fp operations");
510 Statistic<>MultiBranch("ppc-codegen", "Number of setcc logical ops collapsed");
511 //===--------------------------------------------------------------------===//
512 /// ISel - PPC32 specific code to select PPC32 machine instructions for
513 /// SelectionDAG operations.
514 //===--------------------------------------------------------------------===//
515 class ISel : public SelectionDAGISel {
516 PPC32TargetLowering PPC32Lowering;
517 SelectionDAG *ISelDAG; // Hack to support us having a dag->dag transform
518 // for sdiv and udiv until it is put into the future
521 /// ExprMap - As shared expressions are codegen'd, we keep track of which
522 /// vreg the value is produced in, so we only emit one copy of each compiled
524 std::map<SDOperand, unsigned> ExprMap;
526 unsigned GlobalBaseReg;
527 bool GlobalBaseInitialized;
530 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM),
533 /// runOnFunction - Override this function in order to reset our per-function
535 virtual bool runOnFunction(Function &Fn) {
536 // Make sure we re-emit a set of the global base reg if necessary
537 GlobalBaseInitialized = false;
538 return SelectionDAGISel::runOnFunction(Fn);
541 /// InstructionSelectBasicBlock - This callback is invoked by
542 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
543 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
545 // Codegen the basic block.
547 Select(DAG.getRoot());
549 // Clear state used for selection.
554 // dag -> dag expanders for integer divide by constant
555 SDOperand BuildSDIVSequence(SDOperand N);
556 SDOperand BuildUDIVSequence(SDOperand N);
558 unsigned getGlobalBaseReg();
559 unsigned getConstDouble(double floatVal, unsigned Result);
560 void MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result);
561 bool SelectBitfieldInsert(SDOperand OR, unsigned Result);
562 unsigned FoldIfWideZeroExtend(SDOperand N);
563 unsigned SelectCC(SDOperand CC, unsigned &Opc, bool &Inv, unsigned &Idx);
564 unsigned SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv, unsigned &Idx);
565 unsigned SelectExpr(SDOperand N, bool Recording=false);
566 unsigned SelectExprFP(SDOperand N, unsigned Result);
567 void Select(SDOperand N);
569 bool SelectAddr(SDOperand N, unsigned& Reg, int& offset);
570 void SelectBranchCC(SDOperand N);
573 /// ExactLog2 - This function solves for (Val == 1 << (N-1)) and returns N. It
574 /// returns zero when the input is not exactly a power of two.
575 static unsigned ExactLog2(unsigned Val) {
576 if (Val == 0 || (Val & (Val-1))) return 0;
585 // IsRunOfOnes - returns true if Val consists of one contiguous run of 1's with
586 // any number of 0's on either side. the 1's are allowed to wrap from LSB to
587 // MSB. so 0x000FFF0, 0x0000FFFF, and 0xFF0000FF are all runs. 0x0F0F0000 is
588 // not, since all 1's are not contiguous.
589 static bool IsRunOfOnes(unsigned Val, unsigned &MB, unsigned &ME) {
594 // look for first set bit
596 for (; i < 32; i++) {
597 if ((Val & (1 << (31 - i))) != 0) {
604 // look for last set bit
605 for (; i < 32; i++) {
606 if ((Val & (1 << (31 - i))) == 0)
611 // look for next set bit
612 for (; i < 32; i++) {
613 if ((Val & (1 << (31 - i))) != 0)
617 // if we exhausted all the bits, we found a match at this point for 0*1*0*
621 // since we just encountered more 1's, if it doesn't wrap around to the
622 // most significant bit of the word, then we did not find a match to 1*0*1* so
627 // look for last set bit
628 for (MB = i; i < 32; i++) {
629 if ((Val & (1 << (31 - i))) == 0)
633 // if we exhausted all the bits, then we found a match for 1*0*1*, otherwise,
634 // the value is not a run of ones.
640 /// getImmediateForOpcode - This method returns a value indicating whether
641 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
642 /// values are either 0, 1 or 2. 0 indicates that either N is not a
643 /// ConstantSDNode, or is not suitable for use by that opcode.
644 /// Return value codes for turning into an enum someday:
645 /// 1: constant may be used in normal immediate form.
646 /// 2: constant may be used in shifted immediate form.
647 /// 3: log base 2 of the constant may be used.
648 /// 4: constant is suitable for integer division conversion
649 /// 5: constant is a bitfield mask
651 static unsigned getImmediateForOpcode(SDOperand N, unsigned Opcode,
652 unsigned& Imm, bool U = false) {
653 if (N.getOpcode() != ISD::Constant) return 0;
655 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
660 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
661 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
665 if (IsRunOfOnes(v, MB, ME)) { Imm = MB << 16 | ME & 0xFFFF; return 5; }
666 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
667 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
672 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
673 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
676 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
679 // handle subtract-from separately from subtract, since subi is really addi
680 if (U && v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
681 if (!U && v <= 32768 && v >= -32767) { Imm = (-v) & 0xFFFF; return 1; }
684 if (U && (v >= 0 && v <= 65535)) { Imm = v & 0xFFFF; return 1; }
685 if (!U && (v <= 32767 && v >= -32768)) { Imm = v & 0xFFFF; return 1; }
688 if ((Imm = ExactLog2(v))) { return 3; }
689 if ((Imm = ExactLog2(-v))) { Imm = -Imm; return 3; }
690 if (v <= -2 || v >= 2) { return 4; }
693 if (v > 1) { return 4; }
699 /// NodeHasRecordingVariant - If SelectExpr can always produce code for
700 /// NodeOpcode that also sets CR0 as a side effect, return true. Otherwise,
702 static bool NodeHasRecordingVariant(unsigned NodeOpcode) {
704 default: return false;
711 /// getBCCForSetCC - Returns the PowerPC condition branch mnemonic corresponding
712 /// to Condition. If the Condition is unordered or unsigned, the bool argument
713 /// U is set to true, otherwise it is set to false.
714 static unsigned getBCCForSetCC(unsigned Condition, bool& U) {
717 default: assert(0 && "Unknown condition!"); abort();
718 case ISD::SETEQ: return PPC::BEQ;
719 case ISD::SETNE: return PPC::BNE;
720 case ISD::SETULT: U = true;
721 case ISD::SETLT: return PPC::BLT;
722 case ISD::SETULE: U = true;
723 case ISD::SETLE: return PPC::BLE;
724 case ISD::SETUGT: U = true;
725 case ISD::SETGT: return PPC::BGT;
726 case ISD::SETUGE: U = true;
727 case ISD::SETGE: return PPC::BGE;
732 /// getCROpForOp - Return the condition register opcode (or inverted opcode)
733 /// associated with the SelectionDAG opcode.
734 static unsigned getCROpForSetCC(unsigned Opcode, bool Inv1, bool Inv2) {
736 default: assert(0 && "Unknown opcode!"); abort();
738 if (Inv1 && Inv2) return PPC::CRNOR; // De Morgan's Law
739 if (!Inv1 && !Inv2) return PPC::CRAND;
740 if (Inv1 ^ Inv2) return PPC::CRANDC;
742 if (Inv1 && Inv2) return PPC::CRNAND; // De Morgan's Law
743 if (!Inv1 && !Inv2) return PPC::CROR;
744 if (Inv1 ^ Inv2) return PPC::CRORC;
749 /// getCRIdxForSetCC - Return the index of the condition register field
750 /// associated with the SetCC condition, and whether or not the field is
751 /// treated as inverted. That is, lt = 0; ge = 0 inverted.
752 static unsigned getCRIdxForSetCC(unsigned Condition, bool& Inv) {
754 default: assert(0 && "Unknown condition!"); abort();
756 case ISD::SETLT: Inv = false; return 0;
758 case ISD::SETGE: Inv = true; return 0;
760 case ISD::SETGT: Inv = false; return 1;
762 case ISD::SETLE: Inv = true; return 1;
763 case ISD::SETEQ: Inv = false; return 2;
764 case ISD::SETNE: Inv = true; return 2;
769 /// IndexedOpForOp - Return the indexed variant for each of the PowerPC load
770 /// and store immediate instructions.
771 static unsigned IndexedOpForOp(unsigned Opcode) {
773 default: assert(0 && "Unknown opcode!"); abort();
774 case PPC::LBZ: return PPC::LBZX; case PPC::STB: return PPC::STBX;
775 case PPC::LHZ: return PPC::LHZX; case PPC::STH: return PPC::STHX;
776 case PPC::LHA: return PPC::LHAX; case PPC::STW: return PPC::STWX;
777 case PPC::LWZ: return PPC::LWZX; case PPC::STFS: return PPC::STFSX;
778 case PPC::LFS: return PPC::LFSX; case PPC::STFD: return PPC::STFDX;
779 case PPC::LFD: return PPC::LFDX;
784 // Structure used to return the necessary information to codegen an SDIV as
787 int m; // magic number
788 int s; // shift amount
792 unsigned int m; // magic number
793 int a; // add indicator
794 int s; // shift amount
797 /// magic - calculate the magic numbers required to codegen an integer sdiv as
798 /// a sequence of multiply and shifts. Requires that the divisor not be 0, 1,
800 static struct ms magic(int d) {
802 unsigned int ad, anc, delta, q1, r1, q2, r2, t;
803 const unsigned int two31 = 2147483648U; // 2^31
807 t = two31 + ((unsigned int)d >> 31);
808 anc = t - 1 - t%ad; // absolute value of nc
809 p = 31; // initialize p
810 q1 = two31/anc; // initialize q1 = 2p/abs(nc)
811 r1 = two31 - q1*anc; // initialize r1 = rem(2p,abs(nc))
812 q2 = two31/ad; // initialize q2 = 2p/abs(d)
813 r2 = two31 - q2*ad; // initialize r2 = rem(2p,abs(d))
816 q1 = 2*q1; // update q1 = 2p/abs(nc)
817 r1 = 2*r1; // update r1 = rem(2p/abs(nc))
818 if (r1 >= anc) { // must be unsigned comparison
822 q2 = 2*q2; // update q2 = 2p/abs(d)
823 r2 = 2*r2; // update r2 = rem(2p/abs(d))
824 if (r2 >= ad) { // must be unsigned comparison
829 } while (q1 < delta || (q1 == delta && r1 == 0));
832 if (d < 0) mag.m = -mag.m; // resulting magic number
833 mag.s = p - 32; // resulting shift
837 /// magicu - calculate the magic numbers required to codegen an integer udiv as
838 /// a sequence of multiply, add and shifts. Requires that the divisor not be 0.
839 static struct mu magicu(unsigned d)
842 unsigned int nc, delta, q1, r1, q2, r2;
844 magu.a = 0; // initialize "add" indicator
846 p = 31; // initialize p
847 q1 = 0x80000000/nc; // initialize q1 = 2p/nc
848 r1 = 0x80000000 - q1*nc; // initialize r1 = rem(2p,nc)
849 q2 = 0x7FFFFFFF/d; // initialize q2 = (2p-1)/d
850 r2 = 0x7FFFFFFF - q2*d; // initialize r2 = rem((2p-1),d)
853 if (r1 >= nc - r1 ) {
854 q1 = 2*q1 + 1; // update q1
855 r1 = 2*r1 - nc; // update r1
858 q1 = 2*q1; // update q1
859 r1 = 2*r1; // update r1
861 if (r2 + 1 >= d - r2) {
862 if (q2 >= 0x7FFFFFFF) magu.a = 1;
863 q2 = 2*q2 + 1; // update q2
864 r2 = 2*r2 + 1 - d; // update r2
867 if (q2 >= 0x80000000) magu.a = 1;
868 q2 = 2*q2; // update q2
869 r2 = 2*r2 + 1; // update r2
872 } while (p < 64 && (q1 < delta || (q1 == delta && r1 == 0)));
873 magu.m = q2 + 1; // resulting magic number
874 magu.s = p - 32; // resulting shift
879 /// BuildSDIVSequence - Given an ISD::SDIV node expressing a divide by constant,
880 /// return a DAG expression to select that will generate the same value by
881 /// multiplying by a magic number. See:
882 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
883 SDOperand ISel::BuildSDIVSequence(SDOperand N) {
884 int d = (int)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
885 ms magics = magic(d);
886 // Multiply the numerator (operand 0) by the magic value
887 SDOperand Q = ISelDAG->getNode(ISD::MULHS, MVT::i32, N.getOperand(0),
888 ISelDAG->getConstant(magics.m, MVT::i32));
889 // If d > 0 and m < 0, add the numerator
890 if (d > 0 && magics.m < 0)
891 Q = ISelDAG->getNode(ISD::ADD, MVT::i32, Q, N.getOperand(0));
892 // If d < 0 and m > 0, subtract the numerator.
893 if (d < 0 && magics.m > 0)
894 Q = ISelDAG->getNode(ISD::SUB, MVT::i32, Q, N.getOperand(0));
895 // Shift right algebraic if shift value is nonzero
897 Q = ISelDAG->getNode(ISD::SRA, MVT::i32, Q,
898 ISelDAG->getConstant(magics.s, MVT::i32));
899 // Extract the sign bit and add it to the quotient
901 ISelDAG->getNode(ISD::SRL, MVT::i32, Q, ISelDAG->getConstant(31, MVT::i32));
902 return ISelDAG->getNode(ISD::ADD, MVT::i32, Q, T);
905 /// BuildUDIVSequence - Given an ISD::UDIV node expressing a divide by constant,
906 /// return a DAG expression to select that will generate the same value by
907 /// multiplying by a magic number. See:
908 /// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
909 SDOperand ISel::BuildUDIVSequence(SDOperand N) {
911 (unsigned)cast<ConstantSDNode>(N.getOperand(1))->getSignExtended();
912 mu magics = magicu(d);
913 // Multiply the numerator (operand 0) by the magic value
914 SDOperand Q = ISelDAG->getNode(ISD::MULHU, MVT::i32, N.getOperand(0),
915 ISelDAG->getConstant(magics.m, MVT::i32));
917 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, Q,
918 ISelDAG->getConstant(magics.s, MVT::i32));
920 SDOperand NPQ = ISelDAG->getNode(ISD::SUB, MVT::i32, N.getOperand(0), Q);
921 NPQ = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
922 ISelDAG->getConstant(1, MVT::i32));
923 NPQ = ISelDAG->getNode(ISD::ADD, MVT::i32, NPQ, Q);
924 Q = ISelDAG->getNode(ISD::SRL, MVT::i32, NPQ,
925 ISelDAG->getConstant(magics.s-1, MVT::i32));
930 /// getGlobalBaseReg - Output the instructions required to put the
931 /// base address to use for accessing globals into a register.
933 unsigned ISel::getGlobalBaseReg() {
934 if (!GlobalBaseInitialized) {
935 // Insert the set of GlobalBaseReg into the first MBB of the function
936 MachineBasicBlock &FirstMBB = BB->getParent()->front();
937 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
938 GlobalBaseReg = MakeReg(MVT::i32);
939 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
940 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
941 GlobalBaseInitialized = true;
943 return GlobalBaseReg;
946 /// getConstDouble - Loads a floating point value into a register, via the
947 /// Constant Pool. Optionally takes a register in which to load the value.
948 unsigned ISel::getConstDouble(double doubleVal, unsigned Result=0) {
949 unsigned Tmp1 = MakeReg(MVT::i32);
950 if (0 == Result) Result = MakeReg(MVT::f64);
951 MachineConstantPool *CP = BB->getParent()->getConstantPool();
952 ConstantFP *CFP = ConstantFP::get(Type::DoubleTy, doubleVal);
953 unsigned CPI = CP->getConstantPoolIndex(CFP);
954 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
955 .addConstantPoolIndex(CPI);
956 BuildMI(BB, PPC::LFD, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
960 /// MoveCRtoGPR - Move CCReg[Idx] to the least significant bit of Result. If
961 /// Inv is true, then invert the result.
962 void ISel::MoveCRtoGPR(unsigned CCReg, bool Inv, unsigned Idx, unsigned Result){
963 unsigned IntCR = MakeReg(MVT::i32);
964 BuildMI(BB, PPC::MCRF, 1, PPC::CR7).addReg(CCReg);
965 BuildMI(BB, PPC::MFCR, 1, IntCR).addReg(PPC::CR7);
967 unsigned Tmp1 = MakeReg(MVT::i32);
968 BuildMI(BB, PPC::RLWINM, 4, Tmp1).addReg(IntCR).addImm(32-(3-Idx))
969 .addImm(31).addImm(31);
970 BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(1);
972 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(IntCR).addImm(32-(3-Idx))
973 .addImm(31).addImm(31);
977 /// SelectBitfieldInsert - turn an or of two masked values into
978 /// the rotate left word immediate then mask insert (rlwimi) instruction.
979 /// Returns true on success, false if the caller still needs to select OR.
981 /// Patterns matched:
982 /// 1. or shl, and 5. or and, and
983 /// 2. or and, shl 6. or shl, shr
984 /// 3. or shr, and 7. or shr, shl
986 bool ISel::SelectBitfieldInsert(SDOperand OR, unsigned Result) {
987 bool IsRotate = false;
988 unsigned TgtMask = 0xFFFFFFFF, InsMask = 0xFFFFFFFF, Amount = 0;
990 SDOperand Op0 = OR.getOperand(0);
991 SDOperand Op1 = OR.getOperand(1);
993 unsigned Op0Opc = Op0.getOpcode();
994 unsigned Op1Opc = Op1.getOpcode();
996 // Verify that we have the correct opcodes
997 if (ISD::SHL != Op0Opc && ISD::SRL != Op0Opc && ISD::AND != Op0Opc)
999 if (ISD::SHL != Op1Opc && ISD::SRL != Op1Opc && ISD::AND != Op1Opc)
1002 // Generate Mask value for Target
1003 if (ConstantSDNode *CN =
1004 dyn_cast<ConstantSDNode>(Op0.getOperand(1).Val)) {
1006 case ISD::SHL: TgtMask <<= (unsigned)CN->getValue(); break;
1007 case ISD::SRL: TgtMask >>= (unsigned)CN->getValue(); break;
1008 case ISD::AND: TgtMask &= (unsigned)CN->getValue(); break;
1014 // Generate Mask value for Insert
1015 if (ConstantSDNode *CN =
1016 dyn_cast<ConstantSDNode>(Op1.getOperand(1).Val)) {
1019 Amount = CN->getValue();
1021 if (Op0Opc == ISD::SRL) IsRotate = true;
1024 Amount = CN->getValue();
1027 if (Op0Opc == ISD::SHL) IsRotate = true;
1030 InsMask &= (unsigned)CN->getValue();
1039 // If both of the inputs are ANDs and one of them has a logical shift by
1040 // constant as its input, make that the inserted value so that we can combine
1041 // the shift into the rotate part of the rlwimi instruction
1042 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) {
1043 if (Op1.getOperand(0).getOpcode() == ISD::SHL ||
1044 Op1.getOperand(0).getOpcode() == ISD::SRL) {
1045 if (ConstantSDNode *CN =
1046 dyn_cast<ConstantSDNode>(Op1.getOperand(0).getOperand(1).Val)) {
1047 Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ?
1048 CN->getValue() : 32 - CN->getValue();
1049 Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
1051 } else if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
1052 Op0.getOperand(0).getOpcode() == ISD::SRL) {
1053 if (ConstantSDNode *CN =
1054 dyn_cast<ConstantSDNode>(Op0.getOperand(0).getOperand(1).Val)) {
1055 std::swap(Op0, Op1);
1056 std::swap(TgtMask, InsMask);
1057 Amount = Op1.getOperand(0).getOpcode() == ISD::SHL ?
1058 CN->getValue() : 32 - CN->getValue();
1059 Tmp3 = SelectExpr(Op1.getOperand(0).getOperand(0));
1064 // Verify that the Target mask and Insert mask together form a full word mask
1065 // and that the Insert mask is a run of set bits (which implies both are runs
1066 // of set bits). Given that, Select the arguments and generate the rlwimi
1069 if (((TgtMask & InsMask) == 0) && IsRunOfOnes(InsMask, MB, ME)) {
1070 unsigned Tmp1, Tmp2;
1071 bool fullMask = (TgtMask ^ InsMask) == 0xFFFFFFFF;
1072 // Check for rotlwi / rotrwi here, a special case of bitfield insert
1073 // where both bitfield halves are sourced from the same value.
1074 if (IsRotate && fullMask &&
1075 OR.getOperand(0).getOperand(0) == OR.getOperand(1).getOperand(0)) {
1076 Tmp1 = SelectExpr(OR.getOperand(0).getOperand(0));
1077 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Amount)
1078 .addImm(0).addImm(31);
1081 if (Op0Opc == ISD::AND && fullMask)
1082 Tmp1 = SelectExpr(Op0.getOperand(0));
1084 Tmp1 = SelectExpr(Op0);
1085 Tmp2 = Tmp3 ? Tmp3 : SelectExpr(Op1.getOperand(0));
1086 BuildMI(BB, PPC::RLWIMI, 5, Result).addReg(Tmp1).addReg(Tmp2)
1087 .addImm(Amount).addImm(MB).addImm(ME);
1093 /// FoldIfWideZeroExtend - 32 bit PowerPC implicit masks shift amounts to the
1094 /// low six bits. If the shift amount is an ISD::AND node with a mask that is
1095 /// wider than the implicit mask, then we can get rid of the AND and let the
1096 /// shift do the mask.
1097 unsigned ISel::FoldIfWideZeroExtend(SDOperand N) {
1099 if (N.getOpcode() == ISD::AND &&
1100 5 == getImmediateForOpcode(N.getOperand(1), ISD::AND, C) && // isMask
1101 31 == (C & 0xFFFF) && // ME
1102 26 >= (C >> 16)) // MB
1103 return SelectExpr(N.getOperand(0));
1105 return SelectExpr(N);
1108 unsigned ISel::SelectCC(SDOperand CC, unsigned& Opc, bool &Inv, unsigned& Idx) {
1109 unsigned Result, Tmp1, Tmp2;
1110 bool AlreadySelected = false;
1111 static const unsigned CompareOpcodes[] =
1112 { PPC::FCMPU, PPC::FCMPU, PPC::CMPW, PPC::CMPLW };
1114 // Allocate a condition register for this expression
1115 Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
1117 // If the first operand to the select is a SETCC node, then we can fold it
1118 // into the branch that selects which value to return.
1119 if (SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(CC.Val)) {
1121 Opc = getBCCForSetCC(SetCC->getCondition(), U);
1122 Idx = getCRIdxForSetCC(SetCC->getCondition(), Inv);
1124 // Pass the optional argument U to getImmediateForOpcode for SETCC,
1125 // so that it knows whether the SETCC immediate range is signed or not.
1126 if (1 == getImmediateForOpcode(SetCC->getOperand(1), ISD::SETCC,
1128 // For comparisons against zero, we can implicity set CR0 if a recording
1129 // variant (e.g. 'or.' instead of 'or') of the instruction that defines
1130 // operand zero of the SetCC node is available.
1132 NodeHasRecordingVariant(SetCC->getOperand(0).getOpcode()) &&
1133 SetCC->getOperand(0).Val->hasOneUse()) {
1134 RecordSuccess = false;
1135 Tmp1 = SelectExpr(SetCC->getOperand(0), true);
1136 if (RecordSuccess) {
1138 BuildMI(BB, PPC::MCRF, 1, Result).addReg(PPC::CR0);
1141 AlreadySelected = true;
1143 // If we could not implicitly set CR0, then emit a compare immediate
1145 if (!AlreadySelected) Tmp1 = SelectExpr(SetCC->getOperand(0));
1147 BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1149 BuildMI(BB, PPC::CMPWI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1151 bool IsInteger = MVT::isInteger(SetCC->getOperand(0).getValueType());
1152 unsigned CompareOpc = CompareOpcodes[2 * IsInteger + U];
1153 Tmp1 = SelectExpr(SetCC->getOperand(0));
1154 Tmp2 = SelectExpr(SetCC->getOperand(1));
1155 BuildMI(BB, CompareOpc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1159 return SelectCCExpr(CC, Opc, Inv, Idx);
1160 // If this isn't a SetCC, then select the value and compare it against zero,
1161 // treating it as if it were a boolean.
1163 Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
1164 Tmp1 = SelectExpr(CC);
1165 BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
1170 unsigned ISel::SelectCCExpr(SDOperand N, unsigned& Opc, bool &Inv,
1173 unsigned Idx0, Idx1, CROpc, Opc1, Tmp1, Tmp2;
1175 // Allocate a condition register for this expression
1176 unsigned Result = RegMap->createVirtualRegister(PPC32::CRRCRegisterClass);
1178 // Check for the operations we support:
1179 switch(N.getOpcode()) {
1182 Idx = getCRIdxForSetCC(ISD::SETNE, Inv);
1183 Tmp1 = SelectExpr(N);
1184 BuildMI(BB, PPC::CMPLWI, 2, Result).addReg(Tmp1).addImm(0);
1189 Tmp1 = SelectCCExpr(N.getOperand(0), Opc, Inv0, Idx0);
1190 Tmp2 = SelectCCExpr(N.getOperand(1), Opc1, Inv1, Idx1);
1191 CROpc = getCROpForSetCC(N.getOpcode(), Inv0, Inv1);
1192 if (Inv0 && !Inv1) {
1193 std::swap(Tmp1, Tmp2);
1194 std::swap(Idx0, Idx1);
1197 if (Inv0 && Inv1) Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
1198 BuildMI(BB, CROpc, 5, Result).addImm(Idx0).addReg(Tmp1).addImm(Idx0)
1199 .addReg(Tmp2).addImm(Idx1);
1204 Tmp1 = SelectCC(N, Opc, Inv, Idx);
1211 /// Check to see if the load is a constant offset from a base register
1212 bool ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
1214 unsigned imm = 0, opcode = N.getOpcode();
1215 if (N.getOpcode() == ISD::ADD) {
1216 Reg = SelectExpr(N.getOperand(0));
1217 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, imm)) {
1221 offset = SelectExpr(N.getOperand(1));
1224 Reg = SelectExpr(N);
1229 void ISel::SelectBranchCC(SDOperand N)
1231 MachineBasicBlock *Dest =
1232 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
1235 unsigned Opc, CCReg, Idx;
1236 Select(N.getOperand(0)); //chain
1237 CCReg = SelectCC(N.getOperand(1), Opc, Inv, Idx);
1239 // Iterate to the next basic block
1240 ilist<MachineBasicBlock>::iterator It = BB;
1243 // If this is a two way branch, then grab the fallthrough basic block argument
1244 // and build a PowerPC branch pseudo-op, suitable for long branch conversion
1245 // if necessary by the branch selection pass. Otherwise, emit a standard
1246 // conditional branch.
1247 if (N.getOpcode() == ISD::BRCONDTWOWAY) {
1248 MachineBasicBlock *Fallthrough =
1249 cast<BasicBlockSDNode>(N.getOperand(3))->getBasicBlock();
1251 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
1252 .addMBB(Dest).addMBB(Fallthrough);
1253 if (Fallthrough != It)
1254 BuildMI(BB, PPC::B, 1).addMBB(Fallthrough);
1256 if (Fallthrough != It) {
1257 Opc = PPC32InstrInfo::invertPPCBranchOpcode(Opc);
1258 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
1259 .addMBB(Fallthrough).addMBB(Dest);
1263 // If the fallthrough path is off the end of the function, which would be
1264 // undefined behavior, set it to be the same as the current block because
1265 // we have nothing better to set it to, and leaving it alone will cause the
1266 // PowerPC Branch Selection pass to crash.
1267 if (It == BB->getParent()->end()) It = Dest;
1268 BuildMI(BB, PPC::COND_BRANCH, 4).addReg(CCReg).addImm(Opc)
1269 .addMBB(Dest).addMBB(It);
1274 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
1276 unsigned Tmp1, Tmp2, Tmp3;
1278 SDNode *Node = N.Val;
1279 MVT::ValueType DestType = N.getValueType();
1280 unsigned opcode = N.getOpcode();
1285 assert(0 && "Node not handled!\n");
1288 // Attempt to generate FSEL. We can do this whenever we have an FP result,
1289 // and an FP comparison in the SetCC node.
1290 SetCCSDNode* SetCC = dyn_cast<SetCCSDNode>(N.getOperand(0).Val);
1291 if (SetCC && N.getOperand(0).getOpcode() == ISD::SETCC &&
1292 !MVT::isInteger(SetCC->getOperand(0).getValueType()) &&
1293 SetCC->getCondition() != ISD::SETEQ &&
1294 SetCC->getCondition() != ISD::SETNE) {
1295 MVT::ValueType VT = SetCC->getOperand(0).getValueType();
1296 unsigned TV = SelectExpr(N.getOperand(1)); // Use if TRUE
1297 unsigned FV = SelectExpr(N.getOperand(2)); // Use if FALSE
1299 ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(SetCC->getOperand(1));
1300 if (CN && (CN->isExactlyValue(-0.0) || CN->isExactlyValue(0.0))) {
1301 switch(SetCC->getCondition()) {
1302 default: assert(0 && "Invalid FSEL condition"); abort();
1305 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1308 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
1309 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp1).addReg(TV).addReg(FV);
1313 std::swap(TV, FV); // fsel is natively setge, swap operands for setlt
1316 if (SetCC->getOperand(0).getOpcode() == ISD::FNEG) {
1317 Tmp2 = SelectExpr(SetCC->getOperand(0).getOperand(0));
1320 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
1321 BuildMI(BB, PPC::FNEG, 1, Tmp2).addReg(Tmp1);
1323 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp2).addReg(TV).addReg(FV);
1328 Opc = (MVT::f64 == VT) ? PPC::FSUB : PPC::FSUBS;
1329 Tmp1 = SelectExpr(SetCC->getOperand(0)); // Val to compare against
1330 Tmp2 = SelectExpr(SetCC->getOperand(1));
1332 switch(SetCC->getCondition()) {
1333 default: assert(0 && "Invalid FSEL condition"); abort();
1336 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
1337 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
1341 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp1).addReg(Tmp2);
1342 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
1346 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
1347 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(FV).addReg(TV);
1351 BuildMI(BB, Opc, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
1352 BuildMI(BB, PPC::FSEL, 3, Result).addReg(Tmp3).addReg(TV).addReg(FV);
1356 assert(0 && "Should never get here");
1361 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
1362 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
1363 unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
1365 // Create an iterator with which to insert the MBB for copying the false
1366 // value and the MBB to hold the PHI instruction for this SetCC.
1367 MachineBasicBlock *thisMBB = BB;
1368 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1369 ilist<MachineBasicBlock>::iterator It = BB;
1375 // cmpTY ccX, r1, r2
1377 // fallthrough --> copy0MBB
1378 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
1379 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
1380 BuildMI(BB, Opc, 2).addReg(CCReg).addMBB(sinkMBB);
1381 MachineFunction *F = BB->getParent();
1382 F->getBasicBlockList().insert(It, copy0MBB);
1383 F->getBasicBlockList().insert(It, sinkMBB);
1384 // Update machine-CFG edges
1385 BB->addSuccessor(copy0MBB);
1386 BB->addSuccessor(sinkMBB);
1389 // %FalseValue = ...
1390 // # fallthrough to sinkMBB
1392 // Update machine-CFG edges
1393 BB->addSuccessor(sinkMBB);
1396 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1399 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
1400 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
1405 if (!NoExcessFPPrecision &&
1406 ISD::ADD == N.getOperand(0).getOpcode() &&
1407 N.getOperand(0).Val->hasOneUse() &&
1408 ISD::MUL == N.getOperand(0).getOperand(0).getOpcode() &&
1409 N.getOperand(0).getOperand(0).Val->hasOneUse()) {
1410 ++FusedFP; // Statistic
1411 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(0));
1412 Tmp2 = SelectExpr(N.getOperand(0).getOperand(0).getOperand(1));
1413 Tmp3 = SelectExpr(N.getOperand(0).getOperand(1));
1414 Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
1415 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1416 } else if (!NoExcessFPPrecision &&
1417 ISD::ADD == N.getOperand(0).getOpcode() &&
1418 N.getOperand(0).Val->hasOneUse() &&
1419 ISD::MUL == N.getOperand(0).getOperand(1).getOpcode() &&
1420 N.getOperand(0).getOperand(1).Val->hasOneUse()) {
1421 ++FusedFP; // Statistic
1422 Tmp1 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(0));
1423 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1).getOperand(1));
1424 Tmp3 = SelectExpr(N.getOperand(0).getOperand(0));
1425 Opc = DestType == MVT::f64 ? PPC::FNMADD : PPC::FNMADDS;
1426 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1427 } else if (ISD::FABS == N.getOperand(0).getOpcode()) {
1428 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1429 BuildMI(BB, PPC::FNABS, 1, Result).addReg(Tmp1);
1431 Tmp1 = SelectExpr(N.getOperand(0));
1432 BuildMI(BB, PPC::FNEG, 1, Result).addReg(Tmp1);
1437 Tmp1 = SelectExpr(N.getOperand(0));
1438 BuildMI(BB, PPC::FABS, 1, Result).addReg(Tmp1);
1442 assert (DestType == MVT::f32 &&
1443 N.getOperand(0).getValueType() == MVT::f64 &&
1444 "only f64 to f32 conversion supported here");
1445 Tmp1 = SelectExpr(N.getOperand(0));
1446 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
1449 case ISD::FP_EXTEND:
1450 assert (DestType == MVT::f64 &&
1451 N.getOperand(0).getValueType() == MVT::f32 &&
1452 "only f32 to f64 conversion supported here");
1453 Tmp1 = SelectExpr(N.getOperand(0));
1454 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
1457 case ISD::CopyFromReg:
1459 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1460 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
1461 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
1464 case ISD::ConstantFP: {
1465 ConstantFPSDNode *CN = cast<ConstantFPSDNode>(N);
1466 Result = getConstDouble(CN->getValue(), Result);
1471 if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
1472 N.getOperand(0).Val->hasOneUse()) {
1473 ++FusedFP; // Statistic
1474 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1475 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1476 Tmp3 = SelectExpr(N.getOperand(1));
1477 Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
1478 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1481 if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
1482 N.getOperand(1).Val->hasOneUse()) {
1483 ++FusedFP; // Statistic
1484 Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
1485 Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
1486 Tmp3 = SelectExpr(N.getOperand(0));
1487 Opc = DestType == MVT::f64 ? PPC::FMADD : PPC::FMADDS;
1488 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1491 Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS;
1492 Tmp1 = SelectExpr(N.getOperand(0));
1493 Tmp2 = SelectExpr(N.getOperand(1));
1494 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1498 if (!NoExcessFPPrecision && N.getOperand(0).getOpcode() == ISD::MUL &&
1499 N.getOperand(0).Val->hasOneUse()) {
1500 ++FusedFP; // Statistic
1501 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1502 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
1503 Tmp3 = SelectExpr(N.getOperand(1));
1504 Opc = DestType == MVT::f64 ? PPC::FMSUB : PPC::FMSUBS;
1505 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1508 if (!NoExcessFPPrecision && N.getOperand(1).getOpcode() == ISD::MUL &&
1509 N.getOperand(1).Val->hasOneUse()) {
1510 ++FusedFP; // Statistic
1511 Tmp1 = SelectExpr(N.getOperand(1).getOperand(0));
1512 Tmp2 = SelectExpr(N.getOperand(1).getOperand(1));
1513 Tmp3 = SelectExpr(N.getOperand(0));
1514 Opc = DestType == MVT::f64 ? PPC::FNMSUB : PPC::FNMSUBS;
1515 BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3);
1518 Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS;
1519 Tmp1 = SelectExpr(N.getOperand(0));
1520 Tmp2 = SelectExpr(N.getOperand(1));
1521 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1527 case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
1528 case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
1530 Tmp1 = SelectExpr(N.getOperand(0));
1531 Tmp2 = SelectExpr(N.getOperand(1));
1532 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1535 case ISD::UINT_TO_FP:
1536 case ISD::SINT_TO_FP: {
1537 assert (N.getOperand(0).getValueType() == MVT::i32
1538 && "int to float must operate on i32");
1539 bool IsUnsigned = (ISD::UINT_TO_FP == opcode);
1540 Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
1541 Tmp2 = MakeReg(MVT::f64); // temp reg to load the integer value into
1542 Tmp3 = MakeReg(MVT::i32); // temp reg to hold the conversion constant
1544 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
1545 MachineConstantPool *CP = BB->getParent()->getConstantPool();
1548 unsigned ConstF = getConstDouble(0x1.000000p52);
1549 // Store the hi & low halves of the fp value, currently in int regs
1550 BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
1551 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
1552 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp1), FrameIdx, 4);
1553 addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
1554 // Generate the return value with a subtract
1555 BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
1557 unsigned ConstF = getConstDouble(0x1.000008p52);
1558 unsigned TmpL = MakeReg(MVT::i32);
1559 // Store the hi & low halves of the fp value, currently in int regs
1560 BuildMI(BB, PPC::LIS, 1, Tmp3).addSImm(0x4330);
1561 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(Tmp3), FrameIdx);
1562 BuildMI(BB, PPC::XORIS, 2, TmpL).addReg(Tmp1).addImm(0x8000);
1563 addFrameReference(BuildMI(BB, PPC::STW, 3).addReg(TmpL), FrameIdx, 4);
1564 addFrameReference(BuildMI(BB, PPC::LFD, 2, Tmp2), FrameIdx);
1565 // Generate the return value with a subtract
1566 BuildMI(BB, PPC::FSUB, 2, Result).addReg(Tmp2).addReg(ConstF);
1571 assert(0 && "Should never get here");
1575 unsigned ISel::SelectExpr(SDOperand N, bool Recording) {
1577 unsigned Tmp1, Tmp2, Tmp3;
1579 unsigned opcode = N.getOpcode();
1581 SDNode *Node = N.Val;
1582 MVT::ValueType DestType = N.getValueType();
1584 if (Node->getOpcode() == ISD::CopyFromReg &&
1585 MRegisterInfo::isVirtualRegister(cast<RegSDNode>(Node)->getReg()))
1586 // Just use the specified register as our input.
1587 return cast<RegSDNode>(Node)->getReg();
1589 unsigned &Reg = ExprMap[N];
1590 if (Reg) return Reg;
1592 switch (N.getOpcode()) {
1594 Reg = Result = (N.getValueType() != MVT::Other) ?
1595 MakeReg(N.getValueType()) : 1;
1599 // If this is a call instruction, make sure to prepare ALL of the result
1600 // values as well as the chain.
1601 if (Node->getNumValues() == 1)
1602 Reg = Result = 1; // Void call, just a chain.
1604 Result = MakeReg(Node->getValueType(0));
1605 ExprMap[N.getValue(0)] = Result;
1606 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
1607 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1608 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
1611 case ISD::ADD_PARTS:
1612 case ISD::SUB_PARTS:
1613 case ISD::SHL_PARTS:
1614 case ISD::SRL_PARTS:
1615 case ISD::SRA_PARTS:
1616 Result = MakeReg(Node->getValueType(0));
1617 ExprMap[N.getValue(0)] = Result;
1618 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
1619 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
1623 if (ISD::CopyFromReg == opcode)
1624 DestType = N.getValue(0).getValueType();
1626 if (DestType == MVT::f64 || DestType == MVT::f32)
1627 if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode &&
1628 ISD::UNDEF != opcode && ISD::CALL != opcode && ISD::TAILCALL != opcode)
1629 return SelectExprFP(N, Result);
1634 assert(0 && "Node not handled!\n");
1636 BuildMI(BB, PPC::IMPLICIT_DEF, 0, Result);
1638 case ISD::DYNAMIC_STACKALLOC:
1639 // Generate both result values. FIXME: Need a better commment here?
1641 ExprMap[N.getValue(1)] = 1;
1643 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1645 // FIXME: We are currently ignoring the requested alignment for handling
1646 // greater than the stack alignment. This will need to be revisited at some
1647 // point. Align = N.getOperand(2);
1648 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
1649 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
1650 std::cerr << "Cannot allocate stack object with greater alignment than"
1651 << " the stack alignment yet!";
1654 Select(N.getOperand(0));
1655 Tmp1 = SelectExpr(N.getOperand(1));
1656 // Subtract size from stack pointer, thereby allocating some space.
1657 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
1658 // Put a pointer to the space into the result register by copying the SP
1659 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
1662 case ISD::ConstantPool:
1663 Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
1664 Tmp2 = MakeReg(MVT::i32);
1665 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp2).addReg(getGlobalBaseReg())
1666 .addConstantPoolIndex(Tmp1);
1667 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp2).addConstantPoolIndex(Tmp1);
1670 case ISD::FrameIndex:
1671 Tmp1 = cast<FrameIndexSDNode>(N)->getIndex();
1672 addFrameReference(BuildMI(BB, PPC::ADDI, 2, Result), (int)Tmp1, 0, false);
1675 case ISD::GlobalAddress: {
1676 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
1677 Tmp1 = MakeReg(MVT::i32);
1678 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
1679 .addGlobalAddress(GV);
1680 if (GV->hasWeakLinkage() || GV->isExternal()) {
1681 BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
1683 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp1).addGlobalAddress(GV);
1691 case ISD::SEXTLOAD: {
1692 MVT::ValueType TypeBeingLoaded = (ISD::LOAD == opcode) ?
1693 Node->getValueType(0) : cast<MVTSDNode>(Node)->getExtraValueType();
1694 bool sext = (ISD::SEXTLOAD == opcode);
1696 // Make sure we generate both values.
1698 ExprMap[N.getValue(1)] = 1; // Generate the token
1700 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1702 SDOperand Chain = N.getOperand(0);
1703 SDOperand Address = N.getOperand(1);
1706 switch (TypeBeingLoaded) {
1707 default: Node->dump(); assert(0 && "Cannot load this type!");
1708 case MVT::i1: Opc = PPC::LBZ; break;
1709 case MVT::i8: Opc = PPC::LBZ; break;
1710 case MVT::i16: Opc = sext ? PPC::LHA : PPC::LHZ; break;
1711 case MVT::i32: Opc = PPC::LWZ; break;
1712 case MVT::f32: Opc = PPC::LFS; break;
1713 case MVT::f64: Opc = PPC::LFD; break;
1716 if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Address)) {
1717 Tmp1 = MakeReg(MVT::i32);
1718 int CPI = CP->getIndex();
1719 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
1720 .addConstantPoolIndex(CPI);
1721 BuildMI(BB, Opc, 2, Result).addConstantPoolIndex(CPI).addReg(Tmp1);
1723 else if(Address.getOpcode() == ISD::FrameIndex) {
1724 Tmp1 = cast<FrameIndexSDNode>(Address)->getIndex();
1725 addFrameReference(BuildMI(BB, Opc, 2, Result), (int)Tmp1);
1728 bool idx = SelectAddr(Address, Tmp1, offset);
1730 Opc = IndexedOpForOp(Opc);
1731 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(offset);
1733 BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
1741 unsigned GPR_idx = 0, FPR_idx = 0;
1742 static const unsigned GPR[] = {
1743 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
1744 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
1746 static const unsigned FPR[] = {
1747 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
1748 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
1751 // Lower the chain for this call.
1752 Select(N.getOperand(0));
1753 ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
1755 MachineInstr *CallMI;
1756 // Emit the correct call instruction based on the type of symbol called.
1757 if (GlobalAddressSDNode *GASD =
1758 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
1759 CallMI = BuildMI(PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(),
1761 } else if (ExternalSymbolSDNode *ESSDN =
1762 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
1763 CallMI = BuildMI(PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(),
1766 Tmp1 = SelectExpr(N.getOperand(1));
1767 BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
1768 BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
1769 CallMI = BuildMI(PPC::CALLindirect, 3).addImm(20).addImm(0)
1773 // Load the register args to virtual regs
1774 std::vector<unsigned> ArgVR;
1775 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
1776 ArgVR.push_back(SelectExpr(N.getOperand(i)));
1778 // Copy the virtual registers into the appropriate argument register
1779 for(int i = 0, e = ArgVR.size(); i < e; ++i) {
1780 switch(N.getOperand(i+2).getValueType()) {
1781 default: Node->dump(); assert(0 && "Unknown value type for call");
1786 assert(GPR_idx < 8 && "Too many int args");
1787 if (N.getOperand(i+2).getOpcode() != ISD::UNDEF) {
1788 BuildMI(BB, PPC::OR,2,GPR[GPR_idx]).addReg(ArgVR[i]).addReg(ArgVR[i]);
1789 CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
1795 assert(FPR_idx < 13 && "Too many fp args");
1796 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(ArgVR[i]);
1797 CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
1803 // Put the call instruction in the correct place in the MachineBasicBlock
1804 BB->push_back(CallMI);
1806 switch (Node->getValueType(0)) {
1807 default: assert(0 && "Unknown value type for call result!");
1808 case MVT::Other: return 1;
1813 if (Node->getValueType(1) == MVT::i32) {
1814 BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3);
1815 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R4).addReg(PPC::R4);
1817 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
1822 BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
1825 return Result+N.ResNo;
1828 case ISD::SIGN_EXTEND:
1829 case ISD::SIGN_EXTEND_INREG:
1830 Tmp1 = SelectExpr(N.getOperand(0));
1831 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1832 default: Node->dump(); assert(0 && "Unhandled SIGN_EXTEND type"); break;
1834 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
1837 BuildMI(BB, PPC::EXTSB, 1, Result).addReg(Tmp1);
1840 BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp1).addSImm(0);
1845 case ISD::CopyFromReg:
1847 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
1848 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
1849 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
1853 Tmp1 = SelectExpr(N.getOperand(0));
1854 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1855 Tmp2 = CN->getValue() & 0x1F;
1856 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
1859 Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
1860 BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1865 Tmp1 = SelectExpr(N.getOperand(0));
1866 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1867 Tmp2 = CN->getValue() & 0x1F;
1868 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(32-Tmp2)
1869 .addImm(Tmp2).addImm(31);
1871 Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
1872 BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1877 Tmp1 = SelectExpr(N.getOperand(0));
1878 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
1879 Tmp2 = CN->getValue() & 0x1F;
1880 BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
1882 Tmp2 = FoldIfWideZeroExtend(N.getOperand(1));
1883 BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
1888 Tmp1 = SelectExpr(N.getOperand(0));
1889 BuildMI(BB, PPC::CNTLZW, 1, Result).addReg(Tmp1);
1893 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
1894 Tmp1 = SelectExpr(N.getOperand(0));
1895 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1896 default: assert(0 && "unhandled result code");
1897 case 0: // No immediate
1898 Tmp2 = SelectExpr(N.getOperand(1));
1899 BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
1901 case 1: // Low immediate
1902 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1904 case 2: // Shifted immediate
1905 BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
1912 if (N.getOperand(0).getOpcode() == ISD::SETCC ||
1913 N.getOperand(1).getOpcode() == ISD::SETCC) {
1915 Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
1916 MoveCRtoGPR(Tmp1, Inv, Tmp2, Result);
1920 // FIXME: should add check in getImmediateForOpcode to return a value
1921 // indicating the immediate is a run of set bits so we can emit a bitfield
1922 // clear with RLWINM instead.
1923 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1924 default: assert(0 && "unhandled result code");
1925 case 0: // No immediate
1926 // Check for andc: and, (xor a, -1), b
1927 if (N.getOperand(0).getOpcode() == ISD::XOR &&
1928 N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
1929 cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->isAllOnesValue()) {
1930 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1931 Tmp2 = SelectExpr(N.getOperand(1));
1932 BuildMI(BB, PPC::ANDC, 2, Result).addReg(Tmp2).addReg(Tmp1);
1935 // It wasn't and-with-complement, emit a regular and
1936 Tmp1 = SelectExpr(N.getOperand(0));
1937 Tmp2 = SelectExpr(N.getOperand(1));
1938 Opc = Recording ? PPC::ANDo : PPC::AND;
1939 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1941 case 1: // Low immediate
1942 Tmp1 = SelectExpr(N.getOperand(0));
1943 BuildMI(BB, PPC::ANDIo, 2, Result).addReg(Tmp1).addImm(Tmp2);
1945 case 2: // Shifted immediate
1946 Tmp1 = SelectExpr(N.getOperand(0));
1947 BuildMI(BB, PPC::ANDISo, 2, Result).addReg(Tmp1).addImm(Tmp2);
1949 case 5: // Bitfield mask
1950 Opc = Recording ? PPC::RLWINMo : PPC::RLWINM;
1951 Tmp3 = Tmp2 >> 16; // MB
1952 Tmp2 &= 0xFFFF; // ME
1954 if (N.getOperand(0).getOpcode() == ISD::SRL)
1955 if (ConstantSDNode *SA =
1956 dyn_cast<ConstantSDNode>(N.getOperand(0).getOperand(1))) {
1958 // We can fold the RLWINM and the SRL together if the mask is
1959 // clearing the top bits which are rotated around.
1960 unsigned RotAmt = 32-(SA->getValue() & 31);
1961 if (Tmp2 <= RotAmt) {
1962 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
1963 BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(RotAmt)
1964 .addImm(Tmp3).addImm(Tmp2);
1969 Tmp1 = SelectExpr(N.getOperand(0));
1970 BuildMI(BB, Opc, 4, Result).addReg(Tmp1).addImm(0)
1971 .addImm(Tmp3).addImm(Tmp2);
1974 RecordSuccess = true;
1978 if (SelectBitfieldInsert(N, Result))
1981 if (N.getOperand(0).getOpcode() == ISD::SETCC ||
1982 N.getOperand(1).getOpcode() == ISD::SETCC) {
1984 Tmp1 = SelectCCExpr(N, Opc, Inv, Tmp2);
1985 MoveCRtoGPR(Tmp1, Inv, Tmp2, Result);
1989 Tmp1 = SelectExpr(N.getOperand(0));
1990 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
1991 default: assert(0 && "unhandled result code");
1992 case 0: // No immediate
1993 Tmp2 = SelectExpr(N.getOperand(1));
1994 Opc = Recording ? PPC::ORo : PPC::OR;
1995 RecordSuccess = true;
1996 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
1998 case 1: // Low immediate
1999 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
2001 case 2: // Shifted immediate
2002 BuildMI(BB, PPC::ORIS, 2, Result).addReg(Tmp1).addImm(Tmp2);
2008 // Check for EQV: xor, (xor a, -1), b
2009 if (N.getOperand(0).getOpcode() == ISD::XOR &&
2010 N.getOperand(0).getOperand(1).getOpcode() == ISD::Constant &&
2011 cast<ConstantSDNode>(N.getOperand(0).getOperand(1))->isAllOnesValue()) {
2012 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
2013 Tmp2 = SelectExpr(N.getOperand(1));
2014 BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
2017 // Check for NOT, NOR, EQV, and NAND: xor (copy, or, xor, and), -1
2018 if (N.getOperand(1).getOpcode() == ISD::Constant &&
2019 cast<ConstantSDNode>(N.getOperand(1))->isAllOnesValue()) {
2020 switch(N.getOperand(0).getOpcode()) {
2022 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
2023 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
2024 BuildMI(BB, PPC::NOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
2027 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
2028 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
2029 BuildMI(BB, PPC::NAND, 2, Result).addReg(Tmp1).addReg(Tmp2);
2032 Tmp1 = SelectExpr(N.getOperand(0).getOperand(0));
2033 Tmp2 = SelectExpr(N.getOperand(0).getOperand(1));
2034 BuildMI(BB, PPC::EQV, 2, Result).addReg(Tmp1).addReg(Tmp2);
2037 Tmp1 = SelectExpr(N.getOperand(0));
2038 BuildMI(BB, PPC::NOR, 2, Result).addReg(Tmp1).addReg(Tmp1);
2043 Tmp1 = SelectExpr(N.getOperand(0));
2044 switch(getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
2045 default: assert(0 && "unhandled result code");
2046 case 0: // No immediate
2047 Tmp2 = SelectExpr(N.getOperand(1));
2048 BuildMI(BB, PPC::XOR, 2, Result).addReg(Tmp1).addReg(Tmp2);
2050 case 1: // Low immediate
2051 BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp1).addImm(Tmp2);
2053 case 2: // Shifted immediate
2054 BuildMI(BB, PPC::XORIS, 2, Result).addReg(Tmp1).addImm(Tmp2);
2061 if (1 == getImmediateForOpcode(N.getOperand(0), opcode, Tmp1, true)) {
2062 Tmp2 = SelectExpr(N.getOperand(1));
2063 BuildMI(BB, PPC::SUBFIC, 2, Result).addReg(Tmp2).addSImm(Tmp1);
2064 } else if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
2065 Tmp1 = SelectExpr(N.getOperand(0));
2066 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
2068 Tmp1 = SelectExpr(N.getOperand(0));
2069 Tmp2 = SelectExpr(N.getOperand(1));
2070 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
2075 Tmp1 = SelectExpr(N.getOperand(0));
2076 if (1 == getImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
2077 BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
2079 Tmp2 = SelectExpr(N.getOperand(1));
2080 BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
2086 Tmp1 = SelectExpr(N.getOperand(0));
2087 Tmp2 = SelectExpr(N.getOperand(1));
2088 Opc = (ISD::MULHU == opcode) ? PPC::MULHWU : PPC::MULHW;
2089 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
2094 switch (getImmediateForOpcode(N.getOperand(1), opcode, Tmp3)) {
2096 // If this is an sdiv by a power of two, we can use an srawi/addze pair.
2098 Tmp1 = MakeReg(MVT::i32);
2099 Tmp2 = SelectExpr(N.getOperand(0));
2100 if ((int)Tmp3 < 0) {
2101 unsigned Tmp4 = MakeReg(MVT::i32);
2102 BuildMI(BB, PPC::SRAWI, 2, Tmp1).addReg(Tmp2).addImm(-Tmp3);
2103 BuildMI(BB, PPC::ADDZE, 1, Tmp4).addReg(Tmp1);
2104 BuildMI(BB, PPC::NEG, 1, Result).addReg(Tmp4);
2106 BuildMI(BB, PPC::SRAWI, 2, Tmp1).addReg(Tmp2).addImm(Tmp3);
2107 BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp1);
2110 // If this is a divide by constant, we can emit code using some magic
2111 // constants to implement it as a multiply instead.
2114 if (opcode == ISD::SDIV)
2115 return SelectExpr(BuildSDIVSequence(N));
2117 return SelectExpr(BuildUDIVSequence(N));
2119 Tmp1 = SelectExpr(N.getOperand(0));
2120 Tmp2 = SelectExpr(N.getOperand(1));
2121 Opc = (ISD::UDIV == opcode) ? PPC::DIVWU : PPC::DIVW;
2122 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
2125 case ISD::ADD_PARTS:
2126 case ISD::SUB_PARTS: {
2127 assert(N.getNumOperands() == 4 && N.getValueType() == MVT::i32 &&
2128 "Not an i64 add/sub!");
2129 // Emit all of the operands.
2130 std::vector<unsigned> InVals;
2131 for (unsigned i = 0, e = N.getNumOperands(); i != e; ++i)
2132 InVals.push_back(SelectExpr(N.getOperand(i)));
2133 if (N.getOpcode() == ISD::ADD_PARTS) {
2134 BuildMI(BB, PPC::ADDC, 2, Result).addReg(InVals[0]).addReg(InVals[2]);
2135 BuildMI(BB, PPC::ADDE, 2, Result+1).addReg(InVals[1]).addReg(InVals[3]);
2137 BuildMI(BB, PPC::SUBFC, 2, Result).addReg(InVals[2]).addReg(InVals[0]);
2138 BuildMI(BB, PPC::SUBFE, 2, Result+1).addReg(InVals[3]).addReg(InVals[1]);
2140 return Result+N.ResNo;
2143 case ISD::SHL_PARTS:
2144 case ISD::SRA_PARTS:
2145 case ISD::SRL_PARTS: {
2146 assert(N.getNumOperands() == 3 && N.getValueType() == MVT::i32 &&
2147 "Not an i64 shift!");
2148 unsigned ShiftOpLo = SelectExpr(N.getOperand(0));
2149 unsigned ShiftOpHi = SelectExpr(N.getOperand(1));
2150 unsigned SHReg = FoldIfWideZeroExtend(N.getOperand(2));
2151 Tmp1 = MakeReg(MVT::i32);
2152 Tmp2 = MakeReg(MVT::i32);
2153 Tmp3 = MakeReg(MVT::i32);
2154 unsigned Tmp4 = MakeReg(MVT::i32);
2155 unsigned Tmp5 = MakeReg(MVT::i32);
2156 unsigned Tmp6 = MakeReg(MVT::i32);
2157 BuildMI(BB, PPC::SUBFIC, 2, Tmp1).addReg(SHReg).addSImm(32);
2158 if (ISD::SHL_PARTS == opcode) {
2159 BuildMI(BB, PPC::SLW, 2, Tmp2).addReg(ShiftOpHi).addReg(SHReg);
2160 BuildMI(BB, PPC::SRW, 2, Tmp3).addReg(ShiftOpLo).addReg(Tmp1);
2161 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
2162 BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
2163 BuildMI(BB, PPC::SLW, 2, Tmp6).addReg(ShiftOpLo).addReg(Tmp5);
2164 BuildMI(BB, PPC::OR, 2, Result+1).addReg(Tmp4).addReg(Tmp6);
2165 BuildMI(BB, PPC::SLW, 2, Result).addReg(ShiftOpLo).addReg(SHReg);
2166 } else if (ISD::SRL_PARTS == opcode) {
2167 BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
2168 BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
2169 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
2170 BuildMI(BB, PPC::ADDI, 2, Tmp5).addReg(SHReg).addSImm(-32);
2171 BuildMI(BB, PPC::SRW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
2172 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp4).addReg(Tmp6);
2173 BuildMI(BB, PPC::SRW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
2175 MachineBasicBlock *TmpMBB = new MachineBasicBlock(BB->getBasicBlock());
2176 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
2177 MachineBasicBlock *OldMBB = BB;
2178 MachineFunction *F = BB->getParent();
2179 ilist<MachineBasicBlock>::iterator It = BB; ++It;
2180 F->getBasicBlockList().insert(It, TmpMBB);
2181 F->getBasicBlockList().insert(It, PhiMBB);
2182 BB->addSuccessor(TmpMBB);
2183 BB->addSuccessor(PhiMBB);
2184 BuildMI(BB, PPC::SRW, 2, Tmp2).addReg(ShiftOpLo).addReg(SHReg);
2185 BuildMI(BB, PPC::SLW, 2, Tmp3).addReg(ShiftOpHi).addReg(Tmp1);
2186 BuildMI(BB, PPC::OR, 2, Tmp4).addReg(Tmp2).addReg(Tmp3);
2187 BuildMI(BB, PPC::ADDICo, 2, Tmp5).addReg(SHReg).addSImm(-32);
2188 BuildMI(BB, PPC::SRAW, 2, Tmp6).addReg(ShiftOpHi).addReg(Tmp5);
2189 BuildMI(BB, PPC::SRAW, 2, Result+1).addReg(ShiftOpHi).addReg(SHReg);
2190 BuildMI(BB, PPC::BLE, 2).addReg(PPC::CR0).addMBB(PhiMBB);
2191 // Select correct least significant half if the shift amount > 32
2193 unsigned Tmp7 = MakeReg(MVT::i32);
2194 BuildMI(BB, PPC::OR, 2, Tmp7).addReg(Tmp6).addReg(Tmp6);
2195 TmpMBB->addSuccessor(PhiMBB);
2197 BuildMI(BB, PPC::PHI, 4, Result).addReg(Tmp4).addMBB(OldMBB)
2198 .addReg(Tmp7).addMBB(TmpMBB);
2200 return Result+N.ResNo;
2203 case ISD::FP_TO_UINT:
2204 case ISD::FP_TO_SINT: {
2205 bool U = (ISD::FP_TO_UINT == opcode);
2206 Tmp1 = SelectExpr(N.getOperand(0));
2208 Tmp2 = MakeReg(MVT::f64);
2209 BuildMI(BB, PPC::FCTIWZ, 1, Tmp2).addReg(Tmp1);
2210 int FrameIdx = BB->getParent()->getFrameInfo()->CreateStackObject(8, 8);
2211 addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(Tmp2), FrameIdx);
2212 addFrameReference(BuildMI(BB, PPC::LWZ, 2, Result), FrameIdx, 4);
2215 unsigned Zero = getConstDouble(0.0);
2216 unsigned MaxInt = getConstDouble((1LL << 32) - 1);
2217 unsigned Border = getConstDouble(1LL << 31);
2218 unsigned UseZero = MakeReg(MVT::f64);
2219 unsigned UseMaxInt = MakeReg(MVT::f64);
2220 unsigned UseChoice = MakeReg(MVT::f64);
2221 unsigned TmpReg = MakeReg(MVT::f64);
2222 unsigned TmpReg2 = MakeReg(MVT::f64);
2223 unsigned ConvReg = MakeReg(MVT::f64);
2224 unsigned IntTmp = MakeReg(MVT::i32);
2225 unsigned XorReg = MakeReg(MVT::i32);
2226 MachineFunction *F = BB->getParent();
2227 int FrameIdx = F->getFrameInfo()->CreateStackObject(8, 8);
2228 // Update machine-CFG edges
2229 MachineBasicBlock *XorMBB = new MachineBasicBlock(BB->getBasicBlock());
2230 MachineBasicBlock *PhiMBB = new MachineBasicBlock(BB->getBasicBlock());
2231 MachineBasicBlock *OldMBB = BB;
2232 ilist<MachineBasicBlock>::iterator It = BB; ++It;
2233 F->getBasicBlockList().insert(It, XorMBB);
2234 F->getBasicBlockList().insert(It, PhiMBB);
2235 BB->addSuccessor(XorMBB);
2236 BB->addSuccessor(PhiMBB);
2237 // Convert from floating point to unsigned 32-bit value
2238 // Use 0 if incoming value is < 0.0
2239 BuildMI(BB, PPC::FSEL, 3, UseZero).addReg(Tmp1).addReg(Tmp1).addReg(Zero);
2240 // Use 2**32 - 1 if incoming value is >= 2**32
2241 BuildMI(BB, PPC::FSUB, 2, UseMaxInt).addReg(MaxInt).addReg(Tmp1);
2242 BuildMI(BB, PPC::FSEL, 3, UseChoice).addReg(UseMaxInt).addReg(UseZero)
2245 BuildMI(BB, PPC::FSUB, 2, TmpReg).addReg(UseChoice).addReg(Border);
2246 // Use difference if >= 2**31
2247 BuildMI(BB, PPC::FCMPU, 2, PPC::CR0).addReg(UseChoice).addReg(Border);
2248 BuildMI(BB, PPC::FSEL, 3, TmpReg2).addReg(TmpReg).addReg(TmpReg)
2250 // Convert to integer
2251 BuildMI(BB, PPC::FCTIWZ, 1, ConvReg).addReg(TmpReg2);
2252 addFrameReference(BuildMI(BB, PPC::STFD, 3).addReg(ConvReg), FrameIdx);
2253 addFrameReference(BuildMI(BB, PPC::LWZ, 2, IntTmp), FrameIdx, 4);
2254 BuildMI(BB, PPC::BLT, 2).addReg(PPC::CR0).addMBB(PhiMBB);
2255 BuildMI(BB, PPC::B, 1).addMBB(XorMBB);
2258 // add 2**31 if input was >= 2**31
2260 BuildMI(BB, PPC::XORIS, 2, XorReg).addReg(IntTmp).addImm(0x8000);
2261 XorMBB->addSuccessor(PhiMBB);
2264 // DestReg = phi [ IntTmp, OldMBB ], [ XorReg, XorMBB ]
2266 BuildMI(BB, PPC::PHI, 4, Result).addReg(IntTmp).addMBB(OldMBB)
2267 .addReg(XorReg).addMBB(XorMBB);
2270 assert(0 && "Should never get here");
2275 if (SetCCSDNode *SetCC = dyn_cast<SetCCSDNode>(Node)) {
2276 if (ConstantSDNode *CN =
2277 dyn_cast<ConstantSDNode>(SetCC->getOperand(1).Val)) {
2278 // We can codegen setcc op, imm very efficiently compared to a brcond.
2279 // Check for those cases here.
2281 if (CN->getValue() == 0) {
2282 Tmp1 = SelectExpr(SetCC->getOperand(0));
2283 switch (SetCC->getCondition()) {
2284 default: SetCC->dump(); assert(0 && "Unhandled SetCC condition"); abort();
2286 Tmp2 = MakeReg(MVT::i32);
2287 BuildMI(BB, PPC::CNTLZW, 1, Tmp2).addReg(Tmp1);
2288 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp2).addImm(27)
2289 .addImm(5).addImm(31);
2292 Tmp2 = MakeReg(MVT::i32);
2293 BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(-1);
2294 BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp2).addReg(Tmp1);
2297 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp1).addImm(1)
2298 .addImm(31).addImm(31);
2301 Tmp2 = MakeReg(MVT::i32);
2302 Tmp3 = MakeReg(MVT::i32);
2303 BuildMI(BB, PPC::NEG, 2, Tmp2).addReg(Tmp1);
2304 BuildMI(BB, PPC::ANDC, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
2305 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
2306 .addImm(31).addImm(31);
2312 if (CN->isAllOnesValue()) {
2313 Tmp1 = SelectExpr(SetCC->getOperand(0));
2314 switch (SetCC->getCondition()) {
2315 default: assert(0 && "Unhandled SetCC condition"); abort();
2317 Tmp2 = MakeReg(MVT::i32);
2318 Tmp3 = MakeReg(MVT::i32);
2319 BuildMI(BB, PPC::ADDIC, 2, Tmp2).addReg(Tmp1).addSImm(1);
2320 BuildMI(BB, PPC::LI, 1, Tmp3).addSImm(0);
2321 BuildMI(BB, PPC::ADDZE, 1, Result).addReg(Tmp3);
2324 Tmp2 = MakeReg(MVT::i32);
2325 Tmp3 = MakeReg(MVT::i32);
2326 BuildMI(BB, PPC::NOR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
2327 BuildMI(BB, PPC::ADDIC, 2, Tmp3).addReg(Tmp2).addSImm(-1);
2328 BuildMI(BB, PPC::SUBFE, 2, Result).addReg(Tmp3).addReg(Tmp2);
2331 Tmp2 = MakeReg(MVT::i32);
2332 Tmp3 = MakeReg(MVT::i32);
2333 BuildMI(BB, PPC::ADDI, 2, Tmp2).addReg(Tmp1).addSImm(1);
2334 BuildMI(BB, PPC::AND, 2, Tmp3).addReg(Tmp2).addReg(Tmp1);
2335 BuildMI(BB, PPC::RLWINM, 4, Result).addReg(Tmp3).addImm(1)
2336 .addImm(31).addImm(31);
2339 Tmp2 = MakeReg(MVT::i32);
2340 BuildMI(BB, PPC::RLWINM, 4, Tmp2).addReg(Tmp1).addImm(1)
2341 .addImm(31).addImm(31);
2342 BuildMI(BB, PPC::XORI, 2, Result).addReg(Tmp2).addImm(1);
2350 unsigned CCReg = SelectCC(N, Opc, Inv, Tmp2);
2351 MoveCRtoGPR(CCReg, Inv, Tmp2, Result);
2354 assert(0 && "Is this legal?");
2359 unsigned TrueValue = SelectExpr(N.getOperand(1)); //Use if TRUE
2360 unsigned FalseValue = SelectExpr(N.getOperand(2)); //Use if FALSE
2361 unsigned CCReg = SelectCC(N.getOperand(0), Opc, Inv, Tmp3);
2363 // Create an iterator with which to insert the MBB for copying the false
2364 // value and the MBB to hold the PHI instruction for this SetCC.
2365 MachineBasicBlock *thisMBB = BB;
2366 const BasicBlock *LLVM_BB = BB->getBasicBlock();
2367 ilist<MachineBasicBlock>::iterator It = BB;
2373 // cmpTY ccX, r1, r2
2375 // fallthrough --> copy0MBB
2376 MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
2377 MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
2378 BuildMI(BB, Opc, 2).addReg(CCReg).addMBB(sinkMBB);
2379 MachineFunction *F = BB->getParent();
2380 F->getBasicBlockList().insert(It, copy0MBB);
2381 F->getBasicBlockList().insert(It, sinkMBB);
2382 // Update machine-CFG edges
2383 BB->addSuccessor(copy0MBB);
2384 BB->addSuccessor(sinkMBB);
2387 // %FalseValue = ...
2388 // # fallthrough to sinkMBB
2390 // Update machine-CFG edges
2391 BB->addSuccessor(sinkMBB);
2394 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
2397 BuildMI(BB, PPC::PHI, 4, Result).addReg(FalseValue)
2398 .addMBB(copy0MBB).addReg(TrueValue).addMBB(thisMBB);
2403 switch (N.getValueType()) {
2404 default: assert(0 && "Cannot use constants of this type!");
2406 BuildMI(BB, PPC::LI, 1, Result)
2407 .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
2411 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
2412 if (v < 32768 && v >= -32768) {
2413 BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
2415 Tmp1 = MakeReg(MVT::i32);
2416 BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
2417 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
2427 void ISel::Select(SDOperand N) {
2428 unsigned Tmp1, Tmp2, Opc;
2429 unsigned opcode = N.getOpcode();
2431 if (!ExprMap.insert(std::make_pair(N, 1)).second)
2432 return; // Already selected.
2434 SDNode *Node = N.Val;
2436 switch (Node->getOpcode()) {
2438 Node->dump(); std::cerr << "\n";
2439 assert(0 && "Node not handled yet!");
2440 case ISD::EntryToken: return; // Noop
2441 case ISD::TokenFactor:
2442 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
2443 Select(Node->getOperand(i));
2445 case ISD::CALLSEQ_START:
2446 case ISD::CALLSEQ_END:
2447 Select(N.getOperand(0));
2448 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
2449 Opc = N.getOpcode() == ISD::CALLSEQ_START ? PPC::ADJCALLSTACKDOWN :
2450 PPC::ADJCALLSTACKUP;
2451 BuildMI(BB, Opc, 1).addImm(Tmp1);
2454 MachineBasicBlock *Dest =
2455 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
2456 Select(N.getOperand(0));
2457 BuildMI(BB, PPC::B, 1).addMBB(Dest);
2461 case ISD::BRCONDTWOWAY:
2464 case ISD::CopyToReg:
2465 Select(N.getOperand(0));
2466 Tmp1 = SelectExpr(N.getOperand(1));
2467 Tmp2 = cast<RegSDNode>(N)->getReg();
2470 if (N.getOperand(1).getValueType() == MVT::f64 ||
2471 N.getOperand(1).getValueType() == MVT::f32)
2472 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
2474 BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
2477 case ISD::ImplicitDef:
2478 Select(N.getOperand(0));
2479 BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
2482 switch (N.getNumOperands()) {
2484 assert(0 && "Unknown return instruction!");
2486 assert(N.getOperand(1).getValueType() == MVT::i32 &&
2487 N.getOperand(2).getValueType() == MVT::i32 &&
2488 "Unknown two-register value!");
2489 Select(N.getOperand(0));
2490 Tmp1 = SelectExpr(N.getOperand(1));
2491 Tmp2 = SelectExpr(N.getOperand(2));
2492 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp2).addReg(Tmp2);
2493 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp1).addReg(Tmp1);
2496 Select(N.getOperand(0));
2497 Tmp1 = SelectExpr(N.getOperand(1));
2498 switch (N.getOperand(1).getValueType()) {
2500 assert(0 && "Unknown return type!");
2503 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
2506 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
2510 Select(N.getOperand(0));
2513 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
2515 case ISD::TRUNCSTORE:
2518 SDOperand Chain = N.getOperand(0);
2519 SDOperand Value = N.getOperand(1);
2520 SDOperand Address = N.getOperand(2);
2523 Tmp1 = SelectExpr(Value); //value
2525 if (opcode == ISD::STORE) {
2526 switch(Value.getValueType()) {
2527 default: assert(0 && "unknown Type in store");
2528 case MVT::i32: Opc = PPC::STW; break;
2529 case MVT::f64: Opc = PPC::STFD; break;
2530 case MVT::f32: Opc = PPC::STFS; break;
2532 } else { //ISD::TRUNCSTORE
2533 switch(cast<VTSDNode>(Node->getOperand(4))->getVT()) {
2534 default: assert(0 && "unknown Type in store");
2536 case MVT::i8: Opc = PPC::STB; break;
2537 case MVT::i16: Opc = PPC::STH; break;
2541 if(Address.getOpcode() == ISD::FrameIndex)
2543 Tmp2 = cast<FrameIndexSDNode>(Address)->getIndex();
2544 addFrameReference(BuildMI(BB, Opc, 3).addReg(Tmp1), (int)Tmp2);
2549 bool idx = SelectAddr(Address, Tmp2, offset);
2551 Opc = IndexedOpForOp(Opc);
2552 BuildMI(BB, Opc, 3).addReg(Tmp1).addReg(Tmp2).addReg(offset);
2554 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
2563 case ISD::CopyFromReg:
2566 case ISD::DYNAMIC_STACKALLOC:
2571 assert(0 && "Should not be reached!");
2575 /// createPPC32PatternInstructionSelector - This pass converts an LLVM function
2576 /// into a machine code representation using pattern matching and a machine
2577 /// description file.
2579 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
2580 return new ISel(TM);