1 //===-- PPC32ISelPattern.cpp - A pattern matching inst selector for PPC32 -===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Nate Begeman and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a pattern matching instruction selector for 32 bit PowerPC.
12 //===----------------------------------------------------------------------===//
15 #include "PowerPCInstrBuilder.h"
16 #include "PowerPCInstrInfo.h"
17 #include "PPC32RegisterInfo.h"
18 #include "llvm/Constants.h" // FIXME: REMOVE
19 #include "llvm/Function.h"
20 #include "llvm/CodeGen/MachineConstantPool.h" // FIXME: REMOVE
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/SelectionDAG.h"
24 #include "llvm/CodeGen/SelectionDAGISel.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetData.h"
27 #include "llvm/Target/TargetLowering.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/MathExtras.h"
30 #include "llvm/ADT/Statistic.h"
35 //===----------------------------------------------------------------------===//
36 // PPC32TargetLowering - PPC32 Implementation of the TargetLowering interface
38 class PPC32TargetLowering : public TargetLowering {
39 int VarArgsFrameIndex; // FrameIndex for start of varargs area.
40 int ReturnAddrIndex; // FrameIndex for return slot.
42 PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
43 // Set up the TargetLowering object.
45 // Set up the register classes.
46 addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
47 addRegisterClass(MVT::f32, PPC32::GPRCRegisterClass);
48 addRegisterClass(MVT::f64, PPC32::FPRCRegisterClass);
50 computeRegisterProperties();
53 /// LowerArguments - This hook must be implemented to indicate how we should
54 /// lower the arguments for the specified function, into the specified DAG.
55 virtual std::vector<SDOperand>
56 LowerArguments(Function &F, SelectionDAG &DAG);
58 /// LowerCallTo - This hook lowers an abstract call to a function into an
60 virtual std::pair<SDOperand, SDOperand>
61 LowerCallTo(SDOperand Chain, const Type *RetTy, bool isVarArg,
62 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG);
64 virtual std::pair<SDOperand, SDOperand>
65 LowerVAStart(SDOperand Chain, SelectionDAG &DAG);
67 virtual std::pair<SDOperand,SDOperand>
68 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
69 const Type *ArgTy, SelectionDAG &DAG);
71 virtual std::pair<SDOperand, SDOperand>
72 LowerFrameReturnAddress(bool isFrameAddr, SDOperand Chain, unsigned Depth,
78 std::vector<SDOperand>
79 PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
81 // add beautiful description of PPC stack frame format, or at least some docs
83 MachineFunction &MF = DAG.getMachineFunction();
84 MachineFrameInfo *MFI = MF.getFrameInfo();
85 MachineBasicBlock& BB = MF.front();
86 std::vector<SDOperand> ArgValues;
88 // Due to the rather complicated nature of the PowerPC ABI, rather than a
89 // fixed size array of physical args, for the sake of simplicity let the STL
90 // handle tracking them for us.
91 std::vector<unsigned> argVR, argPR, argOp;
92 unsigned ArgOffset = 24;
93 unsigned GPR_remaining = 8;
94 unsigned FPR_remaining = 13;
95 unsigned GPR_idx = 0, FPR_idx = 0;
96 static const unsigned GPR[] = {
97 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
98 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
100 static const unsigned FPR[] = {
101 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6, PPC::F7,
102 PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12, PPC::F13
105 // Add DAG nodes to load the arguments... On entry to a function on PPC,
106 // the arguments start at offset 24, although they are likely to be passed
108 for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; ++I) {
109 SDOperand newroot, argt;
111 bool needsLoad = false;
112 MVT::ValueType ObjectVT = getValueType(I->getType());
115 default: assert(0 && "Unhandled argument type!");
121 if (GPR_remaining > 0) {
122 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
124 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
125 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
126 if (ObjectVT != MVT::i32)
127 argt = DAG.getNode(ISD::TRUNCATE, ObjectVT, newroot);
128 argVR.push_back(virtReg);
129 argPR.push_back(GPR[GPR_idx]);
130 argOp.push_back(PPC::OR);
135 case MVT::i64: ObjSize = 8;
136 if (GPR_remaining > 1) {
137 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx]);
138 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
139 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32));
141 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i32))-1;
142 // FIXME: is this correct?
143 argt = newroot = DAG.getCopyFromReg(virtReg, MVT::i32, DAG.getRoot());
144 argt = DAG.getCopyFromReg(virtReg+1, MVT::i32, newroot);
145 // Push the arguments for emitting into BB later
146 argVR.push_back(virtReg); argVR.push_back(virtReg+1);
147 argPR.push_back(GPR[GPR_idx]); argPR.push_back(GPR[GPR_idx+1]);
148 argOp.push_back(PPC::OR); argOp.push_back(PPC::OR);
153 case MVT::f32: ObjSize = 4;
154 case MVT::f64: ObjSize = 8;
155 if (FPR_remaining > 0) {
156 BuildMI(&BB, PPC::IMPLICIT_DEF, 0, FPR[FPR_idx]);
158 MF.getSSARegMap()->createVirtualRegister(getRegClassFor(ObjectVT));
159 argt = newroot = DAG.getCopyFromReg(virtReg, ObjectVT, DAG.getRoot());
160 argVR.push_back(virtReg);
161 argPR.push_back(FPR[FPR_idx]);
162 argOp.push_back(PPC::FMR);
171 // We need to load the argument to a virtual register if we determined above
172 // that we ran out of physical registers of the appropriate type
174 int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
175 SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
176 argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
179 // Every 4 bytes of argument space consumes one of the GPRs available for
181 if (GPR_remaining > 0) {
182 unsigned delta = (GPR_remaining > 1 && ObjSize == 8) ? 2 : 1;
183 GPR_remaining -= delta;
186 ArgOffset += ObjSize;
188 DAG.setRoot(newroot.getValue(1));
189 ArgValues.push_back(argt);
192 for (int i = 0, count = argVR.size(); i < count; ++i) {
193 if (argOp[i] == PPC::FMR)
194 BuildMI(&BB, argOp[i], 1, argVR[i]).addReg(argPR[i]);
196 BuildMI(&BB, argOp[i], 2, argVR[i]).addReg(argPR[i]).addReg(argPR[i]);
199 // If the function takes variable number of arguments, make a frame index for
200 // the start of the first vararg value... for expansion of llvm.va_start.
202 VarArgsFrameIndex = MFI->CreateFixedObject(4, ArgOffset);
207 std::pair<SDOperand, SDOperand>
208 PPC32TargetLowering::LowerCallTo(SDOperand Chain,
209 const Type *RetTy, bool isVarArg,
210 SDOperand Callee, ArgListTy &Args, SelectionDAG &DAG) {
211 // args_to_use will accumulate outgoing args for the ISD::CALL case in
212 // SelectExpr to use to put the arguments in the appropriate registers.
213 std::vector<SDOperand> args_to_use;
215 // Count how many bytes are to be pushed on the stack, including the linkage
216 // area, and parameter passing area.
217 unsigned NumBytes = 24;
220 NumBytes = 0; // Save zero bytes.
222 for (unsigned i = 0, e = Args.size(); i != e; ++i)
223 switch (getValueType(Args[i].second)) {
224 default: assert(0 && "Unknown value type!");
238 // Just to be safe, we'll always reserve the full 24 bytes of linkage area
239 // plus 32 bytes of argument space in case any called code gets funky on us.
240 if (NumBytes < 56) NumBytes = 56;
242 // Adjust the stack pointer for the new arguments...
243 // These operations are automatically eliminated by the prolog/epilog pass
244 Chain = DAG.getNode(ISD::ADJCALLSTACKDOWN, MVT::Other, Chain,
245 DAG.getConstant(NumBytes, getPointerTy()));
247 // Set up a copy of the stack pointer for use loading and storing any
248 // arguments that may not fit in the registers available for argument
250 SDOperand StackPtr = DAG.getCopyFromReg(PPC::R1, MVT::i32,
253 // Figure out which arguments are going to go in registers, and which in
254 // memory. Also, if this is a vararg function, floating point operations
255 // must be stored to our stack, and loaded into integer regs as well, if
256 // any integer regs are available for argument passing.
257 unsigned ArgOffset = 24;
258 unsigned GPR_remaining = 8;
259 unsigned FPR_remaining = 13;
260 std::vector<SDOperand> Stores;
261 for (unsigned i = 0, e = Args.size(); i != e; ++i) {
262 // PtrOff will be used to store the current argument to the stack if a
263 // register cannot be found for it.
264 SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
265 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
267 switch (getValueType(Args[i].second)) {
268 default: assert(0 && "Unexpected ValueType for argument!");
272 // Promote the integer to 32 bits. If the input type is signed use a
273 // sign extend, otherwise use a zero extend.
274 if (Args[i].second->isSigned())
275 Args[i].first =DAG.getNode(ISD::SIGN_EXTEND, MVT::i32, Args[i].first);
277 Args[i].first =DAG.getNode(ISD::ZERO_EXTEND, MVT::i32, Args[i].first);
280 if (GPR_remaining > 0) {
281 args_to_use.push_back(Args[i].first);
284 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
285 Args[i].first, PtrOff));
290 // If we have 2 or more GPRs, we won't do anything and let the ISD::CALL
291 // functionality in SelectExpr move pieces for us.
292 if (GPR_remaining > 1) {
293 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
294 Args[i].first, DAG.getConstant(1, MVT::i32));
295 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
296 Args[i].first, DAG.getConstant(0, MVT::i32));
297 args_to_use.push_back(Hi);
298 args_to_use.push_back(Lo);
300 } else if (GPR_remaining > 0) {
301 SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
302 Args[i].first, DAG.getConstant(1, MVT::i32));
303 SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32,
304 Args[i].first, DAG.getConstant(0, MVT::i32));
305 args_to_use.push_back(Hi);
306 SDOperand ConstFour = DAG.getConstant(4, getPointerTy());
307 PtrOff = DAG.getNode(ISD::ADD, MVT::i32, PtrOff, ConstFour);
308 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
312 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
313 Args[i].first, PtrOff));
318 if (FPR_remaining > 0 && GPR_remaining > 0 && isVarArg) {
321 } else if (FPR_remaining > 0) {
322 args_to_use.push_back(Args[i].first);
324 if (GPR_remaining > 0) --GPR_remaining;
326 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
327 Args[i].first, PtrOff));
332 if (FPR_remaining > 0 && GPR_remaining > 0 && isVarArg) {
334 } else if (FPR_remaining > 0) {
335 args_to_use.push_back(Args[i].first);
337 if (GPR_remaining > 0) --GPR_remaining;
338 if (GPR_remaining > 0) --GPR_remaining;
340 Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
341 Args[i].first, PtrOff));
347 Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
350 std::vector<MVT::ValueType> RetVals;
351 MVT::ValueType RetTyVT = getValueType(RetTy);
352 if (RetTyVT != MVT::isVoid)
353 RetVals.push_back(RetTyVT);
354 RetVals.push_back(MVT::Other);
356 SDOperand TheCall = SDOperand(DAG.getCall(RetVals,
357 Chain, Callee, args_to_use), 0);
358 Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
359 Chain = DAG.getNode(ISD::ADJCALLSTACKUP, MVT::Other, Chain,
360 DAG.getConstant(NumBytes, getPointerTy()));
361 return std::make_pair(TheCall, Chain);
364 std::pair<SDOperand, SDOperand>
365 PPC32TargetLowering::LowerVAStart(SDOperand Chain, SelectionDAG &DAG) {
366 //vastart just returns the address of the VarArgsFrameIndex slot.
367 return std::make_pair(DAG.getFrameIndex(VarArgsFrameIndex, MVT::i32), Chain);
370 std::pair<SDOperand,SDOperand> PPC32TargetLowering::
371 LowerVAArgNext(bool isVANext, SDOperand Chain, SDOperand VAList,
372 const Type *ArgTy, SelectionDAG &DAG) {
373 MVT::ValueType ArgVT = getValueType(ArgTy);
376 Result = DAG.getLoad(ArgVT, DAG.getEntryNode(), VAList);
379 if (ArgVT == MVT::i32 || ArgVT == MVT::f32)
382 assert((ArgVT == MVT::i64 || ArgVT == MVT::f64) &&
383 "Other types should have been promoted for varargs!");
386 Result = DAG.getNode(ISD::ADD, VAList.getValueType(), VAList,
387 DAG.getConstant(Amt, VAList.getValueType()));
389 return std::make_pair(Result, Chain);
393 std::pair<SDOperand, SDOperand> PPC32TargetLowering::
394 LowerFrameReturnAddress(bool isFrameAddress, SDOperand Chain, unsigned Depth,
401 //===--------------------------------------------------------------------===//
402 /// ISel - PPC32 specific code to select PPC32 machine instructions for
403 /// SelectionDAG operations.
404 //===--------------------------------------------------------------------===//
405 class ISel : public SelectionDAGISel {
408 PPC32TargetLowering PPC32Lowering;
410 /// ExprMap - As shared expressions are codegen'd, we keep track of which
411 /// vreg the value is produced in, so we only emit one copy of each compiled
413 std::map<SDOperand, unsigned> ExprMap;
415 unsigned GlobalBaseReg;
416 bool GlobalBaseInitialized;
419 ISel(TargetMachine &TM) : SelectionDAGISel(PPC32Lowering), PPC32Lowering(TM)
422 /// runOnFunction - Override this function in order to reset our per-function
424 virtual bool runOnFunction(Function &Fn) {
425 // Make sure we re-emit a set of the global base reg if necessary
426 GlobalBaseInitialized = false;
427 return SelectionDAGISel::runOnFunction(Fn);
430 /// InstructionSelectBasicBlock - This callback is invoked by
431 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
432 virtual void InstructionSelectBasicBlock(SelectionDAG &DAG) {
434 // Codegen the basic block.
435 Select(DAG.getRoot());
437 // Clear state used for selection.
441 unsigned ISel::getGlobalBaseReg();
442 unsigned SelectExpr(SDOperand N);
443 unsigned SelectExprFP(SDOperand N, unsigned Result);
444 void Select(SDOperand N);
446 void SelectAddr(SDOperand N, unsigned& Reg, int& offset);
447 void SelectBranchCC(SDOperand N);
450 /// canUseAsImmediateForOpcode - This method returns a value indicating whether
451 /// the ConstantSDNode N can be used as an immediate to Opcode. The return
452 /// values are either 0, 1 or 2. 0 indicates that either N is not a
453 /// ConstantSDNode, or is not suitable for use by that opcode. A return value
454 /// of 1 indicates that the constant may be used in normal immediate form. A
455 /// return value of 2 indicates that the constant may be used in shifted
456 /// immediate form. If the return value is nonzero, the constant value is
459 static unsigned canUseAsImmediateForOpcode(SDOperand N, unsigned Opcode,
461 if (N.getOpcode() != ISD::Constant) return 0;
463 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
468 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
469 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
474 if (v >= 0 && v <= 65535) { Imm = v & 0xFFFF; return 1; }
475 if ((v & 0x0000FFFF) == 0) { Imm = v >> 16; return 2; }
478 if (v <= 32767 && v >= -32768) { Imm = v & 0xFFFF; return 1; }
485 /// getGlobalBaseReg - Output the instructions required to put the
486 /// base address to use for accessing globals into a register.
488 unsigned ISel::getGlobalBaseReg() {
489 if (!GlobalBaseInitialized) {
490 // Insert the set of GlobalBaseReg into the first MBB of the function
491 MachineBasicBlock &FirstMBB = BB->getParent()->front();
492 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
493 GlobalBaseReg = MakeReg(MVT::i32);
494 BuildMI(FirstMBB, MBBI, PPC::MovePCtoLR, 0, PPC::LR);
495 BuildMI(FirstMBB, MBBI, PPC::MFLR, 1, GlobalBaseReg).addReg(PPC::LR);
496 GlobalBaseInitialized = true;
498 return GlobalBaseReg;
501 //Check to see if the load is a constant offset from a base register
502 void ISel::SelectAddr(SDOperand N, unsigned& Reg, int& offset)
509 void ISel::SelectBranchCC(SDOperand N)
511 assert(N.getOpcode() == ISD::BRCOND && "Not a BranchCC???");
512 MachineBasicBlock *Dest =
513 cast<BasicBlockSDNode>(N.getOperand(2))->getBasicBlock();
516 Select(N.getOperand(0)); //chain
517 SDOperand CC = N.getOperand(1);
519 //Giveup and do the stupid thing
520 unsigned Tmp1 = SelectExpr(CC);
521 BuildMI(BB, PPC::BNE, 2).addReg(Tmp1).addMBB(Dest);
525 unsigned ISel::SelectExprFP(SDOperand N, unsigned Result)
527 unsigned Tmp1, Tmp2, Tmp3;
529 SDNode *Node = N.Val;
530 MVT::ValueType DestType = N.getValueType();
531 unsigned opcode = N.getOpcode();
536 assert(0 && "Node not handled!\n");
542 assert (DestType == MVT::f32 &&
543 N.getOperand(0).getValueType() == MVT::f64 &&
544 "only f64 to f32 conversion supported here");
545 Tmp1 = SelectExpr(N.getOperand(0));
546 BuildMI(BB, PPC::FRSP, 1, Result).addReg(Tmp1);
550 assert (DestType == MVT::f64 &&
551 N.getOperand(0).getValueType() == MVT::f32 &&
552 "only f32 to f64 conversion supported here");
553 Tmp1 = SelectExpr(N.getOperand(0));
554 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
557 case ISD::CopyFromReg:
559 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
560 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
561 BuildMI(BB, PPC::FMR, 1, Result).addReg(Tmp1);
568 case ISD::ConstantFP:
576 case ISD::MUL: Opc = DestType == MVT::f64 ? PPC::FMUL : PPC::FMULS; break;
577 case ISD::ADD: Opc = DestType == MVT::f64 ? PPC::FADD : PPC::FADDS; break;
578 case ISD::SUB: Opc = DestType == MVT::f64 ? PPC::FSUB : PPC::FSUBS; break;
579 case ISD::SDIV: Opc = DestType == MVT::f64 ? PPC::FDIV : PPC::FDIVS; break;
582 Tmp1 = SelectExpr(N.getOperand(0));
583 Tmp2 = SelectExpr(N.getOperand(1));
584 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
587 case ISD::UINT_TO_FP:
588 case ISD::SINT_TO_FP:
591 assert(0 && "should not get here");
595 unsigned ISel::SelectExpr(SDOperand N) {
597 unsigned Tmp1, Tmp2, Tmp3;
599 unsigned opcode = N.getOpcode();
601 SDNode *Node = N.Val;
602 MVT::ValueType DestType = N.getValueType();
604 unsigned &Reg = ExprMap[N];
607 if (N.getOpcode() != ISD::CALL && N.getOpcode() != ISD::ADD_PARTS &&
608 N.getOpcode() != ISD::SUB_PARTS)
609 Reg = Result = (N.getValueType() != MVT::Other) ?
610 MakeReg(N.getValueType()) : 1;
612 // If this is a call instruction, make sure to prepare ALL of the result
613 // values as well as the chain.
614 if (N.getOpcode() == ISD::CALL) {
615 if (Node->getNumValues() == 1)
616 Reg = Result = 1; // Void call, just a chain.
618 Result = MakeReg(Node->getValueType(0));
619 ExprMap[N.getValue(0)] = Result;
620 for (unsigned i = 1, e = N.Val->getNumValues()-1; i != e; ++i)
621 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
622 ExprMap[SDOperand(Node, Node->getNumValues()-1)] = 1;
625 Result = MakeReg(Node->getValueType(0));
626 ExprMap[N.getValue(0)] = Result;
627 for (unsigned i = 1, e = N.Val->getNumValues(); i != e; ++i)
628 ExprMap[N.getValue(i)] = MakeReg(Node->getValueType(i));
632 if (DestType == MVT::f64 || DestType == MVT::f32)
633 return SelectExprFP(N, Result);
638 assert(0 && "Node not handled!\n");
640 case ISD::DYNAMIC_STACKALLOC:
641 // Generate both result values. FIXME: Need a better commment here?
643 ExprMap[N.getValue(1)] = 1;
645 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
647 // FIXME: We are currently ignoring the requested alignment for handling
648 // greater than the stack alignment. This will need to be revisited at some
649 // point. Align = N.getOperand(2);
650 if (!isa<ConstantSDNode>(N.getOperand(2)) ||
651 cast<ConstantSDNode>(N.getOperand(2))->getValue() != 0) {
652 std::cerr << "Cannot allocate stack object with greater alignment than"
653 << " the stack alignment yet!";
656 Select(N.getOperand(0));
657 Tmp1 = SelectExpr(N.getOperand(1));
658 // Subtract size from stack pointer, thereby allocating some space.
659 BuildMI(BB, PPC::SUBF, 2, PPC::R1).addReg(Tmp1).addReg(PPC::R1);
660 // Put a pointer to the space into the result register by copying the SP
661 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R1).addReg(PPC::R1);
664 case ISD::ConstantPool:
667 case ISD::FrameIndex:
670 case ISD::GlobalAddress: {
671 GlobalValue *GV = cast<GlobalAddressSDNode>(N)->getGlobal();
672 unsigned Tmp1 = MakeReg(MVT::i32);
673 BuildMI(BB, PPC::LOADHiAddr, 2, Tmp1).addReg(getGlobalBaseReg())
674 .addGlobalAddress(GV);
675 if (GV->hasWeakLinkage() || GV->isExternal()) {
676 BuildMI(BB, PPC::LWZ, 2, Result).addGlobalAddress(GV).addReg(Tmp1);
678 BuildMI(BB, PPC::LA, 2, Result).addReg(Tmp1).addGlobalAddress(GV);
686 case ISD::SEXTLOAD: {
687 // Make sure we generate both values.
689 ExprMap[N.getValue(1)] = 1; // Generate the token
691 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
693 SDOperand Chain = N.getOperand(0);
694 SDOperand Address = N.getOperand(1);
697 switch (Node->getValueType(0)) {
698 default: assert(0 && "Cannot load this type!");
699 case MVT::i1: Opc = PPC::LBZ; Tmp3 = 0; break;
700 case MVT::i8: Opc = PPC::LBZ; Tmp3 = 1; break;
701 case MVT::i16: Opc = PPC::LHZ; Tmp3 = 0; break;
702 case MVT::i32: Opc = PPC::LWZ; Tmp3 = 0; break;
705 if(Address.getOpcode() == ISD::FrameIndex) {
706 BuildMI(BB, Opc, 2, Result)
707 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex())
711 SelectAddr(Address, Tmp1, offset);
712 BuildMI(BB, Opc, 2, Result).addSImm(offset).addReg(Tmp1);
718 // Lower the chain for this call.
719 Select(N.getOperand(0));
720 ExprMap[N.getValue(Node->getNumValues()-1)] = 1;
722 // get the virtual reg for each argument
723 std::vector<unsigned> VRegs;
724 for(int i = 2, e = Node->getNumOperands(); i < e; ++i)
725 VRegs.push_back(SelectExpr(N.getOperand(i)));
727 // The ABI specifies that the first 32 bytes of args may be passed in GPRs,
728 // and that 13 FPRs may also be used for passing any floating point args.
729 int GPR_remaining = 8, FPR_remaining = 13;
730 unsigned GPR_idx = 0, FPR_idx = 0;
731 static const unsigned GPR[] = {
732 PPC::R3, PPC::R4, PPC::R5, PPC::R6,
733 PPC::R7, PPC::R8, PPC::R9, PPC::R10,
735 static const unsigned FPR[] = {
736 PPC::F1, PPC::F2, PPC::F3, PPC::F4, PPC::F5, PPC::F6,
737 PPC::F7, PPC::F8, PPC::F9, PPC::F10, PPC::F11, PPC::F12,
741 // move the vregs into the appropriate architected register or stack slot
742 for(int i = 0, e = VRegs.size(); i < e; ++i) {
743 unsigned OperandType = N.getOperand(i+2).getValueType();
744 switch(OperandType) {
747 N.getOperand(i).Val->dump();
748 std::cerr << "Type for " << i << " is: " <<
749 N.getOperand(i+2).getValueType() << "\n";
750 assert(0 && "Unknown value type for call");
755 if (GPR_remaining > 0)
756 BuildMI(BB, PPC::OR, 2, GPR[GPR_idx]).addReg(VRegs[i])
761 if (FPR_remaining > 0) {
762 BuildMI(BB, PPC::FMR, 1, FPR[FPR_idx]).addReg(VRegs[i]);
768 // All arguments consume GPRs available for argument passing
769 if (GPR_remaining > 0) {
773 if (MVT::f64 == OperandType && GPR_remaining > 0) {
779 // Emit the correct call instruction based on the type of symbol called.
780 if (GlobalAddressSDNode *GASD =
781 dyn_cast<GlobalAddressSDNode>(N.getOperand(1))) {
782 BuildMI(BB, PPC::CALLpcrel, 1).addGlobalAddress(GASD->getGlobal(), true);
783 } else if (ExternalSymbolSDNode *ESSDN =
784 dyn_cast<ExternalSymbolSDNode>(N.getOperand(1))) {
785 BuildMI(BB, PPC::CALLpcrel, 1).addExternalSymbol(ESSDN->getSymbol(), true);
787 Tmp1 = SelectExpr(N.getOperand(1));
788 BuildMI(BB, PPC::OR, 2, PPC::R12).addReg(Tmp1).addReg(Tmp1);
789 BuildMI(BB, PPC::MTCTR, 1).addReg(PPC::R12);
790 BuildMI(BB, PPC::CALLindirect, 3).addImm(20).addImm(0).addReg(PPC::R12);
793 switch (Node->getValueType(0)) {
794 default: assert(0 && "Unknown value type for call result!");
795 case MVT::Other: return 1;
800 BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
801 if (Node->getValueType(1) == MVT::i32)
802 BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R4).addReg(PPC::R4);
806 BuildMI(BB, PPC::FMR, 1, Result).addReg(PPC::F1);
809 return Result+N.ResNo;
812 case ISD::SIGN_EXTEND:
813 case ISD::SIGN_EXTEND_INREG:
814 Tmp1 = SelectExpr(N.getOperand(0));
815 BuildMI(BB, PPC::EXTSH, 1, Result).addReg(Tmp1);
818 case ISD::ZERO_EXTEND_INREG:
819 Tmp1 = SelectExpr(N.getOperand(0));
820 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
823 assert(0 && "Zero Extend InReg not there yet");
825 case MVT::i16: Tmp2 = 16; break;
826 case MVT::i8: Tmp2 = 24; break;
827 case MVT::i1: Tmp2 = 31; break;
829 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(0).addImm(0)
830 .addImm(Tmp2).addImm(31);
833 case ISD::CopyFromReg:
835 Result = ExprMap[N.getValue(0)] = MakeReg(N.getValue(0).getValueType());
836 Tmp1 = dyn_cast<RegSDNode>(Node)->getReg();
837 BuildMI(BB, PPC::OR, 2, Result).addReg(Tmp1).addReg(Tmp1);
841 Tmp1 = SelectExpr(N.getOperand(0));
842 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
843 Tmp2 = CN->getValue() & 0x1F;
844 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(Tmp2).addImm(0)
847 Tmp2 = SelectExpr(N.getOperand(1));
848 BuildMI(BB, PPC::SLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
853 Tmp1 = SelectExpr(N.getOperand(0));
854 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
855 Tmp2 = CN->getValue() & 0x1F;
856 BuildMI(BB, PPC::RLWINM, 5, Result).addReg(Tmp1).addImm(32-Tmp2)
857 .addImm(Tmp2).addImm(31);
859 Tmp2 = SelectExpr(N.getOperand(1));
860 BuildMI(BB, PPC::SRW, 2, Result).addReg(Tmp1).addReg(Tmp2);
865 Tmp1 = SelectExpr(N.getOperand(0));
866 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N.getOperand(1))) {
867 Tmp2 = CN->getValue() & 0x1F;
868 BuildMI(BB, PPC::SRAWI, 2, Result).addReg(Tmp1).addImm(Tmp2);
870 Tmp2 = SelectExpr(N.getOperand(1));
871 BuildMI(BB, PPC::SRAW, 2, Result).addReg(Tmp1).addReg(Tmp2);
876 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
877 Tmp1 = SelectExpr(N.getOperand(0));
878 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
879 default: assert(0 && "unhandled result code");
880 case 0: // No immediate
881 Tmp2 = SelectExpr(N.getOperand(1));
882 BuildMI(BB, PPC::ADD, 2, Result).addReg(Tmp1).addReg(Tmp2);
884 case 1: // Low immediate
885 BuildMI(BB, PPC::ADDI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
887 case 2: // Shifted immediate
888 BuildMI(BB, PPC::ADDIS, 2, Result).addReg(Tmp1).addSImm(Tmp2);
896 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
897 Tmp1 = SelectExpr(N.getOperand(0));
898 switch(canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2)) {
899 default: assert(0 && "unhandled result code");
900 case 0: // No immediate
901 Tmp2 = SelectExpr(N.getOperand(1));
903 case ISD::AND: Opc = PPC::AND; break;
904 case ISD::OR: Opc = PPC::OR; break;
905 case ISD::XOR: Opc = PPC::XOR; break;
907 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addReg(Tmp2);
909 case 1: // Low immediate
911 case ISD::AND: Opc = PPC::ANDIo; break;
912 case ISD::OR: Opc = PPC::ORI; break;
913 case ISD::XOR: Opc = PPC::XORI; break;
915 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
917 case 2: // Shifted immediate
919 case ISD::AND: Opc = PPC::ANDISo; break;
920 case ISD::OR: Opc = PPC::ORIS; break;
921 case ISD::XOR: Opc = PPC::XORIS; break;
923 BuildMI(BB, Opc, 2, Result).addReg(Tmp1).addImm(Tmp2);
929 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
930 Tmp1 = SelectExpr(N.getOperand(0));
931 Tmp2 = SelectExpr(N.getOperand(1));
932 BuildMI(BB, PPC::SUBF, 2, Result).addReg(Tmp2).addReg(Tmp1);
936 assert (DestType == MVT::i32 && "Only do arithmetic on i32s!");
937 Tmp1 = SelectExpr(N.getOperand(0));
938 if (1 == canUseAsImmediateForOpcode(N.getOperand(1), opcode, Tmp2))
939 BuildMI(BB, PPC::MULLI, 2, Result).addReg(Tmp1).addSImm(Tmp2);
941 Tmp2 = SelectExpr(N.getOperand(1));
942 BuildMI(BB, PPC::MULLW, 2, Result).addReg(Tmp1).addReg(Tmp2);
954 case ISD::FP_TO_UINT:
955 case ISD::FP_TO_SINT:
965 switch (N.getValueType()) {
966 default: assert(0 && "Cannot use constants of this type!");
968 BuildMI(BB, PPC::LI, 1, Result)
969 .addSImm(!cast<ConstantSDNode>(N)->isNullValue());
973 int v = (int)cast<ConstantSDNode>(N)->getSignExtended();
974 if (v < 32768 && v >= -32768) {
975 BuildMI(BB, PPC::LI, 1, Result).addSImm(v);
977 Tmp1 = MakeReg(MVT::i32);
978 BuildMI(BB, PPC::LIS, 1, Tmp1).addSImm(v >> 16);
979 BuildMI(BB, PPC::ORI, 2, Result).addReg(Tmp1).addImm(v & 0xFFFF);
989 void ISel::Select(SDOperand N) {
990 unsigned Tmp1, Tmp2, Opc;
991 unsigned opcode = N.getOpcode();
993 if (!ExprMap.insert(std::make_pair(N, 1)).second)
994 return; // Already selected.
996 SDNode *Node = N.Val;
998 switch (Node->getOpcode()) {
1000 Node->dump(); std::cerr << "\n";
1001 assert(0 && "Node not handled yet!");
1002 case ISD::EntryToken: return; // Noop
1003 case ISD::TokenFactor:
1004 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i)
1005 Select(Node->getOperand(i));
1007 case ISD::ADJCALLSTACKDOWN:
1008 case ISD::ADJCALLSTACKUP:
1009 Select(N.getOperand(0));
1010 Tmp1 = cast<ConstantSDNode>(N.getOperand(1))->getValue();
1011 Opc = N.getOpcode() == ISD::ADJCALLSTACKDOWN ? PPC::ADJCALLSTACKDOWN :
1012 PPC::ADJCALLSTACKUP;
1013 BuildMI(BB, Opc, 1).addImm(Tmp1);
1016 MachineBasicBlock *Dest =
1017 cast<BasicBlockSDNode>(N.getOperand(1))->getBasicBlock();
1018 Select(N.getOperand(0));
1019 BuildMI(BB, PPC::B, 1).addMBB(Dest);
1025 case ISD::CopyToReg:
1026 Select(N.getOperand(0));
1027 Tmp1 = SelectExpr(N.getOperand(1));
1028 Tmp2 = cast<RegSDNode>(N)->getReg();
1031 if (N.getOperand(1).getValueType() == MVT::f64 ||
1032 N.getOperand(1).getValueType() == MVT::f32)
1033 BuildMI(BB, PPC::FMR, 1, Tmp2).addReg(Tmp1);
1035 BuildMI(BB, PPC::OR, 2, Tmp2).addReg(Tmp1).addReg(Tmp1);
1038 case ISD::ImplicitDef:
1039 Select(N.getOperand(0));
1040 BuildMI(BB, PPC::IMPLICIT_DEF, 0, cast<RegSDNode>(N)->getReg());
1043 switch (N.getNumOperands()) {
1045 assert(0 && "Unknown return instruction!");
1047 assert(N.getOperand(1).getValueType() == MVT::i32 &&
1048 N.getOperand(2).getValueType() == MVT::i32 &&
1049 "Unknown two-register value!");
1050 Select(N.getOperand(0));
1051 Tmp1 = SelectExpr(N.getOperand(1));
1052 Tmp2 = SelectExpr(N.getOperand(2));
1053 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
1054 BuildMI(BB, PPC::OR, 2, PPC::R4).addReg(Tmp2).addReg(Tmp2);
1057 Select(N.getOperand(0));
1058 Tmp1 = SelectExpr(N.getOperand(1));
1059 switch (N.getOperand(1).getValueType()) {
1061 assert(0 && "Unknown return type!");
1064 BuildMI(BB, PPC::FMR, 1, PPC::F1).addReg(Tmp1);
1067 BuildMI(BB, PPC::OR, 2, PPC::R3).addReg(Tmp1).addReg(Tmp1);
1071 Select(N.getOperand(0));
1074 BuildMI(BB, PPC::BLR, 0); // Just emit a 'ret' instruction
1076 case ISD::TRUNCSTORE:
1079 SDOperand Chain = N.getOperand(0);
1080 SDOperand Value = N.getOperand(1);
1081 SDOperand Address = N.getOperand(2);
1084 Tmp1 = SelectExpr(Value); //value
1086 if (opcode == ISD::STORE) {
1087 switch(Value.getValueType()) {
1088 default: assert(0 && "unknown Type in store");
1089 case MVT::i32: Opc = PPC::STW; break;
1090 case MVT::f64: Opc = PPC::STFD; break;
1091 case MVT::f32: Opc = PPC::STFS; break;
1093 } else { //ISD::TRUNCSTORE
1094 switch(cast<MVTSDNode>(Node)->getExtraValueType()) {
1095 default: assert(0 && "unknown Type in store");
1096 case MVT::i1: //FIXME: DAG does not promote this load
1097 case MVT::i8: Opc = PPC::STB; break;
1098 case MVT::i16: Opc = PPC::STH; break;
1102 if (Address.getOpcode() == ISD::GlobalAddress)
1104 BuildMI(BB, Opc, 2).addReg(Tmp1)
1105 .addGlobalAddress(cast<GlobalAddressSDNode>(Address)->getGlobal());
1107 else if(Address.getOpcode() == ISD::FrameIndex)
1109 BuildMI(BB, Opc, 2).addReg(Tmp1)
1110 .addFrameIndex(cast<FrameIndexSDNode>(Address)->getIndex());
1115 SelectAddr(Address, Tmp2, offset);
1116 BuildMI(BB, Opc, 3).addReg(Tmp1).addImm(offset).addReg(Tmp2);
1124 case ISD::CopyFromReg:
1126 case ISD::DYNAMIC_STACKALLOC:
1131 assert(0 && "Should not be reached!");
1135 /// createPPC32PatternInstructionSelector - This pass converts an LLVM function
1136 /// into a machine code representation using pattern matching and a machine
1137 /// description file.
1139 FunctionPass *llvm::createPPC32ISelPattern(TargetMachine &TM) {
1140 return new ISel(TM);