1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
20 let EncoderMethod = "getImm16Encoding";
21 let ParserMatchClass = PPCS16ImmAsmOperand;
22 let DecoderMethod = "decodeSImmOperand<16>";
24 def u16imm64 : Operand<i64> {
25 let PrintMethod = "printU16ImmOperand";
26 let EncoderMethod = "getImm16Encoding";
27 let ParserMatchClass = PPCU16ImmAsmOperand;
28 let DecoderMethod = "decodeUImmOperand<16>";
30 def s17imm64 : Operand<i64> {
31 // This operand type is used for addis/lis to allow the assembler parser
32 // to accept immediates in the range -65536..65535 for compatibility with
33 // the GNU assembler. The operand is treated as 16-bit otherwise.
34 let PrintMethod = "printS16ImmOperand";
35 let EncoderMethod = "getImm16Encoding";
36 let ParserMatchClass = PPCS17ImmAsmOperand;
37 let DecoderMethod = "decodeSImmOperand<16>";
39 def tocentry : Operand<iPTR> {
40 let MIOperandInfo = (ops i64imm:$imm);
42 def tlsreg : Operand<i64> {
43 let EncoderMethod = "getTLSRegEncoding";
44 let ParserMatchClass = PPCTLSRegOperand;
46 def tlsgd : Operand<i64> {}
47 def tlscall : Operand<i64> {
48 let PrintMethod = "printTLSCall";
49 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym);
50 let EncoderMethod = "getTLSCallEncoding";
53 //===----------------------------------------------------------------------===//
54 // 64-bit transformation functions.
57 def SHL64 : SDNodeXForm<imm, [{
58 // Transformation function: 63 - imm
59 return getI32Imm(63 - N->getZExtValue());
62 def SRL64 : SDNodeXForm<imm, [{
63 // Transformation function: 64 - imm
64 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
67 def HI32_48 : SDNodeXForm<imm, [{
68 // Transformation function: shift the immediate value down into the low bits.
69 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
72 def HI48_64 : SDNodeXForm<imm, [{
73 // Transformation function: shift the immediate value down into the low bits.
74 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
78 //===----------------------------------------------------------------------===//
82 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
83 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
84 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in {
85 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
87 Requires<[In64BitMode]>;
88 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
89 "b${cond:cc}ctr${cond:pm} ${cond:reg}", IIC_BrB,
91 Requires<[In64BitMode]>;
93 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
94 "bcctr 12, $bi, 0", IIC_BrB, []>,
95 Requires<[In64BitMode]>;
96 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
97 "bcctr 4, $bi, 0", IIC_BrB, []>,
98 Requires<[In64BitMode]>;
103 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
106 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
107 let Defs = [CTR8], Uses = [CTR8] in {
108 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
110 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
114 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in {
115 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
116 "bdzlr", IIC_BrB, []>;
117 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
118 "bdnzlr", IIC_BrB, []>;
124 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
125 // Convenient aliases for call instructions
127 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func),
128 "bl $func", IIC_BrB, []>; // See Pat patterns below.
130 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func),
131 "bl $func", IIC_BrB, []>;
133 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func),
134 "bla $func", IIC_BrB, [(PPCcall (i64 imm:$func))]>;
136 let Uses = [RM], isCodeGenOnly = 1 in {
137 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24,
138 (outs), (ins calltarget:$func),
139 "bl $func\n\tnop", IIC_BrB, []>;
141 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24,
142 (outs), (ins tlscall:$func),
143 "bl $func\n\tnop", IIC_BrB, []>;
145 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24,
146 (outs), (ins abscalltarget:$func),
147 "bla $func\n\tnop", IIC_BrB,
148 [(PPCcall_nop (i64 imm:$func))]>;
150 let Uses = [CTR8, RM] in {
151 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins),
152 "bctrl", IIC_BrB, [(PPCbctrl)]>,
153 Requires<[In64BitMode]>;
155 let isCodeGenOnly = 1 in {
156 def BCCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond),
157 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", IIC_BrB,
159 Requires<[In64BitMode]>;
161 def BCCTRL8 : XLForm_2_br2<19, 528, 12, 1, (outs), (ins crbitrc:$bi),
162 "bcctrl 12, $bi, 0", IIC_BrB, []>,
163 Requires<[In64BitMode]>;
164 def BCCTRL8n : XLForm_2_br2<19, 528, 4, 1, (outs), (ins crbitrc:$bi),
165 "bcctrl 4, $bi, 0", IIC_BrB, []>,
166 Requires<[In64BitMode]>;
170 } // Interpretation64Bit
172 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
173 // previous definition must be marked as CodeGen only to prevent decoding
175 let Interpretation64Bit = 1, isAsmParserOnly = 1 in
176 let isCall = 1, PPC970_Unit = 7, Defs = [LR8], Uses = [RM] in
177 def BL8_TLS_ : IForm<18, 0, 1, (outs), (ins tlscall:$func),
178 "bl $func", IIC_BrB, []>;
181 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
182 (BL8 tglobaladdr:$dst)>;
183 def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)),
184 (BL8_NOP tglobaladdr:$dst)>;
186 def : Pat<(PPCcall (i64 texternalsym:$dst)),
187 (BL8 texternalsym:$dst)>;
188 def : Pat<(PPCcall_nop (i64 texternalsym:$dst)),
189 (BL8_NOP texternalsym:$dst)>;
192 let usesCustomInserter = 1 in {
193 let Defs = [CR0] in {
194 def ATOMIC_LOAD_ADD_I64 : Pseudo<
195 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64",
196 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>;
197 def ATOMIC_LOAD_SUB_I64 : Pseudo<
198 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64",
199 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>;
200 def ATOMIC_LOAD_OR_I64 : Pseudo<
201 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64",
202 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>;
203 def ATOMIC_LOAD_XOR_I64 : Pseudo<
204 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64",
205 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>;
206 def ATOMIC_LOAD_AND_I64 : Pseudo<
207 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64",
208 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>;
209 def ATOMIC_LOAD_NAND_I64 : Pseudo<
210 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64",
211 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>;
213 def ATOMIC_CMP_SWAP_I64 : Pseudo<
214 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64",
215 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>;
217 def ATOMIC_SWAP_I64 : Pseudo<
218 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64",
219 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>;
223 // Instructions to support atomic operations
224 def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr),
225 "ldarx $rD, $ptr", IIC_LdStLDARX,
226 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>;
229 def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst),
230 "stdcx. $rS, $dst", IIC_LdStSTDCX,
231 [(PPCstcx i64:$rS, xoaddr:$dst)]>,
234 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
235 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
236 def TCRETURNdi8 :Pseudo< (outs),
237 (ins calltarget:$dst, i32imm:$offset),
238 "#TC_RETURNd8 $dst $offset",
241 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
242 def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset),
243 "#TC_RETURNa8 $func $offset",
244 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
246 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
247 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
248 "#TC_RETURNr8 $dst $offset",
251 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
252 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in
253 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
255 Requires<[In64BitMode]>;
257 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
258 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
259 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
263 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
264 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
265 def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst),
268 } // Interpretation64Bit
270 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
271 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
273 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
274 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
276 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
277 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
280 // 64-bit CR instructions
281 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
282 let neverHasSideEffects = 1 in {
283 def MTOCRF8: XFXForm_5a<31, 144, (outs crbitm:$FXM), (ins g8rc:$ST),
284 "mtocrf $FXM, $ST", IIC_BrMCRX>,
285 PPC970_DGroup_First, PPC970_Unit_CRU;
287 def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
288 "mtcrf $FXM, $rS", IIC_BrMCRX>,
289 PPC970_MicroCode, PPC970_Unit_CRU;
291 let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
292 def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
293 "mfocrf $rT, $FXM", IIC_SprMFCRF>,
294 PPC970_DGroup_First, PPC970_Unit_CRU;
296 def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins),
297 "mfcr $rT", IIC_SprMFCR>,
298 PPC970_MicroCode, PPC970_Unit_CRU;
299 } // neverHasSideEffects = 1
301 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
303 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf),
305 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>,
306 Requires<[In64BitMode]>;
307 let isTerminator = 1 in
308 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf),
309 "#EH_SJLJ_LONGJMP64",
310 [(PPCeh_sjlj_longjmp addr:$buf)]>,
311 Requires<[In64BitMode]>;
314 //===----------------------------------------------------------------------===//
315 // 64-bit SPR manipulation instrs.
317 let Uses = [CTR8] in {
318 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins),
319 "mfctr $rT", IIC_SprMFSPR>,
320 PPC970_DGroup_First, PPC970_Unit_FXU;
322 let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in {
323 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
324 "mtctr $rS", IIC_SprMTSPR>,
325 PPC970_DGroup_First, PPC970_Unit_FXU;
327 let hasSideEffects = 1, Defs = [CTR8] in {
328 let Pattern = [(int_ppc_mtctr i64:$rS)] in
329 def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS),
330 "mtctr $rS", IIC_SprMTSPR>,
331 PPC970_DGroup_First, PPC970_Unit_FXU;
334 let Pattern = [(set i64:$rT, readcyclecounter)] in
335 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins),
336 "mfspr $rT, 268", IIC_SprMFTB>,
337 PPC970_DGroup_First, PPC970_Unit_FXU;
338 // Note that encoding mftb using mfspr is now the preferred form,
339 // and has been since at least ISA v2.03. The mftb instruction has
340 // now been phased out. Using mfspr, however, is known not to work on
343 let Defs = [X1], Uses = [X1] in
344 def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8",
346 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>;
348 let Defs = [LR8] in {
349 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS),
350 "mtlr $rS", IIC_SprMTSPR>,
351 PPC970_DGroup_First, PPC970_Unit_FXU;
353 let Uses = [LR8] in {
354 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins),
355 "mflr $rT", IIC_SprMFSPR>,
356 PPC970_DGroup_First, PPC970_Unit_FXU;
358 } // Interpretation64Bit
360 //===----------------------------------------------------------------------===//
361 // Fixed point instructions.
364 let PPC970_Unit = 1 in { // FXU Operations.
365 let Interpretation64Bit = 1 in {
366 let neverHasSideEffects = 1 in {
367 let isCodeGenOnly = 1 in {
369 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
370 def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm),
371 "li $rD, $imm", IIC_IntSimple,
372 [(set i64:$rD, imm64SExt16:$imm)]>;
373 def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm),
374 "lis $rD, $imm", IIC_IntSimple,
375 [(set i64:$rD, imm16ShiftedSExt:$imm)]>;
379 let isCommutable = 1 in {
380 defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
381 "nand", "$rA, $rS, $rB", IIC_IntSimple,
382 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>;
383 defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
384 "and", "$rA, $rS, $rB", IIC_IntSimple,
385 [(set i64:$rA, (and i64:$rS, i64:$rB))]>;
387 defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
388 "andc", "$rA, $rS, $rB", IIC_IntSimple,
389 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>;
390 let isCommutable = 1 in {
391 defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
392 "or", "$rA, $rS, $rB", IIC_IntSimple,
393 [(set i64:$rA, (or i64:$rS, i64:$rB))]>;
394 defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
395 "nor", "$rA, $rS, $rB", IIC_IntSimple,
396 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>;
398 defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
399 "orc", "$rA, $rS, $rB", IIC_IntSimple,
400 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>;
401 let isCommutable = 1 in {
402 defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
403 "eqv", "$rA, $rS, $rB", IIC_IntSimple,
404 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>;
405 defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),
406 "xor", "$rA, $rS, $rB", IIC_IntSimple,
407 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>;
408 } // let isCommutable = 1
410 // Logical ops with immediate.
411 let Defs = [CR0] in {
412 def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
413 "andi. $dst, $src1, $src2", IIC_IntGeneral,
414 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>,
416 def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
417 "andis. $dst, $src1, $src2", IIC_IntGeneral,
418 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>,
421 def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
422 "ori $dst, $src1, $src2", IIC_IntSimple,
423 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>;
424 def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
425 "oris $dst, $src1, $src2", IIC_IntSimple,
426 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>;
427 def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
428 "xori $dst, $src1, $src2", IIC_IntSimple,
429 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>;
430 def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm64:$src2),
431 "xoris $dst, $src1, $src2", IIC_IntSimple,
432 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>;
434 let isCommutable = 1 in
435 defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
436 "add", "$rT, $rA, $rB", IIC_IntSimple,
437 [(set i64:$rT, (add i64:$rA, i64:$rB))]>;
438 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
439 // initial-exec thread-local storage model.
440 def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
441 "add $rT, $rA, $rB", IIC_IntSimple,
442 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>;
444 let isCommutable = 1 in
445 defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
446 "addc", "$rT, $rA, $rB", IIC_IntGeneral,
447 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>,
448 PPC970_DGroup_Cracked;
450 let Defs = [CARRY] in
451 def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
452 "addic $rD, $rA, $imm", IIC_IntGeneral,
453 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>;
454 def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm),
455 "addi $rD, $rA, $imm", IIC_IntSimple,
456 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>;
457 def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm),
458 "addis $rD, $rA, $imm", IIC_IntSimple,
459 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>;
461 let Defs = [CARRY] in {
462 def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
463 "subfic $rD, $rA, $imm", IIC_IntGeneral,
464 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>;
465 defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
466 "subfc", "$rT, $rA, $rB", IIC_IntGeneral,
467 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>,
468 PPC970_DGroup_Cracked;
470 defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
471 "subf", "$rT, $rA, $rB", IIC_IntGeneral,
472 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>;
473 defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA),
474 "neg", "$rT, $rA", IIC_IntSimple,
475 [(set i64:$rT, (ineg i64:$rA))]>;
476 let Uses = [CARRY] in {
477 let isCommutable = 1 in
478 defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
479 "adde", "$rT, $rA, $rB", IIC_IntGeneral,
480 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>;
481 defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA),
482 "addme", "$rT, $rA", IIC_IntGeneral,
483 [(set i64:$rT, (adde i64:$rA, -1))]>;
484 defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA),
485 "addze", "$rT, $rA", IIC_IntGeneral,
486 [(set i64:$rT, (adde i64:$rA, 0))]>;
487 defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
488 "subfe", "$rT, $rA, $rB", IIC_IntGeneral,
489 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>;
490 defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA),
491 "subfme", "$rT, $rA", IIC_IntGeneral,
492 [(set i64:$rT, (sube -1, i64:$rA))]>;
493 defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA),
494 "subfze", "$rT, $rA", IIC_IntGeneral,
495 [(set i64:$rT, (sube 0, i64:$rA))]>;
499 // FIXME: Duplicating this for the asm parser should be unnecessary, but the
500 // previous definition must be marked as CodeGen only to prevent decoding
502 let isAsmParserOnly = 1 in
503 def ADD8TLS_ : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB),
504 "add $rT, $rA, $rB", IIC_IntSimple, []>;
506 let isCommutable = 1 in {
507 defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
508 "mulhd", "$rT, $rA, $rB", IIC_IntMulHW,
509 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>;
510 defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
511 "mulhdu", "$rT, $rA, $rB", IIC_IntMulHWU,
512 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>;
515 } // Interpretation64Bit
517 let isCompare = 1, neverHasSideEffects = 1 in {
518 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
519 "cmpd $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
520 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB),
521 "cmpld $crD, $rA, $rB", IIC_IntCompare>, isPPC64;
522 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm64:$imm),
523 "cmpdi $crD, $rA, $imm", IIC_IntCompare>, isPPC64;
524 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm64:$src2),
525 "cmpldi $dst, $src1, $src2",
526 IIC_IntCompare>, isPPC64;
529 let neverHasSideEffects = 1 in {
530 defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
531 "sld", "$rA, $rS, $rB", IIC_IntRotateD,
532 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64;
533 defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
534 "srd", "$rA, $rS, $rB", IIC_IntRotateD,
535 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64;
536 defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB),
537 "srad", "$rA, $rS, $rB", IIC_IntRotateD,
538 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64;
540 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
541 defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS),
542 "extsb", "$rA, $rS", IIC_IntSimple,
543 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>;
544 defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS),
545 "extsh", "$rA, $rS", IIC_IntSimple,
546 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>;
547 } // Interpretation64Bit
550 let isCodeGenOnly = 1 in {
551 def EXTSB8_32_64 : XForm_11<31, 954, (outs g8rc:$rA), (ins gprc:$rS),
552 "extsb $rA, $rS", IIC_IntSimple, []>, isPPC64;
553 def EXTSH8_32_64 : XForm_11<31, 922, (outs g8rc:$rA), (ins gprc:$rS),
554 "extsh $rA, $rS", IIC_IntSimple, []>, isPPC64;
555 } // isCodeGenOnly for fast-isel
557 defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS),
558 "extsw", "$rA, $rS", IIC_IntSimple,
559 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64;
560 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
561 defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS),
562 "extsw", "$rA, $rS", IIC_IntSimple,
563 [(set i64:$rA, (sext i32:$rS))]>, isPPC64;
565 defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH),
566 "sradi", "$rA, $rS, $SH", IIC_IntRotateDI,
567 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64;
568 defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS),
569 "cntlzd", "$rA, $rS", IIC_IntGeneral,
570 [(set i64:$rA, (ctlz i64:$rS))]>;
571 def POPCNTD : XForm_11<31, 506, (outs g8rc:$rA), (ins g8rc:$rS),
572 "popcntd $rA, $rS", IIC_IntGeneral,
573 [(set i64:$rA, (ctpop i64:$rS))]>;
575 // popcntw also does a population count on the high 32 bits (storing the
576 // results in the high 32-bits of the output). We'll ignore that here (which is
577 // safe because we never separately use the high part of the 64-bit registers).
578 def POPCNTW : XForm_11<31, 378, (outs gprc:$rA), (ins gprc:$rS),
579 "popcntw $rA, $rS", IIC_IntGeneral,
580 [(set i32:$rA, (ctpop i32:$rS))]>;
582 defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
583 "divd", "$rT, $rA, $rB", IIC_IntDivD,
584 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64,
585 PPC970_DGroup_First, PPC970_DGroup_Cracked;
586 defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
587 "divdu", "$rT, $rA, $rB", IIC_IntDivD,
588 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64,
589 PPC970_DGroup_First, PPC970_DGroup_Cracked;
590 let isCommutable = 1 in
591 defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
592 "mulld", "$rT, $rA, $rB", IIC_IntMulHD,
593 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64;
594 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
595 def MULLI8 : DForm_2<7, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm),
596 "mulli $rD, $rA, $imm", IIC_IntMulLI,
597 [(set i64:$rD, (mul i64:$rA, imm64SExt16:$imm))]>;
600 let neverHasSideEffects = 1 in {
601 let isCommutable = 1 in {
602 defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA),
603 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE),
604 "rldimi", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
605 []>, isPPC64, RegConstraint<"$rSi = $rA">,
609 // Rotate instructions.
610 defm RLDCL : MDSForm_1r<30, 8,
611 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
612 "rldcl", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
614 defm RLDCR : MDSForm_1r<30, 9,
615 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE),
616 "rldcr", "$rA, $rS, $rB, $MBE", IIC_IntRotateD,
618 defm RLDICL : MDForm_1r<30, 0,
619 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
620 "rldicl", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
623 let isCodeGenOnly = 1 in
624 def RLDICL_32_64 : MDForm_1<30, 0,
626 (ins gprc:$rS, u6imm:$SH, u6imm:$MBE),
627 "rldicl $rA, $rS, $SH, $MBE", IIC_IntRotateDI,
630 defm RLDICR : MDForm_1r<30, 1,
631 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
632 "rldicr", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
634 defm RLDIC : MDForm_1r<30, 2,
635 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE),
636 "rldic", "$rA, $rS, $SH, $MBE", IIC_IntRotateDI,
639 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
640 defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA),
641 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
642 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IIC_IntGeneral,
645 let isCommutable = 1 in {
646 // RLWIMI can be commuted if the rotate amount is zero.
647 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
648 defm RLWIMI8 : MForm_2r<20, (outs g8rc:$rA),
649 (ins g8rc:$rSi, g8rc:$rS, u5imm:$SH, u5imm:$MB,
650 u5imm:$ME), "rlwimi", "$rA, $rS, $SH, $MB, $ME",
651 IIC_IntRotate, []>, PPC970_DGroup_Cracked,
652 RegConstraint<"$rSi = $rA">, NoEncode<"$rSi">;
656 def ISEL8 : AForm_4<31, 15,
657 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond),
658 "isel $rT, $rA, $rB, $cond", IIC_IntGeneral,
660 } // Interpretation64Bit
661 } // neverHasSideEffects = 1
662 } // End FXU Operations.
665 //===----------------------------------------------------------------------===//
666 // Load/Store instructions.
670 // Sign extending loads.
671 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
672 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
673 def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src),
674 "lha $rD, $src", IIC_LdStLHA,
675 [(set i64:$rD, (sextloadi16 iaddr:$src))]>,
676 PPC970_DGroup_Cracked;
677 def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src),
678 "lwa $rD, $src", IIC_LdStLWA,
680 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
681 PPC970_DGroup_Cracked;
682 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
683 def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src),
684 "lhax $rD, $src", IIC_LdStLHA,
685 [(set i64:$rD, (sextloadi16 xaddr:$src))]>,
686 PPC970_DGroup_Cracked;
687 def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src),
688 "lwax $rD, $src", IIC_LdStLHA,
689 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
690 PPC970_DGroup_Cracked;
692 let isCodeGenOnly = 1, mayLoad = 1 in {
693 def LWA_32 : DSForm_1<58, 2, (outs gprc:$rD), (ins memrix:$src),
694 "lwa $rD, $src", IIC_LdStLWA, []>, isPPC64,
695 PPC970_DGroup_Cracked;
696 def LWAX_32 : XForm_1<31, 341, (outs gprc:$rD), (ins memrr:$src),
697 "lwax $rD, $src", IIC_LdStLHA, []>, isPPC64,
698 PPC970_DGroup_Cracked;
699 } // end fast-isel isCodeGenOnly
702 let mayLoad = 1, neverHasSideEffects = 1 in {
703 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
704 def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
706 "lhau $rD, $addr", IIC_LdStLHAU,
707 []>, RegConstraint<"$addr.reg = $ea_result">,
708 NoEncode<"$ea_result">;
711 let Interpretation64Bit = 1, isCodeGenOnly = 1 in
712 def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
714 "lhaux $rD, $addr", IIC_LdStLHAUX,
715 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
716 NoEncode<"$ea_result">;
717 def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
719 "lwaux $rD, $addr", IIC_LdStLHAUX,
720 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
721 NoEncode<"$ea_result">, isPPC64;
725 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
726 // Zero extending loads.
727 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
728 def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src),
729 "lbz $rD, $src", IIC_LdStLoad,
730 [(set i64:$rD, (zextloadi8 iaddr:$src))]>;
731 def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src),
732 "lhz $rD, $src", IIC_LdStLoad,
733 [(set i64:$rD, (zextloadi16 iaddr:$src))]>;
734 def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src),
735 "lwz $rD, $src", IIC_LdStLoad,
736 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
738 def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src),
739 "lbzx $rD, $src", IIC_LdStLoad,
740 [(set i64:$rD, (zextloadi8 xaddr:$src))]>;
741 def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src),
742 "lhzx $rD, $src", IIC_LdStLoad,
743 [(set i64:$rD, (zextloadi16 xaddr:$src))]>;
744 def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src),
745 "lwzx $rD, $src", IIC_LdStLoad,
746 [(set i64:$rD, (zextloadi32 xaddr:$src))]>;
750 let mayLoad = 1, neverHasSideEffects = 1 in {
751 def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
752 "lbzu $rD, $addr", IIC_LdStLoadUpd,
753 []>, RegConstraint<"$addr.reg = $ea_result">,
754 NoEncode<"$ea_result">;
755 def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
756 "lhzu $rD, $addr", IIC_LdStLoadUpd,
757 []>, RegConstraint<"$addr.reg = $ea_result">,
758 NoEncode<"$ea_result">;
759 def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
760 "lwzu $rD, $addr", IIC_LdStLoadUpd,
761 []>, RegConstraint<"$addr.reg = $ea_result">,
762 NoEncode<"$ea_result">;
764 def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
766 "lbzux $rD, $addr", IIC_LdStLoadUpdX,
767 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
768 NoEncode<"$ea_result">;
769 def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
771 "lhzux $rD, $addr", IIC_LdStLoadUpdX,
772 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
773 NoEncode<"$ea_result">;
774 def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
776 "lwzux $rD, $addr", IIC_LdStLoadUpdX,
777 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
778 NoEncode<"$ea_result">;
781 } // Interpretation64Bit
784 // Full 8-byte loads.
785 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
786 def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src),
787 "ld $rD, $src", IIC_LdStLD,
788 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
789 // The following four definitions are selected for small code model only.
790 // Otherwise, we need to create two instructions to form a 32-bit offset,
791 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
792 def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
795 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64;
796 def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
799 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64;
800 def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
803 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64;
804 def LDtocBA: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg),
807 (PPCtoc_entry tblockaddress:$disp, i64:$reg))]>, isPPC64;
809 let hasSideEffects = 1, isCodeGenOnly = 1, RST = 2, Defs = [X2] in
810 def LDinto_toc: DSForm_1<58, 0, (outs), (ins memrix:$src),
811 "ld 2, $src", IIC_LdStLD,
812 [(PPCload_toc ixaddr:$src)]>, isPPC64;
814 def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src),
815 "ldx $rD, $src", IIC_LdStLD,
816 [(set i64:$rD, (load xaddr:$src))]>, isPPC64;
817 def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src),
818 "ldbrx $rD, $src", IIC_LdStLoad,
819 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64;
821 let mayLoad = 1, neverHasSideEffects = 1 in {
822 def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
823 "ldu $rD, $addr", IIC_LdStLDU,
824 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
825 NoEncode<"$ea_result">;
827 def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result),
829 "ldux $rD, $addr", IIC_LdStLDUX,
830 []>, RegConstraint<"$addr.ptrreg = $ea_result">,
831 NoEncode<"$ea_result">, isPPC64;
835 def : Pat<(PPCload ixaddr:$src),
837 def : Pat<(PPCload xaddr:$src),
840 // Support for medium and large code model.
841 def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
844 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>,
846 def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg),
849 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64;
850 def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp),
853 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64;
855 // Support for thread-local storage.
856 def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
859 (PPCaddisGotTprelHA i64:$reg,
860 tglobaltlsaddr:$disp))]>,
862 def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg),
865 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>,
867 def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g),
868 (ADD8TLS $in, tglobaltlsaddr:$g)>;
869 def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
872 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>,
874 def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
877 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>,
879 def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
882 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>,
884 def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
887 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>,
889 def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
892 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>,
894 def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym),
897 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>,
899 def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
902 (PPCaddisDtprelHA i64:$reg,
903 tglobaltlsaddr:$disp))]>,
905 def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp),
908 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>,
911 let PPC970_Unit = 2 in {
912 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
913 // Truncating stores.
914 def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src),
915 "stb $rS, $src", IIC_LdStStore,
916 [(truncstorei8 i64:$rS, iaddr:$src)]>;
917 def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src),
918 "sth $rS, $src", IIC_LdStStore,
919 [(truncstorei16 i64:$rS, iaddr:$src)]>;
920 def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src),
921 "stw $rS, $src", IIC_LdStStore,
922 [(truncstorei32 i64:$rS, iaddr:$src)]>;
923 def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst),
924 "stbx $rS, $dst", IIC_LdStStore,
925 [(truncstorei8 i64:$rS, xaddr:$dst)]>,
926 PPC970_DGroup_Cracked;
927 def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst),
928 "sthx $rS, $dst", IIC_LdStStore,
929 [(truncstorei16 i64:$rS, xaddr:$dst)]>,
930 PPC970_DGroup_Cracked;
931 def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst),
932 "stwx $rS, $dst", IIC_LdStStore,
933 [(truncstorei32 i64:$rS, xaddr:$dst)]>,
934 PPC970_DGroup_Cracked;
935 } // Interpretation64Bit
937 // Normal 8-byte stores.
938 def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst),
939 "std $rS, $dst", IIC_LdStSTD,
940 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64;
941 def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst),
942 "stdx $rS, $dst", IIC_LdStSTD,
943 [(store i64:$rS, xaddr:$dst)]>, isPPC64,
944 PPC970_DGroup_Cracked;
945 def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst),
946 "stdbrx $rS, $dst", IIC_LdStStore,
947 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64,
948 PPC970_DGroup_Cracked;
951 // Stores with Update (pre-inc).
952 let PPC970_Unit = 2, mayStore = 1 in {
953 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
954 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
955 "stbu $rS, $dst", IIC_LdStStoreUpd, []>,
956 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
957 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
958 "sthu $rS, $dst", IIC_LdStStoreUpd, []>,
959 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
960 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst),
961 "stwu $rS, $dst", IIC_LdStStoreUpd, []>,
962 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
964 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
965 "stbux $rS, $dst", IIC_LdStStoreUpd, []>,
966 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
967 PPC970_DGroup_Cracked;
968 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
969 "sthux $rS, $dst", IIC_LdStStoreUpd, []>,
970 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
971 PPC970_DGroup_Cracked;
972 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
973 "stwux $rS, $dst", IIC_LdStStoreUpd, []>,
974 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
975 PPC970_DGroup_Cracked;
976 } // Interpretation64Bit
978 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst),
979 "stdu $rS, $dst", IIC_LdStSTDU, []>,
980 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
983 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst),
984 "stdux $rS, $dst", IIC_LdStSTDUX, []>,
985 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">,
986 PPC970_DGroup_Cracked, isPPC64;
989 // Patterns to match the pre-inc stores. We can't put the patterns on
990 // the instruction definitions directly as ISel wants the address base
991 // and offset to be separate operands, not a single complex operand.
992 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
993 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>;
994 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
995 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>;
996 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
997 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>;
998 def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff),
999 (STDU $rS, iaddroff:$ptroff, $ptrreg)>;
1001 def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1002 (STBUX8 $rS, $ptrreg, $ptroff)>;
1003 def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1004 (STHUX8 $rS, $ptrreg, $ptroff)>;
1005 def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1006 (STWUX8 $rS, $ptrreg, $ptroff)>;
1007 def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
1008 (STDUX $rS, $ptrreg, $ptroff)>;
1011 //===----------------------------------------------------------------------===//
1012 // Floating point instructions.
1016 let PPC970_Unit = 3, neverHasSideEffects = 1,
1017 Uses = [RM] in { // FPU Operations.
1018 defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB),
1019 "fcfid", "$frD, $frB", IIC_FPGeneral,
1020 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64;
1021 defm FCTID : XForm_26r<63, 814, (outs f8rc:$frD), (ins f8rc:$frB),
1022 "fctid", "$frD, $frB", IIC_FPGeneral,
1024 defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB),
1025 "fctidz", "$frD, $frB", IIC_FPGeneral,
1026 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64;
1028 defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB),
1029 "fcfidu", "$frD, $frB", IIC_FPGeneral,
1030 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64;
1031 defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB),
1032 "fcfids", "$frD, $frB", IIC_FPGeneral,
1033 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64;
1034 defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB),
1035 "fcfidus", "$frD, $frB", IIC_FPGeneral,
1036 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64;
1037 defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB),
1038 "fctiduz", "$frD, $frB", IIC_FPGeneral,
1039 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64;
1040 defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB),
1041 "fctiwuz", "$frD, $frB", IIC_FPGeneral,
1042 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64;
1046 //===----------------------------------------------------------------------===//
1047 // Instruction Patterns
1050 // Extensions and truncates to/from 32-bit regs.
1051 def : Pat<(i64 (zext i32:$in)),
1052 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32),
1054 def : Pat<(i64 (anyext i32:$in)),
1055 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>;
1056 def : Pat<(i32 (trunc i64:$in)),
1057 (EXTRACT_SUBREG $in, sub_32)>;
1059 // Implement the 'not' operation with the NOR instruction.
1060 // (we could use the default xori pattern, but nor has lower latency on some
1061 // cores (such as the A2)).
1062 def i64not : OutPatFrag<(ops node:$in),
1064 def : Pat<(not i64:$in),
1067 // Extending loads with i64 targets.
1068 def : Pat<(zextloadi1 iaddr:$src),
1070 def : Pat<(zextloadi1 xaddr:$src),
1071 (LBZX8 xaddr:$src)>;
1072 def : Pat<(extloadi1 iaddr:$src),
1074 def : Pat<(extloadi1 xaddr:$src),
1075 (LBZX8 xaddr:$src)>;
1076 def : Pat<(extloadi8 iaddr:$src),
1078 def : Pat<(extloadi8 xaddr:$src),
1079 (LBZX8 xaddr:$src)>;
1080 def : Pat<(extloadi16 iaddr:$src),
1082 def : Pat<(extloadi16 xaddr:$src),
1083 (LHZX8 xaddr:$src)>;
1084 def : Pat<(extloadi32 iaddr:$src),
1086 def : Pat<(extloadi32 xaddr:$src),
1087 (LWZX8 xaddr:$src)>;
1089 // Standard shifts. These are represented separately from the real shifts above
1090 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
1092 def : Pat<(sra i64:$rS, i32:$rB),
1094 def : Pat<(srl i64:$rS, i32:$rB),
1096 def : Pat<(shl i64:$rS, i32:$rB),
1100 def : Pat<(shl i64:$in, (i32 imm:$imm)),
1101 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>;
1102 def : Pat<(srl i64:$in, (i32 imm:$imm)),
1103 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>;
1106 def : Pat<(rotl i64:$in, i32:$sh),
1107 (RLDCL $in, $sh, 0)>;
1108 def : Pat<(rotl i64:$in, (i32 imm:$imm)),
1109 (RLDICL $in, imm:$imm, 0)>;
1111 // Hi and Lo for Darwin Global Addresses.
1112 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
1113 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
1114 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
1115 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
1116 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
1117 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
1118 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
1119 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
1120 def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in),
1121 (ADDIS8 $in, tglobaltlsaddr:$g)>;
1122 def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in),
1123 (ADDI8 $in, tglobaltlsaddr:$g)>;
1124 def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)),
1125 (ADDIS8 $in, tglobaladdr:$g)>;
1126 def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)),
1127 (ADDIS8 $in, tconstpool:$g)>;
1128 def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)),
1129 (ADDIS8 $in, tjumptable:$g)>;
1130 def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)),
1131 (ADDIS8 $in, tblockaddress:$g)>;
1133 // Patterns to match r+r indexed loads and stores for
1134 // addresses without at least 4-byte alignment.
1135 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
1136 (LWAX xoaddr:$src)>;
1137 def : Pat<(i64 (unaligned4load xoaddr:$src)),
1139 def : Pat<(unaligned4store i64:$rS, xoaddr:$dst),
1140 (STDX $rS, xoaddr:$dst)>;
1142 // 64-bits atomic loads and stores
1143 def : Pat<(atomic_load_64 ixaddr:$src), (LD memrix:$src)>;
1144 def : Pat<(atomic_load_64 xaddr:$src), (LDX memrr:$src)>;
1146 def : Pat<(atomic_store_64 ixaddr:$ptr, i64:$val), (STD g8rc:$val, memrix:$ptr)>;
1147 def : Pat<(atomic_store_64 xaddr:$ptr, i64:$val), (STDX g8rc:$val, memrr:$ptr)>;