1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
61 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
65 let isCall = 1, PPC970_Unit = 7,
66 // All calls clobber the PPC64 non-callee saved registers.
67 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
68 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
69 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
71 CR0,CR1,CR5,CR6,CR7] in {
72 // Convenient aliases for call instructions
73 def BL8_Macho : IForm<18, 0, 1,
74 (outs), (ins calltarget:$func, variable_ops),
75 "bl $func", BrB, []>; // See Pat patterns below.
76 def BLA8_Macho : IForm<18, 1, 1,
77 (outs), (ins aaddr:$func, variable_ops),
78 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
79 def BCTRL8_Macho : XLForm_2_ext<19, 528, 20, 0, 1,
80 (outs), (ins variable_ops),
82 [(PPCbctrl_Macho)]>, Requires<[In64BitMode]>;
85 // ELF 64 ABI Calls = Macho ABI Calls
86 // Used to define BL8_ELF and BLA8_ELF
87 let isCall = 1, PPC970_Unit = 7,
88 // All calls clobber the PPC64 non-callee saved registers.
89 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
90 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
91 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
93 CR0,CR1,CR5,CR6,CR7] in {
94 // Convenient aliases for call instructions
95 def BL8_ELF : IForm<18, 0, 1,
96 (outs), (ins calltarget:$func, variable_ops),
97 "bl $func", BrB, []>; // See Pat patterns below.
98 def BLA8_ELF : IForm<18, 1, 1,
99 (outs), (ins aaddr:$func, variable_ops),
100 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
101 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
102 (outs), (ins variable_ops),
104 [(PPCbctrl_ELF)]>, Requires<[In64BitMode]>;
109 def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
110 (BL8_Macho tglobaladdr:$dst)>;
111 def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
112 (BL8_Macho texternalsym:$dst)>;
114 def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
115 (BL8_ELF tglobaladdr:$dst)>;
116 def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
117 (BL8_ELF texternalsym:$dst)>;
119 //===----------------------------------------------------------------------===//
120 // 64-bit SPR manipulation instrs.
122 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
123 "mfctr $rT", SprMFSPR>,
124 PPC970_DGroup_First, PPC970_Unit_FXU;
125 let Pattern = [(PPCmtctr G8RC:$rS)] in {
126 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
127 "mtctr $rS", SprMTSPR>,
128 PPC970_DGroup_First, PPC970_Unit_FXU;
131 let Defs = [X1], Uses = [X1] in
132 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),
133 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
135 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
137 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
138 "mtlr $rS", SprMTSPR>,
139 PPC970_DGroup_First, PPC970_Unit_FXU;
140 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
141 "mflr $rT", SprMFSPR>,
142 PPC970_DGroup_First, PPC970_Unit_FXU;
145 //===----------------------------------------------------------------------===//
146 // Fixed point instructions.
149 let PPC970_Unit = 1 in { // FXU Operations.
151 // Copies, extends, truncates.
152 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
153 "or $rA, $rS, $rB", IntGeneral,
155 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
156 "or $rA, $rS, $rB", IntGeneral,
159 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
160 "li $rD, $imm", IntGeneral,
161 [(set G8RC:$rD, immSExt16:$imm)]>;
162 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
163 "lis $rD, $imm", IntGeneral,
164 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
167 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
168 "nand $rA, $rS, $rB", IntGeneral,
169 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
170 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
171 "and $rA, $rS, $rB", IntGeneral,
172 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
173 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
174 "andc $rA, $rS, $rB", IntGeneral,
175 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
176 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
177 "or $rA, $rS, $rB", IntGeneral,
178 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
179 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
180 "nor $rA, $rS, $rB", IntGeneral,
181 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
182 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
183 "orc $rA, $rS, $rB", IntGeneral,
184 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
185 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
186 "eqv $rA, $rS, $rB", IntGeneral,
187 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
188 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
189 "xor $rA, $rS, $rB", IntGeneral,
190 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
192 // Logical ops with immediate.
193 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
194 "andi. $dst, $src1, $src2", IntGeneral,
195 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
197 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
198 "andis. $dst, $src1, $src2", IntGeneral,
199 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
201 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
202 "ori $dst, $src1, $src2", IntGeneral,
203 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
204 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
205 "oris $dst, $src1, $src2", IntGeneral,
206 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
207 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
208 "xori $dst, $src1, $src2", IntGeneral,
209 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
210 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
211 "xoris $dst, $src1, $src2", IntGeneral,
212 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
214 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
215 "add $rT, $rA, $rB", IntGeneral,
216 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
218 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
219 "addc $rT, $rA, $rB", IntGeneral,
220 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
221 PPC970_DGroup_Cracked;
222 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
223 "adde $rT, $rA, $rB", IntGeneral,
224 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
226 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
227 "addi $rD, $rA, $imm", IntGeneral,
228 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
229 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
230 "addis $rD, $rA, $imm", IntGeneral,
231 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
233 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
234 "subfic $rD, $rA, $imm", IntGeneral,
235 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
236 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
237 "subf $rT, $rA, $rB", IntGeneral,
238 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
240 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
241 "subfc $rT, $rA, $rB", IntGeneral,
242 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
243 PPC970_DGroup_Cracked;
245 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
246 "subfe $rT, $rA, $rB", IntGeneral,
247 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
248 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
249 "addme $rT, $rA", IntGeneral,
250 [(set G8RC:$rT, (adde G8RC:$rA, immAllOnes))]>;
251 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
252 "addze $rT, $rA", IntGeneral,
253 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
254 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
255 "neg $rT, $rA", IntGeneral,
256 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
257 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
258 "subfme $rT, $rA", IntGeneral,
259 [(set G8RC:$rT, (sube immAllOnes, G8RC:$rA))]>;
260 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
261 "subfze $rT, $rA", IntGeneral,
262 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
266 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
267 "mulhd $rT, $rA, $rB", IntMulHW,
268 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
269 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
270 "mulhdu $rT, $rA, $rB", IntMulHWU,
271 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
273 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
274 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
275 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
276 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
277 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
278 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
279 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
280 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
282 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
283 "sld $rA, $rS, $rB", IntRotateD,
284 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
285 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
286 "srd $rA, $rS, $rB", IntRotateD,
287 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
288 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
289 "srad $rA, $rS, $rB", IntRotateD,
290 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
292 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
293 "extsb $rA, $rS", IntGeneral,
294 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
295 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
296 "extsh $rA, $rS", IntGeneral,
297 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
299 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
300 "extsw $rA, $rS", IntGeneral,
301 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
302 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
303 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
304 "extsw $rA, $rS", IntGeneral,
305 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
306 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
307 "extsw $rA, $rS", IntGeneral,
308 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
310 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
311 "sradi $rA, $rS, $SH", IntRotateD,
312 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
313 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
314 "cntlzd $rA, $rS", IntGeneral,
315 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
317 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
318 "divd $rT, $rA, $rB", IntDivD,
319 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
320 PPC970_DGroup_First, PPC970_DGroup_Cracked;
321 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
322 "divdu $rT, $rA, $rB", IntDivD,
323 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
324 PPC970_DGroup_First, PPC970_DGroup_Cracked;
325 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
326 "mulld $rT, $rA, $rB", IntMulHD,
327 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
330 let isCommutable = 1 in {
331 def RLDIMI : MDForm_1<30, 3,
332 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
333 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
334 []>, isPPC64, RegConstraint<"$rSi = $rA">,
338 // Rotate instructions.
339 def RLDCL : MDForm_1<30, 0,
340 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
341 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
343 def RLDICL : MDForm_1<30, 0,
344 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
345 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
347 def RLDICR : MDForm_1<30, 1,
348 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
349 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
351 } // End FXU Operations.
354 //===----------------------------------------------------------------------===//
355 // Load/Store instructions.
359 // Sign extending loads.
360 let isSimpleLoad = 1, PPC970_Unit = 2 in {
361 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
362 "lha $rD, $src", LdStLHA,
363 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
364 PPC970_DGroup_Cracked;
365 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
366 "lwa $rD, $src", LdStLWA,
367 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
368 PPC970_DGroup_Cracked;
369 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
370 "lhax $rD, $src", LdStLHA,
371 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
372 PPC970_DGroup_Cracked;
373 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
374 "lwax $rD, $src", LdStLHA,
375 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
376 PPC970_DGroup_Cracked;
379 def LHAU8 : DForm_1<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
381 "lhau $rD, $disp($rA)", LdStGeneral,
382 []>, RegConstraint<"$rA = $ea_result">,
383 NoEncode<"$ea_result">;
388 // Zero extending loads.
389 let isSimpleLoad = 1, PPC970_Unit = 2 in {
390 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
391 "lbz $rD, $src", LdStGeneral,
392 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
393 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
394 "lhz $rD, $src", LdStGeneral,
395 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
396 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
397 "lwz $rD, $src", LdStGeneral,
398 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
400 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
401 "lbzx $rD, $src", LdStGeneral,
402 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
403 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
404 "lhzx $rD, $src", LdStGeneral,
405 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
406 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
407 "lwzx $rD, $src", LdStGeneral,
408 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
412 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
413 "lbzu $rD, $addr", LdStGeneral,
414 []>, RegConstraint<"$addr.reg = $ea_result">,
415 NoEncode<"$ea_result">;
416 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
417 "lhzu $rD, $addr", LdStGeneral,
418 []>, RegConstraint<"$addr.reg = $ea_result">,
419 NoEncode<"$ea_result">;
420 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
421 "lwzu $rD, $addr", LdStGeneral,
422 []>, RegConstraint<"$addr.reg = $ea_result">,
423 NoEncode<"$ea_result">;
427 // Full 8-byte loads.
428 let isSimpleLoad = 1, PPC970_Unit = 2 in {
429 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
430 "ld $rD, $src", LdStLD,
431 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
432 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
433 "ldx $rD, $src", LdStLD,
434 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
436 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
437 "ldu $rD, $addr", LdStLD,
438 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
439 NoEncode<"$ea_result">;
443 let PPC970_Unit = 2 in {
444 // Truncating stores.
445 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
446 "stb $rS, $src", LdStGeneral,
447 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
448 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
449 "sth $rS, $src", LdStGeneral,
450 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
451 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
452 "stw $rS, $src", LdStGeneral,
453 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
454 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
455 "stbx $rS, $dst", LdStGeneral,
456 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
457 PPC970_DGroup_Cracked;
458 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
459 "sthx $rS, $dst", LdStGeneral,
460 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
461 PPC970_DGroup_Cracked;
462 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
463 "stwx $rS, $dst", LdStGeneral,
464 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
465 PPC970_DGroup_Cracked;
466 // Normal 8-byte stores.
467 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
468 "std $rS, $dst", LdStSTD,
469 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
470 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
471 "stdx $rS, $dst", LdStSTD,
472 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
473 PPC970_DGroup_Cracked;
476 let PPC970_Unit = 2 in {
478 def STBU8 : DForm_1<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
479 symbolLo:$ptroff, ptr_rc:$ptrreg),
480 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
481 [(set ptr_rc:$ea_res,
482 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
483 iaddroff:$ptroff))]>,
484 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
485 def STHU8 : DForm_1<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
486 symbolLo:$ptroff, ptr_rc:$ptrreg),
487 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
488 [(set ptr_rc:$ea_res,
489 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
490 iaddroff:$ptroff))]>,
491 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
492 def STWU8 : DForm_1<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
493 symbolLo:$ptroff, ptr_rc:$ptrreg),
494 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
495 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
496 iaddroff:$ptroff))]>,
497 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
500 def STDU : DSForm_1<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
501 s16immX4:$ptroff, ptr_rc:$ptrreg),
502 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
503 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
504 iaddroff:$ptroff))]>,
505 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
509 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
510 "stdux $rS, $dst", LdStSTD,
513 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
514 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
515 "std $rT, $dst", LdStSTD,
516 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
517 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
518 "stdx $rT, $dst", LdStSTD,
519 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
520 PPC970_DGroup_Cracked;
525 //===----------------------------------------------------------------------===//
526 // Floating point instructions.
530 let PPC970_Unit = 3 in { // FPU Operations.
531 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
532 "fcfid $frD, $frB", FPGeneral,
533 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
534 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
535 "fctidz $frD, $frB", FPGeneral,
536 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
540 //===----------------------------------------------------------------------===//
541 // Instruction Patterns
544 // Extensions and truncates to/from 32-bit regs.
545 def : Pat<(i64 (zext GPRC:$in)),
546 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
547 def : Pat<(i64 (anyext GPRC:$in)),
548 (OR4To8 GPRC:$in, GPRC:$in)>;
549 def : Pat<(i32 (trunc G8RC:$in)),
550 (OR8To4 G8RC:$in, G8RC:$in)>;
552 // Extending loads with i64 targets.
553 def : Pat<(zextloadi1 iaddr:$src),
555 def : Pat<(zextloadi1 xaddr:$src),
557 def : Pat<(extloadi1 iaddr:$src),
559 def : Pat<(extloadi1 xaddr:$src),
561 def : Pat<(extloadi8 iaddr:$src),
563 def : Pat<(extloadi8 xaddr:$src),
565 def : Pat<(extloadi16 iaddr:$src),
567 def : Pat<(extloadi16 xaddr:$src),
569 def : Pat<(extloadi32 iaddr:$src),
571 def : Pat<(extloadi32 xaddr:$src),
574 // Standard shifts. These are represented separately from the real shifts above
575 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
577 def : Pat<(sra G8RC:$rS, GPRC:$rB),
578 (SRAD G8RC:$rS, GPRC:$rB)>;
579 def : Pat<(srl G8RC:$rS, GPRC:$rB),
580 (SRD G8RC:$rS, GPRC:$rB)>;
581 def : Pat<(shl G8RC:$rS, GPRC:$rB),
582 (SLD G8RC:$rS, GPRC:$rB)>;
585 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
586 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
587 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
588 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
591 def : Pat<(rotl G8RC:$in, GPRC:$sh),
592 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
593 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
594 (RLDICL G8RC:$in, imm:$imm, 0)>;
596 // Hi and Lo for Darwin Global Addresses.
597 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
598 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
599 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
600 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
601 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
602 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
603 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
604 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
605 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
606 (ADDIS8 G8RC:$in, tconstpool:$g)>;
607 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
608 (ADDIS8 G8RC:$in, tjumptable:$g)>;