1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
32 def tocentry : Operand<iPTR> {
33 let MIOperandInfo = (ops i64imm:$imm);
35 def memrs : Operand<iPTR> { // memri where the immediate is a symbolLo64
36 let PrintMethod = "printMemRegImm";
37 let EncoderMethod = "getMemRIXEncoding";
38 let MIOperandInfo = (ops symbolLo64:$off, ptr_rc_nor0:$reg);
40 def tlsreg : Operand<i64> {
41 let EncoderMethod = "getTLSRegEncoding";
43 def tlsgd : Operand<i64> {}
45 //===----------------------------------------------------------------------===//
46 // 64-bit transformation functions.
49 def SHL64 : SDNodeXForm<imm, [{
50 // Transformation function: 63 - imm
51 return getI32Imm(63 - N->getZExtValue());
54 def SRL64 : SDNodeXForm<imm, [{
55 // Transformation function: 64 - imm
56 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
59 def HI32_48 : SDNodeXForm<imm, [{
60 // Transformation function: shift the immediate value down into the low bits.
61 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
64 def HI48_64 : SDNodeXForm<imm, [{
65 // Transformation function: shift the immediate value down into the low bits.
66 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
70 //===----------------------------------------------------------------------===//
75 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>,
79 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
80 // Convenient aliases for call instructions
82 def BL8_Darwin : IForm<18, 0, 1,
83 (outs), (ins calltarget:$func),
84 "bl $func", BrB, []>; // See Pat patterns below.
85 def BLA8_Darwin : IForm<18, 1, 1,
86 (outs), (ins aaddr:$func),
87 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
89 let Uses = [CTR8, RM] in {
90 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
93 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
97 // ELF 64 ABI Calls = Darwin ABI Calls
98 // Used to define BL8_ELF and BLA8_ELF
99 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
100 // Convenient aliases for call instructions
102 def BL8_ELF : IForm<18, 0, 1,
103 (outs), (ins calltarget:$func),
104 "bl $func", BrB, []>; // See Pat patterns below.
106 let isCodeGenOnly = 1 in
107 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24,
108 (outs), (ins calltarget:$func),
109 "bl $func\n\tnop", BrB, []>;
111 let isCodeGenOnly = 1 in
112 def BL8_NOP_ELF_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24,
113 (outs), (ins calltarget:$func, tlsgd:$sym),
114 "bl $func($sym)\n\tnop", BrB, []>;
116 let isCodeGenOnly = 1 in
117 def BL8_NOP_ELF_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24,
118 (outs), (ins calltarget:$func, tlsgd:$sym),
119 "bl $func($sym)\n\tnop", BrB, []>;
121 def BLA8_ELF : IForm<18, 1, 1,
122 (outs), (ins aaddr:$func),
123 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
125 let isCodeGenOnly = 1 in
126 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24,
127 (outs), (ins aaddr:$func),
128 "bla $func\n\tnop", BrB,
129 [(PPCcall_nop_SVR4 (i64 imm:$func))]>;
131 let Uses = [X11, CTR8, RM] in {
132 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
135 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
141 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
142 (BL8_Darwin tglobaladdr:$dst)>;
143 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
144 (BL8_Darwin texternalsym:$dst)>;
146 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
147 (BL8_ELF tglobaladdr:$dst)>;
148 def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)),
149 (BL8_NOP_ELF tglobaladdr:$dst)>;
151 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
152 (BL8_ELF texternalsym:$dst)>;
153 def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)),
154 (BL8_NOP_ELF texternalsym:$dst)>;
160 let usesCustomInserter = 1 in {
161 let Defs = [CR0] in {
162 def ATOMIC_LOAD_ADD_I64 : Pseudo<
163 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_ADD_I64",
164 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
165 def ATOMIC_LOAD_SUB_I64 : Pseudo<
166 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_SUB_I64",
167 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
168 def ATOMIC_LOAD_OR_I64 : Pseudo<
169 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_OR_I64",
170 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
171 def ATOMIC_LOAD_XOR_I64 : Pseudo<
172 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_XOR_I64",
173 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
174 def ATOMIC_LOAD_AND_I64 : Pseudo<
175 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_AND_i64",
176 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
177 def ATOMIC_LOAD_NAND_I64 : Pseudo<
178 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "#ATOMIC_LOAD_NAND_I64",
179 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
181 def ATOMIC_CMP_SWAP_I64 : Pseudo<
182 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "#ATOMIC_CMP_SWAP_I64",
184 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
186 def ATOMIC_SWAP_I64 : Pseudo<
187 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "#ATOMIC_SWAP_I64",
188 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
192 // Instructions to support atomic operations
193 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
194 "ldarx $rD, $ptr", LdStLDARX,
195 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
198 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
199 "stdcx. $rS, $dst", LdStSTDCX,
200 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
203 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
204 def TCRETURNdi8 :Pseudo< (outs),
205 (ins calltarget:$dst, i32imm:$offset),
206 "#TC_RETURNd8 $dst $offset",
209 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
210 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset),
211 "#TC_RETURNa8 $func $offset",
212 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
214 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
215 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset),
216 "#TC_RETURNr8 $dst $offset",
220 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
221 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in {
222 let isReturn = 1 in {
223 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
224 Requires<[In64BitMode]>;
227 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
228 Requires<[In64BitMode]>;
232 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
233 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
234 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
239 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
240 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
241 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
245 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
246 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
248 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
249 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
251 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
252 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
254 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
255 let Defs = [CTR8], Uses = [CTR8] in {
256 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
258 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
263 // 64-but CR instructions
264 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
265 "mtcrf $FXM, $rS", BrMCRX>,
266 PPC970_MicroCode, PPC970_Unit_CRU;
268 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
269 "#MFCR8pseud", SprMFCR>,
270 PPC970_MicroCode, PPC970_Unit_CRU;
272 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
273 "mfcr $rT", SprMFCR>,
274 PPC970_MicroCode, PPC970_Unit_CRU;
276 //===----------------------------------------------------------------------===//
277 // 64-bit SPR manipulation instrs.
279 let Uses = [CTR8] in {
280 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
281 "mfctr $rT", SprMFSPR>,
282 PPC970_DGroup_First, PPC970_Unit_FXU;
284 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
285 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
286 "mtctr $rS", SprMTSPR>,
287 PPC970_DGroup_First, PPC970_Unit_FXU;
290 let Pattern = [(set G8RC:$rT, readcyclecounter)] in
291 def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs G8RC:$rT), (ins),
292 "mfspr $rT, 268", SprMFTB>,
293 PPC970_DGroup_First, PPC970_Unit_FXU;
294 // Note that encoding mftb using mfspr is now the preferred form,
295 // and has been since at least ISA v2.03. The mftb instruction has
296 // now been phased out. Using mfspr, however, is known not to work on
299 let Defs = [X1], Uses = [X1] in
300 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"#DYNALLOC8",
302 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
304 let Defs = [LR8] in {
305 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
306 "mtlr $rS", SprMTSPR>,
307 PPC970_DGroup_First, PPC970_Unit_FXU;
309 let Uses = [LR8] in {
310 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
311 "mflr $rT", SprMFSPR>,
312 PPC970_DGroup_First, PPC970_Unit_FXU;
315 //===----------------------------------------------------------------------===//
316 // Fixed point instructions.
319 let PPC970_Unit = 1 in { // FXU Operations.
321 let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
322 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
323 "li $rD, $imm", IntSimple,
324 [(set G8RC:$rD, immSExt16:$imm)]>;
325 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
326 "lis $rD, $imm", IntSimple,
327 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
331 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
332 "nand $rA, $rS, $rB", IntSimple,
333 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
334 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
335 "and $rA, $rS, $rB", IntSimple,
336 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
337 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
338 "andc $rA, $rS, $rB", IntSimple,
339 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
340 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
341 "or $rA, $rS, $rB", IntSimple,
342 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
343 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
344 "nor $rA, $rS, $rB", IntSimple,
345 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
346 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
347 "orc $rA, $rS, $rB", IntSimple,
348 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
349 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
350 "eqv $rA, $rS, $rB", IntSimple,
351 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
352 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
353 "xor $rA, $rS, $rB", IntSimple,
354 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
356 // Moves between 32-bit and 64-bit registers (used for copy resolution
357 // after register allocation).
358 let isCodeGenOnly = 1 in {
359 def OR8_32 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
360 "or $rA, $rS, $rB", IntSimple, []>;
361 def OR_64 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
362 "or $rA, $rS, $rB", IntSimple, []>;
365 // Logical ops with immediate.
366 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
367 "andi. $dst, $src1, $src2", IntGeneral,
368 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
370 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
371 "andis. $dst, $src1, $src2", IntGeneral,
372 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
374 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
375 "ori $dst, $src1, $src2", IntSimple,
376 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
377 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
378 "oris $dst, $src1, $src2", IntSimple,
379 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
380 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
381 "xori $dst, $src1, $src2", IntSimple,
382 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
383 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
384 "xoris $dst, $src1, $src2", IntSimple,
385 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
387 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
388 "add $rT, $rA, $rB", IntSimple,
389 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
390 // ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the
391 // initial-exec thread-local storage model.
392 def ADD8TLS : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, tlsreg:$rB),
393 "add $rT, $rA, $rB@tls", IntSimple,
394 [(set G8RC:$rT, (add G8RC:$rA, tglobaltlsaddr:$rB))]>;
396 let Defs = [CARRY] in {
397 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
398 "addc $rT, $rA, $rB", IntGeneral,
399 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
400 PPC970_DGroup_Cracked;
401 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
402 "addic $rD, $rA, $imm", IntGeneral,
403 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
405 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, s16imm64:$imm),
406 "addi $rD, $rA, $imm", IntSimple,
407 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>;
408 def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolLo64:$imm),
409 "addi $rD, $rA, $imm", IntSimple,
410 [(set G8RC:$rD, (add G8RC_NOX0:$rA, immSExt16:$imm))]>;
411 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC_NOX0:$rA, symbolHi64:$imm),
412 "addis $rD, $rA, $imm", IntSimple,
413 [(set G8RC:$rD, (add G8RC_NOX0:$rA,
414 imm16ShiftedSExt:$imm))]>;
416 let Defs = [CARRY] in {
417 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
418 "subfic $rD, $rA, $imm", IntGeneral,
419 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
420 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
421 "subfc $rT, $rA, $rB", IntGeneral,
422 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
423 PPC970_DGroup_Cracked;
425 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
426 "subf $rT, $rA, $rB", IntGeneral,
427 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
428 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
429 "neg $rT, $rA", IntSimple,
430 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
431 let Uses = [CARRY], Defs = [CARRY] in {
432 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
433 "adde $rT, $rA, $rB", IntGeneral,
434 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
435 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
436 "addme $rT, $rA", IntGeneral,
437 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
438 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
439 "addze $rT, $rA", IntGeneral,
440 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
441 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
442 "subfe $rT, $rA, $rB", IntGeneral,
443 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
444 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
445 "subfme $rT, $rA", IntGeneral,
446 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
447 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
448 "subfze $rT, $rA", IntGeneral,
449 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
453 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
454 "mulhd $rT, $rA, $rB", IntMulHW,
455 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
456 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
457 "mulhdu $rT, $rA, $rB", IntMulHWU,
458 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
460 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
461 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
462 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
463 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
464 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
465 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
466 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
467 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
469 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
470 "sld $rA, $rS, $rB", IntRotateD,
471 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
472 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
473 "srd $rA, $rS, $rB", IntRotateD,
474 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
475 let Defs = [CARRY] in {
476 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
477 "srad $rA, $rS, $rB", IntRotateD,
478 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
481 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
482 "extsb $rA, $rS", IntSimple,
483 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
484 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
485 "extsh $rA, $rS", IntSimple,
486 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
488 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
489 "extsw $rA, $rS", IntSimple,
490 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
491 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
492 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
493 "extsw $rA, $rS", IntSimple,
494 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
495 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
496 "extsw $rA, $rS", IntSimple,
497 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
499 let Defs = [CARRY] in {
500 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
501 "sradi $rA, $rS, $SH", IntRotateDI,
502 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
504 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
505 "cntlzd $rA, $rS", IntGeneral,
506 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
508 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
509 "divd $rT, $rA, $rB", IntDivD,
510 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
511 PPC970_DGroup_First, PPC970_DGroup_Cracked;
512 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
513 "divdu $rT, $rA, $rB", IntDivD,
514 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
515 PPC970_DGroup_First, PPC970_DGroup_Cracked;
516 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
517 "mulld $rT, $rA, $rB", IntMulHD,
518 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
521 let isCommutable = 1 in {
522 def RLDIMI : MDForm_1<30, 3,
523 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
524 "rldimi $rA, $rS, $SH, $MB", IntRotateDI,
525 []>, isPPC64, RegConstraint<"$rSi = $rA">,
529 // Rotate instructions.
530 def RLDCL : MDForm_1<30, 0,
531 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MBE),
532 "rldcl $rA, $rS, $rB, $MBE", IntRotateD,
534 def RLDICL : MDForm_1<30, 0,
535 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
536 "rldicl $rA, $rS, $SH, $MBE", IntRotateDI,
538 def RLDICR : MDForm_1<30, 1,
539 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MBE),
540 "rldicr $rA, $rS, $SH, $MBE", IntRotateDI,
543 def RLWINM8 : MForm_2<21,
544 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
545 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
548 def ISEL8 : AForm_4<31, 15,
549 (outs G8RC:$rT), (ins G8RC_NOX0:$rA, G8RC:$rB, pred:$cond),
550 "isel $rT, $rA, $rB, $cond", IntGeneral,
552 } // End FXU Operations.
555 //===----------------------------------------------------------------------===//
556 // Load/Store instructions.
560 // Sign extending loads.
561 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
562 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
563 "lha $rD, $src", LdStLHA,
564 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
565 PPC970_DGroup_Cracked;
566 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
567 "lwa $rD, $src", LdStLWA,
569 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64,
570 PPC970_DGroup_Cracked;
571 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
572 "lhax $rD, $src", LdStLHA,
573 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
574 PPC970_DGroup_Cracked;
575 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
576 "lwax $rD, $src", LdStLHA,
577 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
578 PPC970_DGroup_Cracked;
582 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins symbolLo:$disp,
584 "lhau $rD, $disp($rA)", LdStLHAU,
585 []>, RegConstraint<"$rA = $ea_result">,
586 NoEncode<"$ea_result">;
589 def LHAUX8 : XForm_1<31, 375, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
591 "lhaux $rD, $addr", LdStLHAU,
592 []>, RegConstraint<"$addr.offreg = $ea_result">,
593 NoEncode<"$ea_result">;
594 def LWAUX : XForm_1<31, 373, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
596 "lwaux $rD, $addr", LdStLHAU,
597 []>, RegConstraint<"$addr.offreg = $ea_result">,
598 NoEncode<"$ea_result">, isPPC64;
601 // Zero extending loads.
602 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
603 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
604 "lbz $rD, $src", LdStLoad,
605 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
606 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
607 "lhz $rD, $src", LdStLoad,
608 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
609 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
610 "lwz $rD, $src", LdStLoad,
611 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
613 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
614 "lbzx $rD, $src", LdStLoad,
615 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
616 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
617 "lhzx $rD, $src", LdStLoad,
618 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
619 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
620 "lwzx $rD, $src", LdStLoad,
621 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
626 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
627 "lbzu $rD, $addr", LdStLoadUpd,
628 []>, RegConstraint<"$addr.reg = $ea_result">,
629 NoEncode<"$ea_result">;
630 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
631 "lhzu $rD, $addr", LdStLoadUpd,
632 []>, RegConstraint<"$addr.reg = $ea_result">,
633 NoEncode<"$ea_result">;
634 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr),
635 "lwzu $rD, $addr", LdStLoadUpd,
636 []>, RegConstraint<"$addr.reg = $ea_result">,
637 NoEncode<"$ea_result">;
639 def LBZUX8 : XForm_1<31, 119, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
641 "lbzux $rD, $addr", LdStLoadUpd,
642 []>, RegConstraint<"$addr.offreg = $ea_result">,
643 NoEncode<"$ea_result">;
644 def LHZUX8 : XForm_1<31, 311, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
646 "lhzux $rD, $addr", LdStLoadUpd,
647 []>, RegConstraint<"$addr.offreg = $ea_result">,
648 NoEncode<"$ea_result">;
649 def LWZUX8 : XForm_1<31, 55, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
651 "lwzux $rD, $addr", LdStLoadUpd,
652 []>, RegConstraint<"$addr.offreg = $ea_result">,
653 NoEncode<"$ea_result">;
658 // Full 8-byte loads.
659 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
660 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
661 "ld $rD, $src", LdStLD,
662 [(set G8RC:$rD, (aligned4load ixaddr:$src))]>, isPPC64;
663 def LDrs : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrs:$src),
664 "ld $rD, $src", LdStLD,
666 // The following three definitions are selected for small code model only.
667 // Otherwise, we need to create two instructions to form a 32-bit offset,
668 // so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select().
669 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
672 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
673 def LDtocJTI: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
676 (PPCtoc_entry tjumptable:$disp, G8RC:$reg))]>, isPPC64;
677 def LDtocCPT: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
680 (PPCtoc_entry tconstpool:$disp, G8RC:$reg))]>, isPPC64;
682 let hasSideEffects = 1 in {
683 let RST = 2, DS = 2 in
684 def LDinto_toc: DSForm_1a<58, 0, (outs), (ins G8RC:$reg),
685 "ld 2, 8($reg)", LdStLD,
686 [(PPCload_toc G8RC:$reg)]>, isPPC64;
688 let RST = 2, DS = 10, RA = 1 in
689 def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins),
690 "ld 2, 40(1)", LdStLD,
691 [(PPCtoc_restore)]>, isPPC64;
693 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
694 "ldx $rD, $src", LdStLD,
695 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
698 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr),
699 "ldu $rD, $addr", LdStLDU,
700 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
701 NoEncode<"$ea_result">;
703 def LDUX : XForm_1<31, 53, (outs G8RC:$rD, ptr_rc_nor0:$ea_result),
705 "ldux $rD, $addr", LdStLDU,
706 []>, RegConstraint<"$addr.offreg = $ea_result">,
707 NoEncode<"$ea_result">, isPPC64;
710 def : Pat<(PPCload ixaddr:$src),
712 def : Pat<(PPCload xaddr:$src),
715 // Support for medium and large code model.
716 def ADDIStocHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
719 (PPCaddisTocHA G8RC:$reg, tglobaladdr:$disp))]>,
721 def LDtocL: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
724 (PPCldTocL tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
725 def ADDItocL: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tocentry:$disp),
728 (PPCaddiTocL G8RC:$reg, tglobaladdr:$disp))]>, isPPC64;
730 // Support for thread-local storage.
731 def ADDISgotTprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
734 (PPCaddisGotTprelHA G8RC:$reg,
735 tglobaltlsaddr:$disp))]>,
737 def LDgotTprelL: Pseudo<(outs G8RC:$rD), (ins symbolLo64:$disp, G8RC:$reg),
740 (PPCldGotTprelL tglobaltlsaddr:$disp, G8RC:$reg))]>,
742 def : Pat<(PPCaddTls G8RC:$in, tglobaltlsaddr:$g),
743 (ADD8TLS G8RC:$in, tglobaltlsaddr:$g)>;
744 def ADDIStlsgdHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
747 (PPCaddisTlsgdHA G8RC:$reg, tglobaltlsaddr:$disp))]>,
749 def ADDItlsgdL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
752 (PPCaddiTlsgdL G8RC:$reg, tglobaltlsaddr:$disp))]>,
754 def GETtlsADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
757 (PPCgetTlsAddr G8RC:$reg, tglobaltlsaddr:$sym))]>,
759 def ADDIStlsldHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
762 (PPCaddisTlsldHA G8RC:$reg, tglobaltlsaddr:$disp))]>,
764 def ADDItlsldL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
767 (PPCaddiTlsldL G8RC:$reg, tglobaltlsaddr:$disp))]>,
769 def GETtlsldADDR : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, tlsgd:$sym),
772 (PPCgetTlsldAddr G8RC:$reg, tglobaltlsaddr:$sym))]>,
774 def ADDISdtprelHA: Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolHi64:$disp),
777 (PPCaddisDtprelHA G8RC:$reg,
778 tglobaltlsaddr:$disp))]>,
780 def ADDIdtprelL : Pseudo<(outs G8RC:$rD), (ins G8RC:$reg, symbolLo64:$disp),
783 (PPCaddiDtprelL G8RC:$reg, tglobaltlsaddr:$disp))]>,
786 let PPC970_Unit = 2 in {
787 // Truncating stores.
788 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
789 "stb $rS, $src", LdStStore,
790 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
791 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
792 "sth $rS, $src", LdStStore,
793 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
794 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
795 "stw $rS, $src", LdStStore,
796 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
797 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
798 "stbx $rS, $dst", LdStStore,
799 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
800 PPC970_DGroup_Cracked;
801 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
802 "sthx $rS, $dst", LdStStore,
803 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
804 PPC970_DGroup_Cracked;
805 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
806 "stwx $rS, $dst", LdStStore,
807 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
808 PPC970_DGroup_Cracked;
809 // Normal 8-byte stores.
810 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
811 "std $rS, $dst", LdStSTD,
812 [(aligned4store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
813 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
814 "stdx $rS, $dst", LdStSTD,
815 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
816 PPC970_DGroup_Cracked;
817 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
818 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
819 "std $rT, $dst", LdStSTD,
820 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
821 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
822 "stdx $rT, $dst", LdStSTD,
823 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
824 PPC970_DGroup_Cracked;
827 // Stores with Update (pre-inc).
828 let PPC970_Unit = 2, mayStore = 1 in {
829 def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
830 "stbu $rS, $dst", LdStStoreUpd, []>,
831 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
832 def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
833 "sthu $rS, $dst", LdStStoreUpd, []>,
834 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
835 def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memri:$dst),
836 "stwu $rS, $dst", LdStStoreUpd, []>,
837 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
838 def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrix:$dst),
839 "stdu $rS, $dst", LdStSTDU, []>,
840 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">,
843 def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
844 "stbux $rS, $dst", LdStStoreUpd, []>,
845 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
846 PPC970_DGroup_Cracked;
847 def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
848 "sthux $rS, $dst", LdStStoreUpd, []>,
849 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
850 PPC970_DGroup_Cracked;
851 def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
852 "stwux $rS, $dst", LdStStoreUpd, []>,
853 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
854 PPC970_DGroup_Cracked;
855 def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins G8RC:$rS, memrr:$dst),
856 "stdux $rS, $dst", LdStSTDU, []>,
857 RegConstraint<"$dst.offreg = $ea_res">, NoEncode<"$ea_res">,
858 PPC970_DGroup_Cracked, isPPC64;
861 // Patterns to match the pre-inc stores. We can't put the patterns on
862 // the instruction definitions directly as ISel wants the address base
863 // and offset to be separate operands, not a single complex operand.
864 def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
865 (STBU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
866 def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
867 (STHU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
868 def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
869 (STWU8 G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
870 def : Pat<(aligned4pre_store G8RC:$rS, ptr_rc_nor0:$ptrreg, iaddroff:$ptroff),
871 (STDU G8RC:$rS, iaddroff:$ptroff, ptr_rc_nor0:$ptrreg)>;
873 def : Pat<(pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
874 (STBUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
875 def : Pat<(pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
876 (STHUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
877 def : Pat<(pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
878 (STWUX8 G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
879 def : Pat<(pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff),
880 (STDUX G8RC:$rS, xaddroff:$ptroff, ptr_rc:$ptrreg)>;
883 //===----------------------------------------------------------------------===//
884 // Floating point instructions.
888 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
889 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
890 "fcfid $frD, $frB", FPGeneral,
891 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
892 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
893 "fctidz $frD, $frB", FPGeneral,
894 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
898 //===----------------------------------------------------------------------===//
899 // Instruction Patterns
902 // Extensions and truncates to/from 32-bit regs.
903 def : Pat<(i64 (zext GPRC:$in)),
904 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32),
906 def : Pat<(i64 (anyext GPRC:$in)),
907 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>;
908 def : Pat<(i32 (trunc G8RC:$in)),
909 (EXTRACT_SUBREG G8RC:$in, sub_32)>;
911 // Extending loads with i64 targets.
912 def : Pat<(zextloadi1 iaddr:$src),
914 def : Pat<(zextloadi1 xaddr:$src),
916 def : Pat<(extloadi1 iaddr:$src),
918 def : Pat<(extloadi1 xaddr:$src),
920 def : Pat<(extloadi8 iaddr:$src),
922 def : Pat<(extloadi8 xaddr:$src),
924 def : Pat<(extloadi16 iaddr:$src),
926 def : Pat<(extloadi16 xaddr:$src),
928 def : Pat<(extloadi32 iaddr:$src),
930 def : Pat<(extloadi32 xaddr:$src),
933 // Standard shifts. These are represented separately from the real shifts above
934 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
936 def : Pat<(sra G8RC:$rS, GPRC:$rB),
937 (SRAD G8RC:$rS, GPRC:$rB)>;
938 def : Pat<(srl G8RC:$rS, GPRC:$rB),
939 (SRD G8RC:$rS, GPRC:$rB)>;
940 def : Pat<(shl G8RC:$rS, GPRC:$rB),
941 (SLD G8RC:$rS, GPRC:$rB)>;
944 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
945 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
946 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
947 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
950 def : Pat<(rotl G8RC:$in, GPRC:$sh),
951 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
952 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
953 (RLDICL G8RC:$in, imm:$imm, 0)>;
955 // Hi and Lo for Darwin Global Addresses.
956 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
957 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
958 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
959 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
960 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
961 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
962 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
963 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
964 def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in),
965 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>;
966 def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in),
967 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>;
968 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
969 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
970 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
971 (ADDIS8 G8RC:$in, tconstpool:$g)>;
972 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
973 (ADDIS8 G8RC:$in, tjumptable:$g)>;
974 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
975 (ADDIS8 G8RC:$in, tblockaddress:$g)>;
977 // Patterns to match r+r indexed loads and stores for
978 // addresses without at least 4-byte alignment.
979 def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)),
981 def : Pat<(i64 (unaligned4load xoaddr:$src)),
983 def : Pat<(unaligned4store G8RC:$rS, xoaddr:$dst),
984 (STDX G8RC:$rS, xoaddr:$dst)>;