1 //===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
26 let EncoderMethod = "getHA16Encoding";
28 def symbolLo64 : Operand<i64> {
29 let PrintMethod = "printSymbolLo";
30 let EncoderMethod = "getLO16Encoding";
33 //===----------------------------------------------------------------------===//
34 // 64-bit transformation functions.
37 def SHL64 : SDNodeXForm<imm, [{
38 // Transformation function: 63 - imm
39 return getI32Imm(63 - N->getZExtValue());
42 def SRL64 : SDNodeXForm<imm, [{
43 // Transformation function: 64 - imm
44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0);
47 def HI32_48 : SDNodeXForm<imm, [{
48 // Transformation function: shift the immediate value down into the low bits.
49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32));
52 def HI48_64 : SDNodeXForm<imm, [{
53 // Transformation function: shift the immediate value down into the low bits.
54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48));
58 //===----------------------------------------------------------------------===//
63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>,
67 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
68 // Convenient aliases for call instructions
70 def BL8_Darwin : IForm<18, 0, 1,
71 (outs), (ins calltarget:$func, variable_ops),
72 "bl $func", BrB, []>; // See Pat patterns below.
73 def BLA8_Darwin : IForm<18, 1, 1,
74 (outs), (ins aaddr:$func, variable_ops),
75 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>;
77 let Uses = [CTR8, RM] in {
78 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1,
79 (outs), (ins variable_ops),
81 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>;
85 // ELF 64 ABI Calls = Darwin ABI Calls
86 // Used to define BL8_ELF and BLA8_ELF
87 let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in {
88 // Convenient aliases for call instructions
90 def BL8_ELF : IForm<18, 0, 1,
91 (outs), (ins calltarget:$func, variable_ops),
92 "bl $func", BrB, []>; // See Pat patterns below.
94 let isCodeGenOnly = 1 in
95 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24,
96 (outs), (ins calltarget:$func, variable_ops),
97 "bl $func\n\tnop", BrB, []>;
99 def BLA8_ELF : IForm<18, 1, 1,
100 (outs), (ins aaddr:$func, variable_ops),
101 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>;
103 let isCodeGenOnly = 1 in
104 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24,
105 (outs), (ins aaddr:$func, variable_ops),
106 "bla $func\n\tnop", BrB,
107 [(PPCcall_nop_SVR4 (i64 imm:$func))]>;
109 let Uses = [X11, CTR8, RM] in {
110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1,
111 (outs), (ins variable_ops),
113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>;
119 def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)),
120 (BL8_Darwin tglobaladdr:$dst)>;
121 def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)),
122 (BL8_Darwin texternalsym:$dst)>;
124 def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)),
125 (BL8_ELF tglobaladdr:$dst)>;
126 def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)),
127 (BL8_NOP_ELF tglobaladdr:$dst)>;
129 def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)),
130 (BL8_ELF texternalsym:$dst)>;
131 def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)),
132 (BL8_NOP_ELF texternalsym:$dst)>;
138 let usesCustomInserter = 1 in {
139 let Defs = [CR0] in {
140 def ATOMIC_LOAD_ADD_I64 : Pseudo<
141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
142 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>;
143 def ATOMIC_LOAD_SUB_I64 : Pseudo<
144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
145 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>;
146 def ATOMIC_LOAD_OR_I64 : Pseudo<
147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
148 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>;
149 def ATOMIC_LOAD_XOR_I64 : Pseudo<
150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
151 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>;
152 def ATOMIC_LOAD_AND_I64 : Pseudo<
153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
154 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>;
155 def ATOMIC_LOAD_NAND_I64 : Pseudo<
156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "",
157 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>;
159 def ATOMIC_CMP_SWAP_I64 : Pseudo<
160 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "",
162 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>;
164 def ATOMIC_SWAP_I64 : Pseudo<
165 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "",
166 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>;
170 // Instructions to support atomic operations
171 def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr),
172 "ldarx $rD, $ptr", LdStLDARX,
173 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>;
176 def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst),
177 "stdcx. $rS, $dst", LdStSTDCX,
178 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>,
181 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
182 def TCRETURNdi8 :Pseudo< (outs),
183 (ins calltarget:$dst, i32imm:$offset, variable_ops),
184 "#TC_RETURNd8 $dst $offset",
187 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
188 def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops),
189 "#TC_RETURNa8 $func $offset",
190 [(PPCtc_return (i64 imm:$func), imm:$offset)]>;
192 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in
193 def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops),
194 "#TC_RETURNr8 $dst $offset",
198 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1,
199 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in {
200 let isReturn = 1 in {
201 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
202 Requires<[In64BitMode]>;
205 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>,
206 Requires<[In64BitMode]>;
210 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
212 def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst),
217 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7,
218 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in
219 def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst),
223 def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm),
224 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>;
226 def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm),
227 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>;
229 def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm),
230 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>;
232 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
233 let Defs = [CTR8], Uses = [CTR8] in {
234 def BDZ8 : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
235 "bdz $dst", BrB, []>;
236 def BDNZ8 : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
237 "bdnz $dst", BrB, []>;
241 // 64-but CR instructions
242 def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS),
243 "mtcrf $FXM, $rS", BrMCRX>,
244 PPC970_MicroCode, PPC970_Unit_CRU;
246 def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM),
248 PPC970_MicroCode, PPC970_Unit_CRU;
250 def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins),
251 "mfcr $rT", SprMFCR>,
252 PPC970_MicroCode, PPC970_Unit_CRU;
254 //===----------------------------------------------------------------------===//
255 // 64-bit SPR manipulation instrs.
257 let Uses = [CTR8] in {
258 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins),
259 "mfctr $rT", SprMFSPR>,
260 PPC970_DGroup_First, PPC970_Unit_FXU;
262 let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in {
263 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS),
264 "mtctr $rS", SprMTSPR>,
265 PPC970_DGroup_First, PPC970_Unit_FXU;
268 let Defs = [X1], Uses = [X1] in
269 def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"",
271 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>;
273 let Defs = [LR8] in {
274 def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS),
275 "mtlr $rS", SprMTSPR>,
276 PPC970_DGroup_First, PPC970_Unit_FXU;
278 let Uses = [LR8] in {
279 def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins),
280 "mflr $rT", SprMFSPR>,
281 PPC970_DGroup_First, PPC970_Unit_FXU;
284 //===----------------------------------------------------------------------===//
285 // Fixed point instructions.
288 let PPC970_Unit = 1 in { // FXU Operations.
290 // Copies, extends, truncates.
291 def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB),
292 "or $rA, $rS, $rB", IntGeneral,
294 def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB),
295 "or $rA, $rS, $rB", IntGeneral,
298 def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm),
299 "li $rD, $imm", IntGeneral,
300 [(set G8RC:$rD, immSExt16:$imm)]>;
301 def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm),
302 "lis $rD, $imm", IntGeneral,
303 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
306 def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
307 "nand $rA, $rS, $rB", IntGeneral,
308 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
309 def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
310 "and $rA, $rS, $rB", IntGeneral,
311 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
312 def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
313 "andc $rA, $rS, $rB", IntGeneral,
314 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
315 def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
316 "or $rA, $rS, $rB", IntGeneral,
317 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
318 def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
319 "nor $rA, $rS, $rB", IntGeneral,
320 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
321 def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
322 "orc $rA, $rS, $rB", IntGeneral,
323 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
324 def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
325 "eqv $rA, $rS, $rB", IntGeneral,
326 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
327 def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB),
328 "xor $rA, $rS, $rB", IntGeneral,
329 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
331 // Logical ops with immediate.
332 def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
333 "andi. $dst, $src1, $src2", IntGeneral,
334 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
336 def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
337 "andis. $dst, $src1, $src2", IntGeneral,
338 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
340 def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
341 "ori $dst, $src1, $src2", IntGeneral,
342 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
343 def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
344 "oris $dst, $src1, $src2", IntGeneral,
345 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
346 def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
347 "xori $dst, $src1, $src2", IntGeneral,
348 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
349 def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2),
350 "xoris $dst, $src1, $src2", IntGeneral,
351 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
353 def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
354 "add $rT, $rA, $rB", IntGeneral,
355 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
357 let Defs = [CARRY] in {
358 def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
359 "addc $rT, $rA, $rB", IntGeneral,
360 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>,
361 PPC970_DGroup_Cracked;
362 def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
363 "addic $rD, $rA, $imm", IntGeneral,
364 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>;
366 def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
367 "addi $rD, $rA, $imm", IntGeneral,
368 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
369 def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm),
370 "addi $rD, $rA, $imm", IntGeneral,
371 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
372 def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm),
373 "addis $rD, $rA, $imm", IntGeneral,
374 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
376 let Defs = [CARRY] in {
377 def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm),
378 "subfic $rD, $rA, $imm", IntGeneral,
379 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
380 def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
381 "subfc $rT, $rA, $rB", IntGeneral,
382 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>,
383 PPC970_DGroup_Cracked;
385 def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
386 "subf $rT, $rA, $rB", IntGeneral,
387 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
388 def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA),
389 "neg $rT, $rA", IntGeneral,
390 [(set G8RC:$rT, (ineg G8RC:$rA))]>;
391 let Uses = [CARRY], Defs = [CARRY] in {
392 def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
393 "adde $rT, $rA, $rB", IntGeneral,
394 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>;
395 def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA),
396 "addme $rT, $rA", IntGeneral,
397 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>;
398 def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA),
399 "addze $rT, $rA", IntGeneral,
400 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>;
401 def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
402 "subfe $rT, $rA, $rB", IntGeneral,
403 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>;
404 def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA),
405 "subfme $rT, $rA", IntGeneral,
406 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>;
407 def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA),
408 "subfze $rT, $rA", IntGeneral,
409 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>;
413 def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
414 "mulhd $rT, $rA, $rB", IntMulHW,
415 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
416 def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
417 "mulhdu $rT, $rA, $rB", IntMulHWU,
418 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
420 def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
421 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
422 def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB),
423 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
424 def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm),
425 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
426 def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2),
427 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
429 def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
430 "sld $rA, $rS, $rB", IntRotateD,
431 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64;
432 def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
433 "srd $rA, $rS, $rB", IntRotateD,
434 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64;
435 let Defs = [CARRY] in {
436 def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB),
437 "srad $rA, $rS, $rB", IntRotateD,
438 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64;
441 def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS),
442 "extsb $rA, $rS", IntGeneral,
443 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
444 def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS),
445 "extsh $rA, $rS", IntGeneral,
446 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
448 def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS),
449 "extsw $rA, $rS", IntGeneral,
450 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
451 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
452 def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS),
453 "extsw $rA, $rS", IntGeneral,
454 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
455 def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS),
456 "extsw $rA, $rS", IntGeneral,
457 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
459 let Defs = [CARRY] in {
460 def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH),
461 "sradi $rA, $rS, $SH", IntRotateD,
462 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
464 def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS),
465 "cntlzd $rA, $rS", IntGeneral,
466 [(set G8RC:$rA, (ctlz G8RC:$rS))]>;
468 def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
469 "divd $rT, $rA, $rB", IntDivD,
470 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
471 PPC970_DGroup_First, PPC970_DGroup_Cracked;
472 def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
473 "divdu $rT, $rA, $rB", IntDivD,
474 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
475 PPC970_DGroup_First, PPC970_DGroup_Cracked;
476 def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB),
477 "mulld $rT, $rA, $rB", IntMulHD,
478 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
481 let isCommutable = 1 in {
482 def RLDIMI : MDForm_1<30, 3,
483 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
484 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
485 []>, isPPC64, RegConstraint<"$rSi = $rA">,
489 // Rotate instructions.
490 def RLDCL : MDForm_1<30, 0,
491 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB),
492 "rldcl $rA, $rS, $rB, $MB", IntRotateD,
494 def RLDICL : MDForm_1<30, 0,
495 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB),
496 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
498 def RLDICR : MDForm_1<30, 1,
499 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME),
500 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
503 def RLWINM8 : MForm_2<21,
504 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME),
505 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral,
508 } // End FXU Operations.
511 //===----------------------------------------------------------------------===//
512 // Load/Store instructions.
516 // Sign extending loads.
517 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
518 def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src),
519 "lha $rD, $src", LdStLHA,
520 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
521 PPC970_DGroup_Cracked;
522 def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src),
523 "lwa $rD, $src", LdStLWA,
524 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
525 PPC970_DGroup_Cracked;
526 def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src),
527 "lhax $rD, $src", LdStLHA,
528 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
529 PPC970_DGroup_Cracked;
530 def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src),
531 "lwax $rD, $src", LdStLHA,
532 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
533 PPC970_DGroup_Cracked;
537 def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp,
539 "lhau $rD, $disp($rA)", LdStLoad,
540 []>, RegConstraint<"$rA = $ea_result">,
541 NoEncode<"$ea_result">;
546 // Zero extending loads.
547 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
548 def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src),
549 "lbz $rD, $src", LdStLoad,
550 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
551 def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src),
552 "lhz $rD, $src", LdStLoad,
553 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
554 def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src),
555 "lwz $rD, $src", LdStLoad,
556 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
558 def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src),
559 "lbzx $rD, $src", LdStLoad,
560 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
561 def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src),
562 "lhzx $rD, $src", LdStLoad,
563 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
564 def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src),
565 "lwzx $rD, $src", LdStLoad,
566 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
571 def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
572 "lbzu $rD, $addr", LdStLoad,
573 []>, RegConstraint<"$addr.reg = $ea_result">,
574 NoEncode<"$ea_result">;
575 def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
576 "lhzu $rD, $addr", LdStLoad,
577 []>, RegConstraint<"$addr.reg = $ea_result">,
578 NoEncode<"$ea_result">;
579 def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr),
580 "lwzu $rD, $addr", LdStLoad,
581 []>, RegConstraint<"$addr.reg = $ea_result">,
582 NoEncode<"$ea_result">;
587 // Full 8-byte loads.
588 let canFoldAsLoad = 1, PPC970_Unit = 2 in {
589 def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src),
590 "ld $rD, $src", LdStLD,
591 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
592 def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg),
595 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64;
597 let hasSideEffects = 1 in {
598 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
599 def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg),
600 "ld 2, 8($reg)", LdStLD,
601 [(PPCload_toc G8RC:$reg)]>, isPPC64;
603 let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo.
604 def LDtoc_restore : DSForm_1<58, 0, (outs), (ins),
605 "ld 2, 40(1)", LdStLD,
606 [(PPCtoc_restore)]>, isPPC64;
608 def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src),
609 "ldx $rD, $src", LdStLD,
610 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
613 def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr),
614 "ldu $rD, $addr", LdStLD,
615 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
616 NoEncode<"$ea_result">;
620 def : Pat<(PPCload ixaddr:$src),
622 def : Pat<(PPCload xaddr:$src),
625 let PPC970_Unit = 2 in {
626 // Truncating stores.
627 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
628 "stb $rS, $src", LdStStore,
629 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
630 def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src),
631 "sth $rS, $src", LdStStore,
632 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
633 def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src),
634 "stw $rS, $src", LdStStore,
635 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
636 def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst),
637 "stbx $rS, $dst", LdStStore,
638 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
639 PPC970_DGroup_Cracked;
640 def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst),
641 "sthx $rS, $dst", LdStStore,
642 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
643 PPC970_DGroup_Cracked;
644 def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst),
645 "stwx $rS, $dst", LdStStore,
646 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
647 PPC970_DGroup_Cracked;
648 // Normal 8-byte stores.
649 def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst),
650 "std $rS, $dst", LdStSTD,
651 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
652 def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst),
653 "stdx $rS, $dst", LdStSTD,
654 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
655 PPC970_DGroup_Cracked;
658 let PPC970_Unit = 2 in {
660 def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
661 symbolLo:$ptroff, ptr_rc:$ptrreg),
662 "stbu $rS, $ptroff($ptrreg)", LdStStore,
663 [(set ptr_rc:$ea_res,
664 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
665 iaddroff:$ptroff))]>,
666 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
667 def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
668 symbolLo:$ptroff, ptr_rc:$ptrreg),
669 "sthu $rS, $ptroff($ptrreg)", LdStStore,
670 [(set ptr_rc:$ea_res,
671 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
672 iaddroff:$ptroff))]>,
673 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
675 def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
676 symbolLo:$ptroff, ptr_rc:$ptrreg),
677 "stwu $rS, $ptroff($ptrreg)", LdStStore,
678 [(set ptr_rc:$ea_res,
679 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg,
680 iaddroff:$ptroff))]>,
681 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
683 def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS,
684 s16immX4:$ptroff, ptr_rc:$ptrreg),
685 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
686 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
687 iaddroff:$ptroff))]>,
688 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
692 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
693 "stdux $rS, $dst", LdStSTD,
696 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
697 def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst),
698 "std $rT, $dst", LdStSTD,
699 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
700 def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst),
701 "stdx $rT, $dst", LdStSTD,
702 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
703 PPC970_DGroup_Cracked;
708 //===----------------------------------------------------------------------===//
709 // Floating point instructions.
713 let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations.
714 def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB),
715 "fcfid $frD, $frB", FPGeneral,
716 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
717 def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB),
718 "fctidz $frD, $frB", FPGeneral,
719 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
723 //===----------------------------------------------------------------------===//
724 // Instruction Patterns
727 // Extensions and truncates to/from 32-bit regs.
728 def : Pat<(i64 (zext GPRC:$in)),
729 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
730 def : Pat<(i64 (anyext GPRC:$in)),
731 (OR4To8 GPRC:$in, GPRC:$in)>;
732 def : Pat<(i32 (trunc G8RC:$in)),
733 (OR8To4 G8RC:$in, G8RC:$in)>;
735 // Extending loads with i64 targets.
736 def : Pat<(zextloadi1 iaddr:$src),
738 def : Pat<(zextloadi1 xaddr:$src),
740 def : Pat<(extloadi1 iaddr:$src),
742 def : Pat<(extloadi1 xaddr:$src),
744 def : Pat<(extloadi8 iaddr:$src),
746 def : Pat<(extloadi8 xaddr:$src),
748 def : Pat<(extloadi16 iaddr:$src),
750 def : Pat<(extloadi16 xaddr:$src),
752 def : Pat<(extloadi32 iaddr:$src),
754 def : Pat<(extloadi32 xaddr:$src),
757 // Standard shifts. These are represented separately from the real shifts above
758 // so that we can distinguish between shifts that allow 6-bit and 7-bit shift
760 def : Pat<(sra G8RC:$rS, GPRC:$rB),
761 (SRAD G8RC:$rS, GPRC:$rB)>;
762 def : Pat<(srl G8RC:$rS, GPRC:$rB),
763 (SRD G8RC:$rS, GPRC:$rB)>;
764 def : Pat<(shl G8RC:$rS, GPRC:$rB),
765 (SLD G8RC:$rS, GPRC:$rB)>;
768 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
769 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
770 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
771 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
774 def : Pat<(rotl G8RC:$in, GPRC:$sh),
775 (RLDCL G8RC:$in, GPRC:$sh, 0)>;
776 def : Pat<(rotl G8RC:$in, (i32 imm:$imm)),
777 (RLDICL G8RC:$in, imm:$imm, 0)>;
779 // Hi and Lo for Darwin Global Addresses.
780 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
781 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
782 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
783 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
784 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
785 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
786 def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>;
787 def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>;
788 def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in),
789 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>;
790 def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in),
791 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>;
792 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
793 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
794 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
795 (ADDIS8 G8RC:$in, tconstpool:$g)>;
796 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
797 (ADDIS8 G8RC:$in, tjumptable:$g)>;
798 def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)),
799 (ADDIS8 G8RC:$in, tblockaddress:$g)>;