1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
57 // Pseudo instructions.
60 def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD",
61 [(set G8RC:$rD, (undef))]>;
64 //===----------------------------------------------------------------------===//
69 def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>,
73 let isCall = 1, noResults = 1, PPC970_Unit = 7,
74 // All calls clobber the PPC64 non-callee saved registers.
75 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
76 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
77 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
79 CR0,CR1,CR5,CR6,CR7] in {
80 // Convenient aliases for call instructions
81 def BL8_Macho : IForm<18, 0, 1,
82 (ops calltarget:$func, variable_ops),
83 "bl $func", BrB, []>; // See Pat patterns below.
85 def BLA8_Macho : IForm<18, 1, 1,
86 (ops aaddr:$func, variable_ops),
87 "bla $func", BrB, [(PPCcall_Macho (i64 imm:$func))]>;
91 let isCall = 1, noResults = 1, PPC970_Unit = 7,
92 // All calls clobber the PPC64 non-callee saved registers.
93 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
94 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,
95 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
97 CR0,CR1,CR5,CR6,CR7] in {
98 // Convenient aliases for call instructions
99 def BL8_ELF : IForm<18, 0, 1,
100 (ops calltarget:$func, variable_ops),
101 "bl $func", BrB, []>; // See Pat patterns below.
103 def BLA8_ELF : IForm<18, 1, 1,
104 (ops aaddr:$func, variable_ops),
105 "bla $func", BrB, [(PPCcall_ELF (i64 imm:$func))]>;
110 def : Pat<(PPCcall_Macho (i64 tglobaladdr:$dst)),
111 (BL8_Macho tglobaladdr:$dst)>;
112 def : Pat<(PPCcall_Macho (i64 texternalsym:$dst)),
113 (BL8_Macho texternalsym:$dst)>;
115 def : Pat<(PPCcall_ELF (i64 tglobaladdr:$dst)),
116 (BL8_ELF tglobaladdr:$dst)>;
117 def : Pat<(PPCcall_ELF (i64 texternalsym:$dst)),
118 (BL8_ELF texternalsym:$dst)>;
120 //===----------------------------------------------------------------------===//
121 // 64-bit SPR manipulation instrs.
123 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>,
124 PPC970_DGroup_First, PPC970_Unit_FXU;
125 let Pattern = [(PPCmtctr G8RC:$rS)] in {
126 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
127 PPC970_DGroup_First, PPC970_Unit_FXU;
130 def DYNALLOC8 : Pseudo<(ops G8RC:$result, G8RC:$negsize, memri:$fpsi),
131 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
133 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>,
136 def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>,
137 PPC970_DGroup_First, PPC970_Unit_FXU;
138 def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>,
139 PPC970_DGroup_First, PPC970_Unit_FXU;
142 //===----------------------------------------------------------------------===//
143 // Fixed point instructions.
146 let PPC970_Unit = 1 in { // FXU Operations.
148 // Copies, extends, truncates.
149 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
150 "or $rA, $rS, $rB", IntGeneral,
152 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
153 "or $rA, $rS, $rB", IntGeneral,
156 def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
157 "li $rD, $imm", IntGeneral,
158 [(set G8RC:$rD, immSExt16:$imm)]>;
159 def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
160 "lis $rD, $imm", IntGeneral,
161 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
164 def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
165 "nand $rA, $rS, $rB", IntGeneral,
166 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
167 def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
168 "and $rA, $rS, $rB", IntGeneral,
169 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
170 def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
171 "andc $rA, $rS, $rB", IntGeneral,
172 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
173 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
174 "or $rA, $rS, $rB", IntGeneral,
175 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
176 def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
177 "nor $rA, $rS, $rB", IntGeneral,
178 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
179 def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
180 "orc $rA, $rS, $rB", IntGeneral,
181 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
182 def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
183 "eqv $rA, $rS, $rB", IntGeneral,
184 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
185 def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
186 "xor $rA, $rS, $rB", IntGeneral,
187 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
189 // Logical ops with immediate.
190 def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
191 "andi. $dst, $src1, $src2", IntGeneral,
192 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
194 def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
195 "andis. $dst, $src1, $src2", IntGeneral,
196 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
198 def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
199 "ori $dst, $src1, $src2", IntGeneral,
200 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
201 def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
202 "oris $dst, $src1, $src2", IntGeneral,
203 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
204 def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
205 "xori $dst, $src1, $src2", IntGeneral,
206 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
207 def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
208 "xoris $dst, $src1, $src2", IntGeneral,
209 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
211 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
212 "add $rT, $rA, $rB", IntGeneral,
213 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
214 def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
215 "addi $rD, $rA, $imm", IntGeneral,
216 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
217 def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
218 "addis $rD, $rA, $imm", IntGeneral,
219 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
221 def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
222 "subfic $rD, $rA, $imm", IntGeneral,
223 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
224 def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
225 "subf $rT, $rA, $rB", IntGeneral,
226 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
229 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
230 "mulhd $rT, $rA, $rB", IntMulHW,
231 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
232 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
233 "mulhdu $rT, $rA, $rB", IntMulHWU,
234 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
236 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
237 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
238 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
239 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
240 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm),
241 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
242 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2),
243 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
245 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
246 "sld $rA, $rS, $rB", IntRotateD,
247 [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
248 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
249 "srd $rA, $rS, $rB", IntRotateD,
250 [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
251 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
252 "srad $rA, $rS, $rB", IntRotateD,
253 [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
255 def EXTSB8 : XForm_11<31, 954, (ops G8RC:$rA, G8RC:$rS),
256 "extsb $rA, $rS", IntGeneral,
257 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>;
258 def EXTSH8 : XForm_11<31, 922, (ops G8RC:$rA, G8RC:$rS),
259 "extsh $rA, $rS", IntGeneral,
260 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>;
262 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
263 "extsw $rA, $rS", IntGeneral,
264 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
265 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
266 def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
267 "extsw $rA, $rS", IntGeneral,
268 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
269 def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS),
270 "extsw $rA, $rS", IntGeneral,
271 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
273 def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH),
274 "sradi $rA, $rS, $SH", IntRotateD,
275 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
277 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
278 "divd $rT, $rA, $rB", IntDivD,
279 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
280 PPC970_DGroup_First, PPC970_DGroup_Cracked;
281 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
282 "divdu $rT, $rA, $rB", IntDivD,
283 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
284 PPC970_DGroup_First, PPC970_DGroup_Cracked;
285 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
286 "mulld $rT, $rA, $rB", IntMulHD,
287 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
290 let isCommutable = 1 in {
291 def RLDIMI : MDForm_1<30, 3,
292 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
293 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
294 []>, isPPC64, RegConstraint<"$rSi = $rA">,
298 // Rotate instructions.
299 def RLDICL : MDForm_1<30, 0,
300 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
301 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
303 def RLDICR : MDForm_1<30, 1,
304 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
305 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
307 } // End FXU Operations.
310 //===----------------------------------------------------------------------===//
311 // Load/Store instructions.
315 // Sign extending loads.
316 let isLoad = 1, PPC970_Unit = 2 in {
317 def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src),
318 "lha $rD, $src", LdStLHA,
319 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
320 PPC970_DGroup_Cracked;
321 def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src),
322 "lwa $rD, $src", LdStLWA,
323 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
324 PPC970_DGroup_Cracked;
325 def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src),
326 "lhax $rD, $src", LdStLHA,
327 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
328 PPC970_DGroup_Cracked;
329 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
330 "lwax $rD, $src", LdStLHA,
331 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
332 PPC970_DGroup_Cracked;
335 def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp,
337 "lhau $rD, $disp($rA)", LdStGeneral,
338 []>, RegConstraint<"$rA = $ea_result">,
339 NoEncode<"$ea_result">;
344 // Zero extending loads.
345 let isLoad = 1, PPC970_Unit = 2 in {
346 def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src),
347 "lbz $rD, $src", LdStGeneral,
348 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
349 def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src),
350 "lhz $rD, $src", LdStGeneral,
351 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
352 def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src),
353 "lwz $rD, $src", LdStGeneral,
354 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
356 def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src),
357 "lbzx $rD, $src", LdStGeneral,
358 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
359 def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src),
360 "lhzx $rD, $src", LdStGeneral,
361 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
362 def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src),
363 "lwzx $rD, $src", LdStGeneral,
364 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
368 def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
369 "lbzu $rD, $addr", LdStGeneral,
370 []>, RegConstraint<"$addr.reg = $ea_result">,
371 NoEncode<"$ea_result">;
372 def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
373 "lhzu $rD, $addr", LdStGeneral,
374 []>, RegConstraint<"$addr.reg = $ea_result">,
375 NoEncode<"$ea_result">;
376 def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
377 "lwzu $rD, $addr", LdStGeneral,
378 []>, RegConstraint<"$addr.reg = $ea_result">,
379 NoEncode<"$ea_result">;
383 // Full 8-byte loads.
384 let isLoad = 1, PPC970_Unit = 2 in {
385 def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src),
386 "ld $rD, $src", LdStLD,
387 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
388 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
389 "ldx $rD, $src", LdStLD,
390 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
392 def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr),
393 "ldu $rD, $addr", LdStLD,
394 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
395 NoEncode<"$ea_result">;
399 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
400 // Truncating stores.
401 def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src),
402 "stb $rS, $src", LdStGeneral,
403 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
404 def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src),
405 "sth $rS, $src", LdStGeneral,
406 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
407 def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src),
408 "stw $rS, $src", LdStGeneral,
409 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
410 def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
411 "stbx $rS, $dst", LdStGeneral,
412 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
413 PPC970_DGroup_Cracked;
414 def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst),
415 "sthx $rS, $dst", LdStGeneral,
416 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
417 PPC970_DGroup_Cracked;
418 def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst),
419 "stwx $rS, $dst", LdStGeneral,
420 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
421 PPC970_DGroup_Cracked;
422 // Normal 8-byte stores.
423 def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst),
424 "std $rS, $dst", LdStSTD,
425 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
426 def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
427 "stdx $rS, $dst", LdStSTD,
428 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
429 PPC970_DGroup_Cracked;
432 let isStore = 1, PPC970_Unit = 2 in {
434 def STBU8 : DForm_1<38, (ops ptr_rc:$ea_res, G8RC:$rS,
435 symbolLo:$ptroff, ptr_rc:$ptrreg),
436 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
437 [(set ptr_rc:$ea_res,
438 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
439 iaddroff:$ptroff))]>,
440 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
441 def STHU8 : DForm_1<45, (ops ptr_rc:$ea_res, G8RC:$rS,
442 symbolLo:$ptroff, ptr_rc:$ptrreg),
443 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
444 [(set ptr_rc:$ea_res,
445 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
446 iaddroff:$ptroff))]>,
447 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
448 def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS,
449 symbolLo:$ptroff, ptr_rc:$ptrreg),
450 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
451 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
452 iaddroff:$ptroff))]>,
453 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
456 def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS,
457 s16immX4:$ptroff, ptr_rc:$ptrreg),
458 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
459 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
460 iaddroff:$ptroff))]>,
461 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
466 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
468 def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst),
469 "stdux $rS, $dst", LdStSTD,
473 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
474 def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst),
475 "std $rT, $dst", LdStSTD,
476 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
477 def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
478 "stdx $rT, $dst", LdStSTD,
479 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
480 PPC970_DGroup_Cracked;
485 //===----------------------------------------------------------------------===//
486 // Floating point instructions.
490 let PPC970_Unit = 3 in { // FPU Operations.
491 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
492 "fcfid $frD, $frB", FPGeneral,
493 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
494 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
495 "fctidz $frD, $frB", FPGeneral,
496 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
500 //===----------------------------------------------------------------------===//
501 // Instruction Patterns
504 // Extensions and truncates to/from 32-bit regs.
505 def : Pat<(i64 (zext GPRC:$in)),
506 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
507 def : Pat<(i64 (anyext GPRC:$in)),
508 (OR4To8 GPRC:$in, GPRC:$in)>;
509 def : Pat<(i32 (trunc G8RC:$in)),
510 (OR8To4 G8RC:$in, G8RC:$in)>;
512 // Extending loads with i64 targets.
513 def : Pat<(zextloadi1 iaddr:$src),
515 def : Pat<(zextloadi1 xaddr:$src),
517 def : Pat<(extloadi1 iaddr:$src),
519 def : Pat<(extloadi1 xaddr:$src),
521 def : Pat<(extloadi8 iaddr:$src),
523 def : Pat<(extloadi8 xaddr:$src),
525 def : Pat<(extloadi16 iaddr:$src),
527 def : Pat<(extloadi16 xaddr:$src),
529 def : Pat<(extloadi32 iaddr:$src),
531 def : Pat<(extloadi32 xaddr:$src),
535 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
536 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
537 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
538 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
540 // Hi and Lo for Darwin Global Addresses.
541 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
542 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
543 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
544 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
545 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
546 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
547 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
548 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
549 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
550 (ADDIS8 G8RC:$in, tconstpool:$g)>;
551 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
552 (ADDIS8 G8RC:$in, tjumptable:$g)>;