1 //===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the PowerPC 64-bit instructions. These patterns are used
11 // both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
13 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
18 def s16imm64 : Operand<i64> {
19 let PrintMethod = "printS16ImmOperand";
21 def u16imm64 : Operand<i64> {
22 let PrintMethod = "printU16ImmOperand";
24 def symbolHi64 : Operand<i64> {
25 let PrintMethod = "printSymbolHi";
27 def symbolLo64 : Operand<i64> {
28 let PrintMethod = "printSymbolLo";
31 //===----------------------------------------------------------------------===//
32 // 64-bit transformation functions.
35 def SHL64 : SDNodeXForm<imm, [{
36 // Transformation function: 63 - imm
37 return getI32Imm(63 - N->getValue());
40 def SRL64 : SDNodeXForm<imm, [{
41 // Transformation function: 64 - imm
42 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
45 def HI32_48 : SDNodeXForm<imm, [{
46 // Transformation function: shift the immediate value down into the low bits.
47 return getI32Imm((unsigned short)(N->getValue() >> 32));
50 def HI48_64 : SDNodeXForm<imm, [{
51 // Transformation function: shift the immediate value down into the low bits.
52 return getI32Imm((unsigned short)(N->getValue() >> 48));
56 //===----------------------------------------------------------------------===//
57 // Pseudo instructions.
60 def IMPLICIT_DEF_G8RC : Pseudo<(ops G8RC:$rD), "; IMPLICIT_DEF_G8RC $rD",
61 [(set G8RC:$rD, (undef))]>;
64 //===----------------------------------------------------------------------===//
69 def MovePCtoLR8 : Pseudo<(ops piclabel:$label), "bl $label", []>,
72 let isCall = 1, noResults = 1, PPC970_Unit = 7,
73 // All calls clobber the PPC64 non-callee saved registers.
74 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
75 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
76 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19,
78 CR0,CR1,CR5,CR6,CR7] in {
79 // Convenient aliases for call instructions
80 def BL8 : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
81 "bl $func", BrB, []>; // See Pat patterns below.
83 def BLA8 : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
84 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>;
88 def : Pat<(PPCcall (i64 tglobaladdr:$dst)),
89 (BL8 tglobaladdr:$dst)>;
90 def : Pat<(PPCcall (i64 texternalsym:$dst)),
91 (BL8 texternalsym:$dst)>;
93 //===----------------------------------------------------------------------===//
94 // 64-bit SPR manipulation instrs.
96 def MFCTR8 : XFXForm_1_ext<31, 339, 9, (ops G8RC:$rT), "mfctr $rT", SprMFSPR>,
97 PPC970_DGroup_First, PPC970_Unit_FXU;
98 let Pattern = [(PPCmtctr G8RC:$rS)] in {
99 def MTCTR8 : XFXForm_7_ext<31, 467, 9, (ops G8RC:$rS), "mtctr $rS", SprMTSPR>,
100 PPC970_DGroup_First, PPC970_Unit_FXU;
103 def DYNALLOC8 : Pseudo<(ops G8RC:$result, G8RC:$negsize, memri:$fpsi),
104 "${:comment} DYNALLOC8 $result, $negsize, $fpsi",
106 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>,
109 def MTLR8 : XFXForm_7_ext<31, 467, 8, (ops G8RC:$rS), "mtlr $rS", SprMTSPR>,
110 PPC970_DGroup_First, PPC970_Unit_FXU;
111 def MFLR8 : XFXForm_1_ext<31, 339, 8, (ops G8RC:$rT), "mflr $rT", SprMFSPR>,
112 PPC970_DGroup_First, PPC970_Unit_FXU;
115 //===----------------------------------------------------------------------===//
116 // Fixed point instructions.
119 let PPC970_Unit = 1 in { // FXU Operations.
121 // Copies, extends, truncates.
122 def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
123 "or $rA, $rS, $rB", IntGeneral,
125 def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
126 "or $rA, $rS, $rB", IntGeneral,
129 def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
130 "li $rD, $imm", IntGeneral,
131 [(set G8RC:$rD, immSExt16:$imm)]>;
132 def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
133 "lis $rD, $imm", IntGeneral,
134 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
137 def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
138 "nand $rA, $rS, $rB", IntGeneral,
139 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
140 def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
141 "and $rA, $rS, $rB", IntGeneral,
142 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
143 def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
144 "andc $rA, $rS, $rB", IntGeneral,
145 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
146 def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
147 "or $rA, $rS, $rB", IntGeneral,
148 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
149 def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
150 "nor $rA, $rS, $rB", IntGeneral,
151 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
152 def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
153 "orc $rA, $rS, $rB", IntGeneral,
154 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
155 def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
156 "eqv $rA, $rS, $rB", IntGeneral,
157 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
158 def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
159 "xor $rA, $rS, $rB", IntGeneral,
160 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
162 // Logical ops with immediate.
163 def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
164 "andi. $dst, $src1, $src2", IntGeneral,
165 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
167 def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
168 "andis. $dst, $src1, $src2", IntGeneral,
169 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
171 def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
172 "ori $dst, $src1, $src2", IntGeneral,
173 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
174 def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
175 "oris $dst, $src1, $src2", IntGeneral,
176 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
177 def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
178 "xori $dst, $src1, $src2", IntGeneral,
179 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
180 def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
181 "xoris $dst, $src1, $src2", IntGeneral,
182 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
184 def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
185 "add $rT, $rA, $rB", IntGeneral,
186 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
187 def ADDI8 : DForm_2<14, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
188 "addi $rD, $rA, $imm", IntGeneral,
189 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>;
190 def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
191 "addis $rD, $rA, $imm", IntGeneral,
192 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
194 def SUBFIC8: DForm_2< 8, (ops G8RC:$rD, G8RC:$rA, s16imm64:$imm),
195 "subfic $rD, $rA, $imm", IntGeneral,
196 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>;
197 def SUBF8 : XOForm_1<31, 40, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
198 "subf $rT, $rA, $rB", IntGeneral,
199 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>;
202 def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
203 "mulhd $rT, $rA, $rB", IntMulHW,
204 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
205 def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
206 "mulhdu $rT, $rA, $rB", IntMulHWU,
207 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
209 def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
210 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
211 def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, G8RC:$rA, G8RC:$rB),
212 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
213 def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, G8RC:$rA, s16imm:$imm),
214 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
215 def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, G8RC:$src1, u16imm:$src2),
216 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
218 def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
219 "sld $rA, $rS, $rB", IntRotateD,
220 [(set G8RC:$rA, (shl G8RC:$rS, GPRC:$rB))]>, isPPC64;
221 def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
222 "srd $rA, $rS, $rB", IntRotateD,
223 [(set G8RC:$rA, (srl G8RC:$rS, GPRC:$rB))]>, isPPC64;
224 def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, GPRC:$rB),
225 "srad $rA, $rS, $rB", IntRotateD,
226 [(set G8RC:$rA, (sra G8RC:$rS, GPRC:$rB))]>, isPPC64;
227 def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
228 "extsw $rA, $rS", IntGeneral,
229 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
230 /// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
231 def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
232 "extsw $rA, $rS", IntGeneral,
233 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
234 def EXTSW_32_64 : XForm_11<31, 986, (ops G8RC:$rA, GPRC:$rS),
235 "extsw $rA, $rS", IntGeneral,
236 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64;
238 def SRADI : XSForm_1<31, 413, (ops G8RC:$rA, G8RC:$rS, u6imm:$SH),
239 "sradi $rA, $rS, $SH", IntRotateD,
240 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64;
242 def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
243 "divd $rT, $rA, $rB", IntDivD,
244 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
245 PPC970_DGroup_First, PPC970_DGroup_Cracked;
246 def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
247 "divdu $rT, $rA, $rB", IntDivD,
248 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
249 PPC970_DGroup_First, PPC970_DGroup_Cracked;
250 def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
251 "mulld $rT, $rA, $rB", IntMulHD,
252 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
255 let isCommutable = 1 in {
256 def RLDIMI : MDForm_1<30, 3,
257 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
258 "rldimi $rA, $rS, $SH, $MB", IntRotateD,
259 []>, isPPC64, RegConstraint<"$rSi = $rA">,
263 // Rotate instructions.
264 def RLDICL : MDForm_1<30, 0,
265 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
266 "rldicl $rA, $rS, $SH, $MB", IntRotateD,
268 def RLDICR : MDForm_1<30, 1,
269 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
270 "rldicr $rA, $rS, $SH, $ME", IntRotateD,
272 } // End FXU Operations.
275 //===----------------------------------------------------------------------===//
276 // Load/Store instructions.
280 // Sign extending loads.
281 let isLoad = 1, PPC970_Unit = 2 in {
282 def LHA8: DForm_1<42, (ops G8RC:$rD, memri:$src),
283 "lha $rD, $src", LdStLHA,
284 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>,
285 PPC970_DGroup_Cracked;
286 def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src),
287 "lwa $rD, $src", LdStLWA,
288 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64,
289 PPC970_DGroup_Cracked;
290 def LHAX8: XForm_1<31, 343, (ops G8RC:$rD, memrr:$src),
291 "lhax $rD, $src", LdStLHA,
292 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>,
293 PPC970_DGroup_Cracked;
294 def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
295 "lwax $rD, $src", LdStLHA,
296 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64,
297 PPC970_DGroup_Cracked;
300 def LHAU8 : DForm_1<43, (ops G8RC:$rD, ptr_rc:$ea_result, symbolLo:$disp,
302 "lhau $rD, $disp($rA)", LdStGeneral,
303 []>, RegConstraint<"$rA = $ea_result">,
304 NoEncode<"$ea_result">;
309 // Zero extending loads.
310 let isLoad = 1, PPC970_Unit = 2 in {
311 def LBZ8 : DForm_1<34, (ops G8RC:$rD, memri:$src),
312 "lbz $rD, $src", LdStGeneral,
313 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>;
314 def LHZ8 : DForm_1<40, (ops G8RC:$rD, memri:$src),
315 "lhz $rD, $src", LdStGeneral,
316 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>;
317 def LWZ8 : DForm_1<32, (ops G8RC:$rD, memri:$src),
318 "lwz $rD, $src", LdStGeneral,
319 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64;
321 def LBZX8 : XForm_1<31, 87, (ops G8RC:$rD, memrr:$src),
322 "lbzx $rD, $src", LdStGeneral,
323 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>;
324 def LHZX8 : XForm_1<31, 279, (ops G8RC:$rD, memrr:$src),
325 "lhzx $rD, $src", LdStGeneral,
326 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>;
327 def LWZX8 : XForm_1<31, 23, (ops G8RC:$rD, memrr:$src),
328 "lwzx $rD, $src", LdStGeneral,
329 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>;
333 def LBZU8 : DForm_1<35, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
334 "lbzu $rD, $addr", LdStGeneral,
335 []>, RegConstraint<"$addr.reg = $ea_result">,
336 NoEncode<"$ea_result">;
337 def LHZU8 : DForm_1<41, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
338 "lhzu $rD, $addr", LdStGeneral,
339 []>, RegConstraint<"$addr.reg = $ea_result">,
340 NoEncode<"$ea_result">;
341 def LWZU8 : DForm_1<33, (ops G8RC:$rD, ptr_rc:$ea_result, memri:$addr),
342 "lwzu $rD, $addr", LdStGeneral,
343 []>, RegConstraint<"$addr.reg = $ea_result">,
344 NoEncode<"$ea_result">;
348 // Full 8-byte loads.
349 let isLoad = 1, PPC970_Unit = 2 in {
350 def LD : DSForm_1<58, 0, (ops G8RC:$rD, memrix:$src),
351 "ld $rD, $src", LdStLD,
352 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
353 def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src),
354 "ldx $rD, $src", LdStLD,
355 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
357 def LDU : DSForm_1<58, 1, (ops G8RC:$rD, ptr_rc:$ea_result, memrix:$addr),
358 "ldu $rD, $addr", LdStLD,
359 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64,
360 NoEncode<"$ea_result">;
364 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
365 // Truncating stores.
366 def STB8 : DForm_1<38, (ops G8RC:$rS, memri:$src),
367 "stb $rS, $src", LdStGeneral,
368 [(truncstorei8 G8RC:$rS, iaddr:$src)]>;
369 def STH8 : DForm_1<44, (ops G8RC:$rS, memri:$src),
370 "sth $rS, $src", LdStGeneral,
371 [(truncstorei16 G8RC:$rS, iaddr:$src)]>;
372 def STW8 : DForm_1<36, (ops G8RC:$rS, memri:$src),
373 "stw $rS, $src", LdStGeneral,
374 [(truncstorei32 G8RC:$rS, iaddr:$src)]>;
375 def STBX8 : XForm_8<31, 215, (ops G8RC:$rS, memrr:$dst),
376 "stbx $rS, $dst", LdStGeneral,
377 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>,
378 PPC970_DGroup_Cracked;
379 def STHX8 : XForm_8<31, 407, (ops G8RC:$rS, memrr:$dst),
380 "sthx $rS, $dst", LdStGeneral,
381 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>,
382 PPC970_DGroup_Cracked;
383 def STWX8 : XForm_8<31, 151, (ops G8RC:$rS, memrr:$dst),
384 "stwx $rS, $dst", LdStGeneral,
385 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>,
386 PPC970_DGroup_Cracked;
387 // Normal 8-byte stores.
388 def STD : DSForm_1<62, 0, (ops G8RC:$rS, memrix:$dst),
389 "std $rS, $dst", LdStSTD,
390 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
391 def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
392 "stdx $rS, $dst", LdStSTD,
393 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64,
394 PPC970_DGroup_Cracked;
397 let isStore = 1, PPC970_Unit = 2 in {
399 def STBU8 : DForm_1<38, (ops ptr_rc:$ea_res, G8RC:$rS,
400 symbolLo:$ptroff, ptr_rc:$ptrreg),
401 "stbu $rS, $ptroff($ptrreg)", LdStGeneral,
402 [(set ptr_rc:$ea_res,
403 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg,
404 iaddroff:$ptroff))]>,
405 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
406 def STHU8 : DForm_1<45, (ops ptr_rc:$ea_res, G8RC:$rS,
407 symbolLo:$ptroff, ptr_rc:$ptrreg),
408 "sthu $rS, $ptroff($ptrreg)", LdStGeneral,
409 [(set ptr_rc:$ea_res,
410 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg,
411 iaddroff:$ptroff))]>,
412 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
413 def STWU8 : DForm_1<37, (ops ptr_rc:$ea_res, G8RC:$rS,
414 symbolLo:$ptroff, ptr_rc:$ptrreg),
415 "stwu $rS, $ptroff($ptrreg)", LdStGeneral,
416 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
417 iaddroff:$ptroff))]>,
418 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">;
421 def STDU : DSForm_1<62, 1, (ops ptr_rc:$ea_res, G8RC:$rS,
422 s16immX4:$ptroff, ptr_rc:$ptrreg),
423 "stdu $rS, $ptroff($ptrreg)", LdStSTD,
424 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg,
425 iaddroff:$ptroff))]>,
426 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">,
431 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
433 def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst),
434 "stdux $rS, $dst", LdStSTD,
438 // STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
439 def STD_32 : DSForm_1<62, 0, (ops GPRC:$rT, memrix:$dst),
440 "std $rT, $dst", LdStSTD,
441 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64;
442 def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
443 "stdx $rT, $dst", LdStSTD,
444 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64,
445 PPC970_DGroup_Cracked;
450 //===----------------------------------------------------------------------===//
451 // Floating point instructions.
455 let PPC970_Unit = 3 in { // FPU Operations.
456 def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
457 "fcfid $frD, $frB", FPGeneral,
458 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
459 def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
460 "fctidz $frD, $frB", FPGeneral,
461 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
465 //===----------------------------------------------------------------------===//
466 // Instruction Patterns
469 // Immediate support.
471 // sext(0x0000_0000_0000_FFFF, i8) -> li imm
472 // sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16
474 // sext(0x0000_0000_FFFF_FFFF, i16) -> lis + ori
475 def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
476 return N->getValue() == (uint64_t)(int32_t)N->getValue();
478 def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm),
479 (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>;
481 // zext(0x0000_0000_FFFF_7FFF, i16) -> oris (li lo16(imm)), imm>>16
482 def zext_0x0000_0000_FFFF_7FFF_i16 : PatLeaf<(imm), [{
483 return (N->getValue() & 0xFFFFFFFF00008000ULL) == 0;
485 def : Pat<(i64 zext_0x0000_0000_FFFF_7FFF_i16:$imm),
486 (ORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>;
488 // zext(0x0000_0000_FFFF_FFFF, i16) -> oris (ori (li 0), lo16(imm)), imm>>16
489 def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
490 return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0;
492 def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm),
493 (ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm))>;
495 // FIXME: Handle smart forms where the top 32-bits are set. Right now, stuff
496 // like 0xABCD0123BCDE0000 hits the case below, which produces ORI R, R, 0's!
498 // Fully general (and most expensive: 6 instructions!) immediate pattern.
499 def : Pat<(i64 imm:$imm),
504 (LIS8 (HI48_64 imm:$imm)),
511 // Extensions and truncates to/from 32-bit regs.
512 def : Pat<(i64 (zext GPRC:$in)),
513 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
514 def : Pat<(i64 (anyext GPRC:$in)),
515 (OR4To8 GPRC:$in, GPRC:$in)>;
516 def : Pat<(i32 (trunc G8RC:$in)),
517 (OR8To4 G8RC:$in, G8RC:$in)>;
519 // Extending loads with i64 targets.
520 def : Pat<(zextloadi1 iaddr:$src),
522 def : Pat<(zextloadi1 xaddr:$src),
524 def : Pat<(extloadi1 iaddr:$src),
526 def : Pat<(extloadi1 xaddr:$src),
528 def : Pat<(extloadi8 iaddr:$src),
530 def : Pat<(extloadi8 xaddr:$src),
532 def : Pat<(extloadi16 iaddr:$src),
534 def : Pat<(extloadi16 xaddr:$src),
536 def : Pat<(extloadi32 iaddr:$src),
538 def : Pat<(extloadi32 xaddr:$src),
542 def : Pat<(shl G8RC:$in, (i32 imm:$imm)),
543 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
544 def : Pat<(srl G8RC:$in, (i32 imm:$imm)),
545 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
547 // Hi and Lo for Darwin Global Addresses.
548 def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
549 def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>;
550 def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
551 def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>;
552 def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
553 def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>;
554 def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
555 (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
556 def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
557 (ADDIS8 G8RC:$in, tconstpool:$g)>;
558 def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
559 (ADDIS8 G8RC:$in, tjumptable:$g)>;